1651 files changed, 38127 insertions, 64350 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2f88d8d97701..431c3753145a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -16,6 +16,7 @@ config ARM
        select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
        select HAVE_ARCH_KGDB
        select HAVE_ARCH_TRACEHOOK
+        select HAVE_SYSCALL_TRACEPOINTS
        select HAVE_KPROBES if !XIP_KERNEL
        select HAVE_KRETPROBES if (HAVE_KPROBES)
        select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
@@ -24,6 +25,7 @@ config ARM
        select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
        select ARCH_BINFMT_ELF_RANDOMIZE_PIE
        select HAVE_GENERIC_DMA_COHERENT
+        select HAVE_DEBUG_KMEMLEAK
        select HAVE_KERNEL_GZIP
        select HAVE_KERNEL_LZO
        select HAVE_KERNEL_LZMA
@@ -38,6 +40,7 @@ config ARM
        select HARDIRQS_SW_RESEND
        select GENERIC_IRQ_PROBE
        select GENERIC_IRQ_SHOW
+        select HAVE_UID16
        select ARCH_WANT_IPC_PARSE_VERSION
        select HARDIRQS_SW_RESEND
        select CPU_PM if (SUSPEND || CPU_IDLE)
@@ -49,6 +52,8 @@ config ARM
        select GENERIC_STRNCPY_FROM_USER
        select GENERIC_STRNLEN_USER
        select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
+        select GENERIC_KERNEL_THREAD
+        select GENERIC_KERNEL_EXECVE
        help
          The ARM series is a line of low-power-consumption RISC chip designs
          licensed by ARM Ltd and targeted at embedded applications and
@@ -202,6 +207,13 @@ config ARM_PATCH_PHYS_VIRT
          this feature (eg, building a kernel for a single machine) and
          you need to shrink the kernel to the minimal size.
+config NEED_MACH_GPIO_H
+        bool
+        help
+          Select this when mach/gpio.h is required to provide special
+          definitions for this platform. The need for mach/gpio.h should
+          be avoided when possible.
 config NEED_MACH_IO_H
        bool
        help
@@ -247,39 +259,29 @@ config MMU
 #
 choice
        prompt "ARM system type"
-        default ARCH_VERSATILE
+        default ARCH_MULTIPLATFORM
-config ARCH_SOCFPGA
+config ARCH_MULTIPLATFORM
-        bool "Altera SOCFPGA family"
+        bool "Allow multiple platforms to be selected"
-        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_PATCH_PHYS_VIRT
-        select ARM_AMBA
+        select AUTO_ZRELADDR
-        select ARM_GIC
-        select CACHE_L2X0
-        select CLKDEV_LOOKUP
        select COMMON_CLK
-        select CPU_V7
+        select MULTI_IRQ_HANDLER
-        select DW_APB_TIMER
-        select DW_APB_TIMER_OF
-        select GENERIC_CLOCKEVENTS
-        select GPIO_PL061 if GPIOLIB
-        select HAVE_ARM_SCU
        select SPARSE_IRQ
        select USE_OF
-        help
+        depends on MMU
-          This enables support for Altera SOCFPGA Cyclone V platform
 config ARCH_INTEGRATOR
        bool "ARM Ltd. Integrator family"
        select ARM_AMBA
        select ARCH_HAS_CPUFREQ
        select COMMON_CLK
-        select CLK_VERSATILE
+        select COMMON_CLK_VERSATILE
        select HAVE_TCM
        select ICST
        select GENERIC_CLOCKEVENTS
        select PLAT_VERSATILE
        select PLAT_VERSATILE_FPGA_IRQ
-        select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
        select SPARSE_IRQ
        select MULTI_IRQ_HANDLER
@@ -289,13 +291,12 @@ config ARCH_INTEGRATOR
 config ARCH_REALVIEW
        bool "ARM Ltd. RealView family"
        select ARM_AMBA
-        select CLKDEV_LOOKUP
+        select COMMON_CLK
-        select HAVE_MACH_CLKDEV
+        select COMMON_CLK_VERSATILE
        select ICST
        select GENERIC_CLOCKEVENTS
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select PLAT_VERSATILE
-        select PLAT_VERSATILE_CLOCK
        select PLAT_VERSATILE_CLCD
        select ARM_TIMER_SP804
        select GPIO_PL061 if GPIOLIB
@@ -312,7 +313,6 @@ config ARCH_VERSATILE
        select ICST
        select GENERIC_CLOCKEVENTS
        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select NEED_MACH_IO_H if PCI
        select PLAT_VERSATILE
        select PLAT_VERSATILE_CLOCK
        select PLAT_VERSATILE_CLCD
@@ -321,69 +321,41 @@ config ARCH_VERSATILE
        help
          This enables support for ARM Ltd Versatile board.
-config ARCH_VEXPRESS
-        bool "ARM Ltd. Versatile Express family"
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select ARM_AMBA
-        select ARM_TIMER_SP804
-        select CLKDEV_LOOKUP
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
-        select HAVE_PATA_PLATFORM
-        select ICST
-        select NO_IOPORT
-        select PLAT_VERSATILE
-        select PLAT_VERSATILE_CLCD
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-        help
-          This enables support for the ARM Ltd Versatile Express boards.
 config ARCH_AT91
        bool "Atmel AT91"
        select ARCH_REQUIRE_GPIOLIB
        select HAVE_CLK
        select CLKDEV_LOOKUP
        select IRQ_DOMAIN
+        select NEED_MACH_GPIO_H
        select NEED_MACH_IO_H if PCCARD
        help
          This enables support for systems based on Atmel
          AT91RM9200 and AT91SAM9* processors.
-config ARCH_BCMRING
+config ARCH_BCM2835
-        bool "Broadcom BCMRING"
+        bool "Broadcom BCM2835 family"
-        depends on MMU
-        select CPU_V6
-        select ARM_AMBA
-        select ARM_TIMER_SP804
-        select CLKDEV_LOOKUP
-        select GENERIC_CLOCKEVENTS
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        help
-          Support for Broadcom's BCMRing platform.
-config ARCH_HIGHBANK
-        bool "Calxeda Highbank-based"
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARM_AMBA
-        select ARM_GIC
+        select ARM_ERRATA_411920
        select ARM_TIMER_SP804
-        select CACHE_L2X0
        select CLKDEV_LOOKUP
        select COMMON_CLK
-        select CPU_V7
+        select CPU_V6
        select GENERIC_CLOCKEVENTS
-        select HAVE_ARM_SCU
+        select MULTI_IRQ_HANDLER
-        select HAVE_SMP
        select SPARSE_IRQ
        select USE_OF
        help
-          Support for the Calxeda Highbank SoC based boards.
+          This enables support for the Broadcom BCM2835 SoC. This SoC is
+          use in the Raspberry Pi, and Roku 2 devices.
 config ARCH_CLPS711X
        bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
        select CPU_ARM720T
        select ARCH_USES_GETTIMEOFFSET
+        select COMMON_CLK
+        select CLKDEV_LOOKUP
        select NEED_MACH_MEMORY_H
        help
          Support for Cirrus Logic 711x/721x/731x based boards.
@@ -407,21 +379,19 @@ config ARCH_GEMINI
        help
          Support for the Cortina Systems Gemini family SoCs
-config ARCH_PRIMA2
+config ARCH_SIRF
-        bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
+        bool "CSR SiRF"
-        select CPU_V7
        select NO_IOPORT
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
-        select CLKDEV_LOOKUP
+        select COMMON_CLK
        select GENERIC_IRQ_CHIP
        select MIGHT_HAVE_CACHE_L2X0
        select PINCTRL
        select PINCTRL_SIRF
        select USE_OF
-        select ZONE_DMA
        help
-          Support for CSR SiRFSoC ARM Cortex A9 Platform
+          Support for CSR SiRFprimaII/Marco/Polo platforms
 config ARCH_EBSA110
        bool "EBSA-110"
@@ -456,7 +426,7 @@ config ARCH_FOOTBRIDGE
        select FOOTBRIDGE
        select GENERIC_CLOCKEVENTS
        select HAVE_IDE
-        select NEED_MACH_IO_H
+        select NEED_MACH_IO_H if !MMU
        select NEED_MACH_MEMORY_H
        help
          Support for systems based on the DC21285 companion chip
@@ -483,7 +453,9 @@ config ARCH_MXS
        select CLKSRC_MMIO
        select COMMON_CLK
        select HAVE_CLK_PREPARE
+        select MULTI_IRQ_HANDLER
        select PINCTRL
+        select SPARSE_IRQ
        select USE_OF
        help
          Support for Freescale MXS-based family of processors
@@ -513,7 +485,6 @@ config ARCH_IOP13XX
        select PCI
        select ARCH_SUPPORTS_MSI
        select VMSPLIT_1G
-        select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
        select NEED_RET_TO_USER
        help
@@ -523,7 +494,7 @@ config ARCH_IOP32X
        bool "IOP32x-based"
        depends on MMU
        select CPU_XSCALE
-        select NEED_MACH_IO_H
+        select NEED_MACH_GPIO_H
        select NEED_RET_TO_USER
        select PLAT_IOP
        select PCI
@@ -536,7 +507,7 @@ config ARCH_IOP33X
        bool "IOP33x-based"
        depends on MMU
        select CPU_XSCALE
-        select NEED_MACH_IO_H
+        select NEED_MACH_GPIO_H
        select NEED_RET_TO_USER
        select PLAT_IOP
        select PCI
@@ -558,26 +529,14 @@ config ARCH_IXP4XX
        help
          Support for Intel's IXP4XX (XScale) family of processors.
-config ARCH_MVEBU
-        bool "Marvell SOCs with Device Tree support"
-        select GENERIC_CLOCKEVENTS
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
-        select CLKSRC_MMIO
-        select GENERIC_IRQ_CHIP
-        select IRQ_DOMAIN
-        select COMMON_CLK
-        help
-          Support for the Marvell SoC Family with device tree support
 config ARCH_DOVE
        bool "Marvell Dove"
        select CPU_V7
-        select PCI
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
-        select NEED_MACH_IO_H
+        select MIGHT_HAVE_PCI
-        select PLAT_ORION
+        select PLAT_ORION_LEGACY
+        select USB_ARCH_HAS_EHCI
        help
          Support for the Marvell Dove SoC 88AP510
@@ -587,8 +546,7 @@ config ARCH_KIRKWOOD
        select PCI
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
-        select NEED_MACH_IO_H
+        select PLAT_ORION_LEGACY
-        select PLAT_ORION
        help
          Support for the following Marvell Kirkwood series SoCs:
          88F6180, 88F6192 and 88F6281.
@@ -614,8 +572,7 @@ config ARCH_MV78XX0
        select PCI
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
-        select NEED_MACH_IO_H
+        select PLAT_ORION_LEGACY
-        select PLAT_ORION
        help
          Support for the following Marvell MV78xx0 series SoCs:
          MV781x0, MV782x0.
@@ -627,8 +584,7 @@ config ARCH_ORION5X
        select PCI
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
-        select NEED_MACH_IO_H
+        select PLAT_ORION_LEGACY
-        select PLAT_ORION
        help
          Support for the following Marvell Orion 5x series SoCs:
          Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
@@ -645,6 +601,7 @@ config ARCH_MMP
        select PLAT_PXA
        select SPARSE_IRQ
        select GENERIC_ALLOCATOR
+        select NEED_MACH_GPIO_H
        help
          Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
@@ -652,8 +609,9 @@ config ARCH_KS8695
        bool "Micrel/Kendin KS8695"
        select CPU_ARM922T
        select ARCH_REQUIRE_GPIOLIB
-        select ARCH_USES_GETTIMEOFFSET
        select NEED_MACH_MEMORY_H
+        select CLKSRC_MMIO
+        select GENERIC_CLOCKEVENTS
        help
          Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
          System-on-Chip devices.
@@ -683,40 +641,13 @@ config ARCH_TEGRA
        select HAVE_CLK
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
-        select NEED_MACH_IO_H if PCI
        select ARCH_HAS_CPUFREQ
        select USE_OF
+        select COMMON_CLK
        help
          This enables support for NVIDIA Tegra based systems (Tegra APX,
          Tegra 6xx and Tegra 2 series).
-config ARCH_PICOXCELL
-        bool "Picochip picoXcell"
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_PATCH_PHYS_VIRT
-        select ARM_VIC
-        select CPU_V6K
-        select DW_APB_TIMER
-        select DW_APB_TIMER_OF
-        select GENERIC_CLOCKEVENTS
-        select GENERIC_GPIO
-        select HAVE_TCM
-        select NO_IOPORT
-        select SPARSE_IRQ
-        select USE_OF
-        help
-          This enables support for systems based on the Picochip picoXcell
-          family of Femtocell devices.  The picoxcell support requires device tree
-          for all boards.
-config ARCH_PNX4008
-        bool "Philips Nexperia PNX4008 Mobile"
-        select CPU_ARM926T
-        select CLKDEV_LOOKUP
-        select ARCH_USES_GETTIMEOFFSET
-        help
-          This enables support for Philips PNX4008 mobile platform.
 config ARCH_PXA
        bool "PXA2xx/PXA3xx-based"
        depends on MMU
@@ -733,6 +664,7 @@ config ARCH_PXA
        select MULTI_IRQ_HANDLER
        select ARM_CPU_SUSPEND if PM
        select HAVE_IDE
+        select NEED_MACH_GPIO_H
        help
          Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
@@ -795,6 +727,7 @@ config ARCH_SA1100
        select CLKDEV_LOOKUP
        select ARCH_REQUIRE_GPIOLIB
        select HAVE_IDE
+        select NEED_MACH_GPIO_H
        select NEED_MACH_MEMORY_H
        select SPARSE_IRQ
        help
@@ -810,6 +743,7 @@ config ARCH_S3C24XX
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C_RTC if RTC_CLASS
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
+        select NEED_MACH_GPIO_H
        select NEED_MACH_IO_H
        help
          Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
@@ -837,6 +771,7 @@ config ARCH_S3C64XX
        select SAMSUNG_GPIOLIB_4BIT
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
+        select NEED_MACH_GPIO_H
        help
          Samsung S3C64XX series based systems
@@ -851,6 +786,7 @@ config ARCH_S5P64X0
        select GENERIC_CLOCKEVENTS
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C_RTC if RTC_CLASS
+        select NEED_MACH_GPIO_H
        help
          Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
          SMDK6450.
@@ -865,6 +801,7 @@ config ARCH_S5PC100
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C_RTC if RTC_CLASS
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
+        select NEED_MACH_GPIO_H
        help
          Samsung S5PC100 series based systems
@@ -882,6 +819,7 @@ config ARCH_S5PV210
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C_RTC if RTC_CLASS
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
+        select NEED_MACH_GPIO_H
        select NEED_MACH_MEMORY_H
        help
          Samsung S5PV210/S5PC110 series based systems
@@ -899,6 +837,7 @@ config ARCH_EXYNOS
        select HAVE_S3C_RTC if RTC_CLASS
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
+        select NEED_MACH_GPIO_H
        select NEED_MACH_MEMORY_H
        help
          Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
@@ -912,7 +851,6 @@ config ARCH_SHARK
        select PCI
        select ARCH_USES_GETTIMEOFFSET
        select NEED_MACH_MEMORY_H
-        select NEED_MACH_IO_H
        help
          Support for the StrongARM based Digital DNARD machine, also known
          as "Shark" (<http://www.shark-linux.de/shark.html>).
@@ -931,6 +869,7 @@ config ARCH_U300
        select COMMON_CLK
        select GENERIC_GPIO
        select ARCH_REQUIRE_GPIOLIB
+        select SPARSE_IRQ
        help
          Support for ST-Ericsson U300 series mobile platforms.
@@ -956,6 +895,7 @@ config ARCH_NOMADIK
        select COMMON_CLK
        select GENERIC_CLOCKEVENTS
        select PINCTRL
+        select PINCTRL_STN8815
        select MIGHT_HAVE_CACHE_L2X0
        select ARCH_REQUIRE_GPIOLIB
        help
@@ -971,6 +911,7 @@ config ARCH_DAVINCI
        select GENERIC_ALLOCATOR
        select GENERIC_IRQ_CHIP
        select ARCH_HAS_HOLES_MEMORYMODEL
+        select NEED_MACH_GPIO_H
        help
          Support for TI's DaVinci platform.
@@ -983,6 +924,7 @@ config ARCH_OMAP
        select CLKSRC_MMIO
        select GENERIC_CLOCKEVENTS
        select ARCH_HAS_HOLES_MEMORYMODEL
+        select NEED_MACH_GPIO_H
        help
          Support for TI's OMAP platform (OMAP1/2/3/4).
@@ -1005,6 +947,10 @@ config ARCH_VT8500
        select ARCH_HAS_CPUFREQ
        select GENERIC_CLOCKEVENTS
        select ARCH_REQUIRE_GPIOLIB
+        select USE_OF
+        select COMMON_CLK
+        select HAVE_CLK
+        select CLKDEV_LOOKUP
        help
          Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
@@ -1022,6 +968,50 @@ config ARCH_ZYNQ
          Support for Xilinx Zynq ARM Cortex A9 Platform
 endchoice
+menu "Multiple platform selection"
+        depends on ARCH_MULTIPLATFORM
+comment "CPU Core family selection"
+config ARCH_MULTI_V4
+        bool "ARMv4 based platforms (FA526, StrongARM)"
+        select ARCH_MULTI_V4_V5
+        depends on !ARCH_MULTI_V6_V7
+config ARCH_MULTI_V4T
+        bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
+        select ARCH_MULTI_V4_V5
+        depends on !ARCH_MULTI_V6_V7
+config ARCH_MULTI_V5
+        bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
+        select ARCH_MULTI_V4_V5
+        depends on !ARCH_MULTI_V6_V7
+config ARCH_MULTI_V4_V5
+        bool
+config ARCH_MULTI_V6
+        bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
+        select CPU_V6
+        select ARCH_MULTI_V6_V7
+config ARCH_MULTI_V7
+        bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
+        select CPU_V7
+        select ARCH_VEXPRESS
+        default y
+        select ARCH_MULTI_V6_V7
+config ARCH_MULTI_V6_V7
+        bool
+config ARCH_MULTI_CPU_AUTO
+        def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
+        select ARCH_MULTI_V5
+endmenu
 #
 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 # Kconfigs may be included either alphabetically (according to the
@@ -1031,8 +1021,6 @@ source "arch/arm/mach-mvebu/Kconfig"
 source "arch/arm/mach-at91/Kconfig"
-source "arch/arm/mach-bcmring/Kconfig"
 source "arch/arm/mach-clps711x/Kconfig"
 source "arch/arm/mach-cns3xxx/Kconfig"
@@ -1049,6 +1037,8 @@ source "arch/arm/mach-gemini/Kconfig"
 source "arch/arm/mach-h720x/Kconfig"
+source "arch/arm/mach-highbank/Kconfig"
 source "arch/arm/mach-integrator/Kconfig"
 source "arch/arm/mach-iop32x/Kconfig"
@@ -1084,6 +1074,8 @@ source "arch/arm/mach-omap2/Kconfig"
 source "arch/arm/mach-orion5x/Kconfig"
+source "arch/arm/mach-picoxcell/Kconfig"
 source "arch/arm/mach-pxa/Kconfig"
 source "arch/arm/plat-pxa/Kconfig"
@@ -1096,6 +1088,8 @@ source "arch/arm/mach-sa1100/Kconfig"
 source "arch/arm/plat-samsung/Kconfig"
 source "arch/arm/plat-s3c24xx/Kconfig"
+source "arch/arm/mach-socfpga/Kconfig"
 source "arch/arm/plat-spear/Kconfig"
 source "arch/arm/mach-s3c24xx/Kconfig"
@@ -1118,6 +1112,8 @@ source "arch/arm/mach-exynos/Kconfig"
 source "arch/arm/mach-shmobile/Kconfig"
+source "arch/arm/mach-prima2/Kconfig"
 source "arch/arm/mach-tegra/Kconfig"
 source "arch/arm/mach-u300/Kconfig"
@@ -1129,8 +1125,6 @@ source "arch/arm/mach-versatile/Kconfig"
 source "arch/arm/mach-vexpress/Kconfig"
 source "arch/arm/plat-versatile/Kconfig"
-source "arch/arm/mach-vt8500/Kconfig"
 source "arch/arm/mach-w90x900/Kconfig"
 # Definitions to make life easier
@@ -1148,6 +1142,10 @@ config PLAT_ORION
        select IRQ_DOMAIN
        select COMMON_CLK
+config PLAT_ORION_LEGACY
+        bool
+        select PLAT_ORION
 config PLAT_PXA
        bool
@@ -1179,12 +1177,6 @@ config XSCALE_PMU
        depends on CPU_XSCALE
        default y
-config CPU_HAS_PMU
-        depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
-                   (!ARCH_OMAP3 || OMAP3_EMU)
-        default y
-        bool
 config MULTI_IRQ_HANDLER
        bool
        help
@@ -1413,6 +1405,16 @@ config PL310_ERRATA_769419
          on systems with an outer cache, the store buffer is drained
          explicitly.
+config ARM_ERRATA_775420
+       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 775420 Cortex-A9 (r2p2,
+         r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
+         operation aborts with MMU exception, it might cause the processor
+         to deadlock. This workaround puts DSB before executing ISB if
+         an abort may occur on cache maintenance.
 endmenu
 source "arch/arm/common/Kconfig"
@@ -1623,6 +1625,7 @@ config ARCH_NR_GPIO
        default 355 if ARCH_U8500
        default 264 if MACH_H4700
        default 512 if SOC_OMAP5
+        default 288 if ARCH_VT8500
        default 0
        help
          Maximum number of GPIOs in the system.
@@ -1757,7 +1760,7 @@ config HIGHPTE
 config HW_PERF_EVENTS
        bool "Enable hardware performance counter support for perf events"
-        depends on PERF_EVENTS && CPU_HAS_PMU
+        depends on PERF_EVENTS
        default y
        help
          Enable hardware performance counter support for perf events. If
@@ -1768,6 +1771,7 @@ source "mm/Kconfig"
 config FORCE_MAX_ZONEORDER
        int "Maximum zone order" if ARCH_SHMOBILE
        range 11 64 if ARCH_SHMOBILE
+        default "12" if SOC_AM33XX
        default "9" if SA1111
        default "11"
        help
@@ -1781,59 +1785,6 @@ config FORCE_MAX_ZONEORDER
          This config option is actually maximum order plus one. For example,
          a value of 11 means that the largest free memory block is 2^10 pages.
-config LEDS
-        bool "Timer and CPU usage LEDs"
-        depends on ARCH_CDB89712 || ARCH_EBSA110 || \
-                   ARCH_EBSA285 || ARCH_INTEGRATOR || \
-                   ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
-                   ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
-                   ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
-                   ARCH_AT91 || ARCH_DAVINCI || \
-                   ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
-        help
-          If you say Y here, the LEDs on your machine will be used
-          to provide useful information about your current system status.
-          If you are compiling a kernel for a NetWinder or EBSA-285, you will
-          be able to select which LEDs are active using the options below. If
-          you are compiling a kernel for the EBSA-110 or the LART however, the
-          red LED will simply flash regularly to indicate that the system is
-          still functional. It is safe to say Y here if you have a CATS
-          system, but the driver will do nothing.
-config LEDS_TIMER
-        bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
-                            OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
-                            || MACH_OMAP_PERSEUS2
-        depends on LEDS
-        depends on !GENERIC_CLOCKEVENTS
-        default y if ARCH_EBSA110
-        help
-          If you say Y here, one of the system LEDs (the green one on the
-          NetWinder, the amber one on the EBSA285, or the red one on the LART)
-          will flash regularly to indicate that the system is still
-          operational. This is mainly useful to kernel hackers who are
-          debugging unstable kernels.
-          The LART uses the same LED for both Timer LED and CPU usage LED
-          functions. You may choose to use both, but the Timer LED function
-          will overrule the CPU usage LED.
-config LEDS_CPU
-        bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
-                        !ARCH_OMAP) \
-                        || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
-                        || MACH_OMAP_PERSEUS2
-        depends on LEDS
-        help
-          If you say Y here, the red LED will be used to give a good real
-          time indication of CPU usage, by lighting whenever the idle task
-          is not currently executing.
-          The LART uses the same LED for both Timer LED and CPU usage LED
-          functions. You may choose to use both, but the Timer LED function
-          will overrule the CPU usage LED.
 config ALIGNMENT_TRAP
        bool
        depends on CPU_CP15_MMU
@@ -1849,8 +1800,8 @@ config ALIGNMENT_TRAP
          configuration it is safe to say N, otherwise say Y.
 config UACCESS_WITH_MEMCPY
-        bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
+        bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
-        depends on MMU && EXPERIMENTAL
+        depends on MMU
        default y if CPU_FEROCEON
        help
          Implement faster copy_to_user and clear_user methods for CPU
@@ -1891,11 +1842,15 @@ config CC_STACKPROTECTOR
          neutralized via a kernel panic.
          This feature requires gcc version 4.2 or above.
-config DEPRECATED_PARAM_STRUCT
+config XEN_DOM0
-        bool "Provide old way to pass kernel parameters"
+        def_bool y
+        depends on XEN
+config XEN
+        bool "Xen guest support on ARM (EXPERIMENTAL)"
+        depends on EXPERIMENTAL && ARM && OF
        help
-          This was deprecated in 2001 and announced to live on for 5 years.
+          Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
-          Some old boot loaders still use this way.
 endmenu
@@ -1909,6 +1864,23 @@ config USE_OF
        help
          Include support for flattened device tree machine descriptions.
+config ATAGS
+        bool "Support for the traditional ATAGS boot data passing" if USE_OF
+        default y
+        help
+          This is the traditional way of passing data to the kernel at boot
+          time. If you are solely relying on the flattened device tree (or
+          the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
+          to remove ATAGS support from your kernel binary.  If unsure,
+          leave this to y.
+config DEPRECATED_PARAM_STRUCT
+        bool "Provide old way to pass kernel parameters"
+        depends on ATAGS
+        help
+          This was deprecated in 2001 and announced to live on for 5 years.
+          Some old boot loaders still use this way.
 # Compressed boot loader in ROM.  Yes, we really want to ask about
 # TEXT and BSS so we preserve their values in the config files.
 config ZBOOT_ROM_TEXT
@@ -2035,6 +2007,7 @@ config CMDLINE
 choice
        prompt "Kernel command line type" if CMDLINE != ""
        default CMDLINE_FROM_BOOTLOADER
+        depends on ATAGS
 config CMDLINE_FROM_BOOTLOADER
        bool "Use bootloader kernel arguments if available"
@@ -2060,7 +2033,7 @@ endchoice
 config XIP_KERNEL
        bool "Kernel Execute-In-Place from ROM"
-        depends on !ZBOOT_ROM && !ARM_LPAE
+        depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
        help
          Execute-In-Place allows the kernel to run from non-volatile storage
          directly addressable by the CPU, such as NOR flash. This saves RAM
@@ -2104,7 +2077,7 @@ config KEXEC
 config ATAGS_PROC
        bool "Export atags in procfs"
-        depends on KEXEC
+        depends on ATAGS && KEXEC
        default y
        help
          Should the atags used to boot the kernel be exported in an "atags"
@@ -2313,7 +2286,7 @@ menu "Power management options"
 source "kernel/power/Kconfig"
 config ARCH_SUSPEND_POSSIBLE
-        depends on !ARCH_S5PC100 && !ARCH_TEGRA
+        depends on !ARCH_S5PC100
        depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
                CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
        def_bool y
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index e968a52e4881..b0f3857b3a4c 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -224,6 +224,20 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on i.MX6Q UART4.
+        config DEBUG_MMP_UART2
+                bool "Kernel low-level debugging message via MMP UART2"
+                depends on ARCH_MMP
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on MMP UART2.
+        config DEBUG_MMP_UART3
+                bool "Kernel low-level debugging message via MMP UART3"
+                depends on ARCH_MMP
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on MMP UART3.
        config DEBUG_MSM_UART1
                bool "Kernel low-level debugging messages via MSM UART1"
                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
@@ -261,6 +275,20 @@ choice
                  Say Y here if you want the debug print routines to direct
                  their output to the serial port on MSM 8960 devices.
+        config DEBUG_MVEBU_UART
+                bool "Kernel low-level debugging messages via MVEBU UART"
+                depends on ARCH_MVEBU
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on MVEBU based platforms.
+        config DEBUG_PICOXCELL_UART
+                depends on ARCH_PICOXCELL
+                bool "Use PicoXcell UART for low-level debug"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on PicoXcell based platforms.
        config DEBUG_REALVIEW_STD_PORT
                bool "RealView Default UART"
                depends on ARCH_REALVIEW
@@ -310,6 +338,13 @@ choice
                  The uncompressor code port configuration is now handled
                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+        config DEBUG_SOCFPGA_UART
+                depends on ARCH_SOCFPGA
+                bool "Use SOCFPGA UART for low-level debug"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on SOCFPGA based platforms.
        config DEBUG_VEXPRESS_UART0_DETECT
                bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
                depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -338,6 +373,7 @@ choice
        config DEBUG_LL_UART_NONE
                bool "No low-level debugging UART"
+                depends on !ARCH_MULTIPLATFORM
                help
                  Say Y here if your platform doesn't provide a UART option
                  below. This relies on your platform choosing the right UART
@@ -373,6 +409,17 @@ choice
 endchoice
+config DEBUG_LL_INCLUDE
+        string
+        default "debug/icedcc.S" if DEBUG_ICEDCC
+        default "debug/highbank.S" if DEBUG_HIGHBANK_UART
+        default "debug/mvebu.S" if DEBUG_MVEBU_UART
+        default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
+        default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
+        default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
+                DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
+        default "mach/debug-macro.S"
 config EARLY_PRINTK
        bool "Early printk"
        depends on DEBUG_LL
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a051dfbdd7db..f023e3acdfbd 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -135,84 +135,78 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-machine-$(CONFIG_ARCH_AT91)             := at91
+machine-$(CONFIG_ARCH_AT91)             += at91
-machine-$(CONFIG_ARCH_BCMRING)          := bcmring
+machine-$(CONFIG_ARCH_BCM2835)          += bcm2835
-machine-$(CONFIG_ARCH_CLPS711X)         := clps711x
+machine-$(CONFIG_ARCH_CLPS711X)         += clps711x
-machine-$(CONFIG_ARCH_CNS3XXX)          := cns3xxx
+machine-$(CONFIG_ARCH_CNS3XXX)          += cns3xxx
-machine-$(CONFIG_ARCH_DAVINCI)          := davinci
+machine-$(CONFIG_ARCH_DAVINCI)          += davinci
-machine-$(CONFIG_ARCH_DOVE)             := dove
+machine-$(CONFIG_ARCH_DOVE)             += dove
-machine-$(CONFIG_ARCH_EBSA110)          := ebsa110
+machine-$(CONFIG_ARCH_EBSA110)          += ebsa110
-machine-$(CONFIG_ARCH_EP93XX)           := ep93xx
+machine-$(CONFIG_ARCH_EP93XX)           += ep93xx
-machine-$(CONFIG_ARCH_GEMINI)           := gemini
+machine-$(CONFIG_ARCH_GEMINI)           += gemini
-machine-$(CONFIG_ARCH_H720X)            := h720x
+machine-$(CONFIG_ARCH_H720X)            += h720x
-machine-$(CONFIG_ARCH_HIGHBANK)         := highbank
+machine-$(CONFIG_ARCH_HIGHBANK)         += highbank
-machine-$(CONFIG_ARCH_INTEGRATOR)       := integrator
+machine-$(CONFIG_ARCH_INTEGRATOR)       += integrator
-machine-$(CONFIG_ARCH_IOP13XX)          := iop13xx
+machine-$(CONFIG_ARCH_IOP13XX)          += iop13xx
-machine-$(CONFIG_ARCH_IOP32X)           := iop32x
+machine-$(CONFIG_ARCH_IOP32X)           += iop32x
-machine-$(CONFIG_ARCH_IOP33X)           := iop33x
+machine-$(CONFIG_ARCH_IOP33X)           += iop33x
-machine-$(CONFIG_ARCH_IXP4XX)           := ixp4xx
+machine-$(CONFIG_ARCH_IXP4XX)           += ixp4xx
-machine-$(CONFIG_ARCH_KIRKWOOD)         := kirkwood
+machine-$(CONFIG_ARCH_KIRKWOOD)         += kirkwood
-machine-$(CONFIG_ARCH_KS8695)           := ks8695
+machine-$(CONFIG_ARCH_KS8695)           += ks8695
-machine-$(CONFIG_ARCH_LPC32XX)          := lpc32xx
+machine-$(CONFIG_ARCH_LPC32XX)          += lpc32xx
-machine-$(CONFIG_ARCH_MMP)              := mmp
+machine-$(CONFIG_ARCH_MMP)              += mmp
-machine-$(CONFIG_ARCH_MSM)              := msm
+machine-$(CONFIG_ARCH_MSM)              += msm
-machine-$(CONFIG_ARCH_MV78XX0)          := mv78xx0
+machine-$(CONFIG_ARCH_MV78XX0)          += mv78xx0
-machine-$(CONFIG_ARCH_IMX_V4_V5)        := imx
+machine-$(CONFIG_ARCH_MXC)              += imx
-machine-$(CONFIG_ARCH_IMX_V6_V7)        := imx
+machine-$(CONFIG_ARCH_MXS)              += mxs
-machine-$(CONFIG_ARCH_MXS)              := mxs
+machine-$(CONFIG_ARCH_MVEBU)            += mvebu
-machine-$(CONFIG_ARCH_MVEBU)            := mvebu
+machine-$(CONFIG_ARCH_NETX)             += netx
-machine-$(CONFIG_ARCH_NETX)             := netx
+machine-$(CONFIG_ARCH_NOMADIK)          += nomadik
-machine-$(CONFIG_ARCH_NOMADIK)          := nomadik
+machine-$(CONFIG_ARCH_OMAP1)            += omap1
-machine-$(CONFIG_ARCH_OMAP1)            := omap1
+machine-$(CONFIG_ARCH_OMAP2PLUS)        += omap2
-machine-$(CONFIG_ARCH_OMAP2PLUS)        := omap2
+machine-$(CONFIG_ARCH_ORION5X)          += orion5x
-machine-$(CONFIG_ARCH_ORION5X)          := orion5x
+machine-$(CONFIG_ARCH_PICOXCELL)        += picoxcell
-machine-$(CONFIG_ARCH_PICOXCELL)        := picoxcell
+machine-$(CONFIG_ARCH_PRIMA2)           += prima2
-machine-$(CONFIG_ARCH_PNX4008)          := pnx4008
+machine-$(CONFIG_ARCH_PXA)              += pxa
-machine-$(CONFIG_ARCH_PRIMA2)           := prima2
+machine-$(CONFIG_ARCH_REALVIEW)         += realview
-machine-$(CONFIG_ARCH_PXA)              := pxa
+machine-$(CONFIG_ARCH_RPC)              += rpc
-machine-$(CONFIG_ARCH_REALVIEW)         := realview
+machine-$(CONFIG_ARCH_S3C24XX)          += s3c24xx s3c2412 s3c2440
-machine-$(CONFIG_ARCH_RPC)              := rpc
+machine-$(CONFIG_ARCH_S3C64XX)          += s3c64xx
-machine-$(CONFIG_ARCH_S3C24XX)          := s3c24xx s3c2412 s3c2440
+machine-$(CONFIG_ARCH_S5P64X0)          += s5p64x0
-machine-$(CONFIG_ARCH_S3C64XX)          := s3c64xx
+machine-$(CONFIG_ARCH_S5PC100)          += s5pc100
-machine-$(CONFIG_ARCH_S5P64X0)          := s5p64x0
+machine-$(CONFIG_ARCH_S5PV210)          += s5pv210
-machine-$(CONFIG_ARCH_S5PC100)          := s5pc100
+machine-$(CONFIG_ARCH_EXYNOS)           += exynos
-machine-$(CONFIG_ARCH_S5PV210)          := s5pv210
+machine-$(CONFIG_ARCH_SA1100)           += sa1100
-machine-$(CONFIG_ARCH_EXYNOS4)          := exynos
+machine-$(CONFIG_ARCH_SHARK)            += shark
-machine-$(CONFIG_ARCH_EXYNOS5)          := exynos
+machine-$(CONFIG_ARCH_SHMOBILE)         += shmobile
-machine-$(CONFIG_ARCH_SA1100)           := sa1100
+machine-$(CONFIG_ARCH_TEGRA)            += tegra
-machine-$(CONFIG_ARCH_SHARK)            := shark
+machine-$(CONFIG_ARCH_U300)             += u300
-machine-$(CONFIG_ARCH_SHMOBILE)         := shmobile
+machine-$(CONFIG_ARCH_U8500)            += ux500
-machine-$(CONFIG_ARCH_TEGRA)            := tegra
+machine-$(CONFIG_ARCH_VERSATILE)        += versatile
-machine-$(CONFIG_ARCH_U300)             := u300
+machine-$(CONFIG_ARCH_VEXPRESS)         += vexpress
-machine-$(CONFIG_ARCH_U8500)            := ux500
+machine-$(CONFIG_ARCH_VT8500)           += vt8500
-machine-$(CONFIG_ARCH_VERSATILE)        := versatile
+machine-$(CONFIG_ARCH_W90X900)          += w90x900
-machine-$(CONFIG_ARCH_VEXPRESS)         := vexpress
+machine-$(CONFIG_FOOTBRIDGE)            += footbridge
-machine-$(CONFIG_ARCH_VT8500)           := vt8500
+machine-$(CONFIG_ARCH_SOCFPGA)          += socfpga
-machine-$(CONFIG_ARCH_W90X900)          := w90x900
+machine-$(CONFIG_ARCH_SPEAR13XX)        += spear13xx
-machine-$(CONFIG_FOOTBRIDGE)            := footbridge
+machine-$(CONFIG_ARCH_SPEAR3XX)         += spear3xx
-machine-$(CONFIG_ARCH_SOCFPGA)          := socfpga
+machine-$(CONFIG_MACH_SPEAR600)         += spear6xx
-machine-$(CONFIG_MACH_SPEAR1310)        := spear13xx
+machine-$(CONFIG_ARCH_ZYNQ)             += zynq
-machine-$(CONFIG_MACH_SPEAR1340)        := spear13xx
-machine-$(CONFIG_MACH_SPEAR300)         := spear3xx
-machine-$(CONFIG_MACH_SPEAR310)         := spear3xx
-machine-$(CONFIG_MACH_SPEAR320)         := spear3xx
-machine-$(CONFIG_MACH_SPEAR600)         := spear6xx
-machine-$(CONFIG_ARCH_ZYNQ)             := zynq
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-plat-$(CONFIG_ARCH_MXC)         := mxc
+plat-$(CONFIG_ARCH_MXC)         += mxc
-plat-$(CONFIG_ARCH_OMAP)        := omap
+plat-$(CONFIG_ARCH_OMAP)        += omap
-plat-$(CONFIG_ARCH_S3C64XX)     := samsung
+plat-$(CONFIG_ARCH_S3C64XX)     += samsung
-plat-$(CONFIG_ARCH_ZYNQ)        := versatile
+plat-$(CONFIG_ARCH_ZYNQ)        += versatile
-plat-$(CONFIG_PLAT_IOP)         := iop
+plat-$(CONFIG_PLAT_IOP)         += iop
-plat-$(CONFIG_PLAT_NOMADIK)     := nomadik
+plat-$(CONFIG_PLAT_NOMADIK)     += nomadik
-plat-$(CONFIG_PLAT_ORION)       := orion
+plat-$(CONFIG_PLAT_ORION)       += orion
-plat-$(CONFIG_PLAT_PXA)         := pxa
+plat-$(CONFIG_PLAT_PXA)         += pxa
-plat-$(CONFIG_PLAT_S3C24XX)     := s3c24xx samsung
+plat-$(CONFIG_PLAT_S3C24XX)     += s3c24xx samsung
-plat-$(CONFIG_PLAT_S5P)         := samsung
+plat-$(CONFIG_PLAT_S5P)         += samsung
-plat-$(CONFIG_PLAT_SPEAR)       := spear
+plat-$(CONFIG_PLAT_SPEAR)       += spear
-plat-$(CONFIG_PLAT_VERSATILE)   := versatile
+plat-$(CONFIG_PLAT_VERSATILE)   += versatile
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
@@ -230,15 +224,20 @@ MACHINE  := arch/arm/mach-$(word 1,$(machine-y))/
 else
 MACHINE  :=
 endif
+ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)
+MACHINE  :=
+endif
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
+ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
 ifeq ($(KBUILD_SRC),)
 KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
 else
 KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
 endif
+endif
 export  TEXT_OFFSET GZFLAGS MMUEXT
@@ -251,10 +250,12 @@ endif
 core-$(CONFIG_FPE_NWFPE)        += arch/arm/nwfpe/
 core-$(CONFIG_FPE_FASTFPE)      += $(FASTFPE_OBJ)
 core-$(CONFIG_VFP)              += arch/arm/vfp/
+core-$(CONFIG_XEN)              += arch/arm/xen/
 # If we have a machine-specific directory, then include it in the build.
 core-y                          += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
 core-y                          += arch/arm/net/
+core-y                          += arch/arm/crypto/
 core-y                          += $(machdirs) $(platdirs)
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
@@ -268,7 +269,12 @@ else
 KBUILD_IMAGE := zImage
 endif
-all:    $(KBUILD_IMAGE)
+# Build the DT binary blobs if we have OF configured
+ifeq ($(CONFIG_USE_OF),y)
+KBUILD_DTBS := dtbs
+endif
+all:    $(KBUILD_IMAGE) $(KBUILD_DTBS)
 boot := arch/arm/boot
@@ -306,7 +312,7 @@ define archhelp
  echo  '  uImage        - U-Boot wrapped zImage'
  echo  '  bootpImage    - Combined zImage and initial RAM disk' 
  echo  '                  (supply initrd image via make variable INITRD=<path>)'
-  echo  '  dtbs          - Build device tree blobs for enabled boards'
+  echo  '* dtbs          - Build device tree blobs for enabled boards'
  echo  '  install       - Install uncompressed kernel'
  echo  '  zinstall      - Install compressed kernel'
  echo  '  uinstall      - Install U-Boot wrapped compressed kernel'
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index c877087d2000..3fdab016aa5c 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -15,6 +15,8 @@ ifneq ($(MACHINE),)
 include $(srctree)/$(MACHINE)/Makefile.boot
 endif
+include $(srctree)/arch/arm/boot/dts/Makefile
 # Note: the following conditions must always be true:
 #   ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
 #   PARAMS_PHYS must be within 4MB of ZRELADDR
diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore
index d0d441c429ae..f79a08efe000 100644
--- a/arch/arm/boot/compressed/.gitignore
+++ b/arch/arm/boot/compressed/.gitignore
@@ -1,6 +1,7 @@
 ashldi3.S
 font.c
 lib1funcs.S
+hyp-stub.S
 piggy.gzip
 piggy.lzo
 piggy.lzma
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index bb267562e7ed..a517153a13ea 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -30,6 +30,10 @@ FONTC	= $(srctree)/drivers/video/console/font_acorn_8x8.c
 OBJS            += string.o
 CFLAGS_string.o := -Os
+ifeq ($(CONFIG_ARM_VIRT_EXT),y)
+OBJS            += hyp-stub.o
+endif
 #
 # Architecture dependencies
 #
@@ -126,7 +130,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
 endif
 ccflags-y := -fpic -fno-builtin -I$(obj)
-asflags-y := -Wa,-march=all
+asflags-y := -Wa,-march=all -DZIMAGE
 # Supply kernel BSS size to the decompressor via a linker symbol.
 KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \
@@ -198,3 +202,6 @@ $(obj)/font.c: $(FONTC)
 $(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile $(KCONFIG_CONFIG)
        @sed "$(SEDFLAGS)" < $< > $@
+$(obj)/hyp-stub.S: $(srctree)/arch/$(SRCARCH)/kernel/hyp-stub.S
+        $(call cmd,shipped)
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index f41b38cafce8..9deb56a702ce 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -32,6 +32,9 @@ extern void error(char *);
 #  define Tracecv(c,x)
 #endif
+/* Not needed, but used in some headers pulled in by decompressors */
+extern char * strstr(const char * s1, const char *s2);
 #ifdef CONFIG_KERNEL_GZIP
 #include "../../../../lib/decompress_inflate.c"
 #endif
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index bc67cbff3944..90275f036cd1 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -9,6 +9,7 @@
 * published by the Free Software Foundation.
 */
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 /*
 * Debugging stuff
@@ -132,7 +133,12 @@ start:
                .word   start                   @ absolute load/run zImage address
                .word   _edata                  @ zImage end address
 THUMB(         .thumb                  )
-1:              mov     r7, r1                  @ save architecture ID
+1:
+                mrs     r9, cpsr
+#ifdef CONFIG_ARM_VIRT_EXT
+                bl      __hyp_stub_install      @ get into SVC mode, reversibly
+#endif
+                mov     r7, r1                  @ save architecture ID
                mov     r8, r2                  @ save atags pointer
 #ifndef __ARM_ARCH_2__
@@ -148,9 +154,9 @@ start:
 ARM(           swi     0x123456        )       @ angel_SWI_ARM
 THUMB(         svc     0xab            )       @ angel_SWI_THUMB
 not_angel:
-                mrs     r2, cpsr                @ turn off interrupts to
+                safe_svcmode_maskall r0
-                orr     r2, r2, #0xc0           @ prevent angel from running
+                msr     spsr_cxsf, r9           @ Save the CPU boot mode in
-                msr     cpsr_c, r2
+                                                @ SPSR
 #else
                teqp    pc, #0x0c000003         @ turn off interrupts
 #endif
@@ -350,6 +356,20 @@ dtb_check_done:
                adr     r5, restart
                bic     r5, r5, #31
+/* Relocate the hyp vector base if necessary */
+#ifdef CONFIG_ARM_VIRT_EXT
+                mrs     r0, spsr
+                and     r0, r0, #MODE_MASK
+                cmp     r0, #HYP_MODE
+                bne     1f
+                bl      __hyp_get_vectors
+                sub     r0, r0, r5
+                add     r0, r0, r10
+                bl      __hyp_set_vectors
+1:
+#endif
                sub     r9, r6, r5              @ size to copy
                add     r9, r9, #31             @ rounded up to a multiple
                bic     r9, r9, #31             @ ... of 32 bytes
@@ -458,11 +478,29 @@ not_relocated:	mov	r0, #0
                bl      decompress_kernel
                bl      cache_clean_flush
                bl      cache_off
-                mov     r0, #0                  @ must be zero
                mov     r1, r7                  @ restore architecture number
                mov     r2, r8                  @ restore atags pointer
- ARM(           mov     pc, r4  )               @ call kernel
- THUMB(         bx      r4      )               @ entry point is always ARM
+#ifdef CONFIG_ARM_VIRT_EXT
+                mrs     r0, spsr                @ Get saved CPU boot mode
+                and     r0, r0, #MODE_MASK
+                cmp     r0, #HYP_MODE           @ if not booted in HYP mode...
+                bne     __enter_kernel          @ boot kernel directly
+                adr     r12, .L__hyp_reentry_vectors_offset
+                ldr     r0, [r12]
+                add     r0, r0, r12
+                bl      __hyp_set_vectors
+                __HVC(0)                        @ otherwise bounce to hyp mode
+                b       .                       @ should never be reached
+                .align  2
+.L__hyp_reentry_vectors_offset: .long   __hyp_reentry_vectors - .
+#else
+                b       __enter_kernel
+#endif
                .align  2
                .type   LC0, #object
@@ -1196,6 +1234,25 @@ memdump:	mov	r12, r0
 #endif
                .ltorg
+#ifdef CONFIG_ARM_VIRT_EXT
+.align 5
+__hyp_reentry_vectors:
+                W(b)    .                       @ reset
+                W(b)    .                       @ undef
+                W(b)    .                       @ svc
+                W(b)    .                       @ pabort
+                W(b)    .                       @ dabort
+                W(b)    __enter_kernel          @ hyp
+                W(b)    .                       @ irq
+                W(b)    .                       @ fiq
+#endif /* CONFIG_ARM_VIRT_EXT */
+__enter_kernel:
+                mov     r0, #0                  @ must be 0
+ ARM(           mov     pc, r4  )               @ call kernel
+ THUMB(         bx      r4      )               @ entry point is always ARM
 reloc_code_end:
                .align
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 8e2a8fca5ed2..df899834d84e 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -25,7 +25,13 @@ unsigned int __machine_arch_type;
 static void putstr(const char *ptr);
 extern void error(char *x);
+#ifdef CONFIG_ARCH_MULTIPLATFORM
+static inline void putc(int c) {}
+static inline void flush(void) {}
+static inline void arch_decomp_setup(void) {}
+#else
 #include <mach/uncompress.h>
+#endif
 #ifdef CONFIG_DEBUG_ICEDCC
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
new file mode 100644
index 000000000000..c1ce813fcc4a
--- /dev/null
+++ b/arch/arm/boot/dts/Makefile
@@ -0,0 +1,105 @@
+ifeq ($(CONFIG_OF),y)
+dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \
+        at91sam9263ek.dtb \
+        at91sam9g20ek_2mmc.dtb \
+        at91sam9g20ek.dtb \
+        at91sam9g25ek.dtb \
+        at91sam9m10g45ek.dtb \
+        at91sam9n12ek.dtb \
+        ethernut5.dtb \
+        evk-pro3.dtb \
+        kizbox.dtb \
+        tny_a9260.dtb \
+        tny_a9263.dtb \
+        tny_a9g20.dtb \
+        usb_a9260.dtb \
+        usb_a9263.dtb \
+        usb_a9g20.dtb
+dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
+        dove-cubox.dtb \
+        dove-dove-db.dtb
+dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
+        exynos4210-smdkv310.dtb \
+        exynos4210-trats.dtb \
+        exynos5250-smdk5250.dtb
+dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
+dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
+dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
+        kirkwood-dns325.dtb \
+        kirkwood-dockstar.dtb \
+        kirkwood-dreamplug.dtb \
+        kirkwood-goflexnet.dtb \
+        kirkwood-ib62x0.dtb \
+        kirkwood-iconnect.dtb \
+        kirkwood-iomega_ix2_200.dtb \
+        kirkwood-km_kirkwood.dtb \
+        kirkwood-lschlv2.dtb \
+        kirkwood-lsxhl.dtb \
+        kirkwood-ts219-6281.dtb \
+        kirkwood-ts219-6282.dtb
+dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
+        msm8960-cdp.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
+        armada-xp-db.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
+        imx53-ard.dtb \
+        imx53-evk.dtb \
+        imx53-qsb.dtb \
+        imx53-smd.dtb \
+        imx6q-arm2.dtb \
+        imx6q-sabrelite.dtb \
+        imx6q-sabresd.dtb
+dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
+        imx23-olinuxino.dtb \
+        imx23-stmp378x_devb.dtb \
+        imx28-apx4devkit.dtb \
+        imx28-cfa10036.dtb \
+        imx28-cfa10049.dtb \
+        imx28-evk.dtb \
+        imx28-m28evk.dtb \
+        imx28-tx28.dtb
+dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
+        omap3-beagle-xm.dtb \
+        omap3-evm.dtb \
+        omap3-tobi.dtb \
+        omap4-panda.dtb \
+        omap4-pandaES.dtb \
+        omap4-var_som.dtb \
+        omap4-sdp.dtb \
+        omap5-evm.dtb \
+        am335x-evm.dtb \
+        am335x-bone.dtb
+dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
+dtb-$(CONFIG_ARCH_U8500) += snowball.dtb
+dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
+        r8a7740-armadillo800eva.dtb \
+        sh73a0-kzm9g.dtb
+dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
+        spear1340-evb.dtb
+dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
+        spear310-evb.dtb \
+        spear320-evb.dtb
+dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
+dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
+        tegra20-medcom-wide.dtb \
+        tegra20-paz00.dtb \
+        tegra20-plutux.dtb \
+        tegra20-seaboard.dtb \
+        tegra20-tec.dtb \
+        tegra20-trimslice.dtb \
+        tegra20-ventana.dtb \
+        tegra20-whistler.dtb \
+        tegra30-cardhu-a02.dtb \
+        tegra30-cardhu-a04.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
+        vexpress-v2p-ca9.dtb \
+        vexpress-v2p-ca15-tc1.dtb \
+        vexpress-v2p-ca15_a7.dtb \
+        xenvm-4.2.dtb
+dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
+        wm8505-ref.dtb \
+        wm8650-mid.dtb
+endif
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index a9af4db7234c..c634f87e230e 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -17,4 +17,64 @@
                device_type = "memory";
                reg = <0x80000000 0x10000000>; /* 256 MB */
        };
+        ocp {
+                uart1: serial@44e09000 {
+                        status = "okay";
+                };
+                i2c1: i2c@44e0b000 {
+                        status = "okay";
+                        clock-frequency = <400000>;
+                        tps: tps@24 {
+                                reg = <0x24>;
+                        };
+                };
+        };
+};
+/include/ "tps65217.dtsi"
+&tps {
+        regulators {
+                dcdc1_reg: regulator@0 {
+                        regulator-always-on;
+                };
+                dcdc2_reg: regulator@1 {
+                        /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+                        regulator-name = "vdd_mpu";
+                        regulator-min-microvolt = <925000>;
+                        regulator-max-microvolt = <1325000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                dcdc3_reg: regulator@2 {
+                        /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+                        regulator-name = "vdd_core";
+                        regulator-min-microvolt = <925000>;
+                        regulator-max-microvolt = <1150000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                ldo1_reg: regulator@3 {
+                        regulator-always-on;
+                };
+                ldo2_reg: regulator@4 {
+                        regulator-always-on;
+                };
+                ldo3_reg: regulator@5 {
+                        regulator-always-on;
+                };
+                ldo4_reg: regulator@6 {
+                        regulator-always-on;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d6a97d9eff72..185d6325a458 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -17,4 +17,104 @@
                device_type = "memory";
                reg = <0x80000000 0x10000000>; /* 256 MB */
        };
+        ocp {
+                uart1: serial@44e09000 {
+                        status = "okay";
+                };
+                i2c1: i2c@44e0b000 {
+                        status = "okay";
+                        clock-frequency = <400000>;
+                        tps: tps@2d {
+                                reg = <0x2d>;
+                        };
+                };
+        };
+        vbat: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vbat";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
+};
+/include/ "tps65910.dtsi"
+&tps {
+        vcc1-supply = <&vbat>;
+        vcc2-supply = <&vbat>;
+        vcc3-supply = <&vbat>;
+        vcc4-supply = <&vbat>;
+        vcc5-supply = <&vbat>;
+        vcc6-supply = <&vbat>;
+        vcc7-supply = <&vbat>;
+        vccio-supply = <&vbat>;
+        regulators {
+                vrtc_reg: regulator@0 {
+                        regulator-always-on;
+                };
+                vio_reg: regulator@1 {
+                        regulator-always-on;
+                };
+                vdd1_reg: regulator@2 {
+                        /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+                        regulator-name = "vdd_mpu";
+                        regulator-min-microvolt = <912500>;
+                        regulator-max-microvolt = <1312500>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                vdd2_reg: regulator@3 {
+                        /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+                        regulator-name = "vdd_core";
+                        regulator-min-microvolt = <912500>;
+                        regulator-max-microvolt = <1150000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                vdd3_reg: regulator@4 {
+                        regulator-always-on;
+                };
+                vdig1_reg: regulator@5 {
+                        regulator-always-on;
+                };
+                vdig2_reg: regulator@6 {
+                        regulator-always-on;
+                };
+                vpll_reg: regulator@7 {
+                        regulator-always-on;
+                };
+                vdac_reg: regulator@8 {
+                        regulator-always-on;
+                };
+                vaux1_reg: regulator@9 {
+                        regulator-always-on;
+                };
+                vaux2_reg: regulator@10 {
+                        regulator-always-on;
+                };
+                vaux33_reg: regulator@11 {
+                        regulator-always-on;
+                };
+                vmmc_reg: regulator@12 {
+                        regulator-always-on;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bd0cff3f808c..bb31bff01998 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -69,95 +69,146 @@
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <1>;
+                        reg = <0x44e07000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <96>;
                };
-                gpio2: gpio@4804C000 {
+                gpio2: gpio@4804c000 {
                        compatible = "ti,omap4-gpio";
                        ti,hwmods = "gpio2";
                        gpio-controller;
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <1>;
+                        reg = <0x4804c000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <98>;
                };
-                gpio3: gpio@481AC000 {
+                gpio3: gpio@481ac000 {
                        compatible = "ti,omap4-gpio";
                        ti,hwmods = "gpio3";
                        gpio-controller;
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <1>;
+                        reg = <0x481ac000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <32>;
                };
-                gpio4: gpio@481AE000 {
+                gpio4: gpio@481ae000 {
                        compatible = "ti,omap4-gpio";
                        ti,hwmods = "gpio4";
                        gpio-controller;
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <1>;
+                        reg = <0x481ae000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <62>;
                };
-                uart1: serial@44E09000 {
+                uart1: serial@44e09000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart1";
                        clock-frequency = <48000000>;
+                        reg = <0x44e09000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <72>;
+                        status = "disabled";
                };
                uart2: serial@48022000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
+                        reg = <0x48022000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <73>;
+                        status = "disabled";
                };
                uart3: serial@48024000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
+                        reg = <0x48024000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <74>;
+                        status = "disabled";
                };
-                uart4: serial@481A6000 {
+                uart4: serial@481a6000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
+                        reg = <0x481a6000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <44>;
+                        status = "disabled";
                };
-                uart5: serial@481A8000 {
+                uart5: serial@481a8000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart5";
                        clock-frequency = <48000000>;
+                        reg = <0x481a8000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <45>;
+                        status = "disabled";
                };
-                uart6: serial@481AA000 {
+                uart6: serial@481aa000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart6";
                        clock-frequency = <48000000>;
+                        reg = <0x481aa000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <46>;
+                        status = "disabled";
                };
-                i2c1: i2c@44E0B000 {
+                i2c1: i2c@44e0b000 {
                        compatible = "ti,omap4-i2c";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c1";
+                        reg = <0x44e0b000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <70>;
+                        status = "disabled";
                };
-                i2c2: i2c@4802A000 {
+                i2c2: i2c@4802a000 {
                        compatible = "ti,omap4-i2c";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c2";
+                        reg = <0x4802a000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <71>;
+                        status = "disabled";
                };
-                i2c3: i2c@4819C000 {
+                i2c3: i2c@4819c000 {
                        compatible = "ti,omap4-i2c";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c3";
+                        reg = <0x4819c000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <30>;
+                        status = "disabled";
                };
                wdt2: wdt@44e35000 {
                        compatible = "ti,omap3-wdt";
                        ti,hwmods = "wd_timer2";
+                        reg = <0x44e35000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <91>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 6b6b932a5a7d..16cc82cdaa81 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -63,6 +63,11 @@
                               reg = <0xd0020300 0x30>;
                               interrupts = <37>, <38>, <39>, <40>;
                };
+                addr-decoding@d0020000 {
+                        compatible = "marvell,armada-addr-decoding-controller";
+                        reg = <0xd0020000 0x258>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 3228ccc83332..2069151afe01 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -21,6 +21,12 @@
        model = "Marvell Armada 370 family SoC";
        compatible = "marvell,armada370", "marvell,armada-370-xp";
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+        };
        mpic: interrupt-controller@d0020000 {
              reg = <0xd0020a00 0x1d0>,
                    <0xd0021870 0x58>;
@@ -31,5 +37,43 @@
                                compatible = "marvell,armada-370-xp-system-controller";
                                reg = <0xd0018200 0x100>;
                };
+                pinctrl {
+                        compatible = "marvell,mv88f6710-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,orion-gpio";
+                        reg = <0xd0018100 0x40>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <82>, <83>, <84>, <85>;
+                };
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,orion-gpio";
+                        reg = <0xd0018140 0x40>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <87>, <88>, <89>, <90>;
+                };
+                gpio2: gpio@d0018180 {
+                        compatible = "marvell,orion-gpio";
+                        reg = <0xd0018180 0x40>;
+                        ngpios = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <91>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index f97040d4258d..b1fc728515e9 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,11 +14,11 @@
 */
 /dts-v1/;
-/include/ "armada-xp.dtsi"
+/include/ "armada-xp-mv78460.dtsi"
 / {
        model = "Marvell Armada XP Evaluation Board";
-        compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+        compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
        chosen {
                bootargs = "console=ttyS0,115200 earlyprintk";
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
new file mode 100644
index 000000000000..ea355192be6f
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78230 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+/include/ "armada-xp.dtsi"
+/ {
+        model = "Marvell Armada XP MV78230 SoC";
+        compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+        };
+        soc {
+                pinctrl {
+                        compatible = "marvell,mv78230-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018100 0x40>,
+                            <0xd0018800 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <16>, <17>, <18>, <19>;
+                };
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018140 0x40>,
+                            <0xd0018840 0x30>;
+                        ngpios = <17>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <20>, <21>, <22>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
new file mode 100644
index 000000000000..2057863f3dfa
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -0,0 +1,70 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78260 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+/include/ "armada-xp.dtsi"
+/ {
+        model = "Marvell Armada XP MV78260 SoC";
+        compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+        };
+        soc {
+                pinctrl {
+                        compatible = "marvell,mv78260-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018100 0x40>,
+                            <0xd0018800 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <16>, <17>, <18>, <19>;
+                };
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018140 0x40>,
+                            <0xd0018840 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <20>, <21>, <22>, <23>;
+                };
+                gpio2: gpio@d0018180 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018180 0x40>,
+                            <0xd0018870 0x30>;
+                        ngpios = <3>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <24>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
new file mode 100644
index 000000000000..ffac98373792
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -0,0 +1,70 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78460 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+/include/ "armada-xp.dtsi"
+/ {
+        model = "Marvell Armada XP MV78460 SoC";
+        compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+        };
+        soc {
+                pinctrl {
+                        compatible = "marvell,mv78460-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018100 0x40>,
+                            <0xd0018800 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <16>, <17>, <18>, <19>;
+                };
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018140 0x40>,
+                            <0xd0018840 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <20>, <21>, <22>, <23>;
+                };
+                gpio2: gpio@d0018180 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018180 0x40>,
+                            <0xd0018870 0x30>;
+                        ngpios = <3>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <24>;
+                };
+        };
+ };
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 7c95f76398de..d410581a5a85 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -28,6 +28,7 @@
                gpio2 = &pioC;
                tcb0 = &tcb0;
                tcb1 = &tcb1;
+                i2c0 = &i2c0;
        };
        cpus {
                cpu@0 {
@@ -202,6 +203,15 @@
                                status = "disabled";
                        };
+                        i2c0: i2c@fffac000 {
+                                compatible = "atmel,at91sam9260-i2c";
+                                reg = <0xfffac000 0x100>;
+                                interrupts = <11 4 6>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
                        adc0: adc@fffe0000 {
                                compatible = "atmel,at91sam9260-adc";
                                reg = <0xfffe0000 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 195019b7ca0e..3e6e5c1abbf3 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -24,6 +24,7 @@
                gpio3 = &pioD;
                gpio4 = &pioE;
                tcb0 = &tcb0;
+                i2c0 = &i2c0;
        };
        cpus {
                cpu@0 {
@@ -185,6 +186,15 @@
                                interrupts = <24 4 2>;
                                status = "disabled";
                        };
+                        i2c0: i2c@fff88000 {
+                                compatible = "atmel,at91sam9263-i2c";
+                                reg = <0xfff88000 0x100>;
+                                interrupts = <13 4 6>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
                };
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 2a1d1ca8bd86..75ce6e760016 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -18,6 +18,10 @@
        ahb {
                apb {
+                        i2c0: i2c@fffac000 {
+                                compatible = "atmel,at91sam9g20-i2c";
+                        };
                        adc0: adc@fffe0000 {
                                atmel,adc-startup-time = <40>;
                        };
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 96514c134e54..877c08f06763 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -32,6 +32,18 @@
                                phy-mode = "rmii";
                                status = "okay";
                        };
+                        i2c0: i2c@f8010000 {
+                                status = "okay";
+                        };
+                        i2c1: i2c@f8014000 {
+                                status = "okay";
+                        };
+                        i2c2: i2c@f8018000 {
+                                status = "okay";
+                        };
                };
                usb0: ohci@00600000 {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 63751b1e744b..3add030d61f8 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -29,6 +29,8 @@
                gpio4 = &pioE;
                tcb0 = &tcb0;
                tcb1 = &tcb1;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
        };
        cpus {
                cpu@0 {
@@ -206,6 +208,24 @@
                                status = "disabled";
                        };
+                        i2c0: i2c@fff84000 {
+                                compatible = "atmel,at91sam9g10-i2c";
+                                reg = <0xfff84000 0x100>;
+                                interrupts = <12 4 6>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        i2c1: i2c@fff88000 {
+                                compatible = "atmel,at91sam9g10-i2c";
+                                reg = <0xfff88000 0x100>;
+                                interrupts = <13 4 6>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
                        adc0: adc@fffb0000 {
                                compatible = "atmel,at91sam9260-adc";
                                reg = <0xfffb0000 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a3633bd13111..15e1dd43f625 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -46,6 +46,14 @@
                                phy-mode = "rmii";
                                status = "okay";
                        };
+                        i2c0: i2c@fff84000 {
+                                status = "okay";
+                        };
+                        i2c1: i2c@fff88000 {
+                                status = "okay";
+                        };
                };
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index ef9336ae9614..82508d68aa7e 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -26,6 +26,8 @@
                gpio3 = &pioD;
                tcb0 = &tcb0;
                tcb1 = &tcb1;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
        };
        cpus {
                cpu@0 {
@@ -182,6 +184,24 @@
                                atmel,use-dma-tx;
                                status = "disabled";
                        };
+                        i2c0: i2c@f8010000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf8010000 0x100>;
+                                interrupts = <9 4 6>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        i2c1: i2c@f8014000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf8014000 0x100>;
+                                interrupts = <10 4 6>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
                };
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index f4e43e38f3a1..912b2c283d6f 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -37,6 +37,14 @@
                        dbgu: serial@fffff200 {
                                status = "okay";
                        };
+                        i2c0: i2c@f8010000 {
+                                status = "okay";
+                        };
+                        i2c1: i2c@f8014000 {
+                                status = "okay";
+                        };
                };
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 8a387a8d61b7..03fc136421c5 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -27,6 +27,9 @@
                gpio3 = &pioD;
                tcb0 = &tcb0;
                tcb1 = &tcb1;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                i2c2 = &i2c2;
        };
        cpus {
                cpu@0 {
@@ -196,6 +199,33 @@
                                status = "disabled";
                        };
+                        i2c0: i2c@f8010000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf8010000 0x100>;
+                                interrupts = <9 4 6>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        i2c1: i2c@f8014000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf8014000 0x100>;
+                                interrupts = <10 4 6>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        i2c2: i2c@f8018000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf8018000 0x100>;
+                                interrupts = <11 4 6>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
                        adc0: adc@f804c000 {
                                compatible = "atmel,at91sam9260-adc";
                                reg = <0xf804c000 0x100>;
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
new file mode 100644
index 000000000000..7dd860f83f96
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/memreserve/ 0x0c000000 0x04000000;
+/include/ "bcm2835.dtsi"
+/ {
+        compatible = "raspberrypi,model-b", "brcm,bcm2835";
+        model = "Raspberry Pi Model B";
+        memory {
+                reg = <0 0x10000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
new file mode 100644
index 000000000000..0b619398532c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -0,0 +1,39 @@
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "brcm,bcm2835";
+        model = "BCM2835";
+        interrupt-parent = <&intc>;
+        chosen {
+                bootargs = "earlyprintk console=ttyAMA0";
+        };
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x7e000000 0x20000000 0x02000000>;
+                timer {
+                        compatible = "brcm,bcm2835-system-timer";
+                        reg = <0x7e003000 0x1000>;
+                        interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
+                        clock-frequency = <1000000>;
+                };
+                intc: interrupt-controller {
+                        compatible = "brcm,bcm2835-armctrl-ic";
+                        reg = <0x7e00b200 0x200>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                uart@20201000 {
+                        compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
+                        reg = <0x7e201000 0x1000>;
+                        interrupts = <2 25>;
+                        clock-frequency = <3000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 3180a9c588b9..748ba7aa746c 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -194,6 +194,8 @@
                        interrupts = <0 47 0x4>;
                        #address-cells = <1>;
                        #size-cells = <1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
                        ranges;
                        prcmu-timer-4@80157450 {
@@ -330,6 +332,7 @@
                        ab8500@5 {
                                compatible = "stericsson,ab8500";
                                reg = <5>; /* mailbox 5 is i2c */
+                                interrupt-parent = <&intc>;
                                interrupts = <0 40 0x4>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
@@ -371,7 +374,7 @@
                                };
                                ab8500-ponkey {
-                                        compatible = "stericsson,ab8500-ponkey";
+                                        compatible = "stericsson,ab8500-poweron-key";
                                        interrupts = <6 0x4
                                                      7 0x4>;
                                        interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
@@ -389,6 +392,12 @@
                                        compatible = "stericsson,ab8500-debug";
                                };
+                                codec: ab8500-codec {
+                                        compatible = "stericsson,ab8500-codec";
+                                        stericsson,earpeice-cmv = <950>; /* Units in mV. */
+                                };
                                ab8500-regulators {
                                        compatible = "stericsson,ab8500-regulator";
@@ -471,48 +480,63 @@
                };
                i2c@80004000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                        reg = <0x80004000 0x1000>;
                        interrupts = <0 21 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+                        clock-frequency = <400000>;
                };
                i2c@80122000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                        reg = <0x80122000 0x1000>;
                        interrupts = <0 22 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+                        clock-frequency = <400000>;
                };
                i2c@80128000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                        reg = <0x80128000 0x1000>;
                        interrupts = <0 55 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+                        clock-frequency = <400000>;
                };
                i2c@80110000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                        reg = <0x80110000 0x1000>;
                        interrupts = <0 12 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+                        clock-frequency = <400000>;
                };
                i2c@8012a000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                        reg = <0x8012a000 0x1000>;
                        interrupts = <0 51 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+                        clock-frequency = <400000>;
                };
                ssp@80002000 {
                        compatible = "arm,pl022", "arm,primecell";
-                        reg = <80002000 0x1000>;
+                        reg = <0x80002000 0x1000>;
                        interrupts = <0 14 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -580,6 +604,39 @@
                        status = "disabled";
                };
+                msp0: msp@80123000 {
+                        compatible = "stericsson,ux500-msp-i2s";
+                        reg = <0x80123000 0x1000>;
+                        interrupts = <0 31 0x4>;
+                        v-ape-supply = <&db8500_vape_reg>;
+                        status = "disabled";
+                };
+                msp1: msp@80124000 {
+                        compatible = "stericsson,ux500-msp-i2s";
+                        reg = <0x80124000 0x1000>;
+                        interrupts = <0 62 0x4>;
+                        v-ape-supply = <&db8500_vape_reg>;
+                        status = "disabled";
+                };
+                // HDMI sound
+                msp2: msp@80117000 {
+                        compatible = "stericsson,ux500-msp-i2s";
+                        reg = <0x80117000 0x1000>;
+                        interrupts = <0 98 0x4>;
+                        v-ape-supply = <&db8500_vape_reg>;
+                        status = "disabled";
+                };
+                msp3: msp@80125000 {
+                        compatible = "stericsson,ux500-msp-i2s";
+                        reg = <0x80125000 0x1000>;
+                        interrupts = <0 62 0x4>;
+                        v-ape-supply = <&db8500_vape_reg>;
+                        status = "disabled";
+                };
                external-bus@50000000 {
                        compatible = "simple-bus";
                        reg = <0x50000000 0x4000000>;
diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts
new file mode 100644
index 000000000000..61a8062e56de
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cm-a510.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+/include/ "dove.dtsi"
+/ {
+        model = "Compulab CM-A510";
+        compatible = "compulab,cm-a510", "marvell,dove";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+};
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+&spi0 {
+        status = "okay";
+        /* spi0.0: 4M Flash Winbond W25Q32BV */
+        spi-flash@0 {
+                compatible = "st,w25q32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+&i2c0 {
+          status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
new file mode 100644
index 000000000000..0adbd5a38095
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -0,0 +1,42 @@
+/dts-v1/;
+/include/ "dove.dtsi"
+/ {
+        model = "SolidRun CuBox";
+        compatible = "solidrun,cubox", "marvell,dove";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+        leds {
+                compatible = "gpio-leds";
+                power {
+                        label = "Power";
+                        gpios = <&gpio0 18 1>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+};
+&uart0 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sata0 { status = "okay"; };
+&i2c0 { status = "okay"; };
+&spi0 {
+        status = "okay";
+        /* spi0.0: 4M Flash Winbond W25Q32BV */
+        spi-flash@0 {
+                compatible = "st,w25q32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts
new file mode 100644
index 000000000000..e5a920beab45
--- /dev/null
+++ b/arch/arm/boot/dts/dove-dove-db.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+/include/ "dove.dtsi"
+/ {
+        model = "Marvell DB-MV88AP510-BP Development Board";
+        compatible = "marvell,dove-db", "marvell,dove";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+};
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+&spi0 {
+        status = "okay";
+        /* spi0.0: 4M Flash ST-M25P32-VMF6P */
+        spi-flash@0 {
+                compatible = "st,m25p32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+&i2c0 {
+          status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
new file mode 100644
index 000000000000..96fb824b5e6e
--- /dev/null
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -0,0 +1,143 @@
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "marvell,dove";
+        model = "Marvell Armada 88AP510 SoC";
+        interrupt-parent = <&intc>;
+        intc: interrupt-controller {
+                compatible = "marvell,orion-intc";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0xf1020204 0x04>,
+                      <0xf1020214 0x04>;
+        };
+        mbus@f1000000 {
+                compatible = "simple-bus";
+                ranges = <0 0xf1000000 0x4000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                uart0: serial@12000 {
+                        compatible = "ns16550a";
+                        reg = <0x12000 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <7>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+                uart1: serial@12100 {
+                        compatible = "ns16550a";
+                        reg = <0x12100 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <8>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+                uart2: serial@12200 {
+                        compatible = "ns16550a";
+                        reg = <0x12000 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <9>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+                uart3: serial@12300 {
+                        compatible = "ns16550a";
+                        reg = <0x12100 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <10>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+                wdt: wdt@20300 {
+                        compatible = "marvell,orion-wdt";
+                        reg = <0x20300 0x28>;
+                };
+                gpio0: gpio@d0400 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0xd0400 0x20>;
+                        ngpio = <32>;
+                        interrupts = <12>, <13>, <14>, <60>;
+                };
+                gpio1: gpio@d0420 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0xd0420 0x20>;
+                        ngpio = <32>;
+                        interrupts = <61>;
+                };
+                gpio2: gpio@e8400 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0xe8400 0x0c>;
+                        ngpio = <8>;
+                };
+                spi0: spi@10600 {
+                        compatible = "marvell,orion-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        interrupts = <6>;
+                        reg = <0x10600 0x28>;
+                        status = "disabled";
+                };
+                spi1: spi@14600 {
+                        compatible = "marvell,orion-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        interrupts = <5>;
+                        reg = <0x14600 0x28>;
+                        status = "disabled";
+                };
+                i2c0: i2c@11000 {
+                        compatible = "marvell,mv64xxx-i2c";
+                        reg = <0x11000 0x20>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <11>;
+                        clock-frequency = <400000>;
+                        timeout-ms = <1000>;
+                        status = "disabled";
+                };
+                sdio0: sdio@92000 {
+                        compatible = "marvell,dove-sdhci";
+                        reg = <0x92000 0x100>;
+                        interrupts = <35>, <37>;
+                        status = "disabled";
+                };
+                sdio1: sdio@90000 {
+                        compatible = "marvell,dove-sdhci";
+                        reg = <0x90000 0x100>;
+                        interrupts = <36>, <38>;
+                        status = "disabled";
+                };
+                sata0: sata@a0000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0xa0000 0x2400>;
+                        interrupts = <62>;
+                        nr-ports = <1>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts
index d79b28d9c963..a4ba31b23c88 100644
--- a/arch/arm/boot/dts/ea3250.dts
+++ b/arch/arm/boot/dts/ea3250.dts
@@ -166,9 +166,116 @@
                #size-cells = <0>;
                autorepeat;
                button@21 {
-                        label = "GPIO Key UP";
+                        label = "Interrupt Key";
                        linux,code = <103>;
                        gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
                };
+                key1 {
+                        label = "KEY1";
+                        linux,code = <1>;
+                        gpios = <&pca9532 0 0>;
+                };
+                key2 {
+                        label = "KEY2";
+                        linux,code = <2>;
+                        gpios = <&pca9532 1 0>;
+                };
+                key3 {
+                        label = "KEY3";
+                        linux,code = <3>;
+                        gpios = <&pca9532 2 0>;
+                };
+                key4 {
+                        label = "KEY4";
+                        linux,code = <4>;
+                        gpios = <&pca9532 3 0>;
+                };
+                joy0 {
+                        label = "Joystick Key 0";
+                        linux,code = <10>;
+                        gpios = <&gpio 2 0 0>; /* P2.0 */
+                };
+                joy1 {
+                        label = "Joystick Key 1";
+                        linux,code = <11>;
+                        gpios = <&gpio 2 1 0>; /* P2.1 */
+                };
+                joy2 {
+                        label = "Joystick Key 2";
+                        linux,code = <12>;
+                        gpios = <&gpio 2 2 0>; /* P2.2 */
+                };
+                joy3 {
+                        label = "Joystick Key 3";
+                        linux,code = <13>;
+                        gpios = <&gpio 2 3 0>; /* P2.3 */
+                };
+                joy4 {
+                        label = "Joystick Key 4";
+                        linux,code = <14>;
+                        gpios = <&gpio 2 4 0>; /* P2.4 */
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                /* LEDs on OEM Board */
+                led1 {
+                        gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
+                        linux,default-trigger = "timer";
+                        default-state = "off";
+                };
+                led2 {
+                        gpios = <&gpio 2 10 1>; /* P2.10, active low */
+                        default-state = "off";
+                };
+                led3 {
+                        gpios = <&gpio 2 11 1>; /* P2.11, active low */
+                        default-state = "off";
+                };
+                led4 {
+                        gpios = <&gpio 2 12 1>; /* P2.12, active low */
+                        default-state = "off";
+                };
+                /* LEDs on Base Board */
+                lede1 {
+                        gpios = <&pca9532 8 0>;
+                        default-state = "off";
+                };
+                lede2 {
+                        gpios = <&pca9532 9 0>;
+                        default-state = "off";
+                };
+                lede3 {
+                        gpios = <&pca9532 10 0>;
+                        default-state = "off";
+                };
+                lede4 {
+                        gpios = <&pca9532 11 0>;
+                        default-state = "off";
+                };
+                lede5 {
+                        gpios = <&pca9532 12 0>;
+                        default-state = "off";
+                };
+                lede6 {
+                        gpios = <&pca9532 13 0>;
+                        default-state = "off";
+                };
+                lede7 {
+                        gpios = <&pca9532 14 0>;
+                        default-state = "off";
+                };
+                lede8 {
+                        gpios = <&pca9532 15 0>;
+                        default-state = "off";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
new file mode 100644
index 000000000000..f97f70f83374
--- /dev/null
+++ b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Common devices used in different OMAP boards
+ */
+/ {
+        elpida_ECB240ABACN: lpddr2 {
+                compatible      = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
+                density         = <2048>;
+                io-width        = <32>;
+                tRPab-min-tck   = <3>;
+                tRCD-min-tck    = <3>;
+                tWR-min-tck     = <3>;
+                tRASmin-min-tck = <3>;
+                tRRD-min-tck    = <2>;
+                tWTR-min-tck    = <2>;
+                tXP-min-tck     = <2>;
+                tRTP-min-tck    = <2>;
+                tCKE-min-tck    = <3>;
+                tCKESR-min-tck  = <3>;
+                tFAW-min-tck    = <8>;
+                timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
+                        compatible      = "jedec,lpddr2-timings";
+                        min-freq        = <10000000>;
+                        max-freq        = <400000000>;
+                        tRPab           = <21000>;
+                        tRCD            = <18000>;
+                        tWR             = <15000>;
+                        tRAS-min        = <42000>;
+                        tRRD            = <10000>;
+                        tWTR            = <7500>;
+                        tXP             = <7500>;
+                        tRTP            = <7500>;
+                        tCKESR          = <15000>;
+                        tDQSCK-max      = <5500>;
+                        tFAW            = <50000>;
+                        tZQCS           = <90000>;
+                        tZQCL           = <360000>;
+                        tZQinit         = <1000000>;
+                        tRAS-max-ns     = <70000>;
+                        tDQSCK-max-derated = <6000>;
+                };
+                timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
+                        compatible      = "jedec,lpddr2-timings";
+                        min-freq        = <10000000>;
+                        max-freq        = <200000000>;
+                        tRPab           = <21000>;
+                        tRCD            = <18000>;
+                        tWR             = <15000>;
+                        tRAS-min        = <42000>;
+                        tRRD            = <10000>;
+                        tWTR            = <10000>;
+                        tXP             = <7500>;
+                        tRTP            = <7500>;
+                        tCKESR          = <15000>;
+                        tDQSCK-max      = <5500>;
+                        tFAW            = <50000>;
+                        tZQCS           = <90000>;
+                        tZQCL           = <360000>;
+                        tZQinit         = <1000000>;
+                        tRAS-max-ns     = <70000>;
+                        tDQSCK-max-derated = <6000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
new file mode 100644
index 000000000000..a26c3dd58269
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -0,0 +1,248 @@
+/*
+ * Samsung's Exynos4 SoC series common device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * Samsung's Exynos4 SoC series device nodes are listed in this file.  Particular
+ * SoCs from Exynos4 series can include this file and provide values for SoCs
+ * specfic bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        interrupt-parent = <&gic>;
+        aliases {
+                spi0 = &spi_0;
+                spi1 = &spi_1;
+                spi2 = &spi_2;
+        };
+        gic:interrupt-controller@10490000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+        };
+        combiner:interrupt-controller@10440000 {
+                compatible = "samsung,exynos4210-combiner";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0x10440000 0x1000>;
+        };
+        watchdog@10060000 {
+                compatible = "samsung,s3c2410-wdt";
+                reg = <0x10060000 0x100>;
+                interrupts = <0 43 0>;
+                status = "disabled";
+        };
+        rtc@10070000 {
+                compatible = "samsung,s3c6410-rtc";
+                reg = <0x10070000 0x100>;
+                interrupts = <0 44 0>, <0 45 0>;
+                status = "disabled";
+        };
+        keypad@100A0000 {
+                compatible = "samsung,s5pv210-keypad";
+                reg = <0x100A0000 0x100>;
+                interrupts = <0 109 0>;
+                status = "disabled";
+        };
+        sdhci@12510000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12510000 0x100>;
+                interrupts = <0 73 0>;
+                status = "disabled";
+        };
+        sdhci@12520000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12520000 0x100>;
+                interrupts = <0 74 0>;
+                status = "disabled";
+        };
+        sdhci@12530000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12530000 0x100>;
+                interrupts = <0 75 0>;
+                status = "disabled";
+        };
+        sdhci@12540000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12540000 0x100>;
+                interrupts = <0 76 0>;
+                status = "disabled";
+        };
+        serial@13800000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13800000 0x100>;
+                interrupts = <0 52 0>;
+                status = "disabled";
+        };
+        serial@13810000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13810000 0x100>;
+                interrupts = <0 53 0>;
+                status = "disabled";
+        };
+        serial@13820000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13820000 0x100>;
+                interrupts = <0 54 0>;
+                status = "disabled";
+        };
+        serial@13830000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13830000 0x100>;
+                interrupts = <0 55 0>;
+                status = "disabled";
+        };
+        i2c@13860000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13860000 0x100>;
+                interrupts = <0 58 0>;
+                status = "disabled";
+        };
+        i2c@13870000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13870000 0x100>;
+                interrupts = <0 59 0>;
+                status = "disabled";
+        };
+        i2c@13880000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13880000 0x100>;
+                interrupts = <0 60 0>;
+                status = "disabled";
+        };
+        i2c@13890000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13890000 0x100>;
+                interrupts = <0 61 0>;
+                status = "disabled";
+        };
+        i2c@138A0000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138A0000 0x100>;
+                interrupts = <0 62 0>;
+                status = "disabled";
+        };
+        i2c@138B0000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138B0000 0x100>;
+                interrupts = <0 63 0>;
+                status = "disabled";
+        };
+        i2c@138C0000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138C0000 0x100>;
+                interrupts = <0 64 0>;
+                status = "disabled";
+        };
+        i2c@138D0000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138D0000 0x100>;
+                interrupts = <0 65 0>;
+                status = "disabled";
+        };
+        spi_0: spi@13920000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x13920000 0x100>;
+                interrupts = <0 66 0>;
+                tx-dma-channel = <&pdma0 7>; /* preliminary */
+                rx-dma-channel = <&pdma0 6>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        spi_1: spi@13930000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x13930000 0x100>;
+                interrupts = <0 67 0>;
+                tx-dma-channel = <&pdma1 7>; /* preliminary */
+                rx-dma-channel = <&pdma1 6>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        spi_2: spi@13940000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x13940000 0x100>;
+                interrupts = <0 68 0>;
+                tx-dma-channel = <&pdma0 9>; /* preliminary */
+                rx-dma-channel = <&pdma0 8>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        amba {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,amba-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+                pdma0: pdma@12680000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x12680000 0x1000>;
+                        interrupts = <0 35 0>;
+                };
+                pdma1: pdma@12690000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x12690000 0x1000>;
+                        interrupts = <0 36 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 0c49caa09978..3e68f52e8454 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -40,6 +40,7 @@
                        <&gpk2 4 2 3 3>,
                        <&gpk2 5 2 3 3>,
                        <&gpk2 6 2 3 3>;
+                status = "okay";
        };
        sdhci@12510000 {
@@ -53,6 +54,7 @@
                        <&gpk0 4 2 3 3>,
                        <&gpk0 5 2 3 3>,
                        <&gpk0 6 2 3 3>;
+                status = "okay";
        };
        gpio_keys {
@@ -62,88 +64,45 @@
                up {
                        label = "Up";
-                        gpios = <&gpx2 0 0 0 2>;
+                        gpios = <&gpx2 0 0 0x10000 2>;
                        linux,code = <103>;
+                        gpio-key,wakeup;
                };
                down {
                        label = "Down";
-                        gpios = <&gpx2 1 0 0 2>;
+                        gpios = <&gpx2 1 0 0x10000 2>;
                        linux,code = <108>;
+                        gpio-key,wakeup;
                };
                back {
                        label = "Back";
-                        gpios = <&gpx1 7 0 0 2>;
+                        gpios = <&gpx1 7 0 0x10000 2>;
                        linux,code = <158>;
+                        gpio-key,wakeup;
                };
                home {
                        label = "Home";
-                        gpios = <&gpx1 6 0 0 2>;
+                        gpios = <&gpx1 6 0 0x10000 2>;
                        linux,code = <102>;
+                        gpio-key,wakeup;
                };
                menu {
                        label = "Menu";
-                        gpios = <&gpx1 5 0 0 2>;
+                        gpios = <&gpx1 5 0 0x10000 2>;
                        linux,code = <139>;
+                        gpio-key,wakeup;
                };
        };
-        keypad@100A0000 {
+        leds {
-                status = "disabled";
+                compatible = "gpio-leds";
-        };
+                status {
+                        gpios = <&gpx1 3 0 0x10000 2>;
-        sdhci@12520000 {
+                        linux,default-trigger = "heartbeat";
-                status = "disabled";
+                };
-        };
-        sdhci@12540000 {
-                status = "disabled";
-        };
-        i2c@13860000 {
-                status = "disabled";
-        };
-        i2c@13870000 {
-                status = "disabled";
-        };
-        i2c@13880000 {
-                status = "disabled";
-        };
-        i2c@13890000 {
-                status = "disabled";
-        };
-        i2c@138A0000 {
-                status = "disabled";
-        };
-        i2c@138B0000 {
-                status = "disabled";
-        };
-        i2c@138C0000 {
-                status = "disabled";
-        };
-        i2c@138D0000 {
-                status = "disabled";
-        };
-        spi_0: spi@13920000 {
-                status = "disabled";
-        };
-        spi_1: spi@13930000 {
-                status = "disabled";
-        };
-        spi_2: spi@13940000 {
-                status = "disabled";
        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
new file mode 100644
index 000000000000..b12cf272ad0d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -0,0 +1,457 @@
+/*
+ * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2011-2012 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/ {
+        pinctrl@11400000 {
+                uart0_data: uart0-data {
+                        samsung,pins = "gpa0-0", "gpa0-1";
+                        samsung,pin-function = <0x2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart0_fctl: uart0-fctl {
+                        samsung,pins = "gpa0-2", "gpa0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart1_data: uart1-data {
+                        samsung,pins = "gpa0-4", "gpa0-5";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart1_fctl: uart1-fctl {
+                        samsung,pins = "gpa0-6", "gpa0-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c2_bus: i2c2-bus {
+                        samsung,pins = "gpa0-6", "gpa0-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                uart2_data: uart2-data {
+                        samsung,pins = "gpa1-0", "gpa1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart2_fctl: uart2-fctl {
+                        samsung,pins = "gpa1-2", "gpa1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart_audio_a: uart-audio-a {
+                        samsung,pins = "gpa1-0", "gpa1-1";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c3_bus: i2c3-bus {
+                        samsung,pins = "gpa1-2", "gpa1-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                uart3_data: uart3-data {
+                        samsung,pins = "gpa1-4", "gpa1-5";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                uart_audio_b: uart-audio-b {
+                        samsung,pins = "gpa1-4", "gpa1-5";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                spi0_bus: spi0-bus {
+                        samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c4_bus: i2c4-bus {
+                        samsung,pins = "gpb-2", "gpb-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                spi1_bus: spi1-bus {
+                        samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c5_bus: i2c5-bus {
+                        samsung,pins = "gpb-6", "gpb-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2s1_bus: i2s1-bus {
+                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                        "gpc0-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pcm1_bus: pcm1-bus {
+                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                        "gpc0-4";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                ac97_bus: ac97-bus {
+                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                        "gpc0-4";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                i2s2_bus: i2s2-bus {
+                        samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                        "gpc1-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pcm2_bus: pcm2-bus {
+                        samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                        "gpc1-4";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                spdif_bus: spdif-bus {
+                        samsung,pins = "gpc1-0", "gpc1-1";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c6_bus: i2c6-bus {
+                        samsung,pins = "gpc1-3", "gpc1-4";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                spi2_bus: spi2-bus {
+                        samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
+                        samsung,pin-function = <5>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c7_bus: i2c7-bus {
+                        samsung,pins = "gpd0-2", "gpd0-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c0_bus: i2c0-bus {
+                        samsung,pins = "gpd1-0", "gpd1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                i2c1_bus: i2c1-bus {
+                        samsung,pins = "gpd1-2", "gpd1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+        pinctrl@11000000 {
+                sd0_clk: sd0-clk {
+                        samsung,pins = "gpk0-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                sd0_cmd: sd0-cmd {
+                        samsung,pins = "gpk0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                sd0_cd: sd0-cd {
+                        samsung,pins = "gpk0-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd0_bus1: sd0-bus-width1 {
+                        samsung,pins = "gpk0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd0_bus4: sd0-bus-width4 {
+                        samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd0_bus8: sd0-bus-width8 {
+                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd4_clk: sd4-clk {
+                        samsung,pins = "gpk0-0";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                sd4_cmd: sd4-cmd {
+                        samsung,pins = "gpk0-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                sd4_cd: sd4-cd {
+                        samsung,pins = "gpk0-2";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd4_bus1: sd4-bus-width1 {
+                        samsung,pins = "gpk0-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd4_bus4: sd4-bus-width4 {
+                        samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd4_bus8: sd4-bus-width8 {
+                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <4>;
+                        samsung,pin-drv = <0>;
+                };
+                sd1_clk: sd1-clk {
+                        samsung,pins = "gpk1-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                sd1_cmd: sd1-cmd {
+                        samsung,pins = "gpk1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                sd1_cd: sd1-cd {
+                        samsung,pins = "gpk1-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd1_bus1: sd1-bus-width1 {
+                        samsung,pins = "gpk1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd1_bus4: sd1-bus-width4 {
+                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd2_clk: sd2-clk {
+                        samsung,pins = "gpk2-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                sd2_cmd: sd2-cmd {
+                        samsung,pins = "gpk2-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                sd2_cd: sd2-cd {
+                        samsung,pins = "gpk2-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd2_bus1: sd2-bus-width1 {
+                        samsung,pins = "gpk2-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd2_bus4: sd2-bus-width4 {
+                        samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd2_bus8: sd2-bus-width8 {
+                        samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd3_clk: sd3-clk {
+                        samsung,pins = "gpk3-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                sd3_cmd: sd3-cmd {
+                        samsung,pins = "gpk3-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                sd3_cd: sd3-cd {
+                        samsung,pins = "gpk3-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd3_bus1: sd3-bus-width1 {
+                        samsung,pins = "gpk3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                sd3_bus4: sd3-bus-width4 {
+                        samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                eint0: ext-int0 {
+                        samsung,pins = "gpx0-0";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                eint8: ext-int8 {
+                        samsung,pins = "gpx1-0";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                eint15: ext-int15 {
+                        samsung,pins = "gpx1-7";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                eint16: ext-int16 {
+                        samsung,pins = "gpx2-0";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                eint31: ext-int31 {
+                        samsung,pins = "gpx3-7";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+        pinctrl@03860000 {
+                i2s0_bus: i2s0-bus {
+                        samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                        "gpz-4", "gpz-5", "gpz-6";
+                        samsung,pin-function = <0x2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pcm0_bus: pcm0-bus {
+                        samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                        "gpz-4";
+                        samsung,pin-function = <0x3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 1beccc8f14ff..63610c3ba3af 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -26,7 +26,7 @@
        };
        chosen {
-                bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
+                bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
        };
        sdhci@12530000 {
@@ -40,6 +40,7 @@
                        <&gpk2 4 2 3 3>,
                        <&gpk2 5 2 3 3>,
                        <&gpk2 6 2 3 3>;
+                status = "okay";
        };
        keypad@100A0000 {
@@ -47,6 +48,7 @@
                samsung,keypad-num-columns = <8>;
                linux,keypad-no-autorepeat;
                linux,keypad-wakeup;
+                status = "okay";
                row-gpios = <&gpx2 0 3 3 0>,
                            <&gpx2 1 3 3 0>;
@@ -128,6 +130,7 @@
                samsung,i2c-max-bus-freq = <20000>;
                gpios = <&gpd1 0 2 3 0>,
                        <&gpd1 1 2 3 0>;
+                status = "okay";
                eeprom@50 {
                        compatible = "samsung,24ad0xd1";
@@ -140,58 +143,11 @@
                };
        };
-        sdhci@12510000 {
-                status = "disabled";
-        };
-        sdhci@12520000 {
-                status = "disabled";
-        };
-        sdhci@12540000 {
-                status = "disabled";
-        };
-        i2c@13870000 {
-                status = "disabled";
-        };
-        i2c@13880000 {
-                status = "disabled";
-        };
-        i2c@13890000 {
-                status = "disabled";
-        };
-        i2c@138A0000 {
-                status = "disabled";
-        };
-        i2c@138B0000 {
-                status = "disabled";
-        };
-        i2c@138C0000 {
-                status = "disabled";
-        };
-        i2c@138D0000 {
-                status = "disabled";
-        };
-        spi_0: spi@13920000 {
-                status = "disabled";
-        };
-        spi_1: spi@13930000 {
-                status = "disabled";
-        };
        spi_2: spi@13940000 {
                gpios = <&gpc1 1 5 3 0>,
                        <&gpc1 3 5 3 0>,
                        <&gpc1 4 5 3 0>;
+                status = "okay";
                w25x80@0 {
                        #address-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
new file mode 100644
index 000000000000..73567b843e72
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -0,0 +1,237 @@
+/*
+ * Samsung's Exynos4210 based Trats board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Trats board which is based on
+ * Samsung's Exynos4210 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/dts-v1/;
+/include/ "exynos4210.dtsi"
+/ {
+        model = "Samsung Trats based on Exynos4210";
+        compatible = "samsung,trats", "samsung,exynos4210";
+        memory {
+                reg =  <0x40000000 0x20000000
+                        0x60000000 0x20000000>;
+        };
+        chosen {
+                bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
+        };
+        vemmc_reg: voltage-regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "VMEM_VDD_2.8V";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpk0 2 1 0 0>;
+                enable-active-high;
+        };
+        sdhci_emmc: sdhci@12510000 {
+                bus-width = <8>;
+                non-removable;
+                broken-voltage;
+                gpios = <&gpk0 0 2 0 3>,
+                        <&gpk0 1 2 0 3>,
+                        <&gpk0 3 2 2 3>,
+                        <&gpk0 4 2 2 3>,
+                        <&gpk0 5 2 2 3>,
+                        <&gpk0 6 2 2 3>,
+                        <&gpk1 3 3 3 3>,
+                        <&gpk1 4 3 3 3>,
+                        <&gpk1 5 3 3 3>,
+                        <&gpk1 6 3 3 3>;
+                vmmc-supply = <&vemmc_reg>;
+                status = "okay";
+        };
+        serial@13800000 {
+                status = "okay";
+        };
+        serial@13810000 {
+                status = "okay";
+        };
+        serial@13820000 {
+                status = "okay";
+        };
+        serial@13830000 {
+                status = "okay";
+        };
+        i2c@138B0000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-slave-addr = <0x10>;
+                samsung,i2c-max-bus-freq = <100000>;
+                gpios = <&gpb 6 3 3 0>,
+                        <&gpb 7 3 3 0>;
+                status = "okay";
+                max8997_pmic@66 {
+                        compatible = "maxim,max8997-pmic";
+                        reg = <0x66>;
+                        max8997,pmic-buck1-uses-gpio-dvs;
+                        max8997,pmic-buck2-uses-gpio-dvs;
+                        max8997,pmic-buck5-uses-gpio-dvs;
+                        max8997,pmic-ignore-gpiodvs-side-effect;
+                        max8997,pmic-buck125-default-dvs-idx = <0>;
+                        max8997,pmic-buck125-dvs-gpios = <&gpx0 5 1 0 0>,
+                                                         <&gpx0 6 1 0 0>,
+                                                         <&gpl0 0 1 0 0>;
+                        max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
+                                                         <1250000>, <1200000>,
+                                                         <1150000>, <1100000>,
+                                                         <1000000>, <950000>;
+                        max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>,
+                                                         <950000>,  <900000>,
+                                                         <1100000>, <1000000>,
+                                                         <950000>,  <900000>;
+                        max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>;
+                        regulators {
+                                valive_reg: LDO2 {
+                                     regulator-name = "VALIVE_1.1V_C210";
+                                     regulator-min-microvolt = <1100000>;
+                                     regulator-max-microvolt = <1100000>;
+                                     regulator-always-on;
+                                };
+                                vusb_reg: LDO3 {
+                                     regulator-name = "VUSB_1.1V_C210";
+                                     regulator-min-microvolt = <1100000>;
+                                     regulator-max-microvolt = <1100000>;
+                                };
+                                vmipi_reg: LDO4 {
+                                     regulator-name = "VMIPI_1.8V";
+                                     regulator-min-microvolt = <1800000>;
+                                     regulator-max-microvolt = <1800000>;
+                                };
+                                vpda_reg: LDO6 {
+                                     regulator-name = "VCC_1.8V_PDA";
+                                     regulator-min-microvolt = <1800000>;
+                                     regulator-max-microvolt = <1800000>;
+                                     regulator-always-on;
+                                };
+                                vcam_reg: LDO7 {
+                                     regulator-name = "CAM_ISP_1.8V";
+                                     regulator-min-microvolt = <1800000>;
+                                     regulator-max-microvolt = <1800000>;
+                                };
+                                vusbdac_reg: LDO8 {
+                                     regulator-name = "VUSB/VDAC_3.3V_C210";
+                                     regulator-min-microvolt = <3300000>;
+                                     regulator-max-microvolt = <3300000>;
+                                };
+                                vccpda_reg: LDO9 {
+                                     regulator-name = "VCC_2.8V_PDA";
+                                     regulator-min-microvolt = <2800000>;
+                                     regulator-max-microvolt = <2800000>;
+                                     regulator-always-on;
+                                };
+                                vpll_reg: LDO10 {
+                                     regulator-name = "VPLL_1.1V_C210";
+                                     regulator-min-microvolt = <1100000>;
+                                     regulator-max-microvolt = <1100000>;
+                                     regulator-always-on;
+                                };
+                                vcclcd_reg: LDO13 {
+                                     regulator-name = "VCC_3.3V_LCD";
+                                     regulator-min-microvolt = <3300000>;
+                                     regulator-max-microvolt = <3300000>;
+                                };
+                                vlcd_reg: LDO15 {
+                                     regulator-name = "VLCD_2.2V";
+                                     regulator-min-microvolt = <2200000>;
+                                     regulator-max-microvolt = <2200000>;
+                                };
+                                camsensor_reg: LDO16 {
+                                     regulator-name = "CAM_SENSOR_IO_1.8V";
+                                     regulator-min-microvolt = <1800000>;
+                                     regulator-max-microvolt = <1800000>;
+                                };
+                                vddq_reg: LDO21 {
+                                     regulator-name = "VDDQ_M1M2_1.2V";
+                                     regulator-min-microvolt = <1200000>;
+                                     regulator-max-microvolt = <1200000>;
+                                     regulator-always-on;
+                                };
+                                varm_breg: BUCK1 {
+                                     regulator-name = "VARM_1.2V_C210";
+                                     regulator-min-microvolt = <900000>;
+                                     regulator-max-microvolt = <1350000>;
+                                     regulator-always-on;
+                                };
+                                vint_breg: BUCK2 {
+                                     regulator-name = "VINT_1.1V_C210";
+                                     regulator-min-microvolt = <900000>;
+                                     regulator-max-microvolt = <1100000>;
+                                     regulator-always-on;
+                                };
+                                camisp_breg: BUCK4 {
+                                     regulator-name = "CAM_ISP_CORE_1.2V";
+                                     regulator-min-microvolt = <1200000>;
+                                     regulator-max-microvolt = <1200000>;
+                                };
+                                vmem_breg: BUCK5 {
+                                     regulator-name = "VMEM_1.2V_C210";
+                                     regulator-min-microvolt = <1200000>;
+                                     regulator-max-microvolt = <1200000>;
+                                     regulator-always-on;
+                                };
+                                vccsub_breg: BUCK7 {
+                                     regulator-name = "VCC_SUB_2.0V";
+                                     regulator-min-microvolt = <2000000>;
+                                     regulator-max-microvolt = <2000000>;
+                                     regulator-always-on;
+                                };
+                                safe1_sreg: ESAFEOUT1 {
+                                     regulator-name = "SAFEOUT1";
+                                     regulator-always-on;
+                                };
+                                safe2_sreg: ESAFEOUT2 {
+                                     regulator-name = "SAFEOUT2";
+                                     regulator-boot-on;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 02891fe876e4..214c557eda7f 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,199 +19,60 @@
 * published by the Free Software Foundation.
 */
-/include/ "skeleton.dtsi"
+/include/ "exynos4.dtsi"
+/include/ "exynos4210-pinctrl.dtsi"
 / {
        compatible = "samsung,exynos4210";
-        interrupt-parent = <&gic>;
        aliases {
-                spi0 = &spi_0;
+                pinctrl0 = &pinctrl_0;
-                spi1 = &spi_1;
+                pinctrl1 = &pinctrl_1;
-                spi2 = &spi_2;
+                pinctrl2 = &pinctrl_2;
        };
        gic:interrupt-controller@10490000 {
-                compatible = "arm,cortex-a9-gic";
-                #interrupt-cells = <3>;
-                interrupt-controller;
                cpu-offset = <0x8000>;
-                reg = <0x10490000 0x1000>, <0x10480000 0x100>;
        };
        combiner:interrupt-controller@10440000 {
-                compatible = "samsung,exynos4210-combiner";
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                reg = <0x10440000 0x1000>;
                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
        };
-        watchdog@10060000 {
+        pinctrl_0: pinctrl@11400000 {
-                compatible = "samsung,s3c2410-wdt";
+                compatible = "samsung,pinctrl-exynos4210";
-                reg = <0x10060000 0x100>;
+                reg = <0x11400000 0x1000>;
-                interrupts = <0 43 0>;
+                interrupts = <0 47 0>;
-        };
+                interrupt-controller;
+                #interrupt-cells = <2>;
-        rtc@10070000 {
-                compatible = "samsung,s3c6410-rtc";
-                reg = <0x10070000 0x100>;
-                interrupts = <0 44 0>, <0 45 0>;
-        };
-        keypad@100A0000 {
-                compatible = "samsung,s5pv210-keypad";
-                reg = <0x100A0000 0x100>;
-                interrupts = <0 109 0>;
-        };
-        sdhci@12510000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12510000 0x100>;
-                interrupts = <0 73 0>;
-        };
-        sdhci@12520000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12520000 0x100>;
-                interrupts = <0 74 0>;
-        };
-        sdhci@12530000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12530000 0x100>;
-                interrupts = <0 75 0>;
-        };
-        sdhci@12540000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12540000 0x100>;
-                interrupts = <0 76 0>;
-        };
-        serial@13800000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x13800000 0x100>;
-                interrupts = <0 52 0>;
-        };
-        serial@13810000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x13810000 0x100>;
-                interrupts = <0 53 0>;
-        };
-        serial@13820000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x13820000 0x100>;
-                interrupts = <0 54 0>;
-        };
-        serial@13830000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x13830000 0x100>;
-                interrupts = <0 55 0>;
-        };
-        i2c@13860000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x13860000 0x100>;
-                interrupts = <0 58 0>;
-        };
-        i2c@13870000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x13870000 0x100>;
-                interrupts = <0 59 0>;
-        };
-        i2c@13880000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x13880000 0x100>;
-                interrupts = <0 60 0>;
-        };
-        i2c@13890000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x13890000 0x100>;
-                interrupts = <0 61 0>;
-        };
-        i2c@138A0000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x138A0000 0x100>;
-                interrupts = <0 62 0>;
-        };
-        i2c@138B0000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x138B0000 0x100>;
-                interrupts = <0 63 0>;
-        };
-        i2c@138C0000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x138C0000 0x100>;
-                interrupts = <0 64 0>;
-        };
-        i2c@138D0000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x138D0000 0x100>;
-                interrupts = <0 65 0>;
-        };
-        spi_0: spi@13920000 {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0x13920000 0x100>;
-                interrupts = <0 66 0>;
-                tx-dma-channel = <&pdma0 7>; /* preliminary */
-                rx-dma-channel = <&pdma0 6>; /* preliminary */
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
-        spi_1: spi@13930000 {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0x13930000 0x100>;
-                interrupts = <0 67 0>;
-                tx-dma-channel = <&pdma1 7>; /* preliminary */
-                rx-dma-channel = <&pdma1 6>; /* preliminary */
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
-        spi_2: spi@13940000 {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0x13940000 0x100>;
-                interrupts = <0 68 0>;
-                tx-dma-channel = <&pdma0 9>; /* preliminary */
-                rx-dma-channel = <&pdma0 8>; /* preliminary */
-                #address-cells = <1>;
-                #size-cells = <0>;
        };
-        amba {
+        pinctrl_1: pinctrl@11000000 {
-                #address-cells = <1>;
+                compatible = "samsung,pinctrl-exynos4210";
-                #size-cells = <1>;
+                reg = <0x11000000 0x1000>;
-                compatible = "arm,amba-bus";
+                interrupts = <0 46 0>;
-                interrupt-parent = <&gic>;
+                interrupt-controller;
-                ranges;
+                #interrupt-cells = <2>;
-                pdma0: pdma@12680000 {
+                wakup_eint: wakeup-interrupt-controller {
-                        compatible = "arm,pl330", "arm,primecell";
+                        compatible = "samsung,exynos4210-wakeup-eint";
-                        reg = <0x12680000 0x1000>;
+                        interrupt-parent = <&gic>;
-                        interrupts = <0 35 0>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                                     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+                                     <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+                                     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
+                                     <0 32 0>;
                };
+        };
-                pdma1: pdma@12690000 {
+        pinctrl_2: pinctrl@03860000 {
-                        compatible = "arm,pl330", "arm,primecell";
+                compatible = "samsung,pinctrl-exynos4210";
-                        reg = <0x12690000 0x1000>;
+                reg = <0x03860000 0x1000>;
-                        interrupts = <0 36 0>;
-                };
        };
        gpio-controllers {
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348793c7..a352df403b7a 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -16,12 +16,19 @@
        model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
        compatible = "samsung,smdk5250", "samsung,exynos5250";
+        aliases {
+                mshc0 = &dwmmc_0;
+                mshc1 = &dwmmc_1;
+                mshc2 = &dwmmc_2;
+                mshc3 = &dwmmc_3;
+        };
        memory {
                reg = <0x40000000 0x80000000>;
        };
        chosen {
-                bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
+                bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
        };
        i2c@12C60000 {
@@ -72,6 +79,56 @@
                status = "disabled";
        };
+        dwmmc_0: dwmmc0@12200000 {
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3 3>;
+                samsung,dw-mshc-ddr-timing = <1 2 3>;
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                        gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
+                                <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
+                                <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
+                                <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
+                                <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
+                };
+        };
+        dwmmc_1: dwmmc1@12210000 {
+                status = "disabled";
+        };
+        dwmmc_2: dwmmc2@12220000 {
+                num-slots = <1>;
+                supports-highspeed;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3 3>;
+                samsung,dw-mshc-ddr-timing = <1 2 3>;
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <4>;
+                        samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
+                        gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
+                                <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
+                                <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>,
+                                <&gpc4 3 3 3 3>, <&gpc4 3 3 3 3>,
+                                <&gpc4 5 3 3 3>, <&gpc4 6 3 3 3>;
+                };
+        };
+        dwmmc_3: dwmmc3@12230000 {
+                status = "disabled";
+        };
        spi_0: spi@12d20000 {
                status = "disabled";
        };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 004aaa8d123c..dddfd6e444dc 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -27,6 +27,10 @@
                spi0 = &spi_0;
                spi1 = &spi_1;
                spi2 = &spi_2;
+                gsc0 = &gsc_0;
+                gsc1 = &gsc_1;
+                gsc2 = &gsc_2;
+                gsc3 = &gsc_3;
        };
        gic:interrupt-controller@10481000 {
@@ -182,6 +186,38 @@
                #size-cells = <0>;
        };
+        dwmmc0@12200000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                reg = <0x12200000 0x1000>;
+                interrupts = <0 75 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+        dwmmc1@12210000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                reg = <0x12210000 0x1000>;
+                interrupts = <0 76 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+        dwmmc2@12220000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                reg = <0x12220000 0x1000>;
+                interrupts = <0 77 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+        dwmmc3@12230000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                reg = <0x12230000 0x1000>;
+                interrupts = <0 78 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
        amba {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -460,4 +496,28 @@
                        #gpio-cells = <4>;
                };
        };
+        gsc_0:  gsc@0x13e00000 {
+                compatible = "samsung,exynos5-gsc";
+                reg = <0x13e00000 0x1000>;
+                interrupts = <0 85 0>;
+        };
+        gsc_1:  gsc@0x13e10000 {
+                compatible = "samsung,exynos5-gsc";
+                reg = <0x13e10000 0x1000>;
+                interrupts = <0 86 0>;
+        };
+        gsc_2:  gsc@0x13e20000 {
+                compatible = "samsung,exynos5-gsc";
+                reg = <0x13e20000 0x1000>;
+                interrupts = <0 87 0>;
+        };
+        gsc_3:  gsc@0x13e30000 {
+                compatible = "samsung,exynos5-gsc";
+                reg = <0x13e30000 0x1000>;
+                interrupts = <0 88 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 9fecf1ae777b..0c6fc34821f9 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -121,6 +121,10 @@
                        compatible = "calxeda,hb-ahci";
                        reg = <0xffe08000 0x10000>;
                        interrupts = <0 83 4>;
+                        calxeda,port-phys = <&combophy5 0 &combophy0 0
+                                             &combophy0 1 &combophy0 2
+                                             &combophy0 3>;
+                        dma-coherent;
                };
                sdhci@ffe0e000 {
@@ -306,5 +310,19 @@
                        reg = <0xfff51000 0x1000>;
                        interrupts = <0 80 4  0 81 4  0 82 4>;
                };
+                combophy0: combo-phy@fff58000 {
+                        compatible = "calxeda,hb-combophy";
+                        #phy-cells = <1>;
+                        reg = <0xfff58000 0x1000>;
+                        phydev = <5>;
+                };
+                combophy5: combo-phy@fff5d000 {
+                        compatible = "calxeda,hb-combophy";
+                        #phy-cells = <1>;
+                        reg = <0xfff5d000 0x1000>;
+                        phydev = <31>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
new file mode 100644
index 000000000000..2131d77dc9c9
--- /dev/null
+++ b/arch/arm/boot/dts/hrefv60plus.dts
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2012 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "dbx5x0.dtsi"
+/ {
+        model = "ST-Ericsson HREF platform with Device Tree";
+        compatible = "st-ericsson,hrefv60+";
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+        soc-u9500 {
+                uart@80120000 {
+                        status = "okay";
+                };
+                uart@80121000 {
+                        status = "okay";
+                };
+                uart@80007000 {
+                        status = "okay";
+                };
+                i2c@80004000 {
+                        tc3589x@42 {
+                                compatible = "tc3589x";
+                                reg = <0x42>;
+                                interrupt-parent = <&gpio6>;
+                                interrupts = <25 0x1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                tc3589x_gpio: tc3589x_gpio {
+                                        compatible = "tc3589x-gpio";
+                                        interrupts = <0 0x1>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+                        };
+                        tps61052@33 {
+                                compatible = "tps61052";
+                                reg = <0x33>;
+                        };
+                };
+                i2c@80128000 {
+                        lp5521@0x33 {
+                                compatible = "lp5521";
+                                reg = <0x33>;
+                        };
+                        lp5521@0x34 {
+                                compatible = "lp5521";
+                                reg = <0x34>;
+                        };
+                        bh1780@0x29 {
+                                compatible = "rohm,bh1780gli";
+                                reg = <0x33>;
+                        };
+                };
+                sound {
+                        compatible = "stericsson,snd-soc-mop500";
+                        stericsson,cpu-dai = <&msp1 &msp3>;
+                        stericsson,audio-codec = <&codec>;
+                };
+                msp1: msp@80124000 {
+                        status = "okay";
+                };
+                msp3: msp@80125000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index e3486f486b40..035c13f9d3c0 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -42,12 +42,13 @@
                                pinctrl-names = "default";
                                pinctrl-0 = <&hog_pins_a>;
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
                                                0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */
                                                0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
                                                0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
+                                                0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
                                        >;
                                        fsl,drive-strength = <0>;
                                        fsl,voltage = <1>;
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index 20912b1d8893..384d8b66f337 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -31,6 +31,22 @@
                                bus-width = <4>;
                                status = "okay";
                        };
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+                                hog_pins_a: hog@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
+                                                0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
                };
                apbx@80040000 {
@@ -39,6 +55,47 @@
                                pinctrl-0 = <&duart_pins_a>;
                                status = "okay";
                        };
+                        auart0: serial@8006c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_2pins_a>;
+                                status = "okay";
+                        };
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+                };
+        };
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        vbus-supply = <&reg_usb0_vbus>;
+                        status = "okay";
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                reg_usb0_vbus: usb0_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
+                        gpio = <&gpio0 17 0>;
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                user {
+                        label = "green";
+                        gpios = <&gpio2 1 0>;
+                        linux,default-trigger = "default-on";
                };
        };
 };
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index 757a327ff3e8..85c3864b6a56 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -36,7 +36,7 @@
                                pinctrl-names = "default";
                                pinctrl-0 = <&hog_pins_a>;
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
                                                0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index e6138310e5ce..9ca4ca70c1bc 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -43,7 +43,7 @@
                        ranges;
                        icoll: interrupt-controller@80000000 {
-                                compatible = "fsl,imx23-icoll", "fsl,mxs-icoll";
+                                compatible = "fsl,imx23-icoll", "fsl,icoll";
                                interrupt-controller;
                                #interrupt-cells = <1>;
                                reg = <0x80000000 0x2000>;
@@ -52,6 +52,7 @@
                        dma-apbh@80004000 {
                                compatible = "fsl,imx23-dma-apbh";
                                reg = <0x80004000 0x2000>;
+                                clocks = <&clks 15>;
                        };
                        ecc@80008000 {
@@ -67,6 +68,7 @@
                                reg-names = "gpmi-nand", "bch";
                                interrupts = <13>, <56>;
                                interrupt-names = "gpmi-dma", "bch";
+                                clocks = <&clks 34>;
                                fsl,gpmi-dma-channel = <4>;
                                status = "disabled";
                        };
@@ -74,6 +76,7 @@
                        ssp0: ssp@80010000 {
                                reg = <0x80010000 0x2000>;
                                interrupts = <15 14>;
+                                clocks = <&clks 33>;
                                fsl,ssp-dma-channel = <1>;
                                status = "disabled";
                        };
@@ -140,6 +143,17 @@
                                        fsl,pull-up = <0>;
                                };
+                                auart0_2pins_a: auart0-2pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
+                                                0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                                gpmi_pins_a: gpmi-nand@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
@@ -183,7 +197,6 @@
                                                0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
                                                0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
                                                0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
-                                                0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
                                                0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
                                        >;
                                        fsl,drive-strength = <1>;
@@ -280,6 +293,7 @@
                        dma-apbx@80024000 {
                                compatible = "fsl,imx23-dma-apbx";
                                reg = <0x80024000 0x2000>;
+                                clocks = <&clks 16>;
                        };
                        dcp@80028000 {
@@ -306,12 +320,14 @@
                                compatible = "fsl,imx23-lcdif";
                                reg = <0x80030000 2000>;
                                interrupts = <46 45>;
+                                clocks = <&clks 38>;
                                status = "disabled";
                        };
                        ssp1: ssp@80034000 {
                                reg = <0x80034000 0x2000>;
                                interrupts = <2 20>;
+                                clocks = <&clks 33>;
                                fsl,ssp-dma-channel = <2>;
                                status = "disabled";
                        };
@@ -329,9 +345,10 @@
                        reg = <0x80040000 0x40000>;
                        ranges;
-                        clkctl@80040000 {
+                        clks: clkctrl@80040000 {
+                                compatible = "fsl,imx23-clkctrl";
                                reg = <0x80040000 0x2000>;
-                                status = "disabled";
+                                #clock-cells = <1>;
                        };
                        saif0: saif@80042000 {
@@ -383,20 +400,23 @@
                        pwm: pwm@80064000 {
                                compatible = "fsl,imx23-pwm";
                                reg = <0x80064000 0x2000>;
+                                clocks = <&clks 30>;
                                #pwm-cells = <2>;
                                fsl,pwm-number = <5>;
                                status = "disabled";
                        };
                        timrot@80068000 {
+                                compatible = "fsl,imx23-timrot", "fsl,timrot";
                                reg = <0x80068000 0x2000>;
-                                status = "disabled";
+                                interrupts = <28 29 30 31>;
                        };
                        auart0: serial@8006c000 {
                                compatible = "fsl,imx23-auart";
                                reg = <0x8006c000 0x2000>;
                                interrupts = <24 25 23>;
+                                clocks = <&clks 32>;
                                status = "disabled";
                        };
@@ -404,6 +424,7 @@
                                compatible = "fsl,imx23-auart";
                                reg = <0x8006e000 0x2000>;
                                interrupts = <59 60 58>;
+                                clocks = <&clks 32>;
                                status = "disabled";
                        };
@@ -411,11 +432,15 @@
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x80070000 0x2000>;
                                interrupts = <0>;
+                                clocks = <&clks 32>, <&clks 16>;
+                                clock-names = "uart", "apb_pclk";
                                status = "disabled";
                        };
-                        usbphy@8007c000 {
+                        usbphy0: usbphy@8007c000 {
+                                compatible = "fsl,imx23-usbphy";
                                reg = <0x8007c000 0x2000>;
+                                clocks = <&clks 41>;
                                status = "disabled";
                        };
                };
@@ -428,8 +453,12 @@
                reg = <0x80080000 0x80000>;
                ranges;
-                usbctrl@80080000 {
+                usb0: usb@80080000 {
+                        compatible = "fsl,imx23-usb", "fsl,imx27-usb";
                        reg = <0x80080000 0x40000>;
+                        interrupts = <11>;
+                        fsl,usbphy = <&usbphy0>;
+                        clocks = <&clks 40>;
                        status = "disabled";
                };
        };
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index 2b0ff60247a4..af50469e34b2 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -23,10 +23,6 @@
        soc {
                aipi@10000000 { /* aipi */
-                        wdog@10002000 {
-                                status = "okay";
-                        };
                        serial@1000a000 {
                                fsl,uart-has-rtscts;
                                status = "okay";
@@ -49,7 +45,7 @@
                        i2c@1001d000 {
                                clock-frequency = <400000>;
                                status = "okay";
-                                at24@4c {
+                                at24@52 {
                                        compatible = "at,24c32";
                                        pagesize = <32>;
                                        reg = <0x52>;
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 5303ab680a34..3e54f1498841 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -62,7 +62,6 @@
                                compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
                                reg = <0x10002000 0x4000>;
                                interrupts = <27>;
-                                status = "disabled";
                        };
                        uart1: serial@1000a000 {
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index b383417a558f..5171667a7763 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -37,7 +37,7 @@
                                pinctrl-names = "default";
                                pinctrl-0 = <&hog_pins_a>;
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
                                                0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
new file mode 100644
index 000000000000..05c892e931e3
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2012 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*
+ * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
+ * need to include the CFA-10036 DTS.
+ */
+/include/ "imx28-cfa10036.dts"
+/ {
+        model = "Crystalfontz CFA-10049 Board";
+        compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
+        apb@80000000 {
+                apbh@80000000 {
+                        pinctrl@80018000 {
+                                spi3_pins_cfa10049: spi3-cfa10049@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */
+                                                0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
+                                                0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
+                                                0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+                        };
+                        ssp3: ssp@80016000 {
+                                compatible = "fsl,imx28-spi";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi3_pins_cfa10049>;
+                                status = "okay";
+                                gpio5: gpio5@0 {
+                                        compatible = "fairchild,74hc595";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <0>;
+                                        registers-number = <2>;
+                                        spi-max-frequency = <100000>;
+                                };
+                                gpio6: gpio6@1 {
+                                        compatible = "fairchild,74hc595";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <1>;
+                                        registers-number = <4>;
+                                        spi-max-frequency = <100000>;
+                                };
+                        };
+                };
+                apbx@80040000 {
+                        i2c1: i2c@8005a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c1_pins_a>;
+                                status = "okay";
+                        };
+                        usbphy1: usbphy@8007e000 {
+                                status = "okay";
+                        };
+                };
+        };
+        ahb@80080000 {
+                usb1: usb@80090000 {
+                        vbus-supply = <&reg_usb1_vbus>;
+                        pinctrl-0 = <&usbphy1_pins_a>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                reg_usb1_vbus: usb1_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio0 7 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 773c0e84d1fb..a0ad71ca3a44 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -46,11 +46,28 @@
                                wp-gpios = <&gpio0 28 0>;
                        };
+                        ssp2: ssp@80014000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx28-spi";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi2_pins_a>;
+                                status = "okay";
+                                flash: m25p80@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "sst,sst25vf016b";
+                                        spi-max-frequency = <40000000>;
+                                        reg = <0>;
+                                };
+                        };
                        pinctrl@80018000 {
                                pinctrl-names = "default";
                                pinctrl-0 = <&hog_pins_a>;
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
                                                0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */
@@ -128,6 +145,10 @@
                                status = "okay";
                        };
+                        lradc@80050000 {
+                                status = "okay";
+                        };
                        i2c0: i2c@80058000 {
                                pinctrl-names = "default";
                                pinctrl-0 = <&i2c0_pins_a>;
@@ -140,6 +161,12 @@
                                        VDDIO-supply = <&reg_3p3v>;
                                };
+                                at24@51 {
+                                        compatible = "at24,24c32";
+                                        pagesize = <32>;
+                                        reg = <0x51>;
+                                };
                        };
                        pwm: pwm@80064000 {
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 183a3fd2d859..3bab6b00c52d 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -23,6 +23,8 @@
        apb@80000000 {
                apbh@80000000 {
                        gpmi-nand@8000c000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
                                status = "okay";
@@ -61,19 +63,40 @@
                                             &mmc0_cd_cfg
                                             &mmc0_sck_cfg>;
                                bus-width = <8>;
-                                wp-gpios = <&gpio3 10 1>;
+                                wp-gpios = <&gpio3 10 0>;
+                                vmmc-supply = <&reg_vddio_sd0>;
                                status = "okay";
                        };
+                        ssp2: ssp@80014000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx28-spi";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi2_pins_a>;
+                                status = "okay";
+                                flash: m25p80@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "m25p80";
+                                        spi-max-frequency = <40000000>;
+                                        reg = <0>;
+                                };
+                        };
                        pinctrl@80018000 {
                                pinctrl-names = "default";
                                pinctrl-0 = <&hog_pins_a>;
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
+                                                0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
                                                0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
                                                0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
+                                                0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */
+                                                0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */
                                        >;
                                        fsl,drive-strength = <0>;
                                        fsl,voltage = <1>;
@@ -129,6 +152,7 @@
                        i2c0: i2c@80058000 {
                                pinctrl-names = "default";
                                pinctrl-0 = <&i2c0_pins_a>;
+                                clock-frequency = <400000>;
                                status = "okay";
                                sgtl5000: codec@0a {
@@ -151,32 +175,51 @@
                                };
                        };
+                        lradc@80050000 {
+                                status = "okay";
+                        };
                        duart: serial@80074000 {
                                pinctrl-names = "default";
                                pinctrl-0 = <&duart_pins_a>;
                                status = "okay";
                        };
-                        auart0: serial@8006a000 {
+                        usbphy0: usbphy@8007c000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&auart0_2pins_a>;
                                status = "okay";
                        };
-                        auart3: serial@80070000 {
+                        usbphy1: usbphy@8007e000 {
+                                status = "okay";
+                        };
+                        auart0: serial@8006a000 {
                                pinctrl-names = "default";
-                                pinctrl-0 = <&auart3_pins_a>;
+                                pinctrl-0 = <&auart0_2pins_a>;
                                status = "okay";
                        };
                };
        };
        ahb@80080000 {
+                usb0: usb@80080000 {
+                        vbus-supply = <&reg_usb0_vbus>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&usbphy0_pins_a>;
+                        status = "okay";
+                };
+                usb1: usb@80090000 {
+                        vbus-supply = <&reg_usb1_vbus>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&usbphy1_pins_a>;
+                        status = "okay";
+                };
                mac0: ethernet@800f0000 {
                        phy-mode = "rmii";
                        pinctrl-names = "default";
                        pinctrl-0 = <&mac0_pins_a>;
-                        phy-reset-gpios = <&gpio3 11 0>;
                        status = "okay";
                };
@@ -198,6 +241,30 @@
                        regulator-max-microvolt = <3300000>;
                        regulator-always-on;
                };
+                reg_vddio_sd0: vddio-sd0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "vddio-sd0";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio3 28 0>;
+                };
+                reg_usb0_vbus: usb0_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 12 0>;
+                };
+                reg_usb1_vbus: usb1_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 13 0>;
+                };
        };
        sound {
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 62bf767409a6..37be532f0055 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -25,7 +25,7 @@
                                pinctrl-names = "default";
                                pinctrl-0 = <&hog_pins_a>;
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
                                                0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */
@@ -34,6 +34,24 @@
                                        fsl,voltage = <1>;
                                        fsl,pull-up = <0>;
                                };
+                                mac0_pins_gpio: mac0-gpio-mode@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */
+                                                0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */
+                                                0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */
+                                                0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */
+                                                0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */
+                                                0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */
+                                                0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */
+                                                0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */
+                                                0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                        };
                };
@@ -72,8 +90,9 @@
        ahb@80080000 {
                mac0: ethernet@800f0000 {
                        phy-mode = "rmii";
-                        pinctrl-names = "default";
+                        pinctrl-names = "default", "gpio_mode";
                        pinctrl-0 = <&mac0_pins_a>;
+                        pinctrl-1 = <&mac0_pins_gpio>;
                        status = "okay";
                };
        };
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 3fa6d190fab4..e16d63155480 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -27,6 +27,8 @@
                serial2 = &auart2;
                serial3 = &auart3;
                serial4 = &auart4;
+                ethernet0 = &mac0;
+                ethernet1 = &mac1;
        };
        cpus {
@@ -50,7 +52,7 @@
                        ranges;
                        icoll: interrupt-controller@80000000 {
-                                compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
+                                compatible = "fsl,imx28-icoll", "fsl,icoll";
                                interrupt-controller;
                                #interrupt-cells = <1>;
                                reg = <0x80000000 0x2000>;
@@ -65,6 +67,7 @@
                        dma-apbh@80004000 {
                                compatible = "fsl,imx28-dma-apbh";
                                reg = <0x80004000 0x2000>;
+                                clocks = <&clks 25>;
                        };
                        perfmon@80006000 {
@@ -81,34 +84,47 @@
                                reg-names = "gpmi-nand", "bch";
                                interrupts = <88>, <41>;
                                interrupt-names = "gpmi-dma", "bch";
+                                clocks = <&clks 50>;
                                fsl,gpmi-dma-channel = <4>;
                                status = "disabled";
                        };
                        ssp0: ssp@80010000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                reg = <0x80010000 0x2000>;
                                interrupts = <96 82>;
+                                clocks = <&clks 46>;
                                fsl,ssp-dma-channel = <0>;
                                status = "disabled";
                        };
                        ssp1: ssp@80012000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                reg = <0x80012000 0x2000>;
                                interrupts = <97 83>;
+                                clocks = <&clks 47>;
                                fsl,ssp-dma-channel = <1>;
                                status = "disabled";
                        };
                        ssp2: ssp@80014000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                reg = <0x80014000 0x2000>;
                                interrupts = <98 84>;
+                                clocks = <&clks 48>;
                                fsl,ssp-dma-channel = <2>;
                                status = "disabled";
                        };
                        ssp3: ssp@80016000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                reg = <0x80016000 0x2000>;
                                interrupts = <99 85>;
+                                clocks = <&clks 49>;
                                fsl,ssp-dma-channel = <3>;
                                status = "disabled";
                        };
@@ -410,6 +426,28 @@
                                        fsl,pull-up = <1>;
                                };
+                                i2c0_pins_b: i2c0@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
+                                                0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+                                i2c1_pins_a: i2c1@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
+                                                0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
                                saif0_pins_a: saif0@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
@@ -453,6 +491,16 @@
                                        fsl,pull-up = <0>;
                                };
+                                pwm4_pins_a: pwm4@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x31d0 /* MX28_PAD_PWM4__PWM_4 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                                lcdif_24bit_pins_a: lcdif-24bit@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
@@ -507,6 +555,49 @@
                                        fsl,voltage = <1>;
                                        fsl,pull-up = <0>;
                                };
+                                spi2_pins_a: spi2@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
+                                                0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
+                                                0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
+                                                0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+                                usbphy0_pins_a: usbphy0@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                                usbphy0_pins_b: usbphy0@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                                usbphy1_pins_a: usbphy1@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                        };
                        digctl@8001c000 {
@@ -523,6 +614,7 @@
                        dma-apbx@80024000 {
                                compatible = "fsl,imx28-dma-apbx";
                                reg = <0x80024000 0x2000>;
+                                clocks = <&clks 26>;
                        };
                        dcp@80028000 {
@@ -551,6 +643,7 @@
                                compatible = "fsl,imx28-lcdif";
                                reg = <0x80030000 0x2000>;
                                interrupts = <38 86>;
+                                clocks = <&clks 55>;
                                status = "disabled";
                        };
@@ -558,6 +651,8 @@
                                compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
                                reg = <0x80032000 0x2000>;
                                interrupts = <8>;
+                                clocks = <&clks 58>, <&clks 58>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -565,6 +660,8 @@
                                compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
                                reg = <0x80034000 0x2000>;
                                interrupts = <9>;
+                                clocks = <&clks 59>, <&clks 59>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -611,15 +708,17 @@
                        reg = <0x80040000 0x40000>;
                        ranges;
-                        clkctl@80040000 {
+                        clks: clkctrl@80040000 {
+                                compatible = "fsl,imx28-clkctrl";
                                reg = <0x80040000 0x2000>;
-                                status = "disabled";
+                                #clock-cells = <1>;
                        };
                        saif0: saif@80042000 {
                                compatible = "fsl,imx28-saif";
                                reg = <0x80042000 0x2000>;
                                interrupts = <59 80>;
+                                clocks = <&clks 53>;
                                fsl,saif-dma-channel = <4>;
                                status = "disabled";
                        };
@@ -633,12 +732,16 @@
                                compatible = "fsl,imx28-saif";
                                reg = <0x80046000 0x2000>;
                                interrupts = <58 81>;
+                                clocks = <&clks 54>;
                                fsl,saif-dma-channel = <5>;
                                status = "disabled";
                        };
                        lradc@80050000 {
+                                compatible = "fsl,imx28-lradc";
                                reg = <0x80050000 0x2000>;
+                                interrupts = <10 14 15 16 17 18 19
+                                                20 21 22 23 24 25>;
                                status = "disabled";
                        };
@@ -661,6 +764,7 @@
                                reg = <0x80058000 0x2000>;
                                interrupts = <111 68>;
                                clock-frequency = <100000>;
+                                fsl,i2c-dma-channel = <6>;
                                status = "disabled";
                        };
@@ -671,26 +775,30 @@
                                reg = <0x8005a000 0x2000>;
                                interrupts = <110 69>;
                                clock-frequency = <100000>;
+                                fsl,i2c-dma-channel = <7>;
                                status = "disabled";
                        };
                        pwm: pwm@80064000 {
                                compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
                                reg = <0x80064000 0x2000>;
+                                clocks = <&clks 44>;
                                #pwm-cells = <2>;
                                fsl,pwm-number = <8>;
                                status = "disabled";
                        };
                        timrot@80068000 {
+                                compatible = "fsl,imx28-timrot", "fsl,timrot";
                                reg = <0x80068000 0x2000>;
-                                status = "disabled";
+                                interrupts = <48 49 50 51>;
                        };
                        auart0: serial@8006a000 {
                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                reg = <0x8006a000 0x2000>;
                                interrupts = <112 70 71>;
+                                clocks = <&clks 45>;
                                status = "disabled";
                        };
@@ -698,6 +806,7 @@
                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                reg = <0x8006c000 0x2000>;
                                interrupts = <113 72 73>;
+                                clocks = <&clks 45>;
                                status = "disabled";
                        };
@@ -705,6 +814,7 @@
                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                reg = <0x8006e000 0x2000>;
                                interrupts = <114 74 75>;
+                                clocks = <&clks 45>;
                                status = "disabled";
                        };
@@ -712,6 +822,7 @@
                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                reg = <0x80070000 0x2000>;
                                interrupts = <115 76 77>;
+                                clocks = <&clks 45>;
                                status = "disabled";
                        };
@@ -719,6 +830,7 @@
                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                reg = <0x80072000 0x2000>;
                                interrupts = <116 78 79>;
+                                clocks = <&clks 45>;
                                status = "disabled";
                        };
@@ -726,18 +838,22 @@
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x80074000 0x1000>;
                                interrupts = <47>;
+                                clocks = <&clks 45>, <&clks 26>;
+                                clock-names = "uart", "apb_pclk";
                                status = "disabled";
                        };
                        usbphy0: usbphy@8007c000 {
                                compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
                                reg = <0x8007c000 0x2000>;
+                                clocks = <&clks 62>;
                                status = "disabled";
                        };
                        usbphy1: usbphy@8007e000 {
                                compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
                                reg = <0x8007e000 0x2000>;
+                                clocks = <&clks 63>;
                                status = "disabled";
                        };
                };
@@ -754,6 +870,7 @@
                        compatible = "fsl,imx28-usb", "fsl,imx27-usb";
                        reg = <0x80080000 0x10000>;
                        interrupts = <93>;
+                        clocks = <&clks 60>;
                        fsl,usbphy = <&usbphy0>;
                        status = "disabled";
                };
@@ -762,6 +879,7 @@
                        compatible = "fsl,imx28-usb", "fsl,imx27-usb";
                        reg = <0x80090000 0x10000>;
                        interrupts = <92>;
+                        clocks = <&clks 61>;
                        fsl,usbphy = <&usbphy1>;
                        status = "disabled";
                };
@@ -775,6 +893,8 @@
                        compatible = "fsl,imx28-fec";
                        reg = <0x800f0000 0x4000>;
                        interrupts = <101>;
+                        clocks = <&clks 57>, <&clks 57>;
+                        clock-names = "ipg", "ahb";
                        status = "disabled";
                };
@@ -782,6 +902,8 @@
                        compatible = "fsl,imx28-fec";
                        reg = <0x800f4000 0x4000>;
                        interrupts = <102>;
+                        clocks = <&clks 57>, <&clks 57>;
+                        clock-names = "ipg", "ahb";
                        status = "disabled";
                };
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 59d9789e5508..cbd2b1c7487b 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -25,23 +25,31 @@
                aips@70000000 { /* aips-1 */
                        spba@70000000 {
                                esdhc@70004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
                                        fsl,cd-controller;
                                        fsl,wp-controller;
                                        status = "okay";
                                };
                                esdhc@70008000 { /* ESDHC2 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc2_1>;
                                        cd-gpios = <&gpio1 6 0>;
                                        wp-gpios = <&gpio1 5 0>;
                                        status = "okay";
                                };
                                uart3: serial@7000c000 {
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_uart3_1>;
                                        fsl,uart-has-rtscts;
                                        status = "okay";
                                };
                                ecspi@70010000 { /* ECSPI1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
                                        fsl,spi-num-chipselects = <2>;
                                        cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
                                        status = "okay";
@@ -169,31 +177,43 @@
                                };
                        };
-                        wdog@73f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
                        iomuxc@73fa8000 {
-                                compatible = "fsl,imx51-iomuxc-babbage";
+                                pinctrl-names = "default";
-                                reg = <0x73fa8000 0x4000>;
+                                pinctrl-0 = <&pinctrl_hog>;
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        694  0x20d5     /* MX51_PAD_GPIO1_0__SD1_CD */
+                                                        697  0x20d5     /* MX51_PAD_GPIO1_1__SD1_WP */
+                                                        737  0x100      /* MX51_PAD_GPIO1_5__GPIO1_5 */
+                                                        740  0x100      /* MX51_PAD_GPIO1_6__GPIO1_6 */
+                                                        121  0x5        /* MX51_PAD_EIM_A27__GPIO2_21 */
+                                                        402  0x85       /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
+                                                        405  0x85       /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
+                                                >;
+                                        };
+                                };
                        };
                        uart1: serial@73fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_1>;
                                fsl,uart-has-rtscts;
                                status = "okay";
                        };
                        uart2: serial@73fc0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart2_1>;
                                status = "okay";
                        };
                };
                aips@80000000 { /* aips-2 */
-                        sdma@83fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
-                        };
                        i2c@83fc4000 { /* I2C2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2_1>;
                                status = "okay";
                                sgtl5000: codec@0a {
@@ -206,10 +226,14 @@
                        };
                        audmux@83fd0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_audmux_1>;
                                status = "okay";
                        };
                        ethernet@83fec000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_fec_1>;
                                phy-mode = "mii";
                                status = "okay";
                        };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index aba28dc87fc8..75d069fcf897 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -130,6 +130,34 @@
                                };
                        };
+                        usb@73f80000 {
+                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+                                reg = <0x73f80000 0x0200>;
+                                interrupts = <18>;
+                                status = "disabled";
+                        };
+                        usb@73f80200 {
+                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+                                reg = <0x73f80200 0x0200>;
+                                interrupts = <14>;
+                                status = "disabled";
+                        };
+                        usb@73f80400 {
+                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+                                reg = <0x73f80400 0x0200>;
+                                interrupts = <16>;
+                                status = "disabled";
+                        };
+                        usb@73f80600 {
+                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+                                reg = <0x73f80600 0x0200>;
+                                interrupts = <17>;
+                                status = "disabled";
+                        };
                        gpio1: gpio@73f84000 {
                                compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
                                reg = <0x73f84000 0x4000>;
@@ -174,7 +202,6 @@
                                compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
                                reg = <0x73f98000 0x4000>;
                                interrupts = <58>;
-                                status = "disabled";
                        };
                        wdog@73f9c000 { /* WDOG2 */
@@ -184,6 +211,122 @@
                                status = "disabled";
                        };
+                        iomuxc@73fa8000 {
+                                compatible = "fsl,imx51-iomuxc";
+                                reg = <0x73fa8000 0x4000>;
+                                audmux {
+                                        pinctrl_audmux_1: audmuxgrp-1 {
+                                                fsl,pins = <
+                                                        384 0x80000000  /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
+                                                        386 0x80000000  /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
+                                                        389 0x80000000  /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
+                                                        391 0x80000000  /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
+                                                >;
+                                        };
+                                };
+                                fec {
+                                        pinctrl_fec_1: fecgrp-1 {
+                                                fsl,pins = <
+                                                        128 0x80000000  /* MX51_PAD_EIM_EB2__FEC_MDIO */
+                                                        134 0x80000000  /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
+                                                        146 0x80000000  /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
+                                                        152 0x80000000  /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
+                                                        158 0x80000000  /* MX51_PAD_EIM_CS4__FEC_RX_ER */
+                                                        165 0x80000000  /* MX51_PAD_EIM_CS5__FEC_CRS */
+                                                        206 0x80000000  /* MX51_PAD_NANDF_RB2__FEC_COL */
+                                                        213 0x80000000  /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
+                                                        293 0x80000000  /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
+                                                        298 0x80000000  /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
+                                                        225 0x80000000  /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
+                                                        231 0x80000000  /* MX51_PAD_NANDF_CS3__FEC_MDC */
+                                                        237 0x80000000  /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
+                                                        243 0x80000000  /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
+                                                        250 0x80000000  /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
+                                                        255 0x80000000  /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
+                                                        260 0x80000000  /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
+                                                >;
+                                        };
+                                };
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <
+                                                        398 0x185       /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
+                                                        394 0x185       /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
+                                                        409 0x185       /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
+                                                >;
+                                        };
+                                };
+                                esdhc1 {
+                                        pinctrl_esdhc1_1: esdhc1grp-1 {
+                                                fsl,pins = <
+                                                        666 0x400020d5  /* MX51_PAD_SD1_CMD__SD1_CMD */
+                                                        669 0x20d5      /* MX51_PAD_SD1_CLK__SD1_CLK */
+                                                        672 0x20d5      /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
+                                                        678 0x20d5      /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
+                                                        684 0x20d5      /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
+                                                        691 0x20d5      /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
+                                                >;
+                                        };
+                                };
+                                esdhc2 {
+                                        pinctrl_esdhc2_1: esdhc2grp-1 {
+                                                fsl,pins = <
+                                                        704 0x400020d5  /* MX51_PAD_SD2_CMD__SD2_CMD */
+                                                        707 0x20d5      /* MX51_PAD_SD2_CLK__SD2_CLK */
+                                                        710 0x20d5      /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
+                                                        712 0x20d5      /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
+                                                        715 0x20d5      /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
+                                                        719 0x20d5      /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
+                                                >;
+                                        };
+                                };
+                                i2c2 {
+                                        pinctrl_i2c2_1: i2c2grp-1 {
+                                                fsl,pins = <
+                                                        449 0x400001ed  /* MX51_PAD_KEY_COL4__I2C2_SCL */
+                                                        454 0x400001ed  /* MX51_PAD_KEY_COL5__I2C2_SDA */
+                                                >;
+                                        };
+                                };
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp-1 {
+                                                fsl,pins = <
+                                                        413 0x1c5       /* MX51_PAD_UART1_RXD__UART1_RXD */
+                                                        416 0x1c5       /* MX51_PAD_UART1_TXD__UART1_TXD */
+                                                        418 0x1c5       /* MX51_PAD_UART1_RTS__UART1_RTS */
+                                                        420 0x1c5       /* MX51_PAD_UART1_CTS__UART1_CTS */
+                                                >;
+                                        };
+                                };
+                                uart2 {
+                                        pinctrl_uart2_1: uart2grp-1 {
+                                                fsl,pins = <
+                                                        423 0x1c5       /* MX51_PAD_UART2_RXD__UART2_RXD */
+                                                        426 0x1c5       /* MX51_PAD_UART2_TXD__UART2_TXD */
+                                                >;
+                                        };
+                                };
+                                uart3 {
+                                        pinctrl_uart3_1: uart3grp-1 {
+                                                fsl,pins = <
+                                                        54 0x1c5        /* MX51_PAD_EIM_D25__UART3_RXD */
+                                                        59 0x1c5        /* MX51_PAD_EIM_D26__UART3_TXD */
+                                                        65 0x1c5        /* MX51_PAD_EIM_D27__UART3_RTS */
+                                                        49 0x1c5        /* MX51_PAD_EIM_D24__UART3_CTS */
+                                                >;
+                                        };
+                                };
+                        };
                        uart1: serial@73fbc000 {
                                compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                reg = <0x73fbc000 0x4000>;
@@ -219,6 +362,7 @@
                                compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
                                reg = <0x83fb0000 0x4000>;
                                interrupts = <6>;
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
                        };
                        cspi@83fc0000 {
@@ -263,6 +407,13 @@
                                status = "disabled";
                        };
+                        nand@83fdb000 {
+                                compatible = "fsl,imx51-nand";
+                                reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
+                                interrupts = <8>;
+                                status = "disabled";
+                        };
                        ssi3: ssi@83fe8000 {
                                compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                reg = <0x83fe8000 0x4000>;
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index da895e93a999..4be76f223526 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -25,31 +25,66 @@
                aips@50000000 { /* AIPS1 */
                        spba@50000000 {
                                esdhc@50004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_2>;
                                        cd-gpios = <&gpio1 1 0>;
                                        wp-gpios = <&gpio1 9 0>;
                                        status = "okay";
                                };
                        };
-                        wdog@53f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
                        iomuxc@53fa8000 {
-                                compatible = "fsl,imx53-iomuxc-ard";
+                                pinctrl-names = "default";
-                                reg = <0x53fa8000 0x4000>;
+                                pinctrl-0 = <&pinctrl_hog>;
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
+                                                        1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
+                                                        486  0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
+                                                        739  0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
+                                                        218  0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
+                                                        226  0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
+                                                        233  0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
+                                                        241  0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
+                                                        429  0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
+                                                        435  0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
+                                                        441  0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
+                                                        448  0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
+                                                        456  0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
+                                                        464  0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
+                                                        471  0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
+                                                        477  0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
+                                                        492  0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
+                                                        500  0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
+                                                        508  0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
+                                                        516  0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
+                                                        524  0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
+                                                        532  0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
+                                                        540  0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
+                                                        548  0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
+                                                        637  0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
+                                                        642  0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
+                                                        647  0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
+                                                        652  0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
+                                                        657  0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
+                                                        662  0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
+                                                        667  0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
+                                                        611  0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
+                                                        616  0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
+                                                        607  0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
+                                                >;
+                                        };
+                                };
                        };
                        uart1: serial@53fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_2>;
                                status = "okay";
                        };
                };
-                aips@60000000 { /* AIPS2 */
-                        sdma@63fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-                        };
-                };
        };
        eim-cs1@f4000000 {
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 9c798034675e..a124d1e25258 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -25,12 +25,16 @@
                aips@50000000 { /* AIPS1 */
                        spba@50000000 {
                                esdhc@50004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
                                        cd-gpios = <&gpio3 13 0>;
                                        wp-gpios = <&gpio3 14 0>;
                                        status = "okay";
                                };
                                ecspi@50010000 { /* ECSPI1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
                                        fsl,spi-num-chipselects = <2>;
                                        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
                                        status = "okay";
@@ -56,32 +60,45 @@
                                };
                                esdhc@50020000 { /* ESDHC3 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc3_1>;
                                        cd-gpios = <&gpio3 11 0>;
                                        wp-gpios = <&gpio3 12 0>;
                                        status = "okay";
                                };
                        };
-                        wdog@53f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
                        iomuxc@53fa8000 {
-                                compatible = "fsl,imx53-iomuxc-evk";
+                                pinctrl-names = "default";
-                                reg = <0x53fa8000 0x4000>;
+                                pinctrl-0 = <&pinctrl_hog>;
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        424  0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
+                                                        449  0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
+                                                        693  0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
+                                                        697  0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
+                                                        701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+                                                        705  0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
+                                                        868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+                                                        873  0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
+                                                >;
+                                        };
+                                };
                        };
                        uart1: serial@53fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_1>;
                                status = "okay";
                        };
                };
                aips@60000000 { /* AIPS2 */
-                        sdma@63fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-                        };
                        i2c@63fc4000 { /* I2C2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2_1>;
                                status = "okay";
                                pmic: mc13892@08 {
@@ -96,6 +113,8 @@
                        };
                        ethernet@63fec000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_fec_1>;
                                phy-mode = "rmii";
                                phy-reset-gpios = <&gpio7 6 0>;
                                status = "okay";
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 2d803a9a6949..08948af86d1a 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -25,6 +25,8 @@
                aips@50000000 { /* AIPS1 */
                        spba@50000000 {
                                esdhc@50004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
                                        cd-gpios = <&gpio3 13 0>;
                                        status = "okay";
                                };
@@ -35,32 +37,46 @@
                                };
                                esdhc@50020000 { /* ESDHC3 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc3_1>;
                                        cd-gpios = <&gpio3 11 0>;
                                        wp-gpios = <&gpio3 12 0>;
                                        status = "okay";
                                };
                        };
-                        wdog@53f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
                        iomuxc@53fa8000 {
-                                compatible = "fsl,imx53-iomuxc-qsb";
+                                pinctrl-names = "default";
-                                reg = <0x53fa8000 0x4000>;
+                                pinctrl-0 = <&pinctrl_hog>;
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
+                                                        1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
+                                                        982  0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
+                                                        989  0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
+                                                        693  0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
+                                                        697  0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
+                                                        701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+                                                        868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+                                                        873  0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
+                                                >;
+                                        };
+                                };
                        };
                        uart1: serial@53fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_1>;
                                status = "okay";
                        };
                };
                aips@60000000 { /* AIPS2 */
-                        sdma@63fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-                        };
                        i2c@63fc4000 { /* I2C2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2_1>;
                                status = "okay";
                                sgtl5000: codec@0a {
@@ -72,6 +88,8 @@
                        };
                        i2c@63fc8000 { /* I2C1 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1_1>;
                                status = "okay";
                                accelerometer: mma8450@1c {
@@ -158,10 +176,14 @@
                        };
                        audmux@63fd0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_audmux_1>;
                                status = "okay";
                        };
                        ethernet@63fec000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_fec_1>;
                                phy-mode = "rmii";
                                phy-reset-gpios = <&gpio7 6 0>;
                                status = "okay";
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 08091029168e..06c68580c842 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -25,22 +25,30 @@
                aips@50000000 { /* AIPS1 */
                        spba@50000000 {
                                esdhc@50004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
                                        cd-gpios = <&gpio3 13 0>;
                                        wp-gpios = <&gpio4 11 0>;
                                        status = "okay";
                                };
                                esdhc@50008000 { /* ESDHC2 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc2_1>;
                                        non-removable;
                                        status = "okay";
                                };
                                uart3: serial@5000c000 {
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_uart3_1>;
                                        fsl,uart-has-rtscts;
                                        status = "okay";
                                };
                                ecspi@50010000 { /* ECSPI1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
                                        fsl,spi-num-chipselects = <2>;
                                        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
                                        status = "okay";
@@ -72,35 +80,49 @@
                                };
                                esdhc@50020000 { /* ESDHC3 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc3_1>;
                                        non-removable;
                                        status = "okay";
                                };
                        };
-                        wdog@53f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
                        iomuxc@53fa8000 {
-                                compatible = "fsl,imx53-iomuxc-smd";
+                                pinctrl-names = "default";
-                                reg = <0x53fa8000 0x4000>;
+                                pinctrl-0 = <&pinctrl_hog>;
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        982  0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
+                                                        989  0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
+                                                        424  0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
+                                                        701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+                                                        449  0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
+                                                        43   0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
+                                                        868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+                                                >;
+                                        };
+                                };
                        };
                        uart1: serial@53fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_1>;
                                status = "okay";
                        };
                        uart2: serial@53fc0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart2_1>;
                                status = "okay";
                        };
                };
                aips@60000000 { /* AIPS2 */
-                        sdma@63fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-                        };
                        i2c@63fc4000 { /* I2C2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2_1>;
                                status = "okay";
                                codec: sgtl5000@0a {
@@ -120,6 +142,8 @@
                        };
                        i2c@63fc8000 { /* I2C1 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1_1>;
                                status = "okay";
                                accelerometer: mma8450@1c {
@@ -139,6 +163,8 @@
                        };
                        ethernet@63fec000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_fec_1>;
                                phy-mode = "rmii";
                                phy-reset-gpios = <&gpio7 6 0>;
                                status = "okay";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index cd37165edce5..76ebb1ad2675 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -135,6 +135,34 @@
                                };
                        };
+                        usb@53f80000 {
+                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+                                reg = <0x53f80000 0x0200>;
+                                interrupts = <18>;
+                                status = "disabled";
+                        };
+                        usb@53f80200 {
+                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+                                reg = <0x53f80200 0x0200>;
+                                interrupts = <14>;
+                                status = "disabled";
+                        };
+                        usb@53f80400 {
+                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+                                reg = <0x53f80400 0x0200>;
+                                interrupts = <16>;
+                                status = "disabled";
+                        };
+                        usb@53f80600 {
+                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+                                reg = <0x53f80600 0x0200>;
+                                interrupts = <17>;
+                                status = "disabled";
+                        };
                        gpio1: gpio@53f84000 {
                                compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                reg = <0x53f84000 0x4000>;
@@ -179,7 +207,6 @@
                                compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
                                reg = <0x53f98000 0x4000>;
                                interrupts = <58>;
-                                status = "disabled";
                        };
                        wdog@53f9c000 { /* WDOG2 */
@@ -189,6 +216,161 @@
                                status = "disabled";
                        };
+                        iomuxc@53fa8000 {
+                                compatible = "fsl,imx53-iomuxc";
+                                reg = <0x53fa8000 0x4000>;
+                                audmux {
+                                        pinctrl_audmux_1: audmuxgrp-1 {
+                                                fsl,pins = <
+                                                        10 0x80000000   /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
+                                                        17 0x80000000   /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
+                                                        23 0x80000000   /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
+                                                        30 0x80000000   /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
+                                                >;
+                                        };
+                                };
+                                fec {
+                                        pinctrl_fec_1: fecgrp-1 {
+                                                fsl,pins = <
+                                                        820 0x80000000  /* MX53_PAD_FEC_MDC__FEC_MDC */
+                                                        779 0x80000000  /* MX53_PAD_FEC_MDIO__FEC_MDIO */
+                                                        786 0x80000000  /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
+                                                        791 0x80000000  /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
+                                                        796 0x80000000  /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
+                                                        799 0x80000000  /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
+                                                        804 0x80000000  /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
+                                                        808 0x80000000  /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
+                                                        811 0x80000000  /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
+                                                        816 0x80000000  /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
+                                                >;
+                                        };
+                                };
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <
+                                                        433 0x80000000  /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
+                                                        439 0x80000000  /* MX53_PAD_EIM_D17__ECSPI1_MISO */
+                                                        445 0x80000000  /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
+                                                >;
+                                        };
+                                };
+                                esdhc1 {
+                                        pinctrl_esdhc1_1: esdhc1grp-1 {
+                                                fsl,pins = <
+                                                        995  0x1d5      /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
+                                                        1000 0x1d5      /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
+                                                        1010 0x1d5      /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
+                                                        1024 0x1d5      /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
+                                                        1005 0x1d5      /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
+                                                        1018 0x1d5      /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
+                                                >;
+                                        };
+                                        pinctrl_esdhc1_2: esdhc1grp-2 {
+                                                fsl,pins = <
+                                                        995  0x1d5      /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
+                                                        1000 0x1d5      /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
+                                                        1010 0x1d5      /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
+                                                        1024 0x1d5      /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
+                                                        941  0x1d5      /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
+                                                        948  0x1d5      /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
+                                                        955  0x1d5      /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
+                                                        962  0x1d5      /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
+                                                        1005 0x1d5      /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
+                                                        1018 0x1d5      /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
+                                                >;
+                                        };
+                                };
+                                esdhc2 {
+                                        pinctrl_esdhc2_1: esdhc2grp-1 {
+                                                fsl,pins = <
+                                                        1038 0x1d5      /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
+                                                        1032 0x1d5      /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
+                                                        1062 0x1d5      /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
+                                                        1056 0x1d5      /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
+                                                        1050 0x1d5      /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
+                                                        1044 0x1d5      /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
+                                                >;
+                                        };
+                                };
+                                esdhc3 {
+                                        pinctrl_esdhc3_1: esdhc3grp-1 {
+                                                fsl,pins = <
+                                                        943 0x1d5       /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
+                                                        950 0x1d5       /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
+                                                        957 0x1d5       /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
+                                                        964 0x1d5       /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
+                                                        893 0x1d5       /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
+                                                        900 0x1d5       /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
+                                                        906 0x1d5       /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
+                                                        912 0x1d5       /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
+                                                        857 0x1d5       /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
+                                                        863 0x1d5       /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
+                                                >;
+                                        };
+                                };
+                                i2c1 {
+                                        pinctrl_i2c1_1: i2c1grp-1 {
+                                                fsl,pins = <
+                                                        333 0xc0000000  /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
+                                                        341 0xc0000000  /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
+                                                >;
+                                        };
+                                };
+                                i2c2 {
+                                        pinctrl_i2c2_1: i2c2grp-1 {
+                                                fsl,pins = <
+                                                        61 0xc0000000   /* MX53_PAD_KEY_ROW3__I2C2_SDA */
+                                                        53 0xc0000000   /* MX53_PAD_KEY_COL3__I2C2_SCL */
+                                                >;
+                                        };
+                                };
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp-1 {
+                                                fsl,pins = <
+                                                        346 0x1c5       /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
+                                                        354 0x1c5       /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
+                                                >;
+                                        };
+                                        pinctrl_uart1_2: uart1grp-2 {
+                                                fsl,pins = <
+                                                        828 0x1c5       /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
+                                                        832 0x1c5       /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
+                                                >;
+                                        };
+                                };
+                                uart2 {
+                                        pinctrl_uart2_1: uart2grp-1 {
+                                                fsl,pins = <
+                                                        841 0x1c5       /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
+                                                        836 0x1c5       /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
+                                                >;
+                                        };
+                                };
+                                uart3 {
+                                        pinctrl_uart3_1: uart3grp-1 {
+                                                fsl,pins = <
+                                                        884 0x1c5       /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
+                                                        888 0x1c5       /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
+                                                        875 0x1c5       /* MX53_PAD_PATA_DA_1__UART3_CTS */
+                                                        880 0x1c5       /* MX53_PAD_PATA_DA_2__UART3_RTS */
+                                                >;
+                                        };
+                                };
+                        };
                        uart1: serial@53fbc000 {
                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                reg = <0x53fbc000 0x4000>;
@@ -203,6 +385,20 @@
                                status = "disabled";
                        };
+                        can1: can@53fc8000 {
+                                compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+                                reg = <0x53fc8000 0x4000>;
+                                interrupts = <82>;
+                                status = "disabled";
+                        };
+                        can2: can@53fcc000 {
+                                compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+                                reg = <0x53fcc000 0x4000>;
+                                interrupts = <83>;
+                                status = "disabled";
+                        };
                        gpio5: gpio@53fdc000 {
                                compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                reg = <0x53fdc000 0x4000>;
@@ -277,6 +473,7 @@
                                compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
                                reg = <0x63fb0000 0x4000>;
                                interrupts = <6>;
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
                        };
                        cspi@63fc0000 {
@@ -321,6 +518,13 @@
                                status = "disabled";
                        };
+                        nand@63fdb000 {
+                                compatible = "fsl,imx53-nand";
+                                reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
+                                interrupts = <8>;
+                                status = "disabled";
+                        };
                        ssi3: ssi@63fe8000 {
                                compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
                                reg = <0x63fe8000 0x4000>;
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index d792581672cc..15df4c105e89 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -28,8 +28,27 @@
                        status = "disabled"; /* gpmi nand conflicts with SD */
                };
+                aips-bus@02000000 { /* AIPS1 */
+                        iomuxc@020e0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        176  0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
+                                                        1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
+                                                        1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
+                                                >;
+                                        };
+                                };
+                        };
+                };
                aips-bus@02100000 { /* AIPS2 */
                        ethernet@02188000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_enet_2>;
                                phy-mode = "rgmii";
                                status = "okay";
                        };
@@ -52,6 +71,8 @@
                        };
                        uart4: serial@021f0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart4_1>;
                                status = "okay";
                        };
                };
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 72f30f3e6171..d152328285a1 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -46,15 +46,20 @@
                        iomuxc@020e0000 {
                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_gpio_hog>;
+                                pinctrl-0 = <&pinctrl_hog>;
-                                gpios {
+                                hog {
-                                        pinctrl_gpio_hog: gpiohog {
+                                        pinctrl_hog: hoggrp {
                                                fsl,pins = <
-                                                           144  0x80000000      /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
+                                                        1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
-                                                           121  0x80000000      /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+                                                        1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
-                                                           953  0x80000000      /* MX6Q_PAD_GPIO_0__CCM_CLKO */
+                                                        121  0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
-                                                           >;
+                                                        144  0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
+                                                        152  0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
+                                                        1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
+                                                        1270 0x1f0b0    /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
+                                                        953  0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
+                                                >;
                                        };
                                };
                        };
@@ -63,6 +68,9 @@
                aips-bus@02100000 { /* AIPS2 */
                        usb@02184000 { /* USB OTG */
                                vbus-supply = <&reg_usb_otg_vbus>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usbotg_1>;
+                                disable-over-current;
                                status = "okay";
                        };
@@ -71,12 +79,16 @@
                        };
                        ethernet@02188000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_enet_1>;
                                phy-mode = "rgmii";
                                phy-reset-gpios = <&gpio3 23 0>;
                                status = "okay";
                        };
                        usdhc@02198000 { /* uSDHC3 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usdhc3_2>;
                                cd-gpios = <&gpio7 0 0>;
                                wp-gpios = <&gpio7 1 0>;
                                vmmc-supply = <&reg_3p3v>;
@@ -84,6 +96,8 @@
                        };
                        usdhc@0219c000 { /* uSDHC4 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usdhc4_2>;
                                cd-gpios = <&gpio2 6 0>;
                                wp-gpios = <&gpio2 7 0>;
                                vmmc-supply = <&reg_3p3v>;
@@ -99,7 +113,7 @@
                        uart2: serial@021e8000 {
                                status = "okay";
                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_serial2_1>;
+                                pinctrl-0 = <&pinctrl_uart2_1>;
                        };
                        i2c@021a0000 { /* I2C1 */
@@ -111,6 +125,7 @@
                                codec: sgtl5000@0a {
                                        compatible = "fsl,sgtl5000";
                                        reg = <0x0a>;
+                                        clocks = <&clks 169>;
                                        VDDA-supply = <&reg_2p5v>;
                                        VDDIO-supply = <&reg_3p3v>;
                                };
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 07509a181178..e596c28c214d 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -22,28 +22,51 @@
        };
        soc {
                aips-bus@02000000 { /* AIPS1 */
                        spba-bus@02000000 {
                                uart1: serial@02020000 {
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_uart1_1>;
                                        status = "okay";
                                };
                        };
+                        iomuxc@020e0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
+                                                        1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
+                                                        1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
+                                                        1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
+                                                >;
+                                        };
+                                };
+                        };
                };
                aips-bus@02100000 { /* AIPS2 */
                        ethernet@02188000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_enet_1>;
                                phy-mode = "rgmii";
                                status = "okay";
                        };
                        usdhc@02194000 { /* uSDHC2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usdhc2_1>;
                                cd-gpios = <&gpio2 2 0>;
                                wp-gpios = <&gpio2 3 0>;
                                status = "okay";
                        };
                        usdhc@02198000 { /* uSDHC3 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usdhc3_1>;
                                cd-gpios = <&gpio2 0 0>;
                                wp-gpios = <&gpio2 1 0>;
                                status = "okay";
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079f71a9..f3990b04fecf 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -97,18 +97,23 @@
                dma-apbh@00110000 {
                        compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
                        reg = <0x00110000 0x2000>;
+                        clocks = <&clks 106>;
                };
                gpmi-nand@00112000 {
-                       compatible = "fsl,imx6q-gpmi-nand";
+                        compatible = "fsl,imx6q-gpmi-nand";
-                       #address-cells = <1>;
+                        #address-cells = <1>;
-                       #size-cells = <1>;
+                        #size-cells = <1>;
-                       reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+                        reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
-                       reg-names = "gpmi-nand", "bch";
+                        reg-names = "gpmi-nand", "bch";
-                       interrupts = <0 13 0x04>, <0 15 0x04>;
+                        interrupts = <0 13 0x04>, <0 15 0x04>;
-                       interrupt-names = "gpmi-dma", "bch";
+                        interrupt-names = "gpmi-dma", "bch";
-                       fsl,gpmi-dma-channel = <0>;
+                        clocks = <&clks 152>, <&clks 153>, <&clks 151>,
-                       status = "disabled";
+                                 <&clks 150>, <&clks 149>;
+                        clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+                                      "gpmi_bch_apb", "per1_bch";
+                        fsl,gpmi-dma-channel = <0>;
+                        status = "disabled";
                };
                timer@00a00600 {
@@ -150,6 +155,8 @@
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x02008000 0x4000>;
                                        interrupts = <0 31 0x04>;
+                                        clocks = <&clks 112>, <&clks 112>;
+                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
@@ -159,6 +166,8 @@
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x0200c000 0x4000>;
                                        interrupts = <0 32 0x04>;
+                                        clocks = <&clks 113>, <&clks 113>;
+                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
@@ -168,6 +177,8 @@
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x02010000 0x4000>;
                                        interrupts = <0 33 0x04>;
+                                        clocks = <&clks 114>, <&clks 114>;
+                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
@@ -177,6 +188,8 @@
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x02014000 0x4000>;
                                        interrupts = <0 34 0x04>;
+                                        clocks = <&clks 115>, <&clks 115>;
+                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
@@ -186,6 +199,8 @@
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x02018000 0x4000>;
                                        interrupts = <0 35 0x04>;
+                                        clocks = <&clks 116>, <&clks 116>;
+                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
@@ -193,6 +208,8 @@
                                        compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                        reg = <0x02020000 0x4000>;
                                        interrupts = <0 26 0x04>;
+                                        clocks = <&clks 160>, <&clks 161>;
+                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
@@ -205,6 +222,7 @@
                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
                                        reg = <0x02028000 0x4000>;
                                        interrupts = <0 46 0x04>;
+                                        clocks = <&clks 178>;
                                        fsl,fifo-depth = <15>;
                                        fsl,ssi-dma-events = <38 37>;
                                        status = "disabled";
@@ -214,6 +232,7 @@
                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
                                        reg = <0x0202c000 0x4000>;
                                        interrupts = <0 47 0x04>;
+                                        clocks = <&clks 179>;
                                        fsl,fifo-depth = <15>;
                                        fsl,ssi-dma-events = <42 41>;
                                        status = "disabled";
@@ -223,6 +242,7 @@
                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
                                        reg = <0x02030000 0x4000>;
                                        interrupts = <0 48 0x04>;
+                                        clocks = <&clks 180>;
                                        fsl,fifo-depth = <15>;
                                        fsl,ssi-dma-events = <46 45>;
                                        status = "disabled";
@@ -362,24 +382,26 @@
                                compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
                                reg = <0x020bc000 0x4000>;
                                interrupts = <0 80 0x04>;
-                                status = "disabled";
+                                clocks = <&clks 0>;
                        };
                        wdog@020c0000 { /* WDOG2 */
                                compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
                                reg = <0x020c0000 0x4000>;
                                interrupts = <0 81 0x04>;
+                                clocks = <&clks 0>;
                                status = "disabled";
                        };
-                        ccm@020c4000 {
+                        clks: ccm@020c4000 {
                                compatible = "fsl,imx6q-ccm";
                                reg = <0x020c4000 0x4000>;
                                interrupts = <0 87 0x04 0 88 0x04>;
+                                #clock-cells = <1>;
                        };
-                        anatop@020c8000 {
+                        anatop: anatop@020c8000 {
-                                compatible = "fsl,imx6q-anatop";
+                                compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
                                reg = <0x020c8000 0x1000>;
                                interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
@@ -472,12 +494,14 @@
                                compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
                                reg = <0x020c9000 0x1000>;
                                interrupts = <0 44 0x04>;
+                                clocks = <&clks 182>;
                        };
                        usbphy2: usbphy@020ca000 {
                                compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
                                reg = <0x020ca000 0x1000>;
                                interrupts = <0 45 0x04>;
+                                clocks = <&clks 183>;
                        };
                        snvs@020cc000 {
@@ -507,6 +531,11 @@
                                interrupts = <0 89 0x04 0 90 0x04>;
                        };
+                        gpr: iomuxc-gpr@020e0000 {
+                                compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+                                reg = <0x020e0000 0x38>;
+                        };
                        iomuxc@020e0000 {
                                compatible = "fsl,imx6q-iomuxc";
                                reg = <0x020e0000 0x4000>;
@@ -514,86 +543,207 @@
                                /* shared pinctrl settings */
                                audmux {
                                        pinctrl_audmux_1: audmux-1 {
-                                                fsl,pins = <18   0x80000000     /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
+                                                fsl,pins = <
-                                                            1586 0x80000000     /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
+                                                        18   0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
-                                                            11   0x80000000     /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
+                                                        1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
-                                                            3    0x80000000>;   /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+                                                        11   0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
+                                                        3    0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+                                                >;
+                                        };
+                                };
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <
+                                                        101 0x100b1     /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
+                                                        109 0x100b1     /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
+                                                        94  0x100b1     /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+                                                >;
+                                        };
+                                };
+                                enet {
+                                        pinctrl_enet_1: enetgrp-1 {
+                                                fsl,pins = <
+                                                        695 0x1b0b0     /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
+                                                        756 0x1b0b0     /* MX6Q_PAD_ENET_MDC__ENET_MDC */
+                                                        24  0x1b0b0     /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+                                                        30  0x1b0b0     /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+                                                        34  0x1b0b0     /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+                                                        39  0x1b0b0     /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+                                                        44  0x1b0b0     /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+                                                        56  0x1b0b0     /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+                                                        702 0x1b0b0     /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+                                                        74  0x1b0b0     /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+                                                        52  0x1b0b0     /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+                                                        61  0x1b0b0     /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+                                                        66  0x1b0b0     /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+                                                        70  0x1b0b0     /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+                                                        48  0x1b0b0     /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+                                                >;
+                                        };
+                                        pinctrl_enet_2: enetgrp-2 {
+                                                fsl,pins = <
+                                                        890 0x1b0b0     /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
+                                                        909 0x1b0b0     /* MX6Q_PAD_KEY_COL2__ENET_MDC */
+                                                        24  0x1b0b0     /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+                                                        30  0x1b0b0     /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+                                                        34  0x1b0b0     /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+                                                        39  0x1b0b0     /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+                                                        44  0x1b0b0     /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+                                                        56  0x1b0b0     /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+                                                        702 0x1b0b0     /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+                                                        74  0x1b0b0     /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+                                                        52  0x1b0b0     /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+                                                        61  0x1b0b0     /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+                                                        66  0x1b0b0     /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+                                                        70  0x1b0b0     /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+                                                        48  0x1b0b0     /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+                                                >;
                                        };
                                };
                                gpmi-nand {
                                        pinctrl_gpmi_nand_1: gpmi-nand-1 {
-                                                fsl,pins = <1328 0xb0b1         /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
+                                                fsl,pins = <
-                                                            1336 0xb0b1         /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
+                                                        1328 0xb0b1     /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
-                                                            1344 0xb0b1         /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
+                                                        1336 0xb0b1     /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
-                                                            1352 0xb000         /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
+                                                        1344 0xb0b1     /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
-                                                            1360 0xb0b1         /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
+                                                        1352 0xb000     /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
-                                                            1365 0xb0b1         /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
+                                                        1360 0xb0b1     /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
-                                                            1371 0xb0b1         /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
+                                                        1365 0xb0b1     /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
-                                                            1378 0xb0b1         /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
+                                                        1371 0xb0b1     /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
-                                                            1387 0xb0b1         /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
+                                                        1378 0xb0b1     /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
-                                                            1393 0xb0b1         /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
+                                                        1387 0xb0b1     /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
-                                                            1397 0xb0b1         /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
+                                                        1393 0xb0b1     /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
-                                                            1405 0xb0b1         /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
+                                                        1397 0xb0b1     /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
-                                                            1413 0xb0b1         /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
+                                                        1405 0xb0b1     /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
-                                                            1421 0xb0b1         /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
+                                                        1413 0xb0b1     /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
-                                                            1429 0xb0b1         /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
+                                                        1421 0xb0b1     /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
-                                                            1437 0xb0b1         /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
+                                                        1429 0xb0b1     /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
-                                                            1445 0xb0b1         /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
+                                                        1437 0xb0b1     /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
-                                                            1453 0xb0b1         /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
+                                                        1445 0xb0b1     /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
-                                                            1463 0x00b1>;       /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+                                                        1453 0xb0b1     /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
+                                                        1463 0x00b1     /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+                                                >;
                                        };
                                };
                                i2c1 {
                                        pinctrl_i2c1_1: i2c1grp-1 {
-                                                fsl,pins = <137 0x4001b8b1      /* MX6Q_PAD_EIM_D21__I2C1_SCL */
+                                                fsl,pins = <
-                                                            196 0x4001b8b1>;    /* MX6Q_PAD_EIM_D28__I2C1_SDA */
+                                                        137 0x4001b8b1  /* MX6Q_PAD_EIM_D21__I2C1_SCL */
+                                                        196 0x4001b8b1  /* MX6Q_PAD_EIM_D28__I2C1_SDA */
+                                                >;
+                                        };
+                                };
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp-1 {
+                                                fsl,pins = <
+                                                        1140 0x1b0b1    /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
+                                                        1148 0x1b0b1    /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
+                                                >;
                                        };
                                };
-                                serial2 {
+                                uart2 {
-                                        pinctrl_serial2_1: serial2grp-1 {
+                                        pinctrl_uart2_1: uart2grp-1 {
-                                                fsl,pins = <183 0x1b0b1         /* MX6Q_PAD_EIM_D26__UART2_TXD */
+                                                fsl,pins = <
-                                                            191 0x1b0b1>;       /* MX6Q_PAD_EIM_D27__UART2_RXD */
+                                                        183 0x1b0b1     /* MX6Q_PAD_EIM_D26__UART2_TXD */
+                                                        191 0x1b0b1     /* MX6Q_PAD_EIM_D27__UART2_RXD */
+                                                >;
+                                        };
+                                };
+                                uart4 {
+                                        pinctrl_uart4_1: uart4grp-1 {
+                                                fsl,pins = <
+                                                        877 0x1b0b1     /* MX6Q_PAD_KEY_COL0__UART4_TXD */
+                                                        885 0x1b0b1     /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
+                                                >;
+                                        };
+                                };
+                                usbotg {
+                                        pinctrl_usbotg_1: usbotggrp-1 {
+                                                fsl,pins = <
+                                                        1592 0x17059    /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
+                                                >;
+                                        };
+                                };
+                                usdhc2 {
+                                        pinctrl_usdhc2_1: usdhc2grp-1 {
+                                                fsl,pins = <
+                                                        1577 0x17059    /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
+                                                        1569 0x10059    /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
+                                                        16   0x17059    /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
+                                                        0    0x17059    /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
+                                                        8    0x17059    /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
+                                                        1583 0x17059    /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
+                                                        1430 0x17059    /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
+                                                        1438 0x17059    /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
+                                                        1446 0x17059    /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
+                                                        1454 0x17059    /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
+                                                >;
                                        };
                                };
                                usdhc3 {
                                        pinctrl_usdhc3_1: usdhc3grp-1 {
-                                                fsl,pins = <1273 0x17059        /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+                                                fsl,pins = <
-                                                            1281 0x10059        /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
+                                                        1273 0x17059    /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
-                                                            1289 0x17059        /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+                                                        1281 0x10059    /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
-                                                            1297 0x17059        /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+                                                        1289 0x17059    /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
-                                                            1305 0x17059        /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+                                                        1297 0x17059    /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
-                                                            1312 0x17059        /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+                                                        1305 0x17059    /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
-                                                            1265 0x17059        /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
+                                                        1312 0x17059    /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
-                                                            1257 0x17059        /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
+                                                        1265 0x17059    /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
-                                                            1249 0x17059        /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
+                                                        1257 0x17059    /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
-                                                            1241 0x17059>;      /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+                                                        1249 0x17059    /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
+                                                        1241 0x17059    /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+                                                >;
+                                        };
+                                        pinctrl_usdhc3_2: usdhc3grp-2 {
+                                                fsl,pins = <
+                                                        1273 0x17059    /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+                                                        1281 0x10059    /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
+                                                        1289 0x17059    /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+                                                        1297 0x17059    /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+                                                        1305 0x17059    /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+                                                        1312 0x17059    /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+                                                >;
                                        };
                                };
                                usdhc4 {
                                        pinctrl_usdhc4_1: usdhc4grp-1 {
-                                                fsl,pins = <1386 0x17059        /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+                                                fsl,pins = <
-                                                            1392 0x10059        /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+                                                        1386 0x17059    /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
-                                                            1462 0x17059        /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+                                                        1392 0x10059    /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
-                                                            1470 0x17059        /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+                                                        1462 0x17059    /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
-                                                            1478 0x17059        /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+                                                        1470 0x17059    /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
-                                                            1486 0x17059        /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+                                                        1478 0x17059    /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
-                                                            1493 0x17059        /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
+                                                        1486 0x17059    /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
-                                                            1501 0x17059        /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
+                                                        1493 0x17059    /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
-                                                            1509 0x17059        /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+                                                        1501 0x17059    /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
-                                                            1517 0x17059>;      /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+                                                        1509 0x17059    /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+                                                        1517 0x17059    /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+                                                >;
                                        };
-                                };
-                                ecspi1 {
+                                        pinctrl_usdhc4_2: usdhc4grp-2 {
-                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <
-                                                fsl,pins = <101 0x100b1         /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
+                                                        1386 0x17059    /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
-                                                            109 0x100b1         /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
+                                                        1392 0x10059    /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
-                                                            94  0x100b1>;       /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+                                                        1462 0x17059    /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+                                                        1470 0x17059    /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+                                                        1478 0x17059    /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+                                                        1486 0x17059    /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+                                                >;
                                        };
                                };
                        };
@@ -612,6 +762,9 @@
                                compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
                                reg = <0x020ec000 0x4000>;
                                interrupts = <0 2 0x04>;
+                                clocks = <&clks 155>, <&clks 155>;
+                                clock-names = "ipg", "ahb";
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
                        };
                };
@@ -635,7 +788,9 @@
                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                reg = <0x02184000 0x200>;
                                interrupts = <0 43 0x04>;
+                                clocks = <&clks 162>;
                                fsl,usbphy = <&usbphy1>;
+                                fsl,usbmisc = <&usbmisc 0>;
                                status = "disabled";
                        };
@@ -643,7 +798,9 @@
                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                reg = <0x02184200 0x200>;
                                interrupts = <0 40 0x04>;
+                                clocks = <&clks 162>;
                                fsl,usbphy = <&usbphy2>;
+                                fsl,usbmisc = <&usbmisc 1>;
                                status = "disabled";
                        };
@@ -651,6 +808,8 @@
                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                reg = <0x02184400 0x200>;
                                interrupts = <0 41 0x04>;
+                                clocks = <&clks 162>;
+                                fsl,usbmisc = <&usbmisc 2>;
                                status = "disabled";
                        };
@@ -658,13 +817,24 @@
                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                reg = <0x02184600 0x200>;
                                interrupts = <0 42 0x04>;
+                                clocks = <&clks 162>;
+                                fsl,usbmisc = <&usbmisc 3>;
                                status = "disabled";
                        };
+                        usbmisc: usbmisc@02184800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx6q-usbmisc";
+                                reg = <0x02184800 0x200>;
+                                clocks = <&clks 162>;
+                        };
                        ethernet@02188000 {
                                compatible = "fsl,imx6q-fec";
                                reg = <0x02188000 0x4000>;
                                interrupts = <0 118 0x04 0 119 0x04>;
+                                clocks = <&clks 117>, <&clks 117>;
+                                clock-names = "ipg", "ahb";
                                status = "disabled";
                        };
@@ -677,6 +847,8 @@
                                compatible = "fsl,imx6q-usdhc";
                                reg = <0x02190000 0x4000>;
                                interrupts = <0 22 0x04>;
+                                clocks = <&clks 163>, <&clks 163>, <&clks 163>;
+                                clock-names = "ipg", "ahb", "per";
                                status = "disabled";
                        };
@@ -684,6 +856,8 @@
                                compatible = "fsl,imx6q-usdhc";
                                reg = <0x02194000 0x4000>;
                                interrupts = <0 23 0x04>;
+                                clocks = <&clks 164>, <&clks 164>, <&clks 164>;
+                                clock-names = "ipg", "ahb", "per";
                                status = "disabled";
                        };
@@ -691,6 +865,8 @@
                                compatible = "fsl,imx6q-usdhc";
                                reg = <0x02198000 0x4000>;
                                interrupts = <0 24 0x04>;
+                                clocks = <&clks 165>, <&clks 165>, <&clks 165>;
+                                clock-names = "ipg", "ahb", "per";
                                status = "disabled";
                        };
@@ -698,6 +874,8 @@
                                compatible = "fsl,imx6q-usdhc";
                                reg = <0x0219c000 0x4000>;
                                interrupts = <0 25 0x04>;
+                                clocks = <&clks 166>, <&clks 166>, <&clks 166>;
+                                clock-names = "ipg", "ahb", "per";
                                status = "disabled";
                        };
@@ -707,6 +885,7 @@
                                compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
                                reg = <0x021a0000 0x4000>;
                                interrupts = <0 36 0x04>;
+                                clocks = <&clks 125>;
                                status = "disabled";
                        };
@@ -716,6 +895,7 @@
                                compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
                                reg = <0x021a4000 0x4000>;
                                interrupts = <0 37 0x04>;
+                                clocks = <&clks 126>;
                                status = "disabled";
                        };
@@ -725,6 +905,7 @@
                                compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
                                reg = <0x021a8000 0x4000>;
                                interrupts = <0 38 0x04>;
+                                clocks = <&clks 127>;
                                status = "disabled";
                        };
@@ -788,6 +969,8 @@
                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021e8000 0x4000>;
                                interrupts = <0 27 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -795,6 +978,8 @@
                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021ec000 0x4000>;
                                interrupts = <0 28 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -802,6 +987,8 @@
                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021f0000 0x4000>;
                                interrupts = <0 29 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -809,6 +996,8 @@
                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021f4000 0x4000>;
                                interrupts = <0 30 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
                };
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi
new file mode 100644
index 000000000000..813b91d7bea2
--- /dev/null
+++ b/arch/arm/boot/dts/integrator.dtsi
@@ -0,0 +1,76 @@
+/*
+ * SoC core Device Tree for the ARM Integrator platforms
+ */
+/include/ "skeleton.dtsi"
+/ {
+        timer@13000000 {
+                reg = <0x13000000 0x100>;
+                interrupt-parent = <&pic>;
+                interrupts = <5>;
+        };
+        timer@13000100 {
+                reg = <0x13000100 0x100>;
+                interrupt-parent = <&pic>;
+                interrupts = <6>;
+        };
+        timer@13000200 {
+                reg = <0x13000200 0x100>;
+                interrupt-parent = <&pic>;
+                interrupts = <7>;
+        };
+        pic@14000000 {
+                compatible = "arm,versatile-fpga-irq";
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                reg = <0x14000000 0x100>;
+                clear-mask = <0xffffffff>;
+        };
+        flash@24000000 {
+                compatible = "cfi-flash";
+                reg = <0x24000000 0x02000000>;
+        };
+        fpga {
+                compatible = "arm,amba-bus", "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                interrupt-parent = <&pic>;
+                /*
+                 * These PrimeCells are in the same locations and using the
+                 * same interrupts in all Integrators, however the silicon
+                 * version deployed is different.
+                 */
+                rtc@15000000 {
+                        reg = <0x15000000 0x1000>;
+                        interrupts = <8>;
+                };
+                uart@16000000 {
+                        reg = <0x16000000 0x1000>;
+                        interrupts = <1>;
+                };
+                uart@17000000 {
+                        reg = <0x17000000 0x1000>;
+                        interrupts = <2>;
+                };
+                kmi@18000000 {
+                        reg = <0x18000000 0x1000>;
+                        interrupts = <3>;
+                };
+                kmi@19000000 {
+                        reg = <0x19000000 0x1000>;
+                        interrupts = <4>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
new file mode 100644
index 000000000000..61767757b50a
--- /dev/null
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -0,0 +1,68 @@
+/*
+ * Device Tree for the ARM Integrator/AP platform
+ */
+/dts-v1/;
+/include/ "integrator.dtsi"
+/ {
+        model = "ARM Integrator/AP";
+        compatible = "arm,integrator-ap";
+        aliases {
+                arm,timer-primary = &timer2;
+                arm,timer-secondary = &timer1;
+        };
+        chosen {
+                bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
+        };
+        timer0: timer@13000000 {
+                compatible = "arm,integrator-timer";
+        };
+        timer1: timer@13000100 {
+                compatible = "arm,integrator-timer";
+        };
+        timer2: timer@13000200 {
+                compatible = "arm,integrator-timer";
+        };
+        pic: pic@14000000 {
+                valid-mask = <0x003fffff>;
+        };
+        fpga {
+                /*
+                 * The Integator/AP predates the idea to have magic numbers
+                 * identifying the PrimeCell in hardware, thus we have to
+                 * supply these from the device tree.
+                 */
+                rtc: rtc@15000000 {
+                        compatible = "arm,pl030", "arm,primecell";
+                        arm,primecell-periphid = <0x00041030>;
+                };
+                uart0: uart@16000000 {
+                        compatible = "arm,pl010", "arm,primecell";
+                        arm,primecell-periphid = <0x00041010>;
+                };
+                uart1: uart@17000000 {
+                        compatible = "arm,pl010", "arm,primecell";
+                        arm,primecell-periphid = <0x00041010>;
+                };
+                kmi0: kmi@18000000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                        arm,primecell-periphid = <0x00041050>;
+                };
+                kmi1: kmi@19000000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                        arm,primecell-periphid = <0x00041050>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
new file mode 100644
index 000000000000..2dd5e4e48481
--- /dev/null
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -0,0 +1,110 @@
+/*
+ * Device Tree for the ARM Integrator/CP platform
+ */
+/dts-v1/;
+/include/ "integrator.dtsi"
+/ {
+        model = "ARM Integrator/CP";
+        compatible = "arm,integrator-cp";
+        aliases {
+                arm,timer-primary = &timer2;
+                arm,timer-secondary = &timer1;
+        };
+        chosen {
+                bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
+        };
+        timer0: timer@13000000 {
+                compatible = "arm,sp804", "arm,primecell";
+        };
+        timer1: timer@13000100 {
+                compatible = "arm,sp804", "arm,primecell";
+        };
+        timer2: timer@13000200 {
+                compatible = "arm,sp804", "arm,primecell";
+        };
+        pic: pic@14000000 {
+                valid-mask = <0x1fc003ff>;
+        };
+        cic: cic@10000040 {
+                compatible = "arm,versatile-fpga-irq";
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                reg = <0x10000040 0x100>;
+                clear-mask = <0xffffffff>;
+                valid-mask = <0x00000007>;
+        };
+        sic: sic@ca000000 {
+                compatible = "arm,versatile-fpga-irq";
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                reg = <0xca000000 0x100>;
+                clear-mask = <0x00000fff>;
+                valid-mask = <0x00000fff>;
+        };
+        ethernet@c8000000 {
+                compatible = "smsc,lan91c111";
+                reg = <0xc8000000 0x10>;
+                interrupt-parent = <&pic>;
+                interrupts = <27>;
+        };
+        fpga {
+                /*
+                 * These PrimeCells are at the same location and using
+                 * the same interrupts in all Integrators, but in the CP
+                 * slightly newer versions are deployed.
+                 */
+                rtc@15000000 {
+                        compatible = "arm,pl031", "arm,primecell";
+                };
+                uart@16000000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                };
+                uart@17000000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                };
+                kmi@18000000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                };
+                kmi@19000000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                };
+                /*
+                 * These PrimeCells are only available on the Integrator/CP
+                 */
+                mmc@1c000000 {
+                        compatible = "arm,pl180", "arm,primecell";
+                        reg = <0x1c000000 0x1000>;
+                        interrupts = <23 24>;
+                        max-frequency = <515633>;
+                };
+                aaci@1d000000 {
+                        compatible = "arm,pl041", "arm,primecell";
+                        reg = <0x1d000000 0x1000>;
+                        interrupts = <25>;
+                };
+                clcd@c0000000 {
+                        compatible = "arm,pl110", "arm,primecell";
+                        reg = <0xC0000000 0x1000>;
+                        interrupts = <22>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 7408655f91b5..9b32d0272825 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -25,6 +25,16 @@
                };
        };
+        gpio_fan {
+                /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
+                compatible = "gpio-fan";
+                gpios = <&gpio1 14 1
+                         &gpio1 13 1>;
+                gpio-fan,speed-map = <0    0
+                                      3000 1
+                                      6000 2>;
+        };
        ocp@f1000000 {
                sata@80000 {
                        status = "okay";
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
new file mode 100644
index 000000000000..08a582414b88
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -0,0 +1,57 @@
+/dts-v1/;
+/include/ "kirkwood.dtsi"
+/ {
+        model = "Seagate FreeAgent Dockstar";
+        compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+        };
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+                nand@3000000 {
+                        status = "okay";
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                                read-only;
+                        };
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x0100000 0x400000>;
+                        };
+                        partition@500000 {
+                                label = "data";
+                                reg = <0x0500000 0xfb00000>;
+                        };
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                health {
+                        label = "status:green:health";
+                        gpios = <&gpio1 14 1>;
+                        linux,default-trigger = "default-on";
+                };
+                fault {
+                        label = "status:orange:fault";
+                        gpios = <&gpio1 15 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index f8ca6fa88192..d97cd9d4753e 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -12,7 +12,7 @@
        };
        chosen {
-                bootargs = "console=ttyS0,115200n8 earlyprintk mtdparts=orion_nand:0xc0000@0x0(uboot),0x20000@0xa0000(env),0x300000@0x100000(zImage),0x300000@0x540000(initrd),0x1f400000@0x980000(boot)";
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
                linux,initrd-start = <0x4500040>;
                linux,initrd-end   = <0x4800000>;
        };
@@ -30,7 +30,37 @@
                        clock-frequency = <200000000>;
                        status = "ok";
                };
+                nand@3000000 {
+                        status = "okay";
+                        partition@0 {
+                                label = "uboot";
+                                reg = <0x0000000 0xc0000>;
+                        };
+                        partition@a0000 {
+                                label = "env";
+                                reg = <0xa0000 0x20000>;
+                        };
+                        partition@100000 {
+                                label = "zImage";
+                                reg = <0x100000 0x300000>;
+                        };
+                        partition@540000 {
+                                label = "initrd";
+                                reg = <0x540000 0x300000>;
+                        };
+                        partition@980000 {
+                                label = "boot";
+                                reg = <0x980000 0x1f400000>;
+                        };
+                };
        };
        gpio-leds {
                compatible = "gpio-leds";
@@ -69,4 +99,22 @@
                        gpios = <&gpio1 16 0>;
                };
        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "OTB Button";
+                        linux,code = <133>;
+                        gpios = <&gpio1 3 1>;
+                        debounce-interval = <100>;
+                };
+                button@2 {
+                        label = "Reset";
+                        linux,code = <0x198>;
+                        gpios = <&gpio0 12 1>;
+                        debounce-interval = <100>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
new file mode 100644
index 000000000000..865aeec40a26
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -0,0 +1,105 @@
+/dts-v1/;
+/include/ "kirkwood.dtsi"
+/ {
+        model = "Iomega StorCenter ix2-200";
+        compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+        ocp@f1000000 {
+                i2c@11000 {
+                        status = "okay";
+                        lm63: lm63@4c {
+                                compatible = "national,lm63";
+                                reg = <0x4c>;
+                        };
+                };
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+                nand@3000000 {
+                        status = "okay";
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                                read-only;
+                        };
+                        partition@a0000 {
+                                label = "env";
+                                reg = <0xa0000 0x20000>;
+                                read-only;
+                        };
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x100000 0x300000>;
+                        };
+                        partition@400000 {
+                                label = "uInitrd";
+                                reg = <0x540000 0x1000000>;
+                        };
+                };
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                power_led {
+                        label = "status:white:power_led";
+                        gpios = <&gpio0 16 0>;
+                        linux,default-trigger = "default-on";
+                };
+                health_led1 {
+                        label = "status:red:health_led";
+                        gpios = <&gpio1 5 0>;
+                };
+                health_led2 {
+                        label = "status:white:health_led";
+                        gpios = <&gpio1 4 0>;
+                };
+                backup_led {
+                        label = "status:blue:backup_led";
+                        gpios = <&gpio0 15 0>;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                Power {
+                        label = "Power Button";
+                        linux,code = <116>;
+                        gpios = <&gpio0 14 1>;
+                };
+                Reset {
+                        label = "Reset Button";
+                        linux,code = <0x198>;
+                        gpios = <&gpio0 12 1>;
+                };
+                OTB {
+                        label = "OTB Button";
+                        linux,code = <133>;
+                        gpios = <&gpio1 3 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
new file mode 100644
index 000000000000..75bdb93fed26
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -0,0 +1,29 @@
+/dts-v1/;
+/include/ "kirkwood.dtsi"
+/ {
+        model = "Keymile Kirkwood Reference Design";
+        compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x08000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+                nand@3000000 {
+                        status = "ok";
+                        chip-delay = <25>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index cef9616f330a..4e5b8154a5be 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -14,7 +14,8 @@
        ocp@f1000000 {
                compatible = "simple-bus";
-                ranges = <0 0xf1000000 0x4000000>;
+                ranges = <0x00000000 0xf1000000 0x4000000
+                          0xf5000000 0xf5000000 0x0000400>;
                #address-cells = <1>;
                #size-cells = <1>;
@@ -105,5 +106,14 @@
                        clock-frequency = <100000>;
                        status = "disabled";
                };
+                crypto@30000 {
+                        compatible = "marvell,orion-crypto";
+                        reg = <0x30000 0x10000>,
+                              <0xf5000000 0x800>;
+                        reg-names = "regs", "sram";
+                        interrupts = <22>;
+                        status = "okay";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 80f74e256408..0514fb41627e 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -26,6 +26,11 @@
                interrupt-parent = <&intc>;
                ranges;
+                L2: l2-cache {
+                        compatible = "marvell,tauros2-cache";
+                        marvell,tauros2-cache-features = <0x3>;
+                };
                axi@d4200000 {  /* AXI */
                        compatible = "mrvl,axi-bus", "simple-bus";
                        #address-cells = <1>;
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 45bc4bb04e57..31f2157cd7d7 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -7,7 +7,7 @@
        compatible = "qcom,msm8660-surf", "qcom,msm8660";
        interrupt-parent = <&intc>;
-        intc: interrupt-controller@02080000 {
+        intc: interrupt-controller@2080000 {
                compatible = "qcom,msm-8660-qgic";
                interrupt-controller;
                #interrupt-cells = <3>;
@@ -15,6 +15,23 @@
                      < 0x02081000 0x1000 >;
        };
+        timer@2000004 {
+                compatible = "qcom,msm-gpt", "qcom,msm-timer";
+                interrupts = <1 1 0x301>;
+                reg = <0x02000004 0x10>;
+                clock-frequency = <32768>;
+                cpu-offset = <0x40000>;
+        };
+        timer@2000024 {
+                compatible = "qcom,msm-dgt", "qcom,msm-timer";
+                interrupts = <1 0 0x301>;
+                reg = <0x02000024 0x10>,
+                      <0x02000034 0x4>;
+                clock-frequency = <6750000>;
+                cpu-offset = <0x40000>;
+        };
        serial@19c400000 {
                compatible = "qcom,msm-hsuart", "qcom,msm-uart";
                reg = <0x19c40000 0x1000>,
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts
new file mode 100644
index 000000000000..9e621b5ad3dd
--- /dev/null
+++ b/arch/arm/boot/dts/msm8960-cdp.dts
@@ -0,0 +1,41 @@
+/dts-v1/;
+/include/ "skeleton.dtsi"
+/ {
+        model = "Qualcomm MSM8960 CDP";
+        compatible = "qcom,msm8960-cdp", "qcom,msm8960";
+        interrupt-parent = <&intc>;
+        intc: interrupt-controller@2000000 {
+                compatible = "qcom,msm-qgic2";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = < 0x02000000 0x1000 >,
+                      < 0x02002000 0x1000 >;
+        };
+        timer@200a004 {
+                compatible = "qcom,msm-gpt", "qcom,msm-timer";
+                interrupts = <1 2 0x301>;
+                reg = <0x0200a004 0x10>;
+                clock-frequency = <32768>;
+                cpu-offset = <0x80000>;
+        };
+        timer@200a024 {
+                compatible = "qcom,msm-dgt", "qcom,msm-timer";
+                interrupts = <1 1 0x301>;
+                reg = <0x0200a024 0x10>,
+                      <0x0200a034 0x4>;
+                clock-frequency = <6750000>;
+                cpu-offset = <0x80000>;
+        };
+        serial@19c400000 {
+                compatible = "qcom,msm-hsuart", "qcom,msm-uart";
+                reg = <0x16440000 0x1000>,
+                      <0x16400000 0x1000>;
+                interrupts = <0 154 0x0>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 25b50b759dec..77b84e17c477 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
 */
 /dts-v1/;
-/include/ "omap2.dtsi"
+/include/ "omap2420.dtsi"
 / {
        model = "TI OMAP2420 H4 board";
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
new file mode 100644
index 000000000000..bfd76b4a0ddc
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -0,0 +1,48 @@
+/*
+ * Device Tree Source for OMAP2420 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/include/ "omap2.dtsi"
+/ {
+        compatible = "ti,omap2420", "ti,omap2";
+        ocp {
+                omap2420_pmx: pinmux@48000030 {
+                        compatible = "ti,omap2420-padconf", "pinctrl-single";
+                        reg = <0x48000030 0x0113>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <8>;
+                        pinctrl-single,function-mask = <0x3f>;
+                };
+                mcbsp1: mcbsp@48074000 {
+                        compatible = "ti,omap2420-mcbsp";
+                        reg = <0x48074000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <59>, /* TX interrupt */
+                                     <60>; /* RX interrupt */
+                        interrupt-names = "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,hwmods = "mcbsp1";
+                };
+                mcbsp2: mcbsp@48076000 {
+                        compatible = "ti,omap2420-mcbsp";
+                        reg = <0x48076000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <62>, /* TX interrupt */
+                                     <63>; /* RX interrupt */
+                        interrupt-names = "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,hwmods = "mcbsp2";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
new file mode 100644
index 000000000000..4565d9750f4d
--- /dev/null
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Device Tree Source for OMAP243x SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/include/ "omap2.dtsi"
+/ {
+        compatible = "ti,omap2430", "ti,omap2";
+        ocp {
+                omap2430_pmx: pinmux@49002030 {
+                        compatible = "ti,omap2430-padconf", "pinctrl-single";
+                        reg = <0x49002030 0x0154>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <8>;
+                        pinctrl-single,function-mask = <0x3f>;
+                };
+                mcbsp1: mcbsp@48074000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x48074000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <64>, /* OCP compliant interrupt */
+                                     <59>, /* TX interrupt */
+                                     <60>, /* RX interrupt */
+                                     <61>; /* RX overflow interrupt */
+                        interrupt-names = "common", "tx", "rx", "rx_overflow";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp1";
+                };
+                mcbsp2: mcbsp@48076000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x48076000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <16>, /* OCP compliant interrupt */
+                                     <62>, /* TX interrupt */
+                                     <63>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp2";
+                };
+                mcbsp3: mcbsp@4808c000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x4808c000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <17>, /* OCP compliant interrupt */
+                                     <89>, /* TX interrupt */
+                                     <90>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp3";
+                };
+                mcbsp4: mcbsp@4808e000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x4808e000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <18>, /* OCP compliant interrupt */
+                                     <54>, /* TX interrupt */
+                                     <55>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp4";
+                };
+                mcbsp5: mcbsp@48096000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x48096000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <19>, /* OCP compliant interrupt */
+                                     <81>, /* TX interrupt */
+                                     <82>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp5";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index cdcb98c7e075..c38cf76df81f 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -7,16 +7,44 @@
 */
 /dts-v1/;
-/include/ "omap3.dtsi"
+/include/ "omap36xx.dtsi"
 / {
-        model = "TI OMAP3 BeagleBoard";
+        model = "TI OMAP3 BeagleBoard xM";
-        compatible = "ti,omap3-beagle", "ti,omap3";
+        compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3";
        memory {
                device_type = "memory";
                reg = <0x80000000 0x20000000>; /* 512 MB */
        };
+        leds {
+                compatible = "gpio-leds";
+                pmu_stat {
+                        label = "beagleboard::pmu_stat";
+                        gpios = <&twl_gpio 19 0>; /* LEDB */
+                };
+                heartbeat {
+                        label = "beagleboard::usr0";
+                        gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+                        linux,default-trigger = "heartbeat";
+                };
+                mmc {
+                        label = "beagleboard::usr1";
+                        gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+                        linux,default-trigger = "mmc0";
+                };
+        };
+        sound {
+                compatible = "ti,omap-twl4030";
+                ti,model = "omap3beagle";
+                ti,mcbsp = <&mcbsp2>;
+                ti,codec = <&twl_audio>;
+        };
 };
 &i2c1 {
@@ -27,11 +55,17 @@
                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
                interrupt-parent = <&intc>;
-                vsim: regulator@10 {
+                vsim: regulator-vsim {
                        compatible = "ti,twl4030-vsim";
                        regulator-min-microvolt = <1800000>;
                        regulator-max-microvolt = <3000000>;
                };
+                twl_audio: audio {
+                        compatible = "ti,twl4030-audio";
+                        codec {
+                        };
+                };
        };
 };
@@ -67,3 +101,15 @@
 &mmc3 {
        status = "disabled";
 };
+&twl_gpio {
+        ti,use-leds;
+        /* pullups: BIT(1) */
+        ti,pullups = <0x000002>;
+        /*
+         * pulldowns:
+         * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
+         * BIT(15), BIT(16), BIT(17)
+         */
+        ti,pulldowns = <0x03a1c4>;
+};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index f349ee9182ce..e8ba1c247a39 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -17,6 +17,15 @@
                device_type = "memory";
                reg = <0x80000000 0x10000000>; /* 256 MB */
        };
+        leds {
+                compatible = "gpio-leds";
+                ledb {
+                        label = "omap3evm::ledb";
+                        gpios = <&twl_gpio 19 0>; /* LEDB */
+                        linux,default-trigger = "default-on";
+                };
+        };
 };
 &i2c1 {
@@ -46,3 +55,7 @@
                reg = <0x5c>;
        };
 };
+&twl_gpio {
+        ti,use-leds;
+};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
new file mode 100644
index 000000000000..89808ce01673
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * The Gumstix Overo must be combined with an expansion board.
+ */
+/dts-v1/;
+/include/ "omap3.dtsi"
+/ {
+        leds {
+                compatible = "gpio-leds";
+                overo {
+                        label = "overo:blue:COM";
+                        gpios = <&twl_gpio 19 0>;
+                        linux,default-trigger = "mmc0";
+                };
+        };
+};
+&i2c1 {
+        clock-frequency = <2600000>;
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+        };
+};
+/include/ "twl4030.dtsi"
+/* i2c2 pins are used for gpio */
+&i2c2 {
+        status = "disabled";
+};
+/* on board microSD slot */
+&mmc1 {
+        vmmc-supply = <&vmmc1>;
+        bus-width = <4>;
+};
+/* optional on board WiFi */
+&mmc2 {
+        bus-width = <4>;
+};
+&twl_gpio {
+        ti,use-leds;
+};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
new file mode 100644
index 000000000000..a13d12de77ff
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Tobi expansion board is manufactured by Gumstix Inc.
+ */
+/include/ "omap3-overo.dtsi"
+/ {
+        model = "TI OMAP3 Gumstix Overo on Tobi";
+        compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3";
+        leds {
+                compatible = "gpio-leds";
+                heartbeat {
+                        label = "overo:red:gpio21";
+                        gpios = <&gpio1 21 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+&i2c3 {
+        clock-frequency = <100000>;
+};
+&mmc3 {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 810947198208..f38ea8771b44 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -17,7 +17,6 @@
                serial0 = &uart1;
                serial1 = &uart2;
                serial2 = &uart3;
-                serial3 = &uart4;
        };
        cpus {
@@ -69,6 +68,24 @@
                        reg = <0x48200000 0x1000>;
                };
+                omap3_pmx_core: pinmux@48002030 {
+                        compatible = "ti,omap3-padconf", "pinctrl-single";
+                        reg = <0x48002030 0x05cc>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0x7fff>;
+                };
+                omap3_pmx_wkup: pinmux@0x48002a58 {
+                        compatible = "ti,omap3-padconf", "pinctrl-single";
+                        reg = <0x48002a58 0x5c>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0x7fff>;
+                };
                gpio1: gpio@48310000 {
                        compatible = "ti,omap3-gpio";
                        ti,hwmods = "gpio1";
@@ -141,12 +158,6 @@
                        clock-frequency = <48000000>;
                };
-                uart4: serial@49042000 {
-                        compatible = "ti,omap3-uart";
-                        ti,hwmods = "uart4";
-                        clock-frequency = <48000000>;
-                };
                i2c1: i2c@48070000 {
                        compatible = "ti,omap3-i2c";
                        #address-cells = <1>;
@@ -220,5 +231,74 @@
                        compatible = "ti,omap3-wdt";
                        ti,hwmods = "wd_timer2";
                };
+                mcbsp1: mcbsp@48074000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x48074000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <16>, /* OCP compliant interrupt */
+                                     <59>, /* TX interrupt */
+                                     <60>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp1";
+                };
+                mcbsp2: mcbsp@49022000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x49022000 0xff>,
+                              <0x49028000 0xff>;
+                        reg-names = "mpu", "sidetone";
+                        interrupts = <17>, /* OCP compliant interrupt */
+                                     <62>, /* TX interrupt */
+                                     <63>, /* RX interrupt */
+                                     <4>;  /* Sidetone */
+                        interrupt-names = "common", "tx", "rx", "sidetone";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <1280>;
+                        ti,hwmods = "mcbsp2";
+                };
+                mcbsp3: mcbsp@49024000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x49024000 0xff>,
+                              <0x4902a000 0xff>;
+                        reg-names = "mpu", "sidetone";
+                        interrupts = <22>, /* OCP compliant interrupt */
+                                     <89>, /* TX interrupt */
+                                     <90>, /* RX interrupt */
+                                     <5>;  /* Sidetone */
+                        interrupt-names = "common", "tx", "rx", "sidetone";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp3";
+                };
+                mcbsp4: mcbsp@49026000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x49026000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <23>, /* OCP compliant interrupt */
+                                     <54>, /* TX interrupt */
+                                     <55>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp4";
+                };
+                mcbsp5: mcbsp@48096000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x48096000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <27>, /* OCP compliant interrupt */
+                                     <81>, /* TX interrupt */
+                                     <82>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp5";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
new file mode 100644
index 000000000000..96bf0287cb9f
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Device Tree Source for OMAP3 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/include/ "omap3.dtsi"
+/ {
+        aliases {
+                serial3 = &uart4;
+        };
+        ocp {
+                uart4: serial@49042000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 9880c12877b3..e8f927cbb376 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 /include/ "omap4.dtsi"
+/include/ "elpida_ecb240abacn.dtsi"
 / {
        model = "TI OMAP4 PandaBoard";
@@ -58,6 +59,41 @@
        };
 };
+&omap4_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &twl6040_pins
+                        &mcpdm_pins
+                        &mcbsp1_pins
+        >;
+        twl6040_pins: pinmux_twl6040_pins {
+                pinctrl-single,pins = <
+                        0xe0 0x3        /* hdq_sio.gpio_127 OUTPUT | MODE3 */
+                        0x160 0x100     /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
+                >;
+        };
+        mcpdm_pins: pinmux_mcpdm_pins {
+                pinctrl-single,pins = <
+                        0xc6 0x108      /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
+                        0xc8 0x108      /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
+                        0xca 0x118      /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
+                        0xcc 0x108      /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
+                        0xce 0x108      /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+                >;
+        };
+        mcbsp1_pins: pinmux_mcbsp1_pins {
+                pinctrl-single,pins = <
+                        0xbe 0x100      /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
+                        0xc0 0x108      /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
+                        0xc2 0x8                /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
+                        0xc4 0x100      /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
+                >;
+        };
+};
 &i2c1 {
        clock-frequency = <400000>;
@@ -126,3 +162,25 @@
        ti,non-removable;
        bus-width = <4>;
 };
+&emif1 {
+        cs1-used;
+        device-handle = <&elpida_ECB240ABACN>;
+};
+&emif2 {
+        cs1-used;
+        device-handle = <&elpida_ECB240ABACN>;
+};
+&mcbsp2 {
+        status = "disabled";
+};
+&mcbsp3 {
+        status = "disabled";
+};
+&dmic {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 72216e932fc0..5b7e04fbff50 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 /include/ "omap4.dtsi"
+/include/ "elpida_ecb240abacn.dtsi"
 / {
        model = "TI OMAP4 SDP board";
@@ -18,7 +19,7 @@
                reg = <0x80000000 0x40000000>; /* 1 GB */
        };
-        vdd_eth: fixedregulator@0 {
+        vdd_eth: fixedregulator-vdd-eth {
                compatible = "regulator-fixed";
                regulator-name = "VDD_ETH";
                regulator-min-microvolt = <3300000>;
@@ -28,7 +29,7 @@
                regulator-boot-on;
        };
-        vbat: fixedregulator@2 {
+        vbat: fixedregulator-vbat {
                compatible = "regulator-fixed";
                regulator-name = "VBAT";
                regulator-min-microvolt = <3750000>;
@@ -115,6 +116,86 @@
        };
 };
+&omap4_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &twl6040_pins
+                        &mcpdm_pins
+                        &dmic_pins
+                        &mcbsp1_pins
+                        &mcbsp2_pins
+        >;
+        uart2_pins: pinmux_uart2_pins {
+                pinctrl-single,pins = <
+                        0xd8 0x118      /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
+                        0xda 0          /* uart2_rts.uart2_rts OUTPUT | MODE0 */
+                        0xdc 0x118      /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */
+                        0xde 0          /* uart2_tx.uart2_tx OUTPUT | MODE0 */
+                >;
+        };
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x100 0x118     /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */
+                        0x102 0         /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */
+                        0x104 0x100     /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */
+                        0x106 0         /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+                >;
+        };
+        uart4_pins: pinmux_uart4_pins {
+                pinctrl-single,pins = <
+                        0x11c 0x100     /* uart4_rx.uart4_rx INPUT | MODE0 */
+                        0x11e 0         /* uart4_tx.uart4_tx OUTPUT | MODE0 */
+                >;
+        };
+        twl6040_pins: pinmux_twl6040_pins {
+                pinctrl-single,pins = <
+                        0xe0 0x3        /* hdq_sio.gpio_127 OUTPUT | MODE3 */
+                        0x160 0x100     /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
+                >;
+        };
+        mcpdm_pins: pinmux_mcpdm_pins {
+                pinctrl-single,pins = <
+                        0xc6 0x108      /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
+                        0xc8 0x108      /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
+                        0xca 0x118      /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
+                        0xcc 0x108      /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
+                        0xce 0x108      /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+                >;
+        };
+        dmic_pins: pinmux_dmic_pins {
+                pinctrl-single,pins = <
+                        0xd0 0          /* abe_dmic_clk1.abe_dmic_clk1 OUTPUT | MODE0 */
+                        0xd2 0x100      /* abe_dmic_din1.abe_dmic_din1 INPUT | MODE0 */
+                        0xd4 0x100      /* abe_dmic_din2.abe_dmic_din2 INPUT | MODE0 */
+                        0xd6 0x100      /* abe_dmic_din3.abe_dmic_din3 INPUT | MODE0 */
+                >;
+        };
+        mcbsp1_pins: pinmux_mcbsp1_pins {
+                pinctrl-single,pins = <
+                        0xbe 0x100      /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
+                        0xc0 0x108      /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
+                        0xc2 0x8        /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
+                        0xc4 0x100      /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
+                >;
+        };
+        mcbsp2_pins: pinmux_mcbsp2_pins {
+                pinctrl-single,pins = <
+                        0xb6 0x100      /* abe_mcbsp2_clkx.abe_mcbsp2_clkx INPUT | MODE0 */
+                        0xb8 0x108      /* abe_mcbsp2_dr.abe_mcbsp2_dr INPUT PULLDOWN | MODE0 */
+                        0xba 0x8        /* abe_mcbsp2_dx.abe_mcbsp2_dx OUTPUT PULLDOWN | MODE0 */
+                        0xbc 0x100      /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */
+                >;
+        };
+};
 &i2c1 {
        clock-frequency = <400000>;
@@ -226,3 +307,102 @@
        bus-width = <4>;
        ti,non-removable;
 };
+&emif1 {
+        cs1-used;
+        device-handle = <&elpida_ECB240ABACN>;
+};
+&emif2 {
+        cs1-used;
+        device-handle = <&elpida_ECB240ABACN>;
+};
+&keypad {
+        keypad,num-rows = <8>;
+        keypad,num-columns = <8>;
+        linux,keymap = <0x00000012      /* KEY_E */
+                        0x00010013      /* KEY_R */
+                        0x00020014      /* KEY_T */
+                        0x00030066      /* KEY_HOME */
+                        0x0004003f      /* KEY_F5 */
+                        0x000500f0      /* KEY_UNKNOWN */
+                        0x00060017      /* KEY_I */
+                        0x0007002a      /* KEY_LEFTSHIFT */
+                        0x01000020      /* KEY_D*/
+                        0x01010021      /* KEY_F */
+                        0x01020022      /* KEY_G */
+                        0x010300e7      /* KEY_SEND */
+                        0x01040040      /* KEY_F6 */
+                        0x010500f0      /* KEY_UNKNOWN */
+                        0x01060025      /* KEY_K */
+                        0x0107001c      /* KEY_ENTER */
+                        0x0200002d      /* KEY_X */
+                        0x0201002e      /* KEY_C */
+                        0x0202002f      /* KEY_V */
+                        0x0203006b      /* KEY_END */
+                        0x02040041      /* KEY_F7 */
+                        0x020500f0      /* KEY_UNKNOWN */
+                        0x02060034      /* KEY_DOT */
+                        0x0207003a      /* KEY_CAPSLOCK */
+                        0x0300002c      /* KEY_Z */
+                        0x0301004e      /* KEY_KPLUS */
+                        0x03020030      /* KEY_B */
+                        0x0303003b      /* KEY_F1 */
+                        0x03040042      /* KEY_F8 */
+                        0x030500f0      /* KEY_UNKNOWN */
+                        0x03060018      /* KEY_O */
+                        0x03070039      /* KEY_SPACE */
+                        0x04000011      /* KEY_W */
+                        0x04010015      /* KEY_Y */
+                        0x04020016      /* KEY_U */
+                        0x0403003c      /* KEY_F2 */
+                        0x04040073      /* KEY_VOLUMEUP */
+                        0x040500f0      /* KEY_UNKNOWN */
+                        0x04060026      /* KEY_L */
+                        0x04070069      /* KEY_LEFT */
+                        0x0500001f      /* KEY_S */
+                        0x05010023      /* KEY_H */
+                        0x05020024      /* KEY_J */
+                        0x0503003d      /* KEY_F3 */
+                        0x05040043      /* KEY_F9 */
+                        0x05050072      /* KEY_VOLUMEDOWN */
+                        0x05060032      /* KEY_M */
+                        0x0507006a      /* KEY_RIGHT */
+                        0x06000010      /* KEY_Q */
+                        0x0601001e      /* KEY_A */
+                        0x06020031      /* KEY_N */
+                        0x0603009e      /* KEY_BACK */
+                        0x0604000e      /* KEY_BACKSPACE */
+                        0x060500f0      /* KEY_UNKNOWN */
+                        0x06060019      /* KEY_P */
+                        0x06070067      /* KEY_UP */
+                        0x07000094      /* KEY_PROG1 */
+                        0x07010095      /* KEY_PROG2 */
+                        0x070200ca      /* KEY_PROG3 */
+                        0x070300cb      /* KEY_PROG4 */
+                        0x0704003e      /* KEY_F4 */
+                        0x070500f0      /* KEY_UNKNOWN */
+                        0x07060160      /* KEY_OK */
+                        0x0707006c>;    /* KEY_DOWN */
+        linux,input-no-autorepeat;
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart4_pins>;
+};
+&mcbsp3 {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 04cbbcb6ff91..3883f94fdbd0 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -30,12 +30,35 @@
        cpus {
                cpu@0 {
                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
                };
                cpu@1 {
                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
                };
        };
+        gic: interrupt-controller@48241000 {
+                compatible = "arm,cortex-a9-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x48241000 0x1000>,
+                      <0x48240100 0x0100>;
+        };
+        L2: l2-cache-controller@48242000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x48242000 0x1000>;
+                cache-unified;
+                cache-level = <2>;
+        };
+        local-timer@0x48240600 {
+                compatible = "arm,cortex-a9-twd-timer";
+                reg = <0x48240600 0x20>;
+                interrupts = <1 13 0x304>;
+        };
        /*
         * The soc node represents the soc top level view. It is uses for IPs
         * that are not memory mapped in the MPU view or for the MPU itself.
@@ -61,30 +84,6 @@
        /*
         * XXX: Use a flat representation of the OMAP4 interconnect.
         * The real OMAP interconnect network is quite complex.
-         *
-         * MPU -+-- MPU_PRIVATE - GIC, L2
-         *      |
-         *      +----------------+----------+
-         *      |                |          |
-         *      +            +- EMIF - DDR  |
-         *      |            |              |
-         *      |            +     +--------+
-         *      |            |     |
-         *      |            +- L4_ABE - AESS, MCBSP, TIMERs...
-         *      |            |
-         *      +- L3_MAIN --+- L4_CORE - IPs...
-         *                   |
-         *                   +- L4_PER - IPs...
-         *                   |
-         *                   +- L4_CFG -+- L4_WKUP - IPs...
-         *                   |          |
-         *                   |          +- IPs...
-         *                   +- IPU ----+
-         *                   |          |
-         *                   +- DSP ----+
-         *                   |          |
-         *                   +- DSS ----+
-         *
         * Since that will not bring real advantage to represent that in DT for
         * the moment, just use a fake OCP bus entry to represent the whole bus
         * hierarchy.
@@ -96,16 +95,27 @@
                ranges;
                ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
-                gic: interrupt-controller@48241000 {
+                omap4_pmx_core: pinmux@4a100040 {
-                        compatible = "arm,cortex-a9-gic";
+                        compatible = "ti,omap4-padconf", "pinctrl-single";
-                        interrupt-controller;
+                        reg = <0x4a100040 0x0196>;
-                        #interrupt-cells = <3>;
+                        #address-cells = <1>;
-                        reg = <0x48241000 0x1000>,
+                        #size-cells = <0>;
-                              <0x48240100 0x0100>;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0x7fff>;
+                };
+                omap4_pmx_wkup: pinmux@4a31e040 {
+                        compatible = "ti,omap4-padconf", "pinctrl-single";
+                        reg = <0x4a31e040 0x0038>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0x7fff>;
                };
                gpio1: gpio@4a310000 {
                        compatible = "ti,omap4-gpio";
+                        reg = <0x4a310000 0x200>;
+                        interrupts = <0 29 0x4>;
                        ti,hwmods = "gpio1";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -115,6 +125,8 @@
                gpio2: gpio@48055000 {
                        compatible = "ti,omap4-gpio";
+                        reg = <0x48055000 0x200>;
+                        interrupts = <0 30 0x4>;
                        ti,hwmods = "gpio2";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -124,6 +136,8 @@
                gpio3: gpio@48057000 {
                        compatible = "ti,omap4-gpio";
+                        reg = <0x48057000 0x200>;
+                        interrupts = <0 31 0x4>;
                        ti,hwmods = "gpio3";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -133,6 +147,8 @@
                gpio4: gpio@48059000 {
                        compatible = "ti,omap4-gpio";
+                        reg = <0x48059000 0x200>;
+                        interrupts = <0 32 0x4>;
                        ti,hwmods = "gpio4";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -142,6 +158,8 @@
                gpio5: gpio@4805b000 {
                        compatible = "ti,omap4-gpio";
+                        reg = <0x4805b000 0x200>;
+                        interrupts = <0 33 0x4>;
                        ti,hwmods = "gpio5";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -151,6 +169,8 @@
                gpio6: gpio@4805d000 {
                        compatible = "ti,omap4-gpio";
+                        reg = <0x4805d000 0x200>;
+                        interrupts = <0 34 0x4>;
                        ti,hwmods = "gpio6";
                        gpio-controller;
                        #gpio-cells = <2>;
@@ -160,30 +180,40 @@
                uart1: serial@4806a000 {
                        compatible = "ti,omap4-uart";
+                        reg = <0x4806a000 0x100>;
+                        interrupts = <0 72 0x4>;
                        ti,hwmods = "uart1";
                        clock-frequency = <48000000>;
                };
                uart2: serial@4806c000 {
                        compatible = "ti,omap4-uart";
+                        reg = <0x4806c000 0x100>;
+                        interrupts = <0 73 0x4>;
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
                };
                uart3: serial@48020000 {
                        compatible = "ti,omap4-uart";
+                        reg = <0x48020000 0x100>;
+                        interrupts = <0 74 0x4>;
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
                };
                uart4: serial@4806e000 {
                        compatible = "ti,omap4-uart";
+                        reg = <0x4806e000 0x100>;
+                        interrupts = <0 70 0x4>;
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
                };
                i2c1: i2c@48070000 {
                        compatible = "ti,omap4-i2c";
+                        reg = <0x48070000 0x100>;
+                        interrupts = <0 56 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c1";
@@ -191,6 +221,8 @@
                i2c2: i2c@48072000 {
                        compatible = "ti,omap4-i2c";
+                        reg = <0x48072000 0x100>;
+                        interrupts = <0 57 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c2";
@@ -198,6 +230,8 @@
                i2c3: i2c@48060000 {
                        compatible = "ti,omap4-i2c";
+                        reg = <0x48060000 0x100>;
+                        interrupts = <0 61 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c3";
@@ -205,6 +239,8 @@
                i2c4: i2c@48350000 {
                        compatible = "ti,omap4-i2c";
+                        reg = <0x48350000 0x100>;
+                        interrupts = <0 62 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "i2c4";
@@ -212,6 +248,8 @@
                mcspi1: spi@48098000 {
                        compatible = "ti,omap4-mcspi";
+                        reg = <0x48098000 0x200>;
+                        interrupts = <0 65 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "mcspi1";
@@ -220,6 +258,8 @@
                mcspi2: spi@4809a000 {
                        compatible = "ti,omap4-mcspi";
+                        reg = <0x4809a000 0x200>;
+                        interrupts = <0 66 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "mcspi2";
@@ -228,6 +268,8 @@
                mcspi3: spi@480b8000 {
                        compatible = "ti,omap4-mcspi";
+                        reg = <0x480b8000 0x200>;
+                        interrupts = <0 91 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "mcspi3";
@@ -236,6 +278,8 @@
                mcspi4: spi@480ba000 {
                        compatible = "ti,omap4-mcspi";
+                        reg = <0x480ba000 0x200>;
+                        interrupts = <0 48 0x4>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        ti,hwmods = "mcspi4";
@@ -244,6 +288,8 @@
                mmc1: mmc@4809c000 {
                        compatible = "ti,omap4-hsmmc";
+                        reg = <0x4809c000 0x400>;
+                        interrupts = <0 83 0x4>;
                        ti,hwmods = "mmc1";
                        ti,dual-volt;
                        ti,needs-special-reset;
@@ -251,30 +297,40 @@
                mmc2: mmc@480b4000 {
                        compatible = "ti,omap4-hsmmc";
+                        reg = <0x480b4000 0x400>;
+                        interrupts = <0 86 0x4>;
                        ti,hwmods = "mmc2";
                        ti,needs-special-reset;
                };
                mmc3: mmc@480ad000 {
                        compatible = "ti,omap4-hsmmc";
+                        reg = <0x480ad000 0x400>;
+                        interrupts = <0 94 0x4>;
                        ti,hwmods = "mmc3";
                        ti,needs-special-reset;
                };
                mmc4: mmc@480d1000 {
                        compatible = "ti,omap4-hsmmc";
+                        reg = <0x480d1000 0x400>;
+                        interrupts = <0 96 0x4>;
                        ti,hwmods = "mmc4";
                        ti,needs-special-reset;
                };
                mmc5: mmc@480d5000 {
                        compatible = "ti,omap4-hsmmc";
+                        reg = <0x480d5000 0x400>;
+                        interrupts = <0 59 0x4>;
                        ti,hwmods = "mmc5";
                        ti,needs-special-reset;
                };
                wdt2: wdt@4a314000 {
                        compatible = "ti,omap4-wdt", "ti,omap3-wdt";
+                        reg = <0x4a314000 0x80>;
+                        interrupts = <0 80 0x4>;
                        ti,hwmods = "wd_timer2";
                };
@@ -282,6 +338,7 @@
                        compatible = "ti,omap4-mcpdm";
                        reg = <0x40132000 0x7f>, /* MPU private access */
                              <0x49032000 0x7f>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
                        interrupts = <0 112 0x4>;
                        interrupt-parent = <&gic>;
                        ti,hwmods = "mcpdm";
@@ -291,9 +348,95 @@
                        compatible = "ti,omap4-dmic";
                        reg = <0x4012e000 0x7f>, /* MPU private access */
                              <0x4902e000 0x7f>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
                        interrupts = <0 114 0x4>;
                        interrupt-parent = <&gic>;
                        ti,hwmods = "dmic";
                };
+                mcbsp1: mcbsp@40122000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40122000 0xff>, /* MPU private access */
+                              <0x49022000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 17 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp1";
+                };
+                mcbsp2: mcbsp@40124000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40124000 0xff>, /* MPU private access */
+                              <0x49024000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 22 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp2";
+                };
+                mcbsp3: mcbsp@40126000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40126000 0xff>, /* MPU private access */
+                              <0x49026000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 23 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp3";
+                };
+                mcbsp4: mcbsp@48096000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x48096000 0xff>; /* L4 Interconnect */
+                        reg-names = "mpu";
+                        interrupts = <0 16 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp4";
+                };
+                keypad: keypad@4a31c000 {
+                        compatible = "ti,omap4-keypad";
+                        reg = <0x4a31c000 0x80>;
+                        interrupts = <0 120 0x4>;
+                        reg-names = "mpu";
+                        ti,hwmods = "kbd";
+                };
+                emif1: emif@4c000000 {
+                        compatible = "ti,emif-4d";
+                        reg = <0x4c000000 0x100>;
+                        interrupts = <0 110 0x4>;
+                        ti,hwmods = "emif1";
+                        phy-type = <1>;
+                        hw-caps-read-idle-ctrl;
+                        hw-caps-ll-interface;
+                        hw-caps-temp-alert;
+                };
+                emif2: emif@4d000000 {
+                        compatible = "ti,emif-4d";
+                        reg = <0x4d000000 0x100>;
+                        interrupts = <0 111 0x4>;
+                        ti,hwmods = "emif2";
+                        phy-type = <1>;
+                        hw-caps-read-idle-ctrl;
+                        hw-caps-ll-interface;
+                        hw-caps-temp-alert;
+                };
+                ocp2scp {
+                        compatible = "ti,omap-ocp2scp";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        ti,hwmods = "ocp2scp_usb_phy";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 200c39ad1c82..c663eba73168 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -17,4 +17,126 @@
                device_type = "memory";
                reg = <0x80000000 0x40000000>; /* 1 GB */
        };
+        vmmcsd_fixed: fixedregulator-mmcsd {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmcsd_fixed";
+                regulator-min-microvolt = <3000000>;
+                regulator-max-microvolt = <3000000>;
+        };
+};
+&omap5_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &twl6040_pins
+                        &mcpdm_pins
+                        &dmic_pins
+                        &mcbsp1_pins
+                        &mcbsp2_pins
+        >;
+        twl6040_pins: pinmux_twl6040_pins {
+                pinctrl-single,pins = <
+                        0x18a 0x6       /* perslimbus2_clock.gpio5_145 OUTPUT | MODE6 */
+                >;
+        };
+        mcpdm_pins: pinmux_mcpdm_pins {
+                pinctrl-single,pins = <
+                        0x142 0x108     /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+                        0x15c 0x108     /* abemcpdm_ul_data.abemcpdm_ul_data INPUT PULLDOWN | MODE0 */
+                        0x15e 0x108     /* abemcpdm_dl_data.abemcpdm_dl_data INPUT PULLDOWN | MODE0 */
+                        0x160 0x118     /* abemcpdm_frame.abemcpdm_frame INPUT PULLUP | MODE0 */
+                        0x162 0x108     /* abemcpdm_lb_clk.abemcpdm_lb_clk INPUT PULLDOWN | MODE0 */
+                >;
+        };
+        dmic_pins: pinmux_dmic_pins {
+                pinctrl-single,pins = <
+                        0x144 0x100     /* abedmic_din1.abedmic_din1 INPUT | MODE0 */
+                        0x146 0x100     /* abedmic_din2.abedmic_din2 INPUT | MODE0 */
+                        0x148 0x100     /* abedmic_din3.abedmic_din3 INPUT | MODE0 */
+                        0x14a 0         /* abedmic_clk1.abedmic_clk1 OUTPUT | MODE0 */
+                >;
+        };
+        mcbsp1_pins: pinmux_mcbsp1_pins {
+                pinctrl-single,pins = <
+                        0x14c 0x101     /* abedmic_clk2.abemcbsp1_fsx INPUT | MODE1 */
+                        0x14e 0x9       /* abedmic_clk3.abemcbsp1_dx OUTPUT PULLDOWN | MODE1 */
+                        0x150 0x101     /* abeslimbus1_clock.abemcbsp1_clkx INPUT | MODE0 */
+                        0x152 0x109     /* abeslimbus1_data.abemcbsp1_dr INPUT PULLDOWN | MODE1 */
+                >;
+        };
+        mcbsp2_pins: pinmux_mcbsp2_pins {
+                pinctrl-single,pins = <
+                        0x154 0x108     /* abemcbsp2_dr.abemcbsp2_dr INPUT PULLDOWN | MODE0 */
+                        0x156 0x8       /* abemcbsp2_dx.abemcbsp2_dx OUTPUT PULLDOWN | MODE0 */
+                        0x158 0x100     /* abemcbsp2_fsx.abemcbsp2_fsx INPUT | MODE0 */
+                        0x15a 0x100     /* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */
+                >;
+        };
+};
+&mmc1 {
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <4>;
+};
+&mmc2 {
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <8>;
+        ti,non-removable;
+};
+&mmc3 {
+        bus-width = <4>;
+        ti,non-removable;
+};
+&mmc4 {
+        status = "disabled";
+};
+&mmc5 {
+        status = "disabled";
+};
+&i2c2 {
+        clock-frequency = <400000>;
+        /* Pressure Sensor */
+        bmp085@77 {
+                compatible = "bosch,bmp085";
+                reg = <0x77>;
+        };
+};
+&i2c4 {
+        clock-frequency = <400000>;
+        /* Temperature Sensor */
+        tmp102@48{
+                compatible = "ti,tmp102";
+                reg = <0x48>;
+        };
+};
+&keypad {
+        keypad,num-rows = <8>;
+        keypad,num-columns = <8>;
+        linux,keymap = <0x02020073      /* VOLUP */
+                        0x02030072      /* VOLDOWM */
+                        0x020400e7      /* SEND */
+                        0x02050066      /* HOME */
+                        0x0206006b      /* END */
+                        0x020700d9>;    /* SEARCH */
+        linux,input-no-autorepeat;
+};
+&mcbsp3 {
+        status = "disabled";
 };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e527083746..42c78beb4fdc 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -33,9 +33,21 @@
        cpus {
                cpu@0 {
                        compatible = "arm,cortex-a15";
+                        timer {
+                                compatible = "arm,armv7-timer";
+                                /* 14th PPI IRQ, active low level-sensitive */
+                                interrupts = <1 14 0x308>;
+                                clock-frequency = <6144000>;
+                        };
                };
                cpu@1 {
                        compatible = "arm,cortex-a15";
+                        timer {
+                                compatible = "arm,armv7-timer";
+                                /* 14th PPI IRQ, active low level-sensitive */
+                                interrupts = <1 14 0x308>;
+                                clock-frequency = <6144000>;
+                        };
                };
        };
@@ -65,6 +77,23 @@
                ranges;
                ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+                omap5_pmx_core: pinmux@4a002840 {
+                        compatible = "ti,omap4-padconf", "pinctrl-single";
+                        reg = <0x4a002840 0x01b6>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0x7fff>;
+                };
+                omap5_pmx_wkup: pinmux@4ae0c840 {
+                        compatible = "ti,omap4-padconf", "pinctrl-single";
+                        reg = <0x4ae0c840 0x0038>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0x7fff>;
+                };
                gic: interrupt-controller@48211000 {
                        compatible = "arm,cortex-a15-gic";
                        interrupt-controller;
@@ -145,6 +174,41 @@
                        #interrupt-cells = <1>;
                };
+                i2c1: i2c@48070000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c1";
+                };
+                i2c2: i2c@48072000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c2";
+                };
+                i2c3: i2c@48060000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c3";
+                };
+                i2c4: i2c@4807A000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c4";
+                };
+                i2c5: i2c@4807C000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c5";
+                };
                uart1: serial@4806a000 {
                        compatible = "ti,omap4-uart";
                        ti,hwmods = "uart1";
@@ -180,5 +244,97 @@
                        ti,hwmods = "uart6";
                        clock-frequency = <48000000>;
                };
+                mmc1: mmc@4809c000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc1";
+                        ti,dual-volt;
+                        ti,needs-special-reset;
+                };
+                mmc2: mmc@480b4000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc2";
+                        ti,needs-special-reset;
+                };
+                mmc3: mmc@480ad000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc3";
+                        ti,needs-special-reset;
+                };
+                mmc4: mmc@480d1000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc4";
+                        ti,needs-special-reset;
+                };
+                mmc5: mmc@480d5000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc5";
+                        ti,needs-special-reset;
+                };
+                keypad: keypad@4ae1c000 {
+                        compatible = "ti,omap4-keypad";
+                        ti,hwmods = "kbd";
+                };
+                mcpdm: mcpdm@40132000 {
+                        compatible = "ti,omap4-mcpdm";
+                        reg = <0x40132000 0x7f>, /* MPU private access */
+                              <0x49032000 0x7f>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 112 0x4>;
+                        interrupt-parent = <&gic>;
+                        ti,hwmods = "mcpdm";
+                };
+                dmic: dmic@4012e000 {
+                        compatible = "ti,omap4-dmic";
+                        reg = <0x4012e000 0x7f>, /* MPU private access */
+                              <0x4902e000 0x7f>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 114 0x4>;
+                        interrupt-parent = <&gic>;
+                        ti,hwmods = "dmic";
+                };
+                mcbsp1: mcbsp@40122000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40122000 0xff>, /* MPU private access */
+                              <0x49022000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 17 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp1";
+                };
+                mcbsp2: mcbsp@40124000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40124000 0xff>, /* MPU private access */
+                              <0x49024000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 22 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp2";
+                };
+                mcbsp3: mcbsp@40126000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40126000 0xff>, /* MPU private access */
+                              <0x49026000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 23 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp3";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
index 802ec5b2fd00..90fdbd77f274 100644
--- a/arch/arm/boot/dts/phy3250.dts
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -135,13 +135,11 @@
                        ssp0: ssp@20084000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                pl022,num-chipselects = <1>;
+                                num-cs = <1>;
                                cs-gpios = <&gpio 3 5 0>;
                                eeprom: at25@0 {
-                                        pl022,hierarchy = <0>;
                                        pl022,interface = <0>;
-                                        pl022,slave-tx-disable = <0>;
                                        pl022,com-mode = <0>;
                                        pl022,rx-level-trig = <1>;
                                        pl022,tx-level-trig = <1>;
@@ -191,16 +189,14 @@
        leds {
                compatible = "gpio-leds";
-                led0 {
+                led0 { /* red */
-                        gpios = <&gpio 5 1 1>; /* GPO_P3 1, GPIO 80, active low */
+                        gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
-                        linux,default-trigger = "heartbeat";
                        default-state = "off";
                };
-                led1 {
+                led1 { /* green */
-                        gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
+                        gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
-                        linux,default-trigger = "timer";
+                        linux,default-trigger = "heartbeat";
-                        default-state = "off";
                };
        };
 };
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts
deleted file mode 100644
index 34ae3a64ba25..000000000000
--- a/arch/arm/boot/dts/prima2-cb.dts
+++ /dev/null
@@ -1,424 +0,0 @@
-/dts-v1/;
-/ {
-        model = "SiRF Prima2 eVB";
-        compatible = "sirf,prima2-cb", "sirf,prima2";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&intc>;
-        memory {
-                reg = <0x00000000 0x20000000>;
-        };
-        chosen {
-                bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1";
-                linux,stdout-path = &uart1;
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                cpu@0 {
-                        reg = <0x0>;
-                        d-cache-line-size = <32>;
-                        i-cache-line-size = <32>;
-                        d-cache-size = <32768>;
-                        i-cache-size = <32768>;
-                        /* from bootloader */
-                        timebase-frequency = <0>;
-                        bus-frequency = <0>;
-                        clock-frequency = <0>;
-                };
-        };
-        axi {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0x40000000 0x40000000 0x80000000>;
-                l2-cache-controller@80040000 {
-                        compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
-                        reg = <0x80040000 0x1000>;
-                        interrupts = <59>;
-                        arm,tag-latency = <1 1 1>;
-                        arm,data-latency = <1 1 1>;
-                        arm,filter-ranges = <0 0x40000000>;
-                };
-                intc: interrupt-controller@80020000 {
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        compatible = "sirf,prima2-intc";
-                        reg = <0x80020000 0x1000>;
-                };
-                sys-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0x88000000 0x88000000 0x40000>;
-                        clock-controller@88000000 {
-                                compatible = "sirf,prima2-clkc";
-                                reg = <0x88000000 0x1000>;
-                                interrupts = <3>;
-                        };
-                        reset-controller@88010000 {
-                                compatible = "sirf,prima2-rstc";
-                                reg = <0x88010000 0x1000>;
-                        };
-                        rsc-controller@88020000 {
-                                compatible = "sirf,prima2-rsc";
-                                reg = <0x88020000 0x1000>;
-                        };
-                };
-                mem-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0x90000000 0x90000000 0x10000>;
-                        memory-controller@90000000 {
-                                compatible = "sirf,prima2-memc";
-                                reg = <0x90000000 0x10000>;
-                                interrupts = <27>;
-                        };
-                };
-                disp-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0x90010000 0x90010000 0x30000>;
-                        display@90010000 {
-                                compatible = "sirf,prima2-lcd";
-                                reg = <0x90010000 0x20000>;
-                                interrupts = <30>;
-                        };
-                        vpp@90020000 {
-                                compatible = "sirf,prima2-vpp";
-                                reg = <0x90020000 0x10000>;
-                                interrupts = <31>;
-                        };
-                };
-                graphics-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0x98000000 0x98000000 0x8000000>;
-                        graphics@98000000 {
-                                compatible = "powervr,sgx531";
-                                reg = <0x98000000 0x8000000>;
-                                interrupts = <6>;
-                        };
-                };
-                multimedia-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0xa0000000 0xa0000000 0x8000000>;
-                        multimedia@a0000000 {
-                                compatible = "sirf,prima2-video-codec";
-                                reg = <0xa0000000 0x8000000>;
-                                interrupts = <5>;
-                        };
-                };
-                dsp-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0xa8000000 0xa8000000 0x2000000>;
-                        dspif@a8000000 {
-                                compatible = "sirf,prima2-dspif";
-                                reg = <0xa8000000 0x10000>;
-                                interrupts = <9>;
-                        };
-                        gps@a8010000 {
-                                compatible = "sirf,prima2-gps";
-                                reg = <0xa8010000 0x10000>;
-                                interrupts = <7>;
-                        };
-                        dsp@a9000000 {
-                                compatible = "sirf,prima2-dsp";
-                                reg = <0xa9000000 0x1000000>;
-                                interrupts = <8>;
-                        };
-                };
-                peri-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0xb0000000 0xb0000000 0x180000>;
-                        timer@b0020000 {
-                                compatible = "sirf,prima2-tick";
-                                reg = <0xb0020000 0x1000>;
-                                interrupts = <0>;
-                        };
-                        nand@b0030000 {
-                                compatible = "sirf,prima2-nand";
-                                reg = <0xb0030000 0x10000>;
-                                interrupts = <41>;
-                        };
-                        audio@b0040000 {
-                                compatible = "sirf,prima2-audio";
-                                reg = <0xb0040000 0x10000>;
-                                interrupts = <35>;
-                        };
-                        uart0: uart@b0050000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-uart";
-                                reg = <0xb0050000 0x10000>;
-                                interrupts = <17>;
-                        };
-                        uart1: uart@b0060000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-uart";
-                                reg = <0xb0060000 0x10000>;
-                                interrupts = <18>;
-                        };
-                        uart2: uart@b0070000 {
-                                cell-index = <2>;
-                                compatible = "sirf,prima2-uart";
-                                reg = <0xb0070000 0x10000>;
-                                interrupts = <19>;
-                        };
-                        usp0: usp@b0080000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-usp";
-                                reg = <0xb0080000 0x10000>;
-                                interrupts = <20>;
-                        };
-                        usp1: usp@b0090000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-usp";
-                                reg = <0xb0090000 0x10000>;
-                                interrupts = <21>;
-                        };
-                        usp2: usp@b00a0000 {
-                                cell-index = <2>;
-                                compatible = "sirf,prima2-usp";
-                                reg = <0xb00a0000 0x10000>;
-                                interrupts = <22>;
-                        };
-                        dmac0: dma-controller@b00b0000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-dmac";
-                                reg = <0xb00b0000 0x10000>;
-                                interrupts = <12>;
-                        };
-                        dmac1: dma-controller@b0160000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-dmac";
-                                reg = <0xb0160000 0x10000>;
-                                interrupts = <13>;
-                        };
-                        vip@b00C0000 {
-                                compatible = "sirf,prima2-vip";
-                                reg = <0xb00C0000 0x10000>;
-                        };
-                        spi0: spi@b00d0000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-spi";
-                                reg = <0xb00d0000 0x10000>;
-                                interrupts = <15>;
-                        };
-                        spi1: spi@b0170000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-spi";
-                                reg = <0xb0170000 0x10000>;
-                                interrupts = <16>;
-                        };
-                        i2c0: i2c@b00e0000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-i2c";
-                                reg = <0xb00e0000 0x10000>;
-                                interrupts = <24>;
-                        };
-                        i2c1: i2c@b00f0000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-i2c";
-                                reg = <0xb00f0000 0x10000>;
-                                interrupts = <25>;
-                        };
-                        tsc@b0110000 {
-                                compatible = "sirf,prima2-tsc";
-                                reg = <0xb0110000 0x10000>;
-                                interrupts = <33>;
-                        };
-                        gpio: gpio-controller@b0120000 {
-                                #gpio-cells = <2>;
-                                #interrupt-cells = <2>;
-                                compatible = "sirf,prima2-gpio-pinmux";
-                                reg = <0xb0120000 0x10000>;
-                                gpio-controller;
-                                interrupt-controller;
-                        };
-                        pwm@b0130000 {
-                                compatible = "sirf,prima2-pwm";
-                                reg = <0xb0130000 0x10000>;
-                        };
-                        efusesys@b0140000 {
-                                compatible = "sirf,prima2-efuse";
-                                reg = <0xb0140000 0x10000>;
-                        };
-                        pulsec@b0150000 {
-                                compatible = "sirf,prima2-pulsec";
-                                reg = <0xb0150000 0x10000>;
-                                interrupts = <48>;
-                        };
-                        pci-iobg {
-                                compatible = "sirf,prima2-pciiobg", "simple-bus";
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                ranges = <0x56000000 0x56000000 0x1b00000>;
-                                sd0: sdhci@56000000 {
-                                        cell-index = <0>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56000000 0x100000>;
-                                        interrupts = <38>;
-                                };
-                                sd1: sdhci@56100000 {
-                                        cell-index = <1>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56100000 0x100000>;
-                                        interrupts = <38>;
-                                };
-                                sd2: sdhci@56200000 {
-                                        cell-index = <2>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56200000 0x100000>;
-                                        interrupts = <23>;
-                                };
-                                sd3: sdhci@56300000 {
-                                        cell-index = <3>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56300000 0x100000>;
-                                        interrupts = <23>;
-                                };
-                                sd4: sdhci@56400000 {
-                                        cell-index = <4>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56400000 0x100000>;
-                                        interrupts = <39>;
-                                };
-                                sd5: sdhci@56500000 {
-                                        cell-index = <5>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56500000 0x100000>;
-                                        interrupts = <39>;
-                                };
-                                pci-copy@57900000 {
-                                        compatible = "sirf,prima2-pcicp";
-                                        reg = <0x57900000 0x100000>;
-                                        interrupts = <40>;
-                                };
-                                rom-interface@57a00000 {
-                                        compatible = "sirf,prima2-romif";
-                                        reg = <0x57a00000 0x100000>;
-                                };
-                        };
-                };
-                rtc-iobg {
-                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x80030000 0x10000>;
-                        gpsrtc@1000 {
-                                compatible = "sirf,prima2-gpsrtc";
-                                reg = <0x1000 0x1000>;
-                                interrupts = <55 56 57>;
-                        };
-                        sysrtc@2000 {
-                                compatible = "sirf,prima2-sysrtc";
-                                reg = <0x2000 0x1000>;
-                                interrupts = <52 53 54>;
-                        };
-                        pwrc@3000 {
-                                compatible = "sirf,prima2-pwrc";
-                                reg = <0x3000 0x1000>;
-                                interrupts = <32>;
-                        };
-                };
-                uus-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0xb8000000 0xb8000000 0x40000>;
-                        usb0: usb@b00e0000 {
-                                compatible = "chipidea,ci13611a-prima2";
-                                reg = <0xb8000000 0x10000>;
-                                interrupts = <10>;
-                        };
-                        usb1: usb@b00f0000 {
-                                compatible = "chipidea,ci13611a-prima2";
-                                reg = <0xb8010000 0x10000>;
-                                interrupts = <11>;
-                        };
-                        sata@b00f0000 {
-                                compatible = "synopsys,dwc-ahsata";
-                                reg = <0xb8020000 0x10000>;
-                                interrupts = <37>;
-                        };
-                        security@b00f0000 {
-                                compatible = "sirf,prima2-security";
-                                reg = <0xb8030000 0x10000>;
-                                interrupts = <42>;
-                        };
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts
new file mode 100644
index 000000000000..57286b4e7b87
--- /dev/null
+++ b/arch/arm/boot/dts/prima2-evb.dts
@@ -0,0 +1,37 @@
+/*
+ * DTS file for CSR SiRFprimaII Evaluation Board
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "prima2.dtsi"
+/ {
+        model = "CSR SiRFprimaII Evaluation Board";
+        compatible = "sirf,prima2", "sirf,prima2-cb";
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+        axi {
+                peri-iobg {
+                        uart@b0060000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&uart1_pins_a>;
+                        };
+                        spi@b00d0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi0_pins_a>;
+                        };
+                        spi@b0170000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi1_pins_a>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
new file mode 100644
index 000000000000..055fca542120
--- /dev/null
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -0,0 +1,640 @@
+/*
+ * DTS file for CSR SiRFprimaII SoC
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "sirf,prima2";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&intc>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <32768>;
+                        i-cache-size = <32768>;
+                        /* from bootloader */
+                        timebase-frequency = <0>;
+                        bus-frequency = <0>;
+                        clock-frequency = <0>;
+                };
+        };
+        axi {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x40000000 0x40000000 0x80000000>;
+                l2-cache-controller@80040000 {
+                        compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
+                        reg = <0x80040000 0x1000>;
+                        interrupts = <59>;
+                        arm,tag-latency = <1 1 1>;
+                        arm,data-latency = <1 1 1>;
+                        arm,filter-ranges = <0 0x40000000>;
+                };
+                intc: interrupt-controller@80020000 {
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        compatible = "sirf,prima2-intc";
+                        reg = <0x80020000 0x1000>;
+                };
+                sys-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x88000000 0x88000000 0x40000>;
+                        clock-controller@88000000 {
+                                compatible = "sirf,prima2-clkc";
+                                reg = <0x88000000 0x1000>;
+                                interrupts = <3>;
+                        };
+                        reset-controller@88010000 {
+                                compatible = "sirf,prima2-rstc";
+                                reg = <0x88010000 0x1000>;
+                        };
+                        rsc-controller@88020000 {
+                                compatible = "sirf,prima2-rsc";
+                                reg = <0x88020000 0x1000>;
+                        };
+                };
+                mem-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x90000000 0x90000000 0x10000>;
+                        memory-controller@90000000 {
+                                compatible = "sirf,prima2-memc";
+                                reg = <0x90000000 0x10000>;
+                                interrupts = <27>;
+                        };
+                };
+                disp-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x90010000 0x90010000 0x30000>;
+                        display@90010000 {
+                                compatible = "sirf,prima2-lcd";
+                                reg = <0x90010000 0x20000>;
+                                interrupts = <30>;
+                        };
+                        vpp@90020000 {
+                                compatible = "sirf,prima2-vpp";
+                                reg = <0x90020000 0x10000>;
+                                interrupts = <31>;
+                        };
+                };
+                graphics-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x98000000 0x98000000 0x8000000>;
+                        graphics@98000000 {
+                                compatible = "powervr,sgx531";
+                                reg = <0x98000000 0x8000000>;
+                                interrupts = <6>;
+                        };
+                };
+                multimedia-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xa0000000 0xa0000000 0x8000000>;
+                        multimedia@a0000000 {
+                                compatible = "sirf,prima2-video-codec";
+                                reg = <0xa0000000 0x8000000>;
+                                interrupts = <5>;
+                        };
+                };
+                dsp-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xa8000000 0xa8000000 0x2000000>;
+                        dspif@a8000000 {
+                                compatible = "sirf,prima2-dspif";
+                                reg = <0xa8000000 0x10000>;
+                                interrupts = <9>;
+                        };
+                        gps@a8010000 {
+                                compatible = "sirf,prima2-gps";
+                                reg = <0xa8010000 0x10000>;
+                                interrupts = <7>;
+                        };
+                        dsp@a9000000 {
+                                compatible = "sirf,prima2-dsp";
+                                reg = <0xa9000000 0x1000000>;
+                                interrupts = <8>;
+                        };
+                };
+                peri-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xb0000000 0xb0000000 0x180000>;
+                        timer@b0020000 {
+                                compatible = "sirf,prima2-tick";
+                                reg = <0xb0020000 0x1000>;
+                                interrupts = <0>;
+                        };
+                        nand@b0030000 {
+                                compatible = "sirf,prima2-nand";
+                                reg = <0xb0030000 0x10000>;
+                                interrupts = <41>;
+                        };
+                        audio@b0040000 {
+                                compatible = "sirf,prima2-audio";
+                                reg = <0xb0040000 0x10000>;
+                                interrupts = <35>;
+                        };
+                        uart0: uart@b0050000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0050000 0x10000>;
+                                interrupts = <17>;
+                        };
+                        uart1: uart@b0060000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0060000 0x10000>;
+                                interrupts = <18>;
+                        };
+                        uart2: uart@b0070000 {
+                                cell-index = <2>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0070000 0x10000>;
+                                interrupts = <19>;
+                        };
+                        usp0: usp@b0080000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb0080000 0x10000>;
+                                interrupts = <20>;
+                        };
+                        usp1: usp@b0090000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb0090000 0x10000>;
+                                interrupts = <21>;
+                        };
+                        usp2: usp@b00a0000 {
+                                cell-index = <2>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb00a0000 0x10000>;
+                                interrupts = <22>;
+                        };
+                        dmac0: dma-controller@b00b0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-dmac";
+                                reg = <0xb00b0000 0x10000>;
+                                interrupts = <12>;
+                        };
+                        dmac1: dma-controller@b0160000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-dmac";
+                                reg = <0xb0160000 0x10000>;
+                                interrupts = <13>;
+                        };
+                        vip@b00C0000 {
+                                compatible = "sirf,prima2-vip";
+                                reg = <0xb00C0000 0x10000>;
+                        };
+                        spi0: spi@b00d0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-spi";
+                                reg = <0xb00d0000 0x10000>;
+                                interrupts = <15>;
+                        };
+                        spi1: spi@b0170000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-spi";
+                                reg = <0xb0170000 0x10000>;
+                                interrupts = <16>;
+                        };
+                        i2c0: i2c@b00e0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-i2c";
+                                reg = <0xb00e0000 0x10000>;
+                                interrupts = <24>;
+                        };
+                        i2c1: i2c@b00f0000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-i2c";
+                                reg = <0xb00f0000 0x10000>;
+                                interrupts = <25>;
+                        };
+                        tsc@b0110000 {
+                                compatible = "sirf,prima2-tsc";
+                                reg = <0xb0110000 0x10000>;
+                                interrupts = <33>;
+                        };
+                        gpio: pinctrl@b0120000 {
+                                #gpio-cells = <2>;
+                                #interrupt-cells = <2>;
+                                compatible = "sirf,prima2-pinctrl";
+                                reg = <0xb0120000 0x10000>;
+                                interrupts = <43 44 45 46 47>;
+                                gpio-controller;
+                                interrupt-controller;
+                                lcd_16pins_a: lcd0@0 {
+                                        lcd {
+                                                sirf,pins = "lcd_16bitsgrp";
+                                                sirf,function = "lcd_16bits";
+                                        };
+                                };
+                                lcd_18pins_a: lcd0@1 {
+                                        lcd {
+                                                sirf,pins = "lcd_18bitsgrp";
+                                                sirf,function = "lcd_18bits";
+                                        };
+                                };
+                                lcd_24pins_a: lcd0@2 {
+                                        lcd {
+                                                sirf,pins = "lcd_24bitsgrp";
+                                                sirf,function = "lcd_24bits";
+                                        };
+                                };
+                                lcdrom_pins_a: lcdrom0@0 {
+                                        lcd {
+                                                sirf,pins = "lcdromgrp";
+                                                sirf,function = "lcdrom";
+                                        };
+                                };
+                                uart0_pins_a: uart0@0 {
+                                        uart {
+                                                sirf,pins = "uart0grp";
+                                                sirf,function = "uart0";
+                                        };
+                                };
+                                uart1_pins_a: uart1@0 {
+                                        uart {
+                                                sirf,pins = "uart1grp";
+                                                sirf,function = "uart1";
+                                        };
+                                };
+                                uart2_pins_a: uart2@0 {
+                                        uart {
+                                                sirf,pins = "uart2grp";
+                                                sirf,function = "uart2";
+                                        };
+                                };
+                                uart2_noflow_pins_a: uart2@1 {
+                                        uart {
+                                                sirf,pins = "uart2_nostreamctrlgrp";
+                                                sirf,function = "uart2_nostreamctrl";
+                                        };
+                                };
+                                spi0_pins_a: spi0@0 {
+                                        spi {
+                                                sirf,pins = "spi0grp";
+                                                sirf,function = "spi0";
+                                        };
+                                };
+                                spi1_pins_a: spi1@0 {
+                                        spi {
+                                                sirf,pins = "spi1grp";
+                                                sirf,function = "spi1";
+                                        };
+                                };
+                                i2c0_pins_a: i2c0@0 {
+                                        i2c {
+                                                sirf,pins = "i2c0grp";
+                                                sirf,function = "i2c0";
+                                        };
+                                };
+                                i2c1_pins_a: i2c1@0 {
+                                        i2c {
+                                                sirf,pins = "i2c1grp";
+                                                sirf,function = "i2c1";
+                                        };
+                                };
+                                pwm0_pins_a: pwm0@0 {
+                                        pwm {
+                                                sirf,pins = "pwm0grp";
+                                                sirf,function = "pwm0";
+                                        };
+                                };
+                                pwm1_pins_a: pwm1@0 {
+                                        pwm {
+                                                sirf,pins = "pwm1grp";
+                                                sirf,function = "pwm1";
+                                        };
+                                };
+                                pwm2_pins_a: pwm2@0 {
+                                        pwm {
+                                                sirf,pins = "pwm2grp";
+                                                sirf,function = "pwm2";
+                                        };
+                                };
+                                pwm3_pins_a: pwm3@0 {
+                                        pwm {
+                                                sirf,pins = "pwm3grp";
+                                                sirf,function = "pwm3";
+                                        };
+                                };
+                                gps_pins_a: gps@0 {
+                                        gps {
+                                                sirf,pins = "gpsgrp";
+                                                sirf,function = "gps";
+                                        };
+                                };
+                                vip_pins_a: vip@0 {
+                                        vip {
+                                                sirf,pins = "vipgrp";
+                                                sirf,function = "vip";
+                                        };
+                                };
+                                sdmmc0_pins_a: sdmmc0@0 {
+                                        sdmmc0 {
+                                                sirf,pins = "sdmmc0grp";
+                                                sirf,function = "sdmmc0";
+                                        };
+                                };
+                                sdmmc1_pins_a: sdmmc1@0 {
+                                        sdmmc1 {
+                                                sirf,pins = "sdmmc1grp";
+                                                sirf,function = "sdmmc1";
+                                        };
+                                };
+                                sdmmc2_pins_a: sdmmc2@0 {
+                                        sdmmc2 {
+                                                sirf,pins = "sdmmc2grp";
+                                                sirf,function = "sdmmc2";
+                                        };
+                                };
+                                sdmmc3_pins_a: sdmmc3@0 {
+                                        sdmmc3 {
+                                                sirf,pins = "sdmmc3grp";
+                                                sirf,function = "sdmmc3";
+                                        };
+                                };
+                                sdmmc4_pins_a: sdmmc4@0 {
+                                        sdmmc4 {
+                                                sirf,pins = "sdmmc4grp";
+                                                sirf,function = "sdmmc4";
+                                        };
+                                };
+                                sdmmc5_pins_a: sdmmc5@0 {
+                                        sdmmc5 {
+                                                sirf,pins = "sdmmc5grp";
+                                                sirf,function = "sdmmc5";
+                                        };
+                                };
+                                i2s_pins_a: i2s@0 {
+                                        i2s {
+                                                sirf,pins = "i2sgrp";
+                                                sirf,function = "i2s";
+                                        };
+                                };
+                                ac97_pins_a: ac97@0 {
+                                        ac97 {
+                                                sirf,pins = "ac97grp";
+                                                sirf,function = "ac97";
+                                        };
+                                };
+                                nand_pins_a: nand@0 {
+                                        nand {
+                                                sirf,pins = "nandgrp";
+                                                sirf,function = "nand";
+                                        };
+                                };
+                                usp0_pins_a: usp0@0 {
+                                        usp0 {
+                                                sirf,pins = "usp0grp";
+                                                sirf,function = "usp0";
+                                        };
+                                };
+                                usp1_pins_a: usp1@0 {
+                                        usp1 {
+                                                sirf,pins = "usp1grp";
+                                                sirf,function = "usp1";
+                                        };
+                                };
+                                usp2_pins_a: usp2@0 {
+                                        usp2 {
+                                                sirf,pins = "usp2grp";
+                                                sirf,function = "usp2";
+                                        };
+                                };
+                                usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
+                                        usb0_utmi_drvbus {
+                                                sirf,pins = "usb0_utmi_drvbusgrp";
+                                                sirf,function = "usb0_utmi_drvbus";
+                                        };
+                                };
+                                usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
+                                        usb1_utmi_drvbus {
+                                                sirf,pins = "usb1_utmi_drvbusgrp";
+                                                sirf,function = "usb1_utmi_drvbus";
+                                        };
+                                };
+                                warm_rst_pins_a: warm_rst@0 {
+                                        warm_rst {
+                                                sirf,pins = "warm_rstgrp";
+                                                sirf,function = "warm_rst";
+                                        };
+                                };
+                                pulse_count_pins_a: pulse_count@0 {
+                                        pulse_count {
+                                                sirf,pins = "pulse_countgrp";
+                                                sirf,function = "pulse_count";
+                                        };
+                                };
+                                cko0_rst_pins_a: cko0_rst@0 {
+                                        cko0_rst {
+                                                sirf,pins = "cko0_rstgrp";
+                                                sirf,function = "cko0_rst";
+                                        };
+                                };
+                                cko1_rst_pins_a: cko1_rst@0 {
+                                        cko1_rst {
+                                                sirf,pins = "cko1_rstgrp";
+                                                sirf,function = "cko1_rst";
+                                        };
+                                };
+                        };
+                        pwm@b0130000 {
+                                compatible = "sirf,prima2-pwm";
+                                reg = <0xb0130000 0x10000>;
+                        };
+                        efusesys@b0140000 {
+                                compatible = "sirf,prima2-efuse";
+                                reg = <0xb0140000 0x10000>;
+                        };
+                        pulsec@b0150000 {
+                                compatible = "sirf,prima2-pulsec";
+                                reg = <0xb0150000 0x10000>;
+                                interrupts = <48>;
+                        };
+                        pci-iobg {
+                                compatible = "sirf,prima2-pciiobg", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0x56000000 0x56000000 0x1b00000>;
+                                sd0: sdhci@56000000 {
+                                        cell-index = <0>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56000000 0x100000>;
+                                        interrupts = <38>;
+                                };
+                                sd1: sdhci@56100000 {
+                                        cell-index = <1>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56100000 0x100000>;
+                                        interrupts = <38>;
+                                };
+                                sd2: sdhci@56200000 {
+                                        cell-index = <2>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56200000 0x100000>;
+                                        interrupts = <23>;
+                                };
+                                sd3: sdhci@56300000 {
+                                        cell-index = <3>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56300000 0x100000>;
+                                        interrupts = <23>;
+                                };
+                                sd4: sdhci@56400000 {
+                                        cell-index = <4>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56400000 0x100000>;
+                                        interrupts = <39>;
+                                };
+                                sd5: sdhci@56500000 {
+                                        cell-index = <5>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56500000 0x100000>;
+                                        interrupts = <39>;
+                                };
+                                pci-copy@57900000 {
+                                        compatible = "sirf,prima2-pcicp";
+                                        reg = <0x57900000 0x100000>;
+                                        interrupts = <40>;
+                                };
+                                rom-interface@57a00000 {
+                                        compatible = "sirf,prima2-romif";
+                                        reg = <0x57a00000 0x100000>;
+                                };
+                        };
+                };
+                rtc-iobg {
+                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x80030000 0x10000>;
+                        gpsrtc@1000 {
+                                compatible = "sirf,prima2-gpsrtc";
+                                reg = <0x1000 0x1000>;
+                                interrupts = <55 56 57>;
+                        };
+                        sysrtc@2000 {
+                                compatible = "sirf,prima2-sysrtc";
+                                reg = <0x2000 0x1000>;
+                                interrupts = <52 53 54>;
+                        };
+                        pwrc@3000 {
+                                compatible = "sirf,prima2-pwrc";
+                                reg = <0x3000 0x1000>;
+                                interrupts = <32>;
+                        };
+                };
+                uus-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xb8000000 0xb8000000 0x40000>;
+                        usb0: usb@b00e0000 {
+                                compatible = "chipidea,ci13611a-prima2";
+                                reg = <0xb8000000 0x10000>;
+                                interrupts = <10>;
+                        };
+                        usb1: usb@b00f0000 {
+                                compatible = "chipidea,ci13611a-prima2";
+                                reg = <0xb8010000 0x10000>;
+                                interrupts = <11>;
+                        };
+                        sata@b00f0000 {
+                                compatible = "synopsys,dwc-ahsata";
+                                reg = <0xb8020000 0x10000>;
+                                interrupts = <37>;
+                        };
+                        security@b00f0000 {
+                                compatible = "sirf,prima2-security";
+                                reg = <0xb8030000 0x10000>;
+                                interrupts = <42>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
new file mode 100644
index 000000000000..d7c5d721a5c7
--- /dev/null
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -0,0 +1,14 @@
+/* The pxa3xx skeleton simply augments the 2xx version */
+/include/ "pxa2xx.dtsi"
+/ {
+        model = "Marvell PXA27x familiy SoC";
+        compatible = "marvell,pxa27x";
+        pxabus {
+                pxairq: interrupt-controller@40d00000 {
+                        marvell,intc-priority;
+                        marvell,intc-nr-irqs = <34>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
new file mode 100644
index 000000000000..f18aad35e8b3
--- /dev/null
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -0,0 +1,132 @@
+/*
+ * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        model = "Marvell PXA2xx family SoC";
+        compatible = "marvell,pxa2xx";
+        interrupt-parent = <&pxairq>;
+        aliases {
+                serial0 = &ffuart;
+                serial1 = &btuart;
+                serial2 = &stuart;
+                serial3 = &hwuart;
+                i2c0 = &pwri2c;
+                i2c1 = &pxai2c1;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,xscale";
+                };
+        };
+        pxabus {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                pxairq: interrupt-controller@40d00000 {
+                        #interrupt-cells = <1>;
+                        compatible = "marvell,pxa-intc";
+                        interrupt-controller;
+                        interrupt-parent;
+                        marvell,intc-nr-irqs = <32>;
+                        reg = <0x40d00000 0xd0>;
+                };
+                gpio: gpio@40e00000 {
+                        compatible = "mrvl,pxa-gpio";
+                        #address-cells = <0x1>;
+                        #size-cells = <0x1>;
+                        reg = <0x40e00000 0x10000>;
+                        gpio-controller;
+                        #gpio-cells = <0x2>;
+                        interrupts = <10>;
+                        interrupt-names = "gpio_mux";
+                        interrupt-controller;
+                        #interrupt-cells = <0x2>;
+                        ranges;
+                        gcb0: gpio@40e00000 {
+                                reg = <0x40e00000 0x4>;
+                        };
+                        gcb1: gpio@40e00004 {
+                                reg = <0x40e00004 0x4>;
+                        };
+                        gcb2: gpio@40e00008 {
+                                reg = <0x40e00008 0x4>;
+                        };
+                        gcb3: gpio@40e0000c {
+                                reg = <0x40e0000c 0x4>;
+                        };
+                };
+                ffuart: uart@40100000 {
+                        compatible = "mrvl,pxa-uart";
+                        reg = <0x40100000 0x30>;
+                        interrupts = <22>;
+                        status = "disabled";
+                };
+                btuart: uart@40200000 {
+                        compatible = "mrvl,pxa-uart";
+                        reg = <0x40200000 0x30>;
+                        interrupts = <21>;
+                        status = "disabled";
+                };
+                stuart: uart@40700000 {
+                        compatible = "mrvl,pxa-uart";
+                        reg = <0x40700000 0x30>;
+                        interrupts = <20>;
+                        status = "disabled";
+                };
+                hwuart: uart@41100000 {
+                        compatible = "mrvl,pxa-uart";
+                        reg = <0x41100000 0x30>;
+                        interrupts = <7>;
+                        status = "disabled";
+                };
+                pxai2c1: i2c@40301680 {
+                        compatible = "mrvl,pxa-i2c";
+                        reg = <0x40301680 0x30>;
+                        interrupts = <18>;
+                        #address-cells = <0x1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                usb0: ohci@4c000000 {
+                        compatible = "mrvl,pxa-ohci";
+                        reg = <0x4c000000 0x10000>;
+                        interrupts = <3>;
+                        status = "disabled";
+                };
+                mmc0: mmc@41100000 {
+                        compatible = "mrvl,pxa-mmc";
+                        reg = <0x41100000 0x1000>;
+                        interrupts = <23>;
+                        status = "disabled";
+                };
+                rtc@40900000 {
+                        compatible = "marvell,pxa-rtc";
+                        reg = <0x40900000 0x3c>;
+                        interrupts = <30 31>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
new file mode 100644
index 000000000000..f9d92da86783
--- /dev/null
+++ b/arch/arm/boot/dts/pxa3xx.dtsi
@@ -0,0 +1,32 @@
+/* The pxa3xx skeleton simply augments the 2xx version */
+/include/ "pxa2xx.dtsi"
+/ {
+        model = "Marvell PXA3xx familiy SoC";
+        compatible = "marvell,pxa3xx";
+        pxabus {
+                pwri2c: i2c@40f500c0 {
+                        compatible = "mrvl,pwri2c";
+                        reg = <0x40f500c0 0x30>;
+                        interrupts = <6>;
+                        #address-cells = <0x1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                nand0: nand@43100000 {
+                        compatible = "marvell,pxa3xx-nand";
+                        reg = <0x43100000 90>;
+                        interrupts = <45>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;      
+                        status = "disabled";
+                };
+                pxairq: interrupt-controller@40d00000 {
+                        marvell,intc-priority;
+                        marvell,intc-nr-irqs = <56>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
index e92be5a474e7..595492aa5053 100644
--- a/arch/arm/boot/dts/pxa910-dkb.dts
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -29,6 +29,143 @@
                        };
                        twsi1: i2c@d4011000 {
                                status = "okay";
+                                pmic: 88pm860x@34 {
+                                        compatible = "marvell,88pm860x";
+                                        reg = <0x34>;
+                                        interrupts = <4>;
+                                        interrupt-parent = <&intc>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <1>;
+                                        marvell,88pm860x-irq-read-clr;
+                                        marvell,88pm860x-slave-addr = <0x11>;
+                                        regulators {
+                                                BUCK1 {
+                                                        regulator-min-microvolt = <1000000>;
+                                                        regulator-max-microvolt = <1500000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                BUCK2 {
+                                                        regulator-min-microvolt = <1000000>;
+                                                        regulator-max-microvolt = <1500000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                BUCK3 {
+                                                        regulator-min-microvolt = <1000000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO1 {
+                                                        regulator-min-microvolt = <1200000>;
+                                                        regulator-max-microvolt = <2800000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO2 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO3 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO4 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
+                                                };
+                                                LDO5 {
+                                                        regulator-min-microvolt = <2900000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO6 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO7 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <2900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO8 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <2900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO9 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO10 {
+                                                        regulator-min-microvolt = <1200000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO12 {
+                                                        regulator-min-microvolt = <1200000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
+                                                };
+                                                LDO13 {
+                                                        regulator-min-microvolt = <1200000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
+                                                };
+                                                LDO14 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
+                                                };
+                                        };
+                                        rtc {
+                                                marvell,88pm860x-vrtc = <1>;
+                                        };
+                                        touch {
+                                                marvell,88pm860x-gpadc-prebias = <1>;
+                                                marvell,88pm860x-gpadc-slot-cycle = <1>;
+                                                marvell,88pm860x-tsi-prebias = <6>;
+                                                marvell,88pm860x-pen-prebias = <16>;
+                                                marvell,88pm860x-pen-prechg = <2>;
+                                                marvell,88pm860x-resistor-X = <300>;
+                                        };
+                                        backlights {
+                                                backlight-0 {
+                                                        marvell,88pm860x-iset = <4>;
+                                                        marvell,88pm860x-pwm = <3>;
+                                                };
+                                                backlight-2 {
+                                                };
+                                        };
+                                        leds {
+                                                led0-red {
+                                                        marvell,88pm860x-iset = <12>;
+                                                };
+                                                led0-green {
+                                                        marvell,88pm860x-iset = <12>;
+                                                };
+                                                led0-blue {
+                                                        marvell,88pm860x-iset = <12>;
+                                                };
+                                        };
+                                };
                        };
                        rtc: rtc@d4010000 {
                                status = "okay";
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index aebf32de73b4..825aaca33034 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -25,6 +25,11 @@
                interrupt-parent = <&intc>;
                ranges;
+                L2: l2-cache {
+                        compatible = "marvell,tauros2-cache";
+                        marvell,tauros2-cache-features = <0x3>;
+                };
                axi@d4200000 {  /* AXI */
                        compatible = "mrvl,axi-bus", "simple-bus";
                        #address-cells = <1>;
@@ -115,6 +120,8 @@
                        twsi1: i2c@d4011000 {
                                compatible = "mrvl,mmp-twsi";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                reg = <0xd4011000 0x1000>;
                                interrupts = <7>;
                                mrvl,i2c-fast-mode;
@@ -123,6 +130,8 @@
                        twsi2: i2c@d4037000 {
                                compatible = "mrvl,mmp-twsi";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                reg = <0xd4037000 0x1000>;
                                interrupts = <54>;
                                status = "disabled";
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 7e334d4cae21..702c0baa6004 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -10,7 +10,7 @@
 */
 /dts-v1/;
-/include/ "db8500.dtsi"
+/include/ "dbx5x0.dtsi"
 / {
        model = "Calao Systems Snowball platform with device tree";
@@ -83,6 +83,22 @@
        };
        soc-u9500 {
+                sound {
+                        compatible = "stericsson,snd-soc-mop500";
+                        stericsson,cpu-dai = <&msp1 &msp3>;
+                        stericsson,audio-codec = <&codec>;
+                };
+                msp1: msp@80124000 {
+                        status = "okay";
+                };
+                msp3: msp@80125000 {
+                        status = "okay";
+                };
                external-bus@50000000 {
                        status = "okay";
@@ -111,7 +127,6 @@
                        mmc-cap-mmc-highspeed;
                        vmmc-supply = <&ab8500_ldo_aux3_reg>;
-                        #gpio-cells = <1>;
                        cd-gpios  = <&gpio6 26 0x4>; // 218
                        cd-inverted;
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index d71b8d581e3d..1e7c7a8e2123 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -80,8 +80,7 @@
                };
                sdhci@70000000 {
-                        int-gpio = <&gpio1 0 0>;
+                        cd-gpios = <&gpio1 0 0>;
-                        power-gpio = <&gpio1 2 1>;
                        status = "okay";
                };
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index e4e912f95024..082328bd64ab 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -103,8 +103,6 @@
                };
                sdhci@70000000 {
-                        power-gpio = <&gpio0 2 1>;
-                        power_always_enb;
                        status = "okay";
                };
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index f146dbf6f7f8..c3ef1ad26b6a 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -275,6 +275,160 @@
        i2c@7000d000 {
                status = "okay";
                clock-frequency = <400000>;
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+                        ti,system-power-controller;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        sys-supply = <&vdd_5v0_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "vdd_sm0,vdd_core";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "vdd_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "vdd_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+                                regulator@4 {
+                                        reg = <4>;
+                                        regulator-compatible = "ldo0";
+                                        regulator-name = "vdd_ldo0,vddio_pex_clk";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "vdd_ldo3,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vdd_ldo5,vcore_mmc";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "vdd_ldo6,avdd_vdac";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_ldo7,avdd_hdmi";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "vdd_rtc_out,vdd_cell";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
        };
        pmc {
@@ -310,6 +464,72 @@
                bus-width = <8>;
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vdd_5v0_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+                regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "vdd_1v5";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        gpio = <&pmic 0 0>;
+                };
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "vdd_1v2";
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                        gpio = <&pmic 1 0>;
+                        enable-active-high;
+                };
+                regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "vdd_1v05";
+                        regulator-min-microvolt = <1050000>;
+                        regulator-max-microvolt = <1050000>;
+                        gpio = <&pmic 2 0>;
+                        enable-active-high;
+                        /* Hack until board-harmony-pcie.c is removed */
+                        status = "disabled";
+                };
+                regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "vdd_pnl";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        gpio = <&gpio 22 0>; /* gpio PC6 */
+                        enable-active-high;
+                };
+                regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "vdd_bl";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        gpio = <&gpio 176 0>; /* gpio PW0 */
+                        enable-active-high;
+                };
+        };
        sound {
                compatible = "nvidia,tegra-audio-wm8903-harmony",
                             "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
new file mode 100644
index 000000000000..a2d6d6541f83
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -0,0 +1,58 @@
+/dts-v1/;
+/include/ "tegra20-tamonten.dtsi"
+/ {
+        model = "Avionic Design Medcom-Wide board";
+        compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
+        i2c@7000c000 {
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <187 0x04>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = <0xffffffff
+                                    0xffffffff
+                                    0
+                                    0xffffffff
+                                    0xffffffff>;
+                };
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+        sound {
+                compatible = "ad,tegra-audio-wm8903-medcom-wide",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "Avionic Design Medcom-Wide";
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 684a9e1ff7e9..ddf287f52d49 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -272,12 +272,170 @@
                status = "okay";
                clock-frequency = <400000>;
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        sys-supply = <&p5valw_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "+1.2vs_sm0,vdd_core";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "+1.0vs_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "+3.7vs_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+                                /* LDO0 is not connected to anything */
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "+1.1vs_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "+1.2vs_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "+3.3vs_ldo3,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "+2.85vs_ldo5,vcore_mmc";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        /*
+                                         * Research indicates this should be
+                                         * 1.8v; other boards that use this
+                                         * rail for the same purpose need it
+                                         * set to 1.8v. The schematic signal
+                                         * name is incorrect; perhaps copied
+                                         * from an incorrect NVIDIA reference.
+                                         */
+                                        regulator-name = "+2.85vs_ldo6,avdd_vdac";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "+3.3vs_ldo7,avdd_hdmi";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "+3.3vs_rtc";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
                adt7461@4c {
                        compatible = "adi,adt7461";
                        reg = <0x4c>;
                };
        };
+        pmc {
+                nvidia,invert-interrupt;
+        };
        usb@c5000000 {
                status = "okay";
        };
@@ -325,6 +483,21 @@
                };
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                p5valw_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "+5valw";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+        };
        sound {
                compatible = "nvidia,tegra-audio-alc5632-paz00",
                        "nvidia,tegra-audio-alc5632";
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
new file mode 100644
index 000000000000..331a3ef24d59
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -0,0 +1,50 @@
+/dts-v1/;
+/include/ "tegra20-tamonten.dtsi"
+/ {
+        model = "Avionic Design Plutux board";
+        compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
+        i2c@7000c000 {
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <187 0x04>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = <0xffffffff
+                                    0xffffffff
+                                    0
+                                    0xffffffff
+                                    0xffffffff>;
+                };
+        };
+        sound {
+                compatible = "ad,tegra-audio-plutux",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "Avionic Design Plutux";
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 85e621ab2968..f0ba901676ac 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -374,6 +374,154 @@
                status = "okay";
                clock-frequency = <400000>;
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+                        ti,system-power-controller;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        sys-supply = <&vdd_5v0_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "vdd_sm0,vdd_core";
+                                        regulator-min-microvolt = <1300000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                };
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "vdd_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1125000>;
+                                        regulator-max-microvolt = <1125000>;
+                                        regulator-always-on;
+                                };
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "vdd_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+                                /* LDO0 is not connected to anything */
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "vdd_ldo3,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vdd_ldo5,vcore_mmc";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "vdd_rtc_out,vdd_cell";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
                temperature-sensor@4c {
                        compatible = "nct1008";
                        reg = <0x4c>;
@@ -387,7 +535,11 @@
                };
        };
-        memory-controller@0x7000f400 {
+        pmc {
+                nvidia,invert-interrupt;
+        };
+        memory-controller@7000f400 {
                emc-table@190000 {
                        reg = <190000>;
                        compatible = "nvidia,tegra20-emc-table";
@@ -473,6 +625,40 @@
                };
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vdd_5v0_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+                regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "vdd_1v5";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        gpio = <&pmic 0 0>;
+                };
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "vdd_1v2";
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                        gpio = <&pmic 1 0>;
+                        enable-active-high;
+                };
+        };
        sound {
                compatible = "nvidia,tegra-audio-wm8903-seaboard",
                             "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
new file mode 100644
index 000000000000..f18cec9f6a77
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -0,0 +1,449 @@
+/include/ "tegra20.dtsi"
+/ {
+        model = "Avionic Design Tamonten SOM";
+        compatible = "ad,tamonten", "nvidia,tegra20";
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+        pinmux {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata";
+                                nvidia,function = "ide";
+                        };
+                        atb {
+                                nvidia,pins = "atb", "gma", "gme";
+                                nvidia,function = "sdio4";
+                        };
+                        atc {
+                                nvidia,pins = "atc";
+                                nvidia,function = "nand";
+                        };
+                        atd {
+                                nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+                                        "spia", "spib", "spic";
+                                nvidia,function = "gmi";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap2 {
+                                nvidia,pins = "dap2";
+                                nvidia,function = "dap2";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtd";
+                                nvidia,function = "sdio2";
+                        };
+                        dtb {
+                                nvidia,pins = "dtb", "dtc", "dte";
+                                nvidia,function = "rsvd1";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gmc {
+                                nvidia,pins = "gmc";
+                                nvidia,function = "uartd";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv", "slxa", "slxk";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint", "pta";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uarta";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+                                        "ld3", "ld4", "ld5", "ld6", "ld7",
+                                        "ld8", "ld9", "ld10", "ld11", "ld12",
+                                        "ld13", "ld14", "ld15", "ld16", "ld17",
+                                        "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+                                        "lhs", "lm0", "lm1", "lpp", "lpw0",
+                                        "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+                                        "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+                                        "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        owc {
+                                nvidia,pins = "owc", "spdi", "spdo", "uac";
+                                nvidia,function = "rsvd2";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdb {
+                                nvidia,pins = "sdb", "sdc", "sdd";
+                                nvidia,function = "pwm";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        slxc {
+                                nvidia,pins = "slxc", "slxd";
+                                nvidia,function = "spdif";
+                        };
+                        spid {
+                                nvidia,pins = "spid", "spie", "spif";
+                                nvidia,function = "spi1";
+                        };
+                        spig {
+                                nvidia,pins = "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+                                        "cdev1", "cdev2", "dap1", "dtb", "gma",
+                                        "gmb", "gmc", "gmd", "gme", "gpu7",
+                                        "gpv", "i2cp", "pta", "rm", "slxa",
+                                        "slxk", "spia", "spib", "uac";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+                                        "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_csus {
+                                nvidia,pins = "csus", "spid", "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_crtp {
+                                nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+                                        "dtc", "dte", "dtf", "gpu", "sdio1",
+                                        "slxc", "slxd", "spdi", "spdo", "spig",
+                                        "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ddc {
+                                nvidia,pins = "ddc", "dta", "dtd", "kbca",
+                                        "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+                                        "sdc";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_hdint {
+                                nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+                                        "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+                                        "lvp0", "owc", "sdb";
+                                nvidia,tristate = <1>;
+                        };
+                        conf_irrx {
+                                nvidia,pins = "irrx", "irtx", "sdd", "spic",
+                                        "spie", "spih", "uaa", "uab", "uad",
+                                        "uca", "ucb";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_lc {
+                                nvidia,pins = "lc", "ls";
+                                nvidia,pull = <2>;
+                        };
+                        conf_ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lm0", "lpp",
+                                        "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+                                        "lvs", "pmc";
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                };
+        };
+        i2s@70002800 {
+                status = "okay";
+        };
+        serial@70006300 {
+                clock-frequency = <216000000>;
+                status = "okay";
+        };
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+                status = "okay";
+        };
+        i2c@7000d000 {
+                clock-frequency = <400000>;
+                status = "okay";
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+                        ti,system-power-controller;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        sys-supply = <&vdd_5v0_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "vdd_sys_sm0,vdd_core";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "vdd_sys_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "vdd_sys_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+                                regulator@4 {
+                                        reg = <4>;
+                                        regulator-compatible = "ldo0";
+                                        regulator-name = "vdd_ldo0,vddio_pex_clk";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "vdd_ldo3,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vdd_ldo5,vcore_mmc";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                };
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "vdd_ldo6,avdd_vdac";
+                                        /*
+                                         * According to the Tegra 2 Automotive
+                                         * DataSheet, a typical value for this
+                                         * would be 2.8V, but the PMIC only
+                                         * supports 2.85V.
+                                         */
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                };
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_ldo7,avdd_hdmi";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
+                                        /*
+                                         * According to the Tegra 2 Automotive
+                                         * DataSheet, a typical value for this
+                                         * would be 2.8V, but the PMIC only
+                                         * supports 2.85V.
+                                         */
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "vdd_rtc_out";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+        pmc {
+                nvidia,invert-interrupt;
+        };
+        usb@c5008000 {
+                status = "okay";
+        };
+        sdhci@c8000600 {
+                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+                wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+                bus-width = <4>;
+                status = "okay";
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vdd_5v0_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
new file mode 100644
index 000000000000..9aff31b0fe4a
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -0,0 +1,53 @@
+/dts-v1/;
+/include/ "tegra20-tamonten.dtsi"
+/ {
+        model = "Avionic Design Tamonten Evaluation Carrier";
+        compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+                status = "okay";
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <187 0x04>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = <0xffffffff
+                                    0xffffffff
+                                    0
+                                    0xffffffff
+                                    0xffffffff>;
+                };
+        };
+        sound {
+                compatible = "ad,tegra-audio-wm8903-tec",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "Avionic Design TEC";
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index be90544e6b59..3e5952fcfbc5 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -289,6 +289,158 @@
        i2c@7000d000 {
                status = "okay";
                clock-frequency = <400000>;
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+                        ti,system-power-controller;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        sys-supply = <&vdd_5v0_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "vdd_sm0,vdd_core";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "vdd_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "vdd_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+                                /* LDO0 is not connected to anything */
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "vdd_ldo3,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vdd_ldo5,vcore_mmc";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "vdd_ldo6,avdd_vdac";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "vdd_rtc_out,vdd_cell";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+        pmc {
+                nvidia,invert-interrupt;
        };
        usb@c5000000 {
@@ -317,6 +469,60 @@
                bus-width = <8>;
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vdd_5v0_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+                regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "vdd_1v5";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        gpio = <&pmic 0 0>;
+                };
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "vdd_1v2";
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                        gpio = <&pmic 1 0>;
+                        enable-active-high;
+                };
+                regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "vdd_pnl";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        gpio = <&gpio 22 0>; /* gpio PC6 */
+                        enable-active-high;
+                };
+                regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "vdd_bl";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        gpio = <&gpio 176 0>; /* gpio PW0 */
+                        enable-active-high;
+                };
+        };
        sound {
                compatible = "nvidia,tegra-audio-wm8903-ventana",
                             "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 6916310bf58f..c636d002d6d8 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -261,6 +261,286 @@
                        gpio-controller;
                        #gpio-cells = <2>;
                };
+                max8907@3c {
+                        compatible = "maxim,max8907";
+                        reg = <0x3c>;
+                        interrupts = <0 86 0x4>;
+                        maxim,system-power-controller;
+                        mbatt-supply = <&usb0_vbus_reg>;
+                        in-v1-supply = <&mbatt_reg>;
+                        in-v2-supply = <&mbatt_reg>;
+                        in-v3-supply = <&mbatt_reg>;
+                        in1-supply = <&mbatt_reg>;
+                        in2-supply = <&nvvdd_sv3_reg>;
+                        in3-supply = <&mbatt_reg>;
+                        in4-supply = <&mbatt_reg>;
+                        in5-supply = <&mbatt_reg>;
+                        in6-supply = <&mbatt_reg>;
+                        in7-supply = <&mbatt_reg>;
+                        in8-supply = <&mbatt_reg>;
+                        in9-supply = <&mbatt_reg>;
+                        in10-supply = <&mbatt_reg>;
+                        in11-supply = <&mbatt_reg>;
+                        in12-supply = <&mbatt_reg>;
+                        in13-supply = <&mbatt_reg>;
+                        in14-supply = <&mbatt_reg>;
+                        in15-supply = <&mbatt_reg>;
+                        in16-supply = <&mbatt_reg>;
+                        in17-supply = <&nvvdd_sv3_reg>;
+                        in18-supply = <&nvvdd_sv3_reg>;
+                        in19-supply = <&mbatt_reg>;
+                        in20-supply = <&mbatt_reg>;
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                mbatt_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "mbatt";
+                                        regulator-name = "vbat_pmu";
+                                        regulator-always-on;
+                                };
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sd1";
+                                        regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sd2";
+                                        regulator-name = "nvvdd_sv2,vdd_core";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                nvvdd_sv3_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sd3";
+                                        regulator-name = "nvvdd_sv3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                regulator@4 {
+                                        reg = <4>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "nvvdd_ldo2,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "nvvdd_ldo3,vcom_1v8b";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "nvvdd_ldo4,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "nvvdd_ldo7,avddio_audio";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                };
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "nvvdd_ldo9,avdd_cam*";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo10";
+                                        regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                };
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo11";
+                                        regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                regulator@15 {
+                                        reg = <15>;
+                                        regulator-compatible = "ldo12";
+                                        regulator-name = "nvvdd_ldo12,vddio_sdio";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+                                regulator@16 {
+                                        reg = <16>;
+                                        regulator-compatible = "ldo13";
+                                        regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                regulator@17 {
+                                        reg = <17>;
+                                        regulator-compatible = "ldo14";
+                                        regulator-name = "nvvdd_ldo14,avdd_vdac";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                regulator@18 {
+                                        reg = <18>;
+                                        regulator-compatible = "ldo15";
+                                        regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                regulator@19 {
+                                        reg = <19>;
+                                        regulator-compatible = "ldo16";
+                                        regulator-name = "nvvdd_ldo16,vdd_dbrtr";
+                                        regulator-min-microvolt = <1300000>;
+                                        regulator-max-microvolt = <1300000>;
+                                };
+                                regulator@20 {
+                                        reg = <20>;
+                                        regulator-compatible = "ldo17";
+                                        regulator-name = "nvvdd_ldo17,vddio_mipi";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+                                regulator@21 {
+                                        reg = <21>;
+                                        regulator-compatible = "ldo18";
+                                        regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                regulator@22 {
+                                        reg = <22>;
+                                        regulator-compatible = "ldo19";
+                                        regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                regulator@23 {
+                                        reg = <23>;
+                                        regulator-compatible = "ldo20";
+                                        regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                regulator@24 {
+                                        reg = <24>;
+                                        regulator-compatible = "out5v";
+                                        regulator-name = "usb0_vbus_reg";
+                                };
+                                regulator@25 {
+                                        reg = <25>;
+                                        regulator-compatible = "out33v";
+                                        regulator-name = "pmu_out3v3";
+                                };
+                                regulator@26 {
+                                        reg = <26>;
+                                        regulator-compatible = "bbat";
+                                        regulator-name = "pmu_bbat";
+                                        regulator-min-microvolt = <2400000>;
+                                        regulator-max-microvolt = <2400000>;
+                                        regulator-always-on;
+                                };
+                                regulator@27 {
+                                        reg = <27>;
+                                        regulator-compatible = "sdby";
+                                        regulator-name = "vdd_aon";
+                                        regulator-always-on;
+                                };
+                                regulator@28 {
+                                        reg = <28>;
+                                        regulator-compatible = "vrtc";
+                                        regulator-name = "vrtc,pmu_vccadc";
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+        pmc {
+                nvidia,invert-interrupt;
        };
        usb@c5000000 {
@@ -284,6 +564,21 @@
                bus-width = <8>;
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                usb0_vbus_reg: regulator {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+        };
        sound {
                compatible = "nvidia,tegra-audio-wm8753-whistler",
                             "nvidia,tegra-audio-wm8753";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 405d1673904e..f3a09d0d45bc 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -123,7 +123,7 @@
                status = "disabled";
        };
-        pwm {
+        pwm: pwm {
                compatible = "nvidia,tegra20-pwm";
                reg = <0x7000a000 0x100>;
                #pwm-cells = <2>;
@@ -170,7 +170,7 @@
                reg = <0x7000e400 0x400>;
        };
-        memory-controller@0x7000f000 {
+        memory-controller@7000f000 {
                compatible = "nvidia,tegra20-mc";
                reg = <0x7000f000 0x024
                       0x7000f03c 0x3c4>;
@@ -183,7 +183,7 @@
                       0x58000000 0x02000000>;  /* GART aperture */
        };
-        memory-controller@0x7000f400 {
+        memory-controller@7000f400 {
                compatible = "nvidia,tegra20-emc";
                reg = <0x7000f400 0x200>;
                #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
new file mode 100644
index 000000000000..dd4222f00eca
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -0,0 +1,87 @@
+/dts-v1/;
+/include/ "tegra30-cardhu.dtsi"
+/* This dts file support the cardhu A02 version of board */
+/ {
+        model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
+        compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                ddr_reg: regulator@100 {
+                        compatible = "regulator-fixed";
+                        reg = <100>;
+                        regulator-name = "vdd_ddr";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&pmic 6 0>;
+                };
+                sys_3v3_reg: regulator@101 {
+                        compatible = "regulator-fixed";
+                        reg = <101>;
+                        regulator-name = "sys_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&pmic 7 0>;
+                };
+                usb1_vbus_reg: regulator@102 {
+                        compatible = "regulator-fixed";
+                        reg = <102>;
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 68 0>; /* GPIO PI4 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+                usb3_vbus_reg: regulator@103 {
+                        compatible = "regulator-fixed";
+                        reg = <103>;
+                        regulator-name = "usb3_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 63 0>; /* GPIO PH7 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+                vdd_5v0_reg: regulator@104 {
+                        compatible = "regulator-fixed";
+                        reg = <104>;
+                        regulator-name = "5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&pmic 2 0>;
+                };
+                vdd_bl_reg: regulator@105 {
+                        compatible = "regulator-fixed";
+                        reg = <105>;
+                        regulator-name = "vdd_bl";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 83 0>; /* GPIO PK3 */
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
new file mode 100644
index 000000000000..0828f097ca86
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -0,0 +1,98 @@
+/dts-v1/;
+/include/ "tegra30-cardhu.dtsi"
+/* This dts file support the cardhu A04 and later versions of board */
+/ {
+        model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
+        compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                ddr_reg: regulator@100 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "ddr";
+                        reg = <100>;
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&pmic 7 0>;
+                };
+                sys_3v3_reg: regulator@101 {
+                        compatible = "regulator-fixed";
+                        reg = <101>;
+                        regulator-name = "sys_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&pmic 6 0>;
+                };
+                usb1_vbus_reg: regulator@102 {
+                        compatible = "regulator-fixed";
+                        reg = <102>;
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 238 0>; /* GPIO PDD6 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+                usb3_vbus_reg: regulator@103 {
+                        compatible = "regulator-fixed";
+                        reg = <103>;
+                        regulator-name = "usb3_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 236 0>; /* GPIO PDD4 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+                vdd_5v0_reg: regulator@104 {
+                        compatible = "regulator-fixed";
+                        reg = <104>;
+                        regulator-name = "5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&pmic 8 0>;
+                };
+                vdd_bl_reg: regulator@105 {
+                        compatible = "regulator-fixed";
+                        reg = <105>;
+                        regulator-name = "vdd_bl";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 234 0>; /* GPIO PDD2 */
+                };
+                vdd_bl2_reg: regulator@106 {
+                        compatible = "regulator-fixed";
+                        reg = <106>;
+                        regulator-name = "vdd_bl2";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 232 0>; /* GPIO PDD0 */
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts
deleted file mode 100644
index c169bced131e..000000000000
--- a/arch/arm/boot/dts/tegra30-cardhu.dts
+++ /dev/null
@@ -1,171 +0,0 @@
-/dts-v1/;
-/include/ "tegra30.dtsi"
-/ {
-        model = "NVIDIA Tegra30 Cardhu evaluation board";
-        compatible = "nvidia,cardhu", "nvidia,tegra30";
-        memory {
-                reg = <0x80000000 0x40000000>;
-        };
-        pinmux {
-                pinctrl-names = "default";
-                pinctrl-0 = <&state_default>;
-                state_default: pinmux {
-                        sdmmc1_clk_pz0 {
-                                nvidia,pins = "sdmmc1_clk_pz0";
-                                nvidia,function = "sdmmc1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                        };
-                        sdmmc1_cmd_pz1 {
-                                nvidia,pins =   "sdmmc1_cmd_pz1",
-                                                "sdmmc1_dat0_py7",
-                                                "sdmmc1_dat1_py6",
-                                                "sdmmc1_dat2_py5",
-                                                "sdmmc1_dat3_py4";
-                                nvidia,function = "sdmmc1";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                        };
-                        sdmmc4_clk_pcc4 {
-                                nvidia,pins =   "sdmmc4_clk_pcc4",
-                                                "sdmmc4_rst_n_pcc3";
-                                nvidia,function = "sdmmc4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                        };
-                        sdmmc4_dat0_paa0 {
-                                nvidia,pins =   "sdmmc4_dat0_paa0",
-                                                "sdmmc4_dat1_paa1",
-                                                "sdmmc4_dat2_paa2",
-                                                "sdmmc4_dat3_paa3",
-                                                "sdmmc4_dat4_paa4",
-                                                "sdmmc4_dat5_paa5",
-                                                "sdmmc4_dat6_paa6",
-                                                "sdmmc4_dat7_paa7";
-                                nvidia,function = "sdmmc4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                        };
-                        dap2_fs_pa2 {
-                                nvidia,pins =   "dap2_fs_pa2",
-                                                "dap2_sclk_pa3",
-                                                "dap2_din_pa4",
-                                                "dap2_dout_pa5";
-                                nvidia,function = "i2s1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                        };
-                };
-        };
-        serial@70006000 {
-                status = "okay";
-                clock-frequency = <408000000>;
-        };
-        i2c@7000c000 {
-                status = "okay";
-                clock-frequency = <100000>;
-        };
-        i2c@7000c400 {
-                status = "okay";
-                clock-frequency = <100000>;
-        };
-        i2c@7000c500 {
-                status = "okay";
-                clock-frequency = <100000>;
-                /* ALS and Proximity sensor */
-                isl29028@44 {
-                        compatible = "isil,isl29028";
-                        reg = <0x44>;
-                        interrupt-parent = <&gpio>;
-                        interrupts = <88 0x04>; /*gpio PL0 */
-                };
-        };
-        i2c@7000c700 {
-                status = "okay";
-                clock-frequency = <100000>;
-        };
-        i2c@7000d000 {
-                status = "okay";
-                clock-frequency = <100000>;
-                wm8903: wm8903@1a {
-                        compatible = "wlf,wm8903";
-                        reg = <0x1a>;
-                        interrupt-parent = <&gpio>;
-                        interrupts = <179 0x04>; /* gpio PW3 */
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        micdet-cfg = <0>;
-                        micdet-delay = <100>;
-                        gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
-                };
-                tps62361 {
-                        compatible = "ti,tps62361";
-                        reg = <0x60>;
-                        regulator-name = "tps62361-vout";
-                        regulator-min-microvolt = <500000>;
-                        regulator-max-microvolt = <1500000>;
-                        regulator-boot-on;
-                        regulator-always-on;
-                        ti,vsel0-state-high;
-                        ti,vsel1-state-high;
-                };
-        };
-        ahub {
-                i2s@70080400 {
-                        status = "okay";
-                };
-        };
-        sdhci@78000000 {
-                status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
-                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-                power-gpios = <&gpio 31 0>; /* gpio PD7 */
-                bus-width = <4>;
-        };
-        sdhci@78000600 {
-                status = "okay";
-                bus-width = <8>;
-        };
-        sound {
-                compatible = "nvidia,tegra-audio-wm8903-cardhu",
-                             "nvidia,tegra-audio-wm8903";
-                nvidia,model = "NVIDIA Tegra Cardhu";
-                nvidia,audio-routing =
-                        "Headphone Jack", "HPOUTR",
-                        "Headphone Jack", "HPOUTL",
-                        "Int Spk", "ROP",
-                        "Int Spk", "RON",
-                        "Int Spk", "LOP",
-                        "Int Spk", "LON",
-                        "Mic Jack", "MICBIAS",
-                        "IN1L", "Mic Jack";
-                nvidia,i2s-controller = <&tegra_i2s1>;
-                nvidia,audio-codec = <&wm8903>;
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
-        };
-};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
new file mode 100644
index 000000000000..d10c9c5a3606
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -0,0 +1,475 @@
+/include/ "tegra30.dtsi"
+/**
+ * This file contains common DT entry for all fab version of Cardhu.
+ * There is multiple fab version of Cardhu starting from A01 to A07.
+ * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
+ * A02 will have different sets of GPIOs for fixed regulator compare to
+ * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
+ * compatible with fab version A04. Based on Cardhu fab version, the
+ * related dts file need to be chosen like for Cardhu fab version A02,
+ * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
+ * tegra30-cardhu-a04.dts.
+ * The identification of board is done in two ways, by looking the sticker
+ * on PCB and by reading board id eeprom.
+ * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
+ * number is the fab version like here it is 002 and hence fab version A02.
+ * The (downstream internal) U-Boot of Cardhu display the board-id as
+ * follows:
+ * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
+ * In this Fab version is 02 i.e. A02.
+ * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
+ * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
+ * wide.
+ */
+/ {
+        model = "NVIDIA Tegra30 Cardhu evaluation board";
+        compatible = "nvidia,cardhu", "nvidia,tegra30";
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+        pinmux {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+                state_default: pinmux {
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins =   "sdmmc1_cmd_pz1",
+                                                "sdmmc1_dat0_py7",
+                                                "sdmmc1_dat1_py6",
+                                                "sdmmc1_dat2_py5",
+                                                "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins =   "sdmmc4_clk_pcc4",
+                                                "sdmmc4_rst_n_pcc3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins =   "sdmmc4_dat0_paa0",
+                                                "sdmmc4_dat1_paa1",
+                                                "sdmmc4_dat2_paa2",
+                                                "sdmmc4_dat3_paa3",
+                                                "sdmmc4_dat4_paa4",
+                                                "sdmmc4_dat5_paa5",
+                                                "sdmmc4_dat6_paa6",
+                                                "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        dap2_fs_pa2 {
+                                nvidia,pins =   "dap2_fs_pa2",
+                                                "dap2_sclk_pa3",
+                                                "dap2_din_pa4",
+                                                "dap2_dout_pa5";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                };
+        };
+        serial@70006000 {
+                status = "okay";
+                clock-frequency = <408000000>;
+        };
+        i2c@7000c000 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+        i2c@7000c400 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+        i2c@7000c500 {
+                status = "okay";
+                clock-frequency = <100000>;
+                /* ALS and Proximity sensor */
+                isl29028@44 {
+                        compatible = "isil,isl29028";
+                        reg = <0x44>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <88 0x04>; /*gpio PL0 */
+                };
+        };
+        i2c@7000c700 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <100000>;
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <179 0x04>; /* gpio PW3 */
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+                };
+                tps62361 {
+                        compatible = "ti,tps62361";
+                        reg = <0x60>;
+                        regulator-name = "tps62361-vout";
+                        regulator-min-microvolt = <500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        ti,vsel0-state-high;
+                        ti,vsel1-state-high;
+                };
+                pmic: tps65911@2d {
+                        compatible = "ti,tps65911";
+                        reg = <0x2d>;
+                        interrupts = <0 86 0x4>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        ti,system-power-controller;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        vcc1-supply = <&vdd_ac_bat_reg>;
+                        vcc2-supply = <&vdd_ac_bat_reg>;
+                        vcc3-supply = <&vio_reg>;
+                        vcc4-supply = <&vdd_5v0_reg>;
+                        vcc5-supply = <&vdd_ac_bat_reg>;
+                        vcc6-supply = <&vdd2_reg>;
+                        vcc7-supply = <&vdd_ac_bat_reg>;
+                        vccio-supply = <&vdd_ac_bat_reg>;
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                vdd1_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "vdd1";
+                                        regulator-name = "vddio_ddr_1v2";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                vdd2_reg: regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "vdd2";
+                                        regulator-name = "vdd_1v5_gen";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                };
+                                vddctrl_reg: regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "vddctrl";
+                                        regulator-name = "vdd_cpu,vdd_sys";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                vio_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "vio";
+                                        regulator-name = "vdd_1v8_gen";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo1_reg: regulator@4 {
+                                        reg = <4>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_pexa,vdd_pexb";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+                                ldo2_reg: regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_sata,avdd_plle";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+                                /* LDO3 is not connected to anything */
+                                ldo4_reg: regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                ldo5_reg: regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vddio_sdmmc,avdd_vdac";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                                ldo6_reg: regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+                                ldo7_reg: regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_pllm,x,u,a_p_c_s";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                ldo8_reg: regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ddr_hs";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+        ahub {
+                i2s@70080400 {
+                        status = "okay";
+                };
+        };
+        pmc {
+                status = "okay";
+                nvidia,invert-interrupt;
+        };
+        sdhci@78000000 {
+                status = "okay";
+                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+                power-gpios = <&gpio 31 0>; /* gpio PD7 */
+                bus-width = <4>;
+        };
+        sdhci@78000600 {
+                status = "okay";
+                bus-width = <8>;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vdd_ac_bat_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_ac_bat";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+                cam_1v8_reg: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "cam_1v8";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        enable-active-high;
+                        gpio = <&gpio 220 0>; /* gpio PBB4 */
+                        vin-supply = <&vio_reg>;
+                };
+                cp_5v_reg: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "cp_5v";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        enable-active-high;
+                        gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+                };
+                emmc_3v3_reg: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "emmc_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 25 0>; /* gpio PD1 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+                modem_3v3_reg: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "modem_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 30 0>; /* gpio PD6 */
+                };
+                pex_hvdd_3v3_reg: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "pex_hvdd_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 95 0>; /* gpio PL7 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+                vdd_cam1_ldo_reg: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        regulator-name = "vdd_cam1_ldo";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        enable-active-high;
+                        gpio = <&gpio 142 0>; /* gpio PR6 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+                vdd_cam2_ldo_reg: regulator@7 {
+                        compatible = "regulator-fixed";
+                        reg = <7>;
+                        regulator-name = "vdd_cam2_ldo";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        enable-active-high;
+                        gpio = <&gpio 143 0>; /* gpio PR7 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+                vdd_cam3_ldo_reg: regulator@8 {
+                        compatible = "regulator-fixed";
+                        reg = <8>;
+                        regulator-name = "vdd_cam3_ldo";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 144 0>; /* gpio PS0 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+                vdd_com_reg: regulator@9 {
+                        compatible = "regulator-fixed";
+                        reg = <9>;
+                        regulator-name = "vdd_com";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 24 0>; /* gpio PD0 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+                vdd_fuse_3v3_reg: regulator@10 {
+                        compatible = "regulator-fixed";
+                        reg = <10>;
+                        regulator-name = "vdd_fuse_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 94 0>; /* gpio PL6 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+                vdd_pnl1_reg: regulator@11 {
+                        compatible = "regulator-fixed";
+                        reg = <11>;
+                        regulator-name = "vdd_pnl1";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 92 0>; /* gpio PL4 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+                vdd_vid_reg: regulator@12 {
+                        compatible = "regulator-fixed";
+                        reg = <12>;
+                        regulator-name = "vddio_vid";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 152 0>; /* GPIO PT0 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+        };
+        sound {
+                compatible = "nvidia,tegra-audio-wm8903-cardhu",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "NVIDIA Tegra Cardhu";
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 3e4334d14efb..b1497c7d7d68 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -117,7 +117,7 @@
                status = "disabled";
        };
-        pwm {
+        pwm: pwm {
                compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
                reg = <0x7000a000 0x100>;
                #pwm-cells = <2>;
diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi
new file mode 100644
index 000000000000..a63272422d76
--- /dev/null
+++ b/arch/arm/boot/dts/tps65217.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65217.pdf
+ */
+&tps {
+        compatible = "ti,tps65217";
+        regulators {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                dcdc1_reg: regulator@0 {
+                        reg = <0>;
+                        regulator-compatible = "dcdc1";
+                };
+                dcdc2_reg: regulator@1 {
+                        reg = <1>;
+                        regulator-compatible = "dcdc2";
+                };
+                dcdc3_reg: regulator@2 {
+                        reg = <2>;
+                        regulator-compatible = "dcdc3";
+                };
+                ldo1_reg: regulator@3 {
+                        reg = <3>;
+                        regulator-compatible = "ldo1";
+                };
+                ldo2_reg: regulator@4 {
+                        reg = <4>;
+                        regulator-compatible = "ldo2";
+                };
+                ldo3_reg: regulator@5 {
+                        reg = <5>;
+                        regulator-compatible = "ldo3";
+                };
+                ldo4_reg: regulator@6 {
+                        reg = <6>;
+                        regulator-compatible = "ldo4";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi
new file mode 100644
index 000000000000..92693a89160e
--- /dev/null
+++ b/arch/arm/boot/dts/tps65910.dtsi
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65910.pdf
+ */
+&tps {
+        compatible = "ti,tps65910";
+        regulators {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vrtc_reg: regulator@0 {
+                        reg = <0>;
+                        regulator-compatible = "vrtc";
+                };
+                vio_reg: regulator@1 {
+                        reg = <1>;
+                        regulator-compatible = "vio";
+                };
+                vdd1_reg: regulator@2 {
+                        reg = <2>;
+                        regulator-compatible = "vdd1";
+                };
+                vdd2_reg: regulator@3 {
+                        reg = <3>;
+                        regulator-compatible = "vdd2";
+                };
+                vdd3_reg: regulator@4 {
+                        reg = <4>;
+                        regulator-compatible = "vdd3";
+                };
+                vdig1_reg: regulator@5 {
+                        reg = <5>;
+                        regulator-compatible = "vdig1";
+                };
+                vdig2_reg: regulator@6 {
+                        reg = <6>;
+                        regulator-compatible = "vdig2";
+                };
+                vpll_reg: regulator@7 {
+                        reg = <7>;
+                        regulator-compatible = "vpll";
+                };
+                vdac_reg: regulator@8 {
+                        reg = <8>;
+                        regulator-compatible = "vdac";
+                };
+                vaux1_reg: regulator@9 {
+                        reg = <9>;
+                        regulator-compatible = "vaux1";
+                };
+                vaux2_reg: regulator@10 {
+                        reg = <10>;
+                        regulator-compatible = "vaux2";
+                };
+                vaux33_reg: regulator@11 {
+                        reg = <11>;
+                        regulator-compatible = "vaux33";
+                };
+                vmmc_reg: regulator@12 {
+                        reg = <12>;
+                        regulator-compatible = "vmmc";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index 22f4d1394ed3..ff000172c93c 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -19,19 +19,19 @@
                interrupts = <11>;
        };
-        vdac: regulator@0 {
+        vdac: regulator-vdac {
                compatible = "ti,twl4030-vdac";
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <1800000>;
        };
-        vpll2: regulator@1 {
+        vpll2: regulator-vpll2 {
                compatible = "ti,twl4030-vpll2";
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <1800000>;
        };
-        vmmc1: regulator@2 {
+        vmmc1: regulator-vmmc1 {
                compatible = "ti,twl4030-vmmc1";
                regulator-min-microvolt = <1850000>;
                regulator-max-microvolt = <3150000>;
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index d351b27d7213..123e2c40218a 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -20,70 +20,70 @@
                interrupts = <11>;
        };
-        vaux1: regulator@0 {
+        vaux1: regulator-vaux1 {
                compatible = "ti,twl6030-vaux1";
                regulator-min-microvolt = <1000000>;
                regulator-max-microvolt = <3000000>;
        };
-        vaux2: regulator@1 {
+        vaux2: regulator-vaux2 {
                compatible = "ti,twl6030-vaux2";
                regulator-min-microvolt = <1200000>;
                regulator-max-microvolt = <2800000>;
        };
-        vaux3: regulator@2 {
+        vaux3: regulator-vaux3 {
                compatible = "ti,twl6030-vaux3";
                regulator-min-microvolt = <1000000>;
                regulator-max-microvolt = <3000000>;
        };
-        vmmc: regulator@3 {
+        vmmc: regulator-vmmc {
                compatible = "ti,twl6030-vmmc";
                regulator-min-microvolt = <1200000>;
                regulator-max-microvolt = <3000000>;
        };
-        vpp: regulator@4 {
+        vpp: regulator-vpp {
                compatible = "ti,twl6030-vpp";
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <2500000>;
        };
-        vusim: regulator@5 {
+        vusim: regulator-vusim {
                compatible = "ti,twl6030-vusim";
                regulator-min-microvolt = <1200000>;
                regulator-max-microvolt = <2900000>;
        };
-        vdac: regulator@6 {
+        vdac: regulator-vdac {
                compatible = "ti,twl6030-vdac";
        };
-        vana: regulator@7 {
+        vana: regulator-vana {
                compatible = "ti,twl6030-vana";
        };
-        vcxio: regulator@8 {
+        vcxio: regulator-vcxio {
                compatible = "ti,twl6030-vcxio";
                regulator-always-on;
        };
-        vusb: regulator@9 {
+        vusb: regulator-vusb {
                compatible = "ti,twl6030-vusb";
        };
-        v1v8: regulator@10 {
+        v1v8: regulator-v1v8 {
                compatible = "ti,twl6030-v1v8";
                regulator-always-on;
        };
-        v2v1: regulator@11 {
+        v2v1: regulator-v2v1 {
                compatible = "ti,twl6030-v2v1";
                regulator-always-on;
        };
-        clk32kg: regulator@12 {
+        clk32kg: regulator-clk32kg {
                compatible = "ti,twl6030-clk32kg";
        };
 };
diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
new file mode 100644
index 000000000000..567cf4e8ab84
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500-bv07.dts
@@ -0,0 +1,36 @@
+/*
+ * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+/dts-v1/;
+/include/ "vt8500.dtsi"
+/ {
+        model = "Benign BV07 Netbook";
+        /*
+         * Display node is based on Sascha Hauer's patch on dri-devel.
+         * Added a bpp property to calculate the size of the framebuffer
+         * until the binding is formalized.
+         */
+        display: display@0 {
+                modes {
+                        mode0: mode@0 {
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <88>;
+                                hfront-porch = <40>;
+                                hsync-len = <0>;
+                                vback-porch = <32>;
+                                vfront-porch = <11>;
+                                vsync-len = <1>;
+                                clock = <0>;    /* unused but required */
+                                bpp = <16>;     /* non-standard but required */
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
new file mode 100644
index 000000000000..d8645e990b21
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -0,0 +1,116 @@
+/*
+ * vt8500.dtsi - Device tree file for VIA VT8500 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "via,vt8500";
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                interrupt-parent = <&intc>;
+                intc: interrupt-controller@d8140000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        reg = <0xd8140000 0x10000>;
+                        #interrupt-cells = <1>;
+                };
+                gpio: gpio-controller@d8110000 {
+                        compatible = "via,vt8500-gpio";
+                        gpio-controller;
+                        reg = <0xd8110000 0x10000>;
+                        #gpio-cells = <3>;
+                };
+                pmc@d8130000 {
+                        compatible = "via,vt8500-pmc";
+                        reg = <0xd8130000 0x1000>;
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                ref24: ref24M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <24000000>;
+                                };
+                        };
+                };
+                timer@d8130100 {
+                        compatible = "via,vt8500-timer";
+                        reg = <0xd8130100 0x28>;
+                        interrupts = <36>;
+                };
+                ehci@d8007900 {
+                        compatible = "via,vt8500-ehci";
+                        reg = <0xd8007900 0x200>;
+                        interrupts = <43>;
+                };
+                uhci@d8007b00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8007b00 0x200>;
+                        interrupts = <43>;
+                };
+                fb@d800e400 {
+                        compatible = "via,vt8500-fb";
+                        reg = <0xd800e400 0x400>;
+                        interrupts = <12>;
+                        display = <&display>;
+                        default-mode = <&mode0>;
+                };
+                ge_rops@d8050400 {
+                        compatible = "wm,prizm-ge-rops";
+                        reg = <0xd8050400 0x100>;
+                };
+                uart@d8200000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8200000 0x1040>;
+                        interrupts = <32>;
+                        clocks = <&ref24>;
+                };
+                uart@d82b0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82b0000 0x1040>;
+                        interrupts = <33>;
+                        clocks = <&ref24>;
+                };
+                uart@d8210000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8210000 0x1040>;
+                        interrupts = <47>;
+                        clocks = <&ref24>;
+                };
+                uart@d82c0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82c0000 0x1040>;
+                        interrupts = <50>;
+                        clocks = <&ref24>;
+                };
+                rtc@d8100000 {
+                        compatible = "via,vt8500-rtc";
+                        reg = <0xd8100000 0x10000>;
+                        interrupts = <48>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
new file mode 100644
index 000000000000..fd4e248074c6
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505-ref.dts
@@ -0,0 +1,36 @@
+/*
+ * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+/dts-v1/;
+/include/ "wm8505.dtsi"
+/ {
+        model = "Wondermedia WM8505 Netbook";
+        /*
+         * Display node is based on Sascha Hauer's patch on dri-devel.
+         * Added a bpp property to calculate the size of the framebuffer
+         * until the binding is formalized.
+         */
+        display: display@0 {
+                modes {
+                        mode0: mode@0 {
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <88>;
+                                hfront-porch = <40>;
+                                hsync-len = <0>;
+                                vback-porch = <32>;
+                                vfront-porch = <11>;
+                                vsync-len = <1>;
+                                clock = <0>;    /* unused but required */
+                                bpp = <32>;     /* non-standard but required */
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
new file mode 100644
index 000000000000..b459691655ab
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -0,0 +1,143 @@
+/*
+ * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "wm,wm8505";
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                interrupt-parent = <&intc0>;
+                intc0: interrupt-controller@d8140000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        reg = <0xd8140000 0x10000>;
+                        #interrupt-cells = <1>;
+                };
+                /* Secondary IC cascaded to intc0 */
+                intc1: interrupt-controller@d8150000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xD8150000 0x10000>;
+                        interrupts = <56 57 58 59 60 61 62 63>;
+                };
+                gpio: gpio-controller@d8110000 {
+                        compatible = "wm,wm8505-gpio";
+                        gpio-controller;
+                        reg = <0xd8110000 0x10000>;
+                        #gpio-cells = <3>;
+                };
+                pmc@d8130000 {
+                        compatible = "via,vt8500-pmc";
+                        reg = <0xd8130000 0x1000>;
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                ref24: ref24M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <24000000>;
+                                };
+                        };
+                };
+                timer@d8130100 {
+                        compatible = "via,vt8500-timer";
+                        reg = <0xd8130100 0x28>;
+                        interrupts = <36>;
+                };
+                ehci@d8007100 {
+                        compatible = "via,vt8500-ehci";
+                        reg = <0xd8007100 0x200>;
+                        interrupts = <43>;
+                };
+                uhci@d8007300 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8007300 0x200>;
+                        interrupts = <43>;
+                };
+                fb@d8050800 {
+                        compatible = "wm,wm8505-fb";
+                        reg = <0xd8050800 0x200>;
+                        display = <&display>;
+                        default-mode = <&mode0>;
+                };
+                ge_rops@d8050400 {
+                        compatible = "wm,prizm-ge-rops";
+                        reg = <0xd8050400 0x100>;
+                };
+                uart@d8200000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8200000 0x1040>;
+                        interrupts = <32>;
+                        clocks = <&ref24>;
+                };
+                uart@d82b0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82b0000 0x1040>;
+                        interrupts = <33>;
+                        clocks = <&ref24>;
+                };
+                uart@d8210000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8210000 0x1040>;
+                        interrupts = <47>;
+                        clocks = <&ref24>;
+                };
+                uart@d82c0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82c0000 0x1040>;
+                        interrupts = <50>;
+                        clocks = <&ref24>;
+                };
+                uart@d8370000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8370000 0x1040>;
+                        interrupts = <31>;
+                        clocks = <&ref24>;
+                };
+                uart@d8380000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8380000 0x1040>;
+                        interrupts = <30>;
+                        clocks = <&ref24>;
+                };
+                rtc@d8100000 {
+                        compatible = "via,vt8500-rtc";
+                        reg = <0xd8100000 0x10000>;
+                        interrupts = <48>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
new file mode 100644
index 000000000000..cefd938f842f
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650-mid.dts
@@ -0,0 +1,36 @@
+/*
+ * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+/dts-v1/;
+/include/ "wm8650.dtsi"
+/ {
+        model = "Wondermedia WM8650-MID Tablet";
+        /*
+         * Display node is based on Sascha Hauer's patch on dri-devel.
+         * Added a bpp property to calculate the size of the framebuffer
+         * until the binding is formalized.
+         */
+        display: display@0 {
+                modes {
+                        mode0: mode@0 {
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <88>;
+                                hfront-porch = <40>;
+                                hsync-len = <0>;
+                                vback-porch = <32>;
+                                vfront-porch = <11>;
+                                vsync-len = <1>;
+                                clock = <0>;    /* unused but required */
+                                bpp = <16>;     /* non-standard but required */
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
new file mode 100644
index 000000000000..83b9467559bb
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -0,0 +1,147 @@
+/*
+ * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "wm,wm8650";
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                interrupt-parent = <&intc0>;
+                intc0: interrupt-controller@d8140000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        reg = <0xd8140000 0x10000>;
+                        #interrupt-cells = <1>;
+                };
+                /* Secondary IC cascaded to intc0 */
+                intc1: interrupt-controller@d8150000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xD8150000 0x10000>;
+                        interrupts = <56 57 58 59 60 61 62 63>;
+                };
+                gpio: gpio-controller@d8110000 {
+                        compatible = "wm,wm8650-gpio";
+                        gpio-controller;
+                        reg = <0xd8110000 0x10000>;
+                        #gpio-cells = <3>;
+                };
+                pmc@d8130000 {
+                        compatible = "via,vt8500-pmc";
+                        reg = <0xd8130000 0x1000>;
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                ref25: ref25M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <25000000>;
+                                };
+                                ref24: ref24M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <24000000>;
+                                };
+                                plla: plla {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x200>;
+                                };
+                                pllb: pllb {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x204>;
+                                };
+                                arm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+                                sdhc: sdhc {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x328>;
+                                        divisor-mask = <0x3f>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <18>;
+                                };
+                        };
+                };
+                timer@d8130100 {
+                        compatible = "via,vt8500-timer";
+                        reg = <0xd8130100 0x28>;
+                        interrupts = <36>;
+                };
+                ehci@d8007900 {
+                        compatible = "via,vt8500-ehci";
+                        reg = <0xd8007900 0x200>;
+                        interrupts = <43>;
+                };
+                uhci@d8007b00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8007b00 0x200>;
+                        interrupts = <43>;
+                };
+                fb@d8050800 {
+                        compatible = "wm,wm8505-fb";
+                        reg = <0xd8050800 0x200>;
+                        display = <&display>;
+                        default-mode = <&mode0>;
+                };
+                ge_rops@d8050400 {
+                        compatible = "wm,prizm-ge-rops";
+                        reg = <0xd8050400 0x100>;
+                };
+                uart@d8200000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8200000 0x1040>;
+                        interrupts = <32>;
+                        clocks = <&ref24>;
+                };
+                uart@d82b0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82b0000 0x1040>;
+                        interrupts = <33>;
+                        clocks = <&ref24>;
+                };
+                rtc@d8100000 {
+                        compatible = "via,vt8500-rtc";
+                        reg = <0xd8100000 0x10000>;
+                        interrupts = <48>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/xenvm-4.2.dts b/arch/arm/boot/dts/xenvm-4.2.dts
new file mode 100644
index 000000000000..ec3f9528e180
--- /dev/null
+++ b/arch/arm/boot/dts/xenvm-4.2.dts
@@ -0,0 +1,68 @@
+/*
+ * Xen Virtual Machine for unprivileged guests
+ *
+ * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU)
+ * Cortex-A15 MPCore (V2P-CA15)
+ *
+ */
+/dts-v1/;
+/ {
+        model = "XENVM-4.2";
+        compatible = "xen,xenvm-4.2", "xen,xenvm";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        chosen {
+                /* this field is going to be adjusted by the hypervisor */
+                bootargs = "console=hvc0 root=/dev/xvda";
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                };
+        };
+        memory@80000000 {
+                device_type = "memory";
+                /* this field is going to be adjusted by the hypervisor */
+                reg = <0 0x80000000 0 0x08000000>;
+        };
+        gic: interrupt-controller@2c001000 {
+                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0 0x2c001000 0 0x1000>,
+                      <0 0x2c002000 0 0x100>;
+        };
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
+        };
+        hypervisor {
+                compatible = "xen,xen-4.2", "xen,xen";
+                /* this field is going to be adjusted by the hypervisor */
+                reg = <0 0xb0000000 0 0x20000>;
+                /* this field is going to be adjusted by the hypervisor */
+                interrupts = <1 15 0xf08>;
+        };
+        motherboard {
+                arm,v2m-memory-map = "rs1";
+        };
+};
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index c4110d1b1f2d..001f4913799c 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -284,11 +284,17 @@ int dma_set_coherent_mask(struct device *dev, u64 mask)
 int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
 {
-        it8152_io.start = IT8152_IO_BASE + 0x12000;
+        /*
-        it8152_io.end   = IT8152_IO_BASE + 0x12000 + 0x100000;
+         * FIXME: use pci_ioremap_io to remap the IO space here and
+         * move over to the generic io.h implementation.
+         * This requires solving the same problem for PXA PCMCIA
+         * support.
+         */
+        it8152_io.start = (unsigned long)IT8152_IO_BASE + 0x12000;
+        it8152_io.end   = (unsigned long)IT8152_IO_BASE + 0x12000 + 0x100000;
        sys->mem_offset = 0x10000000;
-        sys->io_offset  = IT8152_IO_BASE;
+        sys->io_offset  = (unsigned long)IT8152_IO_BASE;
        if (request_resource(&ioport_resource, &it8152_io)) {
                printk(KERN_ERR "PCI: unable to allocate IO region\n");
diff --git a/arch/arm/configs/afeb9260_defconfig b/arch/arm/configs/afeb9260_defconfig
index 2afdf67c2127..c285a9d777d9 100644
--- a/arch/arm/configs/afeb9260_defconfig
+++ b/arch/arm/configs/afeb9260_defconfig
@@ -39,7 +39,6 @@ CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_ATMEL_SSC=y
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index 90610c7030f7..f78d259f8d23 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -85,6 +85,7 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=8
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
 CONFIG_I2C_SH_MOBILE=y
 # CONFIG_HWMON is not set
 CONFIG_MEDIA_SUPPORT=y
@@ -120,6 +121,8 @@ CONFIG_USB_ETH=m
 CONFIG_MMC=y
 CONFIG_MMC_SDHI=y
 CONFIG_MMC_SH_MMCIF=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_S35390A=y
 CONFIG_DMADEVICES=y
 CONFIG_SH_DMAE=y
 CONFIG_UIO=y
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
index d54e2acd3ab1..4ae57a34a582 100644
--- a/arch/arm/configs/at91rm9200_defconfig
+++ b/arch/arm/configs/at91rm9200_defconfig
@@ -232,7 +232,7 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 CONFIG_USB_MASS_STORAGE=m
 CONFIG_MMC=y
-CONFIG_MMC_AT91=y
+CONFIG_MMC_ATMELMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/at91sam9261_defconfig b/arch/arm/configs/at91sam9261_defconfig
index ade6b2f23116..1e8712ef062e 100644
--- a/arch/arm/configs/at91sam9261_defconfig
+++ b/arch/arm/configs/at91sam9261_defconfig
@@ -128,7 +128,7 @@ CONFIG_USB_GADGETFS=m
 CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
-CONFIG_MMC_AT91=m
+CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index 1cf96264cba1..d2050cada82d 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -61,7 +61,6 @@ CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_BLOCK2MTD=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
@@ -138,7 +137,7 @@ CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
 CONFIG_SDIO_UART=m
-CONFIG_MMC_AT91=m
+CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_ATMEL_PWM=y
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9g20_defconfig
index 994d331b2319..e1b0e80b54a5 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9g20_defconfig
@@ -99,7 +99,7 @@ CONFIG_USB_GADGETFS=m
 CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
-CONFIG_MMC_AT91=m
+CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/at91sam9rl_defconfig b/arch/arm/configs/at91sam9rl_defconfig
index ad562ee64209..7cf87856d63c 100644
--- a/arch/arm/configs/at91sam9rl_defconfig
+++ b/arch/arm/configs/at91sam9rl_defconfig
@@ -60,7 +60,7 @@ CONFIG_AT91SAM9X_WATCHDOG=y
 CONFIG_FB=y
 CONFIG_FB_ATMEL=y
 CONFIG_MMC=y
-CONFIG_MMC_AT91=m
+CONFIG_MMC_ATMELMCI=m
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
new file mode 100644
index 000000000000..7aea70253c63
--- /dev/null
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -0,0 +1,95 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_FHANDLE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_NAMESPACES=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_JUMP_LABEL=y
+# CONFIG_BLOCK is not set
+CONFIG_ARCH_BCM2835=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_AEABI=y
+CONFIG_COMPACTION=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_CLEANCACHE=y
+CONFIG_SECCOMP=y
+CONFIG_CC_STACKPROTECTOR=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_VFP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_UNIX98_PTYS is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_TTY_PRINTK=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_PROC_FS is not set
+# CONFIG_SYSFS is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_BOOT_PRINTK_DELAY=y
+CONFIG_SCHED_TRACER=y
+CONFIG_STACK_TRACER=y
+CONFIG_FUNCTION_PROFILER=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_KGDB=y
+CONFIG_KGDB_KDB=y
+CONFIG_TEST_KSTRTOX=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
diff --git a/arch/arm/configs/bcmring_defconfig b/arch/arm/configs/bcmring_defconfig
deleted file mode 100644
index 9e6a8fe13164..000000000000
--- a/arch/arm/configs/bcmring_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_PERF_EVENTS=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_BCMRING=y
-CONFIG_BCM_ZRELADDR=0x8000
-CONFIG_CPU_32v6K=y
-CONFIG_NO_HZ=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_ZBOOT_ROM_TEXT=0x0e000000
-CONFIG_ZBOOT_ROM_BSS=0x0ea00000
-CONFIG_ZBOOT_ROM=y
-CONFIG_NET=y
-# CONFIG_WIRELESS is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
-CONFIG_MTD_NAND_BCM_UMI=y
-CONFIG_MTD_NAND_BCM_UMI_HWCS=y
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=64
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-# CONFIG_JFFS2_FS_SECURITY is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_HEADERS_CHECK=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/cam60_defconfig b/arch/arm/configs/cam60_defconfig
index cedc92ef88ab..14579711d8fc 100644
--- a/arch/arm/configs/cam60_defconfig
+++ b/arch/arm/configs/cam60_defconfig
@@ -49,7 +49,6 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
 CONFIG_MTD_PLATRAM=m
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
index e53c47563845..4b8a25d9e686 100644
--- a/arch/arm/configs/corgi_defconfig
+++ b/arch/arm/configs/corgi_defconfig
@@ -97,7 +97,6 @@ CONFIG_MTD_BLOCK=y
 CONFIG_MTD_ROM=y
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_SHARPSL=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_IDE=y
diff --git a/arch/arm/configs/cpu9260_defconfig b/arch/arm/configs/cpu9260_defconfig
index bbf729e2fb6f..921480c23b98 100644
--- a/arch/arm/configs/cpu9260_defconfig
+++ b/arch/arm/configs/cpu9260_defconfig
@@ -82,7 +82,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 CONFIG_MMC=y
-CONFIG_MMC_AT91=m
+CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/cpu9g20_defconfig b/arch/arm/configs/cpu9g20_defconfig
index e7d7942927f3..ea116cbdffa1 100644
--- a/arch/arm/configs/cpu9g20_defconfig
+++ b/arch/arm/configs/cpu9g20_defconfig
@@ -82,7 +82,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 CONFIG_MMC=y
-CONFIG_MMC_AT91=m
+CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 8e97b2f7ceec..806005a4c4c1 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -61,7 +61,6 @@ CONFIG_MTD_CFI_STAA=y
 CONFIG_MTD_ROM=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_BLK_DEV_NBD=y
 CONFIG_EEPROM_LEGACY=y
 CONFIG_SCSI=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 3c9f32f9b6b4..66aa7a6db884 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -32,9 +32,7 @@ CONFIG_MACH_VPR200=y
 CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_MX51_3DS=y
 CONFIG_MACH_EUKREA_CPUIMX51SD=y
-CONFIG_MACH_MX51_EFIKAMX=y
+CONFIG_SOC_IMX53=y
-CONFIG_MACH_MX51_EFIKASB=y
-CONFIG_MACH_IMX53_DT=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_MXC_PWM=y
 CONFIG_SMP=y
@@ -42,7 +40,6 @@ CONFIG_VMSPLIT_2G=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
 CONFIG_VFP=y
 CONFIG_NEON=y
@@ -179,6 +176,9 @@ CONFIG_SND_SOC_IMX_MC13783=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_MXS_PHY=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index aeb3af541fed..74eee0c78f28 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -1,5 +1,7 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=19
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
@@ -15,9 +17,19 @@ CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
 CONFIG_MACH_ESATA_SHEEVAPLUG=y
 CONFIG_MACH_GURUPLUG=y
-CONFIG_MACH_DOCKSTAR=y
+CONFIG_MACH_DREAMPLUG_DT=y
+CONFIG_MACH_ICONNECT_DT=y
+CONFIG_MACH_DLINK_KIRKWOOD_DT=y
+CONFIG_MACH_IB62X0_DT=y
+CONFIG_MACH_TS219_DT=y
+CONFIG_MACH_DOCKSTAR_DT=y
+CONFIG_MACH_GOFLEXNET_DT=y
+CONFIG_MACH_LSXL_DT=y
+CONFIG_MACH_IOMEGA_IX2_200_DT=y
+CONFIG_MACH_KM_KIRKWOOD_DT=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
+CONFIG_MACH_DOCKSTAR=y
 CONFIG_MACH_OPENRD_BASE=y
 CONFIG_MACH_OPENRD_CLIENT=y
 CONFIG_MACH_OPENRD_ULTIMATE=y
@@ -29,8 +41,6 @@ CONFIG_MACH_NET2BIG_V2=y
 CONFIG_MACH_NET5BIG_V2=y
 CONFIG_MACH_T5325=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
@@ -47,13 +57,11 @@ CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IPV6 is not set
 CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_NET_PKTGEN=m
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -69,7 +77,6 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ORION=y
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=m
@@ -78,22 +85,21 @@ CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
-CONFIG_MARVELL_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
-CONFIG_NET_PCI=y
+CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_MV643XX_ETH=y
-# CONFIG_NETDEV_10000 is not set
+CONFIG_MARVELL_PHY=y
 CONFIG_LIBERTAS=y
 CONFIG_LIBERTAS_SDIO=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
+CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
@@ -103,7 +109,8 @@ CONFIG_SPI=y
 CONFIG_SPI_ORION=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
+CONFIG_WATCHDOG=y
+CONFIG_ORION_WATCHDOG=y
 CONFIG_HID_DRAGONRISE=y
 CONFIG_HID_GYRATION=y
 CONFIG_HID_TWINHAN=y
@@ -119,10 +126,8 @@ CONFIG_HID_TOPSEED=y
 CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
 CONFIG_USB_PRINTER=m
 CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_DATAFAB=y
@@ -148,7 +153,6 @@ CONFIG_MV_XOR=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
 CONFIG_UDF_FS=m
@@ -158,7 +162,6 @@ CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
@@ -171,11 +174,8 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 CONFIG_CRYPTO_CBC=m
 CONFIG_CRYPTO_PCBC=m
diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig
index 26146ffea1a5..8c49df66cac3 100644
--- a/arch/arm/configs/kzm9d_defconfig
+++ b/arch/arm/configs/kzm9d_defconfig
@@ -8,6 +8,7 @@ CONFIG_LOG_BUF_SHIFT=16
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 2388c8610627..c88b57886e79 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -14,6 +14,7 @@ CONFIG_NAMESPACES=y
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_FORCE_LOAD=y
@@ -22,7 +23,6 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_SHMOBILE=y
-CONFIG_KEYBOARD_GPIO_POLLED=y
 CONFIG_ARCH_SH73A0=y
 CONFIG_MACH_KZM9G=y
 CONFIG_MEMORY_START=0x41000000
@@ -70,6 +70,7 @@ CONFIG_INPUT_SPARSEKMAP=y
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ST1232=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index e42a0e3d4c3a..92386b20bd09 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -133,7 +133,6 @@ CONFIG_SND_DEBUG_VERBOSE=y
 # CONFIG_SND_ARM is not set
 # CONFIG_SND_SPI is not set
 CONFIG_SND_SOC=y
-# CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
@@ -149,6 +148,7 @@ CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_PCA9532=y
 CONFIG_LEDS_PCA9532_GPIO=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
@@ -161,10 +161,13 @@ CONFIG_RTC_DRV_DS1374=y
 CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_LPC32XX=y
 CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
 CONFIG_STAGING=y
 CONFIG_LPC32XX_ADC=y
-CONFIG_MAX517=y
 CONFIG_IIO=y
+CONFIG_MAX517=y
+CONFIG_PWM=y
+CONFIG_PWM_LPC32XX=y
 CONFIG_EXT2_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_MSDOS_FS=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 864f9a5c39dd..53382b6c8bb4 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -1,13 +1,14 @@
 # CONFIG_ARM_PATCH_PHYS_VIRT is not set
 CONFIG_EXPERIMENTAL=y
 CONFIG_KERNEL_LZMA=y
+CONFIG_NO_HZ=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
-# CONFIG_BLOCK is not set
+# CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_SHMOBILE=y
 CONFIG_ARCH_R8A7779=y
 CONFIG_MACH_MARZEN=y
@@ -21,7 +22,6 @@ CONFIG_ARM_ERRATA_458693=y
 CONFIG_ARM_ERRATA_460075=y
 CONFIG_ARM_ERRATA_743622=y
 CONFIG_ARM_ERRATA_754322=y
-CONFIG_NO_HZ=y
 CONFIG_SMP=y
 # CONFIG_ARM_CPU_TOPOLOGY is not set
 CONFIG_AEABI=y
@@ -29,13 +29,16 @@ CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
+CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on"
 CONFIG_CMDLINE_FORCE=y
 CONFIG_KEXEC=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
+CONFIG_UNIX=y
 CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
@@ -68,17 +71,21 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_RCAR_THERMAL=y
 CONFIG_SSB=y
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
-# CONFIG_FILE_LOCKING is not set
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY_USER is not set
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_INFO_REDUCED=y
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
index 082175c54e7c..00630e6af45c 100644
--- a/arch/arm/configs/mini2440_defconfig
+++ b/arch/arm/configs/mini2440_defconfig
@@ -102,7 +102,6 @@ CONFIG_MTD_CFI_STAA=y
 CONFIG_MTD_RAM=y
 CONFIG_MTD_ROM=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_S3C2410=y
 CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_MTD_LPDDR=y
diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 5a584520db2f..f1cb95e58af0 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -16,7 +16,7 @@ CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=128M user_debug=255"
+CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=128M user_debug=255 earlyprintk"
 CONFIG_VFP=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -90,6 +90,9 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_DYNAMIC_DEBUG is not set
 CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_MMP_UART3=y
+CONFIG_EARLY_PRINTK=y
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
new file mode 100644
index 000000000000..159f75fc4377
--- /dev/null
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -0,0 +1,57 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_MACH_ARMADA_370=y
+CONFIG_MACH_ARMADA_XP=y
+CONFIG_ARCH_HIGHBANK=y
+CONFIG_ARCH_SOCFPGA=y
+# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_SMP=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_NET=y
+CONFIG_ATA=y
+CONFIG_SATA_HIGHBANK=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_CALXEDA_XGMAC=y
+CONFIG_SMSC911X=y
+CONFIG_STMMAC_ETH=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_IPMI_HANDLER=y
+CONFIG_IPMI_SI=y
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_GPIOLIB=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_USB=y
+CONFIG_USB_ISP1760_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EDAC=y
+CONFIG_EDAC_MM_EDAC=y
+CONFIG_EDAC_HIGHBANK_MC=y
+CONFIG_EDAC_HIGHBANK_L2=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_DMADEVICES=y
+CONFIG_PL330_DMA=y
diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig
index 7305ebddb510..1f08219c1b3c 100644
--- a/arch/arm/configs/mv78xx0_defconfig
+++ b/arch/arm/configs/mv78xx0_defconfig
@@ -49,7 +49,6 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_ORION=y
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_SCSI_PROC_FS is not set
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2e86b31c33cf..7bcf850eddcd 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -21,6 +21,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 4edcfb4e4dee..048aaca60814 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -23,12 +23,6 @@ CONFIG_BLK_DEV_INTEGRITY=y
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_MXS=y
 CONFIG_MACH_MXS_DT=y
-CONFIG_MACH_MX23EVK=y
-CONFIG_MACH_MX28EVK=y
-CONFIG_MACH_STMP378X_DEVB=y
-CONFIG_MACH_TX28=y
-CONFIG_MACH_M28EVK=y
-CONFIG_MACH_APX4DEVKIT=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -59,6 +53,9 @@ CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 # CONFIG_BLK_DEV is not set
 CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_M25P80
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_GPMI_NAND=y
 CONFIG_NETDEVICES=y
@@ -88,13 +85,13 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MXS=y
 CONFIG_SPI=y
 CONFIG_SPI_GPIO=m
+CONFIG_SPI_MXS=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 # CONFIG_MFD_SUPPORT is not set
 CONFIG_DISPLAY_SUPPORT=m
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
@@ -109,14 +106,45 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 CONFIG_SND_SOC_SGTL5000=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_FB=y
+CONFIG_FB_MXS=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_LOGO=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_MMC=y
 CONFIG_MMC_MXS=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1307=m
 CONFIG_RTC_DRV_STMP=y
 CONFIG_DMADEVICES=y
 CONFIG_MXS_DMA=y
+CONFIG_STAGING=y
+CONFIG_MXS_LRADC=y
+CONFIG_IIO_SYSFS_TRIGGER=y
 CONFIG_COMMON_CLK_DEBUG=y
+CONFIG_IIO=y
+CONFIG_PWM=y
+CONFIG_PWM_MXS=y
 CONFIG_EXT3_FS=y
 # CONFIG_DNOTIFY is not set
 CONFIG_FSCACHE=m
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index bf123c5384d4..240b25eea565 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -57,7 +57,6 @@ CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ECC_SMC=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_NOMADIK=y
 CONFIG_MTD_ONENAND=y
 CONFIG_MTD_ONENAND_VERIFY_WRITE=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index e58edc36b406..62303043db9c 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -123,6 +123,7 @@ CONFIG_HW_RANDOM=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_SPI=y
 CONFIG_SPI_OMAP24XX=y
+CONFIG_PINCTRL_SINGLE=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_TWL4030=y
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index a288d7033950..cd5e6ba9a54d 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -72,7 +72,6 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_MTD_NAND_ORION=y
 CONFIG_BLK_DEV_LOOP=y
diff --git a/arch/arm/configs/pnx4008_defconfig b/arch/arm/configs/pnx4008_defconfig
deleted file mode 100644
index 35a31ccacc32..000000000000
--- a/arch/arm/configs/pnx4008_defconfig
+++ /dev/null
@@ -1,472 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_AUDIT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_ARCH_PNX4008=y
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-CONFIG_PM=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_IPV6_PRIVACY=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_NETFILTER=y
-CONFIG_IP_VS=m
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_DECNET_NF_GRABULATOR=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_IP_SCTP=m
-CONFIG_ATM=y
-CONFIG_ATM_CLIP=y
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_DECNET=m
-CONFIG_LLC2=m
-CONFIG_IPX=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_ECONET=m
-CONFIG_ECONET_AUNUDP=y
-CONFIG_ECONET_NATIVE=y
-CONFIG_WAN_ROUTER=m
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_PKTGEN=m
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTD_DOC2000=m
-CONFIG_MTD_DOC2001=m
-CONFIG_MTD_DOC2001PLUS=m
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_NANDSIM=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_DEBUG=m
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_BONDING=m
-CONFIG_EQUALIZER=m
-CONFIG_TUN=m
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_WAN=y
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_DLCI=m
-CONFIG_WAN_ROUTER_DRIVERS=m
-CONFIG_LAPBETHER=m
-CONFIG_X25_ASY=m
-CONFIG_ATM_TCP=m
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
-CONFIG_PPPOATM=m
-CONFIG_SLIP=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_VSXXXAA=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=y
-CONFIG_JOYSTICK_IFORCE_232=y
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_JOYDUMP=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_RAW=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_USBPCWATCHDOG=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SEQUENCER_OSS=y
-CONFIG_SND_DUMMY=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SOUND_PRIME=m
-CONFIG_USB_HID=m
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_SL811_HCD=m
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_RIO500=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_LED=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_TEST=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DUMMY_HCD=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_MMC=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=m
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_REISERFS_FS=m
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_STATISTICS=y
-CONFIG_XFS_FS=m
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=m
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_TMPFS=y
-CONFIG_ADFS_FS=m
-CONFIG_AFFS_FS=m
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_CRAMFS=y
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_ROMFS_FS=m
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V4=y
-CONFIG_RPCSEC_GSS_SPKM3=m
-CONFIG_SMB_FS=m
-CONFIG_CIFS=m
-CONFIG_NCP_FS=m
-CONFIG_NCPFS_PACKET_SIGNING=y
-CONFIG_NCPFS_IOCTL_LOCKING=y
-CONFIG_NCPFS_STRONG=y
-CONFIG_NCPFS_NFS_NS=y
-CONFIG_NCPFS_OS2_NS=y
-CONFIG_NCPFS_NLS=y
-CONFIG_NCPFS_EXTRAS=y
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_ACORN_PARTITION=y
-CONFIG_ACORN_PARTITION_ICS=y
-CONFIG_ACORN_PARTITION_RISCIX=y
-CONFIG_OSF_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_ATARI_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_SGI_PARTITION=y
-CONFIG_ULTRIX_PARTITION=y
-CONFIG_SUN_PARTITION=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_SECURITY=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRC16=m
diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig
index c328ac65479a..807d4e2acb17 100644
--- a/arch/arm/configs/prima2_defconfig
+++ b/arch/arm/configs/prima2_defconfig
@@ -1,4 +1,6 @@
 CONFIG_EXPERIMENTAL=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_RELAY=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_ALL=y
@@ -8,9 +10,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_BSD_DISKLABEL=y
 CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_ARCH_PRIMA2=y
+CONFIG_ARCH_SIRF=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_KEXEC=y
@@ -36,7 +36,6 @@ CONFIG_SPI=y
 CONFIG_SPI_SIRF=y
 CONFIG_SPI_SPIDEV=y
 # CONFIG_HWMON is not set
-# CONFIG_HID_SUPPORT is not set
 CONFIG_USB_GADGET=y
 CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_MASS_STORAGE=m
diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig
index 1677a0607ca9..60e313834b3f 100644
--- a/arch/arm/configs/pxa3xx_defconfig
+++ b/arch/arm/configs/pxa3xx_defconfig
@@ -36,7 +36,6 @@ CONFIG_MTD_CONCAT=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_PXA3xx=y
 CONFIG_MTD_NAND_PXA3xx_BUILTIN=y
 CONFIG_MTD_ONENAND=y
diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig
index 1cd381e1d47d..191118caa5c0 100644
--- a/arch/arm/configs/pxa910_defconfig
+++ b/arch/arm/configs/pxa910_defconfig
@@ -17,7 +17,7 @@ CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M"
+CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M earlyprintk"
 CONFIG_FPE_NWFPE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -66,5 +66,7 @@ CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_MMP_UART2=y
+CONFIG_EARLY_PRINTK=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/qil-a9260_defconfig b/arch/arm/configs/qil-a9260_defconfig
index 9160f3b7751f..42d5db1876ab 100644
--- a/arch/arm/configs/qil-a9260_defconfig
+++ b/arch/arm/configs/qil-a9260_defconfig
@@ -50,7 +50,6 @@ CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
@@ -87,7 +86,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 CONFIG_MMC=y
-CONFIG_MMC_AT91=m
+CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig
index ba6a515086b5..3a186d653dac 100644
--- a/arch/arm/configs/s3c6400_defconfig
+++ b/arch/arm/configs/s3c6400_defconfig
@@ -9,11 +9,14 @@ CONFIG_ARCH_S3C64XX=y
 CONFIG_S3C_BOOT_ERROR_RESET=y
 CONFIG_MACH_SMDK6400=y
 CONFIG_MACH_ANW6410=y
+CONFIG_MACH_MINI6410=y
+CONFIG_MACH_REAL6410=y
 CONFIG_MACH_SMDK6410=y
 CONFIG_MACH_NCP=y
 CONFIG_MACH_HMT=y
 CONFIG_MACH_SMARTQ5=y
 CONFIG_MACH_SMARTQ7=y
+CONFIG_MACH_WLF_CRAGG_6410=y
 CONFIG_CPU_32v6K=y
 CONFIG_AEABI=y
 CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc initrd=0x51000000,6M ramdisk_size=6144"
diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
index ecf2531523a1..b4384af1bea6 100644
--- a/arch/arm/configs/sam9_l9260_defconfig
+++ b/arch/arm/configs/sam9_l9260_defconfig
@@ -39,7 +39,7 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_RESERVE=3
+CONFIG_MTD_UBI_BEB_LIMIT=25
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
index 70158273c6dd..df77931a4326 100644
--- a/arch/arm/configs/spitz_defconfig
+++ b/arch/arm/configs/spitz_defconfig
@@ -94,7 +94,6 @@ CONFIG_MTD_BLOCK=y
 CONFIG_MTD_ROM=y
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_SHARPSL=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_IDE=y
diff --git a/arch/arm/configs/stamp9g20_defconfig b/arch/arm/configs/stamp9g20_defconfig
index d5e260b8b160..52f1488591c7 100644
--- a/arch/arm/configs/stamp9g20_defconfig
+++ b/arch/arm/configs/stamp9g20_defconfig
@@ -100,7 +100,6 @@ CONFIG_USB_ETH=m
 CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
-# CONFIG_MMC_AT91 is not set
 CONFIG_MMC_ATMELMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index db2245353f0f..e2184f6c20b3 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -24,11 +24,11 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_TEGRA=y
+CONFIG_GPIO_PCA953X=y
 CONFIG_ARCH_TEGRA_2x_SOC=y
 CONFIG_ARCH_TEGRA_3x_SOC=y
-CONFIG_MACH_HARMONY=y
+CONFIG_TEGRA_PCI=y
-CONFIG_MACH_PAZ00=y
+CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA=y
-CONFIG_MACH_TRIMSLICE=y
 CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
@@ -67,7 +67,18 @@ CONFIG_INET6_IPCOMP=y
 CONFIG_IPV6_MIP6=y
 CONFIG_IPV6_TUNNEL=y
 CONFIG_IPV6_MULTIPLE_TABLES=y
-# CONFIG_WIRELESS is not set
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIBTUSB=m
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_GPIO=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
@@ -87,7 +98,8 @@ CONFIG_USB_PEGASUS=y
 CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
-# CONFIG_WLAN is not set
+CONFIG_RT2X00=y
+CONFIG_RT2800USB=m
 CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
@@ -105,25 +117,31 @@ CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
 CONFIG_SPI_TEGRA=y
-CONFIG_GPIO_TPS65910=y
+CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GPIO_TPS6586X=y
+CONFIG_GPIO_TPS65910=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_BATTERY_SBS=y
 CONFIG_SENSORS_LM90=y
 CONFIG_MFD_TPS6586X=y
 CONFIG_MFD_TPS65910=y
+CONFIG_MFD_MAX8907=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MAX8907=y
 CONFIG_REGULATOR_TPS62360=y
 CONFIG_REGULATOR_TPS6586X=y
 CONFIG_REGULATOR_TPS65910=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
 CONFIG_SOUND=y
 CONFIG_SND=y
 # CONFIG_SND_SUPPORT_OLD_API is not set
 # CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_PCI is not set
 # CONFIG_SND_ARM is not set
 # CONFIG_SND_SPI is not set
 # CONFIG_SND_USB is not set
@@ -136,15 +154,29 @@ CONFIG_SND_SOC_TEGRA_ALC5632=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_ACM=y
+CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_DRV_MAX8907=y
+CONFIG_RTC_DRV_TPS65910=y
 CONFIG_RTC_DRV_EM3027=y
 CONFIG_RTC_DRV_TEGRA=y
+CONFIG_DMADEVICES=y
+CONFIG_TEGRA20_APB_DMA=y
 CONFIG_STAGING=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_ISL29028=y
@@ -152,10 +184,14 @@ CONFIG_SENSORS_AK8975=y
 CONFIG_MFD_NVEC=y
 CONFIG_KEYBOARD_NVEC=y
 CONFIG_SERIO_NVEC_PS2=y
+CONFIG_NVEC_POWER=y
+CONFIG_NVEC_PAZ00=y
 CONFIG_TEGRA_IOMMU_GART=y
 CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_MEMORY=y
 CONFIG_IIO=y
+CONFIG_PWM=y
+CONFIG_PWM_TEGRA=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
@@ -168,6 +204,7 @@ CONFIG_EXT4_FS=y
 # CONFIG_DNOTIFY is not set
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
@@ -186,8 +223,6 @@ CONFIG_DEBUG_VM=y
 CONFIG_DEBUG_SG=y
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ARC4=y
 CONFIG_CRYPTO_TWOFISH=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_DEV_TEGRA_AES=y
diff --git a/arch/arm/configs/usb-a9260_defconfig b/arch/arm/configs/usb-a9260_defconfig
index 2e39f38b9627..a1501e1e1a90 100644
--- a/arch/arm/configs/usb-a9260_defconfig
+++ b/arch/arm/configs/usb-a9260_defconfig
@@ -49,7 +49,6 @@ CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile
new file mode 100644
index 000000000000..a2c83851bc90
--- /dev/null
+++ b/arch/arm/crypto/Makefile
@@ -0,0 +1,9 @@
+#
+# Arch-specific CryptoAPI modules.
+#
+obj-$(CONFIG_CRYPTO_AES_ARM) += aes-arm.o
+obj-$(CONFIG_CRYPTO_SHA1_ARM) += sha1-arm.o
+aes-arm-y  := aes-armv4.o aes_glue.o
+sha1-arm-y := sha1-armv4-large.o sha1_glue.o
diff --git a/arch/arm/crypto/aes-armv4.S b/arch/arm/crypto/aes-armv4.S
new file mode 100644
index 000000000000..e59b1d505d6c
--- /dev/null
+++ b/arch/arm/crypto/aes-armv4.S
@@ -0,0 +1,1112 @@
+#define __ARM_ARCH__ __LINUX_ARM_ARCH__
+@ ====================================================================
+@ Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
+@ project. The module is, however, dual licensed under OpenSSL and
+@ CRYPTOGAMS licenses depending on where you obtain it. For further
+@ details see http://www.openssl.org/~appro/cryptogams/.
+@ ====================================================================
+@ AES for ARMv4
+@ January 2007.
+@
+@ Code uses single 1K S-box and is >2 times faster than code generated
+@ by gcc-3.4.1. This is thanks to unique feature of ARMv4 ISA, which
+@ allows to merge logical or arithmetic operation with shift or rotate
+@ in one instruction and emit combined result every cycle. The module
+@ is endian-neutral. The performance is ~42 cycles/byte for 128-bit
+@ key [on single-issue Xscale PXA250 core].
+@ May 2007.
+@
+@ AES_set_[en|de]crypt_key is added.
+@ July 2010.
+@
+@ Rescheduling for dual-issue pipeline resulted in 12% improvement on
+@ Cortex A8 core and ~25 cycles per byte processed with 128-bit key.
+@ February 2011.
+@
+@ Profiler-assisted and platform-specific optimization resulted in 16%
+@ improvement on Cortex A8 core and ~21.5 cycles per byte.
+@ A little glue here to select the correct code below for the ARM CPU
+@ that is being targetted.
+.text
+.code   32
+.type   AES_Te,%object
+.align  5
+AES_Te:
+.word   0xc66363a5, 0xf87c7c84, 0xee777799, 0xf67b7b8d
+.word   0xfff2f20d, 0xd66b6bbd, 0xde6f6fb1, 0x91c5c554
+.word   0x60303050, 0x02010103, 0xce6767a9, 0x562b2b7d
+.word   0xe7fefe19, 0xb5d7d762, 0x4dababe6, 0xec76769a
+.word   0x8fcaca45, 0x1f82829d, 0x89c9c940, 0xfa7d7d87
+.word   0xeffafa15, 0xb25959eb, 0x8e4747c9, 0xfbf0f00b
+.word   0x41adadec, 0xb3d4d467, 0x5fa2a2fd, 0x45afafea
+.word   0x239c9cbf, 0x53a4a4f7, 0xe4727296, 0x9bc0c05b
+.word   0x75b7b7c2, 0xe1fdfd1c, 0x3d9393ae, 0x4c26266a
+.word   0x6c36365a, 0x7e3f3f41, 0xf5f7f702, 0x83cccc4f
+.word   0x6834345c, 0x51a5a5f4, 0xd1e5e534, 0xf9f1f108
+.word   0xe2717193, 0xabd8d873, 0x62313153, 0x2a15153f
+.word   0x0804040c, 0x95c7c752, 0x46232365, 0x9dc3c35e
+.word   0x30181828, 0x379696a1, 0x0a05050f, 0x2f9a9ab5
+.word   0x0e070709, 0x24121236, 0x1b80809b, 0xdfe2e23d
+.word   0xcdebeb26, 0x4e272769, 0x7fb2b2cd, 0xea75759f
+.word   0x1209091b, 0x1d83839e, 0x582c2c74, 0x341a1a2e
+.word   0x361b1b2d, 0xdc6e6eb2, 0xb45a5aee, 0x5ba0a0fb
+.word   0xa45252f6, 0x763b3b4d, 0xb7d6d661, 0x7db3b3ce
+.word   0x5229297b, 0xdde3e33e, 0x5e2f2f71, 0x13848497
+.word   0xa65353f5, 0xb9d1d168, 0x00000000, 0xc1eded2c
+.word   0x40202060, 0xe3fcfc1f, 0x79b1b1c8, 0xb65b5bed
+.word   0xd46a6abe, 0x8dcbcb46, 0x67bebed9, 0x7239394b
+.word   0x944a4ade, 0x984c4cd4, 0xb05858e8, 0x85cfcf4a
+.word   0xbbd0d06b, 0xc5efef2a, 0x4faaaae5, 0xedfbfb16
+.word   0x864343c5, 0x9a4d4dd7, 0x66333355, 0x11858594
+.word   0x8a4545cf, 0xe9f9f910, 0x04020206, 0xfe7f7f81
+.word   0xa05050f0, 0x783c3c44, 0x259f9fba, 0x4ba8a8e3
+.word   0xa25151f3, 0x5da3a3fe, 0x804040c0, 0x058f8f8a
+.word   0x3f9292ad, 0x219d9dbc, 0x70383848, 0xf1f5f504
+.word   0x63bcbcdf, 0x77b6b6c1, 0xafdada75, 0x42212163
+.word   0x20101030, 0xe5ffff1a, 0xfdf3f30e, 0xbfd2d26d
+.word   0x81cdcd4c, 0x180c0c14, 0x26131335, 0xc3ecec2f
+.word   0xbe5f5fe1, 0x359797a2, 0x884444cc, 0x2e171739
+.word   0x93c4c457, 0x55a7a7f2, 0xfc7e7e82, 0x7a3d3d47
+.word   0xc86464ac, 0xba5d5de7, 0x3219192b, 0xe6737395
+.word   0xc06060a0, 0x19818198, 0x9e4f4fd1, 0xa3dcdc7f
+.word   0x44222266, 0x542a2a7e, 0x3b9090ab, 0x0b888883
+.word   0x8c4646ca, 0xc7eeee29, 0x6bb8b8d3, 0x2814143c
+.word   0xa7dede79, 0xbc5e5ee2, 0x160b0b1d, 0xaddbdb76
+.word   0xdbe0e03b, 0x64323256, 0x743a3a4e, 0x140a0a1e
+.word   0x924949db, 0x0c06060a, 0x4824246c, 0xb85c5ce4
+.word   0x9fc2c25d, 0xbdd3d36e, 0x43acacef, 0xc46262a6
+.word   0x399191a8, 0x319595a4, 0xd3e4e437, 0xf279798b
+.word   0xd5e7e732, 0x8bc8c843, 0x6e373759, 0xda6d6db7
+.word   0x018d8d8c, 0xb1d5d564, 0x9c4e4ed2, 0x49a9a9e0
+.word   0xd86c6cb4, 0xac5656fa, 0xf3f4f407, 0xcfeaea25
+.word   0xca6565af, 0xf47a7a8e, 0x47aeaee9, 0x10080818
+.word   0x6fbabad5, 0xf0787888, 0x4a25256f, 0x5c2e2e72
+.word   0x381c1c24, 0x57a6a6f1, 0x73b4b4c7, 0x97c6c651
+.word   0xcbe8e823, 0xa1dddd7c, 0xe874749c, 0x3e1f1f21
+.word   0x964b4bdd, 0x61bdbddc, 0x0d8b8b86, 0x0f8a8a85
+.word   0xe0707090, 0x7c3e3e42, 0x71b5b5c4, 0xcc6666aa
+.word   0x904848d8, 0x06030305, 0xf7f6f601, 0x1c0e0e12
+.word   0xc26161a3, 0x6a35355f, 0xae5757f9, 0x69b9b9d0
+.word   0x17868691, 0x99c1c158, 0x3a1d1d27, 0x279e9eb9
+.word   0xd9e1e138, 0xebf8f813, 0x2b9898b3, 0x22111133
+.word   0xd26969bb, 0xa9d9d970, 0x078e8e89, 0x339494a7
+.word   0x2d9b9bb6, 0x3c1e1e22, 0x15878792, 0xc9e9e920
+.word   0x87cece49, 0xaa5555ff, 0x50282878, 0xa5dfdf7a
+.word   0x038c8c8f, 0x59a1a1f8, 0x09898980, 0x1a0d0d17
+.word   0x65bfbfda, 0xd7e6e631, 0x844242c6, 0xd06868b8
+.word   0x824141c3, 0x299999b0, 0x5a2d2d77, 0x1e0f0f11
+.word   0x7bb0b0cb, 0xa85454fc, 0x6dbbbbd6, 0x2c16163a
+@ Te4[256]
+.byte   0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5
+.byte   0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76
+.byte   0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0
+.byte   0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0
+.byte   0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc
+.byte   0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15
+.byte   0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a
+.byte   0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75
+.byte   0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0
+.byte   0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84
+.byte   0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b
+.byte   0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf
+.byte   0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85
+.byte   0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8
+.byte   0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5
+.byte   0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2
+.byte   0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17
+.byte   0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73
+.byte   0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88
+.byte   0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb
+.byte   0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c
+.byte   0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79
+.byte   0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9
+.byte   0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08
+.byte   0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6
+.byte   0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a
+.byte   0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e
+.byte   0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e
+.byte   0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94
+.byte   0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf
+.byte   0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68
+.byte   0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
+@ rcon[]
+.word   0x01000000, 0x02000000, 0x04000000, 0x08000000
+.word   0x10000000, 0x20000000, 0x40000000, 0x80000000
+.word   0x1B000000, 0x36000000, 0, 0, 0, 0, 0, 0
+.size   AES_Te,.-AES_Te
+@ void AES_encrypt(const unsigned char *in, unsigned char *out,
+@                const AES_KEY *key) {
+.global AES_encrypt
+.type   AES_encrypt,%function
+.align  5
+AES_encrypt:
+        sub     r3,pc,#8                @ AES_encrypt
+        stmdb   sp!,{r1,r4-r12,lr}
+        mov     r12,r0          @ inp
+        mov     r11,r2
+        sub     r10,r3,#AES_encrypt-AES_Te      @ Te
+#if __ARM_ARCH__<7
+        ldrb    r0,[r12,#3]     @ load input data in endian-neutral
+        ldrb    r4,[r12,#2]     @ manner...
+        ldrb    r5,[r12,#1]
+        ldrb    r6,[r12,#0]
+        orr     r0,r0,r4,lsl#8
+        ldrb    r1,[r12,#7]
+        orr     r0,r0,r5,lsl#16
+        ldrb    r4,[r12,#6]
+        orr     r0,r0,r6,lsl#24
+        ldrb    r5,[r12,#5]
+        ldrb    r6,[r12,#4]
+        orr     r1,r1,r4,lsl#8
+        ldrb    r2,[r12,#11]
+        orr     r1,r1,r5,lsl#16
+        ldrb    r4,[r12,#10]
+        orr     r1,r1,r6,lsl#24
+        ldrb    r5,[r12,#9]
+        ldrb    r6,[r12,#8]
+        orr     r2,r2,r4,lsl#8
+        ldrb    r3,[r12,#15]
+        orr     r2,r2,r5,lsl#16
+        ldrb    r4,[r12,#14]
+        orr     r2,r2,r6,lsl#24
+        ldrb    r5,[r12,#13]
+        ldrb    r6,[r12,#12]
+        orr     r3,r3,r4,lsl#8
+        orr     r3,r3,r5,lsl#16
+        orr     r3,r3,r6,lsl#24
+#else
+        ldr     r0,[r12,#0]
+        ldr     r1,[r12,#4]
+        ldr     r2,[r12,#8]
+        ldr     r3,[r12,#12]
+#ifdef __ARMEL__
+        rev     r0,r0
+        rev     r1,r1
+        rev     r2,r2
+        rev     r3,r3
+#endif
+#endif
+        bl      _armv4_AES_encrypt
+        ldr     r12,[sp],#4             @ pop out
+#if __ARM_ARCH__>=7
+#ifdef __ARMEL__
+        rev     r0,r0
+        rev     r1,r1
+        rev     r2,r2
+        rev     r3,r3
+#endif
+        str     r0,[r12,#0]
+        str     r1,[r12,#4]
+        str     r2,[r12,#8]
+        str     r3,[r12,#12]
+#else
+        mov     r4,r0,lsr#24            @ write output in endian-neutral
+        mov     r5,r0,lsr#16            @ manner...
+        mov     r6,r0,lsr#8
+        strb    r4,[r12,#0]
+        strb    r5,[r12,#1]
+        mov     r4,r1,lsr#24
+        strb    r6,[r12,#2]
+        mov     r5,r1,lsr#16
+        strb    r0,[r12,#3]
+        mov     r6,r1,lsr#8
+        strb    r4,[r12,#4]
+        strb    r5,[r12,#5]
+        mov     r4,r2,lsr#24
+        strb    r6,[r12,#6]
+        mov     r5,r2,lsr#16
+        strb    r1,[r12,#7]
+        mov     r6,r2,lsr#8
+        strb    r4,[r12,#8]
+        strb    r5,[r12,#9]
+        mov     r4,r3,lsr#24
+        strb    r6,[r12,#10]
+        mov     r5,r3,lsr#16
+        strb    r2,[r12,#11]
+        mov     r6,r3,lsr#8
+        strb    r4,[r12,#12]
+        strb    r5,[r12,#13]
+        strb    r6,[r12,#14]
+        strb    r3,[r12,#15]
+#endif
+#if __ARM_ARCH__>=5
+        ldmia   sp!,{r4-r12,pc}
+#else
+        ldmia   sp!,{r4-r12,lr}
+        tst     lr,#1
+        moveq   pc,lr                   @ be binary compatible with V4, yet
+        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
+#endif
+.size   AES_encrypt,.-AES_encrypt
+.type   _armv4_AES_encrypt,%function
+.align  2
+_armv4_AES_encrypt:
+        str     lr,[sp,#-4]!            @ push lr
+        ldmia   r11!,{r4-r7}
+        eor     r0,r0,r4
+        ldr     r12,[r11,#240-16]
+        eor     r1,r1,r5
+        eor     r2,r2,r6
+        eor     r3,r3,r7
+        sub     r12,r12,#1
+        mov     lr,#255
+        and     r7,lr,r0
+        and     r8,lr,r0,lsr#8
+        and     r9,lr,r0,lsr#16
+        mov     r0,r0,lsr#24
+.Lenc_loop:
+        ldr     r4,[r10,r7,lsl#2]       @ Te3[s0>>0]
+        and     r7,lr,r1,lsr#16 @ i0
+        ldr     r5,[r10,r8,lsl#2]       @ Te2[s0>>8]
+        and     r8,lr,r1
+        ldr     r6,[r10,r9,lsl#2]       @ Te1[s0>>16]
+        and     r9,lr,r1,lsr#8
+        ldr     r0,[r10,r0,lsl#2]       @ Te0[s0>>24]
+        mov     r1,r1,lsr#24
+        ldr     r7,[r10,r7,lsl#2]       @ Te1[s1>>16]
+        ldr     r8,[r10,r8,lsl#2]       @ Te3[s1>>0]
+        ldr     r9,[r10,r9,lsl#2]       @ Te2[s1>>8]
+        eor     r0,r0,r7,ror#8
+        ldr     r1,[r10,r1,lsl#2]       @ Te0[s1>>24]
+        and     r7,lr,r2,lsr#8  @ i0
+        eor     r5,r5,r8,ror#8
+        and     r8,lr,r2,lsr#16 @ i1
+        eor     r6,r6,r9,ror#8
+        and     r9,lr,r2
+        ldr     r7,[r10,r7,lsl#2]       @ Te2[s2>>8]
+        eor     r1,r1,r4,ror#24
+        ldr     r8,[r10,r8,lsl#2]       @ Te1[s2>>16]
+        mov     r2,r2,lsr#24
+        ldr     r9,[r10,r9,lsl#2]       @ Te3[s2>>0]
+        eor     r0,r0,r7,ror#16
+        ldr     r2,[r10,r2,lsl#2]       @ Te0[s2>>24]
+        and     r7,lr,r3                @ i0
+        eor     r1,r1,r8,ror#8
+        and     r8,lr,r3,lsr#8  @ i1
+        eor     r6,r6,r9,ror#16
+        and     r9,lr,r3,lsr#16 @ i2
+        ldr     r7,[r10,r7,lsl#2]       @ Te3[s3>>0]
+        eor     r2,r2,r5,ror#16
+        ldr     r8,[r10,r8,lsl#2]       @ Te2[s3>>8]
+        mov     r3,r3,lsr#24
+        ldr     r9,[r10,r9,lsl#2]       @ Te1[s3>>16]
+        eor     r0,r0,r7,ror#24
+        ldr     r7,[r11],#16
+        eor     r1,r1,r8,ror#16
+        ldr     r3,[r10,r3,lsl#2]       @ Te0[s3>>24]
+        eor     r2,r2,r9,ror#8
+        ldr     r4,[r11,#-12]
+        eor     r3,r3,r6,ror#8
+        ldr     r5,[r11,#-8]
+        eor     r0,r0,r7
+        ldr     r6,[r11,#-4]
+        and     r7,lr,r0
+        eor     r1,r1,r4
+        and     r8,lr,r0,lsr#8
+        eor     r2,r2,r5
+        and     r9,lr,r0,lsr#16
+        eor     r3,r3,r6
+        mov     r0,r0,lsr#24
+        subs    r12,r12,#1
+        bne     .Lenc_loop
+        add     r10,r10,#2
+        ldrb    r4,[r10,r7,lsl#2]       @ Te4[s0>>0]
+        and     r7,lr,r1,lsr#16 @ i0
+        ldrb    r5,[r10,r8,lsl#2]       @ Te4[s0>>8]
+        and     r8,lr,r1
+        ldrb    r6,[r10,r9,lsl#2]       @ Te4[s0>>16]
+        and     r9,lr,r1,lsr#8
+        ldrb    r0,[r10,r0,lsl#2]       @ Te4[s0>>24]
+        mov     r1,r1,lsr#24
+        ldrb    r7,[r10,r7,lsl#2]       @ Te4[s1>>16]
+        ldrb    r8,[r10,r8,lsl#2]       @ Te4[s1>>0]
+        ldrb    r9,[r10,r9,lsl#2]       @ Te4[s1>>8]
+        eor     r0,r7,r0,lsl#8
+        ldrb    r1,[r10,r1,lsl#2]       @ Te4[s1>>24]
+        and     r7,lr,r2,lsr#8  @ i0
+        eor     r5,r8,r5,lsl#8
+        and     r8,lr,r2,lsr#16 @ i1
+        eor     r6,r9,r6,lsl#8
+        and     r9,lr,r2
+        ldrb    r7,[r10,r7,lsl#2]       @ Te4[s2>>8]
+        eor     r1,r4,r1,lsl#24
+        ldrb    r8,[r10,r8,lsl#2]       @ Te4[s2>>16]
+        mov     r2,r2,lsr#24
+        ldrb    r9,[r10,r9,lsl#2]       @ Te4[s2>>0]
+        eor     r0,r7,r0,lsl#8
+        ldrb    r2,[r10,r2,lsl#2]       @ Te4[s2>>24]
+        and     r7,lr,r3                @ i0
+        eor     r1,r1,r8,lsl#16
+        and     r8,lr,r3,lsr#8  @ i1
+        eor     r6,r9,r6,lsl#8
+        and     r9,lr,r3,lsr#16 @ i2
+        ldrb    r7,[r10,r7,lsl#2]       @ Te4[s3>>0]
+        eor     r2,r5,r2,lsl#24
+        ldrb    r8,[r10,r8,lsl#2]       @ Te4[s3>>8]
+        mov     r3,r3,lsr#24
+        ldrb    r9,[r10,r9,lsl#2]       @ Te4[s3>>16]
+        eor     r0,r7,r0,lsl#8
+        ldr     r7,[r11,#0]
+        ldrb    r3,[r10,r3,lsl#2]       @ Te4[s3>>24]
+        eor     r1,r1,r8,lsl#8
+        ldr     r4,[r11,#4]
+        eor     r2,r2,r9,lsl#16
+        ldr     r5,[r11,#8]
+        eor     r3,r6,r3,lsl#24
+        ldr     r6,[r11,#12]
+        eor     r0,r0,r7
+        eor     r1,r1,r4
+        eor     r2,r2,r5
+        eor     r3,r3,r6
+        sub     r10,r10,#2
+        ldr     pc,[sp],#4              @ pop and return
+.size   _armv4_AES_encrypt,.-_armv4_AES_encrypt
+.global private_AES_set_encrypt_key
+.type   private_AES_set_encrypt_key,%function
+.align  5
+private_AES_set_encrypt_key:
+_armv4_AES_set_encrypt_key:
+        sub     r3,pc,#8                @ AES_set_encrypt_key
+        teq     r0,#0
+        moveq   r0,#-1
+        beq     .Labrt
+        teq     r2,#0
+        moveq   r0,#-1
+        beq     .Labrt
+        teq     r1,#128
+        beq     .Lok
+        teq     r1,#192
+        beq     .Lok
+        teq     r1,#256
+        movne   r0,#-1
+        bne     .Labrt
+.Lok:   stmdb   sp!,{r4-r12,lr}
+        sub     r10,r3,#_armv4_AES_set_encrypt_key-AES_Te-1024  @ Te4
+        mov     r12,r0          @ inp
+        mov     lr,r1                   @ bits
+        mov     r11,r2                  @ key
+#if __ARM_ARCH__<7
+        ldrb    r0,[r12,#3]     @ load input data in endian-neutral
+        ldrb    r4,[r12,#2]     @ manner...
+        ldrb    r5,[r12,#1]
+        ldrb    r6,[r12,#0]
+        orr     r0,r0,r4,lsl#8
+        ldrb    r1,[r12,#7]
+        orr     r0,r0,r5,lsl#16
+        ldrb    r4,[r12,#6]
+        orr     r0,r0,r6,lsl#24
+        ldrb    r5,[r12,#5]
+        ldrb    r6,[r12,#4]
+        orr     r1,r1,r4,lsl#8
+        ldrb    r2,[r12,#11]
+        orr     r1,r1,r5,lsl#16
+        ldrb    r4,[r12,#10]
+        orr     r1,r1,r6,lsl#24
+        ldrb    r5,[r12,#9]
+        ldrb    r6,[r12,#8]
+        orr     r2,r2,r4,lsl#8
+        ldrb    r3,[r12,#15]
+        orr     r2,r2,r5,lsl#16
+        ldrb    r4,[r12,#14]
+        orr     r2,r2,r6,lsl#24
+        ldrb    r5,[r12,#13]
+        ldrb    r6,[r12,#12]
+        orr     r3,r3,r4,lsl#8
+        str     r0,[r11],#16
+        orr     r3,r3,r5,lsl#16
+        str     r1,[r11,#-12]
+        orr     r3,r3,r6,lsl#24
+        str     r2,[r11,#-8]
+        str     r3,[r11,#-4]
+#else
+        ldr     r0,[r12,#0]
+        ldr     r1,[r12,#4]
+        ldr     r2,[r12,#8]
+        ldr     r3,[r12,#12]
+#ifdef __ARMEL__
+        rev     r0,r0
+        rev     r1,r1
+        rev     r2,r2
+        rev     r3,r3
+#endif
+        str     r0,[r11],#16
+        str     r1,[r11,#-12]
+        str     r2,[r11,#-8]
+        str     r3,[r11,#-4]
+#endif
+        teq     lr,#128
+        bne     .Lnot128
+        mov     r12,#10
+        str     r12,[r11,#240-16]
+        add     r6,r10,#256                     @ rcon
+        mov     lr,#255
+.L128_loop:
+        and     r5,lr,r3,lsr#24
+        and     r7,lr,r3,lsr#16
+        ldrb    r5,[r10,r5]
+        and     r8,lr,r3,lsr#8
+        ldrb    r7,[r10,r7]
+        and     r9,lr,r3
+        ldrb    r8,[r10,r8]
+        orr     r5,r5,r7,lsl#24
+        ldrb    r9,[r10,r9]
+        orr     r5,r5,r8,lsl#16
+        ldr     r4,[r6],#4                      @ rcon[i++]
+        orr     r5,r5,r9,lsl#8
+        eor     r5,r5,r4
+        eor     r0,r0,r5                        @ rk[4]=rk[0]^...
+        eor     r1,r1,r0                        @ rk[5]=rk[1]^rk[4]
+        str     r0,[r11],#16
+        eor     r2,r2,r1                        @ rk[6]=rk[2]^rk[5]
+        str     r1,[r11,#-12]
+        eor     r3,r3,r2                        @ rk[7]=rk[3]^rk[6]
+        str     r2,[r11,#-8]
+        subs    r12,r12,#1
+        str     r3,[r11,#-4]
+        bne     .L128_loop
+        sub     r2,r11,#176
+        b       .Ldone
+.Lnot128:
+#if __ARM_ARCH__<7
+        ldrb    r8,[r12,#19]
+        ldrb    r4,[r12,#18]
+        ldrb    r5,[r12,#17]
+        ldrb    r6,[r12,#16]
+        orr     r8,r8,r4,lsl#8
+        ldrb    r9,[r12,#23]
+        orr     r8,r8,r5,lsl#16
+        ldrb    r4,[r12,#22]
+        orr     r8,r8,r6,lsl#24
+        ldrb    r5,[r12,#21]
+        ldrb    r6,[r12,#20]
+        orr     r9,r9,r4,lsl#8
+        orr     r9,r9,r5,lsl#16
+        str     r8,[r11],#8
+        orr     r9,r9,r6,lsl#24
+        str     r9,[r11,#-4]
+#else
+        ldr     r8,[r12,#16]
+        ldr     r9,[r12,#20]
+#ifdef __ARMEL__
+        rev     r8,r8
+        rev     r9,r9
+#endif
+        str     r8,[r11],#8
+        str     r9,[r11,#-4]
+#endif
+        teq     lr,#192
+        bne     .Lnot192
+        mov     r12,#12
+        str     r12,[r11,#240-24]
+        add     r6,r10,#256                     @ rcon
+        mov     lr,#255
+        mov     r12,#8
+.L192_loop:
+        and     r5,lr,r9,lsr#24
+        and     r7,lr,r9,lsr#16
+        ldrb    r5,[r10,r5]
+        and     r8,lr,r9,lsr#8
+        ldrb    r7,[r10,r7]
+        and     r9,lr,r9
+        ldrb    r8,[r10,r8]
+        orr     r5,r5,r7,lsl#24
+        ldrb    r9,[r10,r9]
+        orr     r5,r5,r8,lsl#16
+        ldr     r4,[r6],#4                      @ rcon[i++]
+        orr     r5,r5,r9,lsl#8
+        eor     r9,r5,r4
+        eor     r0,r0,r9                        @ rk[6]=rk[0]^...
+        eor     r1,r1,r0                        @ rk[7]=rk[1]^rk[6]
+        str     r0,[r11],#24
+        eor     r2,r2,r1                        @ rk[8]=rk[2]^rk[7]
+        str     r1,[r11,#-20]
+        eor     r3,r3,r2                        @ rk[9]=rk[3]^rk[8]
+        str     r2,[r11,#-16]
+        subs    r12,r12,#1
+        str     r3,[r11,#-12]
+        subeq   r2,r11,#216
+        beq     .Ldone
+        ldr     r7,[r11,#-32]
+        ldr     r8,[r11,#-28]
+        eor     r7,r7,r3                        @ rk[10]=rk[4]^rk[9]
+        eor     r9,r8,r7                        @ rk[11]=rk[5]^rk[10]
+        str     r7,[r11,#-8]
+        str     r9,[r11,#-4]
+        b       .L192_loop
+.Lnot192:
+#if __ARM_ARCH__<7
+        ldrb    r8,[r12,#27]
+        ldrb    r4,[r12,#26]
+        ldrb    r5,[r12,#25]
+        ldrb    r6,[r12,#24]
+        orr     r8,r8,r4,lsl#8
+        ldrb    r9,[r12,#31]
+        orr     r8,r8,r5,lsl#16
+        ldrb    r4,[r12,#30]
+        orr     r8,r8,r6,lsl#24
+        ldrb    r5,[r12,#29]
+        ldrb    r6,[r12,#28]
+        orr     r9,r9,r4,lsl#8
+        orr     r9,r9,r5,lsl#16
+        str     r8,[r11],#8
+        orr     r9,r9,r6,lsl#24
+        str     r9,[r11,#-4]
+#else
+        ldr     r8,[r12,#24]
+        ldr     r9,[r12,#28]
+#ifdef __ARMEL__
+        rev     r8,r8
+        rev     r9,r9
+#endif
+        str     r8,[r11],#8
+        str     r9,[r11,#-4]
+#endif
+        mov     r12,#14
+        str     r12,[r11,#240-32]
+        add     r6,r10,#256                     @ rcon
+        mov     lr,#255
+        mov     r12,#7
+.L256_loop:
+        and     r5,lr,r9,lsr#24
+        and     r7,lr,r9,lsr#16
+        ldrb    r5,[r10,r5]
+        and     r8,lr,r9,lsr#8
+        ldrb    r7,[r10,r7]
+        and     r9,lr,r9
+        ldrb    r8,[r10,r8]
+        orr     r5,r5,r7,lsl#24
+        ldrb    r9,[r10,r9]
+        orr     r5,r5,r8,lsl#16
+        ldr     r4,[r6],#4                      @ rcon[i++]
+        orr     r5,r5,r9,lsl#8
+        eor     r9,r5,r4
+        eor     r0,r0,r9                        @ rk[8]=rk[0]^...
+        eor     r1,r1,r0                        @ rk[9]=rk[1]^rk[8]
+        str     r0,[r11],#32
+        eor     r2,r2,r1                        @ rk[10]=rk[2]^rk[9]
+        str     r1,[r11,#-28]
+        eor     r3,r3,r2                        @ rk[11]=rk[3]^rk[10]
+        str     r2,[r11,#-24]
+        subs    r12,r12,#1
+        str     r3,[r11,#-20]
+        subeq   r2,r11,#256
+        beq     .Ldone
+        and     r5,lr,r3
+        and     r7,lr,r3,lsr#8
+        ldrb    r5,[r10,r5]
+        and     r8,lr,r3,lsr#16
+        ldrb    r7,[r10,r7]
+        and     r9,lr,r3,lsr#24
+        ldrb    r8,[r10,r8]
+        orr     r5,r5,r7,lsl#8
+        ldrb    r9,[r10,r9]
+        orr     r5,r5,r8,lsl#16
+        ldr     r4,[r11,#-48]
+        orr     r5,r5,r9,lsl#24
+        ldr     r7,[r11,#-44]
+        ldr     r8,[r11,#-40]
+        eor     r4,r4,r5                        @ rk[12]=rk[4]^...
+        ldr     r9,[r11,#-36]
+        eor     r7,r7,r4                        @ rk[13]=rk[5]^rk[12]
+        str     r4,[r11,#-16]
+        eor     r8,r8,r7                        @ rk[14]=rk[6]^rk[13]
+        str     r7,[r11,#-12]
+        eor     r9,r9,r8                        @ rk[15]=rk[7]^rk[14]
+        str     r8,[r11,#-8]
+        str     r9,[r11,#-4]
+        b       .L256_loop
+.Ldone: mov     r0,#0
+        ldmia   sp!,{r4-r12,lr}
+.Labrt: tst     lr,#1
+        moveq   pc,lr                   @ be binary compatible with V4, yet
+        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
+.size   private_AES_set_encrypt_key,.-private_AES_set_encrypt_key
+.global private_AES_set_decrypt_key
+.type   private_AES_set_decrypt_key,%function
+.align  5
+private_AES_set_decrypt_key:
+        str     lr,[sp,#-4]!            @ push lr
+#if 0
+        @ kernel does both of these in setkey so optimise this bit out by
+        @ expecting the key to already have the enc_key work done (see aes_glue.c)
+        bl      _armv4_AES_set_encrypt_key
+#else
+        mov     r0,#0
+#endif
+        teq     r0,#0
+        ldrne   lr,[sp],#4              @ pop lr
+        bne     .Labrt
+        stmdb   sp!,{r4-r12}
+        ldr     r12,[r2,#240]   @ AES_set_encrypt_key preserves r2,
+        mov     r11,r2                  @ which is AES_KEY *key
+        mov     r7,r2
+        add     r8,r2,r12,lsl#4
+.Linv:  ldr     r0,[r7]
+        ldr     r1,[r7,#4]
+        ldr     r2,[r7,#8]
+        ldr     r3,[r7,#12]
+        ldr     r4,[r8]
+        ldr     r5,[r8,#4]
+        ldr     r6,[r8,#8]
+        ldr     r9,[r8,#12]
+        str     r0,[r8],#-16
+        str     r1,[r8,#16+4]
+        str     r2,[r8,#16+8]
+        str     r3,[r8,#16+12]
+        str     r4,[r7],#16
+        str     r5,[r7,#-12]
+        str     r6,[r7,#-8]
+        str     r9,[r7,#-4]
+        teq     r7,r8
+        bne     .Linv
+        ldr     r0,[r11,#16]!           @ prefetch tp1
+        mov     r7,#0x80
+        mov     r8,#0x1b
+        orr     r7,r7,#0x8000
+        orr     r8,r8,#0x1b00
+        orr     r7,r7,r7,lsl#16
+        orr     r8,r8,r8,lsl#16
+        sub     r12,r12,#1
+        mvn     r9,r7
+        mov     r12,r12,lsl#2   @ (rounds-1)*4
+.Lmix:  and     r4,r0,r7
+        and     r1,r0,r9
+        sub     r4,r4,r4,lsr#7
+        and     r4,r4,r8
+        eor     r1,r4,r1,lsl#1  @ tp2
+        and     r4,r1,r7
+        and     r2,r1,r9
+        sub     r4,r4,r4,lsr#7
+        and     r4,r4,r8
+        eor     r2,r4,r2,lsl#1  @ tp4
+        and     r4,r2,r7
+        and     r3,r2,r9
+        sub     r4,r4,r4,lsr#7
+        and     r4,r4,r8
+        eor     r3,r4,r3,lsl#1  @ tp8
+        eor     r4,r1,r2
+        eor     r5,r0,r3                @ tp9
+        eor     r4,r4,r3                @ tpe
+        eor     r4,r4,r1,ror#24
+        eor     r4,r4,r5,ror#24 @ ^= ROTATE(tpb=tp9^tp2,8)
+        eor     r4,r4,r2,ror#16
+        eor     r4,r4,r5,ror#16 @ ^= ROTATE(tpd=tp9^tp4,16)
+        eor     r4,r4,r5,ror#8  @ ^= ROTATE(tp9,24)
+        ldr     r0,[r11,#4]             @ prefetch tp1
+        str     r4,[r11],#4
+        subs    r12,r12,#1
+        bne     .Lmix
+        mov     r0,#0
+#if __ARM_ARCH__>=5
+        ldmia   sp!,{r4-r12,pc}
+#else
+        ldmia   sp!,{r4-r12,lr}
+        tst     lr,#1
+        moveq   pc,lr                   @ be binary compatible with V4, yet
+        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
+#endif
+.size   private_AES_set_decrypt_key,.-private_AES_set_decrypt_key
+.type   AES_Td,%object
+.align  5
+AES_Td:
+.word   0x51f4a750, 0x7e416553, 0x1a17a4c3, 0x3a275e96
+.word   0x3bab6bcb, 0x1f9d45f1, 0xacfa58ab, 0x4be30393
+.word   0x2030fa55, 0xad766df6, 0x88cc7691, 0xf5024c25
+.word   0x4fe5d7fc, 0xc52acbd7, 0x26354480, 0xb562a38f
+.word   0xdeb15a49, 0x25ba1b67, 0x45ea0e98, 0x5dfec0e1
+.word   0xc32f7502, 0x814cf012, 0x8d4697a3, 0x6bd3f9c6
+.word   0x038f5fe7, 0x15929c95, 0xbf6d7aeb, 0x955259da
+.word   0xd4be832d, 0x587421d3, 0x49e06929, 0x8ec9c844
+.word   0x75c2896a, 0xf48e7978, 0x99583e6b, 0x27b971dd
+.word   0xbee14fb6, 0xf088ad17, 0xc920ac66, 0x7dce3ab4
+.word   0x63df4a18, 0xe51a3182, 0x97513360, 0x62537f45
+.word   0xb16477e0, 0xbb6bae84, 0xfe81a01c, 0xf9082b94
+.word   0x70486858, 0x8f45fd19, 0x94de6c87, 0x527bf8b7
+.word   0xab73d323, 0x724b02e2, 0xe31f8f57, 0x6655ab2a
+.word   0xb2eb2807, 0x2fb5c203, 0x86c57b9a, 0xd33708a5
+.word   0x302887f2, 0x23bfa5b2, 0x02036aba, 0xed16825c
+.word   0x8acf1c2b, 0xa779b492, 0xf307f2f0, 0x4e69e2a1
+.word   0x65daf4cd, 0x0605bed5, 0xd134621f, 0xc4a6fe8a
+.word   0x342e539d, 0xa2f355a0, 0x058ae132, 0xa4f6eb75
+.word   0x0b83ec39, 0x4060efaa, 0x5e719f06, 0xbd6e1051
+.word   0x3e218af9, 0x96dd063d, 0xdd3e05ae, 0x4de6bd46
+.word   0x91548db5, 0x71c45d05, 0x0406d46f, 0x605015ff
+.word   0x1998fb24, 0xd6bde997, 0x894043cc, 0x67d99e77
+.word   0xb0e842bd, 0x07898b88, 0xe7195b38, 0x79c8eedb
+.word   0xa17c0a47, 0x7c420fe9, 0xf8841ec9, 0x00000000
+.word   0x09808683, 0x322bed48, 0x1e1170ac, 0x6c5a724e
+.word   0xfd0efffb, 0x0f853856, 0x3daed51e, 0x362d3927
+.word   0x0a0fd964, 0x685ca621, 0x9b5b54d1, 0x24362e3a
+.word   0x0c0a67b1, 0x9357e70f, 0xb4ee96d2, 0x1b9b919e
+.word   0x80c0c54f, 0x61dc20a2, 0x5a774b69, 0x1c121a16
+.word   0xe293ba0a, 0xc0a02ae5, 0x3c22e043, 0x121b171d
+.word   0x0e090d0b, 0xf28bc7ad, 0x2db6a8b9, 0x141ea9c8
+.word   0x57f11985, 0xaf75074c, 0xee99ddbb, 0xa37f60fd
+.word   0xf701269f, 0x5c72f5bc, 0x44663bc5, 0x5bfb7e34
+.word   0x8b432976, 0xcb23c6dc, 0xb6edfc68, 0xb8e4f163
+.word   0xd731dcca, 0x42638510, 0x13972240, 0x84c61120
+.word   0x854a247d, 0xd2bb3df8, 0xaef93211, 0xc729a16d
+.word   0x1d9e2f4b, 0xdcb230f3, 0x0d8652ec, 0x77c1e3d0
+.word   0x2bb3166c, 0xa970b999, 0x119448fa, 0x47e96422
+.word   0xa8fc8cc4, 0xa0f03f1a, 0x567d2cd8, 0x223390ef
+.word   0x87494ec7, 0xd938d1c1, 0x8ccaa2fe, 0x98d40b36
+.word   0xa6f581cf, 0xa57ade28, 0xdab78e26, 0x3fadbfa4
+.word   0x2c3a9de4, 0x5078920d, 0x6a5fcc9b, 0x547e4662
+.word   0xf68d13c2, 0x90d8b8e8, 0x2e39f75e, 0x82c3aff5
+.word   0x9f5d80be, 0x69d0937c, 0x6fd52da9, 0xcf2512b3
+.word   0xc8ac993b, 0x10187da7, 0xe89c636e, 0xdb3bbb7b
+.word   0xcd267809, 0x6e5918f4, 0xec9ab701, 0x834f9aa8
+.word   0xe6956e65, 0xaaffe67e, 0x21bccf08, 0xef15e8e6
+.word   0xbae79bd9, 0x4a6f36ce, 0xea9f09d4, 0x29b07cd6
+.word   0x31a4b2af, 0x2a3f2331, 0xc6a59430, 0x35a266c0
+.word   0x744ebc37, 0xfc82caa6, 0xe090d0b0, 0x33a7d815
+.word   0xf104984a, 0x41ecdaf7, 0x7fcd500e, 0x1791f62f
+.word   0x764dd68d, 0x43efb04d, 0xccaa4d54, 0xe49604df
+.word   0x9ed1b5e3, 0x4c6a881b, 0xc12c1fb8, 0x4665517f
+.word   0x9d5eea04, 0x018c355d, 0xfa877473, 0xfb0b412e
+.word   0xb3671d5a, 0x92dbd252, 0xe9105633, 0x6dd64713
+.word   0x9ad7618c, 0x37a10c7a, 0x59f8148e, 0xeb133c89
+.word   0xcea927ee, 0xb761c935, 0xe11ce5ed, 0x7a47b13c
+.word   0x9cd2df59, 0x55f2733f, 0x1814ce79, 0x73c737bf
+.word   0x53f7cdea, 0x5ffdaa5b, 0xdf3d6f14, 0x7844db86
+.word   0xcaaff381, 0xb968c43e, 0x3824342c, 0xc2a3405f
+.word   0x161dc372, 0xbce2250c, 0x283c498b, 0xff0d9541
+.word   0x39a80171, 0x080cb3de, 0xd8b4e49c, 0x6456c190
+.word   0x7bcb8461, 0xd532b670, 0x486c5c74, 0xd0b85742
+@ Td4[256]
+.byte   0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38
+.byte   0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb
+.byte   0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87
+.byte   0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb
+.byte   0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d
+.byte   0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e
+.byte   0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2
+.byte   0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25
+.byte   0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16
+.byte   0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92
+.byte   0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda
+.byte   0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84
+.byte   0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a
+.byte   0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06
+.byte   0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02
+.byte   0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b
+.byte   0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea
+.byte   0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73
+.byte   0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85
+.byte   0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e
+.byte   0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89
+.byte   0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b
+.byte   0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20
+.byte   0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4
+.byte   0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31
+.byte   0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f
+.byte   0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d
+.byte   0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef
+.byte   0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0
+.byte   0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61
+.byte   0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26
+.byte   0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
+.size   AES_Td,.-AES_Td
+@ void AES_decrypt(const unsigned char *in, unsigned char *out,
+@                const AES_KEY *key) {
+.global AES_decrypt
+.type   AES_decrypt,%function
+.align  5
+AES_decrypt:
+        sub     r3,pc,#8                @ AES_decrypt
+        stmdb   sp!,{r1,r4-r12,lr}
+        mov     r12,r0          @ inp
+        mov     r11,r2
+        sub     r10,r3,#AES_decrypt-AES_Td              @ Td
+#if __ARM_ARCH__<7
+        ldrb    r0,[r12,#3]     @ load input data in endian-neutral
+        ldrb    r4,[r12,#2]     @ manner...
+        ldrb    r5,[r12,#1]
+        ldrb    r6,[r12,#0]
+        orr     r0,r0,r4,lsl#8
+        ldrb    r1,[r12,#7]
+        orr     r0,r0,r5,lsl#16
+        ldrb    r4,[r12,#6]
+        orr     r0,r0,r6,lsl#24
+        ldrb    r5,[r12,#5]
+        ldrb    r6,[r12,#4]
+        orr     r1,r1,r4,lsl#8
+        ldrb    r2,[r12,#11]
+        orr     r1,r1,r5,lsl#16
+        ldrb    r4,[r12,#10]
+        orr     r1,r1,r6,lsl#24
+        ldrb    r5,[r12,#9]
+        ldrb    r6,[r12,#8]
+        orr     r2,r2,r4,lsl#8
+        ldrb    r3,[r12,#15]
+        orr     r2,r2,r5,lsl#16
+        ldrb    r4,[r12,#14]
+        orr     r2,r2,r6,lsl#24
+        ldrb    r5,[r12,#13]
+        ldrb    r6,[r12,#12]
+        orr     r3,r3,r4,lsl#8
+        orr     r3,r3,r5,lsl#16
+        orr     r3,r3,r6,lsl#24
+#else
+        ldr     r0,[r12,#0]
+        ldr     r1,[r12,#4]
+        ldr     r2,[r12,#8]
+        ldr     r3,[r12,#12]
+#ifdef __ARMEL__
+        rev     r0,r0
+        rev     r1,r1
+        rev     r2,r2
+        rev     r3,r3
+#endif
+#endif
+        bl      _armv4_AES_decrypt
+        ldr     r12,[sp],#4             @ pop out
+#if __ARM_ARCH__>=7
+#ifdef __ARMEL__
+        rev     r0,r0
+        rev     r1,r1
+        rev     r2,r2
+        rev     r3,r3
+#endif
+        str     r0,[r12,#0]
+        str     r1,[r12,#4]
+        str     r2,[r12,#8]
+        str     r3,[r12,#12]
+#else
+        mov     r4,r0,lsr#24            @ write output in endian-neutral
+        mov     r5,r0,lsr#16            @ manner...
+        mov     r6,r0,lsr#8
+        strb    r4,[r12,#0]
+        strb    r5,[r12,#1]
+        mov     r4,r1,lsr#24
+        strb    r6,[r12,#2]
+        mov     r5,r1,lsr#16
+        strb    r0,[r12,#3]
+        mov     r6,r1,lsr#8
+        strb    r4,[r12,#4]
+        strb    r5,[r12,#5]
+        mov     r4,r2,lsr#24
+        strb    r6,[r12,#6]
+        mov     r5,r2,lsr#16
+        strb    r1,[r12,#7]
+        mov     r6,r2,lsr#8
+        strb    r4,[r12,#8]
+        strb    r5,[r12,#9]
+        mov     r4,r3,lsr#24
+        strb    r6,[r12,#10]
+        mov     r5,r3,lsr#16
+        strb    r2,[r12,#11]
+        mov     r6,r3,lsr#8
+        strb    r4,[r12,#12]
+        strb    r5,[r12,#13]
+        strb    r6,[r12,#14]
+        strb    r3,[r12,#15]
+#endif
+#if __ARM_ARCH__>=5
+        ldmia   sp!,{r4-r12,pc}
+#else
+        ldmia   sp!,{r4-r12,lr}
+        tst     lr,#1
+        moveq   pc,lr                   @ be binary compatible with V4, yet
+        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
+#endif
+.size   AES_decrypt,.-AES_decrypt
+.type   _armv4_AES_decrypt,%function
+.align  2
+_armv4_AES_decrypt:
+        str     lr,[sp,#-4]!            @ push lr
+        ldmia   r11!,{r4-r7}
+        eor     r0,r0,r4
+        ldr     r12,[r11,#240-16]
+        eor     r1,r1,r5
+        eor     r2,r2,r6
+        eor     r3,r3,r7
+        sub     r12,r12,#1
+        mov     lr,#255
+        and     r7,lr,r0,lsr#16
+        and     r8,lr,r0,lsr#8
+        and     r9,lr,r0
+        mov     r0,r0,lsr#24
+.Ldec_loop:
+        ldr     r4,[r10,r7,lsl#2]       @ Td1[s0>>16]
+        and     r7,lr,r1                @ i0
+        ldr     r5,[r10,r8,lsl#2]       @ Td2[s0>>8]
+        and     r8,lr,r1,lsr#16
+        ldr     r6,[r10,r9,lsl#2]       @ Td3[s0>>0]
+        and     r9,lr,r1,lsr#8
+        ldr     r0,[r10,r0,lsl#2]       @ Td0[s0>>24]
+        mov     r1,r1,lsr#24
+        ldr     r7,[r10,r7,lsl#2]       @ Td3[s1>>0]
+        ldr     r8,[r10,r8,lsl#2]       @ Td1[s1>>16]
+        ldr     r9,[r10,r9,lsl#2]       @ Td2[s1>>8]
+        eor     r0,r0,r7,ror#24
+        ldr     r1,[r10,r1,lsl#2]       @ Td0[s1>>24]
+        and     r7,lr,r2,lsr#8  @ i0
+        eor     r5,r8,r5,ror#8
+        and     r8,lr,r2                @ i1
+        eor     r6,r9,r6,ror#8
+        and     r9,lr,r2,lsr#16
+        ldr     r7,[r10,r7,lsl#2]       @ Td2[s2>>8]
+        eor     r1,r1,r4,ror#8
+        ldr     r8,[r10,r8,lsl#2]       @ Td3[s2>>0]
+        mov     r2,r2,lsr#24
+        ldr     r9,[r10,r9,lsl#2]       @ Td1[s2>>16]
+        eor     r0,r0,r7,ror#16
+        ldr     r2,[r10,r2,lsl#2]       @ Td0[s2>>24]
+        and     r7,lr,r3,lsr#16 @ i0
+        eor     r1,r1,r8,ror#24
+        and     r8,lr,r3,lsr#8  @ i1
+        eor     r6,r9,r6,ror#8
+        and     r9,lr,r3                @ i2
+        ldr     r7,[r10,r7,lsl#2]       @ Td1[s3>>16]
+        eor     r2,r2,r5,ror#8
+        ldr     r8,[r10,r8,lsl#2]       @ Td2[s3>>8]
+        mov     r3,r3,lsr#24
+        ldr     r9,[r10,r9,lsl#2]       @ Td3[s3>>0]
+        eor     r0,r0,r7,ror#8
+        ldr     r7,[r11],#16
+        eor     r1,r1,r8,ror#16
+        ldr     r3,[r10,r3,lsl#2]       @ Td0[s3>>24]
+        eor     r2,r2,r9,ror#24
+        ldr     r4,[r11,#-12]
+        eor     r0,r0,r7
+        ldr     r5,[r11,#-8]
+        eor     r3,r3,r6,ror#8
+        ldr     r6,[r11,#-4]
+        and     r7,lr,r0,lsr#16
+        eor     r1,r1,r4
+        and     r8,lr,r0,lsr#8
+        eor     r2,r2,r5
+        and     r9,lr,r0
+        eor     r3,r3,r6
+        mov     r0,r0,lsr#24
+        subs    r12,r12,#1
+        bne     .Ldec_loop
+        add     r10,r10,#1024
+        ldr     r5,[r10,#0]             @ prefetch Td4
+        ldr     r6,[r10,#32]
+        ldr     r4,[r10,#64]
+        ldr     r5,[r10,#96]
+        ldr     r6,[r10,#128]
+        ldr     r4,[r10,#160]
+        ldr     r5,[r10,#192]
+        ldr     r6,[r10,#224]
+        ldrb    r0,[r10,r0]             @ Td4[s0>>24]
+        ldrb    r4,[r10,r7]             @ Td4[s0>>16]
+        and     r7,lr,r1                @ i0
+        ldrb    r5,[r10,r8]             @ Td4[s0>>8]
+        and     r8,lr,r1,lsr#16
+        ldrb    r6,[r10,r9]             @ Td4[s0>>0]
+        and     r9,lr,r1,lsr#8
+        ldrb    r7,[r10,r7]             @ Td4[s1>>0]
+        ldrb    r1,[r10,r1,lsr#24]      @ Td4[s1>>24]
+        ldrb    r8,[r10,r8]             @ Td4[s1>>16]
+        eor     r0,r7,r0,lsl#24
+        ldrb    r9,[r10,r9]             @ Td4[s1>>8]
+        eor     r1,r4,r1,lsl#8
+        and     r7,lr,r2,lsr#8  @ i0
+        eor     r5,r5,r8,lsl#8
+        and     r8,lr,r2                @ i1
+        ldrb    r7,[r10,r7]             @ Td4[s2>>8]
+        eor     r6,r6,r9,lsl#8
+        ldrb    r8,[r10,r8]             @ Td4[s2>>0]
+        and     r9,lr,r2,lsr#16
+        ldrb    r2,[r10,r2,lsr#24]      @ Td4[s2>>24]
+        eor     r0,r0,r7,lsl#8
+        ldrb    r9,[r10,r9]             @ Td4[s2>>16]
+        eor     r1,r8,r1,lsl#16
+        and     r7,lr,r3,lsr#16 @ i0
+        eor     r2,r5,r2,lsl#16
+        and     r8,lr,r3,lsr#8  @ i1
+        ldrb    r7,[r10,r7]             @ Td4[s3>>16]
+        eor     r6,r6,r9,lsl#16
+        ldrb    r8,[r10,r8]             @ Td4[s3>>8]
+        and     r9,lr,r3                @ i2
+        ldrb    r9,[r10,r9]             @ Td4[s3>>0]
+        ldrb    r3,[r10,r3,lsr#24]      @ Td4[s3>>24]
+        eor     r0,r0,r7,lsl#16
+        ldr     r7,[r11,#0]
+        eor     r1,r1,r8,lsl#8
+        ldr     r4,[r11,#4]
+        eor     r2,r9,r2,lsl#8
+        ldr     r5,[r11,#8]
+        eor     r3,r6,r3,lsl#24
+        ldr     r6,[r11,#12]
+        eor     r0,r0,r7
+        eor     r1,r1,r4
+        eor     r2,r2,r5
+        eor     r3,r3,r6
+        sub     r10,r10,#1024
+        ldr     pc,[sp],#4              @ pop and return
+.size   _armv4_AES_decrypt,.-_armv4_AES_decrypt
+.asciz  "AES for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
+.align  2
diff --git a/arch/arm/crypto/aes_glue.c b/arch/arm/crypto/aes_glue.c
new file mode 100644
index 000000000000..59f7877ead6a
--- /dev/null
+++ b/arch/arm/crypto/aes_glue.c
@@ -0,0 +1,108 @@
+/*
+ * Glue Code for the asm optimized version of the AES Cipher Algorithm
+ */
+#include <linux/module.h>
+#include <linux/crypto.h>
+#include <crypto/aes.h>
+#define AES_MAXNR 14
+typedef struct {
+        unsigned int rd_key[4 *(AES_MAXNR + 1)];
+        int rounds;
+} AES_KEY;
+struct AES_CTX {
+        AES_KEY enc_key;
+        AES_KEY dec_key;
+};
+asmlinkage void AES_encrypt(const u8 *in, u8 *out, AES_KEY *ctx);
+asmlinkage void AES_decrypt(const u8 *in, u8 *out, AES_KEY *ctx);
+asmlinkage int private_AES_set_decrypt_key(const unsigned char *userKey, const int bits, AES_KEY *key);
+asmlinkage int private_AES_set_encrypt_key(const unsigned char *userKey, const int bits, AES_KEY *key);
+static void aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
+{
+        struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
+        AES_encrypt(src, dst, &ctx->enc_key);
+}
+static void aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
+{
+        struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
+        AES_decrypt(src, dst, &ctx->dec_key);
+}
+static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
+                unsigned int key_len)
+{
+        struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
+        switch (key_len) {
+        case AES_KEYSIZE_128:
+                key_len = 128;
+                break;
+        case AES_KEYSIZE_192:
+                key_len = 192;
+                break;
+        case AES_KEYSIZE_256:
+                key_len = 256;
+                break;
+        default:
+                tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+                return -EINVAL;
+        }
+        if (private_AES_set_encrypt_key(in_key, key_len, &ctx->enc_key) == -1) {
+                tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+                return -EINVAL;
+        }
+        /* private_AES_set_decrypt_key expects an encryption key as input */
+        ctx->dec_key = ctx->enc_key;
+        if (private_AES_set_decrypt_key(in_key, key_len, &ctx->dec_key) == -1) {
+                tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+                return -EINVAL;
+        }
+        return 0;
+}
+static struct crypto_alg aes_alg = {
+        .cra_name               = "aes",
+        .cra_driver_name        = "aes-asm",
+        .cra_priority           = 200,
+        .cra_flags              = CRYPTO_ALG_TYPE_CIPHER,
+        .cra_blocksize          = AES_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct AES_CTX),
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(aes_alg.cra_list),
+        .cra_u  = {
+                .cipher = {
+                        .cia_min_keysize        = AES_MIN_KEY_SIZE,
+                        .cia_max_keysize        = AES_MAX_KEY_SIZE,
+                        .cia_setkey                     = aes_set_key,
+                        .cia_encrypt            = aes_encrypt,
+                        .cia_decrypt            = aes_decrypt
+                }
+        }
+};
+static int __init aes_init(void)
+{
+        return crypto_register_alg(&aes_alg);
+}
+static void __exit aes_fini(void)
+{
+        crypto_unregister_alg(&aes_alg);
+}
+module_init(aes_init);
+module_exit(aes_fini);
+MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm (ASM)");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("aes");
+MODULE_ALIAS("aes-asm");
+MODULE_AUTHOR("David McCullough <ucdevel@gmail.com>");
diff --git a/arch/arm/crypto/sha1-armv4-large.S b/arch/arm/crypto/sha1-armv4-large.S
new file mode 100644
index 000000000000..7050ab133b9d
--- /dev/null
+++ b/arch/arm/crypto/sha1-armv4-large.S
@@ -0,0 +1,503 @@
+#define __ARM_ARCH__ __LINUX_ARM_ARCH__
+@ ====================================================================
+@ Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
+@ project. The module is, however, dual licensed under OpenSSL and
+@ CRYPTOGAMS licenses depending on where you obtain it. For further
+@ details see http://www.openssl.org/~appro/cryptogams/.
+@ ====================================================================
+@ sha1_block procedure for ARMv4.
+@
+@ January 2007.
+@ Size/performance trade-off
+@ ====================================================================
+@ impl          size in bytes   comp cycles[*]  measured performance
+@ ====================================================================
+@ thumb         304             3212            4420
+@ armv4-small   392/+29%        1958/+64%       2250/+96%
+@ armv4-compact 740/+89%        1552/+26%       1840/+22%
+@ armv4-large   1420/+92%       1307/+19%       1370/+34%[***]
+@ full unroll   ~5100/+260%     ~1260/+4%       ~1300/+5%
+@ ====================================================================
+@ thumb         = same as 'small' but in Thumb instructions[**] and
+@                 with recurring code in two private functions;
+@ small         = detached Xload/update, loops are folded;
+@ compact       = detached Xload/update, 5x unroll;
+@ large         = interleaved Xload/update, 5x unroll;
+@ full unroll   = interleaved Xload/update, full unroll, estimated[!];
+@
+@ [*]   Manually counted instructions in "grand" loop body. Measured
+@       performance is affected by prologue and epilogue overhead,
+@       i-cache availability, branch penalties, etc.
+@ [**]  While each Thumb instruction is twice smaller, they are not as
+@       diverse as ARM ones: e.g., there are only two arithmetic
+@       instructions with 3 arguments, no [fixed] rotate, addressing
+@       modes are limited. As result it takes more instructions to do
+@       the same job in Thumb, therefore the code is never twice as
+@       small and always slower.
+@ [***] which is also ~35% better than compiler generated code. Dual-
+@       issue Cortex A8 core was measured to process input block in
+@       ~990 cycles.
+@ August 2010.
+@
+@ Rescheduling for dual-issue pipeline resulted in 13% improvement on
+@ Cortex A8 core and in absolute terms ~870 cycles per input block
+@ [or 13.6 cycles per byte].
+@ February 2011.
+@
+@ Profiler-assisted and platform-specific optimization resulted in 10%
+@ improvement on Cortex A8 core and 12.2 cycles per byte.
+.text
+.global sha1_block_data_order
+.type   sha1_block_data_order,%function
+.align  2
+sha1_block_data_order:
+        stmdb   sp!,{r4-r12,lr}
+        add     r2,r1,r2,lsl#6  @ r2 to point at the end of r1
+        ldmia   r0,{r3,r4,r5,r6,r7}
+.Lloop:
+        ldr     r8,.LK_00_19
+        mov     r14,sp
+        sub     sp,sp,#15*4
+        mov     r5,r5,ror#30
+        mov     r6,r6,ror#30
+        mov     r7,r7,ror#30            @ [6]
+.L_00_15:
+#if __ARM_ARCH__<7
+        ldrb    r10,[r1,#2]
+        ldrb    r9,[r1,#3]
+        ldrb    r11,[r1,#1]
+        add     r7,r8,r7,ror#2                  @ E+=K_00_19
+        ldrb    r12,[r1],#4
+        orr     r9,r9,r10,lsl#8
+        eor     r10,r5,r6                       @ F_xx_xx
+        orr     r9,r9,r11,lsl#16
+        add     r7,r7,r3,ror#27                 @ E+=ROR(A,27)
+        orr     r9,r9,r12,lsl#24
+#else
+        ldr     r9,[r1],#4                      @ handles unaligned
+        add     r7,r8,r7,ror#2                  @ E+=K_00_19
+        eor     r10,r5,r6                       @ F_xx_xx
+        add     r7,r7,r3,ror#27                 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+        rev     r9,r9                           @ byte swap
+#endif
+#endif
+        and     r10,r4,r10,ror#2
+        add     r7,r7,r9                        @ E+=X[i]
+        eor     r10,r10,r6,ror#2                @ F_00_19(B,C,D)
+        str     r9,[r14,#-4]!
+        add     r7,r7,r10                       @ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+        ldrb    r10,[r1,#2]
+        ldrb    r9,[r1,#3]
+        ldrb    r11,[r1,#1]
+        add     r6,r8,r6,ror#2                  @ E+=K_00_19
+        ldrb    r12,[r1],#4
+        orr     r9,r9,r10,lsl#8
+        eor     r10,r4,r5                       @ F_xx_xx
+        orr     r9,r9,r11,lsl#16
+        add     r6,r6,r7,ror#27                 @ E+=ROR(A,27)
+        orr     r9,r9,r12,lsl#24
+#else
+        ldr     r9,[r1],#4                      @ handles unaligned
+        add     r6,r8,r6,ror#2                  @ E+=K_00_19
+        eor     r10,r4,r5                       @ F_xx_xx
+        add     r6,r6,r7,ror#27                 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+        rev     r9,r9                           @ byte swap
+#endif
+#endif
+        and     r10,r3,r10,ror#2
+        add     r6,r6,r9                        @ E+=X[i]
+        eor     r10,r10,r5,ror#2                @ F_00_19(B,C,D)
+        str     r9,[r14,#-4]!
+        add     r6,r6,r10                       @ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+        ldrb    r10,[r1,#2]
+        ldrb    r9,[r1,#3]
+        ldrb    r11,[r1,#1]
+        add     r5,r8,r5,ror#2                  @ E+=K_00_19
+        ldrb    r12,[r1],#4
+        orr     r9,r9,r10,lsl#8
+        eor     r10,r3,r4                       @ F_xx_xx
+        orr     r9,r9,r11,lsl#16
+        add     r5,r5,r6,ror#27                 @ E+=ROR(A,27)
+        orr     r9,r9,r12,lsl#24
+#else
+        ldr     r9,[r1],#4                      @ handles unaligned
+        add     r5,r8,r5,ror#2                  @ E+=K_00_19
+        eor     r10,r3,r4                       @ F_xx_xx
+        add     r5,r5,r6,ror#27                 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+        rev     r9,r9                           @ byte swap
+#endif
+#endif
+        and     r10,r7,r10,ror#2
+        add     r5,r5,r9                        @ E+=X[i]
+        eor     r10,r10,r4,ror#2                @ F_00_19(B,C,D)
+        str     r9,[r14,#-4]!
+        add     r5,r5,r10                       @ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+        ldrb    r10,[r1,#2]
+        ldrb    r9,[r1,#3]
+        ldrb    r11,[r1,#1]
+        add     r4,r8,r4,ror#2                  @ E+=K_00_19
+        ldrb    r12,[r1],#4
+        orr     r9,r9,r10,lsl#8
+        eor     r10,r7,r3                       @ F_xx_xx
+        orr     r9,r9,r11,lsl#16
+        add     r4,r4,r5,ror#27                 @ E+=ROR(A,27)
+        orr     r9,r9,r12,lsl#24
+#else
+        ldr     r9,[r1],#4                      @ handles unaligned
+        add     r4,r8,r4,ror#2                  @ E+=K_00_19
+        eor     r10,r7,r3                       @ F_xx_xx
+        add     r4,r4,r5,ror#27                 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+        rev     r9,r9                           @ byte swap
+#endif
+#endif
+        and     r10,r6,r10,ror#2
+        add     r4,r4,r9                        @ E+=X[i]
+        eor     r10,r10,r3,ror#2                @ F_00_19(B,C,D)
+        str     r9,[r14,#-4]!
+        add     r4,r4,r10                       @ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+        ldrb    r10,[r1,#2]
+        ldrb    r9,[r1,#3]
+        ldrb    r11,[r1,#1]
+        add     r3,r8,r3,ror#2                  @ E+=K_00_19
+        ldrb    r12,[r1],#4
+        orr     r9,r9,r10,lsl#8
+        eor     r10,r6,r7                       @ F_xx_xx
+        orr     r9,r9,r11,lsl#16
+        add     r3,r3,r4,ror#27                 @ E+=ROR(A,27)
+        orr     r9,r9,r12,lsl#24
+#else
+        ldr     r9,[r1],#4                      @ handles unaligned
+        add     r3,r8,r3,ror#2                  @ E+=K_00_19
+        eor     r10,r6,r7                       @ F_xx_xx
+        add     r3,r3,r4,ror#27                 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+        rev     r9,r9                           @ byte swap
+#endif
+#endif
+        and     r10,r5,r10,ror#2
+        add     r3,r3,r9                        @ E+=X[i]
+        eor     r10,r10,r7,ror#2                @ F_00_19(B,C,D)
+        str     r9,[r14,#-4]!
+        add     r3,r3,r10                       @ E+=F_00_19(B,C,D)
+        teq     r14,sp
+        bne     .L_00_15                @ [((11+4)*5+2)*3]
+#if __ARM_ARCH__<7
+        ldrb    r10,[r1,#2]
+        ldrb    r9,[r1,#3]
+        ldrb    r11,[r1,#1]
+        add     r7,r8,r7,ror#2                  @ E+=K_00_19
+        ldrb    r12,[r1],#4
+        orr     r9,r9,r10,lsl#8
+        eor     r10,r5,r6                       @ F_xx_xx
+        orr     r9,r9,r11,lsl#16
+        add     r7,r7,r3,ror#27                 @ E+=ROR(A,27)
+        orr     r9,r9,r12,lsl#24
+#else
+        ldr     r9,[r1],#4                      @ handles unaligned
+        add     r7,r8,r7,ror#2                  @ E+=K_00_19
+        eor     r10,r5,r6                       @ F_xx_xx
+        add     r7,r7,r3,ror#27                 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+        rev     r9,r9                           @ byte swap
+#endif
+#endif
+        and     r10,r4,r10,ror#2
+        add     r7,r7,r9                        @ E+=X[i]
+        eor     r10,r10,r6,ror#2                @ F_00_19(B,C,D)
+        str     r9,[r14,#-4]!
+        add     r7,r7,r10                       @ E+=F_00_19(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r6,r8,r6,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r4,r5                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r6,r6,r7,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r3,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r6,r6,r9                        @ E+=X[i]
+        eor     r10,r10,r5,ror#2                @ F_00_19(B,C,D)
+        add     r6,r6,r10                       @ E+=F_00_19(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r5,r8,r5,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r3,r4                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r5,r5,r6,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r7,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r5,r5,r9                        @ E+=X[i]
+        eor     r10,r10,r4,ror#2                @ F_00_19(B,C,D)
+        add     r5,r5,r10                       @ E+=F_00_19(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r4,r8,r4,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r7,r3                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r4,r4,r5,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r6,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r4,r4,r9                        @ E+=X[i]
+        eor     r10,r10,r3,ror#2                @ F_00_19(B,C,D)
+        add     r4,r4,r10                       @ E+=F_00_19(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r3,r8,r3,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r6,r7                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r3,r3,r4,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r5,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r3,r3,r9                        @ E+=X[i]
+        eor     r10,r10,r7,ror#2                @ F_00_19(B,C,D)
+        add     r3,r3,r10                       @ E+=F_00_19(B,C,D)
+        ldr     r8,.LK_20_39            @ [+15+16*4]
+        sub     sp,sp,#25*4
+        cmn     sp,#0                   @ [+3], clear carry to denote 20_39
+.L_20_39_or_60_79:
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r7,r8,r7,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r5,r6                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r7,r7,r3,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        eor r10,r4,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r7,r7,r9                        @ E+=X[i]
+        add     r7,r7,r10                       @ E+=F_20_39(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r6,r8,r6,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r4,r5                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r6,r6,r7,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        eor r10,r3,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r6,r6,r9                        @ E+=X[i]
+        add     r6,r6,r10                       @ E+=F_20_39(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r5,r8,r5,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r3,r4                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r5,r5,r6,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        eor r10,r7,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r5,r5,r9                        @ E+=X[i]
+        add     r5,r5,r10                       @ E+=F_20_39(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r4,r8,r4,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r7,r3                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r4,r4,r5,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        eor r10,r6,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r4,r4,r9                        @ E+=X[i]
+        add     r4,r4,r10                       @ E+=F_20_39(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r3,r8,r3,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r6,r7                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r3,r3,r4,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        eor r10,r5,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r3,r3,r9                        @ E+=X[i]
+        add     r3,r3,r10                       @ E+=F_20_39(B,C,D)
+        teq     r14,sp                  @ preserve carry
+        bne     .L_20_39_or_60_79       @ [+((12+3)*5+2)*4]
+        bcs     .L_done                 @ [+((12+3)*5+2)*4], spare 300 bytes
+        ldr     r8,.LK_40_59
+        sub     sp,sp,#20*4             @ [+2]
+.L_40_59:
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r7,r8,r7,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r5,r6                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r7,r7,r3,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r4,r10,ror#2                                    @ F_xx_xx
+        and r11,r5,r6                                   @ F_xx_xx
+        add     r7,r7,r9                        @ E+=X[i]
+        add     r7,r7,r10                       @ E+=F_40_59(B,C,D)
+        add     r7,r7,r11,ror#2
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r6,r8,r6,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r4,r5                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r6,r6,r7,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r3,r10,ror#2                                    @ F_xx_xx
+        and r11,r4,r5                                   @ F_xx_xx
+        add     r6,r6,r9                        @ E+=X[i]
+        add     r6,r6,r10                       @ E+=F_40_59(B,C,D)
+        add     r6,r6,r11,ror#2
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r5,r8,r5,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r3,r4                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r5,r5,r6,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r7,r10,ror#2                                    @ F_xx_xx
+        and r11,r3,r4                                   @ F_xx_xx
+        add     r5,r5,r9                        @ E+=X[i]
+        add     r5,r5,r10                       @ E+=F_40_59(B,C,D)
+        add     r5,r5,r11,ror#2
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r4,r8,r4,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r7,r3                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r4,r4,r5,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r6,r10,ror#2                                    @ F_xx_xx
+        and r11,r7,r3                                   @ F_xx_xx
+        add     r4,r4,r9                        @ E+=X[i]
+        add     r4,r4,r10                       @ E+=F_40_59(B,C,D)
+        add     r4,r4,r11,ror#2
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r3,r8,r3,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r6,r7                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r3,r3,r4,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r5,r10,ror#2                                    @ F_xx_xx
+        and r11,r6,r7                                   @ F_xx_xx
+        add     r3,r3,r9                        @ E+=X[i]
+        add     r3,r3,r10                       @ E+=F_40_59(B,C,D)
+        add     r3,r3,r11,ror#2
+        teq     r14,sp
+        bne     .L_40_59                @ [+((12+5)*5+2)*4]
+        ldr     r8,.LK_60_79
+        sub     sp,sp,#20*4
+        cmp     sp,#0                   @ set carry to denote 60_79
+        b       .L_20_39_or_60_79       @ [+4], spare 300 bytes
+.L_done:
+        add     sp,sp,#80*4             @ "deallocate" stack frame
+        ldmia   r0,{r8,r9,r10,r11,r12}
+        add     r3,r8,r3
+        add     r4,r9,r4
+        add     r5,r10,r5,ror#2
+        add     r6,r11,r6,ror#2
+        add     r7,r12,r7,ror#2
+        stmia   r0,{r3,r4,r5,r6,r7}
+        teq     r1,r2
+        bne     .Lloop                  @ [+18], total 1307
+#if __ARM_ARCH__>=5
+        ldmia   sp!,{r4-r12,pc}
+#else
+        ldmia   sp!,{r4-r12,lr}
+        tst     lr,#1
+        moveq   pc,lr                   @ be binary compatible with V4, yet
+        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
+#endif
+.align  2
+.LK_00_19:      .word   0x5a827999
+.LK_20_39:      .word   0x6ed9eba1
+.LK_40_59:      .word   0x8f1bbcdc
+.LK_60_79:      .word   0xca62c1d6
+.size   sha1_block_data_order,.-sha1_block_data_order
+.asciz  "SHA1 block transform for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
+.align  2
diff --git a/arch/arm/crypto/sha1_glue.c b/arch/arm/crypto/sha1_glue.c
new file mode 100644
index 000000000000..76cd976230bc
--- /dev/null
+++ b/arch/arm/crypto/sha1_glue.c
@@ -0,0 +1,179 @@
+/*
+ * Cryptographic API.
+ * Glue code for the SHA1 Secure Hash Algorithm assembler implementation
+ *
+ * This file is based on sha1_generic.c and sha1_ssse3_glue.c
+ *
+ * Copyright (c) Alan Smithee.
+ * Copyright (c) Andrew McDonald <andrew@mcdonald.org.uk>
+ * Copyright (c) Jean-Francois Dive <jef@linuxbe.org>
+ * Copyright (c) Mathias Krause <minipli@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ */
+#include <crypto/internal/hash.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/cryptohash.h>
+#include <linux/types.h>
+#include <crypto/sha.h>
+#include <asm/byteorder.h>
+struct SHA1_CTX {
+        uint32_t h0,h1,h2,h3,h4;
+        u64 count;
+        u8 data[SHA1_BLOCK_SIZE];
+};
+asmlinkage void sha1_block_data_order(struct SHA1_CTX *digest,
+                const unsigned char *data, unsigned int rounds);
+static int sha1_init(struct shash_desc *desc)
+{
+        struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+        memset(sctx, 0, sizeof(*sctx));
+        sctx->h0 = SHA1_H0;
+        sctx->h1 = SHA1_H1;
+        sctx->h2 = SHA1_H2;
+        sctx->h3 = SHA1_H3;
+        sctx->h4 = SHA1_H4;
+        return 0;
+}
+static int __sha1_update(struct SHA1_CTX *sctx, const u8 *data,
+                               unsigned int len, unsigned int partial)
+{
+        unsigned int done = 0;
+        sctx->count += len;
+        if (partial) {
+                done = SHA1_BLOCK_SIZE - partial;
+                memcpy(sctx->data + partial, data, done);
+                sha1_block_data_order(sctx, sctx->data, 1);
+        }
+        if (len - done >= SHA1_BLOCK_SIZE) {
+                const unsigned int rounds = (len - done) / SHA1_BLOCK_SIZE;
+                sha1_block_data_order(sctx, data + done, rounds);
+                done += rounds * SHA1_BLOCK_SIZE;
+        }
+        memcpy(sctx->data, data + done, len - done);
+        return 0;
+}
+static int sha1_update(struct shash_desc *desc, const u8 *data,
+                             unsigned int len)
+{
+        struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+        unsigned int partial = sctx->count % SHA1_BLOCK_SIZE;
+        int res;
+        /* Handle the fast case right here */
+        if (partial + len < SHA1_BLOCK_SIZE) {
+                sctx->count += len;
+                memcpy(sctx->data + partial, data, len);
+                return 0;
+        }
+        res = __sha1_update(sctx, data, len, partial);
+        return res;
+}
+/* Add padding and return the message digest. */
+static int sha1_final(struct shash_desc *desc, u8 *out)
+{
+        struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+        unsigned int i, index, padlen;
+        __be32 *dst = (__be32 *)out;
+        __be64 bits;
+        static const u8 padding[SHA1_BLOCK_SIZE] = { 0x80, };
+        bits = cpu_to_be64(sctx->count << 3);
+        /* Pad out to 56 mod 64 and append length */
+        index = sctx->count % SHA1_BLOCK_SIZE;
+        padlen = (index < 56) ? (56 - index) : ((SHA1_BLOCK_SIZE+56) - index);
+        /* We need to fill a whole block for __sha1_update() */
+        if (padlen <= 56) {
+                sctx->count += padlen;
+                memcpy(sctx->data + index, padding, padlen);
+        } else {
+                __sha1_update(sctx, padding, padlen, index);
+        }
+        __sha1_update(sctx, (const u8 *)&bits, sizeof(bits), 56);
+        /* Store state in digest */
+        for (i = 0; i < 5; i++)
+                dst[i] = cpu_to_be32(((u32 *)sctx)[i]);
+        /* Wipe context */
+        memset(sctx, 0, sizeof(*sctx));
+        return 0;
+}
+static int sha1_export(struct shash_desc *desc, void *out)
+{
+        struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+        memcpy(out, sctx, sizeof(*sctx));
+        return 0;
+}
+static int sha1_import(struct shash_desc *desc, const void *in)
+{
+        struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+        memcpy(sctx, in, sizeof(*sctx));
+        return 0;
+}
+static struct shash_alg alg = {
+        .digestsize     =       SHA1_DIGEST_SIZE,
+        .init           =       sha1_init,
+        .update         =       sha1_update,
+        .final          =       sha1_final,
+        .export         =       sha1_export,
+        .import         =       sha1_import,
+        .descsize       =       sizeof(struct SHA1_CTX),
+        .statesize      =       sizeof(struct SHA1_CTX),
+        .base           =       {
+                .cra_name       =       "sha1",
+                .cra_driver_name=       "sha1-asm",
+                .cra_priority   =       150,
+                .cra_flags      =       CRYPTO_ALG_TYPE_SHASH,
+                .cra_blocksize  =       SHA1_BLOCK_SIZE,
+                .cra_module     =       THIS_MODULE,
+        }
+};
+static int __init sha1_mod_init(void)
+{
+        return crypto_register_shash(&alg);
+}
+static void __exit sha1_mod_fini(void)
+{
+        crypto_unregister_shash(&alg);
+}
+module_init(sha1_mod_init);
+module_exit(sha1_mod_fini);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm (ARM)");
+MODULE_ALIAS("sha1");
+MODULE_AUTHOR("David McCullough <ucdevel@gmail.com>");
diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index 960abceb8e14..8a7196ca5106 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -5,16 +5,33 @@ header-y += hwcap.h
 generic-y += auxvec.h
 generic-y += bitsperlong.h
 generic-y += cputime.h
+generic-y += current.h
 generic-y += emergency-restart.h
 generic-y += errno.h
+generic-y += exec.h
 generic-y += ioctl.h
+generic-y += ipcbuf.h
 generic-y += irq_regs.h
 generic-y += kdebug.h
 generic-y += local.h
 generic-y += local64.h
+generic-y += msgbuf.h
+generic-y += param.h
+generic-y += parport.h
 generic-y += percpu.h
 generic-y += poll.h
 generic-y += resource.h
 generic-y += sections.h
+generic-y += segment.h
+generic-y += sembuf.h
+generic-y += serial.h
+generic-y += shmbuf.h
 generic-y += siginfo.h
 generic-y += sizes.h
+generic-y += socket.h
+generic-y += sockios.h
+generic-y += termbits.h
+generic-y += termios.h
+generic-y += timex.h
+generic-y += types.h
+generic-y += unaligned.h
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 62e75475e57e..d40229d9a1c9 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -2,11 +2,12 @@
 #define __ASMARM_ARCH_TIMER_H
 #include <asm/errno.h>
+#include <linux/clocksource.h>
 #ifdef CONFIG_ARM_ARCH_TIMER
-#define ARCH_HAS_READ_CURRENT_TIMER
 int arch_timer_of_register(void);
 int arch_timer_sched_clock_init(void);
+struct timecounter *arch_timer_get_timecounter(void);
 #else
 static inline int arch_timer_of_register(void)
 {
@@ -17,6 +18,11 @@ static inline int arch_timer_sched_clock_init(void)
 {
        return -ENXIO;
 }
+static inline struct timecounter *arch_timer_get_timecounter(void)
+{
+        return NULL;
+}
 #endif
 #endif
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 5c8b3bf4d825..2ef95813fce0 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -22,6 +22,7 @@
 #include <asm/ptrace.h>
 #include <asm/domain.h>
+#include <asm/opcodes-virt.h>
 #define IOMEM(x)        (x)
@@ -240,6 +241,34 @@
 #endif
 /*
+ * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
+ * a scratch register for the macro to overwrite.
+ *
+ * This macro is intended for forcing the CPU into SVC mode at boot time.
+ * you cannot return to the original mode.
+ *
+ * Beware, it also clobers LR.
+ */
+.macro safe_svcmode_maskall reg:req
+        mrs     \reg , cpsr
+        mov     lr , \reg
+        and     lr , lr , #MODE_MASK
+        cmp     lr , #HYP_MODE
+        orr     \reg , \reg , #PSR_I_BIT | PSR_F_BIT
+        bic     \reg , \reg , #MODE_MASK
+        orr     \reg , \reg , #SVC_MODE
+THUMB(  orr     \reg , \reg , #PSR_T_BIT        )
+        bne     1f
+        orr     \reg, \reg, #PSR_A_BIT
+        adr     lr, BSYM(2f)
+        msr     spsr_cxsf, \reg
+        __MSR_ELR_HYP(14)
+        __ERET
+1:      msr     cpsr_c, \reg
+2:
+.endm
+/*
 * STRT/LDRT access macros with ARM and Thumb-2 variants
 */
 #ifdef CONFIG_THUMB2_KERNEL
diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
index 05112380dc53..8dcd9c702d90 100644
--- a/arch/arm/include/asm/barrier.h
+++ b/arch/arm/include/asm/barrier.h
@@ -44,10 +44,9 @@
 #define rmb()           dsb()
 #define wmb()           mb()
 #else
-#include <asm/memory.h>
+#define mb()            barrier()
-#define mb()    do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
+#define rmb()           barrier()
-#define rmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
+#define wmb()           barrier()
-#define wmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 #endif
 #ifndef CONFIG_SMP
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index e4448e16046d..e1489c54cd12 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -49,6 +49,13 @@
 *
 *              Unconditionally clean and invalidate the entire cache.
 *
+ *     flush_kern_louis()
+ *
+ *             Flush data cache levels up to the level of unification
+ *             inner shareable and invalidate the I-cache.
+ *             Only needed from v7 onwards, falls back to flush_cache_all()
+ *             for all other processor versions.
+ *
 *      flush_user_all()
 *
 *              Clean and invalidate all user space cache entries
@@ -97,6 +104,7 @@
 struct cpu_cache_fns {
        void (*flush_icache_all)(void);
        void (*flush_kern_all)(void);
+        void (*flush_kern_louis)(void);
        void (*flush_user_all)(void);
        void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
@@ -119,6 +127,7 @@ extern struct cpu_cache_fns cpu_cache;
 #define __cpuc_flush_icache_all         cpu_cache.flush_icache_all
 #define __cpuc_flush_kern_all           cpu_cache.flush_kern_all
+#define __cpuc_flush_kern_louis         cpu_cache.flush_kern_louis
 #define __cpuc_flush_user_all           cpu_cache.flush_user_all
 #define __cpuc_flush_user_range         cpu_cache.flush_user_range
 #define __cpuc_coherent_kern_range      cpu_cache.coherent_kern_range
@@ -139,6 +148,7 @@ extern struct cpu_cache_fns cpu_cache;
 extern void __cpuc_flush_icache_all(void);
 extern void __cpuc_flush_kern_all(void);
+extern void __cpuc_flush_kern_louis(void);
 extern void __cpuc_flush_user_all(void);
 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
@@ -204,6 +214,11 @@ static inline void __flush_icache_all(void)
        __flush_icache_preferred();
 }
+/*
+ * Flush caches up to Level of Unification Inner Shareable
+ */
+#define flush_cache_louis()             __cpuc_flush_kern_louis()
 #define flush_cache_all()               __cpuc_flush_kern_all()
 static inline void vivt_flush_cache_mm(struct mm_struct *mm)
diff --git a/arch/arm/include/asm/current.h b/arch/arm/include/asm/current.h
deleted file mode 100644
index 75d21e2a3ff7..000000000000
--- a/arch/arm/include/asm/current.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _ASMARM_CURRENT_H
-#define _ASMARM_CURRENT_H
-#include <linux/thread_info.h>
-static inline struct task_struct *get_current(void) __attribute_const__;
-static inline struct task_struct *get_current(void)
-{
-        return current_thread_info()->task;
-}
-#define current (get_current())
-#endif /* _ASMARM_CURRENT_H */
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index dc6145120de3..ab98fdd083bd 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -15,6 +15,11 @@
 #ifndef __ASSEMBLY__
+struct delay_timer {
+        unsigned long (*read_current_timer)(void);
+        unsigned long freq;
+};
 extern struct arm_delay_ops {
        void (*delay)(unsigned long);
        void (*const_udelay)(unsigned long);
@@ -56,6 +61,10 @@ extern void __loop_delay(unsigned long loops);
 extern void __loop_udelay(unsigned long usecs);
 extern void __loop_const_udelay(unsigned long);
+/* Delay-loop timer registration. */
+#define ARCH_HAS_READ_CURRENT_TIMER
+extern void register_current_timer_delay(const struct delay_timer *timer);
 #endif /* __ASSEMBLY__ */
 #endif /* defined(_ARM_DELAY_H) */
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 5c44dcb0987b..23004847bb05 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -13,6 +13,7 @@
 #define DMA_ERROR_CODE  (~0)
 extern struct dma_map_ops arm_dma_ops;
+extern struct dma_map_ops arm_coherent_dma_ops;
 static inline struct dma_map_ops *get_dma_ops(struct device *dev)
 {
diff --git a/arch/arm/include/asm/exec.h b/arch/arm/include/asm/exec.h
deleted file mode 100644
index 7c4fbef72b3a..000000000000
--- a/arch/arm/include/asm/exec.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_ARM_EXEC_H
-#define __ASM_ARM_EXEC_H
-#define arch_align_stack(x) (x)
-#endif /* __ASM_ARM_EXEC_H */
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index 7e30874377e6..cca9f15704ed 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -110,19 +110,19 @@
 #endif
 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
-//# ifdef _CACHE
+# ifdef _CACHE
 #  define MULTI_CACHE 1
-//# else
+# else
-//#  define _CACHE v6
+#  define _CACHE v6
-//# endif
+# endif
 #endif
 #if defined(CONFIG_CPU_V7)
-//# ifdef _CACHE
+# ifdef _CACHE
 #  define MULTI_CACHE 1
-//# else
+# else
-//#  define _CACHE v7
+#  define _CACHE v7
-//# endif
+# endif
 #endif
 #if !defined(_CACHE) && !defined(MULTI_CACHE)
@@ -132,6 +132,7 @@
 #ifndef MULTI_CACHE
 #define __cpuc_flush_icache_all         __glue(_CACHE,_flush_icache_all)
 #define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
+#define __cpuc_flush_kern_louis         __glue(_CACHE,_flush_kern_cache_louis)
 #define __cpuc_flush_user_all           __glue(_CACHE,_flush_user_cache_all)
 #define __cpuc_flush_user_range         __glue(_CACHE,_flush_user_cache_range)
 #define __cpuc_coherent_kern_range      __glue(_CACHE,_coherent_kern_range)
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index c402e9b31f4c..477e0206e016 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -6,7 +6,9 @@
 #endif
 /* not all ARM platforms necessarily support this API ... */
+#ifdef CONFIG_NEED_MACH_GPIO_H
 #include <mach/gpio.h>
+#endif
 #ifndef __ARM_GPIOLIB_COMPLEX
 /* Note: this may rely upon the value of ARCH_NR_GPIOS set in mach/gpio.h */
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h
index 436e60b2cf7a..2740c2a2df63 100644
--- a/arch/arm/include/asm/hardirq.h
+++ b/arch/arm/include/asm/hardirq.h
@@ -5,7 +5,7 @@
 #include <linux/threads.h>
 #include <asm/irq.h>
-#define NR_IPI  5
+#define NR_IPI  6
 typedef struct {
        unsigned int __softirq_pending;
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h
index 538f17ca905b..295e2e40151b 100644
--- a/arch/arm/include/asm/hardware/cache-tauros2.h
+++ b/arch/arm/include/asm/hardware/cache-tauros2.h
@@ -8,4 +8,7 @@
 * warranty of any kind, whether express or implied.
 */
-extern void __init tauros2_init(void);
+#define CACHE_TAUROS2_PREFETCH_ON       (1 << 0)
+#define CACHE_TAUROS2_LINEFILL_BURST8   (1 << 1)
+extern void __init tauros2_init(unsigned int features);
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index 2ff2c75a4639..02fe2fbe2477 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -217,18 +217,8 @@ extern int iop3xx_get_init_atu(void);
 #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
 #define IOP3XX_PCI_MEM_WINDOW_SIZE      0x08000000
-#define IOP3XX_PCI_IO_WINDOW_SIZE       0x00010000
 #define IOP3XX_PCI_LOWER_IO_PA          0x90000000
-#define IOP3XX_PCI_LOWER_IO_VA          0xfe000000
+#define IOP3XX_PCI_LOWER_IO_BA          0x00000000
-#define IOP3XX_PCI_LOWER_IO_BA          0x90000000
-#define IOP3XX_PCI_UPPER_IO_PA          (IOP3XX_PCI_LOWER_IO_PA +\
-                                        IOP3XX_PCI_IO_WINDOW_SIZE - 1)
-#define IOP3XX_PCI_UPPER_IO_VA          (IOP3XX_PCI_LOWER_IO_VA +\
-                                        IOP3XX_PCI_IO_WINDOW_SIZE - 1)
-#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\
-                                        IOP3XX_PCI_LOWER_IO_PA) +\
-                                        IOP3XX_PCI_LOWER_IO_VA)
 #ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/hardware/linkup-l1110.h b/arch/arm/include/asm/hardware/linkup-l1110.h
deleted file mode 100644
index 7ec91168a576..000000000000
--- a/arch/arm/include/asm/hardware/linkup-l1110.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
-*
-* Definitions for H3600 Handheld Computer
-*
-* Copyright 2001 Compaq Computer Corporation.
-*
-* Use consistent with the GNU GPL is permitted,
-* provided that this copyright notice is
-* preserved in its entirety in all copies and derived works.
-*
-* COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
-* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
-* FITNESS FOR ANY PARTICULAR PURPOSE.
-*
-* Author: Jamey Hicks.
-*
-*/
-/* LinkUp Systems PCCard/CompactFlash Interface for SA-1100 */
-/* PC Card Status Register */
-#define LINKUP_PRS_S1   (1 << 0) /* voltage control bits S1-S4 */
-#define LINKUP_PRS_S2   (1 << 1)
-#define LINKUP_PRS_S3   (1 << 2)
-#define LINKUP_PRS_S4   (1 << 3)
-#define LINKUP_PRS_BVD1 (1 << 4)
-#define LINKUP_PRS_BVD2 (1 << 5)
-#define LINKUP_PRS_VS1  (1 << 6)
-#define LINKUP_PRS_VS2  (1 << 7)
-#define LINKUP_PRS_RDY  (1 << 8)
-#define LINKUP_PRS_CD1  (1 << 9)
-#define LINKUP_PRS_CD2  (1 << 10)
-/* PC Card Command Register */
-#define LINKUP_PRC_S1   (1 << 0)
-#define LINKUP_PRC_S2   (1 << 1)
-#define LINKUP_PRC_S3   (1 << 2)
-#define LINKUP_PRC_S4   (1 << 3)
-#define LINKUP_PRC_RESET (1 << 4)
-#define LINKUP_PRC_APOE (1 << 5) /* Auto Power Off Enable: clears S1-S4 when either nCD goes high */
-#define LINKUP_PRC_CFE  (1 << 6) /* CompactFlash mode Enable: addresses A[10:0] only, A[25:11] high */
-#define LINKUP_PRC_SOE  (1 << 7) /* signal output driver enable */
-#define LINKUP_PRC_SSP  (1 << 8) /* sock select polarity: 0 for socket 0, 1 for socket 1 */
-#define LINKUP_PRC_MBZ  (1 << 15) /* must be zero */
-struct linkup_l1110 {
-        volatile short prc;
-};
diff --git a/arch/arm/include/asm/hypervisor.h b/arch/arm/include/asm/hypervisor.h
new file mode 100644
index 000000000000..b90d9e523d6f
--- /dev/null
+++ b/arch/arm/include/asm/hypervisor.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_ARM_HYPERVISOR_H
+#define _ASM_ARM_HYPERVISOR_H
+#include <asm/xen/hypervisor.h>
+#endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 815c669fec0a..35c1ed89b936 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -47,13 +47,68 @@ extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
-#define __raw_writeb(v,a)       ((void)(__chk_io_ptr(a), *(volatile unsigned char __force  *)(a) = (v)))
+#if __LINUX_ARM_ARCH__ < 6
-#define __raw_writew(v,a)       ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
+/*
-#define __raw_writel(v,a)       ((void)(__chk_io_ptr(a), *(volatile unsigned int __force   *)(a) = (v)))
+ * Half-word accesses are problematic with RiscPC due to limitations of
+ * the bus. Rather than special-case the machine, just let the compiler
+ * generate the access for CPUs prior to ARMv6.
+ */
+#define __raw_readw(a)         (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
+#define __raw_writew(v,a)      ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
+#else
+/*
+ * When running under a hypervisor, we want to avoid I/O accesses with
+ * writeback addressing modes as these incur a significant performance
+ * overhead (the address generation must be emulated in software).
+ */
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+        asm volatile("strh %1, %0"
+                     : "+Qo" (*(volatile u16 __force *)addr)
+                     : "r" (val));
+}
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+        u16 val;
+        asm volatile("ldrh %1, %0"
+                     : "+Qo" (*(volatile u16 __force *)addr),
+                       "=r" (val));
+        return val;
+}
+#endif
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
+{
+        asm volatile("strb %1, %0"
+                     : "+Qo" (*(volatile u8 __force *)addr)
+                     : "r" (val));
+}
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+        asm volatile("str %1, %0"
+                     : "+Qo" (*(volatile u32 __force *)addr)
+                     : "r" (val));
+}
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+        u8 val;
+        asm volatile("ldrb %1, %0"
+                     : "+Qo" (*(volatile u8 __force *)addr),
+                       "=r" (val));
+        return val;
+}
-#define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned char __force  *)(a))
+static inline u32 __raw_readl(const volatile void __iomem *addr)
-#define __raw_readw(a)          (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
+{
-#define __raw_readl(a)          (__chk_io_ptr(a), *(volatile unsigned int __force   *)(a))
+        u32 val;
+        asm volatile("ldr %1, %0"
+                     : "+Qo" (*(volatile u32 __force *)addr),
+                       "=r" (val));
+        return val;
+}
 /*
 * Architecture ioremap implementation.
@@ -113,11 +168,19 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 #define __iowmb()               do { } while (0)
 #endif
+/* PCI fixed i/o mapping */
+#define PCI_IO_VIRT_BASE        0xfee00000
+extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
 /*
 * Now, pick up the machine-defined IO definitions
 */
 #ifdef CONFIG_NEED_MACH_IO_H
 #include <mach/io.h>
+#elif defined(CONFIG_PCI)
+#define IO_SPACE_LIMIT  ((resource_size_t)0xfffff)
+#define __io(a)         __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
 #else
 #define __io(a)         __typesafe_io((a) & IO_SPACE_LIMIT)
 #endif
diff --git a/arch/arm/include/asm/ipcbuf.h b/arch/arm/include/asm/ipcbuf.h
deleted file mode 100644
index 84c7e51cb6d0..000000000000
--- a/arch/arm/include/asm/ipcbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ipcbuf.h>
diff --git a/arch/arm/include/asm/leds.h b/arch/arm/include/asm/leds.h
deleted file mode 100644
index c545739f39b7..000000000000
--- a/arch/arm/include/asm/leds.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- *  arch/arm/include/asm/leds.h
- *
- *  Copyright (C) 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Event-driven interface for LEDs on machines
- *  Added led_start and led_stop- Alex Holden, 28th Dec 1998.
- */
-#ifndef ASM_ARM_LEDS_H
-#define ASM_ARM_LEDS_H
-typedef enum {
-        led_idle_start,
-        led_idle_end,
-        led_timer,
-        led_start,
-        led_stop,
-        led_claim,              /* override idle & timer leds */
-        led_release,            /* restore idle & timer leds */
-        led_start_timer_mode,
-        led_stop_timer_mode,
-        led_green_on,
-        led_green_off,
-        led_amber_on,
-        led_amber_off,
-        led_red_on,
-        led_red_off,
-        led_blue_on,
-        led_blue_off,
-        /*
-         * I want this between led_timer and led_start, but
-         * someone has decided to export this to user space
-         */
-        led_halted
-} led_event_t;
-/* Use this routine to handle LEDs */
-#ifdef CONFIG_LEDS
-extern void (*leds_event)(led_event_t);
-#else
-#define leds_event(e)
-#endif
-#endif
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 0b1c94b8c652..917d4fcfd9b4 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -14,6 +14,12 @@ struct tag;
 struct meminfo;
 struct sys_timer;
 struct pt_regs;
+struct smp_operations;
+#ifdef CONFIG_SMP
+#define smp_ops(ops) (&(ops))
+#else
+#define smp_ops(ops) (struct smp_operations *)NULL
+#endif
 struct machine_desc {
        unsigned int            nr;             /* architecture number  */
@@ -35,6 +41,7 @@ struct machine_desc {
        unsigned char           reserve_lp1 :1; /* never has lp1        */
        unsigned char           reserve_lp2 :1; /* never has lp2        */
        char                    restart_mode;   /* default restart mode */
+        struct smp_operations   *smp;           /* SMP operations       */
        void                    (*fixup)(struct tag *, char **,
                                         struct meminfo *);
        void                    (*reserve)(void);/* reserve mem blocks  */
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index a6efcdd6fd25..195ac2f9d3d3 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -9,6 +9,9 @@
 *
 *  Page table mapping constructs and function prototypes
 */
+#ifndef __ASM_MACH_MAP_H
+#define __ASM_MACH_MAP_H
 #include <asm/io.h>
 struct map_desc {
@@ -34,6 +37,8 @@ struct map_desc {
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);
+extern void vm_reserve_area_early(unsigned long addr, unsigned long size,
+                                  void *caller);
 struct mem_type;
 extern const struct mem_type *get_mem_type(unsigned int type);
@@ -44,4 +49,7 @@ extern int ioremap_page(unsigned long virt, unsigned long phys,
                        const struct mem_type *mtype);
 #else
 #define iotable_init(map,num)   do { } while (0)
+#define vm_reserve_area_early(a,s,c)    do { } while (0)
+#endif
 #endif
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 26c511fddf8f..db9fedb57f2c 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_MACH_PCI_H
 #define __ASM_MACH_PCI_H
+#include <linux/ioport.h>
 struct pci_sys_data;
 struct pci_ops;
 struct pci_bus;
@@ -42,6 +44,8 @@ struct pci_sys_data {
        unsigned long   io_offset;      /* bus->cpu IO mapping offset           */
        struct pci_bus  *bus;           /* PCI bus                              */
        struct list_head resources;     /* root bus resources (apertures)       */
+        struct resource io_res;
+        char            io_res_name[12];
                                        /* Bridge swizzling                     */
        u8              (*swizzle)(struct pci_dev *, u8 *);
                                        /* IRQ mapping                          */
@@ -55,6 +59,15 @@ struct pci_sys_data {
 void pci_common_init(struct hw_pci *);
 /*
+ * Setup early fixed I/O mapping.
+ */
+#if defined(CONFIG_PCI)
+extern void pci_map_io_early(unsigned long pfn);
+#else
+static inline void pci_map_io_early(unsigned long pfn) {}
+#endif
+/*
 * PCI controllers
 */
 extern struct pci_ops iop3xx_ops;
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 5f6ddcc56452..73cf03aa981e 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -275,14 +275,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 #define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 #define virt_addr_valid(kaddr)  ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
-/*
- * Optional coherency support.  Currently used only by selected
- * Intel XSC3-based systems.
- */
-#ifndef arch_is_coherent
-#define arch_is_coherent()              0
-#endif
 #endif
 #include <asm-generic/memory_model.h>
diff --git a/arch/arm/include/asm/msgbuf.h b/arch/arm/include/asm/msgbuf.h
deleted file mode 100644
index 33b35b946eaa..000000000000
--- a/arch/arm/include/asm/msgbuf.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _ASMARM_MSGBUF_H
-#define _ASMARM_MSGBUF_H
-/* 
- * The msqid64_ds structure for arm architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-struct msqid64_ds {
-        struct ipc64_perm msg_perm;
-        __kernel_time_t msg_stime;      /* last msgsnd time */
-        unsigned long   __unused1;
-        __kernel_time_t msg_rtime;      /* last msgrcv time */
-        unsigned long   __unused2;
-        __kernel_time_t msg_ctime;      /* last change time */
-        unsigned long   __unused3;
-        unsigned long  msg_cbytes;      /* current number of bytes on queue */
-        unsigned long  msg_qnum;        /* number of messages in queue */
-        unsigned long  msg_qbytes;      /* max number of bytes on queue */
-        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
-        __kernel_pid_t msg_lrpid;       /* last receive pid */
-        unsigned long  __unused4;
-        unsigned long  __unused5;
-};
-#endif /* _ASMARM_MSGBUF_H */
diff --git a/arch/arm/include/asm/mutex.h b/arch/arm/include/asm/mutex.h
index b1479fd04a95..87c044910fe0 100644
--- a/arch/arm/include/asm/mutex.h
+++ b/arch/arm/include/asm/mutex.h
@@ -9,8 +9,13 @@
 #define _ASM_MUTEX_H
 /*
 * On pre-ARMv6 hardware this results in a swp-based implementation,
- * which is the most efficient. For ARMv6+, we emit a pair of exclusive
+ * which is the most efficient. For ARMv6+, we have exclusive memory
- * accesses instead.
+ * accessors and use atomic_dec to avoid the extra xchg operations
+ * on the locking slowpaths.
 */
+#if __LINUX_ARM_ARCH__ < 6
 #include <asm-generic/mutex-xchg.h>
+#else
+#include <asm-generic/mutex-dec.h>
 #endif
+#endif  /* _ASM_MUTEX_H */
diff --git a/arch/arm/mach-mxs/include/mach/entry-macro.S b/arch/arm/include/asm/opcodes-virt.h
index 0c14259705b9..efcfdf92d9d5 100644
--- a/arch/arm/mach-mxs/include/mach/entry-macro.S
+++ b/arch/arm/include/asm/opcodes-virt.h
@@ -1,7 +1,6 @@
 /*
- * Low-level IRQ helper macros for Freescale MXS-based
+ * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions
- *
+ * Copyright (C) 2012  Linaro Limited
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -17,19 +16,24 @@
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */
+#ifndef __ASM_ARM_OPCODES_VIRT_H
+#define __ASM_ARM_OPCODES_VIRT_H
+#include <asm/opcodes.h>
-#include <mach/mxs.h>
+#define __HVC(imm16) __inst_arm_thumb32(                                \
+        0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F),    \
+        0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF)     \
+)
-#define MXS_ICOLL_VBASE         MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR)
+#define __ERET  __inst_arm_thumb32(                                     \
-#define HW_ICOLL_STAT_OFFSET    0x70
+        0xE160006E,                                                     \
+        0xF3DE8F00                                                      \
+)
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+#define __MSR_ELR_HYP(regnum)   __inst_arm_thumb32(                     \
-        ldr     \irqnr, [\base, #HW_ICOLL_STAT_OFFSET]
+        0xE12EF300 | regnum,                                            \
-        cmp     \irqnr, #0x7F
+        0xF3808E30 | (regnum << 16)                                     \
-        strne   \irqnr, [\base]
+)
-        moveqs  \irqnr, #0
-        .endm
-        .macro  get_irqnr_preamble, base, tmp
+#endif /* ! __ASM_ARM_OPCODES_VIRT_H */
-        ldr     \base, =MXS_ICOLL_VBASE
-        .endm
diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index 19c48deda70f..74e211a6fb24 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -19,6 +19,33 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 /*
+ * Assembler opcode byteswap helpers.
+ * These are only intended for use by this header: don't use them directly,
+ * because they will be suboptimal in most cases.
+ */
+#define ___asm_opcode_swab32(x) (       \
+          (((x) << 24) & 0xFF000000)    \
+        | (((x) <<  8) & 0x00FF0000)    \
+        | (((x) >>  8) & 0x0000FF00)    \
+        | (((x) >> 24) & 0x000000FF)    \
+)
+#define ___asm_opcode_swab16(x) (       \
+          (((x) << 8) & 0xFF00)         \
+        | (((x) >> 8) & 0x00FF)         \
+)
+#define ___asm_opcode_swahb32(x) (      \
+          (((x) << 8) & 0xFF00FF00)     \
+        | (((x) >> 8) & 0x00FF00FF)     \
+)
+#define ___asm_opcode_swahw32(x) (      \
+          (((x) << 16) & 0xFFFF0000)    \
+        | (((x) >> 16) & 0x0000FFFF)    \
+)
+#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
+#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
+/*
 * Opcode byteswap helpers
 *
 * These macros help with converting instructions between a canonical integer
@@ -41,39 +68,163 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
 * represent any valid Thumb-2 instruction.  For this range,
 * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
+ *
+ * The ___asm variants are intended only for use by this header, in situations
+ * involving inline assembler.  For .S files, the normal __opcode_*() macros
+ * should do the right thing.
 */
+#ifdef __ASSEMBLY__
-#ifndef __ASSEMBLY__
+#define ___opcode_swab32(x) ___asm_opcode_swab32(x)
+#define ___opcode_swab16(x) ___asm_opcode_swab16(x)
+#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x)
+#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x)
+#define ___opcode_identity32(x) ___asm_opcode_identity32(x)
+#define ___opcode_identity16(x) ___asm_opcode_identity16(x)
+#else /* ! __ASSEMBLY__ */
 #include <linux/types.h>
 #include <linux/swab.h>
+#define ___opcode_swab32(x) swab32(x)
+#define ___opcode_swab16(x) swab16(x)
+#define ___opcode_swahb32(x) swahb32(x)
+#define ___opcode_swahw32(x) swahw32(x)
+#define ___opcode_identity32(x) ((u32)(x))
+#define ___opcode_identity16(x) ((u16)(x))
+#endif /* ! __ASSEMBLY__ */
 #ifdef CONFIG_CPU_ENDIAN_BE8
-#define __opcode_to_mem_arm(x) swab32(x)
-#define __opcode_to_mem_thumb16(x) swab16(x)
+#define __opcode_to_mem_arm(x) ___opcode_swab32(x)
-#define __opcode_to_mem_thumb32(x) swahb32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
-#else
+#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
-#define __opcode_to_mem_arm(x) ((u32)(x))
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
-#define __opcode_to_mem_thumb16(x) ((u16)(x))
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
-#define __opcode_to_mem_thumb32(x) swahw32(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
+#else /* ! CONFIG_CPU_ENDIAN_BE8 */
+#define __opcode_to_mem_arm(x) ___opcode_identity32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
+/*
+ * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
+ * work in all cases, due to alignment constraints.  For now, a correct
+ * version is not provided for BE32.
+ */
+#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x)
 #endif
+#endif /* ! CONFIG_CPU_ENDIAN_BE8 */
 #define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x)
 #define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
 #define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x)
+#endif
 /* Operations specific to Thumb opcodes */
 /* Instruction size checks: */
-#define __opcode_is_thumb32(x) ((u32)(x) >= 0xE8000000UL)
+#define __opcode_is_thumb32(x) (                \
-#define __opcode_is_thumb16(x) ((u32)(x) < 0xE800UL)
+           ((x) & 0xF8000000) == 0xE8000000     \
+        || ((x) & 0xF0000000) == 0xF0000000     \
+)
+#define __opcode_is_thumb16(x) (                                        \
+           ((x) & 0xFFFF0000) == 0                                      \
+        && !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000)      \
+)
 /* Operations to construct or split 32-bit Thumb instructions: */
-#define __opcode_thumb32_first(x) ((u16)((x) >> 16))
+#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16))
-#define __opcode_thumb32_second(x) ((u16)(x))
+#define __opcode_thumb32_second(x) (___opcode_identity16(x))
-#define __opcode_thumb32_compose(first, second) \
+#define __opcode_thumb32_compose(first, second) (                       \
-        (((u32)(u16)(first) << 16) | (u32)(u16)(second))
+          (___opcode_identity32(___opcode_identity16(first)) << 16)     \
+        | ___opcode_identity32(___opcode_identity16(second))            \
+)
+#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16))
+#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x))
+#define ___asm_opcode_thumb32_compose(first, second) (                      \
+          (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
+        | ___asm_opcode_identity32(___asm_opcode_identity16(second))        \
+)
-#endif /* __ASSEMBLY__ */
+/*
+ * Opcode injection helpers
+ *
+ * In rare cases it is necessary to assemble an opcode which the
+ * assembler does not support directly, or which would normally be
+ * rejected because of the CFLAGS or AFLAGS used to build the affected
+ * file.
+ *
+ * Before using these macros, consider carefully whether it is feasible
+ * instead to change the build flags for your file, or whether it really
+ * makes sense to support old assembler versions when building that
+ * particular kernel feature.
+ *
+ * The macros defined here should only be used where there is no viable
+ * alternative.
+ *
+ *
+ * __inst_arm(x): emit the specified ARM opcode
+ * __inst_thumb16(x): emit the specified 16-bit Thumb opcode
+ * __inst_thumb32(x): emit the specified 32-bit Thumb opcode
+ *
+ * __inst_arm_thumb16(arm, thumb): emit either the specified arm or
+ *      16-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *      kernel is being built
+ *
+ * __inst_arm_thumb32(arm, thumb): emit either the specified arm or
+ *      32-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *      kernel is being built
+ *
+ *
+ * Note that using these macros directly is poor practice.  Instead, you
+ * should use them to define human-readable wrapper macros to encode the
+ * instructions that you care about.  In code which might run on ARMv7 or
+ * above, you can usually use the __inst_arm_thumb{16,32} macros to
+ * specify the ARM and Thumb alternatives at the same time.  This ensures
+ * that the correct opcode gets emitted depending on the instruction set
+ * used for the kernel build.
+ *
+ * Look at opcodes-virt.h for an example of how to use these macros.
+ */
+#include <linux/stringify.h>
+#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x))
+#define __inst_thumb32(x) ___inst_thumb32(                              \
+        ___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)),   \
+        ___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x))   \
+)
+#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x))
+#ifdef CONFIG_THUMB2_KERNEL
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \
+        __inst_thumb16(thumb_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \
+        __inst_thumb32(thumb_opcode)
+#else
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#endif
+/* Helpers for the helpers.  Don't use these directly. */
+#ifdef __ASSEMBLY__
+#define ___inst_arm(x) .long x
+#define ___inst_thumb16(x) .short x
+#define ___inst_thumb32(first, second) .short first, second
+#else
+#define ___inst_arm(x) ".long " __stringify(x) "\n\t"
+#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t"
+#define ___inst_thumb32(first, second) \
+        ".short " __stringify(first) ", " __stringify(second) "\n\t"
+#endif
 #endif /* __ASM_ARM_OPCODES_H */
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index ecf901902e44..812a4944e783 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -19,7 +19,7 @@
 #ifndef CONFIG_MMU
-#include "page-nommu.h"
+#include <asm/page-nommu.h>
 #else
diff --git a/arch/arm/include/asm/param.h b/arch/arm/include/asm/param.h
deleted file mode 100644
index 8b24bf94c06b..000000000000
--- a/arch/arm/include/asm/param.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *  arch/arm/include/asm/param.h
- *
- *  Copyright (C) 1995-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_PARAM_H
-#define __ASM_PARAM_H
-#ifdef __KERNEL__
-# define HZ             CONFIG_HZ       /* Internal kernel timer frequency */
-# define USER_HZ        100             /* User interfaces are in "ticks" */
-# define CLOCKS_PER_SEC (USER_HZ)       /* like times() */
-#else
-# define HZ             100
-#endif
-#define EXEC_PAGESIZE   4096
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-/* max length of hostname */
-#define MAXHOSTNAMELEN  64
-#endif
diff --git a/arch/arm/include/asm/parport.h b/arch/arm/include/asm/parport.h
deleted file mode 100644
index 26e94b09035a..000000000000
--- a/arch/arm/include/asm/parport.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  arch/arm/include/asm/parport.h: ARM-specific parport initialisation
- *
- *  Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
- *
- * This file should only be included by drivers/parport/parport_pc.c.
- */
-#ifndef __ASMARM_PARPORT_H
-#define __ASMARM_PARPORT_H
-static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
-static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
-{
-        return parport_pc_find_isa_ports (autoirq, autodma);
-}
-#endif /* !(_ASMARM_PARPORT_H) */
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index e074948d8143..625cd621a436 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -12,6 +12,13 @@
 #ifndef __ARM_PERF_EVENT_H__
 #define __ARM_PERF_EVENT_H__
-/* Nothing to see here... */
+/*
+ * The ARMv7 CPU PMU supports up to 32 event counters.
+ */
+#define ARMPMU_MAX_HWEVENTS             32
+#define HW_OP_UNSUPPORTED               0xFFFF
+#define C(_x)                           PERF_COUNT_HW_CACHE_##_x
+#define CACHE_OP_UNSUPPORTED            0xFFFF
 #endif /* __ARM_PERF_EVENT_H__ */
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 41dc31f834c3..08c12312a1f9 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -16,7 +16,7 @@
 #ifndef CONFIG_MMU
 #include <asm-generic/4level-fixup.h>
-#include "pgtable-nommu.h"
+#include <asm/pgtable-nommu.h>
 #else
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 4432305f4a2a..a26170dce02e 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -16,69 +16,30 @@
 #include <linux/perf_event.h>
 /*
- * Types of PMUs that can be accessed directly and require mutual
- * exclusion between profiling tools.
- */
-enum arm_pmu_type {
-        ARM_PMU_DEVICE_CPU      = 0,
-        ARM_NUM_PMU_DEVICES,
-};
-/*
 * struct arm_pmu_platdata - ARM PMU platform data
 *
 * @handle_irq: an optional handler which will be called from the
 *      interrupt and passed the address of the low level handler,
 *      and can be used to implement any platform specific handling
 *      before or after calling it.
- * @enable_irq: an optional handler which will be called after
+ * @runtime_resume: an optional handler which will be called by the
- *      request_irq and be used to handle some platform specific
+ *      runtime PM framework following a call to pm_runtime_get().
- *      irq enablement
+ *      Note that if pm_runtime_get() is called more than once in
- * @disable_irq: an optional handler which will be called before
+ *      succession this handler will only be called once.
- *      free_irq and be used to handle some platform specific
+ * @runtime_suspend: an optional handler which will be called by the
- *      irq disablement
+ *      runtime PM framework following a call to pm_runtime_put().
+ *      Note that if pm_runtime_get() is called more than once in
+ *      succession this handler will only be called following the
+ *      final call to pm_runtime_put() that actually disables the
+ *      hardware.
 */
 struct arm_pmu_platdata {
        irqreturn_t (*handle_irq)(int irq, void *dev,
                                  irq_handler_t pmu_handler);
-        void (*enable_irq)(int irq);
+        int (*runtime_resume)(struct device *dev);
-        void (*disable_irq)(int irq);
+        int (*runtime_suspend)(struct device *dev);
 };
-#ifdef CONFIG_CPU_HAS_PMU
-/**
- * reserve_pmu() - reserve the hardware performance counters
- *
- * Reserve the hardware performance counters in the system for exclusive use.
- * Returns 0 on success or -EBUSY if the lock is already held.
- */
-extern int
-reserve_pmu(enum arm_pmu_type type);
-/**
- * release_pmu() - Relinquish control of the performance counters
- *
- * Release the performance counters and allow someone else to use them.
- */
-extern void
-release_pmu(enum arm_pmu_type type);
-#else /* CONFIG_CPU_HAS_PMU */
-#include <linux/err.h>
-static inline int
-reserve_pmu(enum arm_pmu_type type)
-{
-        return -ENODEV;
-}
-static inline void
-release_pmu(enum arm_pmu_type type)     { }
-#endif /* CONFIG_CPU_HAS_PMU */
 #ifdef CONFIG_HW_PERF_EVENTS
 /* The events for a given PMU register set. */
@@ -103,7 +64,6 @@ struct pmu_hw_events {
 struct arm_pmu {
        struct pmu      pmu;
-        enum arm_pmu_type type;
        cpumask_t       active_irqs;
        char            *name;
        irqreturn_t     (*handle_irq)(int irq_num, void *dev);
@@ -118,6 +78,8 @@ struct arm_pmu {
        void            (*start)(void);
        void            (*stop)(void);
        void            (*reset)(void *);
+        int             (*request_irq)(irq_handler_t handler);
+        void            (*free_irq)(void);
        int             (*map_event)(struct perf_event *event);
        int             num_events;
        atomic_t        active_events;
@@ -129,7 +91,9 @@ struct arm_pmu {
 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
-int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
+extern const struct dev_pm_ops armpmu_dev_pm_ops;
+int armpmu_register(struct arm_pmu *armpmu, char *name, int type);
 u64 armpmu_event_update(struct perf_event *event,
                        struct hw_perf_event *hwc,
@@ -139,6 +103,13 @@ int armpmu_event_set_period(struct perf_event *event,
                            struct hw_perf_event *hwc,
                            int idx);
+int armpmu_map_event(struct perf_event *event,
+                     const unsigned (*event_map)[PERF_COUNT_HW_MAX],
+                     const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
+                                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                                [PERF_COUNT_HW_CACHE_RESULT_MAX],
+                     u32 raw_event_mask);
 #endif /* CONFIG_HW_PERF_EVENTS */
 #endif /* __ARM_PMU_H__ */
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 99afa7498260..06e7d509eaac 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -85,11 +85,6 @@ unsigned long get_wchan(struct task_struct *p);
 #define cpu_relax()                     barrier()
 #endif
-/*
- * Create a new kernel thread
- */
-extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 #define task_pt_regs(p) \
        ((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 355ece523f41..142d6ae41231 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -44,6 +44,7 @@
 #define IRQ_MODE        0x00000012
 #define SVC_MODE        0x00000013
 #define ABT_MODE        0x00000017
+#define HYP_MODE        0x0000001a
 #define UND_MODE        0x0000001b
 #define SYSTEM_MODE     0x0000001f
 #define MODE32_BIT      0x00000010
@@ -254,6 +255,11 @@ static inline unsigned long user_stack_pointer(struct pt_regs *regs)
        return regs->ARM_sp;
 }
+#define current_pt_regs(void) ({                                \
+        register unsigned long sp asm ("sp");                   \
+        (struct pt_regs *)((sp | (THREAD_SIZE - 1)) - 7) - 1;   \
+})
 #endif /* __KERNEL__ */
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/segment.h b/arch/arm/include/asm/segment.h
deleted file mode 100644
index 9e24c21f6304..000000000000
--- a/arch/arm/include/asm/segment.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __ASM_ARM_SEGMENT_H
-#define __ASM_ARM_SEGMENT_H
-#define __KERNEL_CS   0x0
-#define __KERNEL_DS   0x0
-#define __USER_CS     0x1
-#define __USER_DS     0x1
-#endif /* __ASM_ARM_SEGMENT_H */
diff --git a/arch/arm/include/asm/sembuf.h b/arch/arm/include/asm/sembuf.h
deleted file mode 100644
index 1c0283954289..000000000000
--- a/arch/arm/include/asm/sembuf.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _ASMARM_SEMBUF_H
-#define _ASMARM_SEMBUF_H
-/* 
- * The semid64_ds structure for arm architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-struct semid64_ds {
-        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
-        __kernel_time_t sem_otime;              /* last semop time */
-        unsigned long   __unused1;
-        __kernel_time_t sem_ctime;              /* last change time */
-        unsigned long   __unused2;
-        unsigned long   sem_nsems;              /* no. of semaphores in array */
-        unsigned long   __unused3;
-        unsigned long   __unused4;
-};
-#endif /* _ASMARM_SEMBUF_H */
diff --git a/arch/arm/include/asm/serial.h b/arch/arm/include/asm/serial.h
deleted file mode 100644
index ebb049091e26..000000000000
--- a/arch/arm/include/asm/serial.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *  arch/arm/include/asm/serial.h
- *
- *  Copyright (C) 1996 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Changelog:
- *   15-10-1996 RMK     Created
- */
-#ifndef __ASM_SERIAL_H
-#define __ASM_SERIAL_H
-#define BASE_BAUD       (1843200 / 16)
-#endif
diff --git a/arch/arm/include/asm/shmbuf.h b/arch/arm/include/asm/shmbuf.h
deleted file mode 100644
index 2e5c67ba1c97..000000000000
--- a/arch/arm/include/asm/shmbuf.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef _ASMARM_SHMBUF_H
-#define _ASMARM_SHMBUF_H
-/* 
- * The shmid64_ds structure for arm architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-struct shmid64_ds {
-        struct ipc64_perm       shm_perm;       /* operation perms */
-        size_t                  shm_segsz;      /* size of segment (bytes) */
-        __kernel_time_t         shm_atime;      /* last attach time */
-        unsigned long           __unused1;
-        __kernel_time_t         shm_dtime;      /* last detach time */
-        unsigned long           __unused2;
-        __kernel_time_t         shm_ctime;      /* last change time */
-        unsigned long           __unused3;
-        __kernel_pid_t          shm_cpid;       /* pid of creator */
-        __kernel_pid_t          shm_lpid;       /* pid of last operator */
-        unsigned long           shm_nattch;     /* no. of current attaches */
-        unsigned long           __unused4;
-        unsigned long           __unused5;
-};
-struct shminfo64 {
-        unsigned long   shmmax;
-        unsigned long   shmmin;
-        unsigned long   shmmni;
-        unsigned long   shmseg;
-        unsigned long   shmall;
-        unsigned long   __unused1;
-        unsigned long   __unused2;
-        unsigned long   __unused3;
-        unsigned long   __unused4;
-};
-#endif /* _ASMARM_SHMBUF_H */
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index ae29293270a3..2e3be16c6766 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -60,15 +60,6 @@ extern int boot_secondary(unsigned int cpu, struct task_struct *);
 */
 asmlinkage void secondary_start_kernel(void);
-/*
- * Perform platform specific initialisation of the specified CPU.
- */
-extern void platform_secondary_init(unsigned int cpu);
-/*
- * Initialize cpu_possible map, and enable coherency
- */
-extern void platform_smp_prepare_cpus(unsigned int);
 /*
 * Initial data for bringing up a secondary CPU.
@@ -79,18 +70,47 @@ struct secondary_data {
        void *stack;
 };
 extern struct secondary_data secondary_data;
+extern volatile int pen_release;
 extern int __cpu_disable(void);
-extern int platform_cpu_disable(unsigned int cpu);
 extern void __cpu_die(unsigned int cpu);
 extern void cpu_die(void);
-extern void platform_cpu_die(unsigned int cpu);
-extern int platform_cpu_kill(unsigned int cpu);
-extern void platform_cpu_enable(unsigned int cpu);
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
+struct smp_operations {
+#ifdef CONFIG_SMP
+        /*
+         * Setup the set of possible CPUs (via set_cpu_possible)
+         */
+        void (*smp_init_cpus)(void);
+        /*
+         * Initialize cpu_possible map, and enable coherency
+         */
+        void (*smp_prepare_cpus)(unsigned int max_cpus);
+        /*
+         * Perform platform specific initialisation of the specified CPU.
+         */
+        void (*smp_secondary_init)(unsigned int cpu);
+        /*
+         * Boot a secondary CPU, and assign it the specified idle task.
+         * This also gives us the initial stack to use for this CPU.
+         */
+        int  (*smp_boot_secondary)(unsigned int cpu, struct task_struct *idle);
+#ifdef CONFIG_HOTPLUG_CPU
+        int  (*cpu_kill)(unsigned int cpu);
+        void (*cpu_die)(unsigned int cpu);
+        int  (*cpu_disable)(unsigned int cpu);
+#endif
+#endif
+};
+/*
+ * set platform specific SMP operations
+ */
+extern void smp_set_ops(struct smp_operations *);
 #endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/arch/arm/include/asm/socket.h b/arch/arm/include/asm/socket.h
deleted file mode 100644
index 6433cadb6ed4..000000000000
--- a/arch/arm/include/asm/socket.h
+++ /dev/null
@@ -1,72 +0,0 @@
-#ifndef _ASMARM_SOCKET_H
-#define _ASMARM_SOCKET_H
-#include <asm/sockios.h>
-/* For setsockopt(2) */
-#define SOL_SOCKET      1
-#define SO_DEBUG        1
-#define SO_REUSEADDR    2
-#define SO_TYPE         3
-#define SO_ERROR        4
-#define SO_DONTROUTE    5
-#define SO_BROADCAST    6
-#define SO_SNDBUF       7
-#define SO_RCVBUF       8
-#define SO_SNDBUFFORCE  32
-#define SO_RCVBUFFORCE  33
-#define SO_KEEPALIVE    9
-#define SO_OOBINLINE    10
-#define SO_NO_CHECK     11
-#define SO_PRIORITY     12
-#define SO_LINGER       13
-#define SO_BSDCOMPAT    14
-/* To add :#define SO_REUSEPORT 15 */
-#define SO_PASSCRED     16
-#define SO_PEERCRED     17
-#define SO_RCVLOWAT     18
-#define SO_SNDLOWAT     19
-#define SO_RCVTIMEO     20
-#define SO_SNDTIMEO     21
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION              22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
-#define SO_SECURITY_ENCRYPTION_NETWORK          24
-#define SO_BINDTODEVICE 25
-/* Socket filtering */
-#define SO_ATTACH_FILTER        26
-#define SO_DETACH_FILTER        27
-#define SO_PEERNAME             28
-#define SO_TIMESTAMP            29
-#define SCM_TIMESTAMP           SO_TIMESTAMP
-#define SO_ACCEPTCONN           30
-#define SO_PEERSEC              31
-#define SO_PASSSEC              34
-#define SO_TIMESTAMPNS          35
-#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
-#define SO_MARK                 36
-#define SO_TIMESTAMPING         37
-#define SCM_TIMESTAMPING        SO_TIMESTAMPING
-#define SO_PROTOCOL             38
-#define SO_DOMAIN               39
-#define SO_RXQ_OVFL             40
-#define SO_WIFI_STATUS          41
-#define SCM_WIFI_STATUS         SO_WIFI_STATUS
-#define SO_PEEK_OFF             42
-/* Instruct lower device to use last 4-bytes of skb data as FCS */
-#define SO_NOFCS                43
-#endif /* _ASM_SOCKET_H */
diff --git a/arch/arm/include/asm/sockios.h b/arch/arm/include/asm/sockios.h
deleted file mode 100644
index a2588a2512df..000000000000
--- a/arch/arm/include/asm/sockios.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ARCH_ARM_SOCKIOS_H
-#define __ARCH_ARM_SOCKIOS_H
-/* Socket-level I/O control calls. */
-#define FIOSETOWN       0x8901
-#define SIOCSPGRP       0x8902
-#define FIOGETOWN       0x8903
-#define SIOCGPGRP       0x8904
-#define SIOCATMARK      0x8905
-#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
-#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
-#endif
diff --git a/arch/arm/include/asm/sync_bitops.h b/arch/arm/include/asm/sync_bitops.h
new file mode 100644
index 000000000000..63479eecbf76
--- /dev/null
+++ b/arch/arm/include/asm/sync_bitops.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_SYNC_BITOPS_H__
+#define __ASM_SYNC_BITOPS_H__
+#include <asm/bitops.h>
+#include <asm/system.h>
+/* sync_bitops functions are equivalent to the SMP implementation of the
+ * original functions, independently from CONFIG_SMP being defined.
+ *
+ * We need them because _set_bit etc are not SMP safe if !CONFIG_SMP. But
+ * under Xen you might be communicating with a completely external entity
+ * who might be on another CPU (e.g. two uniprocessor guests communicating
+ * via event channels and grant tables). So we need a variant of the bit
+ * ops which are SMP safe even on a UP kernel.
+ */
+#define sync_set_bit(nr, p)             _set_bit(nr, p)
+#define sync_clear_bit(nr, p)           _clear_bit(nr, p)
+#define sync_change_bit(nr, p)          _change_bit(nr, p)
+#define sync_test_and_set_bit(nr, p)    _test_and_set_bit(nr, p)
+#define sync_test_and_clear_bit(nr, p)  _test_and_clear_bit(nr, p)
+#define sync_test_and_change_bit(nr, p) _test_and_change_bit(nr, p)
+#define sync_test_bit(nr, addr)         test_bit(nr, addr)
+#define sync_cmpxchg                    cmpxchg
+#endif
diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
index c334a23ddf75..9fdded6b1089 100644
--- a/arch/arm/include/asm/syscall.h
+++ b/arch/arm/include/asm/syscall.h
@@ -8,6 +8,11 @@
 #define _ASM_ARM_SYSCALL_H
 #include <linux/err.h>
+#include <linux/sched.h>
+#include <asm/unistd.h>
+#define NR_syscalls (__NR_syscalls)
 extern const unsigned long sys_call_table[];
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 74542c52f9be..368165e33c1c 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -2,7 +2,6 @@
 #include <asm/barrier.h>
 #include <asm/compiler.h>
 #include <asm/cmpxchg.h>
-#include <asm/exec.h>
 #include <asm/switch_to.h>
 #include <asm/system_info.h>
 #include <asm/system_misc.h>
diff --git a/arch/arm/include/asm/termbits.h b/arch/arm/include/asm/termbits.h
deleted file mode 100644
index 704135d28d1d..000000000000
--- a/arch/arm/include/asm/termbits.h
+++ /dev/null
@@ -1,198 +0,0 @@
-#ifndef __ASM_ARM_TERMBITS_H
-#define __ASM_ARM_TERMBITS_H
-typedef unsigned char   cc_t;
-typedef unsigned int    speed_t;
-typedef unsigned int    tcflag_t;
-#define NCCS 19
-struct termios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-};
-struct termios2 {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-struct ktermios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-/* c_iflag bits */
-#define IGNBRK  0000001
-#define BRKINT  0000002
-#define IGNPAR  0000004
-#define PARMRK  0000010
-#define INPCK   0000020
-#define ISTRIP  0000040
-#define INLCR   0000100
-#define IGNCR   0000200
-#define ICRNL   0000400
-#define IUCLC   0001000
-#define IXON    0002000
-#define IXANY   0004000
-#define IXOFF   0010000
-#define IMAXBEL 0020000
-#define IUTF8   0040000
-/* c_oflag bits */
-#define OPOST   0000001
-#define OLCUC   0000002
-#define ONLCR   0000004
-#define OCRNL   0000010
-#define ONOCR   0000020
-#define ONLRET  0000040
-#define OFILL   0000100
-#define OFDEL   0000200
-#define NLDLY   0000400
-#define   NL0   0000000
-#define   NL1   0000400
-#define CRDLY   0003000
-#define   CR0   0000000
-#define   CR1   0001000
-#define   CR2   0002000
-#define   CR3   0003000
-#define TABDLY  0014000
-#define   TAB0  0000000
-#define   TAB1  0004000
-#define   TAB2  0010000
-#define   TAB3  0014000
-#define   XTABS 0014000
-#define BSDLY   0020000
-#define   BS0   0000000
-#define   BS1   0020000
-#define VTDLY   0040000
-#define   VT0   0000000
-#define   VT1   0040000
-#define FFDLY   0100000
-#define   FF0   0000000
-#define   FF1   0100000
-/* c_cflag bit meaning */
-#define CBAUD   0010017
-#define  B0     0000000         /* hang up */
-#define  B50    0000001
-#define  B75    0000002
-#define  B110   0000003
-#define  B134   0000004
-#define  B150   0000005
-#define  B200   0000006
-#define  B300   0000007
-#define  B600   0000010
-#define  B1200  0000011
-#define  B1800  0000012
-#define  B2400  0000013
-#define  B4800  0000014
-#define  B9600  0000015
-#define  B19200 0000016
-#define  B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE   0000060
-#define   CS5   0000000
-#define   CS6   0000020
-#define   CS7   0000040
-#define   CS8   0000060
-#define CSTOPB  0000100
-#define CREAD   0000200
-#define PARENB  0000400
-#define PARODD  0001000
-#define HUPCL   0002000
-#define CLOCAL  0004000
-#define CBAUDEX 0010000
-#define    BOTHER 0010000
-#define    B57600 0010001
-#define   B115200 0010002
-#define   B230400 0010003
-#define   B460800 0010004
-#define   B500000 0010005
-#define   B576000 0010006
-#define   B921600 0010007
-#define  B1000000 0010010
-#define  B1152000 0010011
-#define  B1500000 0010012
-#define  B2000000 0010013
-#define  B2500000 0010014
-#define  B3000000 0010015
-#define  B3500000 0010016
-#define  B4000000 0010017
-#define CIBAUD    002003600000          /* input baud rate */
-#define CMSPAR    010000000000          /* mark or space (stick) parity */
-#define CRTSCTS   020000000000          /* flow control */
-#define IBSHIFT    16
-/* c_lflag bits */
-#define ISIG    0000001
-#define ICANON  0000002
-#define XCASE   0000004
-#define ECHO    0000010
-#define ECHOE   0000020
-#define ECHOK   0000040
-#define ECHONL  0000100
-#define NOFLSH  0000200
-#define TOSTOP  0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE  0004000
-#define FLUSHO  0010000
-#define PENDIN  0040000
-#define IEXTEN  0100000
-#define EXTPROC 0200000
-/* tcflow() and TCXONC use these */
-#define TCOOFF          0
-#define TCOON           1
-#define TCIOFF          2
-#define TCION           3
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH        0
-#define TCOFLUSH        1
-#define TCIOFLUSH       2
-/* tcsetattr uses these */
-#define TCSANOW         0
-#define TCSADRAIN       1
-#define TCSAFLUSH       2
-#endif  /* __ASM_ARM_TERMBITS_H */
diff --git a/arch/arm/include/asm/termios.h b/arch/arm/include/asm/termios.h
deleted file mode 100644
index 293e3f1bc3f2..000000000000
--- a/arch/arm/include/asm/termios.h
+++ /dev/null
@@ -1,92 +0,0 @@
-#ifndef __ASM_ARM_TERMIOS_H
-#define __ASM_ARM_TERMIOS_H
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-struct winsize {
-        unsigned short ws_row;
-        unsigned short ws_col;
-        unsigned short ws_xpixel;
-        unsigned short ws_ypixel;
-};
-#define NCC 8
-struct termio {
-        unsigned short c_iflag;         /* input mode flags */
-        unsigned short c_oflag;         /* output mode flags */
-        unsigned short c_cflag;         /* control mode flags */
-        unsigned short c_lflag;         /* local mode flags */
-        unsigned char c_line;           /* line discipline */
-        unsigned char c_cc[NCC];        /* control characters */
-};
-#ifdef __KERNEL__
-/*      intr=^C         quit=^|         erase=del       kill=^U
-        eof=^D          vtime=\0        vmin=\1         sxtc=\0
-        start=^Q        stop=^S         susp=^Z         eol=\0
-        reprint=^R      discard=^U      werase=^W       lnext=^V
-        eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-#endif
-/* modem lines */
-#define TIOCM_LE        0x001
-#define TIOCM_DTR       0x002
-#define TIOCM_RTS       0x004
-#define TIOCM_ST        0x008
-#define TIOCM_SR        0x010
-#define TIOCM_CTS       0x020
-#define TIOCM_CAR       0x040
-#define TIOCM_RNG       0x080
-#define TIOCM_DSR       0x100
-#define TIOCM_CD        TIOCM_CAR
-#define TIOCM_RI        TIOCM_RNG
-#define TIOCM_OUT1      0x2000
-#define TIOCM_OUT2      0x4000
-#define TIOCM_LOOP      0x8000
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-#ifdef __KERNEL__
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) {              \
-        unsigned short __tmp;                                   \
-        get_user(__tmp,&(termio)->x);                           \
-        *(unsigned short *) &(termios)->x = __tmp;              \
-}
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
-        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
-        put_user((termios)->c_iflag, &(termio)->c_iflag); \
-        put_user((termios)->c_oflag, &(termio)->c_oflag); \
-        put_user((termios)->c_cflag, &(termio)->c_cflag); \
-        put_user((termios)->c_lflag, &(termio)->c_lflag); \
-        put_user((termios)->c_line,  &(termio)->c_line); \
-        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
-#endif  /* __KERNEL__ */
-#endif  /* __ASM_ARM_TERMIOS_H */
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index af7b0bda3355..8477b4c1d39f 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -59,7 +59,9 @@ struct thread_info {
        __u32                   syscall;        /* syscall number */
        __u8                    used_cp[16];    /* thread used copro */
        unsigned long           tp_value;
+#ifdef CONFIG_CRUNCH
        struct crunch_state     crunchstate;
+#endif
        union fp_state          fpstate __attribute__((aligned(8)));
        union vfp_state         vfpstate;
 #ifdef CONFIG_ARM_THUMBEE
@@ -148,7 +150,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define TIF_NOTIFY_RESUME       2       /* callback before returning to user */
 #define TIF_SYSCALL_TRACE       8
 #define TIF_SYSCALL_AUDIT       9
-#define TIF_POLLING_NRFLAG      16
+#define TIF_SYSCALL_TRACEPOINT  10
 #define TIF_USING_IWMMXT        17
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
 #define TIF_RESTORE_SIGMASK     20
@@ -160,12 +162,12 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
 #define _TIF_SYSCALL_AUDIT      (1 << TIF_SYSCALL_AUDIT)
-#define _TIF_POLLING_NRFLAG     (1 << TIF_POLLING_NRFLAG)
+#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
 #define _TIF_USING_IWMMXT       (1 << TIF_USING_IWMMXT)
 #define _TIF_SECCOMP            (1 << TIF_SECCOMP)
 /* Checks for any syscall work in entry-common.S */
-#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
+#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
 /*
 * Change these and you break ASM code in entry-common.S
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index ce119442277c..83f2aa83899c 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -12,15 +12,13 @@
 #ifndef _ASMARM_TIMEX_H
 #define _ASMARM_TIMEX_H
-#include <asm/arch_timer.h>
+#ifdef CONFIG_ARCH_MULTIPLATFORM
+#define CLOCK_TICK_RATE 1000000
+#else
 #include <mach/timex.h>
+#endif
 typedef unsigned long cycles_t;
-#ifdef ARCH_HAS_READ_CURRENT_TIMER
 #define get_cycles()    ({ cycles_t c; read_current_timer(&c) ? 0 : c; })
-#else
-#define get_cycles()    (0)
-#endif
 #endif
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
deleted file mode 100644
index 28beab917ffc..000000000000
--- a/arch/arm/include/asm/types.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __ASM_ARM_TYPES_H
-#define __ASM_ARM_TYPES_H
-#include <asm-generic/int-ll64.h>
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-#define BITS_PER_LONG 32
-#endif /* __KERNEL__ */
-#endif
diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h
deleted file mode 100644
index 44593a894903..000000000000
--- a/arch/arm/include/asm/unaligned.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _ASM_ARM_UNALIGNED_H
-#define _ASM_ARM_UNALIGNED_H
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-/*
- * Select endianness
- */
-#ifndef __ARMEB__
-#define get_unaligned   __get_unaligned_le
-#define put_unaligned   __put_unaligned_le
-#else
-#define get_unaligned   __get_unaligned_be
-#define put_unaligned   __put_unaligned_be
-#endif
-#endif /* _ASM_ARM_UNALIGNED_H */
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 2fde5fd1acce..91819ad54424 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -407,6 +407,14 @@
                                        /* 378 for kcmp */
 /*
+ * This may need to be greater than __NR_last_syscall+1 in order to
+ * account for the padding in the syscall table
+ */
+#ifdef __KERNEL__
+#define __NR_syscalls  (380)
+#endif /* __KERNEL__ */
+/*
 * The following SWIs are ARM private.
 */
 #define __ARM_NR_BASE                   (__NR_SYSCALL_BASE+0x0f0000)
@@ -470,6 +478,7 @@
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_SYS_SOCKETCALL
 #endif
+#define __ARCH_WANT_SYS_EXECVE
 /*
 * "Conditional" syscalls
diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
index 3d5fc41ae8d3..6a6f1e485f41 100644
--- a/arch/arm/include/asm/vfpmacros.h
+++ b/arch/arm/include/asm/vfpmacros.h
@@ -5,7 +5,7 @@
 */
 #include <asm/hwcap.h>
-#include "vfp.h"
+#include <asm/vfp.h>
 @ Macros to allow building with old toolkits (with no VFP support)
        .macro  VFPFMRX, rd, sysreg, cond
@@ -28,7 +28,7 @@
        ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
        ldr     \tmp, [\tmp, #0]
        tst     \tmp, #HWCAP_VFPv3D16
-        ldceq   p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
+        ldceql  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
        addne   \base, \base, #32*4                 @ step over unused register space
 #else
        VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
@@ -52,7 +52,7 @@
        ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
        ldr     \tmp, [\tmp, #0]
        tst     \tmp, #HWCAP_VFPv3D16
-        stceq   p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
+        stceql  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
        addne   \base, \base, #32*4                 @ step over unused register space
 #else
        VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h
new file mode 100644
index 000000000000..86164df86cb4
--- /dev/null
+++ b/arch/arm/include/asm/virt.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2012 Linaro Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef VIRT_H
+#define VIRT_H
+#include <asm/ptrace.h>
+/*
+ * Flag indicating that the kernel was not entered in the same mode on every
+ * CPU.  The zImage loader stashes this value in an SPSR, so we need an
+ * architecturally defined flag bit here (the N flag, as it happens)
+ */
+#define BOOT_CPU_MODE_MISMATCH (1<<31)
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_ARM_VIRT_EXT
+/*
+ * __boot_cpu_mode records what mode the primary CPU was booted in.
+ * A correctly-implemented bootloader must start all CPUs in the same mode:
+ * if it fails to do this, the flag BOOT_CPU_MODE_MISMATCH is set to indicate
+ * that some CPU(s) were booted in a different mode.
+ *
+ * This allows the kernel to flag an error when the secondaries have come up.
+ */
+extern int __boot_cpu_mode;
+void __hyp_set_vectors(unsigned long phys_vector_base);
+unsigned long __hyp_get_vectors(void);
+#else
+#define __boot_cpu_mode (SVC_MODE)
+#endif
+#ifndef ZIMAGE
+void hyp_mode_check(void);
+/* Reports the availability of HYP mode */
+static inline bool is_hyp_mode_available(void)
+{
+        return ((__boot_cpu_mode & MODE_MASK) == HYP_MODE &&
+                !(__boot_cpu_mode & BOOT_CPU_MODE_MISMATCH));
+}
+/* Check if the bootloader has booted CPUs in different modes */
+static inline bool is_hyp_mode_mismatched(void)
+{
+        return !!(__boot_cpu_mode & BOOT_CPU_MODE_MISMATCH);
+}
+#endif
+#endif /* __ASSEMBLY__ */
+#endif /* ! VIRT_H */
diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h
new file mode 100644
index 000000000000..94b4e9020b02
--- /dev/null
+++ b/arch/arm/include/asm/xen/events.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_ARM_XEN_EVENTS_H
+#define _ASM_ARM_XEN_EVENTS_H
+#include <asm/ptrace.h>
+enum ipi_vector {
+        XEN_PLACEHOLDER_VECTOR,
+        /* Xen IPIs go here */
+        XEN_NR_IPIS,
+};
+static inline int xen_irqs_disabled(struct pt_regs *regs)
+{
+        return raw_irqs_disabled_flags(regs->ARM_cpsr);
+}
+#endif /* _ASM_ARM_XEN_EVENTS_H */
diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h
new file mode 100644
index 000000000000..8a823253d775
--- /dev/null
+++ b/arch/arm/include/asm/xen/hypercall.h
@@ -0,0 +1,69 @@
+/******************************************************************************
+ * hypercall.h
+ *
+ * Linux-specific hypervisor handling.
+ *
+ * Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#ifndef _ASM_ARM_XEN_HYPERCALL_H
+#define _ASM_ARM_XEN_HYPERCALL_H
+#include <xen/interface/xen.h>
+long privcmd_call(unsigned call, unsigned long a1,
+                unsigned long a2, unsigned long a3,
+                unsigned long a4, unsigned long a5);
+int HYPERVISOR_xen_version(int cmd, void *arg);
+int HYPERVISOR_console_io(int cmd, int count, char *str);
+int HYPERVISOR_grant_table_op(unsigned int cmd, void *uop, unsigned int count);
+int HYPERVISOR_sched_op(int cmd, void *arg);
+int HYPERVISOR_event_channel_op(int cmd, void *arg);
+unsigned long HYPERVISOR_hvm_op(int op, void *arg);
+int HYPERVISOR_memory_op(unsigned int cmd, void *arg);
+int HYPERVISOR_physdev_op(int cmd, void *arg);
+static inline void
+MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va,
+                        unsigned int new_val, unsigned long flags)
+{
+        BUG();
+}
+static inline void
+MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req,
+                 int count, int *success_count, domid_t domid)
+{
+        BUG();
+}
+static inline int
+HYPERVISOR_multicall(void *call_list, int nr_calls)
+{
+        BUG();
+}
+#endif /* _ASM_ARM_XEN_HYPERCALL_H */
diff --git a/arch/arm/include/asm/xen/hypervisor.h b/arch/arm/include/asm/xen/hypervisor.h
new file mode 100644
index 000000000000..d7ab99a0c9eb
--- /dev/null
+++ b/arch/arm/include/asm/xen/hypervisor.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_ARM_XEN_HYPERVISOR_H
+#define _ASM_ARM_XEN_HYPERVISOR_H
+extern struct shared_info *HYPERVISOR_shared_info;
+extern struct start_info *xen_start_info;
+/* Lazy mode for batching updates / context switch */
+enum paravirt_lazy_mode {
+        PARAVIRT_LAZY_NONE,
+        PARAVIRT_LAZY_MMU,
+        PARAVIRT_LAZY_CPU,
+};
+static inline enum paravirt_lazy_mode paravirt_get_lazy_mode(void)
+{
+        return PARAVIRT_LAZY_NONE;
+}
+#endif /* _ASM_ARM_XEN_HYPERVISOR_H */
diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
new file mode 100644
index 000000000000..ae05e56dd17d
--- /dev/null
+++ b/arch/arm/include/asm/xen/interface.h
@@ -0,0 +1,73 @@
+/******************************************************************************
+ * Guest OS interface to ARM Xen.
+ *
+ * Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012
+ */
+#ifndef _ASM_ARM_XEN_INTERFACE_H
+#define _ASM_ARM_XEN_INTERFACE_H
+#include <linux/types.h>
+#define uint64_aligned_t uint64_t __attribute__((aligned(8)))
+#define __DEFINE_GUEST_HANDLE(name, type) \
+        typedef struct { union { type *p; uint64_aligned_t q; }; }  \
+        __guest_handle_ ## name
+#define DEFINE_GUEST_HANDLE_STRUCT(name) \
+        __DEFINE_GUEST_HANDLE(name, struct name)
+#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name)
+#define GUEST_HANDLE(name)        __guest_handle_ ## name
+#define set_xen_guest_handle(hnd, val)                  \
+        do {                                            \
+                if (sizeof(hnd) == 8)                   \
+                        *(uint64_t *)&(hnd) = 0;        \
+                (hnd).p = val;                          \
+        } while (0)
+#ifndef __ASSEMBLY__
+/* Explicitly size integers that represent pfns in the interface with
+ * Xen so that we can have one ABI that works for 32 and 64 bit guests. */
+typedef uint64_t xen_pfn_t;
+typedef uint64_t xen_ulong_t;
+/* Guest handles for primitive C types. */
+__DEFINE_GUEST_HANDLE(uchar, unsigned char);
+__DEFINE_GUEST_HANDLE(uint,  unsigned int);
+__DEFINE_GUEST_HANDLE(ulong, unsigned long);
+DEFINE_GUEST_HANDLE(char);
+DEFINE_GUEST_HANDLE(int);
+DEFINE_GUEST_HANDLE(long);
+DEFINE_GUEST_HANDLE(void);
+DEFINE_GUEST_HANDLE(uint64_t);
+DEFINE_GUEST_HANDLE(uint32_t);
+DEFINE_GUEST_HANDLE(xen_pfn_t);
+/* Maximum number of virtual CPUs in multi-processor guests. */
+#define MAX_VIRT_CPUS 1
+struct arch_vcpu_info { };
+struct arch_shared_info { };
+/* TODO: Move pvclock definitions some place arch independent */
+struct pvclock_vcpu_time_info {
+        u32   version;
+        u32   pad0;
+        u64   tsc_timestamp;
+        u64   system_time;
+        u32   tsc_to_system_mul;
+        s8    tsc_shift;
+        u8    flags;
+        u8    pad[2];
+} __attribute__((__packed__)); /* 32 bytes */
+/* It is OK to have a 12 bytes struct with no padding because it is packed */
+struct pvclock_wall_clock {
+        u32   version;
+        u32   sec;
+        u32   nsec;
+} __attribute__((__packed__));
+#endif
+#endif /* _ASM_ARM_XEN_INTERFACE_H */
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
new file mode 100644
index 000000000000..174202318dff
--- /dev/null
+++ b/arch/arm/include/asm/xen/page.h
@@ -0,0 +1,82 @@
+#ifndef _ASM_ARM_XEN_PAGE_H
+#define _ASM_ARM_XEN_PAGE_H
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <linux/pfn.h>
+#include <linux/types.h>
+#include <xen/interface/grant_table.h>
+#define pfn_to_mfn(pfn)                 (pfn)
+#define phys_to_machine_mapping_valid   (1)
+#define mfn_to_pfn(mfn)                 (mfn)
+#define mfn_to_virt(m)                  (__va(mfn_to_pfn(m) << PAGE_SHIFT))
+#define pte_mfn     pte_pfn
+#define mfn_pte     pfn_pte
+/* Xen machine address */
+typedef struct xmaddr {
+        phys_addr_t maddr;
+} xmaddr_t;
+/* Xen pseudo-physical address */
+typedef struct xpaddr {
+        phys_addr_t paddr;
+} xpaddr_t;
+#define XMADDR(x)       ((xmaddr_t) { .maddr = (x) })
+#define XPADDR(x)       ((xpaddr_t) { .paddr = (x) })
+static inline xmaddr_t phys_to_machine(xpaddr_t phys)
+{
+        unsigned offset = phys.paddr & ~PAGE_MASK;
+        return XMADDR(PFN_PHYS(pfn_to_mfn(PFN_DOWN(phys.paddr))) | offset);
+}
+static inline xpaddr_t machine_to_phys(xmaddr_t machine)
+{
+        unsigned offset = machine.maddr & ~PAGE_MASK;
+        return XPADDR(PFN_PHYS(mfn_to_pfn(PFN_DOWN(machine.maddr))) | offset);
+}
+/* VIRT <-> MACHINE conversion */
+#define virt_to_machine(v)      (phys_to_machine(XPADDR(__pa(v))))
+#define virt_to_pfn(v)          (PFN_DOWN(__pa(v)))
+#define virt_to_mfn(v)          (pfn_to_mfn(virt_to_pfn(v)))
+#define mfn_to_virt(m)          (__va(mfn_to_pfn(m) << PAGE_SHIFT))
+static inline xmaddr_t arbitrary_virt_to_machine(void *vaddr)
+{
+        /* TODO: assuming it is mapped in the kernel 1:1 */
+        return virt_to_machine(vaddr);
+}
+/* TODO: this shouldn't be here but it is because the frontend drivers
+ * are using it (its rolled in headers) even though we won't hit the code path.
+ * So for right now just punt with this.
+ */
+static inline pte_t *lookup_address(unsigned long address, unsigned int *level)
+{
+        BUG();
+        return NULL;
+}
+static inline int m2p_add_override(unsigned long mfn, struct page *page,
+                struct gnttab_map_grant_ref *kmap_op)
+{
+        return 0;
+}
+static inline int m2p_remove_override(struct page *page, bool clear_pte)
+{
+        return 0;
+}
+static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
+{
+        BUG();
+        return false;
+}
+#endif /* _ASM_ARM_XEN_PAGE_H */
diff --git a/arch/arm/mach-highbank/include/mach/debug-macro.S b/arch/arm/include/debug/highbank.S
index cb57fe5bcd04..8cad4322a5a2 100644
--- a/arch/arm/mach-highbank/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/highbank.S
@@ -10,10 +10,8 @@
 */
                .macro  addruart,rp,rv,tmp
-                movw    \rv, #0x6000
+                ldr     \rv, =0xfee36000
-                movt    \rv, #0xfee3
+                ldr     \rp, =0xfff36000
-                movw    \rp, #0x6000
-                movt    \rp, #0xfff3
                .endm
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/include/debug/icedcc.S b/arch/arm/include/debug/icedcc.S
new file mode 100644
index 000000000000..43afcb021fa3
--- /dev/null
+++ b/arch/arm/include/debug/icedcc.S
@@ -0,0 +1,90 @@
+/*
+ *  arch/arm/include/debug/icedcc.S
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+                @@ debug using ARM EmbeddedICE DCC channel
+                .macro  addruart, rp, rv, tmp
+                .endm
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
+                .macro  senduart, rd, rx
+                mcr     p14, 0, \rd, c0, c5, 0
+                .endm
+                .macro  busyuart, rd, rx
+1001:
+                mrc     p14, 0, \rx, c0, c1, 0
+                tst     \rx, #0x20000000
+                beq     1001b
+                .endm
+                .macro  waituart, rd, rx
+                mov     \rd, #0x2000000
+1001:
+                subs    \rd, \rd, #1
+                bmi     1002f
+                mrc     p14, 0, \rx, c0, c1, 0
+                tst     \rx, #0x20000000
+                bne     1001b
+1002:
+                .endm
+#elif defined(CONFIG_CPU_XSCALE)
+                .macro  senduart, rd, rx
+                mcr     p14, 0, \rd, c8, c0, 0
+                .endm
+                .macro  busyuart, rd, rx
+1001:
+                mrc     p14, 0, \rx, c14, c0, 0
+                tst     \rx, #0x10000000
+                beq     1001b
+                .endm
+                .macro  waituart, rd, rx
+                mov     \rd, #0x10000000
+1001:
+                subs    \rd, \rd, #1
+                bmi     1002f
+                mrc     p14, 0, \rx, c14, c0, 0
+                tst     \rx, #0x10000000
+                bne     1001b
+1002:
+                .endm
+#else
+                .macro  senduart, rd, rx
+                mcr     p14, 0, \rd, c1, c0, 0
+                .endm
+                .macro  busyuart, rd, rx
+1001:
+                mrc     p14, 0, \rx, c0, c0, 0
+                tst     \rx, #2
+                beq     1001b
+                .endm
+                .macro  waituart, rd, rx
+                mov     \rd, #0x2000000
+1001:
+                subs    \rd, \rd, #1
+                bmi     1002f
+                mrc     p14, 0, \rx, c0, c0, 0
+                tst     \rx, #2
+                bne     1001b
+1002:
+                .endm
+#endif  /* CONFIG_CPU_V6 */
diff --git a/arch/arm/mach-mvebu/include/mach/debug-macro.S b/arch/arm/include/debug/mvebu.S
index 22825760c7e1..865c6d02b332 100644
--- a/arch/arm/mach-mvebu/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/mvebu.S
@@ -11,7 +11,8 @@
 * published by the Free Software Foundation.
 */
-#include <mach/armada-370-xp.h>
+#define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
+#define ARMADA_370_XP_REGS_VIRT_BASE    0xfeb00000
        .macro  addruart, rp, rv, tmp
        ldr     \rp, =ARMADA_370_XP_REGS_PHYS_BASE
diff --git a/arch/arm/mach-picoxcell/include/mach/debug-macro.S b/arch/arm/include/debug/picoxcell.S
index 58d4ee3ae949..7419deb1b948 100644
--- a/arch/arm/mach-picoxcell/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/picoxcell.S
@@ -9,10 +9,10 @@
 * accesses to the 8250.
 */
 #include <linux/serial_reg.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
 #define UART_SHIFT 2
+#define PICOXCELL_UART1_BASE            0x80230000
+#define PHYS_TO_IO(x)                   (((x) & 0x00ffffff) | 0xfe000000)
                .macro  addruart, rp, rv, tmp
                ldr     \rv, =PHYS_TO_IO(PICOXCELL_UART1_BASE)
diff --git a/arch/arm/mach-socfpga/include/mach/debug-macro.S b/arch/arm/include/debug/socfpga.S
index d6f26d23374f..d6f26d23374f 100644
--- a/arch/arm/mach-socfpga/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/socfpga.S
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/include/debug/vexpress.S
index 9f509f55d078..9f509f55d078 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/vexpress.S
diff --git a/arch/arm/include/uapi/asm/Kbuild b/arch/arm/include/uapi/asm/Kbuild
new file mode 100644
index 000000000000..baebb3da1d44
--- /dev/null
+++ b/arch/arm/include/uapi/asm/Kbuild
@@ -0,0 +1,3 @@
+# UAPI Header export list
+include include/uapi/asm-generic/Kbuild.asm
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7ad2d5cf7008..5bbec7b8183e 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -19,9 +19,10 @@ obj-y		:= elf.o entry-armv.o entry-common.o irq.o opcodes.o \
                   process.o ptrace.o return_address.o sched_clock.o \
                   setup.o signal.o stacktrace.o sys_arm.o time.o traps.o
-obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
+obj-$(CONFIG_ATAGS)             += atags_parse.o
+obj-$(CONFIG_ATAGS_PROC)        += atags_proc.o
+obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o
-obj-$(CONFIG_LEDS)              += leds.o
 obj-$(CONFIG_OC_ETM)            += etm.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_ISA_DMA_API)       += dma.o
@@ -52,7 +53,6 @@ test-kprobes-objs		+= kprobes-test-thumb.o
 else
 test-kprobes-objs               += kprobes-test-arm.o
 endif
-obj-$(CONFIG_ATAGS_PROC)        += atags.o
 obj-$(CONFIG_OABI_COMPAT)       += sys_oabi-compat.o
 obj-$(CONFIG_ARM_THUMBEE)       += thumbee.o
 obj-$(CONFIG_KGDB)              += kgdb.o
@@ -69,8 +69,7 @@ obj-$(CONFIG_CPU_XSC3)		+= xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)        += xscale-cp0.o
 obj-$(CONFIG_CPU_PJ4)           += pj4-cp0.o
 obj-$(CONFIG_IWMMXT)            += iwmmxt.o
-obj-$(CONFIG_CPU_HAS_PMU)       += pmu.o
+obj-$(CONFIG_HW_PERF_EVENTS)    += perf_event.o perf_event_cpu.o
-obj-$(CONFIG_HW_PERF_EVENTS)    += perf_event.o
 AFLAGS_iwmmxt.o                 := -Wa,-mcpu=iwmmxt
 obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o
@@ -82,4 +81,6 @@ head-y			:= head$(MMUEXT).o
 obj-$(CONFIG_DEBUG_LL)  += debug.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
+obj-$(CONFIG_ARM_VIRT_EXT)      += hyp-stub.o
 extra-y := $(head-y) vmlinux.lds
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index cf258807160d..c8ef20747ee7 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -21,18 +21,28 @@
 #include <linux/io.h>
 #include <asm/cputype.h>
+#include <asm/delay.h>
 #include <asm/localtimer.h>
 #include <asm/arch_timer.h>
 #include <asm/system_info.h>
 #include <asm/sched_clock.h>
 static unsigned long arch_timer_rate;
-static int arch_timer_ppi;
-static int arch_timer_ppi2;
+enum ppi_nr {
+        PHYS_SECURE_PPI,
+        PHYS_NONSECURE_PPI,
+        VIRT_PPI,
+        HYP_PPI,
+        MAX_TIMER_PPI
+};
+static int arch_timer_ppi[MAX_TIMER_PPI];
 static struct clock_event_device __percpu **arch_timer_evt;
+static struct delay_timer arch_delay_timer;
-extern void init_current_timer_delay(unsigned long freq);
+static bool arch_timer_use_virtual = true;
 /*
 * Architected system timer support.
@@ -46,50 +56,104 @@ extern void init_current_timer_delay(unsigned long freq);
 #define ARCH_TIMER_REG_FREQ             1
 #define ARCH_TIMER_REG_TVAL             2
-static void arch_timer_reg_write(int reg, u32 val)
+#define ARCH_TIMER_PHYS_ACCESS          0
+#define ARCH_TIMER_VIRT_ACCESS          1
+/*
+ * These register accessors are marked inline so the compiler can
+ * nicely work out which register we want, and chuck away the rest of
+ * the code. At least it does so with a recent GCC (4.6.3).
+ */
+static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
 {
-        switch (reg) {
+        if (access == ARCH_TIMER_PHYS_ACCESS) {
-        case ARCH_TIMER_REG_CTRL:
+                switch (reg) {
-                asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+                case ARCH_TIMER_REG_CTRL:
-                break;
+                        asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
-        case ARCH_TIMER_REG_TVAL:
+                        break;
-                asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
+                case ARCH_TIMER_REG_TVAL:
-                break;
+                        asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
+                        break;
+                }
+        }
+        if (access == ARCH_TIMER_VIRT_ACCESS) {
+                switch (reg) {
+                case ARCH_TIMER_REG_CTRL:
+                        asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
+                        break;
+                case ARCH_TIMER_REG_TVAL:
+                        asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
+                        break;
+                }
        }
        isb();
 }
-static u32 arch_timer_reg_read(int reg)
+static inline u32 arch_timer_reg_read(const int access, const int reg)
 {
-        u32 val;
+        u32 val = 0;
+        if (access == ARCH_TIMER_PHYS_ACCESS) {
+                switch (reg) {
+                case ARCH_TIMER_REG_CTRL:
+                        asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+                        break;
+                case ARCH_TIMER_REG_TVAL:
+                        asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
+                        break;
+                case ARCH_TIMER_REG_FREQ:
+                        asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
+                        break;
+                }
+        }
-        switch (reg) {
+        if (access == ARCH_TIMER_VIRT_ACCESS) {
-        case ARCH_TIMER_REG_CTRL:
+                switch (reg) {
-                asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+                case ARCH_TIMER_REG_CTRL:
-                break;
+                        asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
-        case ARCH_TIMER_REG_FREQ:
+                        break;
-                asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
+                case ARCH_TIMER_REG_TVAL:
-                break;
+                        asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
-        case ARCH_TIMER_REG_TVAL:
+                        break;
-                asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
+                }
-                break;
-        default:
-                BUG();
        }
        return val;
 }
-static irqreturn_t arch_timer_handler(int irq, void *dev_id)
+static inline cycle_t arch_timer_counter_read(const int access)
 {
-        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+        cycle_t cval = 0;
-        unsigned long ctrl;
+        if (access == ARCH_TIMER_PHYS_ACCESS)
+                asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
+        if (access == ARCH_TIMER_VIRT_ACCESS)
+                asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
+        return cval;
+}
+static inline cycle_t arch_counter_get_cntpct(void)
+{
+        return arch_timer_counter_read(ARCH_TIMER_PHYS_ACCESS);
+}
-        ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+static inline cycle_t arch_counter_get_cntvct(void)
+{
+        return arch_timer_counter_read(ARCH_TIMER_VIRT_ACCESS);
+}
+static irqreturn_t inline timer_handler(const int access,
+                                        struct clock_event_device *evt)
+{
+        unsigned long ctrl;
+        ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
        if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
                ctrl |= ARCH_TIMER_CTRL_IT_MASK;
-                arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+                arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
                evt->event_handler(evt);
                return IRQ_HANDLED;
        }
@@ -97,63 +161,100 @@ static irqreturn_t arch_timer_handler(int irq, void *dev_id)
        return IRQ_NONE;
 }
-static void arch_timer_disable(void)
+static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
 {
-        unsigned long ctrl;
+        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
-        ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+        return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
-        ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
-        arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
 }
-static void arch_timer_set_mode(enum clock_event_mode mode,
+static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
-                                struct clock_event_device *clk)
 {
+        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+        return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
+}
+static inline void timer_set_mode(const int access, int mode)
+{
+        unsigned long ctrl;
        switch (mode) {
        case CLOCK_EVT_MODE_UNUSED:
        case CLOCK_EVT_MODE_SHUTDOWN:
-                arch_timer_disable();
+                ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
+                ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+                arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
                break;
        default:
                break;
        }
 }
-static int arch_timer_set_next_event(unsigned long evt,
+static void arch_timer_set_mode_virt(enum clock_event_mode mode,
-                                     struct clock_event_device *unused)
+                                     struct clock_event_device *clk)
 {
-        unsigned long ctrl;
+        timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode);
+}
-        ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+static void arch_timer_set_mode_phys(enum clock_event_mode mode,
+                                     struct clock_event_device *clk)
+{
+        timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
+}
+static inline void set_next_event(const int access, unsigned long evt)
+{
+        unsigned long ctrl;
+        ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
        ctrl |= ARCH_TIMER_CTRL_ENABLE;
        ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
+        arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
+        arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
+}
-        arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
+static int arch_timer_set_next_event_virt(unsigned long evt,
-        arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+                                          struct clock_event_device *unused)
+{
+        set_next_event(ARCH_TIMER_VIRT_ACCESS, evt);
+        return 0;
+}
+static int arch_timer_set_next_event_phys(unsigned long evt,
+                                          struct clock_event_device *unused)
+{
+        set_next_event(ARCH_TIMER_PHYS_ACCESS, evt);
        return 0;
 }
 static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
 {
-        /* Be safe... */
-        arch_timer_disable();
        clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
        clk->name = "arch_sys_timer";
        clk->rating = 450;
-        clk->set_mode = arch_timer_set_mode;
+        if (arch_timer_use_virtual) {
-        clk->set_next_event = arch_timer_set_next_event;
+                clk->irq = arch_timer_ppi[VIRT_PPI];
-        clk->irq = arch_timer_ppi;
+                clk->set_mode = arch_timer_set_mode_virt;
+                clk->set_next_event = arch_timer_set_next_event_virt;
+        } else {
+                clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
+                clk->set_mode = arch_timer_set_mode_phys;
+                clk->set_next_event = arch_timer_set_next_event_phys;
+        }
+        clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, NULL);
        clockevents_config_and_register(clk, arch_timer_rate,
                                        0xf, 0x7fffffff);
        *__this_cpu_ptr(arch_timer_evt) = clk;
-        enable_percpu_irq(clk->irq, 0);
+        if (arch_timer_use_virtual)
-        if (arch_timer_ppi2)
+                enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
-                enable_percpu_irq(arch_timer_ppi2, 0);
+        else {
+                enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
+                if (arch_timer_ppi[PHYS_NONSECURE_PPI])
+                        enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
+        }
        return 0;
 }
@@ -173,8 +274,8 @@ static int arch_timer_available(void)
                return -ENXIO;
        if (arch_timer_rate == 0) {
-                arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
+                freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS,
-                freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
+                                           ARCH_TIMER_REG_FREQ);
                /* Check the timer frequency. */
                if (freq == 0) {
@@ -185,52 +286,57 @@ static int arch_timer_available(void)
                arch_timer_rate = freq;
        }
-        pr_info_once("Architected local timer running at %lu.%02luMHz.\n",
+        pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
-                     arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100);
+                     arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100,
+                     arch_timer_use_virtual ? "virt" : "phys");
        return 0;
 }
-static inline cycle_t arch_counter_get_cntpct(void)
+static u32 notrace arch_counter_get_cntpct32(void)
 {
-        u32 cvall, cvalh;
+        cycle_t cnt = arch_counter_get_cntpct();
-        asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
-        return ((cycle_t) cvalh << 32) | cvall;
+        /*
-}
+         * The sched_clock infrastructure only knows about counters
+         * with at most 32bits. Forget about the upper 24 bits for the
-static inline cycle_t arch_counter_get_cntvct(void)
+         * time being...
-{
+         */
-        u32 cvall, cvalh;
+        return (u32)cnt;
-        asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
-        return ((cycle_t) cvalh << 32) | cvall;
 }
 static u32 notrace arch_counter_get_cntvct32(void)
 {
-        cycle_t cntvct = arch_counter_get_cntvct();
+        cycle_t cnt = arch_counter_get_cntvct();
        /*
         * The sched_clock infrastructure only knows about counters
         * with at most 32bits. Forget about the upper 24 bits for the
         * time being...
         */
-        return (u32)(cntvct & (u32)~0);
+        return (u32)cnt;
 }
 static cycle_t arch_counter_read(struct clocksource *cs)
 {
+        /*
+         * Always use the physical counter for the clocksource.
+         * CNTHCTL.PL1PCTEN must be set to 1.
+         */
        return arch_counter_get_cntpct();
 }
-int read_current_timer(unsigned long *timer_val)
+static unsigned long arch_timer_read_current_timer(void)
 {
-        if (!arch_timer_rate)
+        return arch_counter_get_cntpct();
-                return -ENXIO;
+}
-        *timer_val = arch_counter_get_cntpct();
-        return 0;
+static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
+{
+        /*
+         * Always use the physical counter for the clocksource.
+         * CNTHCTL.PL1PCTEN must be set to 1.
+         */
+        return arch_counter_get_cntpct();
 }
 static struct clocksource clocksource_counter = {
@@ -241,14 +347,32 @@ static struct clocksource clocksource_counter = {
        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
+static struct cyclecounter cyclecounter = {
+        .read   = arch_counter_read_cc,
+        .mask   = CLOCKSOURCE_MASK(56),
+};
+static struct timecounter timecounter;
+struct timecounter *arch_timer_get_timecounter(void)
+{
+        return &timecounter;
+}
 static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
 {
        pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
                 clk->irq, smp_processor_id());
-        disable_percpu_irq(clk->irq);
-        if (arch_timer_ppi2)
+        if (arch_timer_use_virtual)
-                disable_percpu_irq(arch_timer_ppi2);
+                disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
-        arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
+        else {
+                disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
+                if (arch_timer_ppi[PHYS_NONSECURE_PPI])
+                        disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
+        }
+        clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
 }
 static struct local_timer_ops arch_timer_ops __cpuinitdata = {
@@ -261,36 +385,48 @@ static struct clock_event_device arch_timer_global_evt;
 static int __init arch_timer_register(void)
 {
        int err;
+        int ppi;
        err = arch_timer_available();
        if (err)
-                return err;
+                goto out;
        arch_timer_evt = alloc_percpu(struct clock_event_device *);
-        if (!arch_timer_evt)
+        if (!arch_timer_evt) {
-                return -ENOMEM;
+                err = -ENOMEM;
+                goto out;
+        }
        clocksource_register_hz(&clocksource_counter, arch_timer_rate);
+        cyclecounter.mult = clocksource_counter.mult;
+        cyclecounter.shift = clocksource_counter.shift;
+        timecounter_init(&timecounter, &cyclecounter,
+                         arch_counter_get_cntpct());
+        if (arch_timer_use_virtual) {
+                ppi = arch_timer_ppi[VIRT_PPI];
+                err = request_percpu_irq(ppi, arch_timer_handler_virt,
+                                         "arch_timer", arch_timer_evt);
+        } else {
+                ppi = arch_timer_ppi[PHYS_SECURE_PPI];
+                err = request_percpu_irq(ppi, arch_timer_handler_phys,
+                                         "arch_timer", arch_timer_evt);
+                if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
+                        ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
+                        err = request_percpu_irq(ppi, arch_timer_handler_phys,
+                                                 "arch_timer", arch_timer_evt);
+                        if (err)
+                                free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
+                                                arch_timer_evt);
+                }
+        }
-        err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
-                                 "arch_timer", arch_timer_evt);
        if (err) {
                pr_err("arch_timer: can't register interrupt %d (%d)\n",
-                       arch_timer_ppi, err);
+                       ppi, err);
                goto out_free;
        }
-        if (arch_timer_ppi2) {
-                err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
-                                         "arch_timer", arch_timer_evt);
-                if (err) {
-                        pr_err("arch_timer: can't register interrupt %d (%d)\n",
-                               arch_timer_ppi2, err);
-                        arch_timer_ppi2 = 0;
-                        goto out_free_irq;
-                }
-        }
        err = local_timer_register(&arch_timer_ops);
        if (err) {
                /*
@@ -302,21 +438,29 @@ static int __init arch_timer_register(void)
                arch_timer_global_evt.cpumask = cpumask_of(0);
                err = arch_timer_setup(&arch_timer_global_evt);
        }
        if (err)
                goto out_free_irq;
-        init_current_timer_delay(arch_timer_rate);
+        /* Use the architected timer for the delay loop. */
+        arch_delay_timer.read_current_timer = &arch_timer_read_current_timer;
+        arch_delay_timer.freq = arch_timer_rate;
+        register_current_timer_delay(&arch_delay_timer);
        return 0;
 out_free_irq:
-        free_percpu_irq(arch_timer_ppi, arch_timer_evt);
+        if (arch_timer_use_virtual)
-        if (arch_timer_ppi2)
+                free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
-                free_percpu_irq(arch_timer_ppi2, arch_timer_evt);
+        else {
+                free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
+                                arch_timer_evt);
+                if (arch_timer_ppi[PHYS_NONSECURE_PPI])
+                        free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
+                                        arch_timer_evt);
+        }
 out_free:
        free_percpu(arch_timer_evt);
+out:
        return err;
 }
@@ -329,6 +473,7 @@ int __init arch_timer_of_register(void)
 {
        struct device_node *np;
        u32 freq;
+        int i;
        np = of_find_matching_node(NULL, arch_timer_of_match);
        if (!np) {
@@ -340,22 +485,40 @@ int __init arch_timer_of_register(void)
        if (!of_property_read_u32(np, "clock-frequency", &freq))
                arch_timer_rate = freq;
-        arch_timer_ppi = irq_of_parse_and_map(np, 0);
+        for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
-        arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
+                arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
-        pr_info("arch_timer: found %s irqs %d %d\n",
-                np->name, arch_timer_ppi, arch_timer_ppi2);
+        /*
+         * If no interrupt provided for virtual timer, we'll have to
+         * stick to the physical timer. It'd better be accessible...
+         */
+        if (!arch_timer_ppi[VIRT_PPI]) {
+                arch_timer_use_virtual = false;
+                if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
+                    !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
+                        pr_warn("arch_timer: No interrupt available, giving up\n");
+                        return -EINVAL;
+                }
+        }
        return arch_timer_register();
 }
 int __init arch_timer_sched_clock_init(void)
 {
+        u32 (*cnt32)(void);
        int err;
        err = arch_timer_available();
        if (err)
                return err;
-        setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
+        if (arch_timer_use_virtual)
+                cnt32 = arch_counter_get_cntvct32;
+        else
+                cnt32 = arch_counter_get_cntpct32;
+        setup_sched_clock(cnt32, 32, arch_timer_rate);
        return 0;
 }
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 1429d8989fb9..c985b481192c 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -59,10 +59,12 @@ int main(void)
  DEFINE(TI_USED_CP,            offsetof(struct thread_info, used_cp));
  DEFINE(TI_TP_VALUE,           offsetof(struct thread_info, tp_value));
  DEFINE(TI_FPSTATE,            offsetof(struct thread_info, fpstate));
+#ifdef CONFIG_VFP
  DEFINE(TI_VFPSTATE,           offsetof(struct thread_info, vfpstate));
 #ifdef CONFIG_SMP
  DEFINE(VFP_CPU,               offsetof(union vfp_state, hard.cpu));
 #endif
+#endif
 #ifdef CONFIG_ARM_THUMBEE
  DEFINE(TI_THUMBEE_STATE,      offsetof(struct thread_info, thumbee_state));
 #endif
diff --git a/arch/arm/kernel/atags.h b/arch/arm/kernel/atags.h
index e5f028d214a1..9edc9692332d 100644
--- a/arch/arm/kernel/atags.h
+++ b/arch/arm/kernel/atags.h
@@ -3,3 +3,17 @@ extern void save_atags(struct tag *tags);
 #else
 static inline void save_atags(struct tag *tags) { }
 #endif
+void convert_to_tag_list(struct tag *tags);
+#ifdef CONFIG_ATAGS
+struct machine_desc *setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr);
+#else
+static inline struct machine_desc *
+setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr)
+{
+        early_print("no ATAGS support: can't continue\n");
+        while (true);
+        unreachable();
+}
+#endif
diff --git a/arch/arm/kernel/compat.c b/arch/arm/kernel/atags_compat.c
index 925652318b8b..5236ad38f417 100644
--- a/arch/arm/kernel/compat.c
+++ b/arch/arm/kernel/atags_compat.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/kernel/compat.c
+ *  linux/arch/arm/kernel/atags_compat.c
 *
 *  Copyright (C) 2001 Russell King
 *
@@ -26,7 +26,7 @@
 #include <asm/mach/arch.h>
-#include "compat.h"
+#include "atags.h"
 /*
 * Usage:
diff --git a/arch/arm/kernel/atags_parse.c b/arch/arm/kernel/atags_parse.c
new file mode 100644
index 000000000000..14512e6931d8
--- /dev/null
+++ b/arch/arm/kernel/atags_parse.c
@@ -0,0 +1,238 @@
+/*
+ * Tag parsing.
+ *
+ * Copyright (C) 1995-2001 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * This is the traditional way of passing data to the kernel at boot time.  Rather
+ * than passing a fixed inflexible structure to the kernel, we pass a list
+ * of variable-sized tags to the kernel.  The first tag must be a ATAG_CORE
+ * tag for the list to be recognised (to distinguish the tagged list from
+ * a param_struct).  The list is terminated with a zero-length tag (this tag
+ * is not parsed in any way).
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/root_dev.h>
+#include <linux/screen_info.h>
+#include <asm/setup.h>
+#include <asm/system_info.h>
+#include <asm/page.h>
+#include <asm/mach/arch.h>
+#include "atags.h"
+static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
+#ifndef MEM_SIZE
+#define MEM_SIZE        (16*1024*1024)
+#endif
+static struct {
+        struct tag_header hdr1;
+        struct tag_core   core;
+        struct tag_header hdr2;
+        struct tag_mem32  mem;
+        struct tag_header hdr3;
+} default_tags __initdata = {
+        { tag_size(tag_core), ATAG_CORE },
+        { 1, PAGE_SIZE, 0xff },
+        { tag_size(tag_mem32), ATAG_MEM },
+        { MEM_SIZE },
+        { 0, ATAG_NONE }
+};
+static int __init parse_tag_core(const struct tag *tag)
+{
+        if (tag->hdr.size > 2) {
+                if ((tag->u.core.flags & 1) == 0)
+                        root_mountflags &= ~MS_RDONLY;
+                ROOT_DEV = old_decode_dev(tag->u.core.rootdev);
+        }
+        return 0;
+}
+__tagtable(ATAG_CORE, parse_tag_core);
+static int __init parse_tag_mem32(const struct tag *tag)
+{
+        return arm_add_memory(tag->u.mem.start, tag->u.mem.size);
+}
+__tagtable(ATAG_MEM, parse_tag_mem32);
+#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
+static int __init parse_tag_videotext(const struct tag *tag)
+{
+        screen_info.orig_x            = tag->u.videotext.x;
+        screen_info.orig_y            = tag->u.videotext.y;
+        screen_info.orig_video_page   = tag->u.videotext.video_page;
+        screen_info.orig_video_mode   = tag->u.videotext.video_mode;
+        screen_info.orig_video_cols   = tag->u.videotext.video_cols;
+        screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx;
+        screen_info.orig_video_lines  = tag->u.videotext.video_lines;
+        screen_info.orig_video_isVGA  = tag->u.videotext.video_isvga;
+        screen_info.orig_video_points = tag->u.videotext.video_points;
+        return 0;
+}
+__tagtable(ATAG_VIDEOTEXT, parse_tag_videotext);
+#endif
+#ifdef CONFIG_BLK_DEV_RAM
+static int __init parse_tag_ramdisk(const struct tag *tag)
+{
+        extern int rd_size, rd_image_start, rd_prompt, rd_doload;
+        rd_image_start = tag->u.ramdisk.start;
+        rd_doload = (tag->u.ramdisk.flags & 1) == 0;
+        rd_prompt = (tag->u.ramdisk.flags & 2) == 0;
+        if (tag->u.ramdisk.size)
+                rd_size = tag->u.ramdisk.size;
+        return 0;
+}
+__tagtable(ATAG_RAMDISK, parse_tag_ramdisk);
+#endif
+static int __init parse_tag_serialnr(const struct tag *tag)
+{
+        system_serial_low = tag->u.serialnr.low;
+        system_serial_high = tag->u.serialnr.high;
+        return 0;
+}
+__tagtable(ATAG_SERIAL, parse_tag_serialnr);
+static int __init parse_tag_revision(const struct tag *tag)
+{
+        system_rev = tag->u.revision.rev;
+        return 0;
+}
+__tagtable(ATAG_REVISION, parse_tag_revision);
+static int __init parse_tag_cmdline(const struct tag *tag)
+{
+#if defined(CONFIG_CMDLINE_EXTEND)
+        strlcat(default_command_line, " ", COMMAND_LINE_SIZE);
+        strlcat(default_command_line, tag->u.cmdline.cmdline,
+                COMMAND_LINE_SIZE);
+#elif defined(CONFIG_CMDLINE_FORCE)
+        pr_warning("Ignoring tag cmdline (using the default kernel command line)\n");
+#else
+        strlcpy(default_command_line, tag->u.cmdline.cmdline,
+                COMMAND_LINE_SIZE);
+#endif
+        return 0;
+}
+__tagtable(ATAG_CMDLINE, parse_tag_cmdline);
+/*
+ * Scan the tag table for this tag, and call its parse function.
+ * The tag table is built by the linker from all the __tagtable
+ * declarations.
+ */
+static int __init parse_tag(const struct tag *tag)
+{
+        extern struct tagtable __tagtable_begin, __tagtable_end;
+        struct tagtable *t;
+        for (t = &__tagtable_begin; t < &__tagtable_end; t++)
+                if (tag->hdr.tag == t->tag) {
+                        t->parse(tag);
+                        break;
+                }
+        return t < &__tagtable_end;
+}
+/*
+ * Parse all tags in the list, checking both the global and architecture
+ * specific tag tables.
+ */
+static void __init parse_tags(const struct tag *t)
+{
+        for (; t->hdr.size; t = tag_next(t))
+                if (!parse_tag(t))
+                        printk(KERN_WARNING
+                                "Ignoring unrecognised tag 0x%08x\n",
+                                t->hdr.tag);
+}
+static void __init squash_mem_tags(struct tag *tag)
+{
+        for (; tag->hdr.size; tag = tag_next(tag))
+                if (tag->hdr.tag == ATAG_MEM)
+                        tag->hdr.tag = ATAG_NONE;
+}
+struct machine_desc * __init setup_machine_tags(phys_addr_t __atags_pointer,
+                                                unsigned int machine_nr)
+{
+        struct tag *tags = (struct tag *)&default_tags;
+        struct machine_desc *mdesc = NULL, *p;
+        char *from = default_command_line;
+        default_tags.mem.start = PHYS_OFFSET;
+        /*
+         * locate machine in the list of supported machines.
+         */
+        for_each_machine_desc(p)
+                if (machine_nr == p->nr) {
+                        printk("Machine: %s\n", p->name);
+                        mdesc = p;
+                        break;
+                }
+        if (!mdesc) {
+                early_print("\nError: unrecognized/unsupported machine ID"
+                            " (r1 = 0x%08x).\n\n", machine_nr);
+                dump_machine_table(); /* does not return */
+        }
+        if (__atags_pointer)
+                tags = phys_to_virt(__atags_pointer);
+        else if (mdesc->atag_offset)
+                tags = (void *)(PAGE_OFFSET + mdesc->atag_offset);
+#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
+        /*
+         * If we have the old style parameters, convert them to
+         * a tag list.
+         */
+        if (tags->hdr.tag != ATAG_CORE)
+                convert_to_tag_list(tags);
+#endif
+        if (tags->hdr.tag != ATAG_CORE) {
+                early_print("Warning: Neither atags nor dtb found\n");
+                tags = (struct tag *)&default_tags;
+        }
+        if (mdesc->fixup)
+                mdesc->fixup(tags, &from, &meminfo);
+        if (tags->hdr.tag == ATAG_CORE) {
+                if (meminfo.nr_banks != 0)
+                        squash_mem_tags(tags);
+                save_atags(tags);
+                parse_tags(tags);
+        }
+        /* parse_early_param needs a boot_command_line */
+        strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
+        return mdesc;
+}
diff --git a/arch/arm/kernel/atags.c b/arch/arm/kernel/atags_proc.c
index 42a1a1415fa6..42a1a1415fa6 100644
--- a/arch/arm/kernel/atags.c
+++ b/arch/arm/kernel/atags_proc.c
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 2b2f25e7fef5..9b722612553d 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -13,6 +13,7 @@
 #include <linux/io.h>
 #include <asm/mach-types.h>
+#include <asm/mach/map.h>
 #include <asm/mach/pci.h>
 static int debug_pci;
@@ -270,15 +271,6 @@ static void __devinit pci_fixup_it8152(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
-void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
-{
-        if (debug_pci)
-                printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev));
-        pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
-}
 /*
 * If the bus contains any of these devices, then we must not turn on
 * parity checking of any kind.  Currently this is CyberPro 20x0 only.
@@ -423,6 +415,38 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
        return irq;
 }
+static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys)
+{
+        int ret;
+        struct pci_host_bridge_window *window;
+        if (list_empty(&sys->resources)) {
+                pci_add_resource_offset(&sys->resources,
+                         &iomem_resource, sys->mem_offset);
+        }
+        list_for_each_entry(window, &sys->resources, list) {
+                if (resource_type(window->res) == IORESOURCE_IO)
+                        return 0;
+        }
+        sys->io_res.start = (busnr * SZ_64K) ?  : pcibios_min_io;
+        sys->io_res.end = (busnr + 1) * SZ_64K - 1;
+        sys->io_res.flags = IORESOURCE_IO;
+        sys->io_res.name = sys->io_res_name;
+        sprintf(sys->io_res_name, "PCI%d I/O", busnr);
+        ret = request_resource(&ioport_resource, &sys->io_res);
+        if (ret) {
+                pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
+                return ret;
+        }
+        pci_add_resource_offset(&sys->resources, &sys->io_res,
+                                sys->io_offset);
+        return 0;
+}
 static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
 {
        struct pci_sys_data *sys = NULL;
@@ -445,11 +469,10 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
                ret = hw->setup(nr, sys);
                if (ret > 0) {
-                        if (list_empty(&sys->resources)) {
+                        ret = pcibios_init_resources(nr, sys);
-                                pci_add_resource_offset(&sys->resources,
+                        if (ret)  {
-                                         &ioport_resource, sys->io_offset);
+                                kfree(sys);
-                                pci_add_resource_offset(&sys->resources,
+                                break;
-                                         &iomem_resource, sys->mem_offset);
                        }
                        if (hw->scan)
@@ -627,3 +650,15 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
        return 0;
 }
+void __init pci_map_io_early(unsigned long pfn)
+{
+        struct map_desc pci_io_desc = {
+                .virtual        = PCI_IO_VIRT_BASE,
+                .type           = MT_DEVICE,
+                .length         = SZ_64K,
+        };
+        pci_io_desc.pfn = pfn;
+        iotable_init(&pci_io_desc, 1);
+}
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index e337879595e5..831cd38c8d99 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -20,7 +20,7 @@
                CALL(sys_creat)
                CALL(sys_link)
 /* 10 */        CALL(sys_unlink)
-                CALL(sys_execve_wrapper)
+                CALL(sys_execve)
                CALL(sys_chdir)
                CALL(OBSOLETE(sys_time))        /* used by libc4 */
                CALL(sys_mknod)
diff --git a/arch/arm/kernel/compat.h b/arch/arm/kernel/compat.h
deleted file mode 100644
index 39264ab1b9c6..000000000000
--- a/arch/arm/kernel/compat.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- *  linux/arch/arm/kernel/compat.h
- *
- *  Copyright (C) 2001 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-extern void convert_to_tag_list(struct tag *tags);
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index c45522c36787..66f711b2e0e8 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -20,90 +20,9 @@
 * references to these in a production kernel!
 */
-#if defined(CONFIG_DEBUG_ICEDCC)
+#if !defined(CONFIG_DEBUG_SEMIHOSTING)
-                @@ debug using ARM EmbeddedICE DCC channel
+#include CONFIG_DEBUG_LL_INCLUDE
+#endif
-                .macro  addruart, rp, rv, tmp
-                .endm
-#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
-                .macro  senduart, rd, rx
-                mcr     p14, 0, \rd, c0, c5, 0
-                .endm
-                .macro  busyuart, rd, rx
-1001:
-                mrc     p14, 0, \rx, c0, c1, 0
-                tst     \rx, #0x20000000
-                beq     1001b
-                .endm
-                .macro  waituart, rd, rx
-                mov     \rd, #0x2000000
-1001:
-                subs    \rd, \rd, #1
-                bmi     1002f
-                mrc     p14, 0, \rx, c0, c1, 0
-                tst     \rx, #0x20000000
-                bne     1001b
-1002:
-                .endm
-#elif defined(CONFIG_CPU_XSCALE)
-                .macro  senduart, rd, rx
-                mcr     p14, 0, \rd, c8, c0, 0
-                .endm
-                .macro  busyuart, rd, rx
-1001:
-                mrc     p14, 0, \rx, c14, c0, 0
-                tst     \rx, #0x10000000
-                beq     1001b
-                .endm
-                .macro  waituart, rd, rx
-                mov     \rd, #0x10000000
-1001:
-                subs    \rd, \rd, #1
-                bmi     1002f
-                mrc     p14, 0, \rx, c14, c0, 0
-                tst     \rx, #0x10000000
-                bne     1001b
-1002:
-                .endm
-#else
-                .macro  senduart, rd, rx
-                mcr     p14, 0, \rd, c1, c0, 0
-                .endm
-                .macro  busyuart, rd, rx
-1001:
-                mrc     p14, 0, \rx, c0, c0, 0
-                tst     \rx, #2
-                beq     1001b
-                .endm
-                .macro  waituart, rd, rx
-                mov     \rd, #0x2000000
-1001:
-                subs    \rd, \rd, #1
-                bmi     1002f
-                mrc     p14, 0, \rx, c0, c0, 0
-                tst     \rx, #2
-                bne     1001b
-1002:
-                .endm
-#endif  /* CONFIG_CPU_V6 */
-#elif !defined(CONFIG_DEBUG_SEMIHOSTING)
-#include <mach/debug-macro.S>
-#endif  /* CONFIG_DEBUG_ICEDCC */
 #ifdef CONFIG_MMU
                .macro  addruart_current, rx, tmp1, tmp2
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 978eac57e04a..417bac1846bd 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -86,14 +86,26 @@ ENDPROC(ret_to_user)
 */
 ENTRY(ret_from_fork)
        bl      schedule_tail
+        cmp     r5, #0
+        movne   r0, r4
+        movne   lr, pc
+        movne   pc, r5
        get_thread_info tsk
-        mov     why, #1
        b       ret_slow_syscall
 ENDPROC(ret_from_fork)
        .equ NR_syscalls,0
 #define CALL(x) .equ NR_syscalls,NR_syscalls+1
 #include "calls.S"
+/*
+ * Ensure that the system call table is equal to __NR_syscalls,
+ * which is the value the rest of the system sees
+ */
+.ifne NR_syscalls - __NR_syscalls
+.error "__NR_syscalls is not equal to the size of the syscall table"
+.endif
 #undef CALL
 #define CALL(x) .long x
@@ -508,11 +520,6 @@ sys_vfork_wrapper:
                b       sys_vfork
 ENDPROC(sys_vfork_wrapper)
-sys_execve_wrapper:
-                add     r3, sp, #S_OFF
-                b       sys_execve
-ENDPROC(sys_execve_wrapper)
 sys_clone_wrapper:
                add     ip, sp, #S_OFF
                str     ip, [sp, #4]
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 3db960e20cb8..4eee351f4668 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -23,8 +23,8 @@
 #include <asm/thread_info.h>
 #include <asm/pgtable.h>
-#ifdef CONFIG_DEBUG_LL
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING)
-#include <mach/debug-macro.S>
+#include CONFIG_DEBUG_LL_INCLUDE
 #endif
 /*
@@ -83,8 +83,12 @@ ENTRY(stext)
 THUMB( .thumb                  )       @ switch to Thumb now.
 THUMB(1:                       )
-        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
+#ifdef CONFIG_ARM_VIRT_EXT
-                                                @ and irqs disabled
+        bl      __hyp_stub_install
+#endif
+        @ ensure svc mode and all interrupts masked
+        safe_svcmode_maskall r9
        mrc     p15, 0, r9, c0, c0              @ get processor id
        bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
        movs    r10, r5                         @ invalid processor (r5=0)?
@@ -326,7 +330,11 @@ ENTRY(secondary_startup)
         * the processor type - there is no need to check the machine type
         * as it has already been validated by the primary processor.
         */
-        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
+#ifdef CONFIG_ARM_VIRT_EXT
+        bl      __hyp_stub_install
+#endif
+        safe_svcmode_maskall r9
        mrc     p15, 0, r9, c0, c0              @ get processor id
        bl      __lookup_processor_type
        movs    r10, r5                         @ invalid processor?
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
new file mode 100644
index 000000000000..65b2417aebce
--- /dev/null
+++ b/arch/arm/kernel/hyp-stub.S
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2012 Linaro Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <linux/init.h>
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/virt.h>
+#ifndef ZIMAGE
+/*
+ * For the kernel proper, we need to find out the CPU boot mode long after
+ * boot, so we need to store it in a writable variable.
+ *
+ * This is not in .bss, because we set it sufficiently early that the boot-time
+ * zeroing of .bss would clobber it.
+ */
+.data
+ENTRY(__boot_cpu_mode)
+        .long   0
+.text
+        /*
+         * Save the primary CPU boot mode. Requires 3 scratch registers.
+         */
+        .macro  store_primary_cpu_mode  reg1, reg2, reg3
+        mrs     \reg1, cpsr
+        and     \reg1, \reg1, #MODE_MASK
+        adr     \reg2, .L__boot_cpu_mode_offset
+        ldr     \reg3, [\reg2]
+        str     \reg1, [\reg2, \reg3]
+        .endm
+        /*
+         * Compare the current mode with the one saved on the primary CPU.
+         * If they don't match, record that fact. The Z bit indicates
+         * if there's a match or not.
+         * Requires 3 additionnal scratch registers.
+         */
+        .macro  compare_cpu_mode_with_primary mode, reg1, reg2, reg3
+        adr     \reg2, .L__boot_cpu_mode_offset
+        ldr     \reg3, [\reg2]
+        ldr     \reg1, [\reg2, \reg3]
+        cmp     \mode, \reg1            @ matches primary CPU boot mode?
+        orrne   r7, r7, #BOOT_CPU_MODE_MISMATCH
+        strne   r7, [r5, r6]            @ record what happened and give up
+        .endm
+#else   /* ZIMAGE */
+        .macro  store_primary_cpu_mode  reg1:req, reg2:req, reg3:req
+        .endm
+/*
+ * The zImage loader only runs on one CPU, so we don't bother with mult-CPU
+ * consistency checking:
+ */
+        .macro  compare_cpu_mode_with_primary mode, reg1, reg2, reg3
+        cmp     \mode, \mode
+        .endm
+#endif /* ZIMAGE */
+/*
+ * Hypervisor stub installation functions.
+ *
+ * These must be called with the MMU and D-cache off.
+ * They are not ABI compliant and are only intended to be called from the kernel
+ * entry points in head.S.
+ */
+@ Call this from the primary CPU
+ENTRY(__hyp_stub_install)
+        store_primary_cpu_mode  r4, r5, r6
+ENDPROC(__hyp_stub_install)
+        @ fall through...
+@ Secondary CPUs should call here
+ENTRY(__hyp_stub_install_secondary)
+        mrs     r4, cpsr
+        and     r4, r4, #MODE_MASK
+        /*
+         * If the secondary has booted with a different mode, give up
+         * immediately.
+         */
+        compare_cpu_mode_with_primary   r4, r5, r6, r7
+        bxne    lr
+        /*
+         * Once we have given up on one CPU, we do not try to install the
+         * stub hypervisor on the remaining ones: because the saved boot mode
+         * is modified, it can't compare equal to the CPSR mode field any
+         * more.
+         *
+         * Otherwise...
+         */
+        cmp     r4, #HYP_MODE
+        bxne    lr                      @ give up if the CPU is not in HYP mode
+/*
+ * Configure HSCTLR to set correct exception endianness/instruction set
+ * state etc.
+ * Turn off all traps
+ * Eventually, CPU-specific code might be needed -- assume not for now
+ *
+ * This code relies on the "eret" instruction to synchronize the
+ * various coprocessor accesses.
+ */
+        @ Now install the hypervisor stub:
+        adr     r7, __hyp_stub_vectors
+        mcr     p15, 4, r7, c12, c0, 0  @ set hypervisor vector base (HVBAR)
+        @ Disable all traps, so we don't get any nasty surprise
+        mov     r7, #0
+        mcr     p15, 4, r7, c1, c1, 0   @ HCR
+        mcr     p15, 4, r7, c1, c1, 2   @ HCPTR
+        mcr     p15, 4, r7, c1, c1, 3   @ HSTR
+THUMB(  orr     r7, #(1 << 30)  )       @ HSCTLR.TE
+#ifdef CONFIG_CPU_BIG_ENDIAN
+        orr     r7, #(1 << 9)           @ HSCTLR.EE
+#endif
+        mcr     p15, 4, r7, c1, c0, 0   @ HSCTLR
+        mrc     p15, 4, r7, c1, c1, 1   @ HDCR
+        and     r7, #0x1f               @ Preserve HPMN
+        mcr     p15, 4, r7, c1, c1, 1   @ HDCR
+#if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)
+        @ make CNTP_* and CNTPCT accessible from PL1
+        mrc     p15, 0, r7, c0, c1, 1   @ ID_PFR1
+        lsr     r7, #16
+        and     r7, #0xf
+        cmp     r7, #1
+        bne     1f
+        mrc     p15, 4, r7, c14, c1, 0  @ CNTHCTL
+        orr     r7, r7, #3              @ PL1PCEN | PL1PCTEN
+        mcr     p15, 4, r7, c14, c1, 0  @ CNTHCTL
+1:
+#endif
+        bic     r7, r4, #MODE_MASK
+        orr     r7, r7, #SVC_MODE
+THUMB(  orr     r7, r7, #PSR_T_BIT      )
+        msr     spsr_cxsf, r7           @ This is SPSR_hyp.
+        __MSR_ELR_HYP(14)               @ msr elr_hyp, lr
+        __ERET                          @ return, switching to SVC mode
+                                        @ The boot CPU mode is left in r4.
+ENDPROC(__hyp_stub_install_secondary)
+__hyp_stub_do_trap:
+        cmp     r0, #-1
+        mrceq   p15, 4, r0, c12, c0, 0  @ get HVBAR
+        mcrne   p15, 4, r0, c12, c0, 0  @ set HVBAR
+        __ERET
+ENDPROC(__hyp_stub_do_trap)
+/*
+ * __hyp_set_vectors: Call this after boot to set the initial hypervisor
+ * vectors as part of hypervisor installation.  On an SMP system, this should
+ * be called on each CPU.
+ *
+ * r0 must be the physical address of the new vector table (which must lie in
+ * the bottom 4GB of physical address space.
+ *
+ * r0 must be 32-byte aligned.
+ *
+ * Before calling this, you must check that the stub hypervisor is installed
+ * everywhere, by waiting for any secondary CPUs to be brought up and then
+ * checking that BOOT_CPU_MODE_HAVE_HYP(__boot_cpu_mode) is true.
+ *
+ * If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
+ * something else went wrong... in such cases, trying to install a new
+ * hypervisor is unlikely to work as desired.
+ *
+ * When you call into your shiny new hypervisor, sp_hyp will contain junk,
+ * so you will need to set that to something sensible at the new hypervisor's
+ * initialisation entry point.
+ */
+ENTRY(__hyp_get_vectors)
+        mov     r0, #-1
+ENDPROC(__hyp_get_vectors)
+        @ fall through
+ENTRY(__hyp_set_vectors)
+        __HVC(0)
+        bx      lr
+ENDPROC(__hyp_set_vectors)
+#ifndef ZIMAGE
+.align 2
+.L__boot_cpu_mode_offset:
+        .long   __boot_cpu_mode - .
+#endif
+.align 5
+__hyp_stub_vectors:
+__hyp_stub_reset:       W(b)    .
+__hyp_stub_und:         W(b)    .
+__hyp_stub_svc:         W(b)    .
+__hyp_stub_pabort:      W(b)    .
+__hyp_stub_dabort:      W(b)    .
+__hyp_stub_trap:        W(b)    __hyp_stub_do_trap
+__hyp_stub_irq:         W(b)    .
+__hyp_stub_fiq:         W(b)    .
+ENDPROC(__hyp_stub_vectors)
diff --git a/arch/arm/kernel/leds.c b/arch/arm/kernel/leds.c
deleted file mode 100644
index 1911dae19e4f..000000000000
--- a/arch/arm/kernel/leds.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * LED support code, ripped out of arch/arm/kernel/time.c
- *
- *  Copyright (C) 1994-2001 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/syscore_ops.h>
-#include <linux/string.h>
-#include <asm/leds.h>
-static void dummy_leds_event(led_event_t evt)
-{
-}
-void (*leds_event)(led_event_t) = dummy_leds_event;
-struct leds_evt_name {
-        const char      name[8];
-        int             on;
-        int             off;
-};
-static const struct leds_evt_name evt_names[] = {
-        { "amber", led_amber_on, led_amber_off },
-        { "blue",  led_blue_on,  led_blue_off  },
-        { "green", led_green_on, led_green_off },
-        { "red",   led_red_on,   led_red_off   },
-};
-static ssize_t leds_store(struct device *dev,
-                        struct device_attribute *attr,
-                        const char *buf, size_t size)
-{
-        int ret = -EINVAL, len = strcspn(buf, " ");
-        if (len > 0 && buf[len] == '\0')
-                len--;
-        if (strncmp(buf, "claim", len) == 0) {
-                leds_event(led_claim);
-                ret = size;
-        } else if (strncmp(buf, "release", len) == 0) {
-                leds_event(led_release);
-                ret = size;
-        } else {
-                int i;
-                for (i = 0; i < ARRAY_SIZE(evt_names); i++) {
-                        if (strlen(evt_names[i].name) != len ||
-                            strncmp(buf, evt_names[i].name, len) != 0)
-                                continue;
-                        if (strncmp(buf+len, " on", 3) == 0) {
-                                leds_event(evt_names[i].on);
-                                ret = size;
-                        } else if (strncmp(buf+len, " off", 4) == 0) {
-                                leds_event(evt_names[i].off);
-                                ret = size;
-                        }
-                        break;
-                }
-        }
-        return ret;
-}
-static DEVICE_ATTR(event, 0200, NULL, leds_store);
-static struct bus_type leds_subsys = {
-        .name           = "leds",
-        .dev_name       = "leds",
-};
-static struct device leds_device = {
-        .id             = 0,
-        .bus            = &leds_subsys,
-};
-static int leds_suspend(void)
-{
-        leds_event(led_stop);
-        return 0;
-}
-static void leds_resume(void)
-{
-        leds_event(led_start);
-}
-static void leds_shutdown(void)
-{
-        leds_event(led_halted);
-}
-static struct syscore_ops leds_syscore_ops = {
-        .shutdown       = leds_shutdown,
-        .suspend        = leds_suspend,
-        .resume         = leds_resume,
-};
-static int __init leds_init(void)
-{
-        int ret;
-        ret = subsys_system_register(&leds_subsys, NULL);
-        if (ret == 0)
-                ret = device_register(&leds_device);
-        if (ret == 0)
-                ret = device_create_file(&leds_device, &dev_attr_event);
-        if (ret == 0)
-                register_syscore_ops(&leds_syscore_ops);
-        return ret;
-}
-device_initcall(leds_init);
-EXPORT_SYMBOL(leds_event);
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index dfcdb9f7c126..e29c3337ca81 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -8,7 +8,9 @@
 #include <linux/reboot.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/memblock.h>
 #include <asm/pgtable.h>
+#include <linux/of_fdt.h>
 #include <asm/pgalloc.h>
 #include <asm/mmu_context.h>
 #include <asm/cacheflush.h>
@@ -32,6 +34,29 @@ static atomic_t waiting_for_crash_ipi;
 int machine_kexec_prepare(struct kimage *image)
 {
+        struct kexec_segment *current_segment;
+        __be32 header;
+        int i, err;
+        /*
+         * No segment at default ATAGs address. try to locate
+         * a dtb using magic.
+         */
+        for (i = 0; i < image->nr_segments; i++) {
+                current_segment = &image->segment[i];
+                err = memblock_is_region_memory(current_segment->mem,
+                                                current_segment->memsz);
+                if (err)
+                        return - EINVAL;
+                err = get_user(header, (__be32*)current_segment->buf);
+                if (err)
+                        return err;
+                if (be32_to_cpu(header) == OF_DT_HEADER)
+                        kexec_boot_atags = current_segment->mem;
+        }
        return 0;
 }
@@ -122,7 +147,9 @@ void machine_kexec(struct kimage *image)
        kexec_start_address = image->start;
        kexec_indirection_page = page_list;
        kexec_mach_type = machine_arch_type;
-        kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET;
+        if (!kexec_boot_atags)
+                kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET;
        /* copy our kernel relocation code to the control code page */
        memcpy(reboot_code_buffer,
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index ab243b87118d..93971b1a4f0b 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -12,68 +12,15 @@
 */
 #define pr_fmt(fmt) "hw perfevents: " fmt
-#include <linux/bitmap.h>
-#include <linux/interrupt.h>
 #include <linux/kernel.h>
-#include <linux/export.h>
-#include <linux/perf_event.h>
 #include <linux/platform_device.h>
-#include <linux/spinlock.h>
+#include <linux/pm_runtime.h>
 #include <linux/uaccess.h>
-#include <asm/cputype.h>
-#include <asm/irq.h>
 #include <asm/irq_regs.h>
 #include <asm/pmu.h>
 #include <asm/stacktrace.h>
-/*
- * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
- * another platform that supports more, we need to increase this to be the
- * largest of all platforms.
- *
- * ARMv7 supports up to 32 events:
- *  cycle counter CCNT + 31 events counters CNT0..30.
- *  Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
- */
-#define ARMPMU_MAX_HWEVENTS             32
-static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
-static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
-static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
-#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
-/* Set at runtime when we know what CPU type we are. */
-static struct arm_pmu *cpu_pmu;
-const char *perf_pmu_name(void)
-{
-        if (!cpu_pmu)
-                return NULL;
-        return cpu_pmu->pmu.name;
-}
-EXPORT_SYMBOL_GPL(perf_pmu_name);
-int perf_num_counters(void)
-{
-        int max_events = 0;
-        if (cpu_pmu != NULL)
-                max_events = cpu_pmu->num_events;
-        return max_events;
-}
-EXPORT_SYMBOL_GPL(perf_num_counters);
-#define HW_OP_UNSUPPORTED               0xFFFF
-#define C(_x) \
-        PERF_COUNT_HW_CACHE_##_x
-#define CACHE_OP_UNSUPPORTED            0xFFFF
 static int
 armpmu_map_cache_event(const unsigned (*cache_map)
                                      [PERF_COUNT_HW_CACHE_MAX]
@@ -104,7 +51,7 @@ armpmu_map_cache_event(const unsigned (*cache_map)
 }
 static int
-armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
+armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
 {
        int mapping = (*event_map)[config];
        return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
@@ -116,19 +63,20 @@ armpmu_map_raw_event(u32 raw_event_mask, u64 config)
        return (int)(config & raw_event_mask);
 }
-static int map_cpu_event(struct perf_event *event,
+int
-                         const unsigned (*event_map)[PERF_COUNT_HW_MAX],
+armpmu_map_event(struct perf_event *event,
-                         const unsigned (*cache_map)
+                 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
-                                        [PERF_COUNT_HW_CACHE_MAX]
+                 const unsigned (*cache_map)
-                                        [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_MAX]
-                                        [PERF_COUNT_HW_CACHE_RESULT_MAX],
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
-                         u32 raw_event_mask)
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX],
+                 u32 raw_event_mask)
 {
        u64 config = event->attr.config;
        switch (event->attr.type) {
        case PERF_TYPE_HARDWARE:
-                return armpmu_map_event(event_map, config);
+                return armpmu_map_hw_event(event_map, config);
        case PERF_TYPE_HW_CACHE:
                return armpmu_map_cache_event(cache_map, config);
        case PERF_TYPE_RAW:
@@ -222,7 +170,6 @@ armpmu_stop(struct perf_event *event, int flags)
         */
        if (!(hwc->state & PERF_HES_STOPPED)) {
                armpmu->disable(hwc, hwc->idx);
-                barrier(); /* why? */
                armpmu_event_update(event, hwc, hwc->idx);
                hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
        }
@@ -350,99 +297,41 @@ validate_group(struct perf_event *event)
        return 0;
 }
-static irqreturn_t armpmu_platform_irq(int irq, void *dev)
+static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 {
        struct arm_pmu *armpmu = (struct arm_pmu *) dev;
        struct platform_device *plat_device = armpmu->plat_device;
        struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
-        return plat->handle_irq(irq, dev, armpmu->handle_irq);
+        if (plat && plat->handle_irq)
+                return plat->handle_irq(irq, dev, armpmu->handle_irq);
+        else
+                return armpmu->handle_irq(irq, dev);
 }
 static void
 armpmu_release_hardware(struct arm_pmu *armpmu)
 {
-        int i, irq, irqs;
+        armpmu->free_irq();
-        struct platform_device *pmu_device = armpmu->plat_device;
+        pm_runtime_put_sync(&armpmu->plat_device->dev);
-        struct arm_pmu_platdata *plat =
-                dev_get_platdata(&pmu_device->dev);
-        irqs = min(pmu_device->num_resources, num_possible_cpus());
-        for (i = 0; i < irqs; ++i) {
-                if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
-                        continue;
-                irq = platform_get_irq(pmu_device, i);
-                if (irq >= 0) {
-                        if (plat && plat->disable_irq)
-                                plat->disable_irq(irq);
-                        free_irq(irq, armpmu);
-                }
-        }
-        release_pmu(armpmu->type);
 }
 static int
 armpmu_reserve_hardware(struct arm_pmu *armpmu)
 {
-        struct arm_pmu_platdata *plat;
+        int err;
-        irq_handler_t handle_irq;
-        int i, err, irq, irqs;
        struct platform_device *pmu_device = armpmu->plat_device;
        if (!pmu_device)
                return -ENODEV;
-        err = reserve_pmu(armpmu->type);
+        pm_runtime_get_sync(&pmu_device->dev);
+        err = armpmu->request_irq(armpmu_dispatch_irq);
        if (err) {
-                pr_warning("unable to reserve pmu\n");
+                armpmu_release_hardware(armpmu);
                return err;
        }
-        plat = dev_get_platdata(&pmu_device->dev);
-        if (plat && plat->handle_irq)
-                handle_irq = armpmu_platform_irq;
-        else
-                handle_irq = armpmu->handle_irq;
-        irqs = min(pmu_device->num_resources, num_possible_cpus());
-        if (irqs < 1) {
-                pr_err("no irqs for PMUs defined\n");
-                return -ENODEV;
-        }
-        for (i = 0; i < irqs; ++i) {
-                err = 0;
-                irq = platform_get_irq(pmu_device, i);
-                if (irq < 0)
-                        continue;
-                /*
-                 * If we have a single PMU interrupt that we can't shift,
-                 * assume that we're running on a uniprocessor machine and
-                 * continue. Otherwise, continue without this interrupt.
-                 */
-                if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
-                        pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
-                                    irq, i);
-                        continue;
-                }
-                err = request_irq(irq, handle_irq,
-                                  IRQF_DISABLED | IRQF_NOBALANCING,
-                                  "arm-pmu", armpmu);
-                if (err) {
-                        pr_err("unable to request IRQ%d for ARM PMU counters\n",
-                                irq);
-                        armpmu_release_hardware(armpmu);
-                        return err;
-                } else if (plat && plat->enable_irq)
-                        plat->enable_irq(irq);
-                cpumask_set_cpu(i, &armpmu->active_irqs);
-        }
        return 0;
 }
@@ -581,6 +470,32 @@ static void armpmu_disable(struct pmu *pmu)
        armpmu->stop();
 }
+#ifdef CONFIG_PM_RUNTIME
+static int armpmu_runtime_resume(struct device *dev)
+{
+        struct arm_pmu_platdata *plat = dev_get_platdata(dev);
+        if (plat && plat->runtime_resume)
+                return plat->runtime_resume(dev);
+        return 0;
+}
+static int armpmu_runtime_suspend(struct device *dev)
+{
+        struct arm_pmu_platdata *plat = dev_get_platdata(dev);
+        if (plat && plat->runtime_suspend)
+                return plat->runtime_suspend(dev);
+        return 0;
+}
+#endif
+const struct dev_pm_ops armpmu_dev_pm_ops = {
+        SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
+};
 static void __init armpmu_init(struct arm_pmu *armpmu)
 {
        atomic_set(&armpmu->active_events, 0);
@@ -598,174 +513,14 @@ static void __init armpmu_init(struct arm_pmu *armpmu)
        };
 }
-int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
+int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
 {
        armpmu_init(armpmu);
+        pr_info("enabled with %s PMU driver, %d counters available\n",
+                        armpmu->name, armpmu->num_events);
        return perf_pmu_register(&armpmu->pmu, name, type);
 }
-/* Include the PMU-specific implementations. */
-#include "perf_event_xscale.c"
-#include "perf_event_v6.c"
-#include "perf_event_v7.c"
-/*
- * Ensure the PMU has sane values out of reset.
- * This requires SMP to be available, so exists as a separate initcall.
- */
-static int __init
-cpu_pmu_reset(void)
-{
-        if (cpu_pmu && cpu_pmu->reset)
-                return on_each_cpu(cpu_pmu->reset, NULL, 1);
-        return 0;
-}
-arch_initcall(cpu_pmu_reset);
-/*
- * PMU platform driver and devicetree bindings.
- */
-static struct of_device_id armpmu_of_device_ids[] = {
-        {.compatible = "arm,cortex-a9-pmu"},
-        {.compatible = "arm,cortex-a8-pmu"},
-        {.compatible = "arm,arm1136-pmu"},
-        {.compatible = "arm,arm1176-pmu"},
-        {},
-};
-static struct platform_device_id armpmu_plat_device_ids[] = {
-        {.name = "arm-pmu"},
-        {},
-};
-static int __devinit armpmu_device_probe(struct platform_device *pdev)
-{
-        if (!cpu_pmu)
-                return -ENODEV;
-        cpu_pmu->plat_device = pdev;
-        return 0;
-}
-static struct platform_driver armpmu_driver = {
-        .driver         = {
-                .name   = "arm-pmu",
-                .of_match_table = armpmu_of_device_ids,
-        },
-        .probe          = armpmu_device_probe,
-        .id_table       = armpmu_plat_device_ids,
-};
-static int __init register_pmu_driver(void)
-{
-        return platform_driver_register(&armpmu_driver);
-}
-device_initcall(register_pmu_driver);
-static struct pmu_hw_events *armpmu_get_cpu_events(void)
-{
-        return &__get_cpu_var(cpu_hw_events);
-}
-static void __init cpu_pmu_init(struct arm_pmu *armpmu)
-{
-        int cpu;
-        for_each_possible_cpu(cpu) {
-                struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
-                events->events = per_cpu(hw_events, cpu);
-                events->used_mask = per_cpu(used_mask, cpu);
-                raw_spin_lock_init(&events->pmu_lock);
-        }
-        armpmu->get_hw_events = armpmu_get_cpu_events;
-        armpmu->type = ARM_PMU_DEVICE_CPU;
-}
-/*
- * PMU hardware loses all context when a CPU goes offline.
- * When a CPU is hotplugged back in, since some hardware registers are
- * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
- * junk values out of them.
- */
-static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
-                                        unsigned long action, void *hcpu)
-{
-        if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
-                return NOTIFY_DONE;
-        if (cpu_pmu && cpu_pmu->reset)
-                cpu_pmu->reset(NULL);
-        return NOTIFY_OK;
-}
-static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
-        .notifier_call = pmu_cpu_notify,
-};
-/*
- * CPU PMU identification and registration.
- */
-static int __init
-init_hw_perf_events(void)
-{
-        unsigned long cpuid = read_cpuid_id();
-        unsigned long implementor = (cpuid & 0xFF000000) >> 24;
-        unsigned long part_number = (cpuid & 0xFFF0);
-        /* ARM Ltd CPUs. */
-        if (0x41 == implementor) {
-                switch (part_number) {
-                case 0xB360:    /* ARM1136 */
-                case 0xB560:    /* ARM1156 */
-                case 0xB760:    /* ARM1176 */
-                        cpu_pmu = armv6pmu_init();
-                        break;
-                case 0xB020:    /* ARM11mpcore */
-                        cpu_pmu = armv6mpcore_pmu_init();
-                        break;
-                case 0xC080:    /* Cortex-A8 */
-                        cpu_pmu = armv7_a8_pmu_init();
-                        break;
-                case 0xC090:    /* Cortex-A9 */
-                        cpu_pmu = armv7_a9_pmu_init();
-                        break;
-                case 0xC050:    /* Cortex-A5 */
-                        cpu_pmu = armv7_a5_pmu_init();
-                        break;
-                case 0xC0F0:    /* Cortex-A15 */
-                        cpu_pmu = armv7_a15_pmu_init();
-                        break;
-                case 0xC070:    /* Cortex-A7 */
-                        cpu_pmu = armv7_a7_pmu_init();
-                        break;
-                }
-        /* Intel CPUs [xscale]. */
-        } else if (0x69 == implementor) {
-                part_number = (cpuid >> 13) & 0x7;
-                switch (part_number) {
-                case 1:
-                        cpu_pmu = xscale1pmu_init();
-                        break;
-                case 2:
-                        cpu_pmu = xscale2pmu_init();
-                        break;
-                }
-        }
-        if (cpu_pmu) {
-                pr_info("enabled with %s PMU driver, %d counters available\n",
-                        cpu_pmu->name, cpu_pmu->num_events);
-                cpu_pmu_init(cpu_pmu);
-                register_cpu_notifier(&pmu_cpu_notifier);
-                armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
-        } else {
-                pr_info("no hardware support available\n");
-        }
-        return 0;
-}
-early_initcall(init_hw_perf_events);
 /*
 * Callchain handling code.
 */
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
new file mode 100644
index 000000000000..8d7d8d4de9d6
--- /dev/null
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -0,0 +1,295 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+#define pr_fmt(fmt) "CPU PMU: " fmt
+#include <linux/bitmap.h>
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <asm/cputype.h>
+#include <asm/irq_regs.h>
+#include <asm/pmu.h>
+/* Set at runtime when we know what CPU type we are. */
+static struct arm_pmu *cpu_pmu;
+static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
+static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
+static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
+/*
+ * Despite the names, these two functions are CPU-specific and are used
+ * by the OProfile/perf code.
+ */
+const char *perf_pmu_name(void)
+{
+        if (!cpu_pmu)
+                return NULL;
+        return cpu_pmu->pmu.name;
+}
+EXPORT_SYMBOL_GPL(perf_pmu_name);
+int perf_num_counters(void)
+{
+        int max_events = 0;
+        if (cpu_pmu != NULL)
+                max_events = cpu_pmu->num_events;
+        return max_events;
+}
+EXPORT_SYMBOL_GPL(perf_num_counters);
+/* Include the PMU-specific implementations. */
+#include "perf_event_xscale.c"
+#include "perf_event_v6.c"
+#include "perf_event_v7.c"
+static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
+{
+        return &__get_cpu_var(cpu_hw_events);
+}
+static void cpu_pmu_free_irq(void)
+{
+        int i, irq, irqs;
+        struct platform_device *pmu_device = cpu_pmu->plat_device;
+        irqs = min(pmu_device->num_resources, num_possible_cpus());
+        for (i = 0; i < irqs; ++i) {
+                if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
+                        continue;
+                irq = platform_get_irq(pmu_device, i);
+                if (irq >= 0)
+                        free_irq(irq, cpu_pmu);
+        }
+}
+static int cpu_pmu_request_irq(irq_handler_t handler)
+{
+        int i, err, irq, irqs;
+        struct platform_device *pmu_device = cpu_pmu->plat_device;
+        if (!pmu_device)
+                return -ENODEV;
+        irqs = min(pmu_device->num_resources, num_possible_cpus());
+        if (irqs < 1) {
+                pr_err("no irqs for PMUs defined\n");
+                return -ENODEV;
+        }
+        for (i = 0; i < irqs; ++i) {
+                err = 0;
+                irq = platform_get_irq(pmu_device, i);
+                if (irq < 0)
+                        continue;
+                /*
+                 * If we have a single PMU interrupt that we can't shift,
+                 * assume that we're running on a uniprocessor machine and
+                 * continue. Otherwise, continue without this interrupt.
+                 */
+                if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
+                        pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
+                                    irq, i);
+                        continue;
+                }
+                err = request_irq(irq, handler, IRQF_NOBALANCING, "arm-pmu",
+                                  cpu_pmu);
+                if (err) {
+                        pr_err("unable to request IRQ%d for ARM PMU counters\n",
+                                irq);
+                        return err;
+                }
+                cpumask_set_cpu(i, &cpu_pmu->active_irqs);
+        }
+        return 0;
+}
+static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
+{
+        int cpu;
+        for_each_possible_cpu(cpu) {
+                struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
+                events->events = per_cpu(hw_events, cpu);
+                events->used_mask = per_cpu(used_mask, cpu);
+                raw_spin_lock_init(&events->pmu_lock);
+        }
+        cpu_pmu->get_hw_events  = cpu_pmu_get_cpu_events;
+        cpu_pmu->request_irq    = cpu_pmu_request_irq;
+        cpu_pmu->free_irq       = cpu_pmu_free_irq;
+        /* Ensure the PMU has sane values out of reset. */
+        if (cpu_pmu && cpu_pmu->reset)
+                on_each_cpu(cpu_pmu->reset, NULL, 1);
+}
+/*
+ * PMU hardware loses all context when a CPU goes offline.
+ * When a CPU is hotplugged back in, since some hardware registers are
+ * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
+ * junk values out of them.
+ */
+static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
+                                    unsigned long action, void *hcpu)
+{
+        if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
+                return NOTIFY_DONE;
+        if (cpu_pmu && cpu_pmu->reset)
+                cpu_pmu->reset(NULL);
+        return NOTIFY_OK;
+}
+static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
+        .notifier_call = cpu_pmu_notify,
+};
+/*
+ * PMU platform driver and devicetree bindings.
+ */
+static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = {
+        {.compatible = "arm,cortex-a15-pmu",    .data = armv7_a15_pmu_init},
+        {.compatible = "arm,cortex-a9-pmu",     .data = armv7_a9_pmu_init},
+        {.compatible = "arm,cortex-a8-pmu",     .data = armv7_a8_pmu_init},
+        {.compatible = "arm,cortex-a7-pmu",     .data = armv7_a7_pmu_init},
+        {.compatible = "arm,cortex-a5-pmu",     .data = armv7_a5_pmu_init},
+        {.compatible = "arm,arm11mpcore-pmu",   .data = armv6mpcore_pmu_init},
+        {.compatible = "arm,arm1176-pmu",       .data = armv6pmu_init},
+        {.compatible = "arm,arm1136-pmu",       .data = armv6pmu_init},
+        {},
+};
+static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
+        {.name = "arm-pmu"},
+        {},
+};
+/*
+ * CPU PMU identification and probing.
+ */
+static struct arm_pmu *__devinit probe_current_pmu(void)
+{
+        struct arm_pmu *pmu = NULL;
+        int cpu = get_cpu();
+        unsigned long cpuid = read_cpuid_id();
+        unsigned long implementor = (cpuid & 0xFF000000) >> 24;
+        unsigned long part_number = (cpuid & 0xFFF0);
+        pr_info("probing PMU on CPU %d\n", cpu);
+        /* ARM Ltd CPUs. */
+        if (0x41 == implementor) {
+                switch (part_number) {
+                case 0xB360:    /* ARM1136 */
+                case 0xB560:    /* ARM1156 */
+                case 0xB760:    /* ARM1176 */
+                        pmu = armv6pmu_init();
+                        break;
+                case 0xB020:    /* ARM11mpcore */
+                        pmu = armv6mpcore_pmu_init();
+                        break;
+                case 0xC080:    /* Cortex-A8 */
+                        pmu = armv7_a8_pmu_init();
+                        break;
+                case 0xC090:    /* Cortex-A9 */
+                        pmu = armv7_a9_pmu_init();
+                        break;
+                case 0xC050:    /* Cortex-A5 */
+                        pmu = armv7_a5_pmu_init();
+                        break;
+                case 0xC0F0:    /* Cortex-A15 */
+                        pmu = armv7_a15_pmu_init();
+                        break;
+                case 0xC070:    /* Cortex-A7 */
+                        pmu = armv7_a7_pmu_init();
+                        break;
+                }
+        /* Intel CPUs [xscale]. */
+        } else if (0x69 == implementor) {
+                part_number = (cpuid >> 13) & 0x7;
+                switch (part_number) {
+                case 1:
+                        pmu = xscale1pmu_init();
+                        break;
+                case 2:
+                        pmu = xscale2pmu_init();
+                        break;
+                }
+        }
+        put_cpu();
+        return pmu;
+}
+static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
+{
+        const struct of_device_id *of_id;
+        struct arm_pmu *(*init_fn)(void);
+        struct device_node *node = pdev->dev.of_node;
+        if (cpu_pmu) {
+                pr_info("attempt to register multiple PMU devices!");
+                return -ENOSPC;
+        }
+        if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
+                init_fn = of_id->data;
+                cpu_pmu = init_fn();
+        } else {
+                cpu_pmu = probe_current_pmu();
+        }
+        if (!cpu_pmu)
+                return -ENODEV;
+        cpu_pmu->plat_device = pdev;
+        cpu_pmu_init(cpu_pmu);
+        register_cpu_notifier(&cpu_pmu_hotplug_notifier);
+        armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
+        return 0;
+}
+static struct platform_driver cpu_pmu_driver = {
+        .driver         = {
+                .name   = "arm-pmu",
+                .pm     = &armpmu_dev_pm_ops,
+                .of_match_table = cpu_pmu_of_device_ids,
+        },
+        .probe          = cpu_pmu_device_probe,
+        .id_table       = cpu_pmu_plat_device_ids,
+};
+static int __init register_pmu_driver(void)
+{
+        return platform_driver_register(&cpu_pmu_driver);
+}
+device_initcall(register_pmu_driver);
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index c90fcb2b6967..6ccc07971745 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -645,7 +645,7 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
 static int armv6_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &armv6_perf_map,
+        return armpmu_map_event(event, &armv6_perf_map,
                                &armv6_perf_cache_map, 0xFF);
 }
@@ -664,7 +664,7 @@ static struct arm_pmu armv6pmu = {
        .max_period             = (1LLU << 32) - 1,
 };
-static struct arm_pmu *__init armv6pmu_init(void)
+static struct arm_pmu *__devinit armv6pmu_init(void)
 {
        return &armv6pmu;
 }
@@ -679,7 +679,7 @@ static struct arm_pmu *__init armv6pmu_init(void)
 static int armv6mpcore_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &armv6mpcore_perf_map,
+        return armpmu_map_event(event, &armv6mpcore_perf_map,
                                &armv6mpcore_perf_cache_map, 0xFF);
 }
@@ -698,17 +698,17 @@ static struct arm_pmu armv6mpcore_pmu = {
        .max_period             = (1LLU << 32) - 1,
 };
-static struct arm_pmu *__init armv6mpcore_pmu_init(void)
+static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
 {
        return &armv6mpcore_pmu;
 }
 #else
-static struct arm_pmu *__init armv6pmu_init(void)
+static struct arm_pmu *__devinit armv6pmu_init(void)
 {
        return NULL;
 }
-static struct arm_pmu *__init armv6mpcore_pmu_init(void)
+static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
 {
        return NULL;
 }
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index f04070bd2183..bd4b090ebcfd 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1204,31 +1204,31 @@ static void armv7pmu_reset(void *info)
 static int armv7_a8_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &armv7_a8_perf_map,
+        return armpmu_map_event(event, &armv7_a8_perf_map,
                                &armv7_a8_perf_cache_map, 0xFF);
 }
 static int armv7_a9_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &armv7_a9_perf_map,
+        return armpmu_map_event(event, &armv7_a9_perf_map,
                                &armv7_a9_perf_cache_map, 0xFF);
 }
 static int armv7_a5_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &armv7_a5_perf_map,
+        return armpmu_map_event(event, &armv7_a5_perf_map,
                                &armv7_a5_perf_cache_map, 0xFF);
 }
 static int armv7_a15_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &armv7_a15_perf_map,
+        return armpmu_map_event(event, &armv7_a15_perf_map,
                                &armv7_a15_perf_cache_map, 0xFF);
 }
 static int armv7_a7_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &armv7_a7_perf_map,
+        return armpmu_map_event(event, &armv7_a7_perf_map,
                                &armv7_a7_perf_cache_map, 0xFF);
 }
@@ -1245,7 +1245,7 @@ static struct arm_pmu armv7pmu = {
        .max_period             = (1LLU << 32) - 1,
 };
-static u32 __init armv7_read_num_pmnc_events(void)
+static u32 __devinit armv7_read_num_pmnc_events(void)
 {
        u32 nb_cnt;
@@ -1256,7 +1256,7 @@ static u32 __init armv7_read_num_pmnc_events(void)
        return nb_cnt + 1;
 }
-static struct arm_pmu *__init armv7_a8_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
 {
        armv7pmu.name           = "ARMv7 Cortex-A8";
        armv7pmu.map_event      = armv7_a8_map_event;
@@ -1264,7 +1264,7 @@ static struct arm_pmu *__init armv7_a8_pmu_init(void)
        return &armv7pmu;
 }
-static struct arm_pmu *__init armv7_a9_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
 {
        armv7pmu.name           = "ARMv7 Cortex-A9";
        armv7pmu.map_event      = armv7_a9_map_event;
@@ -1272,7 +1272,7 @@ static struct arm_pmu *__init armv7_a9_pmu_init(void)
        return &armv7pmu;
 }
-static struct arm_pmu *__init armv7_a5_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
 {
        armv7pmu.name           = "ARMv7 Cortex-A5";
        armv7pmu.map_event      = armv7_a5_map_event;
@@ -1280,7 +1280,7 @@ static struct arm_pmu *__init armv7_a5_pmu_init(void)
        return &armv7pmu;
 }
-static struct arm_pmu *__init armv7_a15_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
 {
        armv7pmu.name           = "ARMv7 Cortex-A15";
        armv7pmu.map_event      = armv7_a15_map_event;
@@ -1289,7 +1289,7 @@ static struct arm_pmu *__init armv7_a15_pmu_init(void)
        return &armv7pmu;
 }
-static struct arm_pmu *__init armv7_a7_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
 {
        armv7pmu.name           = "ARMv7 Cortex-A7";
        armv7pmu.map_event      = armv7_a7_map_event;
@@ -1298,27 +1298,27 @@ static struct arm_pmu *__init armv7_a7_pmu_init(void)
        return &armv7pmu;
 }
 #else
-static struct arm_pmu *__init armv7_a8_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
 {
        return NULL;
 }
-static struct arm_pmu *__init armv7_a9_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
 {
        return NULL;
 }
-static struct arm_pmu *__init armv7_a5_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
 {
        return NULL;
 }
-static struct arm_pmu *__init armv7_a15_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
 {
        return NULL;
 }
-static struct arm_pmu *__init armv7_a7_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
 {
        return NULL;
 }
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index f759fe0bab63..426e19f380a2 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -430,7 +430,7 @@ xscale1pmu_write_counter(int counter, u32 val)
 static int xscale_map_event(struct perf_event *event)
 {
-        return map_cpu_event(event, &xscale_perf_map,
+        return armpmu_map_event(event, &xscale_perf_map,
                                &xscale_perf_cache_map, 0xFF);
 }
@@ -449,7 +449,7 @@ static struct arm_pmu xscale1pmu = {
        .max_period     = (1LLU << 32) - 1,
 };
-static struct arm_pmu *__init xscale1pmu_init(void)
+static struct arm_pmu *__devinit xscale1pmu_init(void)
 {
        return &xscale1pmu;
 }
@@ -816,17 +816,17 @@ static struct arm_pmu xscale2pmu = {
        .max_period     = (1LLU << 32) - 1,
 };
-static struct arm_pmu *__init xscale2pmu_init(void)
+static struct arm_pmu *__devinit xscale2pmu_init(void)
 {
        return &xscale2pmu;
 }
 #else
-static struct arm_pmu *__init xscale1pmu_init(void)
+static struct arm_pmu *__devinit xscale1pmu_init(void)
 {
        return NULL;
 }
-static struct arm_pmu *__init xscale2pmu_init(void)
+static struct arm_pmu *__devinit xscale2pmu_init(void)
 {
        return NULL;
 }
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
deleted file mode 100644
index 2334bf8a650a..000000000000
--- a/arch/arm/kernel/pmu.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- *  linux/arch/arm/kernel/pmu.c
- *
- *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
- *  Copyright (C) 2010 ARM Ltd, Will Deacon
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <asm/pmu.h>
-/*
- * PMU locking to ensure mutual exclusion between different subsystems.
- */
-static unsigned long pmu_lock[BITS_TO_LONGS(ARM_NUM_PMU_DEVICES)];
-int
-reserve_pmu(enum arm_pmu_type type)
-{
-        return test_and_set_bit_lock(type, pmu_lock) ? -EBUSY : 0;
-}
-EXPORT_SYMBOL_GPL(reserve_pmu);
-void
-release_pmu(enum arm_pmu_type type)
-{
-        clear_bit_unlock(type, pmu_lock);
-}
-EXPORT_SYMBOL_GPL(release_pmu);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 693b744fd572..90084a6de35a 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -31,9 +31,9 @@
 #include <linux/random.h>
 #include <linux/hw_breakpoint.h>
 #include <linux/cpuidle.h>
+#include <linux/leds.h>
 #include <asm/cacheflush.h>
-#include <asm/leds.h>
 #include <asm/processor.h>
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
@@ -189,7 +189,7 @@ void cpu_idle(void)
        while (1) {
                tick_nohz_idle_enter();
                rcu_idle_enter();
-                leds_event(led_idle_start);
+                ledtrig_cpu(CPU_LED_IDLE_START);
                while (!need_resched()) {
 #ifdef CONFIG_HOTPLUG_CPU
                        if (cpu_is_offline(smp_processor_id()))
@@ -220,7 +220,7 @@ void cpu_idle(void)
                        } else
                                local_irq_enable();
                }
-                leds_event(led_idle_end);
+                ledtrig_cpu(CPU_LED_IDLE_END);
                rcu_idle_exit();
                tick_nohz_idle_exit();
                schedule_preempt_disabled();
@@ -381,13 +381,20 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
        struct thread_info *thread = task_thread_info(p);
        struct pt_regs *childregs = task_pt_regs(p);
-        *childregs = *regs;
-        childregs->ARM_r0 = 0;
-        childregs->ARM_sp = stack_start;
        memset(&thread->cpu_context, 0, sizeof(struct cpu_context_save));
-        thread->cpu_context.sp = (unsigned long)childregs;
+        if (likely(regs)) {
+                *childregs = *regs;
+                childregs->ARM_r0 = 0;
+                childregs->ARM_sp = stack_start;
+        } else {
+                memset(childregs, 0, sizeof(struct pt_regs));
+                thread->cpu_context.r4 = stk_sz;
+                thread->cpu_context.r5 = stack_start;
+                childregs->ARM_cpsr = SVC_MODE;
+        }
        thread->cpu_context.pc = (unsigned long)ret_from_fork;
+        thread->cpu_context.sp = (unsigned long)childregs;
        clear_ptrace_hw_breakpoint(p);
@@ -423,63 +430,6 @@ int dump_fpu (struct pt_regs *regs, struct user_fp *fp)
 }
 EXPORT_SYMBOL(dump_fpu);
-/*
- * Shuffle the argument into the correct register before calling the
- * thread function.  r4 is the thread argument, r5 is the pointer to
- * the thread function, and r6 points to the exit function.
- */
-extern void kernel_thread_helper(void);
-asm(    ".pushsection .text\n"
-"       .align\n"
-"       .type   kernel_thread_helper, #function\n"
-"kernel_thread_helper:\n"
-#ifdef CONFIG_TRACE_IRQFLAGS
-"       bl      trace_hardirqs_on\n"
-#endif
-"       msr     cpsr_c, r7\n"
-"       mov     r0, r4\n"
-"       mov     lr, r6\n"
-"       mov     pc, r5\n"
-"       .size   kernel_thread_helper, . - kernel_thread_helper\n"
-"       .popsection");
-#ifdef CONFIG_ARM_UNWIND
-extern void kernel_thread_exit(long code);
-asm(    ".pushsection .text\n"
-"       .align\n"
-"       .type   kernel_thread_exit, #function\n"
-"kernel_thread_exit:\n"
-"       .fnstart\n"
-"       .cantunwind\n"
-"       bl      do_exit\n"
-"       nop\n"
-"       .fnend\n"
-"       .size   kernel_thread_exit, . - kernel_thread_exit\n"
-"       .popsection");
-#else
-#define kernel_thread_exit      do_exit
-#endif
-/*
- * Create a kernel thread.
- */
-pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
-{
-        struct pt_regs regs;
-        memset(&regs, 0, sizeof(regs));
-        regs.ARM_r4 = (unsigned long)arg;
-        regs.ARM_r5 = (unsigned long)fn;
-        regs.ARM_r6 = (unsigned long)kernel_thread_exit;
-        regs.ARM_r7 = SVC_MODE | PSR_ENDSTATE | PSR_ISETSTATE;
-        regs.ARM_pc = (unsigned long)kernel_thread_helper;
-        regs.ARM_cpsr = regs.ARM_r7 | PSR_I_BIT;
-        return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
-}
-EXPORT_SYMBOL(kernel_thread);
 unsigned long get_wchan(struct task_struct *p)
 {
        struct stackframe frame;
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3e0fc5f7ed4b..739db3a1b2d2 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -30,6 +30,9 @@
 #include <asm/pgtable.h>
 #include <asm/traps.h>
+#define CREATE_TRACE_POINTS
+#include <trace/events/syscalls.h>
 #define REG_PC  15
 #define REG_PSR 16
 /*
@@ -918,11 +921,11 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 {
        unsigned long ip;
+        current_thread_info()->syscall = scno;
        if (!test_thread_flag(TIF_SYSCALL_TRACE))
                return scno;
-        current_thread_info()->syscall = scno;
        /*
         * IP is used to denote syscall entry/exit:
         * IP = 0 -> entry, =1 -> exit
@@ -941,15 +944,19 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
 {
-        int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
+        scno = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
+        if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+                trace_sys_enter(regs, scno);
        audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1,
                            regs->ARM_r2, regs->ARM_r3);
-        return ret;
+        return scno;
 }
 asmlinkage int syscall_trace_exit(struct pt_regs *regs, int scno)
 {
-        int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
+        scno = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
+        if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+                trace_sys_exit(regs, scno);
        audit_syscall_exit(regs);
-        return ret;
+        return scno;
 }
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c
index f4515393248d..e21bac20d90d 100644
--- a/arch/arm/kernel/sched_clock.c
+++ b/arch/arm/kernel/sched_clock.c
@@ -9,6 +9,7 @@
 #include <linux/init.h>
 #include <linux/jiffies.h>
 #include <linux/kernel.h>
+#include <linux/moduleparam.h>
 #include <linux/sched.h>
 #include <linux/syscore_ops.h>
 #include <linux/timer.h>
@@ -27,6 +28,9 @@ struct clock_data {
 static void sched_clock_poll(unsigned long wrap_ticks);
 static DEFINE_TIMER(sched_clock_timer, sched_clock_poll, 0, 0);
+static int irqtime = -1;
+core_param(irqtime, irqtime, int, 0400);
 static struct clock_data cd = {
        .mult   = NSEC_PER_SEC / HZ,
@@ -157,6 +161,10 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
         */
        cd.epoch_ns = 0;
+        /* Enable IRQ time accounting if we have a fast enough sched_clock */
+        if (irqtime > 0 || (irqtime == -1 && rate >= 1000000))
+                enable_sched_clock_irqtime();
        pr_debug("Registered %pF as sched_clock source\n", read);
 }
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index a81dcecc7343..da1d1aa20ad9 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -21,11 +21,9 @@
 #include <linux/init.h>
 #include <linux/kexec.h>
 #include <linux/of_fdt.h>
-#include <linux/root_dev.h>
 #include <linux/cpu.h>
 #include <linux/interrupt.h>
 #include <linux/smp.h>
-#include <linux/fs.h>
 #include <linux/proc_fs.h>
 #include <linux/memblock.h>
 #include <linux/bug.h>
@@ -55,16 +53,11 @@
 #include <asm/traps.h>
 #include <asm/unwind.h>
 #include <asm/memblock.h>
+#include <asm/virt.h>
-#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
-#include "compat.h"
-#endif
 #include "atags.h"
 #include "tcm.h"
-#ifndef MEM_SIZE
-#define MEM_SIZE        (16*1024*1024)
-#endif
 #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
 char fpe_type[8];
@@ -145,7 +138,6 @@ static const char *machine_name;
 static char __initdata cmd_line[COMMAND_LINE_SIZE];
 struct machine_desc *machine_desc __initdata;
-static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
 #define ENDIANNESS ((char)endian_test.l)
@@ -583,21 +575,6 @@ static int __init early_mem(char *p)
 }
 early_param("mem", early_mem);
-static void __init
-setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz)
-{
-#ifdef CONFIG_BLK_DEV_RAM
-        extern int rd_size, rd_image_start, rd_prompt, rd_doload;
-        rd_image_start = image_start;
-        rd_prompt = prompt;
-        rd_doload = doload;
-        if (rd_sz)
-                rd_size = rd_sz;
-#endif
-}
 static void __init request_standard_resources(struct machine_desc *mdesc)
 {
        struct memblock_region *region;
@@ -643,35 +620,6 @@ static void __init request_standard_resources(struct machine_desc *mdesc)
                request_resource(&ioport_resource, &lp2);
 }
-/*
- *  Tag parsing.
- *
- * This is the new way of passing data to the kernel at boot time.  Rather
- * than passing a fixed inflexible structure to the kernel, we pass a list
- * of variable-sized tags to the kernel.  The first tag must be a ATAG_CORE
- * tag for the list to be recognised (to distinguish the tagged list from
- * a param_struct).  The list is terminated with a zero-length tag (this tag
- * is not parsed in any way).
- */
-static int __init parse_tag_core(const struct tag *tag)
-{
-        if (tag->hdr.size > 2) {
-                if ((tag->u.core.flags & 1) == 0)
-                        root_mountflags &= ~MS_RDONLY;
-                ROOT_DEV = old_decode_dev(tag->u.core.rootdev);
-        }
-        return 0;
-}
-__tagtable(ATAG_CORE, parse_tag_core);
-static int __init parse_tag_mem32(const struct tag *tag)
-{
-        return arm_add_memory(tag->u.mem.start, tag->u.mem.size);
-}
-__tagtable(ATAG_MEM, parse_tag_mem32);
 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
 struct screen_info screen_info = {
 .orig_video_lines      = 30,
@@ -681,117 +629,8 @@ struct screen_info screen_info = {
 .orig_video_isVGA      = 1,
 .orig_video_points     = 8
 };
-static int __init parse_tag_videotext(const struct tag *tag)
-{
-        screen_info.orig_x            = tag->u.videotext.x;
-        screen_info.orig_y            = tag->u.videotext.y;
-        screen_info.orig_video_page   = tag->u.videotext.video_page;
-        screen_info.orig_video_mode   = tag->u.videotext.video_mode;
-        screen_info.orig_video_cols   = tag->u.videotext.video_cols;
-        screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx;
-        screen_info.orig_video_lines  = tag->u.videotext.video_lines;
-        screen_info.orig_video_isVGA  = tag->u.videotext.video_isvga;
-        screen_info.orig_video_points = tag->u.videotext.video_points;
-        return 0;
-}
-__tagtable(ATAG_VIDEOTEXT, parse_tag_videotext);
 #endif
-static int __init parse_tag_ramdisk(const struct tag *tag)
-{
-        setup_ramdisk((tag->u.ramdisk.flags & 1) == 0,
-                      (tag->u.ramdisk.flags & 2) == 0,
-                      tag->u.ramdisk.start, tag->u.ramdisk.size);
-        return 0;
-}
-__tagtable(ATAG_RAMDISK, parse_tag_ramdisk);
-static int __init parse_tag_serialnr(const struct tag *tag)
-{
-        system_serial_low = tag->u.serialnr.low;
-        system_serial_high = tag->u.serialnr.high;
-        return 0;
-}
-__tagtable(ATAG_SERIAL, parse_tag_serialnr);
-static int __init parse_tag_revision(const struct tag *tag)
-{
-        system_rev = tag->u.revision.rev;
-        return 0;
-}
-__tagtable(ATAG_REVISION, parse_tag_revision);
-static int __init parse_tag_cmdline(const struct tag *tag)
-{
-#if defined(CONFIG_CMDLINE_EXTEND)
-        strlcat(default_command_line, " ", COMMAND_LINE_SIZE);
-        strlcat(default_command_line, tag->u.cmdline.cmdline,
-                COMMAND_LINE_SIZE);
-#elif defined(CONFIG_CMDLINE_FORCE)
-        pr_warning("Ignoring tag cmdline (using the default kernel command line)\n");
-#else
-        strlcpy(default_command_line, tag->u.cmdline.cmdline,
-                COMMAND_LINE_SIZE);
-#endif
-        return 0;
-}
-__tagtable(ATAG_CMDLINE, parse_tag_cmdline);
-/*
- * Scan the tag table for this tag, and call its parse function.
- * The tag table is built by the linker from all the __tagtable
- * declarations.
- */
-static int __init parse_tag(const struct tag *tag)
-{
-        extern struct tagtable __tagtable_begin, __tagtable_end;
-        struct tagtable *t;
-        for (t = &__tagtable_begin; t < &__tagtable_end; t++)
-                if (tag->hdr.tag == t->tag) {
-                        t->parse(tag);
-                        break;
-                }
-        return t < &__tagtable_end;
-}
-/*
- * Parse all tags in the list, checking both the global and architecture
- * specific tag tables.
- */
-static void __init parse_tags(const struct tag *t)
-{
-        for (; t->hdr.size; t = tag_next(t))
-                if (!parse_tag(t))
-                        printk(KERN_WARNING
-                                "Ignoring unrecognised tag 0x%08x\n",
-                                t->hdr.tag);
-}
-/*
- * This holds our defaults.
- */
-static struct init_tags {
-        struct tag_header hdr1;
-        struct tag_core   core;
-        struct tag_header hdr2;
-        struct tag_mem32  mem;
-        struct tag_header hdr3;
-} init_tags __initdata = {
-        { tag_size(tag_core), ATAG_CORE },
-        { 1, PAGE_SIZE, 0xff },
-        { tag_size(tag_mem32), ATAG_MEM },
-        { MEM_SIZE },
-        { 0, ATAG_NONE }
-};
 static int __init customize_machine(void)
 {
        /* customizes platform devices, or adds new ones */
@@ -858,78 +697,6 @@ static void __init reserve_crashkernel(void)
 static inline void reserve_crashkernel(void) {}
 #endif /* CONFIG_KEXEC */
-static void __init squash_mem_tags(struct tag *tag)
-{
-        for (; tag->hdr.size; tag = tag_next(tag))
-                if (tag->hdr.tag == ATAG_MEM)
-                        tag->hdr.tag = ATAG_NONE;
-}
-static struct machine_desc * __init setup_machine_tags(unsigned int nr)
-{
-        struct tag *tags = (struct tag *)&init_tags;
-        struct machine_desc *mdesc = NULL, *p;
-        char *from = default_command_line;
-        init_tags.mem.start = PHYS_OFFSET;
-        /*
-         * locate machine in the list of supported machines.
-         */
-        for_each_machine_desc(p)
-                if (nr == p->nr) {
-                        printk("Machine: %s\n", p->name);
-                        mdesc = p;
-                        break;
-                }
-        if (!mdesc) {
-                early_print("\nError: unrecognized/unsupported machine ID"
-                        " (r1 = 0x%08x).\n\n", nr);
-                dump_machine_table(); /* does not return */
-        }
-        if (__atags_pointer)
-                tags = phys_to_virt(__atags_pointer);
-        else if (mdesc->atag_offset)
-                tags = (void *)(PAGE_OFFSET + mdesc->atag_offset);
-#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
-        /*
-         * If we have the old style parameters, convert them to
-         * a tag list.
-         */
-        if (tags->hdr.tag != ATAG_CORE)
-                convert_to_tag_list(tags);
-#endif
-        if (tags->hdr.tag != ATAG_CORE) {
-#if defined(CONFIG_OF)
-                /*
-                 * If CONFIG_OF is set, then assume this is a reasonably
-                 * modern system that should pass boot parameters
-                 */
-                early_print("Warning: Neither atags nor dtb found\n");
-#endif
-                tags = (struct tag *)&init_tags;
-        }
-        if (mdesc->fixup)
-                mdesc->fixup(tags, &from, &meminfo);
-        if (tags->hdr.tag == ATAG_CORE) {
-                if (meminfo.nr_banks != 0)
-                        squash_mem_tags(tags);
-                save_atags(tags);
-                parse_tags(tags);
-        }
-        /* parse_early_param needs a boot_command_line */
-        strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
-        return mdesc;
-}
 static int __init meminfo_cmp(const void *_a, const void *_b)
 {
        const struct membank *a = _a, *b = _b;
@@ -937,6 +704,21 @@ static int __init meminfo_cmp(const void *_a, const void *_b)
        return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
 }
+void __init hyp_mode_check(void)
+{
+#ifdef CONFIG_ARM_VIRT_EXT
+        if (is_hyp_mode_available()) {
+                pr_info("CPU: All CPU(s) started in HYP mode.\n");
+                pr_info("CPU: Virtualization extensions available.\n");
+        } else if (is_hyp_mode_mismatched()) {
+                pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
+                        __boot_cpu_mode & MODE_MASK);
+                pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
+        } else
+                pr_info("CPU: All CPU(s) started in SVC mode.\n");
+#endif
+}
 void __init setup_arch(char **cmdline_p)
 {
        struct machine_desc *mdesc;
@@ -944,7 +726,7 @@ void __init setup_arch(char **cmdline_p)
        setup_processor();
        mdesc = setup_machine_fdt(__atags_pointer);
        if (!mdesc)
-                mdesc = setup_machine_tags(machine_arch_type);
+                mdesc = setup_machine_tags(__atags_pointer, machine_arch_type);
        machine_desc = mdesc;
        machine_name = mdesc->name;
@@ -977,9 +759,15 @@ void __init setup_arch(char **cmdline_p)
        unflatten_device_tree();
 #ifdef CONFIG_SMP
-        if (is_smp())
+        if (is_smp()) {
+                smp_set_ops(mdesc->smp);
                smp_init_cpus();
+        }
 #endif
+        if (!is_smp())
+                hyp_mode_check();
        reserve_crashkernel();
        tcm_init();
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index f27789e4e38a..56f72d257ebd 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -10,7 +10,6 @@
 #include <linux/errno.h>
 #include <linux/signal.h>
 #include <linux/personality.h>
-#include <linux/freezer.h>
 #include <linux/uaccess.h>
 #include <linux/tracehook.h>
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index ebd8ad274d76..8e20754dd31d 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -19,14 +19,15 @@
 #include <linux/mm.h>
 #include <linux/err.h>
 #include <linux/cpu.h>
-#include <linux/smp.h>
 #include <linux/seq_file.h>
 #include <linux/irq.h>
 #include <linux/percpu.h>
 #include <linux/clockchips.h>
 #include <linux/completion.h>
+#include <linux/cpufreq.h>
 #include <linux/atomic.h>
+#include <asm/smp.h>
 #include <asm/cacheflush.h>
 #include <asm/cpu.h>
 #include <asm/cputype.h>
@@ -42,6 +43,8 @@
 #include <asm/ptrace.h>
 #include <asm/localtimer.h>
 #include <asm/smp_plat.h>
+#include <asm/virt.h>
+#include <asm/mach/arch.h>
 /*
 * as from 2.5, kernels no longer have an init_tasks structure
@@ -50,8 +53,15 @@
 */
 struct secondary_data secondary_data;
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata pen_release = -1;
 enum ipi_msg_type {
-        IPI_TIMER = 2,
+        IPI_WAKEUP,
+        IPI_TIMER,
        IPI_RESCHEDULE,
        IPI_CALL_FUNC,
        IPI_CALL_FUNC_SINGLE,
@@ -60,6 +70,14 @@ enum ipi_msg_type {
 static DECLARE_COMPLETION(cpu_running);
+static struct smp_operations smp_ops;
+void __init smp_set_ops(struct smp_operations *ops)
+{
+        if (ops)
+                smp_ops = *ops;
+};
 int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
        int ret;
@@ -100,13 +118,64 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
        return ret;
 }
+/* platform specific SMP operations */
+void __init smp_init_cpus(void)
+{
+        if (smp_ops.smp_init_cpus)
+                smp_ops.smp_init_cpus();
+}
+static void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+        if (smp_ops.smp_prepare_cpus)
+                smp_ops.smp_prepare_cpus(max_cpus);
+}
+static void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+        if (smp_ops.smp_secondary_init)
+                smp_ops.smp_secondary_init(cpu);
+}
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        if (smp_ops.smp_boot_secondary)
+                return smp_ops.smp_boot_secondary(cpu, idle);
+        return -ENOSYS;
+}
 #ifdef CONFIG_HOTPLUG_CPU
 static void percpu_timer_stop(void);
+static int platform_cpu_kill(unsigned int cpu)
+{
+        if (smp_ops.cpu_kill)
+                return smp_ops.cpu_kill(cpu);
+        return 1;
+}
+static void platform_cpu_die(unsigned int cpu)
+{
+        if (smp_ops.cpu_die)
+                smp_ops.cpu_die(cpu);
+}
+static int platform_cpu_disable(unsigned int cpu)
+{
+        if (smp_ops.cpu_disable)
+                return smp_ops.cpu_disable(cpu);
+        /*
+         * By default, allow disabling all CPUs except the first one,
+         * since this is special on a lot of platforms, e.g. because
+         * of clock tick interrupts.
+         */
+        return cpu == 0 ? -EPERM : 0;
+}
 /*
 * __cpu_disable runs on the processor to be shutdown.
 */
-int __cpu_disable(void)
+int __cpuinit __cpu_disable(void)
 {
        unsigned int cpu = smp_processor_id();
        int ret;
@@ -134,8 +203,11 @@ int __cpu_disable(void)
        /*
         * Flush user cache and TLB mappings, and then remove this CPU
         * from the vm mask set of all processes.
+         *
+         * Caches are flushed to the Level of Unification Inner Shareable
+         * to write-back dirty lines to unified caches shared by all CPUs.
         */
-        flush_cache_all();
+        flush_cache_louis();
        local_flush_tlb_all();
        clear_tasks_mm_cpumask(cpu);
@@ -149,7 +221,7 @@ static DECLARE_COMPLETION(cpu_died);
 * called on the thread which is asking for a CPU to be shutdown -
 * waits until shutdown has completed, or it is timed out.
 */
-void __cpu_die(unsigned int cpu)
+void __cpuinit __cpu_die(unsigned int cpu)
 {
        if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
                pr_err("CPU%u: cpu didn't die\n", cpu);
@@ -287,6 +359,8 @@ void __init smp_cpus_done(unsigned int max_cpus)
               num_online_cpus(),
               bogosum / (500000/HZ),
               (bogosum / (5000/HZ)) % 100);
+        hyp_mode_check();
 }
 void __init smp_prepare_boot_cpu(void)
@@ -347,7 +421,8 @@ void arch_send_call_function_single_ipi(int cpu)
 }
 static const char *ipi_types[NR_IPI] = {
-#define S(x,s)  [x - IPI_TIMER] = s
+#define S(x,s)  [x] = s
+        S(IPI_WAKEUP, "CPU wakeup interrupts"),
        S(IPI_TIMER, "Timer broadcast interrupts"),
        S(IPI_RESCHEDULE, "Rescheduling interrupts"),
        S(IPI_CALL_FUNC, "Function call interrupts"),
@@ -500,10 +575,13 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
        unsigned int cpu = smp_processor_id();
        struct pt_regs *old_regs = set_irq_regs(regs);
-        if (ipinr >= IPI_TIMER && ipinr < IPI_TIMER + NR_IPI)
+        if (ipinr < NR_IPI)
-                __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_TIMER]);
+                __inc_irq_stat(cpu, ipi_irqs[ipinr]);
        switch (ipinr) {
+        case IPI_WAKEUP:
+                break;
        case IPI_TIMER:
                irq_enter();
                ipi_timer();
@@ -584,3 +662,56 @@ int setup_profiling_timer(unsigned int multiplier)
 {
        return -EINVAL;
 }
+#ifdef CONFIG_CPU_FREQ
+static DEFINE_PER_CPU(unsigned long, l_p_j_ref);
+static DEFINE_PER_CPU(unsigned long, l_p_j_ref_freq);
+static unsigned long global_l_p_j_ref;
+static unsigned long global_l_p_j_ref_freq;
+static int cpufreq_callback(struct notifier_block *nb,
+                                        unsigned long val, void *data)
+{
+        struct cpufreq_freqs *freq = data;
+        int cpu = freq->cpu;
+        if (freq->flags & CPUFREQ_CONST_LOOPS)
+                return NOTIFY_OK;
+        if (!per_cpu(l_p_j_ref, cpu)) {
+                per_cpu(l_p_j_ref, cpu) =
+                        per_cpu(cpu_data, cpu).loops_per_jiffy;
+                per_cpu(l_p_j_ref_freq, cpu) = freq->old;
+                if (!global_l_p_j_ref) {
+                        global_l_p_j_ref = loops_per_jiffy;
+                        global_l_p_j_ref_freq = freq->old;
+                }
+        }
+        if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
+            (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
+            (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE)) {
+                loops_per_jiffy = cpufreq_scale(global_l_p_j_ref,
+                                                global_l_p_j_ref_freq,
+                                                freq->new);
+                per_cpu(cpu_data, cpu).loops_per_jiffy =
+                        cpufreq_scale(per_cpu(l_p_j_ref, cpu),
+                                        per_cpu(l_p_j_ref_freq, cpu),
+                                        freq->new);
+        }
+        return NOTIFY_OK;
+}
+static struct notifier_block cpufreq_notifier = {
+        .notifier_call  = cpufreq_callback,
+};
+static int __init register_cpufreq_notifier(void)
+{
+        return cpufreq_register_notifier(&cpufreq_notifier,
+                                                CPUFREQ_TRANSITION_NOTIFIER);
+}
+core_initcall(register_cpufreq_notifier);
+#endif
diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c
index 1794cc3b0f18..358bca3a995e 100644
--- a/arch/arm/kernel/suspend.c
+++ b/arch/arm/kernel/suspend.c
@@ -17,6 +17,8 @@ extern void cpu_resume_mmu(void);
 */
 void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
 {
+        u32 *ctx = ptr;
        *save_ptr = virt_to_phys(ptr);
        /* This must correspond to the LDM in cpu_resume() assembly */
@@ -26,7 +28,20 @@ void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
        cpu_do_suspend(ptr);
-        flush_cache_all();
+        flush_cache_louis();
+        /*
+         * flush_cache_louis does not guarantee that
+         * save_ptr and ptr are cleaned to main memory,
+         * just up to the Level of Unification Inner Shareable.
+         * Since the context pointer and context itself
+         * are to be retrieved with the MMU off that
+         * data must be cleaned from all cache levels
+         * to main memory using "area" cache primitives.
+        */
+        __cpuc_flush_dcache_area(ctx, ptrsz);
+        __cpuc_flush_dcache_area(save_ptr, sizeof(*save_ptr));
        outer_clean_range(*save_ptr, *save_ptr + ptrsz);
        outer_clean_range(virt_to_phys(save_ptr),
                          virt_to_phys(save_ptr) + sizeof(*save_ptr));
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index 76cbb055dd05..c2a898aa57aa 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -59,69 +59,6 @@ asmlinkage int sys_vfork(struct pt_regs *regs)
        return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->ARM_sp, regs, 0, NULL, NULL);
 }
-/* sys_execve() executes a new program.
- * This is called indirectly via a small wrapper
- */
-asmlinkage int sys_execve(const char __user *filenamei,
-                          const char __user *const __user *argv,
-                          const char __user *const __user *envp, struct pt_regs *regs)
-{
-        int error;
-        char * filename;
-        filename = getname(filenamei);
-        error = PTR_ERR(filename);
-        if (IS_ERR(filename))
-                goto out;
-        error = do_execve(filename, argv, envp, regs);
-        putname(filename);
-out:
-        return error;
-}
-int kernel_execve(const char *filename,
-                  const char *const argv[],
-                  const char *const envp[])
-{
-        struct pt_regs regs;
-        int ret;
-        memset(&regs, 0, sizeof(struct pt_regs));
-        ret = do_execve(filename,
-                        (const char __user *const __user *)argv,
-                        (const char __user *const __user *)envp, &regs);
-        if (ret < 0)
-                goto out;
-        /*
-         * Save argc to the register structure for userspace.
-         */
-        regs.ARM_r0 = ret;
-        /*
-         * We were successful.  We won't be returning to our caller, but
-         * instead to user space by manipulating the kernel stack.
-         */
-        asm(    "add    r0, %0, %1\n\t"
-                "mov    r1, %2\n\t"
-                "mov    r2, %3\n\t"
-                "bl     memmove\n\t"    /* copy regs to top of stack */
-                "mov    r8, #0\n\t"     /* not a syscall */
-                "mov    r9, %0\n\t"     /* thread structure */
-                "mov    sp, r0\n\t"     /* reposition stack pointer */
-                "b      ret_to_user"
-                :
-                : "r" (current_thread_info()),
-                  "Ir" (THREAD_START_SP - sizeof(regs)),
-                  "r" (&regs),
-                  "Ir" (sizeof(regs))
-                : "r0", "r1", "r2", "r3", "r8", "r9", "ip", "lr", "memory");
- out:
-        return ret;
-}
-EXPORT_SYMBOL(kernel_execve);
 /*
 * Since loff_t is a 64 bit type we avoid a lot of ABI hassle
 * with a different argument ordering.
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index af2afb019672..09be0c3c9069 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -25,7 +25,6 @@
 #include <linux/timer.h>
 #include <linux/irq.h>
-#include <asm/leds.h>
 #include <asm/thread_info.h>
 #include <asm/sched_clock.h>
 #include <asm/stacktrace.h>
@@ -80,21 +79,6 @@ u32 arch_gettimeoffset(void)
 }
 #endif /* CONFIG_ARCH_USES_GETTIMEOFFSET */
-#ifdef CONFIG_LEDS_TIMER
-static inline void do_leds(void)
-{
-        static unsigned int count = HZ/2;
-        if (--count == 0) {
-                count = HZ/2;
-                leds_event(led_timer);
-        }
-}
-#else
-#define do_leds()
-#endif
 #ifndef CONFIG_GENERIC_CLOCKEVENTS
 /*
 * Kernel system timer support.
@@ -102,7 +86,6 @@ static inline void do_leds(void)
 void timer_tick(void)
 {
        profile_tick(CPU_PROFILING);
-        do_leds();
        xtime_update(1);
 #ifndef CONFIG_SMP
        update_process_times(user_mode(get_irq_regs()));
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index 395d5fbb8fa2..9d0a30032d7f 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -34,7 +34,18 @@ struct arm_delay_ops arm_delay_ops = {
        .udelay         = __loop_udelay,
 };
-#ifdef ARCH_HAS_READ_CURRENT_TIMER
+static const struct delay_timer *delay_timer;
+static bool delay_calibrated;
+int read_current_timer(unsigned long *timer_val)
+{
+        if (!delay_timer)
+                return -ENXIO;
+        *timer_val = delay_timer->read_current_timer();
+        return 0;
+}
 static void __timer_delay(unsigned long cycles)
 {
        cycles_t start = get_cycles();
@@ -55,18 +66,24 @@ static void __timer_udelay(unsigned long usecs)
        __timer_const_udelay(usecs * UDELAY_MULT);
 }
-void __init init_current_timer_delay(unsigned long freq)
+void __init register_current_timer_delay(const struct delay_timer *timer)
 {
-        pr_info("Switching to timer-based delay loop\n");
+        if (!delay_calibrated) {
-        lpj_fine                        = freq / HZ;
+                pr_info("Switching to timer-based delay loop\n");
-        loops_per_jiffy                 = lpj_fine;
+                delay_timer                     = timer;
-        arm_delay_ops.delay             = __timer_delay;
+                lpj_fine                        = timer->freq / HZ;
-        arm_delay_ops.const_udelay      = __timer_const_udelay;
+                loops_per_jiffy                 = lpj_fine;
-        arm_delay_ops.udelay            = __timer_udelay;
+                arm_delay_ops.delay             = __timer_delay;
+                arm_delay_ops.const_udelay      = __timer_const_udelay;
+                arm_delay_ops.udelay            = __timer_udelay;
+                delay_calibrated                = true;
+        } else {
+                pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");
+        }
 }
 unsigned long __cpuinit calibrate_delay_is_known(void)
 {
+        delay_calibrated = true;
        return lpj_fine;
 }
-#endif
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 30bb7332e30b..5309f9b6aabc 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -12,27 +12,3 @@ else
 params_phys-y   := 0x20000100
 initrd_phys-y   := 0x20410000
 endif
-# Keep dtb files sorted alphabetically for each SoC
-# sam9260
-dtb-$(CONFIG_MACH_AT91SAM_DT) += aks-cdu.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += evk-pro3.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb
-# sam9263
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9263ek.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9263.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9263.dtb
-# sam9g20
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek_2mmc.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += kizbox.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9g20.dtb
-dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
-# sam9g45
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
-# sam9n12
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9n12ek.dtb
-# sam9x5
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 6f50c6722276..b4f0565aff63 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -187,6 +187,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
+        CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200", &twi_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
        CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 01fb7325fecc..a563189cdfc3 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -294,9 +294,9 @@ void __init at91_add_device_cf(struct at91_cf_data *data) {}
 *  MMC / SD
 * -------------------------------------------------------------------- */
-#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
 static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct at91_mmc_data mmc_data;
+static struct mci_platform_data mmc_data;
 static struct resource mmc_resources[] = {
        [0] = {
@@ -312,7 +312,7 @@ static struct resource mmc_resources[] = {
 };
 static struct platform_device at91rm9200_mmc_device = {
-        .name           = "at91_mci",
+        .name           = "atmel_mci",
        .id             = -1,
        .dev            = {
                                .dma_mask               = &mmc_dmamask,
@@ -323,53 +323,69 @@ static struct platform_device at91rm9200_mmc_device = {
        .num_resources  = ARRAY_SIZE(mmc_resources),
 };
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 {
+        unsigned int i;
+        unsigned int slot_count = 0;
        if (!data)
                return;
-        /* input/irq */
+        for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
-        if (gpio_is_valid(data->det_pin)) {
-                at91_set_gpio_input(data->det_pin, 1);
-                at91_set_deglitch(data->det_pin, 1);
-        }
-        if (gpio_is_valid(data->wp_pin))
-                at91_set_gpio_input(data->wp_pin, 1);
-        if (gpio_is_valid(data->vcc_pin))
-                at91_set_gpio_output(data->vcc_pin, 0);
-        /* CLK */
-        at91_set_A_periph(AT91_PIN_PA27, 0);
-        if (data->slot_b) {
+                if (!data->slot[i].bus_width)
-                /* CMD */
+                        continue;
-                at91_set_B_periph(AT91_PIN_PA8, 1);
-                /* DAT0, maybe DAT1..DAT3 */
+                /* input/irq */
-                at91_set_B_periph(AT91_PIN_PA9, 1);
+                if (gpio_is_valid(data->slot[i].detect_pin)) {
-                if (data->wire4) {
+                        at91_set_gpio_input(data->slot[i].detect_pin, 1);
-                        at91_set_B_periph(AT91_PIN_PA10, 1);
+                        at91_set_deglitch(data->slot[i].detect_pin, 1);
-                        at91_set_B_periph(AT91_PIN_PA11, 1);
-                        at91_set_B_periph(AT91_PIN_PA12, 1);
                }
-        } else {
+                if (gpio_is_valid(data->slot[i].wp_pin))
-                /* CMD */
+                        at91_set_gpio_input(data->slot[i].wp_pin, 1);
-                at91_set_A_periph(AT91_PIN_PA28, 1);
+                switch (i) {
-                /* DAT0, maybe DAT1..DAT3 */
+                case 0:                                 /* slot A */
-                at91_set_A_periph(AT91_PIN_PA29, 1);
+                        /* CMD */
-                if (data->wire4) {
+                        at91_set_A_periph(AT91_PIN_PA28, 1);
-                        at91_set_B_periph(AT91_PIN_PB3, 1);
+                        /* DAT0, maybe DAT1..DAT3 */
-                        at91_set_B_periph(AT91_PIN_PB4, 1);
+                        at91_set_A_periph(AT91_PIN_PA29, 1);
-                        at91_set_B_periph(AT91_PIN_PB5, 1);
+                        if (data->slot[i].bus_width == 4) {
+                                at91_set_B_periph(AT91_PIN_PB3, 1);
+                                at91_set_B_periph(AT91_PIN_PB4, 1);
+                                at91_set_B_periph(AT91_PIN_PB5, 1);
+                        }
+                        slot_count++;
+                        break;
+                case 1:                                 /* slot B */
+                        /* CMD */
+                        at91_set_B_periph(AT91_PIN_PA8, 1);
+                        /* DAT0, maybe DAT1..DAT3 */
+                        at91_set_B_periph(AT91_PIN_PA9, 1);
+                        if (data->slot[i].bus_width == 4) {
+                                at91_set_B_periph(AT91_PIN_PA10, 1);
+                                at91_set_B_periph(AT91_PIN_PA11, 1);
+                                at91_set_B_periph(AT91_PIN_PA12, 1);
+                        }
+                        slot_count++;
+                        break;
+                default:
+                        printk(KERN_ERR
+                               "AT91: SD/MMC slot %d not available\n", i);
+                        break;
+                }
+                if (slot_count) {
+                        /* CLK */
+                        at91_set_A_periph(AT91_PIN_PA27, 0);
+                        mmc_data = *data;
+                        platform_device_register(&at91rm9200_mmc_device);
                }
        }
-        mmc_data = *data;
-        platform_device_register(&at91rm9200_mmc_device);
 }
 #else
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
 #endif
@@ -495,7 +511,7 @@ static struct resource twi_resources[] = {
 };
 static struct platform_device at91rm9200_twi_device = {
-        .name           = "at91_i2c",
+        .name           = "i2c-at91rm9200",
        .id             = -1,
        .resource       = twi_resources,
        .num_resources  = ARRAY_SIZE(twi_resources),
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 30c7f26a4668..ad29f93f20ca 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -211,6 +211,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
+        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260", &twi_clk),
+        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20", &twi_clk),
        /* more usart lookup table for DT entries */
        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
        CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
@@ -219,6 +221,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
        CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
        CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
        /* more tc lookup table for DT entries */
        CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
        CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index bce572a530ef..a76b8684f52d 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -209,92 +209,10 @@ void __init at91_add_device_eth(struct macb_platform_data *data) {}
 /* --------------------------------------------------------------------
- *  MMC / SD
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
-static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct at91_mmc_data mmc_data;
-static struct resource mmc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_MCI,
-                .end    = AT91SAM9260_BASE_MCI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9260_mmc_device = {
-        .name           = "at91_mci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc_data,
-        },
-        .resource       = mmc_resources,
-        .num_resources  = ARRAY_SIZE(mmc_resources),
-};
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
-{
-        if (!data)
-                return;
-        /* input/irq */
-        if (gpio_is_valid(data->det_pin)) {
-                at91_set_gpio_input(data->det_pin, 1);
-                at91_set_deglitch(data->det_pin, 1);
-        }
-        if (gpio_is_valid(data->wp_pin))
-                at91_set_gpio_input(data->wp_pin, 1);
-        if (gpio_is_valid(data->vcc_pin))
-                at91_set_gpio_output(data->vcc_pin, 0);
-        /* CLK */
-        at91_set_A_periph(AT91_PIN_PA8, 0);
-        if (data->slot_b) {
-                /* CMD */
-                at91_set_B_periph(AT91_PIN_PA1, 1);
-                /* DAT0, maybe DAT1..DAT3 */
-                at91_set_B_periph(AT91_PIN_PA0, 1);
-                if (data->wire4) {
-                        at91_set_B_periph(AT91_PIN_PA5, 1);
-                        at91_set_B_periph(AT91_PIN_PA4, 1);
-                        at91_set_B_periph(AT91_PIN_PA3, 1);
-                }
-        } else {
-                /* CMD */
-                at91_set_A_periph(AT91_PIN_PA7, 1);
-                /* DAT0, maybe DAT1..DAT3 */
-                at91_set_A_periph(AT91_PIN_PA6, 1);
-                if (data->wire4) {
-                        at91_set_A_periph(AT91_PIN_PA9, 1);
-                        at91_set_A_periph(AT91_PIN_PA10, 1);
-                        at91_set_A_periph(AT91_PIN_PA11, 1);
-                }
-        }
-        mmc_data = *data;
-        platform_device_register(&at91sam9260_mmc_device);
-}
-#else
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
-#endif
-/* --------------------------------------------------------------------
 *  MMC / SD Slot for Atmel MCI Driver
 * -------------------------------------------------------------------- */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
 static u64 mmc_dmamask = DMA_BIT_MASK(32);
 static struct mci_platform_data mmc_data;
@@ -503,7 +421,6 @@ static struct resource twi_resources[] = {
 };
 static struct platform_device at91sam9260_twi_device = {
-        .name           = "at91_i2c",
        .id             = -1,
        .resource       = twi_resources,
        .num_resources  = ARRAY_SIZE(twi_resources),
@@ -511,6 +428,13 @@ static struct platform_device at91sam9260_twi_device = {
 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 {
+        /* IP version is not the same on 9260 and g20 */
+        if (cpu_is_at91sam9g20()) {
+                at91sam9260_twi_device.name = "i2c-at91sam9g20";
+        } else {
+                at91sam9260_twi_device.name = "i2c-at91sam9260";
+        }
        /* pins used for TWI interface */
        at91_set_A_periph(AT91_PIN_PA23, 0);            /* TWD */
        at91_set_multi_drive(AT91_PIN_PA23, 1);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index f40762c5fede..8d999eb1a137 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -178,6 +178,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
+        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261", &twi_clk),
+        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10", &twi_clk),
        CLKDEV_CON_ID("pioA", &pioA_clk),
        CLKDEV_CON_ID("pioB", &pioB_clk),
        CLKDEV_CON_ID("pioC", &pioC_clk),
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index bc2590d712d0..9752f17efba9 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -137,9 +137,9 @@ void __init at91_add_device_udc(struct at91_udc_data *data) {}
 *  MMC / SD
 * -------------------------------------------------------------------- */
-#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
 static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct at91_mmc_data mmc_data;
+static struct mci_platform_data mmc_data;
 static struct resource mmc_resources[] = {
        [0] = {
@@ -155,7 +155,7 @@ static struct resource mmc_resources[] = {
 };
 static struct platform_device at91sam9261_mmc_device = {
-        .name           = "at91_mci",
+        .name           = "atmel_mci",
        .id             = -1,
        .dev            = {
                                .dma_mask               = &mmc_dmamask,
@@ -166,40 +166,40 @@ static struct platform_device at91sam9261_mmc_device = {
        .num_resources  = ARRAY_SIZE(mmc_resources),
 };
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 {
        if (!data)
                return;
-        /* input/irq */
+        if (data->slot[0].bus_width) {
-        if (gpio_is_valid(data->det_pin)) {
+                /* input/irq */
-                at91_set_gpio_input(data->det_pin, 1);
+                if (gpio_is_valid(data->slot[0].detect_pin)) {
-                at91_set_deglitch(data->det_pin, 1);
+                        at91_set_gpio_input(data->slot[0].detect_pin, 1);
-        }
+                        at91_set_deglitch(data->slot[0].detect_pin, 1);
-        if (gpio_is_valid(data->wp_pin))
+                }
-                at91_set_gpio_input(data->wp_pin, 1);
+                if (gpio_is_valid(data->slot[0].wp_pin))
-        if (gpio_is_valid(data->vcc_pin))
+                        at91_set_gpio_input(data->slot[0].wp_pin, 1);
-                at91_set_gpio_output(data->vcc_pin, 0);
+                /* CLK */
-        /* CLK */
+                at91_set_B_periph(AT91_PIN_PA2, 0);
-        at91_set_B_periph(AT91_PIN_PA2, 0);
+                /* CMD */
-        /* CMD */
+                at91_set_B_periph(AT91_PIN_PA1, 1);
-        at91_set_B_periph(AT91_PIN_PA1, 1);
+                /* DAT0, maybe DAT1..DAT3 */
-        /* DAT0, maybe DAT1..DAT3 */
+                at91_set_B_periph(AT91_PIN_PA0, 1);
-        at91_set_B_periph(AT91_PIN_PA0, 1);
+                if (data->slot[0].bus_width == 4) {
-        if (data->wire4) {
+                        at91_set_B_periph(AT91_PIN_PA4, 1);
-                at91_set_B_periph(AT91_PIN_PA4, 1);
+                        at91_set_B_periph(AT91_PIN_PA5, 1);
-                at91_set_B_periph(AT91_PIN_PA5, 1);
+                        at91_set_B_periph(AT91_PIN_PA6, 1);
-                at91_set_B_periph(AT91_PIN_PA6, 1);
+                }
-        }
-        mmc_data = *data;
+                mmc_data = *data;
-        platform_device_register(&at91sam9261_mmc_device);
+                platform_device_register(&at91sam9261_mmc_device);
+        }
 }
 #else
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
 #endif
@@ -317,7 +317,6 @@ static struct resource twi_resources[] = {
 };
 static struct platform_device at91sam9261_twi_device = {
-        .name           = "at91_i2c",
        .id             = -1,
        .resource       = twi_resources,
        .num_resources  = ARRAY_SIZE(twi_resources),
@@ -325,12 +324,19 @@ static struct platform_device at91sam9261_twi_device = {
 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 {
+        /* IP version is not the same on 9261 and g10 */
+        if (cpu_is_at91sam9g10()) {
+                at91sam9261_twi_device.name = "i2c-at91sam9g10";
+                /* I2C PIO must not be configured as open-drain on this chip */
+        } else {
+                at91sam9261_twi_device.name = "i2c-at91sam9261";
+                at91_set_multi_drive(AT91_PIN_PA7, 1);
+                at91_set_multi_drive(AT91_PIN_PA8, 1);
+        }
        /* pins used for TWI interface */
        at91_set_A_periph(AT91_PIN_PA7, 0);             /* TWD */
-        at91_set_multi_drive(AT91_PIN_PA7, 1);
        at91_set_A_periph(AT91_PIN_PA8, 0);             /* TWCK */
-        at91_set_multi_drive(AT91_PIN_PA8, 1);
        i2c_register_board_info(0, devices, nr_devices);
        platform_device_register(&at91sam9261_twi_device);
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 84b38105231e..6a01d0360dfb 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -188,11 +188,12 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_ID("hclk", &macb_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
+        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260", &twi_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
        CLKDEV_CON_ID("pioA", &pioA_clk),
@@ -210,6 +211,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
        CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
        CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 9b6ca734f1a9..8dde220b42b6 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -218,9 +218,9 @@ void __init at91_add_device_eth(struct macb_platform_data *data) {}
 *  MMC / SD
 * -------------------------------------------------------------------- */
-#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
 static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct at91_mmc_data mmc0_data, mmc1_data;
+static struct mci_platform_data mmc0_data, mmc1_data;
 static struct resource mmc0_resources[] = {
        [0] = {
@@ -236,7 +236,7 @@ static struct resource mmc0_resources[] = {
 };
 static struct platform_device at91sam9263_mmc0_device = {
-        .name           = "at91_mci",
+        .name           = "atmel_mci",
        .id             = 0,
        .dev            = {
                                .dma_mask               = &mmc_dmamask,
@@ -261,7 +261,7 @@ static struct resource mmc1_resources[] = {
 };
 static struct platform_device at91sam9263_mmc1_device = {
-        .name           = "at91_mci",
+        .name           = "atmel_mci",
        .id             = 1,
        .dev            = {
                                .dma_mask               = &mmc_dmamask,
@@ -272,85 +272,110 @@ static struct platform_device at91sam9263_mmc1_device = {
        .num_resources  = ARRAY_SIZE(mmc1_resources),
 };
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 {
+        unsigned int i;
+        unsigned int slot_count = 0;
        if (!data)
                return;
-        /* input/irq */
+        for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
-        if (gpio_is_valid(data->det_pin)) {
-                at91_set_gpio_input(data->det_pin, 1);
-                at91_set_deglitch(data->det_pin, 1);
-        }
-        if (gpio_is_valid(data->wp_pin))
-                at91_set_gpio_input(data->wp_pin, 1);
-        if (gpio_is_valid(data->vcc_pin))
-                at91_set_gpio_output(data->vcc_pin, 0);
-        if (mmc_id == 0) {              /* MCI0 */
+                if (!data->slot[i].bus_width)
-                /* CLK */
+                        continue;
-                at91_set_A_periph(AT91_PIN_PA12, 0);
-                if (data->slot_b) {
+                /* input/irq */
-                        /* CMD */
+                if (gpio_is_valid(data->slot[i].detect_pin)) {
-                        at91_set_A_periph(AT91_PIN_PA16, 1);
+                        at91_set_gpio_input(data->slot[i].detect_pin,
+                                        1);
+                        at91_set_deglitch(data->slot[i].detect_pin,
+                                        1);
+                }
+                if (gpio_is_valid(data->slot[i].wp_pin))
+                        at91_set_gpio_input(data->slot[i].wp_pin, 1);
+                if (mmc_id == 0) {                              /* MCI0 */
+                        switch (i) {
+                        case 0:                                 /* slot A */
+                                /* CMD */
+                                at91_set_A_periph(AT91_PIN_PA1, 1);
+                                /* DAT0, maybe DAT1..DAT3 */
+                                at91_set_A_periph(AT91_PIN_PA0, 1);
+                                if (data->slot[i].bus_width == 4) {
+                                        at91_set_A_periph(AT91_PIN_PA3, 1);
+                                        at91_set_A_periph(AT91_PIN_PA4, 1);
+                                        at91_set_A_periph(AT91_PIN_PA5, 1);
+                                }
+                                slot_count++;
+                                break;
+                        case 1:                                 /* slot B */
+                                /* CMD */
+                                at91_set_A_periph(AT91_PIN_PA16, 1);
+                                /* DAT0, maybe DAT1..DAT3 */
+                                at91_set_A_periph(AT91_PIN_PA17, 1);
+                                if (data->slot[i].bus_width == 4) {
+                                        at91_set_A_periph(AT91_PIN_PA18, 1);
+                                        at91_set_A_periph(AT91_PIN_PA19, 1);
+                                        at91_set_A_periph(AT91_PIN_PA20, 1);
+                                }
+                                slot_count++;
+                                break;
+                        default:
+                                printk(KERN_ERR
+                                       "AT91: SD/MMC slot %d not available\n", i);
+                                break;
+                        }
+                        if (slot_count) {
+                                /* CLK */
+                                at91_set_A_periph(AT91_PIN_PA12, 0);
-                        /* DAT0, maybe DAT1..DAT3 */
+                                mmc0_data = *data;
-                        at91_set_A_periph(AT91_PIN_PA17, 1);
+                                platform_device_register(&at91sam9263_mmc0_device);
-                        if (data->wire4) {
-                                at91_set_A_periph(AT91_PIN_PA18, 1);
-                                at91_set_A_periph(AT91_PIN_PA19, 1);
-                                at91_set_A_periph(AT91_PIN_PA20, 1);
                        }
-                } else {
+                } else if (mmc_id == 1) {                       /* MCI1 */
-                        /* CMD */
+                        switch (i) {
-                        at91_set_A_periph(AT91_PIN_PA1, 1);
+                        case 0:                                 /* slot A */
+                                /* CMD */
-                        /* DAT0, maybe DAT1..DAT3 */
+                                at91_set_A_periph(AT91_PIN_PA7, 1);
-                        at91_set_A_periph(AT91_PIN_PA0, 1);
+                                /* DAT0, maybe DAT1..DAT3 */
-                        if (data->wire4) {
+                                at91_set_A_periph(AT91_PIN_PA8, 1);
-                                at91_set_A_periph(AT91_PIN_PA3, 1);
+                                if (data->slot[i].bus_width == 4) {
-                                at91_set_A_periph(AT91_PIN_PA4, 1);
+                                        at91_set_A_periph(AT91_PIN_PA9, 1);
-                                at91_set_A_periph(AT91_PIN_PA5, 1);
+                                        at91_set_A_periph(AT91_PIN_PA10, 1);
+                                        at91_set_A_periph(AT91_PIN_PA11, 1);
+                                }
+                                slot_count++;
+                                break;
+                        case 1:                                 /* slot B */
+                                /* CMD */
+                                at91_set_A_periph(AT91_PIN_PA21, 1);
+                                /* DAT0, maybe DAT1..DAT3 */
+                                at91_set_A_periph(AT91_PIN_PA22, 1);
+                                if (data->slot[i].bus_width == 4) {
+                                        at91_set_A_periph(AT91_PIN_PA23, 1);
+                                        at91_set_A_periph(AT91_PIN_PA24, 1);
+                                        at91_set_A_periph(AT91_PIN_PA25, 1);
+                                }
+                                slot_count++;
+                                break;
+                        default:
+                                printk(KERN_ERR
+                                       "AT91: SD/MMC slot %d not available\n", i);
+                                break;
                        }
-                }
+                        if (slot_count) {
+                                /* CLK */
+                                at91_set_A_periph(AT91_PIN_PA6, 0);
-                mmc0_data = *data;
+                                mmc1_data = *data;
-                platform_device_register(&at91sam9263_mmc0_device);
+                                platform_device_register(&at91sam9263_mmc1_device);
-        } else {                        /* MCI1 */
-                /* CLK */
-                at91_set_A_periph(AT91_PIN_PA6, 0);
-                if (data->slot_b) {
-                        /* CMD */
-                        at91_set_A_periph(AT91_PIN_PA21, 1);
-                        /* DAT0, maybe DAT1..DAT3 */
-                        at91_set_A_periph(AT91_PIN_PA22, 1);
-                        if (data->wire4) {
-                                at91_set_A_periph(AT91_PIN_PA23, 1);
-                                at91_set_A_periph(AT91_PIN_PA24, 1);
-                                at91_set_A_periph(AT91_PIN_PA25, 1);
-                        }
-                } else {
-                        /* CMD */
-                        at91_set_A_periph(AT91_PIN_PA7, 1);
-                        /* DAT0, maybe DAT1..DAT3 */
-                        at91_set_A_periph(AT91_PIN_PA8, 1);
-                        if (data->wire4) {
-                                at91_set_A_periph(AT91_PIN_PA9, 1);
-                                at91_set_A_periph(AT91_PIN_PA10, 1);
-                                at91_set_A_periph(AT91_PIN_PA11, 1);
                        }
                }
-                mmc1_data = *data;
-                platform_device_register(&at91sam9263_mmc1_device);
        }
 }
 #else
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
 #endif
 /* --------------------------------------------------------------------
@@ -574,7 +599,7 @@ static struct resource twi_resources[] = {
 };
 static struct platform_device at91sam9263_twi_device = {
-        .name           = "at91_i2c",
+        .name           = "i2c-at91sam9260",
        .id             = -1,
        .resource       = twi_resources,
        .num_resources  = ARRAY_SIZE(twi_resources),
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index ef6cedd52e3c..84af1b506d92 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -237,6 +237,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
+        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
+        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
        CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
@@ -254,6 +256,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
        CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
        CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
        CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 1b47319ca00b..b1596072dcc2 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -31,7 +31,7 @@
 #include <mach/at91sam9g45_matrix.h>
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
-#include <mach/at_hdmac.h>
+#include <linux/platform_data/dma-atmel.h>
 #include <mach/atmel-mci.h>
 #include <media/atmel-isi.h>
@@ -653,7 +653,7 @@ static struct resource twi0_resources[] = {
 };
 static struct platform_device at91sam9g45_twi0_device = {
-        .name           = "at91_i2c",
+        .name           = "i2c-at91sam9g10",
        .id             = 0,
        .resource       = twi0_resources,
        .num_resources  = ARRAY_SIZE(twi0_resources),
@@ -673,7 +673,7 @@ static struct resource twi1_resources[] = {
 };
 static struct platform_device at91sam9g45_twi1_device = {
-        .name           = "at91_i2c",
+        .name           = "i2c-at91sam9g10",
        .id             = 1,
        .resource       = twi1_resources,
        .num_resources  = ARRAY_SIZE(twi1_resources),
@@ -686,18 +686,12 @@ void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, in
        /* pins used for TWI interface */
        if (i2c_id == 0) {
                at91_set_A_periph(AT91_PIN_PA20, 0);            /* TWD */
-                at91_set_multi_drive(AT91_PIN_PA20, 1);
                at91_set_A_periph(AT91_PIN_PA21, 0);            /* TWCK */
-                at91_set_multi_drive(AT91_PIN_PA21, 1);
                platform_device_register(&at91sam9g45_twi0_device);
        } else {
                at91_set_A_periph(AT91_PIN_PB10, 0);            /* TWD */
-                at91_set_multi_drive(AT91_PIN_PB10, 1);
                at91_set_A_periph(AT91_PIN_PB11, 0);            /* TWCK */
-                at91_set_multi_drive(AT91_PIN_PB11, 1);
                platform_device_register(&at91sam9g45_twi1_device);
        }
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 08494664ab78..732d3d3f4ec5 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -169,6 +169,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
        CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
        CLKDEV_CON_ID("pioA", &pioAB_clk),
        CLKDEV_CON_ID("pioB", &pioAB_clk),
        CLKDEV_CON_ID("pioC", &pioCD_clk),
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 72ce50a50de5..72e908412222 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -186,6 +186,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
+        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
        CLKDEV_CON_ID("pioA", &pioA_clk),
        CLKDEV_CON_ID("pioB", &pioB_clk),
        CLKDEV_CON_ID("pioC", &pioC_clk),
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index b3d365dadef5..d6ca0543ce8d 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -22,7 +22,7 @@
 #include <mach/at91sam9rl_matrix.h>
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
-#include <mach/at_hdmac.h>
+#include <linux/platform_data/dma-atmel.h>
 #include "generic.h"
@@ -161,9 +161,9 @@ void __init at91_add_device_usba(struct usba_platform_data *data) {}
 *  MMC / SD
 * -------------------------------------------------------------------- */
-#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
 static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct at91_mmc_data mmc_data;
+static struct mci_platform_data mmc_data;
 static struct resource mmc_resources[] = {
        [0] = {
@@ -179,7 +179,7 @@ static struct resource mmc_resources[] = {
 };
 static struct platform_device at91sam9rl_mmc_device = {
-        .name           = "at91_mci",
+        .name           = "atmel_mci",
        .id             = -1,
        .dev            = {
                                .dma_mask               = &mmc_dmamask,
@@ -190,40 +190,40 @@ static struct platform_device at91sam9rl_mmc_device = {
        .num_resources  = ARRAY_SIZE(mmc_resources),
 };
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 {
        if (!data)
                return;
-        /* input/irq */
+        if (data->slot[0].bus_width) {
-        if (gpio_is_valid(data->det_pin)) {
+                /* input/irq */
-                at91_set_gpio_input(data->det_pin, 1);
+                if (gpio_is_valid(data->slot[0].detect_pin)) {
-                at91_set_deglitch(data->det_pin, 1);
+                        at91_set_gpio_input(data->slot[0].detect_pin, 1);
-        }
+                        at91_set_deglitch(data->slot[0].detect_pin, 1);
-        if (gpio_is_valid(data->wp_pin))
+                }
-                at91_set_gpio_input(data->wp_pin, 1);
+                if (gpio_is_valid(data->slot[0].wp_pin))
-        if (gpio_is_valid(data->vcc_pin))
+                        at91_set_gpio_input(data->slot[0].wp_pin, 1);
-                at91_set_gpio_output(data->vcc_pin, 0);
+                /* CLK */
-        /* CLK */
+                at91_set_A_periph(AT91_PIN_PA2, 0);
-        at91_set_A_periph(AT91_PIN_PA2, 0);
+                /* CMD */
-        /* CMD */
+                at91_set_A_periph(AT91_PIN_PA1, 1);
-        at91_set_A_periph(AT91_PIN_PA1, 1);
+                /* DAT0, maybe DAT1..DAT3 */
-        /* DAT0, maybe DAT1..DAT3 */
+                at91_set_A_periph(AT91_PIN_PA0, 1);
-        at91_set_A_periph(AT91_PIN_PA0, 1);
+                if (data->slot[0].bus_width == 4) {
-        if (data->wire4) {
+                        at91_set_A_periph(AT91_PIN_PA3, 1);
-                at91_set_A_periph(AT91_PIN_PA3, 1);
+                        at91_set_A_periph(AT91_PIN_PA4, 1);
-                at91_set_A_periph(AT91_PIN_PA4, 1);
+                        at91_set_A_periph(AT91_PIN_PA5, 1);
-                at91_set_A_periph(AT91_PIN_PA5, 1);
+                }
+                mmc_data = *data;
+                platform_device_register(&at91sam9rl_mmc_device);
        }
-        mmc_data = *data;
-        platform_device_register(&at91sam9rl_mmc_device);
 }
 #else
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
 #endif
@@ -346,7 +346,7 @@ static struct resource twi_resources[] = {
 };
 static struct platform_device at91sam9rl_twi_device = {
-        .name           = "at91_i2c",
+        .name           = "i2c-at91sam9g20",
        .id             = -1,
        .resource       = twi_resources,
        .num_resources  = ARRAY_SIZE(twi_resources),
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 477cf9d06672..e5035380dcbc 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -231,6 +231,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
        CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
        CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
        CLKDEV_CON_ID("pioA", &pioAB_clk),
        CLKDEV_CON_ID("pioB", &pioAB_clk),
        CLKDEV_CON_ID("pioC", &pioCD_clk),
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 46090e642d8e..6bd7300a2bc5 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -47,7 +47,7 @@ static void at91x40_idle(void)
         * Disable the processor clock.  The processor will be automatically
         * re-enabled by an interrupt or by a reset.
         */
-        __raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
+        __raw_writel(AT91_PS_CR_CPU, AT91_IO_P2V(AT91_PS_CR));
        cpu_do_idle();
 }
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index 6ca680a1d5d1..ee06d7bcdf76 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -29,10 +29,10 @@
 #include <mach/at91_tc.h>
 #define at91_tc_read(field) \
-        __raw_readl(AT91_TC + field)
+        __raw_readl(AT91_IO_P2V(AT91_TC) + field)
 #define at91_tc_write(field, value) \
-        __raw_writel(value, AT91_TC + field);
+        __raw_writel(value, AT91_IO_P2V(AT91_TC) + field);
 /*
 *      3 counter/timer units present.
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index de7be1931817..93a832f70232 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -133,12 +133,12 @@ static struct atmel_nand_data __initdata afeb9260_nand_data = {
 /*
 * MCI (SD/MMC)
 */
-static struct at91_mmc_data __initdata afeb9260_mmc_data = {
+static struct mci_platform_data __initdata afeb9260_mci0_data = {
-        .det_pin        = AT91_PIN_PC9,
+        .slot[1] = {
-        .wp_pin         = AT91_PIN_PC4,
+                .bus_width      = 4,
-        .slot_b         = 1,
+                .detect_pin     = AT91_PIN_PC9,
-        .wire4          = 1,
+                .wp_pin         = AT91_PIN_PC4,
-        .vcc_pin        = -EINVAL,
+        },
 };
@@ -199,7 +199,7 @@ static void __init afeb9260_board_init(void)
        at91_set_B_periph(AT91_PIN_PA10, 0);    /* ETX2 */
        at91_set_B_periph(AT91_PIN_PA11, 0);    /* ETX3 */
        /* MMC */
-        at91_add_device_mmc(0, &afeb9260_mmc_data);
+        at91_add_device_mci(0, &afeb9260_mci0_data);
        /* I2C */
        at91_add_device_i2c(afeb9260_i2c_devices,
                        ARRAY_SIZE(afeb9260_i2c_devices));
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index a5b002f32a61..71d8f362a1d5 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -71,12 +71,12 @@ static struct at91_udc_data __initdata carmeva_udc_data = {
        // .vcc_pin     = -EINVAL,
 // };
-static struct at91_mmc_data __initdata carmeva_mmc_data = {
+static struct mci_platform_data __initdata carmeva_mci0_data = {
-        .slot_b         = 0,
+        .slot[0] = {
-        .wire4          = 1,
+                .bus_width      = 4,
-        .det_pin        = AT91_PIN_PB10,
+                .detect_pin     = AT91_PIN_PB10,
-        .wp_pin         = AT91_PIN_PC14,
+                .wp_pin         = AT91_PIN_PC14,
-        .vcc_pin        = -EINVAL,
+        },
 };
 static struct spi_board_info carmeva_spi_devices[] = {
@@ -150,7 +150,7 @@ static void __init carmeva_board_init(void)
        /* Compact Flash */
 //      at91_add_device_cf(&carmeva_cf_data);
        /* MMC */
-        at91_add_device_mmc(0, &carmeva_mmc_data);
+        at91_add_device_mci(0, &carmeva_mci0_data);
        /* LEDs */
        at91_gpio_leds(carmeva_leds, ARRAY_SIZE(carmeva_leds));
 }
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index ecbc13b594de..e71c473316e3 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -254,8 +254,7 @@ static struct gpio_led cpu9krea_leds[] = {
 static struct i2c_board_info __initdata cpu9krea_i2c_devices[] = {
        {
-                I2C_BOARD_INFO("rtc-ds1307", 0x68),
+                I2C_BOARD_INFO("ds1339", 0x68),
-                .type   = "ds1339",
        },
 };
@@ -312,12 +311,12 @@ static void __init cpu9krea_add_device_buttons(void)
 /*
 * MCI (SD/MMC)
 */
-static struct at91_mmc_data __initdata cpu9krea_mmc_data = {
+static struct mci_platform_data __initdata cpu9krea_mci0_data = {
-        .slot_b         = 0,
+        .slot[0] = {
-        .wire4          = 1,
+                .bus_width      = 4,
-        .det_pin        = AT91_PIN_PA29,
+                .detect_pin     = AT91_PIN_PA29,
-        .wp_pin         = -EINVAL,
+                .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+        },
 };
 static void __init cpu9krea_board_init(void)
@@ -359,7 +358,7 @@ static void __init cpu9krea_board_init(void)
        /* Ethernet */
        at91_add_device_eth(&cpu9krea_macb_data);
        /* MMC */
-        at91_add_device_mmc(0, &cpu9krea_mmc_data);
+        at91_add_device_mci(0, &cpu9krea_mci0_data);
        /* I2C */
        at91_add_device_i2c(cpu9krea_i2c_devices,
                ARRAY_SIZE(cpu9krea_i2c_devices));
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 2e6d043c82f2..2cbd1a2b6c35 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -78,11 +78,12 @@ static struct at91_udc_data __initdata cpuat91_udc_data = {
        .pullup_pin     = AT91_PIN_PC14,
 };
-static struct at91_mmc_data __initdata cpuat91_mmc_data = {
+static struct mci_platform_data __initdata cpuat91_mci0_data = {
-        .det_pin        = AT91_PIN_PC2,
+        .slot[0] = {
-        .wire4          = 1,
+                .bus_width      = 4,
-        .wp_pin         = -EINVAL,
+                .detect_pin     = AT91_PIN_PC2,
-        .vcc_pin        = -EINVAL,
+                .wp_pin         = -EINVAL,
+        },
 };
 static struct physmap_flash_data cpuat91_flash_data = {
@@ -168,7 +169,7 @@ static void __init cpuat91_board_init(void)
        /* USB Device */
        at91_add_device_udc(&cpuat91_udc_data);
        /* MMC */
-        at91_add_device_mmc(0, &cpuat91_mmc_data);
+        at91_add_device_mci(0, &cpuat91_mci0_data);
        /* I2C */
        at91_add_device_i2c(NULL, 0);
        /* Platform devices */
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 462bc319cbc5..3e37437a7a61 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -87,12 +87,12 @@ static struct at91_cf_data __initdata csb337_cf_data = {
        .rst_pin        = AT91_PIN_PD2,
 };
-static struct at91_mmc_data __initdata csb337_mmc_data = {
+static struct mci_platform_data __initdata csb337_mci0_data = {
-        .det_pin        = AT91_PIN_PD5,
+        .slot[0] = {
-        .slot_b         = 0,
+                .bus_width      = 4,
-        .wire4          = 1,
+                .detect_pin     = AT91_PIN_PD5,
-        .wp_pin         = AT91_PIN_PD6,
+                .wp_pin         = AT91_PIN_PD6,
-        .vcc_pin        = -EINVAL,
+        },
 };
 static struct spi_board_info csb337_spi_devices[] = {
@@ -220,8 +220,6 @@ static struct gpio_led csb_leds[] = {
 static void __init csb337_board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
        /* Serial */
        /* DBGU on ttyS0 */
        at91_register_uart(0, 0, 0);
@@ -240,7 +238,7 @@ static void __init csb337_board_init(void)
        /* SPI */
        at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices));
        /* MMC */
-        at91_add_device_mmc(0, &csb337_mmc_data);
+        at91_add_device_mci(0, &csb337_mci0_data);
        /* NOR flash */
        platform_device_register(&csb_flash);
        /* LEDs */
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index d1e1f3fc0a47..0cfac16ee9d5 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -70,12 +70,12 @@ static struct at91_cf_data __initdata eb9200_cf_data = {
        .rst_pin        = AT91_PIN_PC5,
 };
-static struct at91_mmc_data __initdata eb9200_mmc_data = {
+static struct mci_platform_data __initdata eb9200_mci0_data = {
-        .slot_b         = 0,
+        .slot[0] = {
-        .wire4          = 1,
+                .bus_width      = 4,
-        .det_pin        = -EINVAL,
+                .detect_pin     = -EINVAL,
-        .wp_pin         = -EINVAL,
+                .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+        },
 };
 static struct i2c_board_info __initdata eb9200_i2c_devices[] = {
@@ -113,7 +113,7 @@ static void __init eb9200_board_init(void)
        at91_add_device_spi(NULL, 0);
        /* MMC */
        /* only supports 1 or 4 bit interface, not wired through to SPI */
-        at91_add_device_mmc(0, &eb9200_mmc_data);
+        at91_add_device_mci(0, &eb9200_mci0_data);
 }
 MACHINE_START(ATEB9200, "Embest ATEB9200")
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 9c24cb25707c..3d931ffac4bf 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -64,12 +64,12 @@ static struct at91_usbh_data __initdata ecb_at91usbh_data = {
        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
-static struct at91_mmc_data __initdata ecb_at91mmc_data = {
+static struct mci_platform_data __initdata ecbat91_mci0_data = {
-        .slot_b         = 0,
+        .slot[0] = {
-        .wire4          = 1,
+                .bus_width      = 4,
-        .det_pin        = -EINVAL,
+                .detect_pin     = -EINVAL,
-        .wp_pin         = -EINVAL,
+                .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+        },
 };
@@ -138,11 +138,20 @@ static struct spi_board_info __initdata ecb_at91spi_devices[] = {
        },
 };
+/*
+ * LEDs
+ */
+static struct gpio_led ecb_leds[] = {
+        {       /* D1 */
+                .name                   = "led1",
+                .gpio                   = AT91_PIN_PC7,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        }
+};
 static void __init ecb_at91board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
        /* Serial */
        /* DBGU on ttyS0. (Rx & Tx only) */
        at91_register_uart(0, 0, 0);
@@ -161,10 +170,13 @@ static void __init ecb_at91board_init(void)
        at91_add_device_i2c(NULL, 0);
        /* MMC */
-        at91_add_device_mmc(0, &ecb_at91mmc_data);
+        at91_add_device_mci(0, &ecbat91_mci0_data);
        /* SPI */
        at91_add_device_spi(ecb_at91spi_devices, ARRAY_SIZE(ecb_at91spi_devices));
+        /* LEDs */
+        at91_gpio_leds(ecb_leds, ARRAY_SIZE(ecb_leds));
 }
 MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 82bdfde3405f..d93658a2b128 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -56,12 +56,12 @@ static struct at91_udc_data __initdata eco920_udc_data = {
        .pullup_pin     = AT91_PIN_PB13,
 };
-static struct at91_mmc_data __initdata eco920_mmc_data = {
+static struct mci_platform_data __initdata eco920_mci0_data = {
-        .slot_b         = 0,
+        .slot[0] = {
-        .wire4          = 0,
+                .bus_width      = 1,
-        .det_pin        = -EINVAL,
+                .detect_pin     = -EINVAL,
-        .wp_pin         = -EINVAL,
+                .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+        },
 };
 static struct physmap_flash_data eco920_flash_data = {
@@ -93,10 +93,26 @@ static struct spi_board_info eco920_spi_devices[] = {
        },
 };
+/*
+ * LEDs
+ */
+static struct gpio_led eco920_leds[] = {
+        {       /* D1 */
+                .name                   = "led1",
+                .gpio                   = AT91_PIN_PB0,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+        {       /* D2 */
+                .name                   = "led2",
+                .gpio                   = AT91_PIN_PB1,
+                .active_low             = 1,
+                .default_trigger        = "timer",
+        }
+};
 static void __init eco920_board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
        /* DBGU on ttyS0. (Rx & Tx only */
        at91_register_uart(0, 0, 0);
        at91_add_device_serial();
@@ -104,7 +120,7 @@ static void __init eco920_board_init(void)
        at91_add_device_usbh(&eco920_usbh_data);
        at91_add_device_udc(&eco920_udc_data);
-        at91_add_device_mmc(0, &eco920_mmc_data);
+        at91_add_device_mci(0, &eco920_mci0_data);
        platform_device_register(&eco920_flash);
        at91_ramc_write(0, AT91_SMC_CSR(7),     AT91_SMC_RWHOLD_(1)
@@ -127,6 +143,8 @@ static void __init eco920_board_init(void)
        );
        at91_add_device_spi(eco920_spi_devices, ARRAY_SIZE(eco920_spi_devices));
+        /* LEDs */
+        at91_gpio_leds(eco920_leds, ARRAY_SIZE(eco920_leds));
 }
 MACHINE_START(ECO920, "eco920")
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 6cc83a87d77c..fa98abacb1ba 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -75,12 +75,12 @@ static struct spi_board_info flexibity_spi_devices[] = {
 };
 /* MCI (SD/MMC) */
-static struct at91_mmc_data __initdata flexibity_mmc_data = {
+static struct mci_platform_data __initdata flexibity_mci0_data = {
-        .slot_b         = 0,
+        .slot[0] = {
-        .wire4          = 1,
+                .bus_width      = 4,
-        .det_pin        = AT91_PIN_PC9,
+                .detect_pin     = AT91_PIN_PC9,
-        .wp_pin         = AT91_PIN_PC4,
+                .wp_pin         = AT91_PIN_PC4,
-        .vcc_pin        = -EINVAL,
+        },
 };
 /* LEDs */
@@ -152,7 +152,7 @@ static void __init flexibity_board_init(void)
        at91_add_device_spi(flexibity_spi_devices,
                ARRAY_SIZE(flexibity_spi_devices));
        /* MMC */
-        at91_add_device_mmc(0, &flexibity_mmc_data);
+        at91_add_device_mci(0, &flexibity_mci0_data);
        /* LEDs */
        at91_gpio_leds(flexibity_leds, ARRAY_SIZE(flexibity_leds));
 }
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index 69ab1247ef81..6e47071d8206 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -86,7 +86,7 @@ static struct at91_udc_data __initdata foxg20_udc_data = {
 * SPI devices.
 */
 static struct spi_board_info foxg20_spi_devices[] = {
-#if !defined(CONFIG_MMC_AT91)
+#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
        {
                .modalias       = "mtd_dataflash",
                .chip_select    = 1,
@@ -109,12 +109,12 @@ static struct macb_platform_data __initdata foxg20_macb_data = {
 * MCI (SD/MMC)
 * det_pin, wp_pin and vcc_pin are not connected
 */
-static struct at91_mmc_data __initdata foxg20_mmc_data = {
+static struct mci_platform_data __initdata foxg20_mci0_data = {
-        .slot_b         = 1,
+        .slot[1] = {
-        .wire4          = 1,
+                .bus_width      = 4,
-        .det_pin        = -EINVAL,
+                .detect_pin     = -EINVAL,
-        .wp_pin         = -EINVAL,
+                .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+        },
 };
@@ -247,7 +247,7 @@ static void __init foxg20_board_init(void)
        /* Ethernet */
        at91_add_device_eth(&foxg20_macb_data);
        /* MMC */
-        at91_add_device_mmc(0, &foxg20_mmc_data);
+        at91_add_device_mci(0, &foxg20_mci0_data);
        /* I2C */
        at91_add_device_i2c(foxg20_i2c_devices, ARRAY_SIZE(foxg20_i2c_devices));
        /* LEDs */
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 64c1dbf88a07..86050da3ba53 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -66,11 +66,20 @@ static struct at91_udc_data __initdata kafa_udc_data = {
        .pullup_pin     = AT91_PIN_PB7,
 };
+/*
+ * LEDs
+ */
+static struct gpio_led kafa_leds[] = {
+        {       /* D1 */
+                .name                   = "led1",
+                .gpio                   = AT91_PIN_PB4,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+};
 static void __init kafa_board_init(void)
 {
-        /* Set up the LEDs */
-        at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4);
        /* Serial */
        /* DBGU on ttyS0. (Rx & Tx only) */
        at91_register_uart(0, 0, 0);
@@ -88,6 +97,8 @@ static void __init kafa_board_init(void)
        at91_add_device_i2c(NULL, 0);
        /* SPI */
        at91_add_device_spi(NULL, 0);
+        /* LEDs */
+        at91_gpio_leds(kafa_leds, ARRAY_SIZE(kafa_leds));
 }
 MACHINE_START(KAFA, "Sperry-Sun KAFA")
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 5d96cb85175f..abe9fed7a3e0 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -69,12 +69,12 @@ static struct at91_udc_data __initdata kb9202_udc_data = {
        .pullup_pin     = AT91_PIN_PB22,
 };
-static struct at91_mmc_data __initdata kb9202_mmc_data = {
+static struct mci_platform_data __initdata kb9202_mci0_data = {
-        .det_pin        = AT91_PIN_PB2,
+        .slot[0] = {
-        .slot_b         = 0,
+                .bus_width      = 4,
-        .wire4          = 1,
+                .detect_pin     = AT91_PIN_PB2,
-        .wp_pin         = -EINVAL,
+                .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+        },
 };
 static struct mtd_partition __initdata kb9202_nand_partition[] = {
@@ -96,11 +96,26 @@ static struct atmel_nand_data __initdata kb9202_nand_data = {
        .num_parts      = ARRAY_SIZE(kb9202_nand_partition),
 };
+/*
+ * LEDs
+ */
+static struct gpio_led kb9202_leds[] = {
+        {       /* D1 */
+                .name                   = "led1",
+                .gpio                   = AT91_PIN_PC19,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+        {       /* D2 */
+                .name                   = "led2",
+                .gpio                   = AT91_PIN_PC18,
+                .active_low             = 1,
+                .default_trigger        = "timer",
+        }
+};
 static void __init kb9202_board_init(void)
 {
-        /* Set up the LEDs */
-        at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
        /* Serial */
        /* DBGU on ttyS0. (Rx & Tx only) */
        at91_register_uart(0, 0, 0);
@@ -121,13 +136,15 @@ static void __init kb9202_board_init(void)
        /* USB Device */
        at91_add_device_udc(&kb9202_udc_data);
        /* MMC */
-        at91_add_device_mmc(0, &kb9202_mmc_data);
+        at91_add_device_mci(0, &kb9202_mci0_data);
        /* I2C */
        at91_add_device_i2c(NULL, 0);
        /* SPI */
        at91_add_device_spi(NULL, 0);
        /* NAND */
        at91_add_device_nand(&kb9202_nand_data);
+        /* LEDs */
+        at91_gpio_leds(kb9202_leds, ARRAY_SIZE(kb9202_leds));
 }
 MACHINE_START(KB9200, "KB920x")
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index 18103c5d993c..9cda3fd346ae 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -138,11 +138,12 @@ static struct spi_board_info neocore926_spi_devices[] = {
 /*
 * MCI (SD/MMC)
 */
-static struct at91_mmc_data __initdata neocore926_mmc_data = {
+static struct mci_platform_data __initdata neocore926_mci0_data = {
-        .wire4          = 1,
+        .slot[0] = {
-        .det_pin        = AT91_PIN_PE18,
+                .bus_width      = 4,
-        .wp_pin         = AT91_PIN_PE19,
+                .detect_pin     = AT91_PIN_PE18,
-        .vcc_pin        = -EINVAL,
+                .wp_pin         = AT91_PIN_PE19,
+        },
 };
@@ -354,7 +355,7 @@ static void __init neocore926_board_init(void)
        neocore926_add_device_ts();
        /* MMC */
-        at91_add_device_mmc(1, &neocore926_mmc_data);
+        at91_add_device_mci(0, &neocore926_mci0_data);
        /* Ethernet */
        at91_add_device_eth(&neocore926_macb_data);
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 127065504508..f83e1de699e6 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -62,12 +62,12 @@ static struct at91_usbh_data __initdata picotux200_usbh_data = {
        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
-static struct at91_mmc_data __initdata picotux200_mmc_data = {
+static struct mci_platform_data __initdata picotux200_mci0_data = {
-        .det_pin        = AT91_PIN_PB27,
+        .slot[0] = {
-        .slot_b         = 0,
+                .bus_width      = 4,
-        .wire4          = 1,
+                .detect_pin     = AT91_PIN_PB27,
-        .wp_pin         = AT91_PIN_PA17,
+                .wp_pin         = AT91_PIN_PA17,
-        .vcc_pin        = -EINVAL,
+        },
 };
 #define PICOTUX200_FLASH_BASE   AT91_CHIPSELECT_0
@@ -112,7 +112,7 @@ static void __init picotux200_board_init(void)
        at91_add_device_i2c(NULL, 0);
        /* MMC */
        at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
-        at91_add_device_mmc(0, &picotux200_mmc_data);
+        at91_add_device_mci(0, &picotux200_mci0_data);
        /* NOR Flash */
        platform_device_register(&picotux200_flash);
 }
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index bf351e285422..799f214edebe 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -156,12 +156,12 @@ static void __init ek_add_device_nand(void)
 /*
 * MCI (SD/MMC)
 */
-static struct at91_mmc_data __initdata ek_mmc_data = {
+static struct mci_platform_data __initdata ek_mci0_data = {
-        .slot_b         = 0,
+        .slot[0] = {
-        .wire4          = 1,
+                .bus_width      = 4,
-        .det_pin        = -EINVAL,
+                .detect_pin     = -EINVAL,
-        .wp_pin         = -EINVAL,
+                .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+        },
 };
 /*
@@ -245,7 +245,7 @@ static void __init ek_board_init(void)
        /* Ethernet */
        at91_add_device_eth(&ek_macb_data);
        /* MMC */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        at91_add_device_mci(0, &ek_mci0_data);
        /* Push Buttons */
        ek_add_device_buttons();
        /* LEDs */
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index cc2bf9796073..66338e7ebfba 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -77,12 +77,12 @@ static struct at91_cf_data __initdata dk_cf_data = {
 };
 #ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
-static struct at91_mmc_data __initdata dk_mmc_data = {
+static struct mci_platform_data __initdata dk_mci0_data = {
-        .slot_b         = 0,
+        .slot[0] = {
-        .wire4          = 1,
+                .bus_width      = 4,
-        .det_pin        = -EINVAL,
+                .detect_pin     = -EINVAL,
-        .wp_pin         = -EINVAL,
+                .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+        },
 };
 #endif
@@ -177,9 +177,6 @@ static struct gpio_led dk_leds[] = {
 static void __init dk_board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
        /* Serial */
        /* DBGU on ttyS0. (Rx & Tx only) */
        at91_register_uart(0, 0, 0);
@@ -208,7 +205,7 @@ static void __init dk_board_init(void)
 #else
        /* MMC */
        at91_set_gpio_output(AT91_PIN_PB7, 1);  /* this MMC card slot can optionally use SPI signaling (CS3). */
-        at91_add_device_mmc(0, &dk_mmc_data);
+        at91_add_device_mci(0, &dk_mci0_data);
 #endif
        /* NAND */
        at91_add_device_nand(&dk_nand_data);
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 62e19e64c9d3..5d1b5729dc69 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -70,12 +70,12 @@ static struct at91_udc_data __initdata ek_udc_data = {
 };
 #ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
-static struct at91_mmc_data __initdata ek_mmc_data = {
+static struct mci_platform_data __initdata ek_mci0_data = {
-        .det_pin        = AT91_PIN_PB27,
+        .slot[0] = {
-        .slot_b         = 0,
+                .bus_width      = 4,
-        .wire4          = 1,
+                .detect_pin     = AT91_PIN_PB27,
-        .wp_pin         = AT91_PIN_PA17,
+                .wp_pin         = AT91_PIN_PA17,
-        .vcc_pin        = -EINVAL,
+        }
 };
 #endif
@@ -148,9 +148,6 @@ static struct gpio_led ek_leds[] = {
 static void __init ek_board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
        /* Serial */
        /* DBGU on ttyS0. (Rx & Tx only) */
        at91_register_uart(0, 0, 0);
@@ -177,7 +174,7 @@ static void __init ek_board_init(void)
 #else
        /* MMC */
        at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        at91_add_device_mci(0, &ek_mci0_data);
 #endif
        /* NOR Flash */
        platform_device_register(&ek_flash);
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index c3b43aefdb75..a0ecf04e9ae3 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -58,11 +58,12 @@ static struct at91_usbh_data rsi_ews_usbh_data __initdata = {
 /*
 * SD/MC
 */
-static struct at91_mmc_data rsi_ews_mmc_data __initdata = {
+static struct mci_platform_data __initdata rsi_ews_mci0_data = {
-        .slot_b         = 0,
+        .slot[0] = {
-        .wire4          = 1,
+                .bus_width      = 4,
-        .det_pin        = AT91_PIN_PB27,
+                .detect_pin     = AT91_PIN_PB27,
-        .wp_pin         = AT91_PIN_PB29,
+                .wp_pin         = AT91_PIN_PB29,
+        },
 };
 /*
@@ -185,9 +186,6 @@ static struct platform_device rsiews_nor_flash = {
 */
 static void __init rsi_ews_board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9);
        /* Serial */
        /* DBGU on ttyS0. (Rx & Tx only) */
        /* This one is for debugging */
@@ -215,7 +213,7 @@ static void __init rsi_ews_board_init(void)
        at91_add_device_spi(rsi_ews_spi_devices,
                        ARRAY_SIZE(rsi_ews_spi_devices));
        /* MMC */
-        at91_add_device_mmc(0, &rsi_ews_mmc_data);
+        at91_add_device_mci(0, &rsi_ews_mci0_data);
        /* NOR Flash */
        platform_device_register(&rsiews_nor_flash);
        /* LEDs */
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 7bf6da70d7d5..c5f01acce3c0 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -73,7 +73,7 @@ static struct at91_udc_data __initdata ek_udc_data = {
 * SPI devices.
 */
 static struct spi_board_info ek_spi_devices[] = {
-#if !defined(CONFIG_MMC_AT91)
+#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
        {       /* DataFlash chip */
                .modalias       = "mtd_dataflash",
                .chip_select    = 1,
@@ -158,19 +158,34 @@ static void __init ek_add_device_nand(void)
 /*
 * MCI (SD/MMC)
 */
-static struct at91_mmc_data __initdata ek_mmc_data = {
+static struct mci_platform_data __initdata ek_mci0_data = {
-        .slot_b         = 1,
+        .slot[1] = {
-        .wire4          = 1,
+                .bus_width      = 4,
-        .det_pin        = AT91_PIN_PC8,
+                .detect_pin     = AT91_PIN_PC8,
-        .wp_pin         = AT91_PIN_PC4,
+                .wp_pin         = AT91_PIN_PC4,
-        .vcc_pin        = -EINVAL,
+        },
+};
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* D1 */
+                .name                   = "led1",
+                .gpio                   = AT91_PIN_PA9,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+        {       /* D2 */
+                .name                   = "led2",
+                .gpio                   = AT91_PIN_PA6,
+                .active_low             = 1,
+                .default_trigger        = "timer",
+        }
 };
 static void __init ek_board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6);
        /* Serial */
        /* DBGU on ttyS0. (Rx & Tx only) */
        at91_register_uart(0, 0, 0);
@@ -194,9 +209,11 @@ static void __init ek_board_init(void)
        /* Ethernet */
        at91_add_device_eth(&ek_macb_data);
        /* MMC */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        at91_add_device_mci(0, &ek_mci0_data);
        /* I2C */
        at91_add_device_i2c(NULL, 0);
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
 }
 MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 889c1bf71eb5..8cd6e679fbe0 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -108,7 +108,7 @@ static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
 * SPI devices.
 */
 static struct spi_board_info ek_spi_devices[] = {
-#if !defined(CONFIG_MMC_AT91)
+#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
        {       /* DataFlash chip */
                .modalias       = "mtd_dataflash",
                .chip_select    = 1,
@@ -211,12 +211,12 @@ static void __init ek_add_device_nand(void)
 /*
 * MCI (SD/MMC)
 */
-static struct at91_mmc_data __initdata ek_mmc_data = {
+static struct mci_platform_data __initdata ek_mci0_data = {
-        .slot_b         = 1,
+        .slot[1] = {
-        .wire4          = 1,
+                .bus_width      = 4,
-        .det_pin        = -EINVAL,
+                .detect_pin     = -EINVAL,
-        .wp_pin         = -EINVAL,
+                .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+        },
 };
@@ -329,7 +329,7 @@ static void __init ek_board_init(void)
        /* Ethernet */
        at91_add_device_eth(&ek_macb_data);
        /* MMC */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        at91_add_device_mci(0, &ek_mci0_data);
        /* I2C */
        at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
        /* SSC (to AT73C213) */
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 2269be5fa384..27b3af1a3047 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -340,11 +340,12 @@ static struct spi_board_info ek_spi_devices[] = {
 * MCI (SD/MMC)
 * det_pin, wp_pin and vcc_pin are not connected
 */
-static struct at91_mmc_data __initdata ek_mmc_data = {
+static struct mci_platform_data __initdata mci0_data = {
-        .wire4          = 1,
+        .slot[0] = {
-        .det_pin        = -EINVAL,
+                .bus_width      = 4,
-        .wp_pin         = -EINVAL,
+                .detect_pin     = -EINVAL,
-        .vcc_pin        = -EINVAL,
+                .wp_pin         = -EINVAL,
+        },
 };
 #endif /* CONFIG_SPI_ATMEL_* */
@@ -569,9 +570,6 @@ static struct gpio_led ek_leds[] = {
 static void __init ek_board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
        /* Serial */
        /* DBGU on ttyS0. (Rx & Tx only) */
        at91_register_uart(0, 0, 0);
@@ -598,7 +596,7 @@ static void __init ek_board_init(void)
        at91_add_device_ssc(AT91SAM9261_ID_SSC1, ATMEL_SSC_TX);
 #else
        /* MMC */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        at91_add_device_mci(0, &mci0_data);
 #endif
        /* LCD Controller */
        at91_add_device_lcdc(&ek_lcdc_data);
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 82adf581afc2..073e17403d98 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -141,11 +141,12 @@ static struct spi_board_info ek_spi_devices[] = {
 /*
 * MCI (SD/MMC)
 */
-static struct at91_mmc_data __initdata ek_mmc_data = {
+static struct mci_platform_data __initdata mci1_data = {
-        .wire4          = 1,
+        .slot[0] = {
-        .det_pin        = AT91_PIN_PE18,
+                .bus_width      = 4,
-        .wp_pin         = AT91_PIN_PE19,
+                .detect_pin     = AT91_PIN_PE18,
-        .vcc_pin        = -EINVAL,
+                .wp_pin         = AT91_PIN_PE19,
+        },
 };
@@ -420,7 +421,7 @@ static void __init ek_board_init(void)
        /* Touchscreen */
        ek_add_device_ts();
        /* MMC */
-        at91_add_device_mmc(1, &ek_mmc_data);
+        at91_add_device_mci(1, &mci1_data);
        /* Ethernet */
        at91_add_device_eth(&ek_macb_data);
        /* NAND */
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 4ea4ee00364b..3ab2b86a3762 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -92,7 +92,7 @@ static struct at91_udc_data __initdata ek_udc_data = {
 * SPI devices.
 */
 static struct spi_board_info ek_spi_devices[] = {
-#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91))
+#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
        {       /* DataFlash chip */
                .modalias       = "mtd_dataflash",
                .chip_select    = 1,
@@ -199,7 +199,6 @@ static void __init ek_add_device_nand(void)
 * MCI (SD/MMC)
 * wp_pin and vcc_pin are not connected
 */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
 static struct mci_platform_data __initdata ek_mmc_data = {
        .slot[1] = {
                .bus_width      = 4,
@@ -208,28 +207,15 @@ static struct mci_platform_data __initdata ek_mmc_data = {
        },
 };
-#else
-static struct at91_mmc_data __initdata ek_mmc_data = {
-        .slot_b         = 1,    /* Only one slot so use slot B */
-        .wire4          = 1,
-        .det_pin        = AT91_PIN_PC9,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
-};
-#endif
 static void __init ek_add_device_mmc(void)
 {
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
        if (ek_have_2mmc()) {
                ek_mmc_data.slot[0].bus_width = 4;
                ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2;
                ek_mmc_data.slot[0].wp_pin = -1;
        }
        at91_add_device_mci(0, &ek_mmc_data);
-#else
-        at91_add_device_mmc(0, &ek_mmc_data);
-#endif
 }
 /*
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index e7dc3ead7045..fb89ea92e3f2 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -56,11 +56,12 @@ static struct usba_platform_data __initdata ek_usba_udc_data = {
 /*
 * MCI (SD/MMC)
 */
-static struct at91_mmc_data __initdata ek_mmc_data = {
+static struct mci_platform_data __initdata mci0_data = {
-        .wire4          = 1,
+        .slot[0] = {
-        .det_pin        = AT91_PIN_PA15,
+                .bus_width      = 4,
-        .wp_pin         = -EINVAL,
+                .detect_pin     = AT91_PIN_PA15,
-        .vcc_pin        = -EINVAL,
+                .wp_pin         = -EINVAL,
+        },
 };
@@ -303,7 +304,7 @@ static void __init ek_board_init(void)
        /* SPI */
        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
        /* MMC */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        at91_add_device_mci(0, &mci0_data);
        /* LCD Controller */
        at91_add_device_lcdc(&ek_lcdc_data);
        /* AC97 */
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 29eae1626bf7..c3fb31d5116e 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -83,7 +83,6 @@ static void __init add_device_nand(void)
 * MCI (SD/MMC)
 * det_pin, wp_pin and vcc_pin are not connected
 */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
 static struct mci_platform_data __initdata mmc_data = {
        .slot[0] = {
                .bus_width      = 4,
@@ -91,15 +90,6 @@ static struct mci_platform_data __initdata mmc_data = {
                .wp_pin         = -1,
        },
 };
-#else
-static struct at91_mmc_data __initdata mmc_data = {
-        .slot_b         = 0,
-        .wire4          = 1,
-        .det_pin        = -EINVAL,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
-};
-#endif
 /*
@@ -223,11 +213,7 @@ void __init stamp9g20_board_init(void)
        /* NAND */
        add_device_nand();
        /* MMC */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
        at91_add_device_mci(0, &mmc_data);
-#else
-        at91_add_device_mmc(0, &mmc_data);
-#endif
        /* W1 */
        add_w1();
 }
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index c1476b9fe7b9..6ea069b57335 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -109,14 +109,12 @@ static struct mmc_spi_platform_data at91_mmc_spi_pdata = {
 * SPI devices.
 */
 static struct spi_board_info usb_a9263_spi_devices[] = {
-#if !defined(CONFIG_MMC_AT91)
        {       /* DataFlash chip */
                .modalias       = "mtd_dataflash",
                .chip_select    = 0,
                .max_speed_hz   = 15 * 1000 * 1000,
                .bus_num        = 0,
        }
-#endif
 };
 static struct spi_board_info usb_a9g20_spi_devices[] = {
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 516d340549d8..f162fdfd66eb 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -119,11 +119,12 @@ static struct at91_udc_data __initdata yl9200_udc_data = {
 /*
 * MMC
 */
-static struct at91_mmc_data __initdata yl9200_mmc_data = {
+static struct mci_platform_data __initdata yl9200_mci0_data = {
-        .det_pin        = AT91_PIN_PB9,
+        .slot[0] = {
-        .wire4          = 1,
+                .bus_width      = 4,
-        .wp_pin         = -EINVAL,
+                .detect_pin     = AT91_PIN_PB9,
-        .vcc_pin        = -EINVAL,
+                .wp_pin         = -EINVAL,
+        },
 };
 /*
@@ -541,9 +542,6 @@ void __init yl9200_add_device_video(void) {}
 static void __init yl9200_board_init(void)
 {
-        /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
-        at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
        /* Serial */
        /* DBGU on ttyS0. (Rx & Tx only) */
        at91_register_uart(0, 0, 0);
@@ -568,7 +566,7 @@ static void __init yl9200_board_init(void)
        /* I2C */
        at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
        /* MMC */
-        at91_add_device_mmc(0, &yl9200_mmc_data);
+        at91_add_device_mci(0, &yl9200_mci0_data);
        /* NAND */
        at91_add_device_nand(&yl9200_nand_data);
        /* NOR Flash */
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 188c82971ebd..33361505c0cd 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -625,7 +625,7 @@ fail:
        return 0;
 }
-static struct clk *const standard_pmc_clocks[] __initdata = {
+static struct clk *const standard_pmc_clocks[] __initconst = {
        /* four primary clocks */
        &clk32k,
        &main_clk,
diff --git a/arch/arm/mach-at91/include/mach/at91_twi.h b/arch/arm/mach-at91/include/mach/at91_twi.h
deleted file mode 100644
index bb2880f6ba37..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_twi.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_twi.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Two-wire Interface (TWI) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91_TWI_H
-#define AT91_TWI_H
-#define AT91_TWI_CR             0x00            /* Control Register */
-#define         AT91_TWI_START          (1 <<  0)       /* Send a Start Condition */
-#define         AT91_TWI_STOP           (1 <<  1)       /* Send a Stop Condition */
-#define         AT91_TWI_MSEN           (1 <<  2)       /* Master Transfer Enable */
-#define         AT91_TWI_MSDIS          (1 <<  3)       /* Master Transfer Disable */
-#define         AT91_TWI_SVEN           (1 <<  4)       /* Slave Transfer Enable [SAM9260 only] */
-#define         AT91_TWI_SVDIS          (1 <<  5)       /* Slave Transfer Disable [SAM9260 only] */
-#define         AT91_TWI_SWRST          (1 <<  7)       /* Software Reset */
-#define AT91_TWI_MMR            0x04            /* Master Mode Register */
-#define         AT91_TWI_IADRSZ         (3    <<  8)    /* Internal Device Address Size */
-#define                 AT91_TWI_IADRSZ_NO              (0 << 8)
-#define                 AT91_TWI_IADRSZ_1               (1 << 8)
-#define                 AT91_TWI_IADRSZ_2               (2 << 8)
-#define                 AT91_TWI_IADRSZ_3               (3 << 8)
-#define         AT91_TWI_MREAD          (1    << 12)    /* Master Read Direction */
-#define         AT91_TWI_DADR           (0x7f << 16)    /* Device Address */
-#define AT91_TWI_SMR            0x08            /* Slave Mode Register [SAM9260 only] */
-#define         AT91_TWI_SADR           (0x7f << 16)    /* Slave Address */
-#define AT91_TWI_IADR           0x0c            /* Internal Address Register */
-#define AT91_TWI_CWGR           0x10            /* Clock Waveform Generator Register */
-#define         AT91_TWI_CLDIV          (0xff <<  0)    /* Clock Low Divisor */
-#define         AT91_TWI_CHDIV          (0xff <<  8)    /* Clock High Divisor */
-#define         AT91_TWI_CKDIV          (7    << 16)    /* Clock Divider */
-#define AT91_TWI_SR             0x20            /* Status Register */
-#define         AT91_TWI_TXCOMP         (1 <<  0)       /* Transmission Complete */
-#define         AT91_TWI_RXRDY          (1 <<  1)       /* Receive Holding Register Ready */
-#define         AT91_TWI_TXRDY          (1 <<  2)       /* Transmit Holding Register Ready */
-#define         AT91_TWI_SVREAD         (1 <<  3)       /* Slave Read [SAM9260 only] */
-#define         AT91_TWI_SVACC          (1 <<  4)       /* Slave Access [SAM9260 only] */
-#define         AT91_TWI_GACC           (1 <<  5)       /* General Call Access [SAM9260 only] */
-#define         AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error [AT91RM9200 only] */
-#define         AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error [AT91RM9200 only] */
-#define         AT91_TWI_NACK           (1 <<  8)       /* Not Acknowledged */
-#define         AT91_TWI_ARBLST         (1 <<  9)       /* Arbitration Lost [SAM9260 only] */
-#define         AT91_TWI_SCLWS          (1 << 10)       /* Clock Wait State [SAM9260 only] */
-#define         AT91_TWI_EOSACC         (1 << 11)       /* End of Slave Address [SAM9260 only] */
-#define AT91_TWI_IER            0x24            /* Interrupt Enable Register */
-#define AT91_TWI_IDR            0x28            /* Interrupt Disable Register */
-#define AT91_TWI_IMR            0x2c            /* Interrupt Mask Register */
-#define AT91_TWI_RHR            0x30            /* Receive Holding Register */
-#define AT91_TWI_THR            0x34            /* Transmit Holding Register */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at_hdmac.h b/arch/arm/mach-at91/include/mach/at_hdmac.h
deleted file mode 100644
index cab0997be3de..000000000000
--- a/arch/arm/mach-at91/include/mach/at_hdmac.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Header file for the Atmel AHB DMA Controller driver
- *
- * Copyright (C) 2008 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT_HDMAC_H
-#define AT_HDMAC_H
-#include <linux/dmaengine.h>
-/**
- * struct at_dma_platform_data - Controller configuration parameters
- * @nr_channels: Number of channels supported by hardware (max 8)
- * @cap_mask: dma_capability flags supported by the platform
- */
-struct at_dma_platform_data {
-        unsigned int    nr_channels;
-        dma_cap_mask_t  cap_mask;
-};
-/**
- * struct at_dma_slave - Controller-specific information about a slave
- * @dma_dev: required DMA master device
- * @cfg: Platform-specific initializer for the CFG register
- */
-struct at_dma_slave {
-        struct device           *dma_dev;
-        u32                     cfg;
-};
-/* Platform-configurable bits in CFG */
-#define ATC_SRC_PER(h)          (0xFU & (h))    /* Channel src rq associated with periph handshaking ifc h */
-#define ATC_DST_PER(h)          ((0xFU & (h)) <<  4)    /* Channel dst rq associated with periph handshaking ifc h */
-#define ATC_SRC_REP             (0x1 <<  8)     /* Source Replay Mod */
-#define ATC_SRC_H2SEL           (0x1 <<  9)     /* Source Handshaking Mod */
-#define         ATC_SRC_H2SEL_SW        (0x0 <<  9)
-#define         ATC_SRC_H2SEL_HW        (0x1 <<  9)
-#define ATC_DST_REP             (0x1 << 12)     /* Destination Replay Mod */
-#define ATC_DST_H2SEL           (0x1 << 13)     /* Destination Handshaking Mod */
-#define         ATC_DST_H2SEL_SW        (0x0 << 13)
-#define         ATC_DST_H2SEL_HW        (0x1 << 13)
-#define ATC_SOD                 (0x1 << 16)     /* Stop On Done */
-#define ATC_LOCK_IF             (0x1 << 20)     /* Interface Lock */
-#define ATC_LOCK_B              (0x1 << 21)     /* AHB Bus Lock */
-#define ATC_LOCK_IF_L           (0x1 << 22)     /* Master Interface Arbiter Lock */
-#define         ATC_LOCK_IF_L_CHUNK     (0x0 << 22)
-#define         ATC_LOCK_IF_L_BUFFER    (0x1 << 22)
-#define ATC_AHB_PROT_MASK       (0x7 << 24)     /* AHB Protection */
-#define ATC_FIFOCFG_MASK        (0x3 << 28)     /* FIFO Request Configuration */
-#define         ATC_FIFOCFG_LARGESTBURST        (0x0 << 28)
-#define         ATC_FIFOCFG_HALFFIFO            (0x1 << 28)
-#define         ATC_FIFOCFG_ENOUGHSPACE         (0x2 << 28)
-#endif /* AT_HDMAC_H */
diff --git a/arch/arm/mach-at91/include/mach/atmel-mci.h b/arch/arm/mach-at91/include/mach/atmel-mci.h
index 998cb0c07135..cd580a12e904 100644
--- a/arch/arm/mach-at91/include/mach/atmel-mci.h
+++ b/arch/arm/mach-at91/include/mach/atmel-mci.h
@@ -1,7 +1,7 @@
 #ifndef __MACH_ATMEL_MCI_H
 #define __MACH_ATMEL_MCI_H
-#include <mach/at_hdmac.h>
+#include <linux/platform_data/dma-atmel.h>
 /**
 * struct mci_dma_data - DMA data for MCI interface
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 369afc2ffc5b..c55a4364ffb4 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -187,7 +187,6 @@ struct at91_can_data {
 extern void __init at91_add_device_can(struct at91_can_data *data);
 /* LEDs */
-extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
 extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
 extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 09242b67d277..711a7892d331 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -67,13 +67,13 @@
 * to 0xFEF78000 .. 0xFF000000.  (544Kb)
 */
 #define AT91_IO_PHYS_BASE       0xFFF78000
-#define AT91_IO_VIRT_BASE       (0xFF000000 - AT91_IO_SIZE)
+#define AT91_IO_VIRT_BASE       IOMEM(0xFF000000 - AT91_IO_SIZE)
 #else
 /*
 * Identity mapping for the non MMU case.
 */
 #define AT91_IO_PHYS_BASE       AT91_BASE_SYS
-#define AT91_IO_VIRT_BASE       AT91_IO_PHYS_BASE
+#define AT91_IO_VIRT_BASE       IOMEM(AT91_IO_PHYS_BASE)
 #endif
 #define AT91_IO_SIZE            (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 6f6118d1576a..97ad68a826f8 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -94,7 +94,7 @@ static const u32 uarts_sam9x5[] = {
        0,
 };
-static inline const u32* decomp_soc_detect(u32 dbgu_base)
+static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
 {
        u32 cidr, socid;
@@ -142,10 +142,10 @@ static inline void arch_decomp_setup(void)
        int i = 0;
        const u32* usarts;
-        usarts = decomp_soc_detect(AT91_BASE_DBGU0);
+        usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
        if (!usarts)
-                usarts = decomp_soc_detect(AT91_BASE_DBGU1);
+                usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
        if (!usarts) {
                at91_uart = NULL;
                return;
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
index 8dfafe76ffe6..1b1e62b5f41b 100644
--- a/arch/arm/mach-at91/leds.c
+++ b/arch/arm/mach-at91/leds.c
@@ -90,108 +90,3 @@ void __init at91_pwm_leds(struct gpio_led *leds, int nr)
 #else
 void __init at91_pwm_leds(struct gpio_led *leds, int nr){}
 #endif
-/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_LEDS)
-#include <asm/leds.h>
-/*
- * Old ARM-specific LED framework; not fully functional when generic time is
- * in use.
- */
-static u8 at91_leds_cpu;
-static u8 at91_leds_timer;
-static inline void at91_led_on(unsigned int led)
-{
-        at91_set_gpio_value(led, 0);
-}
-static inline void at91_led_off(unsigned int led)
-{
-        at91_set_gpio_value(led, 1);
-}
-static inline void at91_led_toggle(unsigned int led)
-{
-        unsigned long is_off = at91_get_gpio_value(led);
-        if (is_off)
-                at91_led_on(led);
-        else
-                at91_led_off(led);
-}
-/*
- * Handle LED events.
- */
-static void at91_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        switch(evt) {
-        case led_start:         /* System startup */
-                at91_led_on(at91_leds_cpu);
-                break;
-        case led_stop:          /* System stop / suspend */
-                at91_led_off(at91_leds_cpu);
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:         /* Every 50 timer ticks */
-                at91_led_toggle(at91_leds_timer);
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:    /* Entering idle state */
-                at91_led_off(at91_leds_cpu);
-                break;
-        case led_idle_end:      /* Exit idle state */
-                at91_led_on(at91_leds_cpu);
-                break;
-#endif
-        default:
-                break;
-        }
-        local_irq_restore(flags);
-}
-static int __init leds_init(void)
-{
-        if (!at91_leds_timer || !at91_leds_cpu)
-                return -ENODEV;
-        leds_event = at91_leds_event;
-        leds_event(led_start);
-        return 0;
-}
-__initcall(leds_init);
-void __init at91_init_leds(u8 cpu_led, u8 timer_led)
-{
-        /* Enable GPIO to access the LEDs */
-        at91_set_gpio_output(cpu_led, 1);
-        at91_set_gpio_output(timer_led, 1);
-        at91_leds_cpu   = cpu_led;
-        at91_leds_timer = timer_led;
-}
-#else
-void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
-#endif
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 2c2d86505a54..5315f05896e9 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -153,7 +153,9 @@ static int at91_pm_verify_clocks(void)
                }
        }
-#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
+        if (!IS_ENABLED(CONFIG_AT91_PROGRAMMABLE_CLOCKS))
+                return 1;
        /* PCK0..PCK3 must be disabled, or configured to use clk32k */
        for (i = 0; i < 4; i++) {
                u32 css;
@@ -167,7 +169,6 @@ static int at91_pm_verify_clocks(void)
                        return 0;
                }
        }
-#endif
        return 1;
 }
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 944bffb08991..da9881b161e1 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -73,7 +73,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 {
        struct map_desc *desc = &sram_desc[bank];
-        desc->virtual = AT91_IO_VIRT_BASE - length;
+        desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
        if (bank > 0)
                desc->virtual -= sram_desc[bank - 1].length;
@@ -87,8 +87,8 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
        iotable_init(desc, 1);
 }
-static struct map_desc at91_io_desc __initdata = {
+static struct map_desc at91_io_desc __initdata __maybe_unused = {
-        .virtual        = AT91_VA_BASE_SYS,
+        .virtual        = (unsigned long)AT91_VA_BASE_SYS,
        .pfn            = __phys_to_pfn(AT91_BASE_SYS),
        .length         = SZ_16K,
        .type           = MT_DEVICE,
diff --git a/arch/arm/mach-bcm2835/Makefile b/arch/arm/mach-bcm2835/Makefile
new file mode 100644
index 000000000000..4c3892fe02c3
--- /dev/null
+++ b/arch/arm/mach-bcm2835/Makefile
@@ -0,0 +1 @@
+obj-y += bcm2835.o
diff --git a/arch/arm/mach-bcm2835/Makefile.boot b/arch/arm/mach-bcm2835/Makefile.boot
new file mode 100644
index 000000000000..2d30e17f5b69
--- /dev/null
+++ b/arch/arm/mach-bcm2835/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
new file mode 100644
index 000000000000..f6fea4933571
--- /dev/null
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2010 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/init.h>
+#include <linux/irqchip/bcm2835.h>
+#include <linux/of_platform.h>
+#include <linux/bcm2835_timer.h>
+#include <linux/clk/bcm2835.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/bcm2835_soc.h>
+static struct map_desc io_map __initdata = {
+        .virtual = BCM2835_PERIPH_VIRT,
+        .pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS),
+        .length = BCM2835_PERIPH_SIZE,
+        .type = MT_DEVICE
+};
+void __init bcm2835_map_io(void)
+{
+        iotable_init(&io_map, 1);
+}
+void __init bcm2835_init(void)
+{
+        int ret;
+        bcm2835_init_clocks();
+        ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
+                                   NULL);
+        if (ret) {
+                pr_err("of_platform_populate failed: %d\n", ret);
+                BUG();
+        }
+}
+static const char * const bcm2835_compat[] = {
+        "brcm,bcm2835",
+        NULL
+};
+DT_MACHINE_START(BCM2835, "BCM2835")
+        .map_io = bcm2835_map_io,
+        .init_irq = bcm2835_init_irq,
+        .handle_irq = bcm2835_handle_irq,
+        .init_machine = bcm2835_init,
+        .timer = &bcm2835_timer,
+        .dt_compat = bcm2835_compat
+MACHINE_END
diff --git a/arch/arm/mach-picoxcell/include/mach/hardware.h b/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h
index 70ff58192ec9..d4dfcf7a9cda 100644
--- a/arch/arm/mach-picoxcell/include/mach/hardware.h
+++ b/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h
@@ -1,7 +1,8 @@
 /*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ * Copyright (C) 2012 Stephen Warren
 *
- * This file contains the hardware definitions of the picoXcell SoC devices.
+ * Derived from code:
+ * Copyright (C) 2010 Broadcom
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -13,9 +14,16 @@
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-#include <mach/picoxcell_soc.h>
+#ifndef __MACH_BCM2835_BCM2835_SOC_H__
+#define __MACH_BCM2835_BCM2835_SOC_H__
+#include <asm/sizes.h>
+#define BCM2835_PERIPH_PHYS     0x20000000
+#define BCM2835_PERIPH_VIRT     0xf0000000
+#define BCM2835_PERIPH_SIZE     SZ_16M
+#define BCM2835_DEBUG_PHYS      0x20201000
+#define BCM2835_DEBUG_VIRT      0xf0201000
 #endif
diff --git a/arch/arm/mach-bcm2835/include/mach/debug-macro.S b/arch/arm/mach-bcm2835/include/mach/debug-macro.S
new file mode 100644
index 000000000000..8a161e44ae28
--- /dev/null
+++ b/arch/arm/mach-bcm2835/include/mach/debug-macro.S
@@ -0,0 +1,21 @@
+/*
+ * Debugging macro include header
+ *
+ * Copyright (C) 2010 Broadcom
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <mach/bcm2835_soc.h>
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =BCM2835_DEBUG_PHYS
+        ldr     \rv, =BCM2835_DEBUG_VIRT
+        .endm
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-pnx4008/include/mach/param.h b/arch/arm/mach-bcm2835/include/mach/timex.h
index 6ea02f2176b7..6d021e136ae3 100644
--- a/arch/arm/mach-pnx4008/include/mach/param.h
+++ b/arch/arm/mach-bcm2835/include/mach/timex.h
@@ -1,7 +1,7 @@
 /*
- *  arch/arm/mach-pnx4008/include/mach/param.h
+ *  BCM2835 system clock frequency
 *
- *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2010 Broadcom
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -18,4 +18,9 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#define HZ 100
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+#define CLOCK_TICK_RATE         (1000000)
+#endif
diff --git a/arch/arm/mach-bcm2835/include/mach/uncompress.h b/arch/arm/mach-bcm2835/include/mach/uncompress.h
new file mode 100644
index 000000000000..cc46dcc72377
--- /dev/null
+++ b/arch/arm/mach-bcm2835/include/mach/uncompress.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2010 Broadcom
+ * Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/io.h>
+#include <linux/amba/serial.h>
+#include <mach/bcm2835_soc.h>
+#define UART0_BASE BCM2835_DEBUG_PHYS
+#define BCM2835_UART_DR IOMEM(UART0_BASE + UART01x_DR)
+#define BCM2835_UART_FR IOMEM(UART0_BASE + UART01x_FR)
+#define BCM2835_UART_CR IOMEM(UART0_BASE + UART011_CR)
+static inline void putc(int c)
+{
+        while (__raw_readl(BCM2835_UART_FR) & UART01x_FR_TXFF)
+                barrier();
+        __raw_writel(c, BCM2835_UART_DR);
+}
+static inline void flush(void)
+{
+        int fr;
+        do {
+                fr = __raw_readl(BCM2835_UART_FR);
+                barrier();
+        } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
+}
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-bcmring/Kconfig b/arch/arm/mach-bcmring/Kconfig
deleted file mode 100644
index 9170d16dca50..000000000000
--- a/arch/arm/mach-bcmring/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-choice
-        prompt "Processor selection in BCMRING family of devices"
-        depends on ARCH_BCMRING
-        default ARCH_BCM11107
-config ARCH_FPGA11107
-        bool "FPGA11107"
-config ARCH_BCM11107
-        bool "BCM11107"
-endchoice
-menu "BCMRING Options"
-        depends on ARCH_BCMRING
-config BCM_ZRELADDR
-        hex "Compressed ZREL ADDR"
-endmenu
diff --git a/arch/arm/mach-bcmring/Makefile b/arch/arm/mach-bcmring/Makefile
deleted file mode 100644
index f8d9fcedf917..000000000000
--- a/arch/arm/mach-bcmring/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-# Object file lists.
-obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o
-obj-y += csp/
diff --git a/arch/arm/mach-bcmring/Makefile.boot b/arch/arm/mach-bcmring/Makefile.boot
deleted file mode 100644
index aef2467757fa..000000000000
--- a/arch/arm/mach-bcmring/Makefile.boot
+++ /dev/null
@@ -1,6 +0,0 @@
-# Address where decompressor will be written and eventually executed.
-#
-# default to SDRAM
-zreladdr-y      += $(CONFIG_BCM_ZRELADDR)
-params_phys-y   := 0x00000800
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
deleted file mode 100644
index 45c97b1ee9b1..000000000000
--- a/arch/arm/mach-bcmring/arch.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-#include <linux/proc_fs.h>
-#include <linux/sysctl.h>
-#include <asm/irq.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/time.h>
-#include <asm/pmu.h>
-#include <asm/mach/arch.h>
-#include <mach/dma.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <cfg_global.h>
-#include "core.h"
-HW_DECLARE_SPINLOCK(arch)
-HW_DECLARE_SPINLOCK(gpio)
-#if defined(CONFIG_DEBUG_SPINLOCK)
-    EXPORT_SYMBOL(bcmring_gpio_reg_lock);
-#endif
-/* sysctl */
-static int bcmring_arch_warm_reboot;    /* do a warm reboot on hard reset */
-static void bcmring_restart(char mode, const char *cmd)
-{
-        printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
-        if (mode == 'h') {
-                /* Reboot configured in proc entry */
-                if (bcmring_arch_warm_reboot) {
-                        printk("warm reset\n");
-                        /* Issue Warm reset (do not reset ethernet switch, keep alive) */
-                        chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
-                } else {
-                        /* Force reset of everything */
-                        printk("force reset\n");
-                        chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-                }
-        } else {
-                /* Force reset of everything */
-                printk("force reset\n");
-                chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-        }
-}
-static struct ctl_table_header *bcmring_sysctl_header;
-static struct ctl_table bcmring_sysctl_warm_reboot[] = {
-        {
-         .procname = "warm",
-         .data = &bcmring_arch_warm_reboot,
-         .maxlen = sizeof(int),
-         .mode = 0644,
-         .proc_handler = proc_dointvec},
-        {}
-};
-static struct ctl_table bcmring_sysctl_reboot[] = {
-        {
-         .procname = "reboot",
-         .mode = 0555,
-         .child = bcmring_sysctl_warm_reboot},
-        {}
-};
-static struct resource nand_resource[] = {
-        [0] = {
-                .start = MM_ADDR_IO_NAND,
-                .end = MM_ADDR_IO_NAND + 0x1000 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-static struct platform_device nand_device = {
-        .name = "bcm-nand",
-        .id = -1,
-        .resource = nand_resource,
-        .num_resources  = ARRAY_SIZE(nand_resource),
-};
-static struct resource pmu_resource = {
-        .start  = IRQ_PMUIRQ,
-        .end    = IRQ_PMUIRQ,
-        .flags  = IORESOURCE_IRQ,
-};
-static struct platform_device pmu_device = {
-        .name           = "arm-pmu",
-        .id             = ARM_PMU_DEVICE_CPU,
-        .resource       = &pmu_resource,
-        .num_resources  = 1,
-};
-static struct platform_device *devices[] __initdata = {
-        &nand_device,
-        &pmu_device,
-};
-/****************************************************************************
-*
-*   Called from the customize_machine function in arch/arm/kernel/setup.c
-*
-*   The customize_machine function is tagged as an arch_initcall
-*   (see include/linux/init.h for the order that the various init sections
-*   are called in.
-*
-*****************************************************************************/
-static void __init bcmring_init_machine(void)
-{
-        bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot);
-        /* Enable spread spectrum */
-        chipcHw_enableSpreadSpectrum();
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-        bcmring_amba_init();
-        dma_init();
-}
-/****************************************************************************
-*
-*   Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags
-*   passed in by the boot loader.
-*
-*****************************************************************************/
-static void __init bcmring_fixup(struct tag *t, char **cmdline,
-        struct meminfo *mi) {
-#ifdef CONFIG_BLK_DEV_INITRD
-        printk(KERN_NOTICE "bcmring_fixup\n");
-        t->hdr.tag = ATAG_CORE;
-        t->hdr.size = tag_size(tag_core);
-        t->u.core.flags = 0;
-        t->u.core.pagesize = PAGE_SIZE;
-        t->u.core.rootdev = 31 << 8 | 0;
-        t = tag_next(t);
-        t->hdr.tag = ATAG_MEM;
-        t->hdr.size = tag_size(tag_mem32);
-        t->u.mem.start = CFG_GLOBAL_RAM_BASE;
-        t->u.mem.size = CFG_GLOBAL_RAM_SIZE;
-        t = tag_next(t);
-        t->hdr.tag = ATAG_NONE;
-        t->hdr.size = 0;
-#endif
-}
-/****************************************************************************
-*
-*   Machine Description
-*
-*****************************************************************************/
-MACHINE_START(BCMRING, "BCMRING")
-        /* Maintainer: Broadcom Corporation */
-        .fixup = bcmring_fixup,
-        .map_io = bcmring_map_io,
-        .init_early = bcmring_init_early,
-        .init_irq = bcmring_init_irq,
-        .timer = &bcmring_timer,
-        .init_machine = bcmring_init_machine,
-        .restart = bcmring_restart,
-MACHINE_END
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
deleted file mode 100644
index ad237a42d265..000000000000
--- a/arch/arm/mach-bcmring/clock.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/clkdev.h>
-#include <mach/csp/hw_cfg.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_inline.h>
-#include "clock.h"
-#define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
-#define clk_is_pll1(x)          ((x)->type & CLK_TYPE_PLL1)
-#define clk_is_pll2(x)          ((x)->type & CLK_TYPE_PLL2)
-#define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
-#define clk_is_bypassable(x)    ((x)->type & CLK_TYPE_BYPASSABLE)
-#define clk_is_using_xtal(x)    ((x)->mode & CLK_MODE_XTAL)
-static DEFINE_SPINLOCK(clk_lock);
-static void __clk_enable(struct clk *clk)
-{
-        if (!clk)
-                return;
-        /* enable parent clock first */
-        if (clk->parent)
-                __clk_enable(clk->parent);
-        if (clk->use_cnt++ == 0) {
-                if (clk_is_pll1(clk)) { /* PLL1 */
-                        chipcHw_pll1Enable(clk->rate_hz, 0);
-                } else if (clk_is_pll2(clk)) {  /* PLL2 */
-                        chipcHw_pll2Enable(clk->rate_hz);
-                } else if (clk_is_using_xtal(clk)) {    /* source is crystal */
-                        if (!clk_is_primary(clk))
-                                chipcHw_bypassClockEnable(clk->csp_id);
-                } else {        /* source is PLL */
-                        chipcHw_setClockEnable(clk->csp_id);
-                }
-        }
-}
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-        if (!clk)
-                return -EINVAL;
-        spin_lock_irqsave(&clk_lock, flags);
-        __clk_enable(clk);
-        spin_unlock_irqrestore(&clk_lock, flags);
-        return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-static void __clk_disable(struct clk *clk)
-{
-        if (!clk)
-                return;
-        BUG_ON(clk->use_cnt == 0);
-        if (--clk->use_cnt == 0) {
-                if (clk_is_pll1(clk)) { /* PLL1 */
-                        chipcHw_pll1Disable();
-                } else if (clk_is_pll2(clk)) {  /* PLL2 */
-                        chipcHw_pll2Disable();
-                } else if (clk_is_using_xtal(clk)) {    /* source is crystal */
-                        if (!clk_is_primary(clk))
-                                chipcHw_bypassClockDisable(clk->csp_id);
-                } else {        /* source is PLL */
-                        chipcHw_setClockDisable(clk->csp_id);
-                }
-        }
-        if (clk->parent)
-                __clk_disable(clk->parent);
-}
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-        if (!clk)
-                return;
-        spin_lock_irqsave(&clk_lock, flags);
-        __clk_disable(clk);
-        spin_unlock_irqrestore(&clk_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-unsigned long clk_get_rate(struct clk *clk)
-{
-        if (!clk)
-                return 0;
-        return clk->rate_hz;
-}
-EXPORT_SYMBOL(clk_get_rate);
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long flags;
-        unsigned long actual;
-        unsigned long rate_hz;
-        if (!clk)
-                return -EINVAL;
-        if (!clk_is_programmable(clk))
-                return -EINVAL;
-        if (clk->use_cnt)
-                return -EBUSY;
-        spin_lock_irqsave(&clk_lock, flags);
-        actual = clk->parent->rate_hz;
-        rate_hz = min(actual, rate);
-        spin_unlock_irqrestore(&clk_lock, flags);
-        return rate_hz;
-}
-EXPORT_SYMBOL(clk_round_rate);
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long flags;
-        unsigned long actual;
-        unsigned long rate_hz;
-        if (!clk)
-                return -EINVAL;
-        if (!clk_is_programmable(clk))
-                return -EINVAL;
-        if (clk->use_cnt)
-                return -EBUSY;
-        spin_lock_irqsave(&clk_lock, flags);
-        actual = clk->parent->rate_hz;
-        rate_hz = min(actual, rate);
-        rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
-        clk->rate_hz = rate_hz;
-        spin_unlock_irqrestore(&clk_lock, flags);
-        return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-struct clk *clk_get_parent(struct clk *clk)
-{
-        if (!clk)
-                return NULL;
-        return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        unsigned long flags;
-        struct clk *old_parent;
-        if (!clk || !parent)
-                return -EINVAL;
-        if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
-                return -EINVAL;
-        /* if more than one user, parent is not allowed */
-        if (clk->use_cnt > 1)
-                return -EBUSY;
-        if (clk->parent == parent)
-                return 0;
-        spin_lock_irqsave(&clk_lock, flags);
-        old_parent = clk->parent;
-        clk->parent = parent;
-        if (clk_is_using_xtal(parent))
-                clk->mode |= CLK_MODE_XTAL;
-        else
-                clk->mode &= (~CLK_MODE_XTAL);
-        /* if clock is active */
-        if (clk->use_cnt != 0) {
-                clk->use_cnt--;
-                /* enable clock with the new parent */
-                __clk_enable(clk);
-                /* disable the old parent */
-                __clk_disable(old_parent);
-        }
-        spin_unlock_irqrestore(&clk_lock, flags);
-        return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h
deleted file mode 100644
index 5e0b98138973..000000000000
--- a/arch/arm/mach-bcmring/clock.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <mach/csp/chipcHw_def.h>
-#define CLK_TYPE_PRIMARY         1      /* primary clock must NOT have a parent */
-#define CLK_TYPE_PLL1            2      /* PPL1 */
-#define CLK_TYPE_PLL2            4      /* PPL2 */
-#define CLK_TYPE_PROGRAMMABLE    8      /* programmable clock rate */
-#define CLK_TYPE_BYPASSABLE      16     /* parent can be changed */
-#define CLK_MODE_XTAL            1      /* clock source is from crystal */
-struct clk {
-        const char *name;       /* clock name */
-        unsigned int type;      /* clock type */
-        unsigned int mode;      /* current mode */
-        volatile int use_bypass;        /* indicate if it's in bypass mode */
-        chipcHw_CLOCK_e csp_id; /* clock ID for CSP CHIPC */
-        unsigned long rate_hz;  /* clock rate in Hz */
-        unsigned int use_cnt;   /* usage count */
-        struct clk *parent;     /* parent clock */
-};
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
deleted file mode 100644
index adbfb1994582..000000000000
--- a/arch/arm/mach-bcmring/core.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- *  derived from linux/arch/arm/mach-versatile/core.c
- *  linux/arch/arm/mach-bcmring/core.c
- *
- *  Copyright (C) 1999 - 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/* Portions copyright Broadcom 2008 */
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/amba/bus.h>
-#include <linux/clkdev.h>
-#include <mach/csp/mm_addr.h>
-#include <mach/hardware.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/hardware/arm_timer.h>
-#include <asm/hardware/timer-sp.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-#include <cfg_global.h>
-#include "clock.h"
-#include <csp/secHw.h>
-#include <mach/csp/secHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <mach/csp/tmrHw_reg.h>
-static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
-static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
-static struct clk pll1_clk = {
-        .name = "PLL1",
-        .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
-        .rate_hz = 2000000000,
-        .use_cnt = 7,
-};
-static struct clk uart_clk = {
-        .name = "UART",
-        .type = CLK_TYPE_PROGRAMMABLE,
-        .csp_id = chipcHw_CLOCK_UART,
-        .rate_hz = HW_CFG_UART_CLK_HZ,
-        .parent = &pll1_clk,
-};
-static struct clk dummy_apb_pclk = {
-        .name = "BUSCLK",
-        .type = CLK_TYPE_PRIMARY,
-        .mode = CLK_MODE_XTAL,
-};
-/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically  150-166 MHz */
-#if defined(CONFIG_ARCH_FPGA11107)
-/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
-/* slow down Linux's sense of time */
-#define TIMER0_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
-#define TIMER1_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
-#define TIMER3_FREQUENCY_MHZ  (tmrHw_HIGH_FREQUENCY_MHZ * 30)
-#define TIMER3_FREQUENCY_KHZ   (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
-#else
-#define TIMER0_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
-#define TIMER1_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
-#define TIMER3_FREQUENCY_MHZ  tmrHw_HIGH_FREQUENCY_MHZ
-#define TIMER3_FREQUENCY_KHZ  (tmrHw_HIGH_FREQUENCY_HZ / 1000)
-#endif
-static struct clk sp804_timer012_clk = {
-        .name = "sp804-timer-0,1,2",
-        .type = CLK_TYPE_PRIMARY,
-        .mode = CLK_MODE_XTAL,
-        .rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
-};
-static struct clk sp804_timer3_clk = {
-        .name = "sp804-timer-3",
-        .type = CLK_TYPE_PRIMARY,
-        .mode = CLK_MODE_XTAL,
-        .rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
-};
-static struct clk_lookup lookups[] = {
-        {                       /* Bus clock */
-                .con_id = "apb_pclk",
-                .clk = &dummy_apb_pclk,
-        }, {                    /* UART0 */
-                .dev_id = "uarta",
-                .clk = &uart_clk,
-        }, {                    /* UART1 */
-                .dev_id = "uartb",
-                .clk = &uart_clk,
-        }, {                    /* SP804 timer 0 */
-                .dev_id = "sp804",
-                .con_id = "timer0",
-                .clk = &sp804_timer012_clk,
-        }, {                    /* SP804 timer 1 */
-                .dev_id = "sp804",
-                .con_id = "timer1",
-                .clk = &sp804_timer012_clk,
-        }, {                    /* SP804 timer 3 */
-                .dev_id = "sp804",
-                .con_id = "timer3",
-                .clk = &sp804_timer3_clk,
-        }
-};
-static struct amba_device *amba_devs[] __initdata = {
-        &uartA_device,
-        &uartB_device,
-};
-void __init bcmring_amba_init(void)
-{
-        int i;
-        u32 bus_clock;
-/* Linux is run initially in non-secure mode. Secure peripherals */
-/* generate FIQ, and must be handled in secure mode. Until we have */
-/* a linux security monitor implementation, keep everything in */
-/* non-secure mode. */
-        chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
-        secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
-                          secHw_BLK_MASK_KEY_SCAN |
-                          secHw_BLK_MASK_TOUCH_SCREEN |
-                          secHw_BLK_MASK_UART0 |
-                          secHw_BLK_MASK_UART1 |
-                          secHw_BLK_MASK_WATCHDOG |
-                          secHw_BLK_MASK_SPUM |
-                          secHw_BLK_MASK_DDR2 |
-                          secHw_BLK_MASK_SPU |
-                          secHw_BLK_MASK_PKA |
-                          secHw_BLK_MASK_RNG |
-                          secHw_BLK_MASK_RTC |
-                          secHw_BLK_MASK_OTP |
-                          secHw_BLK_MASK_BOOT |
-                          secHw_BLK_MASK_MPU |
-                          secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
-        /* Only the devices attached to the AMBA bus are enabled just before the bus is */
-        /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
-        /* driver to access these blocks. The bus is probed, and the drivers are loaded. */
-        /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
-        bus_clock = chipcHw_REG_BUS_CLOCK_GE
-            | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
-        chipcHw_busInterfaceClockEnable(bus_clock);
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-                struct amba_device *d = amba_devs[i];
-                amba_device_register(d, &iomem_resource);
-        }
-}
-/*
- * Where is the timer (VA)?
- */
-#define TIMER0_VA_BASE          ((void __iomem *)MM_IO_BASE_TMR)
-#define TIMER1_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x20))
-#define TIMER2_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
-#define TIMER3_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
-static int __init bcmring_clocksource_init(void)
-{
-        /* setup timer1 as free-running clocksource */
-        sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
-        /* setup timer3 as free-running clocksource */
-        sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
-        return 0;
-}
-/*
- * Set up timer interrupt, and return the current time in seconds.
- */
-void __init bcmring_init_timer(void)
-{
-        printk(KERN_INFO "bcmring_init_timer\n");
-        /*
-         * Initialise to a known state (all timers off)
-         */
-        writel(0, TIMER0_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER2_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
-        /*
-         * Make irqs happen for the system timer
-         */
-        bcmring_clocksource_init();
-        sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
-}
-struct sys_timer bcmring_timer = {
-        .init = bcmring_init_timer,
-};
-void __init bcmring_init_early(void)
-{
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-}
diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h
deleted file mode 100644
index e0e02c48f9b1..000000000000
--- a/arch/arm/mach-bcmring/core.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *  linux/arch/arm/mach-versatile/core.h
- *
- *  Copyright (C) 2004 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/* Portions copyright Broadcom 2008 */
-#ifndef __ASM_ARCH_BCMRING_H
-#define __ASM_ARCH_BCMRING_H
-void __init bcmring_amba_init(void);
-void __init bcmring_map_io(void);
-void __init bcmring_init_irq(void);
-void __init bcmring_init_early(void);
-extern struct sys_timer bcmring_timer;
-#endif
diff --git a/arch/arm/mach-bcmring/csp/Makefile b/arch/arm/mach-bcmring/csp/Makefile
deleted file mode 100644
index 648c0377530e..000000000000
--- a/arch/arm/mach-bcmring/csp/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-obj-y += dmac/
-obj-y += tmr/
-obj-y += chipc/
diff --git a/arch/arm/mach-bcmring/csp/chipc/Makefile b/arch/arm/mach-bcmring/csp/chipc/Makefile
deleted file mode 100644
index 673952768ee5..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
deleted file mode 100644
index 96273ff34956..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    chipcHw.c
-*
-*  @brief   Low level Various CHIP clock controlling routines
-*
-*  @note
-*
-*   These routines provide basic clock controlling functionality only.
-*/
-/****************************************************************************/
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <csp/reg.h>
-#include <csp/delay.h>
-/* ---- Private Constants and Types --------------------------------------- */
-/* VPM alignment algorithm uses this */
-#define MAX_PHASE_ADJUST_COUNT         0xFFFF   /* Max number of times allowed to adjust the phase */
-#define MAX_PHASE_ALIGN_ATTEMPTS       10       /* Max number of attempt to align the phase */
-/* Local definition of clock type */
-#define PLL_CLOCK                      1        /* PLL Clock */
-#define NON_PLL_CLOCK                  2        /* Divider clock */
-static int chipcHw_divide(int num, int denom)
-    __attribute__ ((section(".aramtext")));
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in hertz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock    /*  [ IN ] Configurable clock */
-    ) {
-        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-        volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
-        uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
-        uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
-        uint32_t dependentClockType = 0;
-        uint32_t vcoHz = 0;
-        /* Get VCO frequencies */
-        if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-                uint64_t adjustFreq = 0;
-                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-                /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
-                adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
-                        (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
-                        chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
-                vcoFreqPll1Hz += (uint32_t) adjustFreq;
-        } else {
-                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-        }
-        vcoFreqPll2Hz =
-            chipcHw_XTAL_FREQ_Hz *
-                 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-            ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-        switch (clock) {
-        case chipcHw_CLOCK_DDR:
-                pPLLReg = &pChipcHw->DDRClock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ARM:
-                pPLLReg = &pChipcHw->ARMClock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ESW:
-                pPLLReg = &pChipcHw->ESWClock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_VPM:
-                pPLLReg = &pChipcHw->VPMClock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ESW125:
-                pPLLReg = &pChipcHw->ESW125Clock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_UART:
-                pPLLReg = &pChipcHw->UARTClock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_SDIO0:
-                pPLLReg = &pChipcHw->SDIO0Clock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_SDIO1:
-                pPLLReg = &pChipcHw->SDIO1Clock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_SPI:
-                pPLLReg = &pChipcHw->SPIClock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ETM:
-                pPLLReg = &pChipcHw->ETMClock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_USB:
-                pPLLReg = &pChipcHw->USBClock;
-                vcoHz = vcoFreqPll2Hz;
-                break;
-        case chipcHw_CLOCK_LCD:
-                pPLLReg = &pChipcHw->LCDClock;
-                vcoHz = vcoFreqPll2Hz;
-                break;
-        case chipcHw_CLOCK_APM:
-                pPLLReg = &pChipcHw->APMClock;
-                vcoHz = vcoFreqPll2Hz;
-                break;
-        case chipcHw_CLOCK_BUS:
-                pClockCtrl = &pChipcHw->ACLKClock;
-                pDependentClock = &pChipcHw->ARMClock;
-                vcoHz = vcoFreqPll1Hz;
-                dependentClockType = PLL_CLOCK;
-                break;
-        case chipcHw_CLOCK_OTP:
-                pClockCtrl = &pChipcHw->OTPClock;
-                break;
-        case chipcHw_CLOCK_I2C:
-                pClockCtrl = &pChipcHw->I2CClock;
-                break;
-        case chipcHw_CLOCK_I2S0:
-                pClockCtrl = &pChipcHw->I2S0Clock;
-                break;
-        case chipcHw_CLOCK_RTBUS:
-                pClockCtrl = &pChipcHw->RTBUSClock;
-                pDependentClock = &pChipcHw->ACLKClock;
-                dependentClockType = NON_PLL_CLOCK;
-                break;
-        case chipcHw_CLOCK_APM100:
-                pClockCtrl = &pChipcHw->APM100Clock;
-                pDependentClock = &pChipcHw->APMClock;
-                vcoHz = vcoFreqPll2Hz;
-                dependentClockType = PLL_CLOCK;
-                break;
-        case chipcHw_CLOCK_TSC:
-                pClockCtrl = &pChipcHw->TSCClock;
-                break;
-        case chipcHw_CLOCK_LED:
-                pClockCtrl = &pChipcHw->LEDClock;
-                break;
-        case chipcHw_CLOCK_I2S1:
-                pClockCtrl = &pChipcHw->I2S1Clock;
-                break;
-        }
-        if (pPLLReg) {
-                /* Obtain PLL clock frequency */
-                if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
-                        /* Return crystal clock frequency when bypassed */
-                        return chipcHw_XTAL_FREQ_Hz;
-                } else if (clock == chipcHw_CLOCK_DDR) {
-                        /* DDR frequency is configured in PLLDivider register */
-                        return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
-                } else {
-                        /* From chip revision number B0, LCD clock is internally divided by 2 */
-                        if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
-                                vcoHz >>= 1;
-                        }
-                        /* Obtain PLL clock frequency using VCO dividers */
-                        return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
-                }
-        } else if (pClockCtrl) {
-                /* Obtain divider clock frequency */
-                uint32_t div;
-                uint32_t freq = 0;
-                if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
-                        /* Return crystal clock frequency when bypassed */
-                        return chipcHw_XTAL_FREQ_Hz;
-                } else if (pDependentClock) {
-                        /* Identify the dependent clock frequency */
-                        switch (dependentClockType) {
-                        case PLL_CLOCK:
-                                if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
-                                        /* Use crystal clock frequency when dependent PLL clock is bypassed */
-                                        freq = chipcHw_XTAL_FREQ_Hz;
-                                } else {
-                                        /* Obtain PLL clock frequency using VCO dividers */
-                                        div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
-                                        freq = div ? chipcHw_divide(vcoHz, div) : 0;
-                                }
-                                break;
-                        case NON_PLL_CLOCK:
-                                if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
-                                        freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
-                                } else {
-                                        if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
-                                                /* Use crystal clock frequency when dependent divider clock is bypassed */
-                                                freq = chipcHw_XTAL_FREQ_Hz;
-                                        } else {
-                                                /* Obtain divider clock frequency using XTAL dividers */
-                                                div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-                                                freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
-                                        }
-                                }
-                                break;
-                        }
-                } else {
-                        /* Dependent on crystal clock */
-                        freq = chipcHw_XTAL_FREQ_Hz;
-                }
-                div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-                return chipcHw_divide(freq, (div ? div : 256));
-        }
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in Hz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,   /*  [ IN ] Configurable clock */
-                                       uint32_t freq    /*  [ IN ] Clock frequency in Hz */
-    ) {
-        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-        volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
-        uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
-        uint32_t desVcoFreqPll1Hz = 0;  /* Desired VCO frequency for PLL1 in Hz */
-        uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
-        uint32_t dependentClockType = 0;
-        uint32_t vcoHz = 0;
-        uint32_t desVcoHz = 0;
-        /* Get VCO frequencies */
-        if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-                uint64_t adjustFreq = 0;
-                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-                /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
-                adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
-                        (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
-                        chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
-                vcoFreqPll1Hz += (uint32_t) adjustFreq;
-                /* Desired VCO frequency */
-                desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-                      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
-        } else {
-                vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-        }
-        vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-            ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-        switch (clock) {
-        case chipcHw_CLOCK_DDR:
-                /* Configure the DDR_ctrl:BUS ratio settings */
-                {
-                        REG_LOCAL_IRQ_SAVE;
-                        /* Dvide DDR_phy by two to obtain DDR_ctrl clock */
-                        pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-                                << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
-                        REG_LOCAL_IRQ_RESTORE;
-                }
-                pPLLReg = &pChipcHw->DDRClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ARM:
-                pPLLReg = &pChipcHw->ARMClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ESW:
-                pPLLReg = &pChipcHw->ESWClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_VPM:
-                /* Configure the VPM:BUS ratio settings */
-                {
-                        REG_LOCAL_IRQ_SAVE;
-                        pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-                                << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
-                        REG_LOCAL_IRQ_RESTORE;
-                }
-                pPLLReg = &pChipcHw->VPMClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ESW125:
-                pPLLReg = &pChipcHw->ESW125Clock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_UART:
-                pPLLReg = &pChipcHw->UARTClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_SDIO0:
-                pPLLReg = &pChipcHw->SDIO0Clock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_SDIO1:
-                pPLLReg = &pChipcHw->SDIO1Clock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_SPI:
-                pPLLReg = &pChipcHw->SPIClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ETM:
-                pPLLReg = &pChipcHw->ETMClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_USB:
-                pPLLReg = &pChipcHw->USBClock;
-                vcoHz = vcoFreqPll2Hz;
-                desVcoHz = vcoFreqPll2Hz;
-                break;
-        case chipcHw_CLOCK_LCD:
-                pPLLReg = &pChipcHw->LCDClock;
-                vcoHz = vcoFreqPll2Hz;
-                desVcoHz = vcoFreqPll2Hz;
-                break;
-        case chipcHw_CLOCK_APM:
-                pPLLReg = &pChipcHw->APMClock;
-                vcoHz = vcoFreqPll2Hz;
-                desVcoHz = vcoFreqPll2Hz;
-                break;
-        case chipcHw_CLOCK_BUS:
-                pClockCtrl = &pChipcHw->ACLKClock;
-                pDependentClock = &pChipcHw->ARMClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                dependentClockType = PLL_CLOCK;
-                break;
-        case chipcHw_CLOCK_OTP:
-                pClockCtrl = &pChipcHw->OTPClock;
-                break;
-        case chipcHw_CLOCK_I2C:
-                pClockCtrl = &pChipcHw->I2CClock;
-                break;
-        case chipcHw_CLOCK_I2S0:
-                pClockCtrl = &pChipcHw->I2S0Clock;
-                break;
-        case chipcHw_CLOCK_RTBUS:
-                pClockCtrl = &pChipcHw->RTBUSClock;
-                pDependentClock = &pChipcHw->ACLKClock;
-                dependentClockType = NON_PLL_CLOCK;
-                break;
-        case chipcHw_CLOCK_APM100:
-                pClockCtrl = &pChipcHw->APM100Clock;
-                pDependentClock = &pChipcHw->APMClock;
-                vcoHz = vcoFreqPll2Hz;
-                desVcoHz = vcoFreqPll2Hz;
-                dependentClockType = PLL_CLOCK;
-                break;
-        case chipcHw_CLOCK_TSC:
-                pClockCtrl = &pChipcHw->TSCClock;
-                break;
-        case chipcHw_CLOCK_LED:
-                pClockCtrl = &pChipcHw->LEDClock;
-                break;
-        case chipcHw_CLOCK_I2S1:
-                pClockCtrl = &pChipcHw->I2S1Clock;
-                break;
-        }
-        if (pPLLReg) {
-                /* Select XTAL as bypass source */
-                reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO);
-                reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-                /* For DDR settings use only the PLL divider clock */
-                if (pPLLReg == &pChipcHw->DDRClock) {
-                        /* Set M1DIV for PLL1, which controls the DDR clock */
-                        reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
-                        /* Calculate expected frequency */
-                        freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
-                } else {
-                        /* From chip revision number B0, LCD clock is internally divided by 2 */
-                        if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
-                                desVcoHz >>= 1;
-                                vcoHz >>= 1;
-                        }
-                        /* Set MDIV to change the frequency */
-                        reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
-                        reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
-                        /* Calculate expected frequency */
-                        freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
-                }
-                /* Wait for for atleast 200ns as per the protocol to change frequency */
-                udelay(1);
-                /* Do not bypass */
-                reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-                /* Return the configured frequency */
-                return freq;
-        } else if (pClockCtrl) {
-                uint32_t divider = 0;
-                /* Divider clock should not be bypassed  */
-                reg32_modify_and(pClockCtrl,
-                                 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-                /* Identify the clock source */
-                if (pDependentClock) {
-                        switch (dependentClockType) {
-                        case PLL_CLOCK:
-                                divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
-                                break;
-                        case NON_PLL_CLOCK:
-                                {
-                                        uint32_t sourceClock = 0;
-                                        if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
-                                                sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
-                                        } else {
-                                                uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-                                                sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
-                                        }
-                                        divider = chipcHw_divide(sourceClock, freq);
-                                }
-                                break;
-                        }
-                } else {
-                        divider = chipcHw_divide(chipcHw_XTAL_FREQ_Hz, freq);
-                }
-                if (divider) {
-                        REG_LOCAL_IRQ_SAVE;
-                        /* Set the divider to obtain the required frequency */
-                        *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK);
-                        REG_LOCAL_IRQ_RESTORE;
-                        return freq;
-                }
-        }
-        return 0;
-}
-EXPORT_SYMBOL(chipcHw_setClockFrequency);
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock for Chip Rev #A0
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success (# of adjustment required)
-*            -1 : On failure
-*
-*/
-/****************************************************************************/
-static int vpmPhaseAlignA0(void)
-{
-        uint32_t phaseControl;
-        uint32_t phaseValue;
-        uint32_t prevPhaseComp;
-        int iter = 0;
-        int adjustCount = 0;
-        int count = 0;
-        for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) {
-                phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
-                phaseValue = 0;
-                prevPhaseComp = 0;
-                /* Step 1: Look for falling PH_COMP transition */
-                /* Read the contents of VPM Clock resgister */
-                phaseValue = pChipcHw->VPMClock;
-                do {
-                        /* Store previous value of phase comparator */
-                        prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
-                        /* Change the value of PH_CTRL. */
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-                        /* Wait atleast 20 ns */
-                        udelay(1);
-                        /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                        /* Read the contents of  VPM Clock resgister. */
-                        phaseValue = pChipcHw->VPMClock;
-                        if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
-                                phaseControl = (0x3F & (phaseControl - 1));
-                        } else {
-                                /* Increment to the Phase count value for next write, if Phase is not stable. */
-                                phaseControl = (0x3F & (phaseControl + 1));
-                        }
-                        /* Count number of adjustment made */
-                        adjustCount++;
-                } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || /* Look for a transition */
-                          ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) &&  /* Look for a falling edge */
-                         (adjustCount < MAX_PHASE_ADJUST_COUNT) /* Do not exceed the limit while trying */
-                    );
-                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-                        return -1;
-                }
-                /* Step 2: Keep moving forward to make sure falling PH_COMP transition was valid */
-                for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
-                        phaseControl = (0x3F & (phaseControl + 1));
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-                        /* Wait atleast 20 ns */
-                        udelay(1);
-                        /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                        phaseValue = pChipcHw->VPMClock;
-                        /* Count number of adjustment made */
-                        adjustCount++;
-                }
-                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-                        return -1;
-                }
-                if (count != 5) {
-                        /* Detected false transition */
-                        continue;
-                }
-                /* Step 3: Keep moving backward to make sure falling PH_COMP transition was stable */
-                for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
-                        phaseControl = (0x3F & (phaseControl - 1));
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-                        /* Wait atleast 20 ns */
-                        udelay(1);
-                        /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                        phaseValue = pChipcHw->VPMClock;
-                        /* Count number of adjustment made */
-                        adjustCount++;
-                }
-                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-                        return -1;
-                }
-                if (count != 3) {
-                        /* Detected noisy transition */
-                        continue;
-                }
-                /* Step 4: Keep moving backward before the original transition took place. */
-                for (count = 0; (count < 5); count++) {
-                        phaseControl = (0x3F & (phaseControl - 1));
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-                        /* Wait atleast 20 ns */
-                        udelay(1);
-                        /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                        phaseValue = pChipcHw->VPMClock;
-                        /* Count number of adjustment made */
-                        adjustCount++;
-                }
-                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-                        return -1;
-                }
-                if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0) {
-                        /* Detected false transition */
-                        continue;
-                }
-                /* Step 5: Re discover the valid transition */
-                do {
-                        /* Store previous value of phase comparator */
-                        prevPhaseComp = phaseValue;
-                        /* Change the value of PH_CTRL. */
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-                        /* Wait atleast 20 ns */
-                        udelay(1);
-                        /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^=
-                            chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                        /* Read the contents of  VPM Clock resgister. */
-                        phaseValue = pChipcHw->VPMClock;
-                        if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
-                                phaseControl = (0x3F & (phaseControl - 1));
-                        } else {
-                                /* Increment to the Phase count value for next write, if Phase is not stable. */
-                                phaseControl = (0x3F & (phaseControl + 1));
-                        }
-                        /* Count number of adjustment made */
-                        adjustCount++;
-                } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && (adjustCount < MAX_PHASE_ADJUST_COUNT));
-                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries  */
-                        return -1;
-                } else {
-                        /* Valid phase must have detected */
-                        break;
-                }
-        }
-        /* For VPM Phase should be perfectly aligned. */
-        phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
-        {
-                REG_LOCAL_IRQ_SAVE;
-                pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT);
-                /* Load new phase value */
-                pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                REG_LOCAL_IRQ_RESTORE;
-        }
-        /* Return the status */
-        return (int)adjustCount;
-}
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success (# of adjustment required)
-*            -1 : On failure
-*
-*/
-/****************************************************************************/
-int chipcHw_vpmPhaseAlign(void)
-{
-        if (chipcHw_getChipRevisionNumber() == chipcHw_REV_NUMBER_A0) {
-                return vpmPhaseAlignA0();
-        } else {
-                uint32_t phaseControl = chipcHw_getVpmPhaseControl();
-                uint32_t phaseValue = 0;
-                int adjustCount = 0;
-                /* Disable VPM access */
-                pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-                /* Disable HW VPM phase alignment  */
-                chipcHw_vpmHwPhaseAlignDisable();
-                /* Enable SW VPM phase alignment  */
-                chipcHw_vpmSwPhaseAlignEnable();
-                /* Adjust VPM phase */
-                while (adjustCount < MAX_PHASE_ADJUST_COUNT) {
-                        phaseValue = chipcHw_getVpmHwPhaseAlignStatus();
-                        /* Adjust phase control value */
-                        if (phaseValue > 0xF) {
-                                /* Increment phase control value */
-                                phaseControl++;
-                        } else if (phaseValue < 0xF) {
-                                /* Decrement phase control value */
-                                phaseControl--;
-                        } else {
-                                /* Enable VPM access */
-                                pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-                                /* Return adjust count */
-                                return adjustCount;
-                        }
-                        /* Change the value of PH_CTRL. */
-                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-                        /* Wait atleast 20 ns */
-                        udelay(1);
-                        /* Toggle the LOAD_CH after phase control is written. */
-                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                        /* Count adjustment */
-                        adjustCount++;
-                }
-        }
-        /* Disable VPM access */
-        pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-        return -1;
-}
-/****************************************************************************/
-/**
-*  @brief   Local Divide function
-*
-*  This function does the divide
-*
-*  @return divide value
-*
-*/
-/****************************************************************************/
-static int chipcHw_divide(int num, int denom)
-{
-        int r;
-        int t = 1;
-        /* Shift denom and t up to the largest value to optimize algorithm */
-        /* t contains the units of each divide */
-        while ((denom & 0x40000000) == 0) {     /* fails if denom=0 */
-                denom = denom << 1;
-                t = t << 1;
-        }
-        /* Initialize the result */
-        r = 0;
-        do {
-                /* Determine if there exists a positive remainder */
-                if ((num - denom) >= 0) {
-                        /* Accumlate t to the result and calculate a new remainder */
-                        num = num - denom;
-                        r = r + t;
-                }
-                /* Continue to shift denom and shift t down to 0 */
-                denom = denom >> 1;
-                t = t >> 1;
-        } while (t != 0);
-        return r;
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
deleted file mode 100644
index 367df75d4bb3..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    chipcHw_init.c
-*
-*  @brief   Low level CHIPC PLL configuration functions
-*
-*  @note
-*
-*   These routines provide basic PLL controlling functionality only.
-*/
-/****************************************************************************/
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <csp/reg.h>
-#include <csp/delay.h>
-/* ---- Private Constants and Types --------------------------------------- */
-/*
-    Calculation for NDIV_i to obtain VCO frequency
-    -----------------------------------------------
-        Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f)
-        for Freq_vco = VCO_FREQ_MHz
-                Freq_ref = chipcHw_XTAL_FREQ_Hz
-                PLL_P1 = PLL_P2 = 1
-                and
-                PLL_NDIV_f = 0
-        We get:
-                PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz
-    Calculation for PLL MDIV to obtain frequency Freq_x for channel x
-    -----------------------------------------------------------------
-                Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = VCO_FREQ_MHz / PLL_MDIV_x
-                PLL_MDIV_x = VCO_FREQ_MHz / Freq_x
-*/
-/* ---- Private Variables ------------------------------------------------- */
-/****************************************************************************/
-/**
-*  @brief  Initializes the PLL2
-*
-*  This function initializes the PLL2
-*
-*/
-/****************************************************************************/
-void chipcHw_pll2Enable(uint32_t vcoFreqHz)
-{
-        uint32_t pllPreDivider2 = 0;
-        {
-                REG_LOCAL_IRQ_SAVE;
-                pChipcHw->PLLConfig2 =
-                    chipcHw_REG_PLL_CONFIG_D_RESET |
-                    chipcHw_REG_PLL_CONFIG_A_RESET;
-                pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
-                    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
-                    (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
-                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-                    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-                     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-                    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-                     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-                /* Enable CHIPC registers to control the PLL */
-                pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
-                /* Set pre divider to get desired VCO frequency */
-                pChipcHw->PLLPreDivider2 = pllPreDivider2;
-                /* Set NDIV Frac */
-                pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
-                /* This has to be removed once the default values are fixed for PLL2. */
-                pChipcHw->PLLControl12 = 0x38000700;
-                pChipcHw->PLLControl22 = 0x00000015;
-                /* Reset PLL2 */
-                if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-                        pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
-                            chipcHw_REG_PLL_CONFIG_A_RESET |
-                            chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-                } else {
-                        pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
-                            chipcHw_REG_PLL_CONFIG_A_RESET |
-                            chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-                }
-                REG_LOCAL_IRQ_RESTORE;
-        }
-        /* Insert certain amount of delay before deasserting ARESET. */
-        udelay(1);
-        {
-                REG_LOCAL_IRQ_SAVE;
-                /* Remove analog reset and Power on the PLL */
-                pChipcHw->PLLConfig2 &=
-                    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-                      chipcHw_REG_PLL_CONFIG_POWER_DOWN);
-                REG_LOCAL_IRQ_RESTORE;
-        }
-        /* Wait until PLL is locked */
-        while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
-                ;
-        {
-                REG_LOCAL_IRQ_SAVE;
-                /* Remove digital reset */
-                pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
-                REG_LOCAL_IRQ_RESTORE;
-        }
-}
-EXPORT_SYMBOL(chipcHw_pll2Enable);
-/****************************************************************************/
-/**
-*  @brief  Initializes the PLL1
-*
-*  This function initializes the PLL1
-*
-*/
-/****************************************************************************/
-void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
-{
-        uint32_t pllPreDivider = 0;
-        {
-                REG_LOCAL_IRQ_SAVE;
-                pChipcHw->PLLConfig =
-                    chipcHw_REG_PLL_CONFIG_D_RESET |
-                    chipcHw_REG_PLL_CONFIG_A_RESET;
-                /* Setting VCO frequency */
-                if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-                        pllPreDivider =
-                            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 |
-                            ((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) -
-                              1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-                            (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-                             chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-                            (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-                             chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-                } else {
-                        pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
-                            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
-                            (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
-                             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-                            (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-                             chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-                            (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-                             chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-                }
-                /* Enable CHIPC registers to control the PLL */
-                pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
-                /* Set pre divider to get desired VCO frequency */
-                pChipcHw->PLLPreDivider = pllPreDivider;
-                /* Set NDIV Frac */
-                if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-                        pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-                            chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
-                } else {
-                        pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-                            chipcHw_REG_PLL_DIVIDER_NDIV_f;
-                }
-                /* Reset PLL1 */
-                if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-                        pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-                            chipcHw_REG_PLL_CONFIG_A_RESET |
-                            chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-                } else {
-                        pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-                            chipcHw_REG_PLL_CONFIG_A_RESET |
-                            chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-                }
-                REG_LOCAL_IRQ_RESTORE;
-                /* Insert certain amount of delay before deasserting ARESET. */
-                udelay(1);
-                {
-                        REG_LOCAL_IRQ_SAVE;
-                        /* Remove analog reset and Power on the PLL */
-                        pChipcHw->PLLConfig &=
-                            ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-                              chipcHw_REG_PLL_CONFIG_POWER_DOWN);
-                        REG_LOCAL_IRQ_RESTORE;
-                }
-                /* Wait until PLL is locked */
-                while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
-                       || !(pChipcHw->
-                            PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
-                        ;
-                /* Remove digital reset */
-                {
-                        REG_LOCAL_IRQ_SAVE;
-                        pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
-                        REG_LOCAL_IRQ_RESTORE;
-                }
-        }
-}
-EXPORT_SYMBOL(chipcHw_pll1Enable);
-/****************************************************************************/
-/**
-*  @brief  Initializes the chipc module
-*
-*  This function initializes the PLLs and core system clocks
-*
-*/
-/****************************************************************************/
-void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam       /*  [ IN ] Misc chip initialization parameter */
-    ) {
-#if !(defined(__KERNEL__) && !defined(STANDALONE))
-        delay_init();
-#endif
-        /* Do not program PLL, when warm reset */
-        if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) {
-                chipcHw_pll1Enable(initParam->pllVcoFreqHz,
-                                   initParam->ssSupport);
-                chipcHw_pll2Enable(initParam->pll2VcoFreqHz);
-        } else {
-                /* Clear sticky bits */
-                chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET);
-        }
-        /* Clear sticky bits */
-        chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
-        /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
-        pChipcHw->ACLKClock =
-            (pChipcHw->
-             ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
-                                                                 armBusRatio &
-                                                                 chipcHw_REG_ACLKClock_CLK_DIV_MASK);
-        /* Set various core component frequencies. The order in which this is done is important for some. */
-        /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
-        /* frequency to find its ratio with the BUS.  Hence we must set the ARM first, followed by the BUS,  */
-        /* then VPM and RTBUS. */
-        chipcHw_setClockFrequency(chipcHw_CLOCK_ARM,
-                                  initParam->busClockFreqHz *
-                                  initParam->armBusRatio);
-        chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz);
-        chipcHw_setClockFrequency(chipcHw_CLOCK_VPM,
-                                  initParam->busClockFreqHz *
-                                  initParam->vpmBusRatio);
-        chipcHw_setClockFrequency(chipcHw_CLOCK_DDR,
-                                  initParam->busClockFreqHz *
-                                  initParam->ddrBusRatio);
-        chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS,
-                                  initParam->busClockFreqHz / 2);
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
deleted file mode 100644
index 2671d8896bbb..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <csp/intcHw.h>
-#include <csp/cache.h>
-/* ---- Private Constants and Types --------------------------------------- */
-/* ---- Private Variables ------------------------------------------------- */
-void chipcHw_reset_run_from_aram(void);
-typedef void (*RUNFUNC) (void);
-/****************************************************************************/
-/**
-*  @brief   warmReset
-*
-*  @note warmReset configures the clocks which are not reset back to the state
-*   required to execute on reset.  To do so we need to copy the code into internal
-*   memory to change the ARM clock while we are not executing from DDR.
-*/
-/****************************************************************************/
-void chipcHw_reset(uint32_t mask)
-{
-        int i = 0;
-        RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM;
-        /* Disable all interrupts */
-        intcHw_irq_disable(INTCHW_INTC0, 0xffffffff);
-        intcHw_irq_disable(INTCHW_INTC1, 0xffffffff);
-        intcHw_irq_disable(INTCHW_SINTC, 0xffffffff);
-        {
-                REG_LOCAL_IRQ_SAVE;
-                if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) {
-                        chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-                }
-                /* Bypass the PLL clocks before reboot */
-                pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
-                pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
-                /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
-                do {
-                        ((uint32_t *) MM_IO_BASE_ARAM)[i] =
-                            ((uint32_t *) &chipcHw_reset_run_from_aram)[i];
-                        i++;
-                } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f);  /* 0xe1a0f00f == asm ("mov r15, r15"); */
-                CSP_CACHE_FLUSH_ALL;
-                /* run the function from ARAM */
-                runFunc();
-                /* Code will never get here, but include it to balance REG_LOCAL_IRQ_SAVE above */
-                REG_LOCAL_IRQ_RESTORE;
-        }
-}
-/* This function must run from internal memory */
-void chipcHw_reset_run_from_aram(void)
-{
-/* Make sure, pipeline is filled with instructions coming from ARAM */
-__asm (" nop                                                            \n\t"
-                " nop                                                            \n\t"
-#if defined(__KERNEL__) && !defined(STANDALONE)
-                " MRC      p15,#0x0,r0,c1,c0,#0                                  \n\t"
-                " BIC      r0,r0,#0xd                                            \n\t"
-                " MCR      p15,#0x0,r0,c1,c0,#0                                  \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-#endif
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-/* Bypass the ARM clock and switch to XTAL clock */
-                " MOV      r2,#0x80000000                                        \n\t"
-                " LDR      r3,[r2,#8]                                            \n\t"
-                " ORR      r3,r3,#0x20000                                        \n\t"
-                " STR      r3,[r2,#8]                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-/* Issue reset */
-                " MOV      r3,#0x2                                               \n\t"
-                " STR      r3,[r2,#0x80]                                         \n\t"
-/* End here */
-                " MOV      pc,pc                                                 \n\t");
-/* 0xe1a0f00f ==  asm ("mov r15, r15"); */
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
deleted file mode 100644
index 54ad964fe94c..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*****************************************************************************
-* Copyright 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    chipcHw_str.c
-*
-*  @brief   Contains strings which are useful to linux and csp
-*
-*  @note
-*/
-/****************************************************************************/
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/chipcHw_inline.h>
-/* ---- Private Constants and Types --------------------------------------- */
-static const char *gMuxStr[] = {
-        "GPIO",                 /* 0 */
-        "KeyPad",               /* 1 */
-        "I2C-Host",             /* 2 */
-        "SPI",                  /* 3 */
-        "Uart",                 /* 4 */
-        "LED-Mtx-P",            /* 5 */
-        "LED-Mtx-S",            /* 6 */
-        "SDIO-0",               /* 7 */
-        "SDIO-1",               /* 8 */
-        "PCM",                  /* 9 */
-        "I2S",                  /* 10 */
-        "ETM",                  /* 11 */
-        "Debug",                /* 12 */
-        "Misc",                 /* 13 */
-        "0xE",                  /* 14 */
-        "0xF",                  /* 15 */
-};
-/****************************************************************************/
-/**
-*  @brief   Retrieves a string representation of the mux setting for a pin.
-*
-*  @return  Pointer to a character string.
-*/
-/****************************************************************************/
-const char *chipcHw_getGpioPinFunctionStr(int pin)
-{
-        if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) {
-                return "";
-        }
-        return gMuxStr[chipcHw_getGpioPinFunction(pin)];
-}
diff --git a/arch/arm/mach-bcmring/csp/dmac/Makefile b/arch/arm/mach-bcmring/csp/dmac/Makefile
deleted file mode 100644
index fb1104fe56b2..000000000000
--- a/arch/arm/mach-bcmring/csp/dmac/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += dmacHw.o dmacHw_extra.o
-\ No newline at end of file
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
deleted file mode 100644
index 6b9be2e98e51..000000000000
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
+++ /dev/null
@@ -1,917 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    dmacHw.c
-*
-*  @brief   Low level DMA controller driver routines
-*
-*  @note
-*
-*   These routines provide basic DMA functionality only.
-*/
-/****************************************************************************/
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/string.h>
-#include <stddef.h>
-#include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-#include <mach/csp/chipcHw_inline.h>
-/* ---- External Function Prototypes ------------------------------------- */
-/* Allocate DMA control blocks */
-dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];
-uint32_t dmaChannelCount_0 = dmacHw_MAX_CHANNEL_COUNT / 2;
-uint32_t dmaChannelCount_1 = dmacHw_MAX_CHANNEL_COUNT / 2;
-/****************************************************************************/
-/**
-*  @brief   Get maximum FIFO for a DMA channel
-*
-*  @return  Maximum allowable FIFO size
-*
-*
-*/
-/****************************************************************************/
-static uint32_t GetFifoSize(dmacHw_HANDLE_t handle      /*   [ IN ] DMA Channel handle */
-    ) {
-        uint32_t val = 0;
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        dmacHw_MISC_t *pMiscReg =
-            (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
-        switch (pCblk->channel) {
-        case 0:
-                val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
-                break;
-        case 1:
-                val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
-                break;
-        case 2:
-                val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
-                break;
-        case 3:
-                val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
-                break;
-        case 4:
-                val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
-                break;
-        case 5:
-                val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
-                break;
-        case 6:
-                val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
-                break;
-        case 7:
-                val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
-                break;
-        }
-        if (val <= 0x4) {
-                return 8 << val;
-        } else {
-                dmacHw_ASSERT(0);
-        }
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Program channel register to initiate transfer
-*
-*  @return  void
-*
-*
-*  @note
-*     - Descriptor buffer MUST ALWAYS be flushed before calling this function
-*     - This function should also be called from ISR to program the channel with
-*       pending descriptors
-*/
-/****************************************************************************/
-void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,    /*   [ IN ] DMA Channel handle */
-                             dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
-                             void *pDescriptor  /*   [ IN ] Descriptor buffer */
-    ) {
-        dmacHw_DESC_RING_t *pRing;
-        dmacHw_DESC_t *pProg;
-        dmacHw_CBLK_t *pCblk;
-        pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        pRing = dmacHw_GET_DESC_RING(pDescriptor);
-        if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-                /* Not safe yet to program the channel */
-                return;
-        }
-        if (pCblk->varDataStarted) {
-                if (pCblk->descUpdated) {
-                        pCblk->descUpdated = 0;
-                        pProg =
-                            (dmacHw_DESC_t *) ((uint32_t)
-                                               dmacHw_REG_LLP(pCblk->module,
-                                                              pCblk->channel) +
-                                               pRing->virt2PhyOffset);
-                        /* Load descriptor if not loaded */
-                        if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) {
-                                dmacHw_SET_SAR(pCblk->module, pCblk->channel,
-                                               pProg->sar);
-                                dmacHw_SET_DAR(pCblk->module, pCblk->channel,
-                                               pProg->dar);
-                                dmacHw_REG_CTL_LO(pCblk->module,
-                                                  pCblk->channel) =
-                                    pProg->ctl.lo;
-                                dmacHw_REG_CTL_HI(pCblk->module,
-                                                  pCblk->channel) =
-                                    pProg->ctl.hi;
-                        } else if (pProg == (dmacHw_DESC_t *) pRing->pEnd->llp) {
-                                /* Return as end descriptor is processed */
-                                return;
-                        } else {
-                                dmacHw_ASSERT(0);
-                        }
-                } else {
-                        return;
-                }
-        } else {
-                if (pConfig->transferMode == dmacHw_TRANSFER_MODE_PERIODIC) {
-                        /* Do not make a single chain, rather process one descriptor at a time */
-                        pProg = pRing->pHead;
-                        /* Point to the next descriptor for next iteration */
-                        dmacHw_NEXT_DESC(pRing, pHead);
-                } else {
-                        /* Return if no more pending descriptor */
-                        if (pRing->pEnd == NULL) {
-                                return;
-                        }
-                        pProg = pRing->pProg;
-                        if (pConfig->transferMode ==
-                            dmacHw_TRANSFER_MODE_CONTINUOUS) {
-                                /* Make sure a complete ring can be formed */
-                                dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pEnd->
-                                              llp == pRing->pProg);
-                                /* Make sure pProg pointing to the pHead */
-                                dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pProg ==
-                                              pRing->pHead);
-                                /* Make a complete ring */
-                                do {
-                                        pRing->pProg->ctl.lo |=
-                                            (dmacHw_REG_CTL_LLP_DST_EN |
-                                             dmacHw_REG_CTL_LLP_SRC_EN);
-                                        pRing->pProg =
-                                            (dmacHw_DESC_t *) pRing->pProg->llp;
-                                } while (pRing->pProg != pRing->pHead);
-                        } else {
-                                /* Make a single long chain */
-                                while (pRing->pProg != pRing->pEnd) {
-                                        pRing->pProg->ctl.lo |=
-                                            (dmacHw_REG_CTL_LLP_DST_EN |
-                                             dmacHw_REG_CTL_LLP_SRC_EN);
-                                        pRing->pProg =
-                                            (dmacHw_DESC_t *) pRing->pProg->llp;
-                                }
-                        }
-                }
-                /* Program the channel registers */
-                dmacHw_SET_SAR(pCblk->module, pCblk->channel, pProg->sar);
-                dmacHw_SET_DAR(pCblk->module, pCblk->channel, pProg->dar);
-                dmacHw_SET_LLP(pCblk->module, pCblk->channel,
-                               (uint32_t) pProg - pRing->virt2PhyOffset);
-                dmacHw_REG_CTL_LO(pCblk->module, pCblk->channel) =
-                    pProg->ctl.lo;
-                dmacHw_REG_CTL_HI(pCblk->module, pCblk->channel) =
-                    pProg->ctl.hi;
-                if (pRing->pEnd) {
-                        /* Remember the descriptor to use next */
-                        pRing->pProg = (dmacHw_DESC_t *) pRing->pEnd->llp;
-                }
-                /* Indicate no more pending descriptor  */
-                pRing->pEnd = (dmacHw_DESC_t *) NULL;
-        }
-        /* Start DMA operation */
-        dmacHw_DMA_START(pCblk->module, pCblk->channel);
-}
-/****************************************************************************/
-/**
-*  @brief   Initializes DMA
-*
-*  This function initializes DMA CSP driver
-*
-*  @note
-*     Must be called before using any DMA channel
-*/
-/****************************************************************************/
-void dmacHw_initDma(void)
-{
-        uint32_t i = 0;
-        dmaChannelCount_0 = dmacHw_GET_NUM_CHANNEL(0);
-        dmaChannelCount_1 = dmacHw_GET_NUM_CHANNEL(1);
-        /* Enable access to the DMA block */
-        chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC0);
-        chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC1);
-        if ((dmaChannelCount_0 + dmaChannelCount_1) > dmacHw_MAX_CHANNEL_COUNT) {
-                dmacHw_ASSERT(0);
-        }
-        memset((void *)dmacHw_gCblk, 0,
-               sizeof(dmacHw_CBLK_t) * (dmaChannelCount_0 + dmaChannelCount_1));
-        for (i = 0; i < dmaChannelCount_0; i++) {
-                dmacHw_gCblk[i].module = 0;
-                dmacHw_gCblk[i].channel = i;
-        }
-        for (i = 0; i < dmaChannelCount_1; i++) {
-                dmacHw_gCblk[i + dmaChannelCount_0].module = 1;
-                dmacHw_gCblk[i + dmaChannelCount_0].channel = i;
-        }
-}
-/****************************************************************************/
-/**
-*  @brief   Exit function for  DMA
-*
-*  This function isolates DMA from the system
-*
-*/
-/****************************************************************************/
-void dmacHw_exitDma(void)
-{
-        /* Disable access to the DMA block */
-        chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC0);
-        chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC1);
-}
-/****************************************************************************/
-/**
-*  @brief   Gets a handle to a DMA channel
-*
-*  This function returns a handle, representing a control block of a particular DMA channel
-*
-*  @return  -1       - On Failure
-*            handle  - On Success, representing a channel control block
-*
-*  @note
-*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId   /* [ IN ] DMA Channel Id */
-    ) {
-        int idx;
-        switch ((channelId >> 8)) {
-        case 0:
-                dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_0);
-                idx = (channelId & 0xff);
-                break;
-        case 1:
-                dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_1);
-                idx = dmaChannelCount_0 + (channelId & 0xff);
-                break;
-        default:
-                dmacHw_ASSERT(0);
-                return (dmacHw_HANDLE_t) -1;
-        }
-        return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[idx]);
-}
-/****************************************************************************/
-/**
-*  @brief   Initializes a DMA channel for use
-*
-*  This function initializes and resets a DMA channel for use
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_initChannel(dmacHw_HANDLE_t handle   /*   [ IN ] DMA Channel handle */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        int module = pCblk->module;
-        int channel = pCblk->channel;
-        /* Reinitialize the control block */
-        memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t));
-        pCblk->module = module;
-        pCblk->channel = channel;
-        /* Enable DMA controller */
-        dmacHw_DMA_ENABLE(pCblk->module);
-        /* Reset DMA channel */
-        dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel);
-        dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel);
-        dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel);
-        dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel);
-        /* Clear all raw interrupt status */
-        dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-        dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-        dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-        /* Mask event specific interrupts */
-        dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-        dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
-        dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-        dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-        dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief  Finds amount of memory required to form a descriptor ring
-*
-*
-*  @return   Number of bytes required to form a descriptor ring
-*
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorLen(uint32_t descCnt  /* [ IN ] Number of descriptor in the ring */
-    ) {
-        /* Need extra 4 byte to ensure 32 bit alignment  */
-        return (descCnt * sizeof(dmacHw_DESC_t)) + sizeof(dmacHw_DESC_RING_t) +
-                sizeof(uint32_t);
-}
-/****************************************************************************/
-/**
-*  @brief   Initializes descriptor ring
-*
-*  This function will initializes the descriptor ring of a DMA channel
-*
-*
-*  @return   -1 - On failure
-*             0 - On success
-*  @note
-*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
-*     - Descriptor buffer MUST be 32 bit aligned and uncached as it is
-*       accessed by ARM and DMA
-*/
-/****************************************************************************/
-int dmacHw_initDescriptor(void *pDescriptorVirt,        /*  [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
-                          uint32_t descriptorPhyAddr,   /*  [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
-                          uint32_t len, /*  [ IN ] Size of the pBuf */
-                          uint32_t num  /*  [ IN ] Number of descriptor in the ring */
-    ) {
-        uint32_t i;
-        dmacHw_DESC_RING_t *pRing;
-        dmacHw_DESC_t *pDesc;
-        /* Check the alignment of the descriptor */
-        if ((uint32_t) pDescriptorVirt & 0x00000003) {
-                dmacHw_ASSERT(0);
-                return -1;
-        }
-        /* Check if enough space has been allocated for descriptor ring */
-        if (len < dmacHw_descriptorLen(num)) {
-                return -1;
-        }
-        pRing = dmacHw_GET_DESC_RING(pDescriptorVirt);
-        pRing->pHead =
-            (dmacHw_DESC_t *) ((uint32_t) pRing + sizeof(dmacHw_DESC_RING_t));
-        pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
-        pRing->pProg = dmacHw_DESC_INIT;
-        /* Initialize link item chain, starting from the head */
-        pDesc = pRing->pHead;
-        /* Find the offset between virtual to physical address */
-        pRing->virt2PhyOffset = (uint32_t) pDescriptorVirt - descriptorPhyAddr;
-        /* Form the descriptor ring */
-        for (i = 0; i < num - 1; i++) {
-                /* Clear link list item */
-                memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
-                /* Point to the next item in the physical address */
-                pDesc->llpPhy = (uint32_t) (pDesc + 1) - pRing->virt2PhyOffset;
-                /* Point to the next item in the virtual address */
-                pDesc->llp = (uint32_t) (pDesc + 1);
-                /* Mark descriptor is ready to use */
-                pDesc->ctl.hi = dmacHw_DESC_FREE;
-                /* Look into next link list item */
-                pDesc++;
-        }
-        /* Clear last link list item */
-        memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
-        /* Last item pointing to the first item in the
-           physical address to complete the ring */
-        pDesc->llpPhy = (uint32_t) pRing->pHead - pRing->virt2PhyOffset;
-        /* Last item pointing to the first item in the
-           virtual address to complete the ring
-         */
-        pDesc->llp = (uint32_t) pRing->pHead;
-        /* Mark descriptor is ready to use */
-        pDesc->ctl.hi = dmacHw_DESC_FREE;
-        /* Set the number of descriptors in the ring */
-        pRing->num = num;
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Configure DMA channel
-*
-*  @return  0  : On success
-*           -1 : On failure
-*/
-/****************************************************************************/
-int dmacHw_configChannel(dmacHw_HANDLE_t handle,        /*   [ IN ] DMA Channel handle */
-                         dmacHw_CONFIG_t *pConfig       /*   [ IN ] Configuration settings */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        uint32_t cfgHigh = 0;
-        int srcTrSize;
-        int dstTrSize;
-        pCblk->varDataStarted = 0;
-        pCblk->userData = NULL;
-        /* Configure
-           - Burst transaction when enough data in available in FIFO
-           - AHB Access protection 1
-           - Source and destination peripheral ports
-         */
-        cfgHigh =
-            dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
-            dmacHw_SRC_PERI_INTF(pConfig->
-                                 srcPeripheralPort) |
-            dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
-        /* Set priority */
-        dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
-                                    pConfig->channelPriority);
-        if (pConfig->dstStatusRegisterAddress != 0) {
-                /* Destination status update enable */
-                cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
-                /* Configure status registers */
-                dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
-                                   pConfig->dstStatusRegisterAddress);
-        }
-        if (pConfig->srcStatusRegisterAddress != 0) {
-                /* Source status update enable */
-                cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
-                /* Source status update enable */
-                dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
-                                   pConfig->srcStatusRegisterAddress);
-        }
-        /* Configure the config high register */
-        dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;
-        /* Clear all raw interrupt status */
-        dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-        dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-        dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-        /* Configure block interrupt */
-        if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
-                dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
-        } else {
-                dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
-        }
-        /* Configure complete transfer interrupt */
-        if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
-                dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
-        } else {
-                dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-        }
-        /* Configure error interrupt */
-        if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
-                dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
-        } else {
-                dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
-        }
-        /* Configure gather register */
-        if (pConfig->srcGatherWidth) {
-                srcTrSize =
-                    dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-                if (!
-                    ((pConfig->srcGatherWidth % srcTrSize)
-                     && (pConfig->srcGatherJump % srcTrSize))) {
-                        dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
-                            ((pConfig->srcGatherWidth /
-                              srcTrSize) << 20) | (pConfig->srcGatherJump /
-                                                   srcTrSize);
-                } else {
-                        return -1;
-                }
-        }
-        /* Configure scatter register */
-        if (pConfig->dstScatterWidth) {
-                dstTrSize =
-                    dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-                if (!
-                    ((pConfig->dstScatterWidth % dstTrSize)
-                     && (pConfig->dstScatterJump % dstTrSize))) {
-                        dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
-                            ((pConfig->dstScatterWidth /
-                              dstTrSize) << 20) | (pConfig->dstScatterJump /
-                                                   dstTrSize);
-                } else {
-                        return -1;
-                }
-        }
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Indicates whether DMA transfer is in progress or completed
-*
-*  @return   DMA transfer status
-*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
-*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
-*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
-*
-*/
-/****************************************************************************/
-dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle        /*   [ IN ] DMA Channel handle */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-                return dmacHw_TRANSFER_STATUS_BUSY;
-        } else if (dmacHw_REG_INT_RAW_ERROR(pCblk->module) &
-                   (0x00000001 << pCblk->channel)) {
-                return dmacHw_TRANSFER_STATUS_ERROR;
-        }
-        return dmacHw_TRANSFER_STATUS_DONE;
-}
-/****************************************************************************/
-/**
-*  @brief   Set descriptors for known data length
-*
-*  When DMA has to work as a flow controller, this function prepares the
-*  descriptor chain to transfer data
-*
-*  from:
-*          - Memory to memory
-*          - Peripheral to memory
-*          - Memory to Peripheral
-*          - Peripheral to Peripheral
-*
-*  @return   -1 - On failure
-*             0 - On success
-*
-*/
-/****************************************************************************/
-int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
-                             void *pDescriptor, /*   [ IN ] Descriptor buffer */
-                             void *pSrcAddr,    /*   [ IN ] Source (Peripheral/Memory) address */
-                             void *pDstAddr,    /*   [ IN ] Destination (Peripheral/Memory) address */
-                             size_t dataLen     /*   [ IN ] Data length in bytes */
-    ) {
-        dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
-        dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
-        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-        dmacHw_DESC_t *pStart;
-        dmacHw_DESC_t *pProg;
-        int srcTs = 0;
-        int blkTs = 0;
-        int oddSize = 0;
-        int descCount = 0;
-        int count = 0;
-        int dstTrSize = 0;
-        int srcTrSize = 0;
-        uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
-        dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-        srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-        /* Skip Tx if buffer is NULL  or length is unknown */
-        if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
-                /* Do not initiate transfer */
-                return -1;
-        }
-        /* Ensure scatter and gather are transaction aligned */
-        if ((pConfig->srcGatherWidth % srcTrSize)
-            || (pConfig->dstScatterWidth % dstTrSize)) {
-                return -2;
-        }
-        /*
-           Background 1: DMAC can not perform DMA if source and destination addresses are
-           not properly aligned with the channel's transaction width. So, for successful
-           DMA transfer, transaction width must be set according to the alignment of the
-           source and destination address.
-         */
-        /* Adjust destination transaction width if destination address is not aligned properly */
-        dstTrWidth = pConfig->dstMaxTransactionWidth;
-        while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
-                dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
-                dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
-        }
-        /* Adjust source transaction width if source address is not aligned properly */
-        srcTrWidth = pConfig->srcMaxTransactionWidth;
-        while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
-                srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
-                srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
-        }
-        /* Find the maximum transaction per descriptor */
-        if (pConfig->maxDataPerBlock
-            && ((pConfig->maxDataPerBlock / srcTrSize) <
-                dmacHw_MAX_BLOCKSIZE)) {
-                maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
-        }
-        /* Find number of source transactions needed to complete the DMA transfer */
-        srcTs = dataLen / srcTrSize;
-        /* Find the odd number of bytes that need to be transferred as single byte transaction width */
-        if (srcTs && (dstTrSize > srcTrSize)) {
-                oddSize = dataLen % dstTrSize;
-                /* Adjust source transaction count due to "oddSize" */
-                srcTs = srcTs - (oddSize / srcTrSize);
-        } else {
-                oddSize = dataLen % srcTrSize;
-        }
-        /* Adjust "descCount" due to "oddSize" */
-        if (oddSize) {
-                descCount++;
-        }
-        /* Find the number of descriptor needed for total "srcTs" */
-        if (srcTs) {
-                descCount += ((srcTs - 1) / maxBlockSize) + 1;
-        }
-        /* Check the availability of "descCount" discriptors in the ring */
-        pProg = pRing->pHead;
-        for (count = 0; (descCount <= pRing->num) && (count < descCount);
-             count++) {
-                if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) {
-                        /* Sufficient descriptors are not available */
-                        return -3;
-                }
-                pProg = (dmacHw_DESC_t *) pProg->llp;
-        }
-        /* Remember the link list item to program the channel registers */
-        pStart = pProg = pRing->pHead;
-        /* Make a link list with "descCount(=count)" number of descriptors */
-        while (count) {
-                /* Reset channel control information */
-                pProg->ctl.lo = 0;
-                /* Enable source gather if configured */
-                if (pConfig->srcGatherWidth) {
-                        pProg->ctl.lo |= dmacHw_REG_CTL_SG_ENABLE;
-                }
-                /* Enable destination scatter if configured */
-                if (pConfig->dstScatterWidth) {
-                        pProg->ctl.lo |= dmacHw_REG_CTL_DS_ENABLE;
-                }
-                /* Set source and destination address */
-                pProg->sar = (uint32_t) pSrcAddr;
-                pProg->dar = (uint32_t) pDstAddr;
-                /* Use "devCtl" to mark that user memory need to be freed later if needed */
-                if (pProg == pRing->pHead) {
-                        pProg->devCtl = dmacHw_FREE_USER_MEMORY;
-                } else {
-                        pProg->devCtl = 0;
-                }
-                blkTs = srcTs;
-                /* Special treatmeant for last descriptor */
-                if (count == 1) {
-                        /* Mark the last descriptor */
-                        pProg->ctl.lo &=
-                            ~(dmacHw_REG_CTL_LLP_DST_EN |
-                              dmacHw_REG_CTL_LLP_SRC_EN);
-                        /* Treatment for odd data bytes */
-                        if (oddSize) {
-                                /* Adjust for single byte transaction width */
-                                switch (pConfig->transferType) {
-                                case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-                                        dstTrWidth =
-                                            dmacHw_DST_TRANSACTION_WIDTH_8;
-                                        blkTs =
-                                            (oddSize / srcTrSize) +
-                                            ((oddSize % srcTrSize) ? 1 : 0);
-                                        break;
-                                case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-                                        srcTrWidth =
-                                            dmacHw_SRC_TRANSACTION_WIDTH_8;
-                                        blkTs = oddSize;
-                                        break;
-                                case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
-                                        srcTrWidth =
-                                            dmacHw_SRC_TRANSACTION_WIDTH_8;
-                                        dstTrWidth =
-                                            dmacHw_DST_TRANSACTION_WIDTH_8;
-                                        blkTs = oddSize;
-                                        break;
-                                case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
-                                        /* Do not adjust the transaction width  */
-                                        break;
-                                }
-                        } else {
-                                srcTs -= blkTs;
-                        }
-                } else {
-                        if (srcTs / maxBlockSize) {
-                                blkTs = maxBlockSize;
-                        }
-                        /* Remaining source transactions for next iteration */
-                        srcTs -= blkTs;
-                }
-                /* Must have a valid source transactions */
-                dmacHw_ASSERT(blkTs > 0);
-                /* Set control information */
-                if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
-                        pProg->ctl.lo |= pConfig->transferType |
-                            pConfig->srcUpdate |
-                            pConfig->dstUpdate |
-                            srcTrWidth |
-                            dstTrWidth |
-                            pConfig->srcMaxBurstWidth |
-                            pConfig->dstMaxBurstWidth |
-                            pConfig->srcMasterInterface |
-                            pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-                } else {
-                        uint32_t transferType = 0;
-                        switch (pConfig->transferType) {
-                        case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-                                transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
-                                break;
-                        case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-                                transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
-                                break;
-                        default:
-                                dmacHw_ASSERT(0);
-                        }
-                        pProg->ctl.lo |= transferType |
-                            pConfig->srcUpdate |
-                            pConfig->dstUpdate |
-                            srcTrWidth |
-                            dstTrWidth |
-                            pConfig->srcMaxBurstWidth |
-                            pConfig->dstMaxBurstWidth |
-                            pConfig->srcMasterInterface |
-                            pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-                }
-                /* Set block transaction size */
-                pProg->ctl.hi = blkTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
-                /* Look for next descriptor */
-                if (count > 1) {
-                        /* Point to the next descriptor */
-                        pProg = (dmacHw_DESC_t *) pProg->llp;
-                        /* Update source and destination address for next iteration */
-                        switch (pConfig->transferType) {
-                        case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-                                if (pConfig->dstScatterWidth) {
-                                        pDstAddr =
-                                            (char *)pDstAddr +
-                                            blkTs * srcTrSize +
-                                            (((blkTs * srcTrSize) /
-                                              pConfig->dstScatterWidth) *
-                                             pConfig->dstScatterJump);
-                                } else {
-                                        pDstAddr =
-                                            (char *)pDstAddr +
-                                            blkTs * srcTrSize;
-                                }
-                                break;
-                        case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-                                if (pConfig->srcGatherWidth) {
-                                        pSrcAddr =
-                                            (char *)pDstAddr +
-                                            blkTs * srcTrSize +
-                                            (((blkTs * srcTrSize) /
-                                              pConfig->srcGatherWidth) *
-                                             pConfig->srcGatherJump);
-                                } else {
-                                        pSrcAddr =
-                                            (char *)pSrcAddr +
-                                            blkTs * srcTrSize;
-                                }
-                                break;
-                        case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
-                                if (pConfig->dstScatterWidth) {
-                                        pDstAddr =
-                                            (char *)pDstAddr +
-                                            blkTs * srcTrSize +
-                                            (((blkTs * srcTrSize) /
-                                              pConfig->dstScatterWidth) *
-                                             pConfig->dstScatterJump);
-                                } else {
-                                        pDstAddr =
-                                            (char *)pDstAddr +
-                                            blkTs * srcTrSize;
-                                }
-                                if (pConfig->srcGatherWidth) {
-                                        pSrcAddr =
-                                            (char *)pDstAddr +
-                                            blkTs * srcTrSize +
-                                            (((blkTs * srcTrSize) /
-                                              pConfig->srcGatherWidth) *
-                                             pConfig->srcGatherJump);
-                                } else {
-                                        pSrcAddr =
-                                            (char *)pSrcAddr +
-                                            blkTs * srcTrSize;
-                                }
-                                break;
-                        case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
-                                /* Do not adjust the address */
-                                break;
-                        default:
-                                dmacHw_ASSERT(0);
-                        }
-                } else {
-                        /* At the end of transfer "srcTs" must be zero */
-                        dmacHw_ASSERT(srcTs == 0);
-                }
-                count--;
-        }
-        /* Remember the descriptor to initialize the registers */
-        if (pRing->pProg == dmacHw_DESC_INIT) {
-                pRing->pProg = pStart;
-        }
-        /* Indicate that the descriptor is updated */
-        pRing->pEnd = pProg;
-        /* Head pointing to the next descriptor */
-        pRing->pHead = (dmacHw_DESC_t *) pProg->llp;
-        /* Update Tail pointer if destination is a peripheral,
-           because no one is going to read from the pTail
-         */
-        if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-                pRing->pTail = pRing->pHead;
-        }
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Provides DMA controller attributes
-*
-*
-*  @return  DMA controller attributes
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,       /*  [ IN ]  DMA Channel handle */
-                                          dmacHw_CONTROLLER_ATTRIB_e attr       /*  [ IN ]  DMA Controller attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        switch (attr) {
-        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM:
-                return dmacHw_GET_NUM_CHANNEL(pCblk->module);
-        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE:
-                return (1 <<
-                         (dmacHw_GET_MAX_BLOCK_SIZE
-                          (pCblk->module, pCblk->module) + 2)) - 8;
-        case dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM:
-                return dmacHw_GET_NUM_INTERFACE(pCblk->module);
-        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH:
-                return 32 << dmacHw_GET_CHANNEL_DATA_WIDTH(pCblk->module,
-                                                           pCblk->channel);
-        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE:
-                return GetFifoSize(handle);
-        }
-        dmacHw_ASSERT(0);
-        return 0;
-}
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
deleted file mode 100644
index a1f328357aa4..000000000000
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ /dev/null
@@ -1,1017 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    dmacHw_extra.c
-*
-*  @brief   Extra Low level DMA controller driver routines
-*
-*  @note
-*
-*   These routines provide basic DMA functionality only.
-*/
-/****************************************************************************/
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <stddef.h>
-#include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];    /* Declared in dmacHw.c */
-/* ---- External Function Prototypes ------------------------------------- */
-/* ---- Internal Use Function Prototypes --------------------------------- */
-/****************************************************************************/
-/**
-*  @brief   Overwrites data length in the descriptor
-*
-*  This function overwrites data length in the descriptor
-*
-*
-*  @return   void
-*
-*  @note
-*          This is only used for PCM channel
-*/
-/****************************************************************************/
-void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,     /*   [ IN ] Configuration settings */
-                          void *pDescriptor,    /*   [ IN ] Descriptor buffer */
-                          size_t dataLen        /*   [ IN ] Data length in bytes */
-    );
-/****************************************************************************/
-/**
-*  @brief   Helper function to display DMA registers
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static void DisplayRegisterContents(int module, /*   [ IN ] DMA Controller unit  (0-1) */
-                                    int channel,        /*   [ IN ] DMA Channel          (0-7) / -1(all) */
-                                    int (*fpPrint) (const char *, ...)  /*   [ IN ] Callback to the print function */
-    ) {
-        int chan;
-        (*fpPrint) ("Displaying register content \n\n");
-        (*fpPrint) ("Module %d: Interrupt raw transfer              0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_RAW_TRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt raw block                 0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_RAW_BLOCK(module)));
-        (*fpPrint) ("Module %d: Interrupt raw src transfer          0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_RAW_STRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt raw dst transfer          0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_RAW_DTRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt raw error                 0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_RAW_ERROR(module)));
-        (*fpPrint) ("--------------------------------------------------\n");
-        (*fpPrint) ("Module %d: Interrupt stat transfer             0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_STAT_TRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt stat block                0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_STAT_BLOCK(module)));
-        (*fpPrint) ("Module %d: Interrupt stat src transfer         0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_STAT_STRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt stat dst transfer         0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_STAT_DTRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt stat error                0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_STAT_ERROR(module)));
-        (*fpPrint) ("--------------------------------------------------\n");
-        (*fpPrint) ("Module %d: Interrupt mask transfer             0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_MASK_TRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt mask block                0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_MASK_BLOCK(module)));
-        (*fpPrint) ("Module %d: Interrupt mask src transfer         0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_MASK_STRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt mask dst transfer         0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_MASK_DTRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt mask error                0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_MASK_ERROR(module)));
-        (*fpPrint) ("--------------------------------------------------\n");
-        (*fpPrint) ("Module %d: Interrupt clear transfer            0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_TRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt clear block               0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_BLOCK(module)));
-        (*fpPrint) ("Module %d: Interrupt clear src transfer        0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_STRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt clear dst transfer        0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_DTRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt clear error               0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_ERROR(module)));
-        (*fpPrint) ("--------------------------------------------------\n");
-        (*fpPrint) ("Module %d: SW source req                       0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_REQ(module)));
-        (*fpPrint) ("Module %d: SW dest req                         0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_SW_HS_DST_REQ(module)));
-        (*fpPrint) ("Module %d: SW source signal                    0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_SGL_REQ(module)));
-        (*fpPrint) ("Module %d: SW dest signal                      0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_SW_HS_DST_SGL_REQ(module)));
-        (*fpPrint) ("Module %d: SW source last                      0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_LST_REQ(module)));
-        (*fpPrint) ("Module %d: SW dest last                        0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_SW_HS_DST_LST_REQ(module)));
-        (*fpPrint) ("--------------------------------------------------\n");
-        (*fpPrint) ("Module %d: misc config                         0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_MISC_CFG(module)));
-        (*fpPrint) ("Module %d: misc channel enable                 0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_MISC_CH_ENABLE(module)));
-        (*fpPrint) ("Module %d: misc ID                             0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_MISC_ID(module)));
-        (*fpPrint) ("Module %d: misc test                           0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_MISC_TEST(module)));
-        if (channel == -1) {
-                for (chan = 0; chan < 8; chan++) {
-                        (*fpPrint)
-                            ("--------------------------------------------------\n");
-                        (*fpPrint)
-                            ("Module %d: Channel %d Source                   0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_SAR(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Destination              0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_DAR(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d LLP                      0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_LLP(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Control (LO)             0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Control (HI)             0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Source Stats             0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Dest Stats               0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Source Stats Addr        0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Config (LO)              0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Config (HI)              0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
-                }
-        } else {
-                chan = channel;
-                (*fpPrint)
-                    ("--------------------------------------------------\n");
-                (*fpPrint)
-                    ("Module %d: Channel %d Source                   0x%X\n",
-                     module, chan, (uint32_t) (dmacHw_REG_SAR(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Destination              0x%X\n",
-                     module, chan, (uint32_t) (dmacHw_REG_DAR(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d LLP                      0x%X\n",
-                     module, chan, (uint32_t) (dmacHw_REG_LLP(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Control (LO)             0x%X\n",
-                     module, chan,
-                     (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Control (HI)             0x%X\n",
-                     module, chan,
-                     (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Source Stats             0x%X\n",
-                     module, chan, (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Dest Stats               0x%X\n",
-                     module, chan, (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Source Stats Addr        0x%X\n",
-                     module, chan,
-                     (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
-                     module, chan,
-                     (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Config (LO)              0x%X\n",
-                     module, chan,
-                     (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Config (HI)              0x%X\n",
-                     module, chan,
-                     (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
-        }
-}
-/****************************************************************************/
-/**
-*  @brief   Helper function to display descriptor ring
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static void DisplayDescRing(void *pDescriptor,  /*   [ IN ] Descriptor buffer */
-                            int (*fpPrint) (const char *, ...)  /*   [ IN ] Callback to the print function */
-    ) {
-        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-        dmacHw_DESC_t *pStart;
-        if (pRing->pHead == NULL) {
-                return;
-        }
-        pStart = pRing->pHead;
-        while ((dmacHw_DESC_t *) pStart->llp != pRing->pHead) {
-                if (pStart == pRing->pHead) {
-                        (*fpPrint) ("Head\n");
-                }
-                if (pStart == pRing->pTail) {
-                        (*fpPrint) ("Tail\n");
-                }
-                if (pStart == pRing->pProg) {
-                        (*fpPrint) ("Prog\n");
-                }
-                if (pStart == pRing->pEnd) {
-                        (*fpPrint) ("End\n");
-                }
-                if (pStart == pRing->pFree) {
-                        (*fpPrint) ("Free\n");
-                }
-                (*fpPrint) ("0x%X:\n", (uint32_t) pStart);
-                (*fpPrint) ("sar    0x%0X\n", pStart->sar);
-                (*fpPrint) ("dar    0x%0X\n", pStart->dar);
-                (*fpPrint) ("llp    0x%0X\n", pStart->llp);
-                (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
-                (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
-                (*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
-                (*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
-                (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
-                pStart = (dmacHw_DESC_t *) pStart->llp;
-        }
-        if (pStart == pRing->pHead) {
-                (*fpPrint) ("Head\n");
-        }
-        if (pStart == pRing->pTail) {
-                (*fpPrint) ("Tail\n");
-        }
-        if (pStart == pRing->pProg) {
-                (*fpPrint) ("Prog\n");
-        }
-        if (pStart == pRing->pEnd) {
-                (*fpPrint) ("End\n");
-        }
-        if (pStart == pRing->pFree) {
-                (*fpPrint) ("Free\n");
-        }
-        (*fpPrint) ("0x%X:\n", (uint32_t) pStart);
-        (*fpPrint) ("sar    0x%0X\n", pStart->sar);
-        (*fpPrint) ("dar    0x%0X\n", pStart->dar);
-        (*fpPrint) ("llp    0x%0X\n", pStart->llp);
-        (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
-        (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
-        (*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
-        (*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
-        (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
-}
-/****************************************************************************/
-/**
-*  @brief   Check if DMA channel is the flow controller
-*
-*  @return  1 : If DMA is a flow controller
-*           0 : Peripheral is the flow controller
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline int DmaIsFlowController(void *pDescriptor /*   [ IN ] Descriptor buffer */
-    ) {
-        uint32_t ttfc =
-            (dmacHw_GET_DESC_RING(pDescriptor))->pTail->ctl.
-            lo & dmacHw_REG_CTL_TTFC_MASK;
-        switch (ttfc) {
-        case dmacHw_REG_CTL_TTFC_MM_DMAC:
-        case dmacHw_REG_CTL_TTFC_MP_DMAC:
-        case dmacHw_REG_CTL_TTFC_PM_DMAC:
-        case dmacHw_REG_CTL_TTFC_PP_DMAC:
-                return 1;
-        }
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Overwrites data length in the descriptor
-*
-*  This function overwrites data length in the descriptor
-*
-*
-*  @return   void
-*
-*  @note
-*          This is only used for PCM channel
-*/
-/****************************************************************************/
-void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,     /*   [ IN ] Configuration settings */
-                          void *pDescriptor,    /*   [ IN ] Descriptor buffer */
-                          size_t dataLen        /*   [ IN ] Data length in bytes */
-    ) {
-        dmacHw_DESC_t *pProg;
-        dmacHw_DESC_t *pHead;
-        int srcTs = 0;
-        int srcTrSize = 0;
-        pHead = (dmacHw_GET_DESC_RING(pDescriptor))->pHead;
-        pProg = pHead;
-        srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-        srcTs = dataLen / srcTrSize;
-        do {
-                pProg->ctl.hi = srcTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
-                pProg = (dmacHw_DESC_t *) pProg->llp;
-        } while (pProg != pHead);
-}
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the DMA channel specific interrupt
-*
-*
-*  @return   void
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle       /* [ IN ] DMA Channel handle */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-        dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-        dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-}
-/****************************************************************************/
-/**
-*  @brief   Returns the cause of channel specific DMA interrupt
-*
-*  This function returns the cause of interrupt
-*
-*  @return  Interrupt status, each bit representing a specific type of interrupt
-*
-*  @note
-*     Should be called under the context of ISR
-*/
-/****************************************************************************/
-dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle      /* [ IN ] DMA Channel handle */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        dmacHw_INTERRUPT_STATUS_e status = dmacHw_INTERRUPT_STATUS_NONE;
-        if (dmacHw_REG_INT_STAT_TRAN(pCblk->module) &
-            ((0x00000001 << pCblk->channel))) {
-                status |= dmacHw_INTERRUPT_STATUS_TRANS;
-        }
-        if (dmacHw_REG_INT_STAT_BLOCK(pCblk->module) &
-            ((0x00000001 << pCblk->channel))) {
-                status |= dmacHw_INTERRUPT_STATUS_BLOCK;
-        }
-        if (dmacHw_REG_INT_STAT_ERROR(pCblk->module) &
-            ((0x00000001 << pCblk->channel))) {
-                status |= dmacHw_INTERRUPT_STATUS_ERROR;
-        }
-        return status;
-}
-/****************************************************************************/
-/**
-*  @brief   Indentifies a DMA channel causing interrupt
-*
-*  This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
-*
-*  @return  NULL   : No channel causing DMA interrupt
-*           ! NULL : Handle to a channel causing DMA interrupt
-*  @note
-*     dmacHw_clearInterrupt() must be called with a valid handle after calling this function
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getInterruptSource(void)
-{
-        uint32_t i;
-        for (i = 0; i < dmaChannelCount_0 + dmaChannelCount_1; i++) {
-                if ((dmacHw_REG_INT_STAT_TRAN(dmacHw_gCblk[i].module) &
-                     ((0x00000001 << dmacHw_gCblk[i].channel)))
-                    || (dmacHw_REG_INT_STAT_BLOCK(dmacHw_gCblk[i].module) &
-                        ((0x00000001 << dmacHw_gCblk[i].channel)))
-                    || (dmacHw_REG_INT_STAT_ERROR(dmacHw_gCblk[i].module) &
-                        ((0x00000001 << dmacHw_gCblk[i].channel)))
-                    ) {
-                        return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[i]);
-                }
-        }
-        return dmacHw_CBLK_TO_HANDLE(NULL);
-}
-/****************************************************************************/
-/**
-*  @brief  Estimates number of descriptor needed to perform certain DMA transfer
-*
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor count
-*
-*
-*/
-/****************************************************************************/
-int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,   /*   [ IN ] Configuration settings */
-                                    void *pSrcAddr,     /*   [ IN ] Source (Peripheral/Memory) address */
-                                    void *pDstAddr,     /*   [ IN ] Destination (Peripheral/Memory) address */
-                                    size_t dataLen      /*   [ IN ] Data length in bytes */
-    ) {
-        int srcTs = 0;
-        int oddSize = 0;
-        int descCount = 0;
-        int dstTrSize = 0;
-        int srcTrSize = 0;
-        uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
-        dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
-        dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
-        dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-        srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-        /* Skip Tx if buffer is NULL  or length is unknown */
-        if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
-                /* Do not initiate transfer */
-                return -1;
-        }
-        /* Ensure scatter and gather are transaction aligned */
-        if (pConfig->srcGatherWidth % srcTrSize
-            || pConfig->dstScatterWidth % dstTrSize) {
-                return -1;
-        }
-        /*
-           Background 1: DMAC can not perform DMA if source and destination addresses are
-           not properly aligned with the channel's transaction width. So, for successful
-           DMA transfer, transaction width must be set according to the alignment of the
-           source and destination address.
-         */
-        /* Adjust destination transaction width if destination address is not aligned properly */
-        dstTrWidth = pConfig->dstMaxTransactionWidth;
-        while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
-                dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
-                dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
-        }
-        /* Adjust source transaction width if source address is not aligned properly */
-        srcTrWidth = pConfig->srcMaxTransactionWidth;
-        while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
-                srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
-                srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
-        }
-        /* Find the maximum transaction per descriptor */
-        if (pConfig->maxDataPerBlock
-            && ((pConfig->maxDataPerBlock / srcTrSize) <
-                dmacHw_MAX_BLOCKSIZE)) {
-                maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
-        }
-        /* Find number of source transactions needed to complete the DMA transfer */
-        srcTs = dataLen / srcTrSize;
-        /* Find the odd number of bytes that need to be transferred as single byte transaction width */
-        if (srcTs && (dstTrSize > srcTrSize)) {
-                oddSize = dataLen % dstTrSize;
-                /* Adjust source transaction count due to "oddSize" */
-                srcTs = srcTs - (oddSize / srcTrSize);
-        } else {
-                oddSize = dataLen % srcTrSize;
-        }
-        /* Adjust "descCount" due to "oddSize" */
-        if (oddSize) {
-                descCount++;
-        }
-        /* Find the number of descriptor needed for total "srcTs" */
-        if (srcTs) {
-                descCount += ((srcTs - 1) / maxBlockSize) + 1;
-        }
-        return descCount;
-}
-/****************************************************************************/
-/**
-*  @brief   Check the existence of pending descriptor
-*
-*  This function confirmes if there is any pending descriptor in the chain
-*  to program the channel
-*
-*  @return  1 : Channel need to be programmed with pending descriptor
-*           0 : No more pending descriptor to programe the channel
-*
-*  @note
-*     - This function should be called from ISR in case there are pending
-*       descriptor to program the channel.
-*
-*     Example:
-*
-*     dmac_isr ()
-*     {
-*         ...
-*         if (dmacHw_descriptorPending (handle))
-*         {
-*            dmacHw_initiateTransfer (handle);
-*         }
-*     }
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,       /*   [ IN ] DMA Channel handle */
-                                  void *pDescriptor     /*   [ IN ] Descriptor buffer */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-        /* Make sure channel is not busy */
-        if (!CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-                /* Check if pEnd is not processed */
-                if (pRing->pEnd) {
-                        /* Something left for processing */
-                        return 1;
-                }
-        }
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Program channel register to stop transfer
-*
-*  Ensures the channel is not doing any transfer after calling this function
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /*   [ IN ] DMA Channel handle */
-    ) {
-        dmacHw_CBLK_t *pCblk;
-        pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        /* Stop the channel */
-        dmacHw_DMA_STOP(pCblk->module, pCblk->channel);
-}
-/****************************************************************************/
-/**
-*  @brief   Deallocates source or destination memory, allocated
-*
-*  This function can be called to deallocate data memory that was DMAed successfully
-*
-*  @return  On failure : -1
-*           On success : Number of buffer freed
-*
-*  @note
-*     This function will be called ONLY, when source OR destination address is pointing
-*     to dynamic memory
-*/
-/****************************************************************************/
-int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,    /*   [ IN ] Configuration settings */
-                   void *pDescriptor,   /*   [ IN ] Descriptor buffer */
-                   void (*fpFree) (void *)      /*   [ IN ] Function pointer to free data memory */
-    ) {
-        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-        uint32_t count = 0;
-        if (fpFree == NULL) {
-                return -1;
-        }
-        while ((pRing->pFree != pRing->pTail)
-               && (pRing->pFree->ctl.lo & dmacHw_DESC_FREE)) {
-                if (pRing->pFree->devCtl == dmacHw_FREE_USER_MEMORY) {
-                        /* Identify, which memory to free */
-                        if (dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-                                (*fpFree) ((void *)pRing->pFree->dar);
-                        } else {
-                                /* Destination was a peripheral */
-                                (*fpFree) ((void *)pRing->pFree->sar);
-                        }
-                        /* Unmark user memory to indicate it is freed */
-                        pRing->pFree->devCtl = ~dmacHw_FREE_USER_MEMORY;
-                }
-                dmacHw_NEXT_DESC(pRing, pFree);
-                count++;
-        }
-        return count;
-}
-/****************************************************************************/
-/**
-*  @brief   Prepares descriptor ring, when source peripheral working as a flow controller
-*
-*  This function will update the discriptor ring by allocating buffers, when source peripheral
-*  has to work as a flow controller to transfer data from:
-*           - Peripheral to memory.
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor updated
-*
-*
-*  @note
-*     Channel must be configured for peripheral to memory transfer
-*
-*/
-/****************************************************************************/
-int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,    /*   [ IN ] DMA Channel handle */
-                                     dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
-                                     void *pDescriptor, /*   [ IN ] Descriptor buffer */
-                                     uint32_t srcAddr,  /*   [ IN ] Source peripheral address */
-                                     void *(*fpAlloc) (int len),        /*   [ IN ] Function pointer  that provides destination memory */
-                                     int len,   /*   [ IN ] Number of bytes "fpAlloc" will allocate for destination */
-                                     int num    /*   [ IN ] Number of descriptor to set */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        dmacHw_DESC_t *pProg = NULL;
-        dmacHw_DESC_t *pLast = NULL;
-        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-        uint32_t dstAddr;
-        uint32_t controlParam;
-        int i;
-        dmacHw_ASSERT(pConfig->transferType ==
-                      dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM);
-        if (num > pRing->num) {
-                return -1;
-        }
-        pLast = pRing->pEnd;    /* Last descriptor updated */
-        pProg = pRing->pHead;   /* First descriptor in the new list */
-        controlParam = pConfig->srcUpdate |
-            pConfig->dstUpdate |
-            pConfig->srcMaxTransactionWidth |
-            pConfig->dstMaxTransactionWidth |
-            pConfig->srcMasterInterface |
-            pConfig->dstMasterInterface |
-            pConfig->srcMaxBurstWidth |
-            pConfig->dstMaxBurstWidth |
-            dmacHw_REG_CTL_TTFC_PM_PERI |
-            dmacHw_REG_CTL_LLP_DST_EN |
-            dmacHw_REG_CTL_LLP_SRC_EN | dmacHw_REG_CTL_INT_EN;
-        for (i = 0; i < num; i++) {
-                /* Allocate Rx buffer only for idle descriptor */
-                if (((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) ||
-                    ((dmacHw_DESC_t *) pRing->pHead->llp == pRing->pTail)
-                    ) {
-                        /* Rx descriptor is not idle */
-                        break;
-                }
-                /* Set source address */
-                pRing->pHead->sar = srcAddr;
-                if (fpAlloc) {
-                        /* Allocate memory for buffer in descriptor */
-                        dstAddr = (uint32_t) (*fpAlloc) (len);
-                        /* Check the destination address */
-                        if (dstAddr == 0) {
-                                if (i == 0) {
-                                        /* Not a single descriptor is available */
-                                        return -1;
-                                }
-                                break;
-                        }
-                        /* Set destination address */
-                        pRing->pHead->dar = dstAddr;
-                }
-                /* Set control information */
-                pRing->pHead->ctl.lo = controlParam;
-                /* Use "devCtl" to mark the memory that need to be freed later */
-                pRing->pHead->devCtl = dmacHw_FREE_USER_MEMORY;
-                /* Descriptor is now owned by the channel */
-                pRing->pHead->ctl.hi = 0;
-                /* Remember the descriptor last updated */
-                pRing->pEnd = pRing->pHead;
-                /* Update next descriptor */
-                dmacHw_NEXT_DESC(pRing, pHead);
-        }
-        /* Mark the end of the list */
-        pRing->pEnd->ctl.lo &=
-            ~(dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN);
-        /* Connect the list */
-        if (pLast != pProg) {
-                pLast->ctl.lo |=
-                    dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN;
-        }
-        /* Mark the descriptors are updated */
-        pCblk->descUpdated = 1;
-        if (!pCblk->varDataStarted) {
-                /* LLP must be pointing to the first descriptor */
-                dmacHw_SET_LLP(pCblk->module, pCblk->channel,
-                               (uint32_t) pProg - pRing->virt2PhyOffset);
-                /* Channel, handling variable data started */
-                pCblk->varDataStarted = 1;
-        }
-        return i;
-}
-/****************************************************************************/
-/**
-*  @brief   Read data DMAed to memory
-*
-*  This function will read data that has been DMAed to memory while transferring from:
-*          - Memory to memory
-*          - Peripheral to memory
-*
-*  @param    handle     -
-*  @param    ppBbuf     -
-*  @param    pLen       -
-*
-*  @return  0 - No more data is available to read
-*           1 - More data might be available to read
-*
-*/
-/****************************************************************************/
-int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle */
-                               dmacHw_CONFIG_t *pConfig,        /*   [ IN ]  Configuration settings */
-                               void *pDescriptor,       /*   [ IN ] Descriptor buffer */
-                               void **ppBbuf,   /*   [ OUT ] Data received */
-                               size_t *pLlen    /*   [ OUT ] Length of the data received */
-    ) {
-        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-        (void)handle;
-        if (pConfig->transferMode != dmacHw_TRANSFER_MODE_CONTINUOUS) {
-                if (((pRing->pTail->ctl.hi & dmacHw_DESC_FREE) == 0) ||
-                    (pRing->pTail == pRing->pHead)
-                    ) {
-                        /* No receive data available */
-                        *ppBbuf = (char *)NULL;
-                        *pLlen = 0;
-                        return 0;
-                }
-        }
-        /* Return read buffer and length */
-        *ppBbuf = (char *)pRing->pTail->dar;
-        /* Extract length of the received data */
-        if (DmaIsFlowController(pDescriptor)) {
-                uint32_t srcTrSize = 0;
-                switch (pRing->pTail->ctl.lo & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
-                case dmacHw_REG_CTL_SRC_TR_WIDTH_8:
-                        srcTrSize = 1;
-                        break;
-                case dmacHw_REG_CTL_SRC_TR_WIDTH_16:
-                        srcTrSize = 2;
-                        break;
-                case dmacHw_REG_CTL_SRC_TR_WIDTH_32:
-                        srcTrSize = 4;
-                        break;
-                case dmacHw_REG_CTL_SRC_TR_WIDTH_64:
-                        srcTrSize = 8;
-                        break;
-                default:
-                        dmacHw_ASSERT(0);
-                }
-                /* Calculate length from the block size */
-                *pLlen =
-                    (pRing->pTail->ctl.hi & dmacHw_REG_CTL_BLOCK_TS_MASK) *
-                    srcTrSize;
-        } else {
-                /* Extract length from the source peripheral */
-                *pLlen = pRing->pTail->sstat;
-        }
-        /* Advance tail to next descriptor */
-        dmacHw_NEXT_DESC(pRing, pTail);
-        return 1;
-}
-/****************************************************************************/
-/**
-*  @brief   Set descriptor carrying control information
-*
-*  This function will be used to send specific control information to the device
-*  using the DMA channel
-*
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,       /*   [ IN ] Configuration settings */
-                                void *pDescriptor,      /*   [ IN ] Descriptor buffer */
-                                uint32_t ctlAddress,    /*   [ IN ] Address of the device control register */
-                                uint32_t control        /*   [ IN ] Device control information */
-    ) {
-        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-        if (ctlAddress == 0) {
-                return -1;
-        }
-        /* Check the availability of descriptors in the ring */
-        if ((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) {
-                return -1;
-        }
-        /* Set control information */
-        pRing->pHead->devCtl = control;
-        /* Set source and destination address */
-        pRing->pHead->sar = (uint32_t) &pRing->pHead->devCtl;
-        pRing->pHead->dar = ctlAddress;
-        /* Set control parameters */
-        if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
-                pRing->pHead->ctl.lo = pConfig->transferType |
-                    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
-                    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
-                    dmacHw_SRC_TRANSACTION_WIDTH_32 |
-                    pConfig->dstMaxTransactionWidth |
-                    dmacHw_SRC_BURST_WIDTH_0 |
-                    dmacHw_DST_BURST_WIDTH_0 |
-                    pConfig->srcMasterInterface |
-                    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-        } else {
-                uint32_t transferType = 0;
-                switch (pConfig->transferType) {
-                case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-                        transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
-                        break;
-                case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-                        transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
-                        break;
-                default:
-                        dmacHw_ASSERT(0);
-                }
-                pRing->pHead->ctl.lo = transferType |
-                    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
-                    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
-                    dmacHw_SRC_TRANSACTION_WIDTH_32 |
-                    pConfig->dstMaxTransactionWidth |
-                    dmacHw_SRC_BURST_WIDTH_0 |
-                    dmacHw_DST_BURST_WIDTH_0 |
-                    pConfig->srcMasterInterface |
-                    pConfig->dstMasterInterface |
-                    pConfig->flowControler | dmacHw_REG_CTL_INT_EN;
-        }
-        /* Set block transaction size to one 32 bit transaction */
-        pRing->pHead->ctl.hi = dmacHw_REG_CTL_BLOCK_TS_MASK & 1;
-        /* Remember the descriptor to initialize the registers */
-        if (pRing->pProg == dmacHw_DESC_INIT) {
-                pRing->pProg = pRing->pHead;
-        }
-        pRing->pEnd = pRing->pHead;
-        /* Advance the descriptor */
-        dmacHw_NEXT_DESC(pRing, pHead);
-        /* Update Tail pointer if destination is a peripheral */
-        if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-                pRing->pTail = pRing->pHead;
-        }
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Sets channel specific user data
-*
-*  This function associates user data to a specific DMA channel
-*
-*/
-/****************************************************************************/
-void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle */
-                               void *userData   /*  [ IN ] User data */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        pCblk->userData = userData;
-}
-/****************************************************************************/
-/**
-*  @brief   Gets channel specific user data
-*
-*  This function returns user data specific to a DMA channel
-*
-*  @return   user data
-*/
-/****************************************************************************/
-void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle  /*  [ IN ] DMA Channel handle */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        return pCblk->userData;
-}
-/****************************************************************************/
-/**
-*  @brief   Resets descriptor control information
-*
-*  @return  void
-*/
-/****************************************************************************/
-void dmacHw_resetDescriptorControl(void *pDescriptor    /*   [ IN ] Descriptor buffer  */
-    ) {
-        int i;
-        dmacHw_DESC_RING_t *pRing;
-        dmacHw_DESC_t *pDesc;
-        pRing = dmacHw_GET_DESC_RING(pDescriptor);
-        pDesc = pRing->pHead;
-        for (i = 0; i < pRing->num; i++) {
-                /* Mark descriptor is ready to use */
-                pDesc->ctl.hi = dmacHw_DESC_FREE;
-                /* Look into next link list item */
-                pDesc++;
-        }
-        pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
-        pRing->pProg = dmacHw_DESC_INIT;
-}
-/****************************************************************************/
-/**
-*  @brief   Displays channel specific registers and other control parameters
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,      /*  [ IN ] DMA Channel handle */
-                           void *pDescriptor,   /*   [ IN ] Descriptor buffer */
-                           int (*fpPrint) (const char *, ...)   /*  [ IN ] Print callback function */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        DisplayRegisterContents(pCblk->module, pCblk->channel, fpPrint);
-        DisplayDescRing(pDescriptor, fpPrint);
-}
diff --git a/arch/arm/mach-bcmring/csp/tmr/Makefile b/arch/arm/mach-bcmring/csp/tmr/Makefile
deleted file mode 100644
index 244a61ab7697..000000000000
--- a/arch/arm/mach-bcmring/csp/tmr/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += tmrHw.o
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
deleted file mode 100644
index 16225e43f3c3..000000000000
--- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    tmrHw.c
-*
-*  @brief   Low level Timer driver routines
-*
-*  @note
-*
-*   These routines provide basic timer functionality only.
-*/
-/****************************************************************************/
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/tmrHw.h>
-#include <mach/csp/tmrHw_reg.h>
-#define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
-#define tmrHw_MILLISEC_PER_SEC              (1000)
-#define tmrHw_LOW_1_RESOLUTION_COUNT        (tmrHw_LOW_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
-#define tmrHw_LOW_1_MAX_MILLISEC            (0xFFFFFFFF / tmrHw_LOW_1_RESOLUTION_COUNT)
-#define tmrHw_LOW_16_RESOLUTION_COUNT       (tmrHw_LOW_1_RESOLUTION_COUNT / 16)
-#define tmrHw_LOW_16_MAX_MILLISEC           (0xFFFFFFFF / tmrHw_LOW_16_RESOLUTION_COUNT)
-#define tmrHw_LOW_256_RESOLUTION_COUNT      (tmrHw_LOW_1_RESOLUTION_COUNT / 256)
-#define tmrHw_LOW_256_MAX_MILLISEC          (0xFFFFFFFF / tmrHw_LOW_256_RESOLUTION_COUNT)
-#define tmrHw_HIGH_1_RESOLUTION_COUNT       (tmrHw_HIGH_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
-#define tmrHw_HIGH_1_MAX_MILLISEC           (0xFFFFFFFF / tmrHw_HIGH_1_RESOLUTION_COUNT)
-#define tmrHw_HIGH_16_RESOLUTION_COUNT      (tmrHw_HIGH_1_RESOLUTION_COUNT / 16)
-#define tmrHw_HIGH_16_MAX_MILLISEC          (0xFFFFFFFF / tmrHw_HIGH_16_RESOLUTION_COUNT)
-#define tmrHw_HIGH_256_RESOLUTION_COUNT     (tmrHw_HIGH_1_RESOLUTION_COUNT / 256)
-#define tmrHw_HIGH_256_MAX_MILLISEC         (0xFFFFFFFF / tmrHw_HIGH_256_RESOLUTION_COUNT)
-static void ResetTimer(tmrHw_ID_t timerId)
-    __attribute__ ((section(".aramtext")));
-static int tmrHw_divide(int num, int denom)
-    __attribute__ ((section(".aramtext")));
-/****************************************************************************/
-/**
-*  @brief   Get timer capability
-*
-*  This function returns various capabilities/attributes of a timer
-*
-*  @return  Capability
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,   /*  [ IN ] Timer Id */
-                                  tmrHw_CAPABILITY_e capability /*  [ IN ] Timer capability */
-) {
-        switch (capability) {
-        case tmrHw_CAPABILITY_CLOCK:
-                return (timerId <=
-                        1) ? tmrHw_LOW_RESOLUTION_CLOCK :
-                    tmrHw_HIGH_RESOLUTION_CLOCK;
-        case tmrHw_CAPABILITY_RESOLUTION:
-                return 32;
-        default:
-                return 0;
-        }
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Resets a timer
-*
-*  This function initializes  timer
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-static void ResetTimer(tmrHw_ID_t timerId       /*  [ IN ] Timer Id */
-) {
-        /* Reset timer */
-        pTmrHw[timerId].LoadValue = 0;
-        pTmrHw[timerId].CurrentValue = 0xFFFFFFFF;
-        pTmrHw[timerId].Control = 0;
-        pTmrHw[timerId].BackgroundLoad = 0;
-        /* Always configure as a 32 bit timer */
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT;
-        /* Clear interrupt only if raw status interrupt is set */
-        if (pTmrHw[timerId].RawInterruptStatus) {
-                pTmrHw[timerId].InterruptClear = 0xFFFFFFFF;
-        }
-}
-/****************************************************************************/
-/**
-*  @brief   Sets counter value for an interval in ms
-*
-*  @return   On success: Effective counter value set
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-static tmrHw_INTERVAL_t SetTimerPeriod(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
-                                       tmrHw_INTERVAL_t msec    /*  [ IN ] Interval in milli-second */
-) {
-        uint32_t scale = 0;
-        uint32_t count = 0;
-        if (timerId == 0 || timerId == 1) {
-                if (msec <= tmrHw_LOW_1_MAX_MILLISEC) {
-                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-                        scale = tmrHw_LOW_1_RESOLUTION_COUNT;
-                } else if (msec <= tmrHw_LOW_16_MAX_MILLISEC) {
-                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-                        scale = tmrHw_LOW_16_RESOLUTION_COUNT;
-                } else if (msec <= tmrHw_LOW_256_MAX_MILLISEC) {
-                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-                        scale = tmrHw_LOW_256_RESOLUTION_COUNT;
-                } else {
-                        return 0;
-                }
-                count = msec * scale;
-                /* Set counter value */
-                pTmrHw[timerId].LoadValue = count;
-                pTmrHw[timerId].BackgroundLoad = count;
-        } else if (timerId == 2 || timerId == 3) {
-                if (msec <= tmrHw_HIGH_1_MAX_MILLISEC) {
-                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-                        scale = tmrHw_HIGH_1_RESOLUTION_COUNT;
-                } else if (msec <= tmrHw_HIGH_16_MAX_MILLISEC) {
-                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-                        scale = tmrHw_HIGH_16_RESOLUTION_COUNT;
-                } else if (msec <= tmrHw_HIGH_256_MAX_MILLISEC) {
-                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-                        scale = tmrHw_HIGH_256_RESOLUTION_COUNT;
-                } else {
-                        return 0;
-                }
-                count = msec * scale;
-                /* Set counter value */
-                pTmrHw[timerId].LoadValue = count;
-                pTmrHw[timerId].BackgroundLoad = count;
-        }
-        return count / scale;
-}
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer in terms of timer interrupt rate
-*
-*  This function initializes a periodic timer to generate specific number of
-*  timer interrupt per second
-*
-*  @return   On success: Effective timer frequency
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
-                                        tmrHw_RATE_t rate       /*  [ IN ] Number of timer interrupt per second */
-) {
-        uint32_t resolution = 0;
-        uint32_t count = 0;
-        ResetTimer(timerId);
-        /* Set timer mode periodic */
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-        /* Set timer in highest resolution */
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-        if (rate && (timerId == 0 || timerId == 1)) {
-                if (rate > tmrHw_LOW_RESOLUTION_CLOCK) {
-                        return 0;
-                }
-                resolution = tmrHw_LOW_RESOLUTION_CLOCK;
-        } else if (rate && (timerId == 2 || timerId == 3)) {
-                if (rate > tmrHw_HIGH_RESOLUTION_CLOCK) {
-                        return 0;
-                } else {
-                        resolution = tmrHw_HIGH_RESOLUTION_CLOCK;
-                }
-        } else {
-                return 0;
-        }
-        /* Find the counter value */
-        count = resolution / rate;
-        /* Set counter value */
-        pTmrHw[timerId].LoadValue = count;
-        pTmrHw[timerId].BackgroundLoad = count;
-        return resolution / count;
-}
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt after
-*           certain time interval
-*
-*  This function initializes a periodic timer to generate timer interrupt
-*  after every time interval in millisecond
-*
-*  @return   On success: Effective interval set in milli-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
-                                                tmrHw_INTERVAL_t msec   /*  [ IN ] Interval in milli-second */
-) {
-        ResetTimer(timerId);
-        /* Set timer mode periodic */
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-        return SetTimerPeriod(timerId, msec);
-}
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt just once
-*           after certain time interval
-*
-*  This function initializes a periodic timer to generate a single ticks after
-*  certain time interval in millisecond
-*
-*  @return   On success: Effective interval set in milli-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
-                                               tmrHw_INTERVAL_t msec    /*  [ IN ] Interval in milli-second */
-) {
-        ResetTimer(timerId);
-        /* Set timer mode oneshot */
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_ONESHOT;
-        return SetTimerPeriod(timerId, msec);
-}
-/****************************************************************************/
-/**
-*  @brief   Configures a timer to run as a free running timer
-*
-*  This function initializes a timer to run as a free running timer
-*
-*  @return   Timer resolution (count / sec)
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
-                                       uint32_t divider /*  [ IN ] Dividing the clock frequency */
-) {
-        uint32_t scale = 0;
-        ResetTimer(timerId);
-        /* Set timer as free running mode */
-        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_PERIODIC;
-        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-        if (divider >= 64) {
-                pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-                scale = 256;
-        } else if (divider >= 8) {
-                pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-                scale = 16;
-        } else {
-                pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-                scale = 1;
-        }
-        if (timerId == 0 || timerId == 1) {
-                return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, scale);
-        } else if (timerId == 2 || timerId == 3) {
-                return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, scale);
-        }
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Starts a timer
-*
-*  This function starts a preconfigured timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*/
-/****************************************************************************/
-int tmrHw_startTimer(tmrHw_ID_t timerId /*  [ IN ] Timer id */
-) {
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_TIMER_ENABLE;
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Stops a timer
-*
-*  This function stops a running timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*/
-/****************************************************************************/
-int tmrHw_stopTimer(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
-) {
-        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_TIMER_ENABLE;
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Gets current timer count
-*
-*  This function returns the current timer value
-*
-*  @return  Current downcounting timer value
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId       /*  [ IN ] Timer id */
-) {
-        /* return 32 bit timer value */
-        switch (pTmrHw[timerId].Control & tmrHw_CONTROL_MODE_MASK) {
-        case tmrHw_CONTROL_FREE_RUNNING:
-                if (pTmrHw[timerId].CurrentValue) {
-                        return tmrHw_MAX_COUNT - pTmrHw[timerId].CurrentValue;
-                }
-                break;
-        case tmrHw_CONTROL_PERIODIC:
-        case tmrHw_CONTROL_ONESHOT:
-                return pTmrHw[timerId].BackgroundLoad -
-                    pTmrHw[timerId].CurrentValue;
-        }
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Gets timer count rate
-*
-*  This function returns the number of counts per second
-*
-*  @return  Count rate
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId      /*  [ IN ] Timer id */
-) {
-        uint32_t divider = 0;
-        switch (pTmrHw[timerId].Control & tmrHw_CONTROL_PRESCALE_MASK) {
-        case tmrHw_CONTROL_PRESCALE_1:
-                divider = 1;
-                break;
-        case tmrHw_CONTROL_PRESCALE_16:
-                divider = 16;
-                break;
-        case tmrHw_CONTROL_PRESCALE_256:
-                divider = 256;
-                break;
-        default:
-                tmrHw_ASSERT(0);
-        }
-        if (timerId == 0 || timerId == 1) {
-                return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, divider);
-        } else {
-                return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, divider);
-        }
-        return 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Enables timer interrupt
-*
-*  This function enables the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_enableInterrupt(tmrHw_ID_t timerId   /*  [ IN ] Timer id */
-) {
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_INTERRUPT_ENABLE;
-}
-/****************************************************************************/
-/**
-*  @brief   Disables timer interrupt
-*
-*  This function disable the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_disableInterrupt(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
-) {
-        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_INTERRUPT_ENABLE;
-}
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the timer interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void tmrHw_clearInterrupt(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
-) {
-        pTmrHw[timerId].InterruptClear = 0x1;
-}
-/****************************************************************************/
-/**
-*  @brief   Gets the interrupt status
-*
-*  This function returns timer interrupt status
-*
-*  @return   Interrupt status
-*/
-/****************************************************************************/
-tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
-) {
-        if (pTmrHw[timerId].InterruptStatus) {
-                return tmrHw_INTERRUPT_STATUS_SET;
-        } else {
-                return tmrHw_INTERRUPT_STATUS_UNSET;
-        }
-}
-/****************************************************************************/
-/**
-*  @brief   Indentifies a timer causing interrupt
-*
-*  This functions returns a timer causing interrupt
-*
-*  @return  0xFFFFFFFF   : No timer causing an interrupt
-*           ! 0xFFFFFFFF : timer causing an interrupt
-*  @note
-*     tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
-*/
-/****************************************************************************/
-tmrHw_ID_t tmrHw_getInterruptSource(void        /*  void */
-) {
-        int i;
-        for (i = 0; i < tmrHw_TIMER_NUM_COUNT; i++) {
-                if (pTmrHw[i].InterruptStatus) {
-                        return i;
-                }
-        }
-        return 0xFFFFFFFF;
-}
-/****************************************************************************/
-/**
-*  @brief   Displays specific timer registers
-*
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void tmrHw_printDebugInfo(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
-                          int (*fpPrint) (const char *, ...)    /*  [ IN ] Print callback function */
-) {
-        (*fpPrint) ("Displaying register contents \n\n");
-        (*fpPrint) ("Timer %d: Load value              0x%X\n", timerId,
-                    pTmrHw[timerId].LoadValue);
-        (*fpPrint) ("Timer %d: Background load value   0x%X\n", timerId,
-                    pTmrHw[timerId].BackgroundLoad);
-        (*fpPrint) ("Timer %d: Control                 0x%X\n", timerId,
-                    pTmrHw[timerId].Control);
-        (*fpPrint) ("Timer %d: Interrupt clear         0x%X\n", timerId,
-                    pTmrHw[timerId].InterruptClear);
-        (*fpPrint) ("Timer %d: Interrupt raw interrupt 0x%X\n", timerId,
-                    pTmrHw[timerId].RawInterruptStatus);
-        (*fpPrint) ("Timer %d: Interrupt status        0x%X\n", timerId,
-                    pTmrHw[timerId].InterruptStatus);
-}
-/****************************************************************************/
-/**
-*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_udelay(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
-                  unsigned long usecs /*  [ IN ] usec to delay */
-) {
-        tmrHw_RATE_t usec_tick_rate;
-        tmrHw_COUNT_t start_time;
-        tmrHw_COUNT_t delta_time;
-        start_time = tmrHw_GetCurrentCount(timerId);
-        usec_tick_rate = tmrHw_divide(tmrHw_getCountRate(timerId), 1000000);
-        delta_time = usecs * usec_tick_rate;
-        /* Busy wait */
-        while (delta_time > (tmrHw_GetCurrentCount(timerId) - start_time))
-                ;
-}
-/****************************************************************************/
-/**
-*  @brief   Local Divide function
-*
-*  This function does the divide
-*
-*  @return divide value
-*
-*/
-/****************************************************************************/
-static int tmrHw_divide(int num, int denom)
-{
-        int r;
-        int t = 1;
-        /* Shift denom and t up to the largest value to optimize algorithm */
-        /* t contains the units of each divide */
-        while ((denom & 0x40000000) == 0) {     /* fails if denom=0 */
-                denom = denom << 1;
-                t = t << 1;
-        }
-        /* Initialize the result */
-        r = 0;
-        do {
-                /* Determine if there exists a positive remainder */
-                if ((num - denom) >= 0) {
-                        /* Accumlate t to the result and calculate a new remainder */
-                        num = num - denom;
-                        r = r + t;
-                }
-                /* Continue to shift denom and shift t down to 0 */
-                denom = denom >> 1;
-                t = t >> 1;
-        } while (t != 0);
-        return r;
-}
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
deleted file mode 100644
index e5fd241fccdc..000000000000
--- a/arch/arm/mach-bcmring/dma.c
+++ /dev/null
@@ -1,1518 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*   @file   dma.c
-*
-*   @brief  Implements the DMA interface.
-*/
-/****************************************************************************/
-/* ---- Include Files ---------------------------------------------------- */
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/irqreturn.h>
-#include <linux/proc_fs.h>
-#include <linux/slab.h>
-#include <mach/timer.h>
-#include <linux/pfn.h>
-#include <linux/atomic.h>
-#include <mach/dma.h>
-/* ---- Public Variables ------------------------------------------------- */
-/* ---- Private Constants and Types -------------------------------------- */
-#define MAKE_HANDLE(controllerIdx, channelIdx)    (((controllerIdx) << 4) | (channelIdx))
-#define CONTROLLER_FROM_HANDLE(handle)    (((handle) >> 4) & 0x0f)
-#define CHANNEL_FROM_HANDLE(handle)       ((handle) & 0x0f)
-/* ---- Private Variables ------------------------------------------------ */
-static DMA_Global_t gDMA;
-static struct proc_dir_entry *gDmaDir;
-#include "dma_device.c"
-/* ---- Private Function Prototypes -------------------------------------- */
-/* ---- Functions  ------------------------------------------------------- */
-/****************************************************************************/
-/**
-*   Displays information for /proc/dma/channels
-*/
-/****************************************************************************/
-static int dma_proc_read_channels(char *buf, char **start, off_t offset,
-                                  int count, int *eof, void *data)
-{
-        int controllerIdx;
-        int channelIdx;
-        int limit = count - 200;
-        int len = 0;
-        DMA_Channel_t *channel;
-        if (down_interruptible(&gDMA.lock) < 0) {
-                return -ERESTARTSYS;
-        }
-        for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-             controllerIdx++) {
-                for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-                     channelIdx++) {
-                        if (len >= limit) {
-                                break;
-                        }
-                        channel =
-                            &gDMA.controller[controllerIdx].channel[channelIdx];
-                        len +=
-                            sprintf(buf + len, "%d:%d ", controllerIdx,
-                                    channelIdx);
-                        if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
-                            0) {
-                                len +=
-                                    sprintf(buf + len, "Dedicated for %s ",
-                                            DMA_gDeviceAttribute[channel->
-                                                                 devType].name);
-                        } else {
-                                len += sprintf(buf + len, "Shared ");
-                        }
-                        if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) != 0) {
-                                len += sprintf(buf + len, "No ISR ");
-                        }
-                        if ((channel->flags & DMA_CHANNEL_FLAG_LARGE_FIFO) != 0) {
-                                len += sprintf(buf + len, "Fifo: 128 ");
-                        } else {
-                                len += sprintf(buf + len, "Fifo: 64  ");
-                        }
-                        if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
-                                len +=
-                                    sprintf(buf + len, "InUse by %s",
-                                            DMA_gDeviceAttribute[channel->
-                                                                 devType].name);
-#if (DMA_DEBUG_TRACK_RESERVATION)
-                                len +=
-                                    sprintf(buf + len, " (%s:%d)",
-                                            channel->fileName,
-                                            channel->lineNum);
-#endif
-                        } else {
-                                len += sprintf(buf + len, "Avail ");
-                        }
-                        if (channel->lastDevType != DMA_DEVICE_NONE) {
-                                len +=
-                                    sprintf(buf + len, "Last use: %s ",
-                                            DMA_gDeviceAttribute[channel->
-                                                                 lastDevType].
-                                            name);
-                        }
-                        len += sprintf(buf + len, "\n");
-                }
-        }
-        up(&gDMA.lock);
-        *eof = 1;
-        return len;
-}
-/****************************************************************************/
-/**
-*   Displays information for /proc/dma/devices
-*/
-/****************************************************************************/
-static int dma_proc_read_devices(char *buf, char **start, off_t offset,
-                                 int count, int *eof, void *data)
-{
-        int limit = count - 200;
-        int len = 0;
-        int devIdx;
-        if (down_interruptible(&gDMA.lock) < 0) {
-                return -ERESTARTSYS;
-        }
-        for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
-                DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
-                if (devAttr->name == NULL) {
-                        continue;
-                }
-                if (len >= limit) {
-                        break;
-                }
-                len += sprintf(buf + len, "%-12s ", devAttr->name);
-                if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-                        len +=
-                            sprintf(buf + len, "Dedicated %d:%d ",
-                                    devAttr->dedicatedController,
-                                    devAttr->dedicatedChannel);
-                } else {
-                        len += sprintf(buf + len, "Shared DMA:");
-                        if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA0) != 0) {
-                                len += sprintf(buf + len, "0");
-                        }
-                        if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA1) != 0) {
-                                len += sprintf(buf + len, "1");
-                        }
-                        len += sprintf(buf + len, " ");
-                }
-                if ((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0) {
-                        len += sprintf(buf + len, "NoISR ");
-                }
-                if ((devAttr->flags & DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO) != 0) {
-                        len += sprintf(buf + len, "Allow-128 ");
-                }
-                len +=
-                    sprintf(buf + len,
-                            "Xfer #: %Lu Ticks: %Lu Bytes: %Lu DescLen: %u\n",
-                            devAttr->numTransfers, devAttr->transferTicks,
-                            devAttr->transferBytes,
-                            devAttr->ring.bytesAllocated);
-        }
-        up(&gDMA.lock);
-        *eof = 1;
-        return len;
-}
-/****************************************************************************/
-/**
-*   Determines if a DMA_Device_t is "valid".
-*
-*   @return
-*       TRUE        - dma device is valid
-*       FALSE       - dma device isn't valid
-*/
-/****************************************************************************/
-static inline int IsDeviceValid(DMA_Device_t device)
-{
-        return (device >= 0) && (device < DMA_NUM_DEVICE_ENTRIES);
-}
-/****************************************************************************/
-/**
-*   Translates a DMA handle into a pointer to a channel.
-*
-*   @return
-*       non-NULL    - pointer to DMA_Channel_t
-*       NULL        - DMA Handle was invalid
-*/
-/****************************************************************************/
-static inline DMA_Channel_t *HandleToChannel(DMA_Handle_t handle)
-{
-        int controllerIdx;
-        int channelIdx;
-        controllerIdx = CONTROLLER_FROM_HANDLE(handle);
-        channelIdx = CHANNEL_FROM_HANDLE(handle);
-        if ((controllerIdx > DMA_NUM_CONTROLLERS)
-            || (channelIdx > DMA_NUM_CHANNELS)) {
-                return NULL;
-        }
-        return &gDMA.controller[controllerIdx].channel[channelIdx];
-}
-/****************************************************************************/
-/**
-*   Interrupt handler which is called to process DMA interrupts.
-*/
-/****************************************************************************/
-static irqreturn_t dma_interrupt_handler(int irq, void *dev_id)
-{
-        DMA_Channel_t *channel;
-        DMA_DeviceAttribute_t *devAttr;
-        int irqStatus;
-        channel = (DMA_Channel_t *) dev_id;
-        /* Figure out why we were called, and knock down the interrupt */
-        irqStatus = dmacHw_getInterruptStatus(channel->dmacHwHandle);
-        dmacHw_clearInterrupt(channel->dmacHwHandle);
-        if ((channel->devType < 0)
-            || (channel->devType > DMA_NUM_DEVICE_ENTRIES)) {
-                printk(KERN_ERR "dma_interrupt_handler: Invalid devType: %d\n",
-                       channel->devType);
-                return IRQ_NONE;
-        }
-        devAttr = &DMA_gDeviceAttribute[channel->devType];
-        /* Update stats */
-        if ((irqStatus & dmacHw_INTERRUPT_STATUS_TRANS) != 0) {
-                devAttr->transferTicks +=
-                    (timer_get_tick_count() - devAttr->transferStartTime);
-        }
-        if ((irqStatus & dmacHw_INTERRUPT_STATUS_ERROR) != 0) {
-                printk(KERN_ERR
-                       "dma_interrupt_handler: devType :%d DMA error (%s)\n",
-                       channel->devType, devAttr->name);
-        } else {
-                devAttr->numTransfers++;
-                devAttr->transferBytes += devAttr->numBytes;
-        }
-        /* Call any installed handler */
-        if (devAttr->devHandler != NULL) {
-                devAttr->devHandler(channel->devType, irqStatus,
-                                    devAttr->userData);
-        }
-        return IRQ_HANDLED;
-}
-/****************************************************************************/
-/**
-*   Allocates memory to hold a descriptor ring. The descriptor ring then
-*   needs to be populated by making one or more calls to
-*   dna_add_descriptors.
-*
-*   The returned descriptor ring will be automatically initialized.
-*
-*   @return
-*       0           Descriptor ring was allocated successfully
-*       -EINVAL     Invalid parameters passed in
-*       -ENOMEM     Unable to allocate memory for the desired number of descriptors.
-*/
-/****************************************************************************/
-int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,       /* Descriptor ring to populate */
-                              int numDescriptors        /* Number of descriptors that need to be allocated. */
-    ) {
-        size_t bytesToAlloc = dmacHw_descriptorLen(numDescriptors);
-        if ((ring == NULL) || (numDescriptors <= 0)) {
-                return -EINVAL;
-        }
-        ring->physAddr = 0;
-        ring->descriptorsAllocated = 0;
-        ring->bytesAllocated = 0;
-        ring->virtAddr = dma_alloc_writecombine(NULL,
-                                                     bytesToAlloc,
-                                                     &ring->physAddr,
-                                                     GFP_KERNEL);
-        if (ring->virtAddr == NULL) {
-                return -ENOMEM;
-        }
-        ring->bytesAllocated = bytesToAlloc;
-        ring->descriptorsAllocated = numDescriptors;
-        return dma_init_descriptor_ring(ring, numDescriptors);
-}
-EXPORT_SYMBOL(dma_alloc_descriptor_ring);
-/****************************************************************************/
-/**
-*   Releases the memory which was previously allocated for a descriptor ring.
-*/
-/****************************************************************************/
-void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring        /* Descriptor to release */
-    ) {
-        if (ring->virtAddr != NULL) {
-                dma_free_writecombine(NULL,
-                                      ring->bytesAllocated,
-                                      ring->virtAddr, ring->physAddr);
-        }
-        ring->bytesAllocated = 0;
-        ring->descriptorsAllocated = 0;
-        ring->virtAddr = NULL;
-        ring->physAddr = 0;
-}
-EXPORT_SYMBOL(dma_free_descriptor_ring);
-/****************************************************************************/
-/**
-*   Initializes a descriptor ring, so that descriptors can be added to it.
-*   Once a descriptor ring has been allocated, it may be reinitialized for
-*   use with additional/different regions of memory.
-*
-*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
-*   initialize the ring with a smaller number of descriptors. The amount
-*   of memory allocated for the descriptor ring will not be reduced, and
-*   the descriptor ring may be reinitialized later
-*
-*   @return
-*       0           Descriptor ring was initialized successfully
-*       -ENOMEM     The descriptor which was passed in has insufficient space
-*                   to hold the desired number of descriptors.
-*/
-/****************************************************************************/
-int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,        /* Descriptor ring to initialize */
-                             int numDescriptors /* Number of descriptors to initialize. */
-    ) {
-        if (ring->virtAddr == NULL) {
-                return -EINVAL;
-        }
-        if (dmacHw_initDescriptor(ring->virtAddr,
-                                  ring->physAddr,
-                                  ring->bytesAllocated, numDescriptors) < 0) {
-                printk(KERN_ERR
-                       "dma_init_descriptor_ring: dmacHw_initDescriptor failed\n");
-                return -ENOMEM;
-        }
-        return 0;
-}
-EXPORT_SYMBOL(dma_init_descriptor_ring);
-/****************************************************************************/
-/**
-*   Determines the number of descriptors which would be required for a
-*   transfer of the indicated memory region.
-*
-*   This function also needs to know which DMA device this transfer will
-*   be destined for, so that the appropriate DMA configuration can be retrieved.
-*   DMA parameters such as transfer width, and whether this is a memory-to-memory
-*   or memory-to-peripheral, etc can all affect the actual number of descriptors
-*   required.
-*
-*   @return
-*       > 0     Returns the number of descriptors required for the indicated transfer
-*       -ENODEV - Device handed in is invalid.
-*       -EINVAL Invalid parameters
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */
-                                   dma_addr_t srcData,  /* Place to get data to write to device */
-                                   dma_addr_t dstData,  /* Pointer to device data address */
-                                   size_t numBytes      /* Number of bytes to transfer to the device */
-    ) {
-        int numDescriptors;
-        DMA_DeviceAttribute_t *devAttr;
-        if (!IsDeviceValid(device)) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[device];
-        numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
-                                                              (void *)srcData,
-                                                              (void *)dstData,
-                                                              numBytes);
-        if (numDescriptors < 0) {
-                printk(KERN_ERR
-                       "dma_calculate_descriptor_count: dmacHw_calculateDescriptorCount failed\n");
-                return -EINVAL;
-        }
-        return numDescriptors;
-}
-EXPORT_SYMBOL(dma_calculate_descriptor_count);
-/****************************************************************************/
-/**
-*   Adds a region of memory to the descriptor ring. Note that it may take
-*   multiple descriptors for each region of memory. It is the callers
-*   responsibility to allocate a sufficiently large descriptor ring.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*       -EINVAL Invalid parameters
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-int dma_add_descriptors(DMA_DescriptorRing_t *ring,     /* Descriptor ring to add descriptors to */
-                        DMA_Device_t device,    /* DMA Device that descriptors are for */
-                        dma_addr_t srcData,     /* Place to get data (memory or device) */
-                        dma_addr_t dstData,     /* Place to put data (memory or device) */
-                        size_t numBytes /* Number of bytes to transfer to the device */
-    ) {
-        int rc;
-        DMA_DeviceAttribute_t *devAttr;
-        if (!IsDeviceValid(device)) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[device];
-        rc = dmacHw_setDataDescriptor(&devAttr->config,
-                                      ring->virtAddr,
-                                      (void *)srcData,
-                                      (void *)dstData, numBytes);
-        if (rc < 0) {
-                printk(KERN_ERR
-                       "dma_add_descriptors: dmacHw_setDataDescriptor failed with code: %d\n",
-                       rc);
-                return -ENOMEM;
-        }
-        return 0;
-}
-EXPORT_SYMBOL(dma_add_descriptors);
-/****************************************************************************/
-/**
-*   Sets the descriptor ring associated with a device.
-*
-*   Once set, the descriptor ring will be associated with the device, even
-*   across channel request/free calls. Passing in a NULL descriptor ring
-*   will release any descriptor ring currently associated with the device.
-*
-*   Note: If you call dma_transfer, or one of the other dma_alloc_ functions
-*         the descriptor ring may be released and reallocated.
-*
-*   Note: This function will release the descriptor memory for any current
-*         descriptor ring associated with this device.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*/
-/****************************************************************************/
-int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */
-                                   DMA_DescriptorRing_t *ring   /* Descriptor ring to add descriptors to */
-    ) {
-        DMA_DeviceAttribute_t *devAttr;
-        if (!IsDeviceValid(device)) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[device];
-        /* Free the previously allocated descriptor ring */
-        dma_free_descriptor_ring(&devAttr->ring);
-        if (ring != NULL) {
-                /* Copy in the new one */
-                devAttr->ring = *ring;
-        }
-        /* Set things up so that if dma_transfer is called then this descriptor */
-        /* ring will get freed. */
-        devAttr->prevSrcData = 0;
-        devAttr->prevDstData = 0;
-        devAttr->prevNumBytes = 0;
-        return 0;
-}
-EXPORT_SYMBOL(dma_set_device_descriptor_ring);
-/****************************************************************************/
-/**
-*   Retrieves the descriptor ring associated with a device.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*/
-/****************************************************************************/
-int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */
-                                   DMA_DescriptorRing_t *ring   /* Place to store retrieved ring */
-    ) {
-        DMA_DeviceAttribute_t *devAttr;
-        memset(ring, 0, sizeof(*ring));
-        if (!IsDeviceValid(device)) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[device];
-        *ring = devAttr->ring;
-        return 0;
-}
-EXPORT_SYMBOL(dma_get_device_descriptor_ring);
-/****************************************************************************/
-/**
-*   Configures a DMA channel.
-*
-*   @return
-*       >= 0    - Initialization was successful.
-*
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-static int ConfigChannel(DMA_Handle_t handle)
-{
-        DMA_Channel_t *channel;
-        DMA_DeviceAttribute_t *devAttr;
-        int controllerIdx;
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[channel->devType];
-        controllerIdx = CONTROLLER_FROM_HANDLE(handle);
-        if ((devAttr->flags & DMA_DEVICE_FLAG_PORT_PER_DMAC) != 0) {
-                if (devAttr->config.transferType ==
-                    dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL) {
-                        devAttr->config.dstPeripheralPort =
-                            devAttr->dmacPort[controllerIdx];
-                } else if (devAttr->config.transferType ==
-                           dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) {
-                        devAttr->config.srcPeripheralPort =
-                            devAttr->dmacPort[controllerIdx];
-                }
-        }
-        if (dmacHw_configChannel(channel->dmacHwHandle, &devAttr->config) != 0) {
-                printk(KERN_ERR "ConfigChannel: dmacHw_configChannel failed\n");
-                return -EIO;
-        }
-        return 0;
-}
-/****************************************************************************/
-/**
-*   Initializes all of the data structures associated with the DMA.
-*   @return
-*       >= 0    - Initialization was successful.
-*
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-int dma_init(void)
-{
-        int rc = 0;
-        int controllerIdx;
-        int channelIdx;
-        DMA_Device_t devIdx;
-        DMA_Channel_t *channel;
-        DMA_Handle_t dedicatedHandle;
-        memset(&gDMA, 0, sizeof(gDMA));
-        sema_init(&gDMA.lock, 0);
-        init_waitqueue_head(&gDMA.freeChannelQ);
-        /* Initialize the Hardware */
-        dmacHw_initDma();
-        /* Start off by marking all of the DMA channels as shared. */
-        for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-             controllerIdx++) {
-                for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-                     channelIdx++) {
-                        channel =
-                            &gDMA.controller[controllerIdx].channel[channelIdx];
-                        channel->flags = 0;
-                        channel->devType = DMA_DEVICE_NONE;
-                        channel->lastDevType = DMA_DEVICE_NONE;
-#if (DMA_DEBUG_TRACK_RESERVATION)
-                        channel->fileName = "";
-                        channel->lineNum = 0;
-#endif
-                        channel->dmacHwHandle =
-                            dmacHw_getChannelHandle(dmacHw_MAKE_CHANNEL_ID
-                                                    (controllerIdx,
-                                                     channelIdx));
-                        dmacHw_initChannel(channel->dmacHwHandle);
-                }
-        }
-        /* Record any special attributes that channels may have */
-        gDMA.controller[0].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-        gDMA.controller[0].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-        gDMA.controller[1].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-        gDMA.controller[1].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-        /* Now walk through and record the dedicated channels. */
-        for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
-                DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
-                if (((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0)
-                    && ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0)) {
-                        printk(KERN_ERR
-                               "DMA Device: %s Can only request NO_ISR for dedicated devices\n",
-                               devAttr->name);
-                        rc = -EINVAL;
-                        goto out;
-                }
-                if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-                        /* This is a dedicated device. Mark the channel as being reserved. */
-                        if (devAttr->dedicatedController >= DMA_NUM_CONTROLLERS) {
-                                printk(KERN_ERR
-                                       "DMA Device: %s DMA Controller %d is out of range\n",
-                                       devAttr->name,
-                                       devAttr->dedicatedController);
-                                rc = -EINVAL;
-                                goto out;
-                        }
-                        if (devAttr->dedicatedChannel >= DMA_NUM_CHANNELS) {
-                                printk(KERN_ERR
-                                       "DMA Device: %s DMA Channel %d is out of range\n",
-                                       devAttr->name,
-                                       devAttr->dedicatedChannel);
-                                rc = -EINVAL;
-                                goto out;
-                        }
-                        dedicatedHandle =
-                            MAKE_HANDLE(devAttr->dedicatedController,
-                                        devAttr->dedicatedChannel);
-                        channel = HandleToChannel(dedicatedHandle);
-                        if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
-                            0) {
-                                printk
-                                    ("DMA Device: %s attempting to use same DMA Controller:Channel (%d:%d) as %s\n",
-                                     devAttr->name,
-                                     devAttr->dedicatedController,
-                                     devAttr->dedicatedChannel,
-                                     DMA_gDeviceAttribute[channel->devType].
-                                     name);
-                                rc = -EBUSY;
-                                goto out;
-                        }
-                        channel->flags |= DMA_CHANNEL_FLAG_IS_DEDICATED;
-                        channel->devType = devIdx;
-                        if (devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) {
-                                channel->flags |= DMA_CHANNEL_FLAG_NO_ISR;
-                        }
-                        /* For dedicated channels, we can go ahead and configure the DMA channel now */
-                        /* as well. */
-                        ConfigChannel(dedicatedHandle);
-                }
-        }
-        /* Go through and register the interrupt handlers */
-        for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-             controllerIdx++) {
-                for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-                     channelIdx++) {
-                        channel =
-                            &gDMA.controller[controllerIdx].channel[channelIdx];
-                        if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) == 0) {
-                                snprintf(channel->name, sizeof(channel->name),
-                                         "dma %d:%d %s", controllerIdx,
-                                         channelIdx,
-                                         channel->devType ==
-                                         DMA_DEVICE_NONE ? "" :
-                                         DMA_gDeviceAttribute[channel->devType].
-                                         name);
-                                rc =
-                                     request_irq(IRQ_DMA0C0 +
-                                                 (controllerIdx *
-                                                  DMA_NUM_CHANNELS) +
-                                                 channelIdx,
-                                                 dma_interrupt_handler,
-                                                 IRQF_DISABLED, channel->name,
-                                                 channel);
-                                if (rc != 0) {
-                                        printk(KERN_ERR
-                                               "request_irq for IRQ_DMA%dC%d failed\n",
-                                               controllerIdx, channelIdx);
-                                }
-                        }
-                }
-        }
-        /* Create /proc/dma/channels and /proc/dma/devices */
-        gDmaDir = proc_mkdir("dma", NULL);
-        if (gDmaDir == NULL) {
-                printk(KERN_ERR "Unable to create /proc/dma\n");
-        } else {
-                create_proc_read_entry("channels", 0, gDmaDir,
-                                       dma_proc_read_channels, NULL);
-                create_proc_read_entry("devices", 0, gDmaDir,
-                                       dma_proc_read_devices, NULL);
-        }
-out:
-        up(&gDMA.lock);
-        return rc;
-}
-/****************************************************************************/
-/**
-*   Reserves a channel for use with @a dev. If the device is setup to use
-*   a shared channel, then this function will block until a free channel
-*   becomes available.
-*
-*   @return
-*       >= 0    - A valid DMA Handle.
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-#if (DMA_DEBUG_TRACK_RESERVATION)
-DMA_Handle_t dma_request_channel_dbg
-    (DMA_Device_t dev, const char *fileName, int lineNum)
-#else
-DMA_Handle_t dma_request_channel(DMA_Device_t dev)
-#endif
-{
-        DMA_Handle_t handle;
-        DMA_DeviceAttribute_t *devAttr;
-        DMA_Channel_t *channel;
-        int controllerIdx;
-        int controllerIdx2;
-        int channelIdx;
-        if (down_interruptible(&gDMA.lock) < 0) {
-                return -ERESTARTSYS;
-        }
-        if ((dev < 0) || (dev >= DMA_NUM_DEVICE_ENTRIES)) {
-                handle = -ENODEV;
-                goto out;
-        }
-        devAttr = &DMA_gDeviceAttribute[dev];
-#if (DMA_DEBUG_TRACK_RESERVATION)
-        {
-                char *s;
-                s = strrchr(fileName, '/');
-                if (s != NULL) {
-                        fileName = s + 1;
-                }
-        }
-#endif
-        if ((devAttr->flags & DMA_DEVICE_FLAG_IN_USE) != 0) {
-                /* This device has already been requested and not been freed */
-                printk(KERN_ERR "%s: device %s is already requested\n",
-                       __func__, devAttr->name);
-                handle = -EBUSY;
-                goto out;
-        }
-        if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-                /* This device has a dedicated channel. */
-                channel =
-                    &gDMA.controller[devAttr->dedicatedController].
-                    channel[devAttr->dedicatedChannel];
-                if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
-                        handle = -EBUSY;
-                        goto out;
-                }
-                channel->flags |= DMA_CHANNEL_FLAG_IN_USE;
-                devAttr->flags |= DMA_DEVICE_FLAG_IN_USE;
-#if (DMA_DEBUG_TRACK_RESERVATION)
-                channel->fileName = fileName;
-                channel->lineNum = lineNum;
-#endif
-                handle =
-                    MAKE_HANDLE(devAttr->dedicatedController,
-                                devAttr->dedicatedChannel);
-                goto out;
-        }
-        /* This device needs to use one of the shared channels. */
-        handle = DMA_INVALID_HANDLE;
-        while (handle == DMA_INVALID_HANDLE) {
-                /* Scan through the shared channels and see if one is available */
-                for (controllerIdx2 = 0; controllerIdx2 < DMA_NUM_CONTROLLERS;
-                     controllerIdx2++) {
-                        /* Check to see if we should try on controller 1 first. */
-                        controllerIdx = controllerIdx2;
-                        if ((devAttr->
-                             flags & DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST) != 0) {
-                                controllerIdx = 1 - controllerIdx;
-                        }
-                        /* See if the device is available on the controller being tested */
-                        if ((devAttr->
-                             flags & (DMA_DEVICE_FLAG_ON_DMA0 << controllerIdx))
-                            != 0) {
-                                for (channelIdx = 0;
-                                     channelIdx < DMA_NUM_CHANNELS;
-                                     channelIdx++) {
-                                        channel =
-                                            &gDMA.controller[controllerIdx].
-                                            channel[channelIdx];
-                                        if (((channel->
-                                              flags &
-                                              DMA_CHANNEL_FLAG_IS_DEDICATED) ==
-                                             0)
-                                            &&
-                                            ((channel->
-                                              flags & DMA_CHANNEL_FLAG_IN_USE)
-                                             == 0)) {
-                                                if (((channel->
-                                                      flags &
-                                                      DMA_CHANNEL_FLAG_LARGE_FIFO)
-                                                     != 0)
-                                                    &&
-                                                    ((devAttr->
-                                                      flags &
-                                                      DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO)
-                                                     == 0)) {
-                                                        /* This channel is a large fifo - don't tie it up */
-                                                        /* with devices that we don't want using it. */
-                                                        continue;
-                                                }
-                                                channel->flags |=
-                                                    DMA_CHANNEL_FLAG_IN_USE;
-                                                channel->devType = dev;
-                                                devAttr->flags |=
-                                                    DMA_DEVICE_FLAG_IN_USE;
-#if (DMA_DEBUG_TRACK_RESERVATION)
-                                                channel->fileName = fileName;
-                                                channel->lineNum = lineNum;
-#endif
-                                                handle =
-                                                    MAKE_HANDLE(controllerIdx,
-                                                                channelIdx);
-                                                /* Now that we've reserved the channel - we can go ahead and configure it */
-                                                if (ConfigChannel(handle) != 0) {
-                                                        handle = -EIO;
-                                                        printk(KERN_ERR
-                                                               "dma_request_channel: ConfigChannel failed\n");
-                                                }
-                                                goto out;
-                                        }
-                                }
-                        }
-                }
-                /* No channels are currently available. Let's wait for one to free up. */
-                {
-                        DEFINE_WAIT(wait);
-                        prepare_to_wait(&gDMA.freeChannelQ, &wait,
-                                        TASK_INTERRUPTIBLE);
-                        up(&gDMA.lock);
-                        schedule();
-                        finish_wait(&gDMA.freeChannelQ, &wait);
-                        if (signal_pending(current)) {
-                                /* We don't currently hold gDMA.lock, so we return directly */
-                                return -ERESTARTSYS;
-                        }
-                }
-                if (down_interruptible(&gDMA.lock)) {
-                        return -ERESTARTSYS;
-                }
-        }
-out:
-        up(&gDMA.lock);
-        return handle;
-}
-/* Create both _dbg and non _dbg functions for modules. */
-#if (DMA_DEBUG_TRACK_RESERVATION)
-#undef dma_request_channel
-DMA_Handle_t dma_request_channel(DMA_Device_t dev)
-{
-        return dma_request_channel_dbg(dev, __FILE__, __LINE__);
-}
-EXPORT_SYMBOL(dma_request_channel_dbg);
-#endif
-EXPORT_SYMBOL(dma_request_channel);
-/****************************************************************************/
-/**
-*   Frees a previously allocated DMA Handle.
-*/
-/****************************************************************************/
-int dma_free_channel(DMA_Handle_t handle        /* DMA handle. */
-    ) {
-        int rc = 0;
-        DMA_Channel_t *channel;
-        DMA_DeviceAttribute_t *devAttr;
-        if (down_interruptible(&gDMA.lock) < 0) {
-                return -ERESTARTSYS;
-        }
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                rc = -EINVAL;
-                goto out;
-        }
-        devAttr = &DMA_gDeviceAttribute[channel->devType];
-        if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) == 0) {
-                channel->lastDevType = channel->devType;
-                channel->devType = DMA_DEVICE_NONE;
-        }
-        channel->flags &= ~DMA_CHANNEL_FLAG_IN_USE;
-        devAttr->flags &= ~DMA_DEVICE_FLAG_IN_USE;
-out:
-        up(&gDMA.lock);
-        wake_up_interruptible(&gDMA.freeChannelQ);
-        return rc;
-}
-EXPORT_SYMBOL(dma_free_channel);
-/****************************************************************************/
-/**
-*   Determines if a given device has been configured as using a shared
-*   channel.
-*
-*   @return
-*       0           Device uses a dedicated channel
-*       > zero      Device uses a shared channel
-*       < zero      Error code
-*/
-/****************************************************************************/
-int dma_device_is_channel_shared(DMA_Device_t device    /* Device to check. */
-    ) {
-        DMA_DeviceAttribute_t *devAttr;
-        if (!IsDeviceValid(device)) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[device];
-        return ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0);
-}
-EXPORT_SYMBOL(dma_device_is_channel_shared);
-/****************************************************************************/
-/**
-*   Allocates buffers for the descriptors. This is normally done automatically
-*   but needs to be done explicitly when initiating a dma from interrupt
-*   context.
-*
-*   @return
-*       0       Descriptors were allocated successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-int dma_alloc_descriptors(DMA_Handle_t handle,  /* DMA Handle */
-                          dmacHw_TRANSFER_TYPE_e transferType,  /* Type of transfer being performed */
-                          dma_addr_t srcData,   /* Place to get data to write to device */
-                          dma_addr_t dstData,   /* Pointer to device data address */
-                          size_t numBytes       /* Number of bytes to transfer to the device */
-    ) {
-        DMA_Channel_t *channel;
-        DMA_DeviceAttribute_t *devAttr;
-        int numDescriptors;
-        size_t ringBytesRequired;
-        int rc = 0;
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[channel->devType];
-        if (devAttr->config.transferType != transferType) {
-                return -EINVAL;
-        }
-        /* Figure out how many descriptors we need. */
-        /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
-        /*        srcData, dstData, numBytes); */
-        numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
-                                                              (void *)srcData,
-                                                              (void *)dstData,
-                                                              numBytes);
-        if (numDescriptors < 0) {
-                printk(KERN_ERR "%s: dmacHw_calculateDescriptorCount failed\n",
-                       __func__);
-                return -EINVAL;
-        }
-        /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */
-        /* a new one. */
-        ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
-        /* printk("ringBytesRequired: %d\n", ringBytesRequired); */
-        if (ringBytesRequired > devAttr->ring.bytesAllocated) {
-                /* Make sure that this code path is never taken from interrupt context. */
-                /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */
-                /* allocation needs to have already been done. */
-                might_sleep();
-                /* Free the old descriptor ring and allocate a new one. */
-                dma_free_descriptor_ring(&devAttr->ring);
-                /* And allocate a new one. */
-                rc =
-                     dma_alloc_descriptor_ring(&devAttr->ring,
-                                               numDescriptors);
-                if (rc < 0) {
-                        printk(KERN_ERR
-                               "%s: dma_alloc_descriptor_ring(%d) failed\n",
-                               __func__, numDescriptors);
-                        return rc;
-                }
-                /* Setup the descriptor for this transfer */
-                if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
-                                          devAttr->ring.physAddr,
-                                          devAttr->ring.bytesAllocated,
-                                          numDescriptors) < 0) {
-                        printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n",
-                               __func__);
-                        return -EINVAL;
-                }
-        } else {
-                /* We've already got enough ring buffer allocated. All we need to do is reset */
-                /* any control information, just in case the previous DMA was stopped. */
-                dmacHw_resetDescriptorControl(devAttr->ring.virtAddr);
-        }
-        /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */
-        /* as last time, then we don't need to call setDataDescriptor again. */
-        if (dmacHw_setDataDescriptor(&devAttr->config,
-                                     devAttr->ring.virtAddr,
-                                     (void *)srcData,
-                                     (void *)dstData, numBytes) < 0) {
-                printk(KERN_ERR "%s: dmacHw_setDataDescriptor failed\n",
-                       __func__);
-                return -EINVAL;
-        }
-        /* Remember the critical information for this transfer so that we can eliminate */
-        /* another call to dma_alloc_descriptors if the caller reuses the same buffers */
-        devAttr->prevSrcData = srcData;
-        devAttr->prevDstData = dstData;
-        devAttr->prevNumBytes = numBytes;
-        return 0;
-}
-EXPORT_SYMBOL(dma_alloc_descriptors);
-/****************************************************************************/
-/**
-*   Allocates and sets up descriptors for a double buffered circular buffer.
-*
-*   This is primarily intended to be used for things like the ingress samples
-*   from a microphone.
-*
-*   @return
-*       > 0     Number of descriptors actually allocated.
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,       /* DMA Handle */
-                                     dma_addr_t srcData,        /* Physical address of source data */
-                                     dma_addr_t dstData1,       /* Physical address of first destination buffer */
-                                     dma_addr_t dstData2,       /* Physical address of second destination buffer */
-                                     size_t numBytes    /* Number of bytes in each destination buffer */
-    ) {
-        DMA_Channel_t *channel;
-        DMA_DeviceAttribute_t *devAttr;
-        int numDst1Descriptors;
-        int numDst2Descriptors;
-        int numDescriptors;
-        size_t ringBytesRequired;
-        int rc = 0;
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[channel->devType];
-        /* Figure out how many descriptors we need. */
-        /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
-        /*        srcData, dstData, numBytes); */
-        numDst1Descriptors =
-             dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
-                                             (void *)dstData1, numBytes);
-        if (numDst1Descriptors < 0) {
-                return -EINVAL;
-        }
-        numDst2Descriptors =
-             dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
-                                             (void *)dstData2, numBytes);
-        if (numDst2Descriptors < 0) {
-                return -EINVAL;
-        }
-        numDescriptors = numDst1Descriptors + numDst2Descriptors;
-        /* printk("numDescriptors: %d\n", numDescriptors); */
-        /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */
-        /* a new one. */
-        ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
-        /* printk("ringBytesRequired: %d\n", ringBytesRequired); */
-        if (ringBytesRequired > devAttr->ring.bytesAllocated) {
-                /* Make sure that this code path is never taken from interrupt context. */
-                /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */
-                /* allocation needs to have already been done. */
-                might_sleep();
-                /* Free the old descriptor ring and allocate a new one. */
-                dma_free_descriptor_ring(&devAttr->ring);
-                /* And allocate a new one. */
-                rc =
-                     dma_alloc_descriptor_ring(&devAttr->ring,
-                                               numDescriptors);
-                if (rc < 0) {
-                        printk(KERN_ERR
-                               "%s: dma_alloc_descriptor_ring(%d) failed\n",
-                               __func__, ringBytesRequired);
-                        return rc;
-                }
-        }
-        /* Setup the descriptor for this transfer. Since this function is used with */
-        /* CONTINUOUS DMA operations, we need to reinitialize every time, otherwise */
-        /* setDataDescriptor will keep trying to append onto the end. */
-        if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
-                                  devAttr->ring.physAddr,
-                                  devAttr->ring.bytesAllocated,
-                                  numDescriptors) < 0) {
-                printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n", __func__);
-                return -EINVAL;
-        }
-        /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */
-        /* as last time, then we don't need to call setDataDescriptor again. */
-        if (dmacHw_setDataDescriptor(&devAttr->config,
-                                     devAttr->ring.virtAddr,
-                                     (void *)srcData,
-                                     (void *)dstData1, numBytes) < 0) {
-                printk(KERN_ERR "%s: dmacHw_setDataDescriptor 1 failed\n",
-                       __func__);
-                return -EINVAL;
-        }
-        if (dmacHw_setDataDescriptor(&devAttr->config,
-                                     devAttr->ring.virtAddr,
-                                     (void *)srcData,
-                                     (void *)dstData2, numBytes) < 0) {
-                printk(KERN_ERR "%s: dmacHw_setDataDescriptor 2 failed\n",
-                       __func__);
-                return -EINVAL;
-        }
-        /* You should use dma_start_transfer rather than dma_transfer_xxx so we don't */
-        /* try to make the 'prev' variables right. */
-        devAttr->prevSrcData = 0;
-        devAttr->prevDstData = 0;
-        devAttr->prevNumBytes = 0;
-        return numDescriptors;
-}
-EXPORT_SYMBOL(dma_alloc_double_dst_descriptors);
-/****************************************************************************/
-/**
-*   Initiates a transfer when the descriptors have already been setup.
-*
-*   This is a special case, and normally, the dma_transfer_xxx functions should
-*   be used.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-int dma_start_transfer(DMA_Handle_t handle)
-{
-        DMA_Channel_t *channel;
-        DMA_DeviceAttribute_t *devAttr;
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[channel->devType];
-        dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
-                                devAttr->ring.virtAddr);
-        /* Since we got this far, everything went successfully */
-        return 0;
-}
-EXPORT_SYMBOL(dma_start_transfer);
-/****************************************************************************/
-/**
-*   Stops a previously started DMA transfer.
-*
-*   @return
-*       0       Transfer was stopped successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-int dma_stop_transfer(DMA_Handle_t handle)
-{
-        DMA_Channel_t *channel;
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                return -ENODEV;
-        }
-        dmacHw_stopTransfer(channel->dmacHwHandle);
-        return 0;
-}
-EXPORT_SYMBOL(dma_stop_transfer);
-/****************************************************************************/
-/**
-*   Waits for a DMA to complete by polling. This function is only intended
-*   to be used for testing. Interrupts should be used for most DMA operations.
-*/
-/****************************************************************************/
-int dma_wait_transfer_done(DMA_Handle_t handle)
-{
-        DMA_Channel_t *channel;
-        dmacHw_TRANSFER_STATUS_e status;
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                return -ENODEV;
-        }
-        while ((status =
-                dmacHw_transferCompleted(channel->dmacHwHandle)) ==
-               dmacHw_TRANSFER_STATUS_BUSY) {
-                ;
-        }
-        if (status == dmacHw_TRANSFER_STATUS_ERROR) {
-                printk(KERN_ERR "%s: DMA transfer failed\n", __func__);
-                return -EIO;
-        }
-        return 0;
-}
-EXPORT_SYMBOL(dma_wait_transfer_done);
-/****************************************************************************/
-/**
-*   Initiates a DMA, allocating the descriptors as required.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
-*/
-/****************************************************************************/
-int dma_transfer(DMA_Handle_t handle,   /* DMA Handle */
-                 dmacHw_TRANSFER_TYPE_e transferType,   /* Type of transfer being performed */
-                 dma_addr_t srcData,    /* Place to get data to write to device */
-                 dma_addr_t dstData,    /* Pointer to device data address */
-                 size_t numBytes        /* Number of bytes to transfer to the device */
-    ) {
-        DMA_Channel_t *channel;
-        DMA_DeviceAttribute_t *devAttr;
-        int rc = 0;
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[channel->devType];
-        if (devAttr->config.transferType != transferType) {
-                return -EINVAL;
-        }
-        /* We keep track of the information about the previous request for this */
-        /* device, and if the attributes match, then we can use the descriptors we setup */
-        /* the last time, and not have to reinitialize everything. */
-        {
-                rc =
-                     dma_alloc_descriptors(handle, transferType, srcData,
-                                           dstData, numBytes);
-                if (rc != 0) {
-                        return rc;
-                }
-        }
-        /* And kick off the transfer */
-        devAttr->numBytes = numBytes;
-        devAttr->transferStartTime = timer_get_tick_count();
-        dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
-                                devAttr->ring.virtAddr);
-        /* Since we got this far, everything went successfully */
-        return 0;
-}
-EXPORT_SYMBOL(dma_transfer);
-/****************************************************************************/
-/**
-*   Set the callback function which will be called when a transfer completes.
-*   If a NULL callback function is set, then no callback will occur.
-*
-*   @note   @a devHandler will be called from IRQ context.
-*
-*   @return
-*       0       - Success
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-int dma_set_device_handler(DMA_Device_t dev,    /* Device to set the callback for. */
-                           DMA_DeviceHandler_t devHandler,      /* Function to call when the DMA completes */
-                           void *userData       /* Pointer which will be passed to devHandler. */
-    ) {
-        DMA_DeviceAttribute_t *devAttr;
-        unsigned long flags;
-        if (!IsDeviceValid(dev)) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[dev];
-        local_irq_save(flags);
-        devAttr->userData = userData;
-        devAttr->devHandler = devHandler;
-        local_irq_restore(flags);
-        return 0;
-}
-EXPORT_SYMBOL(dma_set_device_handler);
diff --git a/arch/arm/mach-bcmring/dma_device.c b/arch/arm/mach-bcmring/dma_device.c
deleted file mode 100644
index ca0ad736870b..000000000000
--- a/arch/arm/mach-bcmring/dma_device.c
+++ /dev/null
@@ -1,593 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*   @file   dma_device.c
-*
-*   @brief  private array of DMA_DeviceAttribute_t
-*/
-/****************************************************************************/
-DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = {
-        [DMA_DEVICE_MEM_TO_MEM] =       /* MEM 2 MEM */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "mem-to-mem",
-         .config = {
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    },
-         },
-        [DMA_DEVICE_VPM_MEM_TO_MEM] =   /* VPM */
-        {
-         .flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR,
-         .name = "vpm",
-         .dedicatedController = 0,
-         .dedicatedChannel = 0,
-         /* reserve DMA0:0 for VPM */
-         },
-        [DMA_DEVICE_NAND_MEM_TO_MEM] =  /* NAND */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "nand",
-         .config = {
-                    .srcPeripheralPort = 0,
-                    .dstPeripheralPort = 0,
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_6,
-                    },
-         },
-        [DMA_DEVICE_PIF_MEM_TO_DEV] =   /* PIF TX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
-         | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
-         | DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC,
-         .name = "pif_tx",
-         .dmacPort = {14, 5},
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    /* dstPeripheralPort          = 5 or 14 */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-                    .maxDataPerBlock = 16256,
-                    },
-         },
-        [DMA_DEVICE_PIF_DEV_TO_MEM] =   /* PIF RX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
-         | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
-         /* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */
-         | DMA_DEVICE_FLAG_PORT_PER_DMAC,
-         .name = "pif_rx",
-         .dmacPort = {14, 5},
-         .config = {
-                    /* srcPeripheralPort          = 5 or 14 */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-                    .maxDataPerBlock = 16256,
-                    },
-         },
-        [DMA_DEVICE_I2S0_DEV_TO_MEM] =  /* I2S RX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "i2s0_rx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: I2S0 */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-                    },
-         },
-        [DMA_DEVICE_I2S0_MEM_TO_DEV] =  /* I2S TX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "i2s0_tx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 1,     /* DST: I2S0 */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    },
-         },
-        [DMA_DEVICE_I2S1_DEV_TO_MEM] =  /* I2S1 RX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "i2s1_rx",
-         .config = {
-                    .srcPeripheralPort = 2,     /* SRC: I2S1 */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-                    },
-         },
-        [DMA_DEVICE_I2S1_MEM_TO_DEV] =  /* I2S1 TX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "i2s1_tx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 3,     /* DST: I2S1 */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    },
-         },
-        [DMA_DEVICE_ESW_MEM_TO_DEV] =   /* ESW TX */
-        {
-         .name = "esw_tx",
-         .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
-         .dedicatedController = 1,
-         .dedicatedChannel = 3,
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 1,     /* DST: ESW (MTP) */
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    /* DMAx_AHB_SSTATARy */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    /* DMAx_AHB_DSTATARy */
-                    .dstStatusRegisterAddress = 0x30490010,
-                    /* DMAx_AHB_CFGy */
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    /* DMAx_AHB_CTLy */
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    },
-         },
-        [DMA_DEVICE_ESW_DEV_TO_MEM] =   /* ESW RX */
-        {
-         .name = "esw_rx",
-         .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
-         .dedicatedController = 1,
-         .dedicatedChannel = 2,
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: ESW (PTM) */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    /* DMAx_AHB_SSTATARy */
-                    .srcStatusRegisterAddress = 0x30480010,
-                    /* DMAx_AHB_DSTATARy */
-                    .dstStatusRegisterAddress = 0x00000000,
-                    /* DMAx_AHB_CFGy */
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    /* DMAx_AHB_CTLy */
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    },
-         },
-        [DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] =   /* APM Codec A Ingress */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "apm_a_rx",
-         .config = {
-                    .srcPeripheralPort = 2,     /* SRC: Codec A Ingress FIFO */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-                    },
-         },
-        [DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] =   /* APM Codec A Egress */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "apm_a_tx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 3,     /* DST: Codec A Egress FIFO */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    },
-         },
-        [DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] =   /* APM Codec B Ingress */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "apm_b_rx",
-         .config = {
-                    .srcPeripheralPort = 4,     /* SRC: Codec B Ingress FIFO */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-                    },
-         },
-        [DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] =   /* APM Codec B Egress */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "apm_b_tx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 5,     /* DST: Codec B Egress FIFO */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    },
-         },
-        [DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] =   /* APM Codec C Ingress */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "apm_c_rx",
-         .config = {
-                    .srcPeripheralPort = 4,     /* SRC: Codec C Ingress FIFO */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-                    },
-         },
-        [DMA_DEVICE_APM_PCM0_DEV_TO_MEM] =      /* PCM0 RX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "pcm0_rx",
-         .config = {
-                    .srcPeripheralPort = 12,    /* SRC: PCM0 */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-                    },
-         },
-        [DMA_DEVICE_APM_PCM0_MEM_TO_DEV] =      /* PCM0 TX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "pcm0_tx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 13,    /* DST: PCM0 */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    },
-         },
-        [DMA_DEVICE_APM_PCM1_DEV_TO_MEM] =      /* PCM1 RX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "pcm1_rx",
-         .config = {
-                    .srcPeripheralPort = 14,    /* SRC: PCM1 */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-                    },
-         },
-        [DMA_DEVICE_APM_PCM1_MEM_TO_DEV] =      /* PCM1 TX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "pcm1_tx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 15,    /* DST: PCM1 */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    },
-         },
-        [DMA_DEVICE_SPUM_DEV_TO_MEM] =  /* SPUM RX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "spum_rx",
-         .config = {
-                    .srcPeripheralPort = 6,     /* SRC: Codec A Ingress FIFO */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    /* Busrt size **MUST** be 16 for SPUM to work */
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    /* on the RX side, SPU needs to be the flow controller */
-                    .flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL,
-                    },
-         },
-        [DMA_DEVICE_SPUM_MEM_TO_DEV] =  /* SPUM TX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "spum_tx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 7,     /* DST: SPUM */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    /* Busrt size **MUST** be 16 for SPUM to work */
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    },
-         },
-        [DMA_DEVICE_MEM_TO_VRAM] =      /* MEM 2 VRAM */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "mem-to-vram",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-                    },
-         },
-        [DMA_DEVICE_VRAM_TO_MEM] =      /* VRAM 2 MEM */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "vram-to-mem",
-         .config = {
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-                    },
-         },
-};
-EXPORT_SYMBOL(DMA_gDeviceAttribute);    /* primarily for dma-test.c */
diff --git a/arch/arm/mach-bcmring/include/cfg_global.h b/arch/arm/mach-bcmring/include/cfg_global.h
deleted file mode 100644
index f01da877148e..000000000000
--- a/arch/arm/mach-bcmring/include/cfg_global.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _CFG_GLOBAL_H_
-#define _CFG_GLOBAL_H_
-#include <cfg_global_defines.h>
-#define CFG_GLOBAL_CHIP                         BCM11107
-#define CFG_GLOBAL_CHIP_FAMILY                  CFG_GLOBAL_CHIP_FAMILY_BCMRING
-#define CFG_GLOBAL_CHIP_REV                     0xB0
-#define CFG_GLOBAL_RAM_SIZE                     0x10000000
-#define CFG_GLOBAL_RAM_BASE                     0x00000000
-#define CFG_GLOBAL_RAM_RESERVED_SIZE            0x000000
-#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h b/arch/arm/mach-bcmring/include/cfg_global_defines.h
deleted file mode 100644
index b5beb0b30734..000000000000
--- a/arch/arm/mach-bcmring/include/cfg_global_defines.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*****************************************************************************
-* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CFG_GLOBAL_DEFINES_H
-#define CFG_GLOBAL_DEFINES_H
-/* CHIP */
-#define BCM1103 1
-#define BCM1191 4
-#define BCM2153 5
-#define BCM2820 6
-#define BCM2826 8
-#define FPGA11107 9
-#define BCM11107   10
-#define BCM11109   11
-#define BCM11170   12
-#define BCM11110   13
-#define BCM11211   14
-/* CFG_GLOBAL_CHIP_FAMILY types */
-#define CFG_GLOBAL_CHIP_FAMILY_NONE        0
-#define CFG_GLOBAL_CHIP_FAMILY_BCM116X     2
-#define CFG_GLOBAL_CHIP_FAMILY_BCMRING     4
-#define CFG_GLOBAL_CHIP_FAMILY_BCM1103     8
-#define IMAGE_HEADER_SIZE_CHECKSUM    4
-#endif
diff --git a/arch/arm/mach-bcmring/include/csp/cache.h b/arch/arm/mach-bcmring/include/csp/cache.h
deleted file mode 100644
index caa20e59db99..000000000000
--- a/arch/arm/mach-bcmring/include/csp/cache.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CSP_CACHE_H
-#define CSP_CACHE_H
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-/* ---- Public Constants and Types --------------------------------------- */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <asm/cacheflush.h>
-#define CSP_CACHE_FLUSH_ALL      flush_cache_all()
-#else
-#define CSP_CACHE_FLUSH_ALL
-#endif
-#endif /* CSP_CACHE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/delay.h b/arch/arm/mach-bcmring/include/csp/delay.h
deleted file mode 100644
index 8b3d80367293..000000000000
--- a/arch/arm/mach-bcmring/include/csp/delay.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CSP_DELAY_H
-#define CSP_DELAY_H
-/* ---- Include Files ---------------------------------------------------- */
-/* Some CSP routines require use of the following delay routines. Use the OS */
-/* version if available, otherwise use a CSP specific definition. */
-/* void udelay(unsigned long usecs); */
-/* void mdelay(unsigned long msecs); */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-   #include <linux/delay.h>
-#else
-   #include <mach/csp/delay.h>
-#endif
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-#endif /*  CSP_DELAY_H */
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h
deleted file mode 100644
index e6a1dc484ca7..000000000000
--- a/arch/arm/mach-bcmring/include/csp/dmacHw.h
+++ /dev/null
@@ -1,596 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    dmacHw.h
-*
-*  @brief   API definitions for low level DMA controller driver
-*
-*/
-/****************************************************************************/
-#ifndef _DMACHW_H
-#define _DMACHW_H
-#include <stddef.h>
-#include <csp/stdint.h>
-#include <mach/csp/dmacHw_reg.h>
-/* Define DMA Channel ID using DMA controller number (m) and channel number (c).
-   System specific channel ID should be defined as follows
-   For example:
-   #include <dmacHw.h>
-   ...
-   #define systemHw_LCD_CHANNEL_ID                dmacHw_MAKE_CHANNEL_ID(0,5)
-   #define systemHw_SWITCH_RX_CHANNEL_ID          dmacHw_MAKE_CHANNEL_ID(0,0)
-   #define systemHw_SWITCH_TX_CHANNEL_ID          dmacHw_MAKE_CHANNEL_ID(0,1)
-   #define systemHw_APM_RX_CHANNEL_ID             dmacHw_MAKE_CHANNEL_ID(0,3)
-   #define systemHw_APM_TX_CHANNEL_ID             dmacHw_MAKE_CHANNEL_ID(0,4)
-   ...
-   #define systemHw_SHARED1_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(1,4)
-   #define systemHw_SHARED2_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(1,5)
-   #define systemHw_SHARED3_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(0,6)
-   ...
-*/
-#define dmacHw_MAKE_CHANNEL_ID(m, c)         (m << 8 | c)
-typedef enum {
-        dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0,    /* Channel priority 0. Lowest priority DMA channel */
-        dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1,    /* Channel priority 1 */
-        dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2,    /* Channel priority 2 */
-        dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3,    /* Channel priority 3 */
-        dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4,    /* Channel priority 4 */
-        dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5,    /* Channel priority 5 */
-        dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6,    /* Channel priority 6 */
-        dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7     /* Channel priority 7. Highest priority DMA channel */
-} dmacHw_CHANNEL_PRIORITY_e;
-/* Source destination master interface */
-typedef enum {
-        dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1,   /* Source DMA master interface 1 */
-        dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2,   /* Source DMA master interface 2 */
-        dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1,   /* Destination DMA master interface 1 */
-        dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2    /* Destination DMA master interface 2 */
-} dmacHw_MASTER_INTERFACE_e;
-typedef enum {
-        dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, /* Source 8 bit  (1 byte) per transaction */
-        dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16,       /* Source 16 bit (2 byte) per transaction */
-        dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32,       /* Source 32 bit (4 byte) per transaction */
-        dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64,       /* Source 64 bit (8 byte) per transaction */
-        dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, /* Destination 8 bit  (1 byte) per transaction */
-        dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16,       /* Destination 16 bit (2 byte) per transaction */
-        dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32,       /* Destination 32 bit (4 byte) per transaction */
-        dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64        /* Destination 64 bit (8 byte) per transaction */
-} dmacHw_TRANSACTION_WIDTH_e;
-typedef enum {
-        dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0,  /* Source No burst */
-        dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4,  /* Source 4  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-        dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8,  /* Source 8  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-        dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16,        /* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-        dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0,  /* Destination No burst */
-        dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4,  /* Destination 4  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-        dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8,  /* Destination 8  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-        dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16 /* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-} dmacHw_BURST_WIDTH_e;
-typedef enum {
-        dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC,  /* Memory to memory transfer */
-        dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC,   /* Peripheral to memory transfer */
-        dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC,   /* Memory to peripheral transfer */
-        dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC     /* Peripheral to peripheral transfer */
-} dmacHw_TRANSFER_TYPE_e;
-typedef enum {
-        dmacHw_TRANSFER_MODE_PERREQUEST,        /* Block transfer per DMA request */
-        dmacHw_TRANSFER_MODE_CONTINUOUS,        /* Continuous transfer of streaming data */
-        dmacHw_TRANSFER_MODE_PERIODIC   /* Periodic transfer of streaming data */
-} dmacHw_TRANSFER_MODE_e;
-typedef enum {
-        dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC,   /* Increment source address after every transaction */
-        dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC,   /* Decrement source address after every transaction */
-        dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC,   /* Increment destination address after every transaction */
-        dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC,   /* Decrement destination address after every transaction */
-        dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC,     /* No change in source address after every transaction */
-        dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC      /* No change in destination address after every transaction */
-} dmacHw_ADDRESS_UPDATE_MODE_e;
-typedef enum {
-        dmacHw_FLOW_CONTROL_DMA,        /* DMA working as flow controller (default) */
-        dmacHw_FLOW_CONTROL_PERIPHERAL  /* Peripheral working as flow controller */
-} dmacHw_FLOW_CONTROL_e;
-typedef enum {
-        dmacHw_TRANSFER_STATUS_BUSY,    /* DMA Transfer ongoing */
-        dmacHw_TRANSFER_STATUS_DONE,    /* DMA Transfer completed */
-        dmacHw_TRANSFER_STATUS_ERROR    /* DMA Transfer error */
-} dmacHw_TRANSFER_STATUS_e;
-typedef enum {
-        dmacHw_INTERRUPT_DISABLE,       /* Interrupt disable  */
-        dmacHw_INTERRUPT_ENABLE /* Interrupt enable */
-} dmacHw_INTERRUPT_e;
-typedef enum {
-        dmacHw_INTERRUPT_STATUS_NONE = 0x0,     /* No DMA interrupt */
-        dmacHw_INTERRUPT_STATUS_TRANS = 0x1,    /* End of DMA transfer interrupt */
-        dmacHw_INTERRUPT_STATUS_BLOCK = 0x2,    /* End of block transfer interrupt */
-        dmacHw_INTERRUPT_STATUS_ERROR = 0x4     /* Error interrupt */
-} dmacHw_INTERRUPT_STATUS_e;
-typedef enum {
-        dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM,   /* Number of DMA channel */
-        dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE,        /* Maximum channel burst size */
-        dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM,       /* Number of DMA master interface */
-        dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH,     /* Channel Data bus width */
-        dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE      /* Channel FIFO size */
-} dmacHw_CONTROLLER_ATTRIB_e;
-typedef unsigned long dmacHw_HANDLE_t;  /* DMA channel handle */
-typedef uint32_t dmacHw_ID_t;   /* DMA channel Id.  Must be created using
-                                   "dmacHw_MAKE_CHANNEL_ID" macro
-                                 */
-/* DMA channel configuration parameters */
-typedef struct {
-        uint32_t srcPeripheralPort;     /* Source peripheral port */
-        uint32_t dstPeripheralPort;     /* Destination peripheral port */
-        uint32_t srcStatusRegisterAddress;      /* Source status register address */
-        uint32_t dstStatusRegisterAddress;      /* Destination status register address of type  */
-        uint32_t srcGatherWidth;        /* Number of bytes gathered before successive gather opearation */
-        uint32_t srcGatherJump; /* Number of bytes jumpped before successive gather opearation */
-        uint32_t dstScatterWidth;       /* Number of bytes sacattered before successive scatter opearation */
-        uint32_t dstScatterJump;        /* Number of bytes jumpped  before successive scatter opearation */
-        uint32_t maxDataPerBlock;       /* Maximum number of bytes to be transferred per block/descrptor.
-                                           0 = Maximum possible.
-                                         */
-        dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate; /* Source address update mode */
-        dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate; /* Destination address update mode */
-        dmacHw_TRANSFER_TYPE_e transferType;    /* DMA transfer type  */
-        dmacHw_TRANSFER_MODE_e transferMode;    /* DMA transfer mode */
-        dmacHw_MASTER_INTERFACE_e srcMasterInterface;   /* DMA source interface  */
-        dmacHw_MASTER_INTERFACE_e dstMasterInterface;   /* DMA destination interface */
-        dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth;      /* Source transaction width   */
-        dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth;      /* Destination transaction width */
-        dmacHw_BURST_WIDTH_e srcMaxBurstWidth;  /* Source burst width */
-        dmacHw_BURST_WIDTH_e dstMaxBurstWidth;  /* Destination burst width */
-        dmacHw_INTERRUPT_e blockTransferInterrupt;      /* Block trsnafer interrupt */
-        dmacHw_INTERRUPT_e completeTransferInterrupt;   /* Complete DMA trsnafer interrupt */
-        dmacHw_INTERRUPT_e errorInterrupt;      /* Error interrupt */
-        dmacHw_CHANNEL_PRIORITY_e channelPriority;      /* Channel priority */
-        dmacHw_FLOW_CONTROL_e flowControler;    /* Data flow controller */
-} dmacHw_CONFIG_t;
-/****************************************************************************/
-/**
-*  @brief   Initializes DMA
-*
-*  This function initializes DMA CSP driver
-*
-*  @note
-*     Must be called before using any DMA channel
-*/
-/****************************************************************************/
-void dmacHw_initDma(void);
-/****************************************************************************/
-/**
-*  @brief   Exit function for  DMA
-*
-*  This function isolates DMA from the system
-*
-*/
-/****************************************************************************/
-void dmacHw_exitDma(void);
-/****************************************************************************/
-/**
-*  @brief   Gets a handle to a DMA channel
-*
-*  This function returns a handle, representing a control block of a particular DMA channel
-*
-*  @return  -1       - On Failure
-*            handle  - On Success, representing a channel control block
-*
-*  @note
-*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId   /* [ IN ] DMA Channel Id */
-    );
-/****************************************************************************/
-/**
-*  @brief   Initializes a DMA channel for use
-*
-*  This function initializes and resets a DMA channel for use
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_initChannel(dmacHw_HANDLE_t handle   /*  [ IN ] DMA Channel handle  */
-    );
-/****************************************************************************/
-/**
-*  @brief  Estimates number of descriptor needed to perform certain DMA transfer
-*
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor count
-*
-*
-*/
-/****************************************************************************/
-int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,   /*   [ IN ] Configuration settings */
-                                    void *pSrcAddr,     /*   [ IN ] Source (Peripheral/Memory) address */
-                                    void *pDstAddr,     /*   [ IN ] Destination (Peripheral/Memory) address */
-                                    size_t dataLen      /*   [ IN ] Data length in bytes */
-    );
-/****************************************************************************/
-/**
-*  @brief   Initializes descriptor ring
-*
-*  This function will initializes the descriptor ring of a DMA channel
-*
-*
-*  @return   -1 - On failure
-*             0 - On success
-*  @note
-*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
-*     - Descriptor buffer MUST be 32 bit aligned and uncached as it
-*       is accessed by ARM and DMA
-*/
-/****************************************************************************/
-int dmacHw_initDescriptor(void *pDescriptorVirt,        /*  [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
-                          uint32_t descriptorPhyAddr,   /*  [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
-                          uint32_t len, /*  [ IN ] Size of the pBuf */
-                          uint32_t num  /*  [ IN ] Number of descriptor in the ring */
-    );
-/****************************************************************************/
-/**
-*  @brief  Finds amount of memory required to form a descriptor ring
-*
-*
-*  @return   Number of bytes required to form a descriptor ring
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorLen(uint32_t descCnt  /*  [ IN ] Number of descriptor in the ring */
-    );
-/****************************************************************************/
-/**
-*  @brief   Configure DMA channel
-*
-*  @return  0  : On success
-*           -1 : On failure
-*/
-/****************************************************************************/
-int dmacHw_configChannel(dmacHw_HANDLE_t handle,        /*  [ IN ] DMA Channel handle  */
-                         dmacHw_CONFIG_t *pConfig       /*   [ IN ] Configuration settings */
-    );
-/****************************************************************************/
-/**
-*  @brief   Set descriptors for known data length
-*
-*  When DMA has to work as a flow controller, this function prepares the
-*  descriptor chain to transfer data
-*
-*  from:
-*          - Memory to memory
-*          - Peripheral to memory
-*          - Memory to Peripheral
-*          - Peripheral to Peripheral
-*
-*  @return   -1 - On failure
-*             0 - On success
-*
-*/
-/****************************************************************************/
-int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,  /*  [ IN ] Configuration settings */
-                             void *pDescriptor, /*  [ IN ] Descriptor buffer  */
-                             void *pSrcAddr,    /*  [ IN ] Source (Peripheral/Memory) address */
-                             void *pDstAddr,    /*  [ IN ] Destination (Peripheral/Memory) address */
-                             size_t dataLen     /*  [ IN ] Length in bytes   */
-    );
-/****************************************************************************/
-/**
-*  @brief   Indicates whether DMA transfer is in progress or completed
-*
-*  @return   DMA transfer status
-*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
-*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
-*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
-*
-*/
-/****************************************************************************/
-dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle        /*   [ IN ] DMA Channel handle  */
-    );
-/****************************************************************************/
-/**
-*  @brief   Set descriptor carrying control information
-*
-*  This function will be used to send specific control information to the device
-*  using the DMA channel
-*
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,       /*  [ IN ] Configuration settings */
-                                void *pDescriptor,      /*  [ IN ] Descriptor buffer  */
-                                uint32_t ctlAddress,    /*  [ IN ] Address of the device control register  */
-                                uint32_t control        /*  [ IN ] Device control information */
-    );
-/****************************************************************************/
-/**
-*  @brief   Read data DMA transferred to memory
-*
-*  This function will read data that has been DMAed to memory while transferring from:
-*          - Memory to memory
-*          - Peripheral to memory
-*
-*  @return  0 - No more data is available to read
-*           1 - More data might be available to read
-*
-*/
-/****************************************************************************/
-int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle    */
-                               dmacHw_CONFIG_t *pConfig,        /*  [ IN ]  Configuration settings */
-                               void *pDescriptor,       /*  [ IN ] Descriptor buffer  */
-                               void **ppBbuf,   /*  [ OUT ] Data received */
-                               size_t *pLlen    /*  [ OUT ] Length of the data received */
-    );
-/****************************************************************************/
-/**
-*  @brief   Prepares descriptor ring, when source peripheral working as a flow controller
-*
-*  This function will form the descriptor ring by allocating buffers, when source peripheral
-*  has to work as a flow controller to transfer data from:
-*           - Peripheral to memory.
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,    /*  [ IN ] DMA Channel handle   */
-                                     dmacHw_CONFIG_t *pConfig,  /*  [ IN ] Configuration settings */
-                                     void *pDescriptor, /*  [ IN ] Descriptor buffer  */
-                                     uint32_t srcAddr,  /*  [ IN ] Source peripheral address */
-                                     void *(*fpAlloc) (int len),        /*  [ IN ] Function pointer  that provides destination memory */
-                                     int len,   /*  [ IN ] Number of bytes "fpAlloc" will allocate for destination */
-                                     int num    /*  [ IN ] Number of descriptor to set */
-    );
-/****************************************************************************/
-/**
-*  @brief   Program channel register to initiate transfer
-*
-*  @return  void
-*
-*
-*  @note
-*     - Descriptor buffer MUST ALWAYS be flushed before calling this function
-*     - This function should also be called from ISR to program the channel with
-*       pending descriptors
-*/
-/****************************************************************************/
-void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,    /*   [ IN ] DMA Channel handle */
-                             dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
-                             void *pDescriptor  /*   [ IN ] Descriptor buffer  */
-    );
-/****************************************************************************/
-/**
-*  @brief   Resets descriptor control information
-*
-*  @return  void
-*/
-/****************************************************************************/
-void dmacHw_resetDescriptorControl(void *pDescriptor    /*   [ IN ] Descriptor buffer  */
-    );
-/****************************************************************************/
-/**
-*  @brief   Program channel register to stop transfer
-*
-*  Ensures the channel is not doing any transfer after calling this function
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /*   [ IN ] DMA Channel handle */
-    );
-/****************************************************************************/
-/**
-*  @brief   Check the existence of pending descriptor
-*
-*  This function confirmes if there is any pending descriptor in the chain
-*  to program the channel
-*
-*  @return  1 : Channel need to be programmed with pending descriptor
-*           0 : No more pending descriptor to programe the channel
-*
-*  @note
-*     - This function should be called from ISR in case there are pending
-*       descriptor to program the channel.
-*
-*     Example:
-*
-*     dmac_isr ()
-*     {
-*         ...
-*         if (dmacHw_descriptorPending (handle))
-*         {
-*            dmacHw_initiateTransfer (handle);
-*         }
-*     }
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,       /*   [ IN ] DMA Channel handle */
-                                  void *pDescriptor     /*   [ IN ] Descriptor buffer */
-    );
-/****************************************************************************/
-/**
-*  @brief   Deallocates source or destination memory, allocated
-*
-*  This function can be called to deallocate data memory that was DMAed successfully
-*
-*  @return  -1  - On failure
-*            0  - On success
-*
-*  @note
-*     This function will be called ONLY, when source OR destination address is pointing
-*     to dynamic memory
-*/
-/****************************************************************************/
-int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,    /*  [ IN ] Configuration settings */
-                   void *pDescriptor,   /*  [ IN ] Descriptor buffer  */
-                   void (*fpFree) (void *)      /*  [ IN ] Function pointer to free data memory */
-    );
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the DMA channel specific interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle       /*  [ IN ] DMA Channel handle  */
-    );
-/****************************************************************************/
-/**
-*  @brief   Returns the cause of channel specific DMA interrupt
-*
-*  This function returns the cause of interrupt
-*
-*  @return  Interrupt status, each bit representing a specific type of interrupt
-*           of type dmacHw_INTERRUPT_STATUS_e
-*  @note
-*           This function should be called under the context of ISR
-*/
-/****************************************************************************/
-dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle      /*  [ IN ] DMA Channel handle  */
-    );
-/****************************************************************************/
-/**
-*  @brief   Indentifies a DMA channel causing interrupt
-*
-*  This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
-*
-*  @return  NULL   : No channel causing DMA interrupt
-*           ! NULL : Handle to a channel causing DMA interrupt
-*  @note
-*     dmacHw_clearInterrupt() must be called with a valid handle after calling this function
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
-/****************************************************************************/
-/**
-*  @brief   Sets channel specific user data
-*
-*  This function associates user data to a specific DMA channel
-*
-*/
-/****************************************************************************/
-void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle  */
-                               void *userData   /*  [ IN ] User data  */
-    );
-/****************************************************************************/
-/**
-*  @brief   Gets channel specific user data
-*
-*  This function returns user data specific to a DMA channel
-*
-*  @return   user data
-*/
-/****************************************************************************/
-void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle  /*  [ IN ] DMA Channel handle  */
-    );
-/****************************************************************************/
-/**
-*  @brief   Displays channel specific registers and other control parameters
-*
-*
-*  @return  void
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,      /*  [ IN ] DMA Channel handle  */
-                           void *pDescriptor,   /*  [ IN ] Descriptor buffer  */
-                           int (*fpPrint) (const char *, ...)   /*  [ IN ] Print callback function */
-    );
-/****************************************************************************/
-/**
-*  @brief   Provides DMA controller attributes
-*
-*
-*  @return  DMA controller attributes
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,       /*  [ IN ]  DMA Channel handle  */
-                                          dmacHw_CONTROLLER_ATTRIB_e attr       /*  [ IN ]  DMA Controller attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
-    );
-#endif /* _DMACHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/errno.h b/arch/arm/mach-bcmring/include/csp/errno.h
deleted file mode 100644
index 51357dd5b666..000000000000
--- a/arch/arm/mach-bcmring/include/csp/errno.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CSP_ERRNO_H
-#define CSP_ERRNO_H
-/* ---- Include Files ---------------------------------------------------- */
-#if   defined(__KERNEL__)
-#include <linux/errno.h>
-#elif defined(CSP_SIMULATION)
-#include <asm-generic/errno.h>
-#else
-#include <errno.h>
-#endif
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-#endif /* CSP_ERRNO_H */
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h
deleted file mode 100644
index 1c639c8ee08f..000000000000
--- a/arch/arm/mach-bcmring/include/csp/intcHw.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    intcHw.h
-*
-*  @brief   generic interrupt controller API
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-#ifndef _INTCHW_H
-#define _INTCHW_H
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/intcHw_reg.h>
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask);
-static inline void intcHw_irq_enable(void *basep, uint32_t mask);
-#endif /* _INTCHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/module.h b/arch/arm/mach-bcmring/include/csp/module.h
deleted file mode 100644
index c30d2a5975a6..000000000000
--- a/arch/arm/mach-bcmring/include/csp/module.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CSP_MODULE_H
-#define CSP_MODULE_H
-/* ---- Include Files ---------------------------------------------------- */
-#ifdef __KERNEL__
-    #include <linux/module.h>
-#else
-    #define EXPORT_SYMBOL(symbol)
-#endif
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-#endif /* CSP_MODULE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/csp/reg.h
deleted file mode 100644
index 56654d23c3d7..000000000000
--- a/arch/arm/mach-bcmring/include/csp/reg.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    reg.h
-*
-*  @brief   Generic register definitions used in CSP
-*/
-/****************************************************************************/
-#ifndef CSP_REG_H
-#define CSP_REG_H
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-/* ---- Public Constants and Types --------------------------------------- */
-#define __REG32(x)      (*((volatile uint32_t *)(x)))
-#define __REG16(x)      (*((volatile uint16_t *)(x)))
-#define __REG8(x)       (*((volatile uint8_t *) (x)))
-/* Macros used to define a sequence of reserved registers. The start / end */
-/* are byte offsets in the particular register definition, with the "end" */
-/* being the offset of the next un-reserved register. E.g. if offsets */
-/* 0x10 through to 0x1f are reserved, then this reserved area could be */
-/* specified as follows. */
-/*  typedef struct */
-/*  { */
-/*      uint32_t reg1;           offset 0x00 */
-/*      uint32_t reg2;           offset 0x04 */
-/*      uint32_t reg3;           offset 0x08 */
-/*      uint32_t reg4;           offset 0x0c */
-/*      REG32_RSVD(0x10, 0x20); */
-/*      uint32_t reg5;           offset 0x20 */
-/*      ... */
-/*  } EXAMPLE_REG_t; */
-#define REG8_RSVD(start, end)   uint8_t rsvd_##start[(end - start) / sizeof(uint8_t)]
-#define REG16_RSVD(start, end)  uint16_t rsvd_##start[(end - start) / sizeof(uint16_t)]
-#define REG32_RSVD(start, end)  uint32_t rsvd_##start[(end - start) / sizeof(uint32_t)]
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */
-/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the  */
-/* flags variable to be declared locally. */
-/* e.g. */
-/*    statement1; */
-/*    { */
-/*       REG_LOCAL_IRQ_SAVE; */
-/*       <multiple statements here> */
-/*       REG_LOCAL_IRQ_RESTORE; */
-/*    } */
-/*    statement2; */
-/*  */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <mach/hardware.h>
-#include <linux/interrupt.h>
-#define REG_LOCAL_IRQ_SAVE      HW_DECLARE_SPINLOCK(reg32) \
-        unsigned long flags; HW_IRQ_SAVE(reg32, flags)
-#define REG_LOCAL_IRQ_RESTORE   HW_IRQ_RESTORE(reg32, flags)
-#else
-#define REG_LOCAL_IRQ_SAVE
-#define REG_LOCAL_IRQ_RESTORE
-#endif
-static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
-{
-        REG_LOCAL_IRQ_SAVE;
-        *reg &= value;
-        REG_LOCAL_IRQ_RESTORE;
-}
-static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
-{
-        REG_LOCAL_IRQ_SAVE;
-        *reg |= value;
-        REG_LOCAL_IRQ_RESTORE;
-}
-static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
-                                     uint32_t value)
-{
-        REG_LOCAL_IRQ_SAVE;
-        *reg = (*reg & mask) | value;
-        REG_LOCAL_IRQ_RESTORE;
-}
-static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
-{
-        *reg = value;
-}
-#endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h b/arch/arm/mach-bcmring/include/csp/secHw.h
deleted file mode 100644
index b9d7e0732dfc..000000000000
--- a/arch/arm/mach-bcmring/include/csp/secHw.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    secHw.h
-*
-*  @brief   Definitions for accessing low level security features
-*
-*/
-/****************************************************************************/
-#ifndef SECHW_H
-#define SECHW_H
-typedef void (*secHw_FUNC_t) (void);
-typedef enum {
-        secHw_MODE_SECURE = 0x0,        /* Switches processor into secure mode */
-        secHw_MODE_NONSECURE = 0x1      /* Switches processor into non-secure mode */
-} secHw_MODE;
-/****************************************************************************/
-/**
-*  @brief   Requesting to execute the function in secure mode
-*
-*  This function requests the given function to run in secure mode
-*
-*/
-/****************************************************************************/
-void secHw_RunSecure(secHw_FUNC_t       /* Function to run in secure mode */
-    );
-/****************************************************************************/
-/**
-*  @brief   Sets the  mode
-*
-*  his function sets the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_SetMode(secHw_MODE   /* Processor mode */
-    );
-/****************************************************************************/
-/**
-*  @brief   Get the current mode
-*
-*  This function retieves the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_GetMode(secHw_MODE *);
-#endif /* SECHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h b/arch/arm/mach-bcmring/include/csp/stdint.h
deleted file mode 100644
index 3a8718bbf700..000000000000
--- a/arch/arm/mach-bcmring/include/csp/stdint.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CSP_STDINT_H
-#define CSP_STDINT_H
-/* ---- Include Files ---------------------------------------------------- */
-#ifdef __KERNEL__
-#include <linux/types.h>
-#else
-#include <stdint.h>
-#endif
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-#endif /* CSP_STDINT_H */
diff --git a/arch/arm/mach-bcmring/include/csp/string.h b/arch/arm/mach-bcmring/include/csp/string.h
deleted file mode 100644
index ad9e4005f141..000000000000
--- a/arch/arm/mach-bcmring/include/csp/string.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CSP_STRING_H
-#define CSP_STRING_H
-/* ---- Include Files ---------------------------------------------------- */
-#ifdef __KERNEL__
-   #include <linux/string.h>
-#else
-   #include <string.h>
-#endif
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-#endif /* CSP_STRING_H */
diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h b/arch/arm/mach-bcmring/include/csp/tmrHw.h
deleted file mode 100644
index 2cbb530db8ea..000000000000
--- a/arch/arm/mach-bcmring/include/csp/tmrHw.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    tmrHw.h
-*
-*  @brief   API definitions for low level Timer driver
-*
-*/
-/****************************************************************************/
-#ifndef _TMRHW_H
-#define _TMRHW_H
-#include <csp/stdint.h>
-typedef uint32_t tmrHw_ID_t;    /* Timer ID */
-typedef uint32_t tmrHw_COUNT_t; /* Timer count */
-typedef uint32_t tmrHw_INTERVAL_t;      /* Timer interval */
-typedef uint32_t tmrHw_RATE_t;  /* Timer event (count/interrupt) rate */
-typedef enum {
-        tmrHw_INTERRUPT_STATUS_SET,     /* Interrupted  */
-        tmrHw_INTERRUPT_STATUS_UNSET    /* No Interrupt */
-} tmrHw_INTERRUPT_STATUS_e;
-typedef enum {
-        tmrHw_CAPABILITY_CLOCK, /* Clock speed in HHz */
-        tmrHw_CAPABILITY_RESOLUTION     /* Timer resolution in bits */
-} tmrHw_CAPABILITY_e;
-/****************************************************************************/
-/**
-*  @brief   Get timer capability
-*
-*  This function returns various capabilities/attributes of a timer
-*
-*  @return  Numeric capability
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,   /*  [ IN ] Timer Id */
-                                  tmrHw_CAPABILITY_e capability /*  [ IN ] Timer capability */
-);
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer in terms of timer interrupt rate
-*
-*  This function initializes a periodic timer to generate specific number of
-*  timer interrupt per second
-*
-*  @return   On success: Effective timer frequency
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
-                                        tmrHw_RATE_t rate       /*  [ IN ] Number of timer interrupt per second */
-);
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt after
-*           certain time interval
-*
-*  This function initializes a periodic timer to generate timer interrupt
-*  after every time interval in millisecond
-*
-*  @return   On success: Effective interval set in mili-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
-                                                tmrHw_INTERVAL_t msec   /*  [ IN ] Interval in mili-second */
-);
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt just once
-*           after certain time interval
-*
-*  This function initializes a periodic timer to generate a single ticks after
-*  certain time interval in millisecond
-*
-*  @return   On success: Effective interval set in mili-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
-                                               tmrHw_INTERVAL_t msec    /*  [ IN ] Interval in mili-second */
-);
-/****************************************************************************/
-/**
-*  @brief   Configures a timer to run as a free running timer
-*
-*  This function initializes a timer to run as a free running timer
-*
-*  @return   Timer resolution (count / sec)
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
-                                       uint32_t divider /*  [ IN ] Dividing the clock frequency */
-) __attribute__ ((section(".aramtext")));
-/****************************************************************************/
-/**
-*  @brief   Starts a timer
-*
-*  This function starts a preconfigured timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*/
-/****************************************************************************/
-int tmrHw_startTimer(tmrHw_ID_t timerId /*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-/****************************************************************************/
-/**
-*  @brief   Stops a timer
-*
-*  This function stops a running timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*/
-/****************************************************************************/
-int tmrHw_stopTimer(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
-);
-/****************************************************************************/
-/**
-*  @brief   Gets current timer count
-*
-*  This function returns the current timer value
-*
-*  @return  Current downcounting timer value
-*
-*/
-/****************************************************************************/
-tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-/****************************************************************************/
-/**
-*  @brief   Gets timer count rate
-*
-*  This function returns the number of counts per second
-*
-*  @return  Count rate
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId      /*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-/****************************************************************************/
-/**
-*  @brief   Enables timer interrupt
-*
-*  This function enables the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_enableInterrupt(tmrHw_ID_t timerId   /*  [ IN ] Timer id */
-);
-/****************************************************************************/
-/**
-*  @brief   Disables timer interrupt
-*
-*  This function disable the timer interrupt
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_disableInterrupt(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
-);
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the timer interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void tmrHw_clearInterrupt(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
-);
-/****************************************************************************/
-/**
-*  @brief   Gets the interrupt status
-*
-*  This function returns timer interrupt status
-*
-*  @return   Interrupt status
-*/
-/****************************************************************************/
-tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
-);
-/****************************************************************************/
-/**
-*  @brief   Indentifies a timer causing interrupt
-*
-*  This functions returns a timer causing interrupt
-*
-*  @return  0xFFFFFFFF   : No timer causing an interrupt
-*           ! 0xFFFFFFFF : timer causing an interrupt
-*  @note
-*     tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
-*/
-/****************************************************************************/
-tmrHw_ID_t tmrHw_getInterruptSource(void);
-/****************************************************************************/
-/**
-*  @brief   Displays specific timer registers
-*
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void tmrHw_printDebugInfo(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
-                          int (*fpPrint) (const char *, ...)    /*  [ IN ] Print callback function */
-);
-/****************************************************************************/
-/**
-*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_udelay(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
-                  unsigned long usecs   /*  [ IN ] usec to delay */
-) __attribute__ ((section(".aramtext")));
-#endif /* _TMRHW_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap.h b/arch/arm/mach-bcmring/include/mach/csp/cap.h
deleted file mode 100644
index 30fa2d540630..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/cap.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*****************************************************************************
-* Copyright 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CAP_H
-#define CAP_H
-/* ---- Include Files ---------------------------------------------------- */
-/* ---- Public Constants and Types --------------------------------------- */
-typedef enum {
-        CAP_NOT_PRESENT = 0,
-        CAP_PRESENT
-} CAP_RC_T;
-typedef enum {
-        CAP_VPM,
-        CAP_ETH_PHY,
-        CAP_ETH_GMII,
-        CAP_ETH_SGMII,
-        CAP_USB,
-        CAP_TSC,
-        CAP_EHSS,
-        CAP_SDIO,
-        CAP_UARTB,
-        CAP_KEYPAD,
-        CAP_CLCD,
-        CAP_GE,
-        CAP_LEDM,
-        CAP_BBL,
-        CAP_VDEC,
-        CAP_PIF,
-        CAP_APM,
-        CAP_SPU,
-        CAP_PKA,
-        CAP_RNG,
-} CAP_CAPABILITY_T;
-typedef enum {
-        CAP_LCD_WVGA = 0,
-        CAP_LCD_VGA = 0x1,
-        CAP_LCD_WQVGA = 0x2,
-        CAP_LCD_QVGA = 0x3
-} CAP_LCD_RES_T;
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index);
-static inline uint32_t cap_getMaxArmSpeedHz(void);
-static inline uint32_t cap_getMaxVpmSpeedHz(void);
-static inline CAP_LCD_RES_T cap_getMaxLcdRes(void);
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
deleted file mode 100644
index 933ce68ed90b..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*****************************************************************************
-* Copyright 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CAP_INLINE_H
-#define CAP_INLINE_H
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/cap.h>
-#include <cfg_global.h>
-/* ---- Public Constants and Types --------------------------------------- */
-#define CAP_CONFIG0_VPM_DIS          0x00000001
-#define CAP_CONFIG0_ETH_PHY0_DIS     0x00000002
-#define CAP_CONFIG0_ETH_PHY1_DIS     0x00000004
-#define CAP_CONFIG0_ETH_GMII0_DIS    0x00000008
-#define CAP_CONFIG0_ETH_GMII1_DIS    0x00000010
-#define CAP_CONFIG0_ETH_SGMII0_DIS   0x00000020
-#define CAP_CONFIG0_ETH_SGMII1_DIS   0x00000040
-#define CAP_CONFIG0_USB0_DIS         0x00000080
-#define CAP_CONFIG0_USB1_DIS         0x00000100
-#define CAP_CONFIG0_TSC_DIS          0x00000200
-#define CAP_CONFIG0_EHSS0_DIS        0x00000400
-#define CAP_CONFIG0_EHSS1_DIS        0x00000800
-#define CAP_CONFIG0_SDIO0_DIS        0x00001000
-#define CAP_CONFIG0_SDIO1_DIS        0x00002000
-#define CAP_CONFIG0_UARTB_DIS        0x00004000
-#define CAP_CONFIG0_KEYPAD_DIS       0x00008000
-#define CAP_CONFIG0_CLCD_DIS         0x00010000
-#define CAP_CONFIG0_GE_DIS           0x00020000
-#define CAP_CONFIG0_LEDM_DIS         0x00040000
-#define CAP_CONFIG0_BBL_DIS          0x00080000
-#define CAP_CONFIG0_VDEC_DIS         0x00100000
-#define CAP_CONFIG0_PIF_DIS          0x00200000
-#define CAP_CONFIG0_RESERVED1_DIS    0x00400000
-#define CAP_CONFIG0_RESERVED2_DIS    0x00800000
-#define CAP_CONFIG1_APMA_DIS         0x00000001
-#define CAP_CONFIG1_APMB_DIS         0x00000002
-#define CAP_CONFIG1_APMC_DIS         0x00000004
-#define CAP_CONFIG1_CLCD_RES_MASK    0x00000600
-#define CAP_CONFIG1_CLCD_RES_SHIFT   9
-#define CAP_CONFIG1_CLCD_RES_WVGA    (CAP_LCD_WVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_VGA     (CAP_LCD_VGA << CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_WQVGA   (CAP_LCD_WQVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_QVGA    (CAP_LCD_QVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG2_SPU_DIS          0x00000010
-#define CAP_CONFIG2_PKA_DIS          0x00000020
-#define CAP_CONFIG2_RNG_DIS          0x00000080
-#if   (CFG_GLOBAL_CHIP == BCM11107)
-#define capConfig0 0
-#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 3
-#elif (CFG_GLOBAL_CHIP == FPGA11107)
-#define capConfig0 0
-#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 3
-#elif (CFG_GLOBAL_CHIP == BCM11109)
-#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11170)
-#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11110)
-#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 CAP_CONFIG1_APMC_DIS
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | CAP_CONFIG0_CLCD_DIS)
-#define capConfig1 CAP_CONFIG1_APMC_DIS
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 2
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
-#define CAP_HW_CFG_ARM_CLK_HZ 500000000
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
-#define CAP_HW_CFG_ARM_CLK_HZ 300000000
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-#define CAP_HW_CFG_ARM_CLK_HZ 666666666
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
-#define CAP_HW_CFG_VPM_CLK_HZ 333333333
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
-#define CAP_HW_CFG_VPM_CLK_HZ 200000000
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-/****************************************************************************
-*  cap_isPresent -
-*
-*  PURPOSE:
-*     Determines if the chip has a certain capability present
-*
-*  PARAMETERS:
-*     capability - type of capability to determine if present
-*
-*  RETURNS:
-*     CAP_PRESENT or CAP_NOT_PRESENT
-****************************************************************************/
-static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index)
-{
-        CAP_RC_T returnVal = CAP_NOT_PRESENT;
-        switch (capability) {
-        case CAP_VPM:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_ETH_PHY:
-                {
-                        if ((index == 0)
-                            && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 1)
-                            && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_ETH_GMII:
-                {
-                        if ((index == 0)
-                            && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 1)
-                            && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_ETH_SGMII:
-                {
-                        if ((index == 0)
-                            && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 1)
-                            && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_USB:
-                {
-                        if ((index == 0)
-                            && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 1)
-                            && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_TSC:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_EHSS:
-                {
-                        if ((index == 0)
-                            && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 1)
-                            && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_SDIO:
-                {
-                        if ((index == 0)
-                            && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 1)
-                            && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_UARTB:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_KEYPAD:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_CLCD:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_GE:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_LEDM:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_BBL:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_VDEC:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_PIF:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_APM:
-                {
-                        if ((index == 0)
-                            && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 1)
-                            && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 2)
-                            && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_SPU:
-                {
-                        if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_PKA:
-                {
-                        if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        case CAP_RNG:
-                {
-                        if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-        default:
-                {
-                }
-                break;
-        }
-        return returnVal;
-}
-/****************************************************************************
-*  cap_getMaxArmSpeedHz -
-*
-*  PURPOSE:
-*     Determines the maximum speed of the ARM CPU
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*     clock speed in Hz that the ARM processor is able to run at
-****************************************************************************/
-static inline uint32_t cap_getMaxArmSpeedHz(void)
-{
-#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
-        return 500000000;
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
-        return 300000000;
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-        return 666666666;
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-}
-/****************************************************************************
-*  cap_getMaxVpmSpeedHz -
-*
-*  PURPOSE:
-*     Determines the maximum speed of the VPM
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*     clock speed in Hz that the VPM is able to run at
-****************************************************************************/
-static inline uint32_t cap_getMaxVpmSpeedHz(void)
-{
-#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
-        return 333333333;
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
-        return 200000000;
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-}
-/****************************************************************************
-*  cap_getMaxLcdRes -
-*
-*  PURPOSE:
-*     Determines the maximum LCD resolution capabilities
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*   CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA
-*
-****************************************************************************/
-static inline CAP_LCD_RES_T cap_getMaxLcdRes(void)
-{
-        return (CAP_LCD_RES_T)
-                ((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >>
-                 CAP_CONFIG1_CLCD_RES_SHIFT);
-}
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
deleted file mode 100644
index 161973385faf..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
+++ /dev/null
@@ -1,1123 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CHIPC_DEF_H
-#define CHIPC_DEF_H
-/* ---- Include Files ----------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/errno.h>
-#include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-/* ---- Public Constants and Types ---------------------------------------- */
-/* Set 1 to configure DDR/VPM phase alignment by HW */
-#define chipcHw_DDR_HW_PHASE_ALIGN    0
-#define chipcHw_VPM_HW_PHASE_ALIGN    0
-typedef uint32_t chipcHw_freq;
-/* Configurable miscellaneous clocks */
-typedef enum {
-        chipcHw_CLOCK_DDR,      /* DDR PHY Clock */
-        chipcHw_CLOCK_ARM,      /* ARM Clock */
-        chipcHw_CLOCK_ESW,      /* Ethernet Switch Clock */
-        chipcHw_CLOCK_VPM,      /* VPM Clock */
-        chipcHw_CLOCK_ESW125,   /* Ethernet MII Clock */
-        chipcHw_CLOCK_UART,     /* UART Clock */
-        chipcHw_CLOCK_SDIO0,    /* SDIO 0 Clock */
-        chipcHw_CLOCK_SDIO1,    /* SDIO 1 Clock */
-        chipcHw_CLOCK_SPI,      /* SPI Clock */
-        chipcHw_CLOCK_ETM,      /* ARM ETM Clock */
-        chipcHw_CLOCK_BUS,      /* BUS Clock */
-        chipcHw_CLOCK_OTP,      /* OTP Clock */
-        chipcHw_CLOCK_I2C,      /* I2C Host Clock */
-        chipcHw_CLOCK_I2S0,     /* I2S 0 Host Clock */
-        chipcHw_CLOCK_RTBUS,    /* DDR PHY Configuration Clock */
-        chipcHw_CLOCK_APM100,   /* APM100 Clock */
-        chipcHw_CLOCK_TSC,      /* Touch screen Clock */
-        chipcHw_CLOCK_LED,      /* LED Clock */
-        chipcHw_CLOCK_USB,      /* USB Clock */
-        chipcHw_CLOCK_LCD,      /* LCD CLock */
-        chipcHw_CLOCK_APM,      /* APM Clock */
-        chipcHw_CLOCK_I2S1,     /* I2S 1 Host Clock */
-} chipcHw_CLOCK_e;
-/* System booting strap options */
-typedef enum {
-        chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART,
-        chipcHw_BOOT_DEVICE_SERIAL_FLASH =
-            chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH,
-        chipcHw_BOOT_DEVICE_NOR_FLASH_16 =
-            chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16,
-        chipcHw_BOOT_DEVICE_NAND_FLASH_8 =
-            chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8,
-        chipcHw_BOOT_DEVICE_NAND_FLASH_16 =
-            chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16
-} chipcHw_BOOT_DEVICE_e;
-/* System booting modes */
-typedef enum {
-        chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL,
-        chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW,
-        chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT,
-        chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET
-} chipcHw_BOOT_MODE_e;
-/* NAND Flash page size strap options */
-typedef enum {
-        chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512,
-        chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048,
-        chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096,
-        chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT
-} chipcHw_NAND_PAGESIZE_e;
-/* GPIO Pin function */
-typedef enum {
-        chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD,
-        chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH,
-        chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI,
-        chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART,
-        chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP,
-        chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS,
-        chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0,
-        chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1,
-        chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM,
-        chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S,
-        chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM,
-        chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG,
-        chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC,
-        chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO
-} chipcHw_GPIO_FUNCTION_e;
-/* PIN Output slew rate */
-typedef enum {
-        chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH,
-        chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL
-} chipcHw_PIN_SLEW_RATE_e;
-/* PIN Current drive strength */
-typedef enum {
-        chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA,
-        chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA,
-        chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA,
-        chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA,
-        chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA,
-        chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA
-} chipcHw_PIN_CURRENT_STRENGTH_e;
-/* PIN Pull up register settings */
-typedef enum {
-        chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE,
-        chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP,
-        chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN
-} chipcHw_PIN_PULL_e;
-/* PIN input type settings */
-typedef enum {
-        chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS,
-        chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST
-} chipcHw_PIN_INPUTTYPE_e;
-/* Allow/Disalow the support of spread spectrum  */
-typedef enum {
-        chipcHw_SPREAD_SPECTRUM_DISALLOW,       /* Spread spectrum support is not allowed */
-        chipcHw_SPREAD_SPECTRUM_ALLOW   /* Spread spectrum support is allowed */
-} chipcHw_SPREAD_SPECTRUM_e;
-typedef struct {
-        chipcHw_SPREAD_SPECTRUM_e ssSupport;    /* Allow/Disalow to support spread spectrum.
-                                                   If supported, call chipcHw_enableSpreadSpectrum ()
-                                                   to activate the spread spectrum with desired spread. */
-        uint32_t pllVcoFreqHz;  /* PLL VCO frequency in Hz */
-        uint32_t pll2VcoFreqHz; /* PLL2 VCO frequency in Hz */
-        uint32_t busClockFreqHz;        /* Bus clock frequency in Hz */
-        uint32_t armBusRatio;   /* ARM clock : Bus clock */
-        uint32_t vpmBusRatio;   /* VPM clock : Bus clock */
-        uint32_t ddrBusRatio;   /* DDR clock : Bus clock */
-} chipcHw_INIT_PARAM_t;
-/* CHIP revision number */
-typedef enum {
-        chipcHw_REV_NUMBER_A0 = chipcHw_REG_REV_A0,
-        chipcHw_REV_NUMBER_B0 = chipcHw_REG_REV_B0
-} chipcHw_REV_NUMBER_e;
-typedef enum {
-        chipcHw_VPM_HW_PHASE_INTR_DISABLE = chipcHw_REG_VPM_INTR_DISABLE,
-        chipcHw_VPM_HW_PHASE_INTR_FAST = chipcHw_REG_VPM_INTR_FAST,
-        chipcHw_VPM_HW_PHASE_INTR_MEDIUM = chipcHw_REG_VPM_INTR_MEDIUM,
-        chipcHw_VPM_HW_PHASE_INTR_SLOW = chipcHw_REG_VPM_INTR_SLOW
-} chipcHw_VPM_HW_PHASE_INTR_e;
-typedef enum {
-        chipcHw_DDR_HW_PHASE_MARGIN_STRICT,     /*  Strict margin for DDR phase align condition */
-        chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM,     /*  Medium margin for DDR phase align condition */
-        chipcHw_DDR_HW_PHASE_MARGIN_WIDE        /*  Wider margin for DDR phase align condition */
-} chipcHw_DDR_HW_PHASE_MARGIN_e;
-typedef enum {
-        chipcHw_VPM_HW_PHASE_MARGIN_STRICT,     /*  Strict margin for VPM phase align condition */
-        chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM,     /*  Medium margin for VPM phase align condition */
-        chipcHw_VPM_HW_PHASE_MARGIN_WIDE        /*  Wider margin for VPM phase align condition */
-} chipcHw_VPM_HW_PHASE_MARGIN_e;
-#define chipcHw_XTAL_FREQ_Hz                    25000000        /* Reference clock frequency in Hz */
-/* Programmable pin defines */
-#define chipcHw_PIN_GPIO(n)                     ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF)
-                                                                             /* GPIO pin 0 - 60 */
-#define chipcHw_PIN_UARTTXD                     (chipcHw_GPIO_COUNT + 0)        /* UART Transmit */
-#define chipcHw_PIN_NVI_A                       (chipcHw_GPIO_COUNT + 1)        /* NVI Interface */
-#define chipcHw_PIN_NVI_D                       (chipcHw_GPIO_COUNT + 2)        /* NVI Interface */
-#define chipcHw_PIN_NVI_OEB                     (chipcHw_GPIO_COUNT + 3)        /* NVI Interface */
-#define chipcHw_PIN_NVI_WEB                     (chipcHw_GPIO_COUNT + 4)        /* NVI Interface */
-#define chipcHw_PIN_NVI_CS                      (chipcHw_GPIO_COUNT + 5)        /* NVI Interface */
-#define chipcHw_PIN_NVI_NAND_CSB                (chipcHw_GPIO_COUNT + 6)        /* NVI Interface */
-#define chipcHw_PIN_NVI_FLASHWP                 (chipcHw_GPIO_COUNT + 7)        /* NVI Interface */
-#define chipcHw_PIN_NVI_NAND_RDYB               (chipcHw_GPIO_COUNT + 8)        /* NVI Interface */
-#define chipcHw_PIN_CL_DATA_0_17                (chipcHw_GPIO_COUNT + 9)        /* LCD Data 0 - 17 */
-#define chipcHw_PIN_CL_DATA_18_20               (chipcHw_GPIO_COUNT + 10)       /* LCD Data 18 - 20 */
-#define chipcHw_PIN_CL_DATA_21_23               (chipcHw_GPIO_COUNT + 11)       /* LCD Data 21 - 23 */
-#define chipcHw_PIN_CL_POWER                    (chipcHw_GPIO_COUNT + 12)       /* LCD Power */
-#define chipcHw_PIN_CL_ACK                      (chipcHw_GPIO_COUNT + 13)       /* LCD Ack */
-#define chipcHw_PIN_CL_FP                       (chipcHw_GPIO_COUNT + 14)       /* LCD FP */
-#define chipcHw_PIN_CL_LP                       (chipcHw_GPIO_COUNT + 15)       /* LCD LP */
-#define chipcHw_PIN_UARTRXD                     (chipcHw_GPIO_COUNT + 16)       /* UART Receive */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-/****************************************************************************/
-/**
-*  @brief  Initializes the clock module
-*
-*/
-/****************************************************************************/
-void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam       /*  [ IN ] Misc chip initialization parameter */
-    ) __attribute__ ((section(".aramtext")));
-/****************************************************************************/
-/**
-*  @brief  Enables the PLL1
-*
-*  This function enables the PLL1
-*
-*/
-/****************************************************************************/
-void chipcHw_pll1Enable(uint32_t vcoFreqHz,     /*  [ IN ] VCO frequency in Hz */
-                        chipcHw_SPREAD_SPECTRUM_e ssSupport     /*  [ IN ] SS status */
-    ) __attribute__ ((section(".aramtext")));
-/****************************************************************************/
-/**
-*  @brief  Enables the PLL2
-*
-*  This function enables the PLL2
-*
-*/
-/****************************************************************************/
-void chipcHw_pll2Enable(uint32_t vcoFreqHz      /*  [ IN ] VCO frequency in Hz */
-    ) __attribute__ ((section(".aramtext")));
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL1
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll1Disable(void);
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL2
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll2Disable(void);
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in KHz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock    /*  [ IN ] Configurable clock */
-    ) __attribute__ ((section(".aramtext")));
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in Hz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,   /*  [ IN ] Configurable clock */
-                                       uint32_t freq    /*  [ IN ] Clock frequency in Hz */
-    ) __attribute__ ((section(".aramtext")));
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success ( # of adjustment required )
-*            -1 : On failure
-*/
-/****************************************************************************/
-int chipcHw_vpmPhaseAlign(void);
-/****************************************************************************/
-/**
-*  @brief   Enables core a clock of a certain device
-*
-*  This function enables a core clock
-*
-*  @return  void
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock /*  [ IN ] Configurable clock */
-    );
-/****************************************************************************/
-/**
-*  @brief   Disabled a core clock of a certain device
-*
-*  This function disables a core clock
-*
-*  @return  void
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock        /*  [ IN ] Configurable clock */
-    );
-/****************************************************************************/
-/**
-*  @brief   Enables bypass clock of a certain device
-*
-*  This function enables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock      /*  [ IN ] Configurable clock */
-    );
-/****************************************************************************/
-/**
-*  @brief   Disabled bypass clock of a certain device
-*
-*  This function disables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock     /*  [ IN ] Configurable clock */
-    );
-/****************************************************************************/
-/**
-*  @brief   Get Numeric Chip ID
-*
-*  This function returns Chip ID that includes the revison number
-*
-*  @return  Complete numeric Chip ID
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipId(void);
-/****************************************************************************/
-/**
-*  @brief   Get Chip Product ID
-*
-*  This function returns Chip Product ID
-*
-*  @return  Chip Product ID
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipProductId(void);
-/****************************************************************************/
-/**
-*  @brief   Get revision number
-*
-*  This function returns revision number of the chip
-*
-*  @return  Revision number
-*/
-/****************************************************************************/
-static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void);
-/****************************************************************************/
-/**
-*  @brief   Enables bus interface clock
-*
-*  Enables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockEnable(uint32_t mask        /*  [ IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
-    );
-/****************************************************************************/
-/**
-*  @brief   Disables bus interface clock
-*
-*  Disables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockDisable(uint32_t mask       /*  [ IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
-    );
-/****************************************************************************/
-/**
-*  @brief   Enables various audio channels
-*
-*  Enables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelEnable(uint32_t mask     /*  [ IN ] Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
-    );
-/****************************************************************************/
-/**
-*  @brief   Disables various audio channels
-*
-*  Disables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelDisable(uint32_t mask    /*  [ IN ] Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
-    );
-/****************************************************************************/
-/**
-*  @brief    Soft resets devices
-*
-*  Soft resets various devices
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
-*/
-/****************************************************************************/
-static inline void chipcHw_softReset(uint64_t mask      /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-static inline void chipcHw_softResetDisable(uint64_t mask       /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-static inline void chipcHw_softResetEnable(uint64_t mask        /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-/****************************************************************************/
-/**
-*  @brief    Configures misc CHIP functionality
-*
-*  Configures CHIP functionality
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_miscControl(uint32_t mask    /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-static inline void chipcHw_miscControlDisable(uint32_t mask     /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-static inline void chipcHw_miscControlEnable(uint32_t mask      /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-/****************************************************************************/
-/**
-*  @brief    Set OTP options
-*
-*  Set OTP options
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_OTP_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setOTPOption(uint64_t mask   /*  [ IN ] Bit map of type chipcHw_REG_OTP_XXXXXX */
-    );
-/****************************************************************************/
-/**
-*  @brief    Get sticky bits
-*
-*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getStickyBits(void);
-/****************************************************************************/
-/**
-*  @brief    Set sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setStickyBits(uint32_t mask  /*  [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
-    );
-/****************************************************************************/
-/**
-*  @brief    Clear sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_clearStickyBits(uint32_t mask        /*  [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
-    );
-/****************************************************************************/
-/**
-*  @brief    Get software override strap options
-*
-*  Retrieves software override strap options
-*
-*  @return   Software override strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getSoftStraps(void);
-/****************************************************************************/
-/**
-*  @brief    Set software override strap options
-*
-*  set software override strap options
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setSoftStraps(uint32_t strapOptions);
-/****************************************************************************/
-/**
-*  @brief    Get pin strap options
-*
-*  Retrieves pin strap options
-*
-*  @return   Pin strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getPinStraps(void);
-/****************************************************************************/
-/**
-*  @brief    Get valid pin strap options
-*
-*  Retrieves valid pin strap options
-*
-*  @return   valid Pin strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getValidStraps(void);
-/****************************************************************************/
-/**
-*  @brief    Initialize valid pin strap options
-*
-*  Retrieves valid pin strap options by copying HW strap options to soft register
-*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_initValidStraps(void);
-/****************************************************************************/
-/**
-*  @brief   Get status (enabled/disabled) of bus interface clock
-*
-*  This function returns the status of devices' bus interface clock
-*
-*  @return  Bus interface clock
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getBusInterfaceClockStatus(void);
-/****************************************************************************/
-/**
-*  @brief   Get boot device
-*
-*  This function returns the device type used in booting the system
-*
-*  @return  Boot device of type chipcHw_BOOT_DEVICE_e
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void);
-/****************************************************************************/
-/**
-*  @brief   Get boot mode
-*
-*  This function returns the way the system was booted
-*
-*  @return  Boot mode of type chipcHw_BOOT_MODE_e
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void);
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash page size
-*
-*  This function returns the NAND device page size
-*
-*  @return  Boot NAND device page size
-*
-*/
-/****************************************************************************/
-static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void);
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash address cycle configuration
-*
-*  This function returns the NAND flash address cycle configuration
-*
-*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
-*
-*/
-/****************************************************************************/
-static inline int chipcHw_getNandExtraCycle(void);
-/****************************************************************************/
-/**
-*  @brief   Activates PIF interface
-*
-*  This function activates PIF interface by taking control of LCD pins
-*
-*  @note
-*       When activated, LCD pins will be defined as follows for PIF operation
-*
-*       CLD[17:0]  = pif_data[17:0]
-*       CLD[23:18] = pif_address[5:0]
-*       CLPOWER    = pif_wr_str
-*       CLCP       = pif_rd_str
-*       CLAC       = pif_hat1
-*       CLFP       = pif_hrdy1
-*       CLLP       = pif_hat2
-*       GPIO[42]   = pif_hrdy2
-*
-*       In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_activatePifInterface(void);
-/****************************************************************************/
-/**
-*  @brief   Activates LCD interface
-*
-*  This function activates LCD interface
-*
-*  @note
-*       When activated, LCD pins will be defined as follows
-*
-*       CLD[17:0]  = LCD data
-*       CLD[23:18] = LCD data
-*       CLPOWER    = LCD power
-*       CLCP       =
-*       CLAC       = LCD ack
-*       CLFP       =
-*       CLLP       =
-*/
-/****************************************************************************/
-static inline void chipcHw_activateLcdInterface(void);
-/****************************************************************************/
-/**
-*  @brief   Deactivates PIF/LCD interface
-*
-*  This function deactivates PIF/LCD interface
-*
-*  @note
-*       When deactivated LCD pins will be in rti-stated
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_deactivatePifLcdInterface(void);
-/****************************************************************************/
-/**
-*  @brief   Get to know the configuration of GPIO pin
-*
-*/
-/****************************************************************************/
-static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin        /* GPIO Pin number */
-    );
-/****************************************************************************/
-/**
-*  @brief   Configure GPIO pin function
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setGpioPinFunction(int pin,  /* GPIO Pin number */
-                                              chipcHw_GPIO_FUNCTION_e func      /* Configuration function */
-    );
-/****************************************************************************/
-/**
-*  @brief   Set Pin slew rate
-*
-*  This function sets the slew of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinSlewRate(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
-                                          chipcHw_PIN_SLEW_RATE_e slewRate      /* Pin slew rate */
-    );
-/****************************************************************************/
-/**
-*  @brief   Set Pin output drive current
-*
-*  This function sets output drive current of individual pin
-*
-*  Note: Avoid the use of the word 'current' since linux headers define this
-*        to be the current task.
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinOutputCurrent(uint32_t pin,    /* Pin of type chipcHw_PIN_XXXXX */
-                                               chipcHw_PIN_CURRENT_STRENGTH_e curr      /* Pin current rating */
-    );
-/****************************************************************************/
-/**
-*  @brief   Set Pin pullup register
-*
-*  This function sets pullup register of individual  pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinPullup(uint32_t pin,   /* Pin of type chipcHw_PIN_XXXXX */
-                                        chipcHw_PIN_PULL_e pullup       /* Pullup register settings */
-    );
-/****************************************************************************/
-/**
-*  @brief   Set Pin input type
-*
-*  This function sets input type of individual Pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinInputType(uint32_t pin,        /* Pin of type chipcHw_PIN_XXXXX */
-                                           chipcHw_PIN_INPUTTYPE_e inputType    /* Pin input type */
-    );
-/****************************************************************************/
-/**
-*  @brief   Retrieves a string representation of the mux setting for a pin.
-*
-*  @return  Pointer to a character string.
-*/
-/****************************************************************************/
-const char *chipcHw_getGpioPinFunctionStr(int pin);
-/****************************************************************************/
-/**  @brief issue warmReset
- */
-/****************************************************************************/
-void chipcHw_reset(uint32_t mask);
-/****************************************************************************/
-/**  @brief clock reconfigure
- */
-/****************************************************************************/
-void chipcHw_clockReconfig(uint32_t busHz, uint32_t armRatio, uint32_t vpmRatio,
-                           uint32_t ddrRatio);
-/****************************************************************************/
-/**
-*  @brief   Enable Spread Spectrum
-*
-*  @note chipcHw_Init() must be called earlier
-*/
-/****************************************************************************/
-static inline void chipcHw_enableSpreadSpectrum(void);
-/****************************************************************************/
-/**
-*  @brief   Disable Spread Spectrum
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_disableSpreadSpectrum(void);
-/****************************************************************************/
-/**  @brief Checks if software strap is enabled
- *
- *   @return 1 : When enable
- *           0 : When disable
- */
-/****************************************************************************/
-static inline int chipcHw_isSoftwareStrapsEnable(void);
-/****************************************************************************/
-/**  @brief Enable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsEnable(void);
-/****************************************************************************/
-/**  @brief Disable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsDisable(void);
-/****************************************************************************/
-/**  @brief PLL test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestEnable(void);
-/****************************************************************************/
-/**  @brief PLL2 test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestEnable(void);
-/****************************************************************************/
-/**  @brief PLL test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestDisable(void);
-/****************************************************************************/
-/**  @brief PLL2 test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestDisable(void);
-/****************************************************************************/
-/**  @brief Get PLL test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPllTestEnable(void);
-/****************************************************************************/
-/**  @brief Get PLL2 test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPll2TestEnable(void);
-/****************************************************************************/
-/**  @brief PLL test select
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestSelect(uint32_t val);
-/****************************************************************************/
-/**  @brief PLL2 test select
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestSelect(uint32_t val);
-/****************************************************************************/
-/**  @brief Get PLL test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPllTestSelected(void);
-/****************************************************************************/
-/**  @brief Get PLL2 test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPll2TestSelected(void);
-/****************************************************************************/
-/**
-*  @brief   Enables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptEnable(void);
-/****************************************************************************/
-/**
-*  @brief   Disables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptDisable(void);
-/****************************************************************************/
-/**
-*  @brief   Set VPM SW phase alignment interrupt mode
-*
-*  This function sets VPM phase alignment interrupt
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode);
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignEnable(void);
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignDisable(void);
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignEnable(void);
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignDisable(void);
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignEnable(void);
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignDisable(void);
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignEnable(void);
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignDisable(void);
-/****************************************************************************/
-/**
-*  @brief   Set DDR phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin        /* Margin alinging DDR  phase */
-    );
-/****************************************************************************/
-/**
-*  @brief   Set VPM phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin        /* Margin alinging VPM  phase */
-    );
-/****************************************************************************/
-/**
-*  @brief   Checks DDR phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isDdrHwPhaseAligned(void);
-/****************************************************************************/
-/**
-*  @brief   Checks VPM phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isVpmHwPhaseAligned(void);
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void);
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void);
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrPhaseControl(void);
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmPhaseControl(void);
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a DDR phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle     /* Timeout in bus cycle */
-    );
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a VPM phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle     /* Timeout in bus cycle */
-    );
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void);
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void);
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void);
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void);
-/****************************************************************************/
-/**
-*  @brief   Clear DDR phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void);
-/****************************************************************************/
-/**
-*  @brief   Clear VPM phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void);
-/* ---- Private Constants and Types -------------------------------------- */
-#endif /* CHIPC_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
deleted file mode 100644
index 03238c299001..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
+++ /dev/null
@@ -1,1673 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CHIPC_INLINE_H
-#define CHIPC_INLINE_H
-/* ---- Include Files ----------------------------------------------------- */
-#include <csp/errno.h>
-#include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_def.h>
-/* ---- Private Constants and Types --------------------------------------- */
-typedef enum {
-        chipcHw_OPTYPE_BYPASS,  /* Bypass operation */
-        chipcHw_OPTYPE_OUTPUT   /* Output operation */
-} chipcHw_OPTYPE_e;
-/* ---- Public Constants and Types ---------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------- */
-/* ---- Public Function Prototypes ---------------------------------------- */
-/* ---- Private Function Prototypes --------------------------------------- */
-static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
-                                    chipcHw_OPTYPE_e type, int mode);
-/****************************************************************************/
-/**
-*  @brief   Get Numeric Chip ID
-*
-*  This function returns Chip ID that includes the revison number
-*
-*  @return  Complete numeric Chip ID
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipId(void)
-{
-        return pChipcHw->ChipId;
-}
-/****************************************************************************/
-/**
-*  @brief   Enable Spread Spectrum
-*
-*  @note chipcHw_Init() must be called earlier
-*/
-/****************************************************************************/
-static inline void chipcHw_enableSpreadSpectrum(void)
-{
-        if ((pChipcHw->
-             PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
-            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-                ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
-                    (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
-                    (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
-                     ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
-                ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
-                    ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
-        }
-}
-/****************************************************************************/
-/**
-*  @brief   Disable Spread Spectrum
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_disableSpreadSpectrum(void)
-{
-        ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
-}
-/****************************************************************************/
-/**
-*  @brief   Get Chip Product ID
-*
-*  This function returns Chip Product ID
-*
-*  @return  Chip Product ID
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipProductId(void)
-{
-        return (pChipcHw->
-                 ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
-                chipcHw_REG_CHIPID_BASE_SHIFT;
-}
-/****************************************************************************/
-/**
-*  @brief   Get revision number
-*
-*  This function returns revision number of the chip
-*
-*  @return  Revision number
-*/
-/****************************************************************************/
-static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
-{
-        return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
-}
-/****************************************************************************/
-/**
-*  @brief   Enables bus interface clock
-*
-*  Enables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX for mask
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockEnable(uint32_t mask)
-{
-        reg32_modify_or(&pChipcHw->BusIntfClock, mask);
-}
-/****************************************************************************/
-/**
-*  @brief   Disables bus interface clock
-*
-*  Disables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
-{
-        reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
-}
-/****************************************************************************/
-/**
-*  @brief   Get status (enabled/disabled) of bus interface clock
-*
-*  This function returns the status of devices' bus interface clock
-*
-*  @return  Bus interface clock
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
-{
-        return pChipcHw->BusIntfClock;
-}
-/****************************************************************************/
-/**
-*  @brief   Enables various audio channels
-*
-*  Enables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelEnable(uint32_t mask)
-{
-        reg32_modify_or(&pChipcHw->AudioEnable, mask);
-}
-/****************************************************************************/
-/**
-*  @brief   Disables various audio channels
-*
-*  Disables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelDisable(uint32_t mask)
-{
-        reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
-}
-/****************************************************************************/
-/**
-*  @brief    Soft resets devices
-*
-*  Soft resets various devices
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
-*/
-/****************************************************************************/
-static inline void chipcHw_softReset(uint64_t mask)
-{
-        chipcHw_softResetEnable(mask);
-        chipcHw_softResetDisable(mask);
-}
-static inline void chipcHw_softResetDisable(uint64_t mask)
-{
-        uint32_t ctrl1 = (uint32_t) mask;
-        uint32_t ctrl2 = (uint32_t) (mask >> 32);
-        /* Deassert module soft reset */
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->SoftReset1 ^= ctrl1;
-        pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
-        REG_LOCAL_IRQ_RESTORE;
-}
-static inline void chipcHw_softResetEnable(uint64_t mask)
-{
-        uint32_t ctrl1 = (uint32_t) mask;
-        uint32_t ctrl2 = (uint32_t) (mask >> 32);
-        uint32_t unhold = 0;
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->SoftReset1 |= ctrl1;
-        /* Mask out unhold request bits */
-        pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
-        /* Process unhold requests */
-        if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
-                unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD;
-        }
-        if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) {
-                unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD;
-        }
-        if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) {
-                unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD;
-        }
-        if (unhold) {
-                /* Make sure unhold request is effective */
-                pChipcHw->SoftReset1 &= ~unhold;
-        }
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief    Configures misc CHIP functionality
-*
-*  Configures CHIP functionality
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_miscControl(uint32_t mask)
-{
-        reg32_write(&pChipcHw->MiscCtrl, mask);
-}
-static inline void chipcHw_miscControlDisable(uint32_t mask)
-{
-        reg32_modify_and(&pChipcHw->MiscCtrl, ~mask);
-}
-static inline void chipcHw_miscControlEnable(uint32_t mask)
-{
-        reg32_modify_or(&pChipcHw->MiscCtrl, mask);
-}
-/****************************************************************************/
-/**
-*  @brief    Set OTP options
-*
-*  Set OTP options
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_OTP_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setOTPOption(uint64_t mask)
-{
-        uint32_t ctrl1 = (uint32_t) mask;
-        uint32_t ctrl2 = (uint32_t) (mask >> 32);
-        reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1);
-        reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2);
-}
-/****************************************************************************/
-/**
-*  @brief    Get sticky bits
-*
-*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getStickyBits(void)
-{
-        return pChipcHw->Sticky;
-}
-/****************************************************************************/
-/**
-*  @brief    Set sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setStickyBits(uint32_t mask)
-{
-        uint32_t bits = 0;
-        REG_LOCAL_IRQ_SAVE;
-        if (mask & chipcHw_REG_STICKY_POR_BROM) {
-                bits |= chipcHw_REG_STICKY_POR_BROM;
-        } else {
-                uint32_t sticky;
-                sticky = pChipcHw->Sticky;
-                if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
-                    && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
-                        bits |= chipcHw_REG_STICKY_BOOT_DONE;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_1)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_1;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_2)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_2;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_3)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_3;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_4)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_4;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_5)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_5;
-                }
-        }
-        pChipcHw->Sticky = bits;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief    Clear sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_clearStickyBits(uint32_t mask)
-{
-        uint32_t bits = 0;
-        REG_LOCAL_IRQ_SAVE;
-        if (mask &
-            (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
-             chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
-             chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
-                uint32_t sticky = pChipcHw->Sticky;
-                if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
-                    && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
-                        bits = chipcHw_REG_STICKY_BOOT_DONE;
-                        mask &= ~chipcHw_REG_STICKY_BOOT_DONE;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_1)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_1)) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_1;
-                        mask &= ~chipcHw_REG_STICKY_GENERAL_1;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_2)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_2)) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_2;
-                        mask &= ~chipcHw_REG_STICKY_GENERAL_2;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_3)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_3)) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_3;
-                        mask &= ~chipcHw_REG_STICKY_GENERAL_3;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_4)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_4)) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_4;
-                        mask &= ~chipcHw_REG_STICKY_GENERAL_4;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_5)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_5)) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_5;
-                        mask &= ~chipcHw_REG_STICKY_GENERAL_5;
-                }
-        }
-        pChipcHw->Sticky = bits | mask;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief    Get software strap value
-*
-*  Retrieves software strap value
-*
-*  @return   Software strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getSoftStraps(void)
-{
-        return pChipcHw->SoftStraps;
-}
-/****************************************************************************/
-/**
-*  @brief    Set software override strap options
-*
-*  set software override strap options
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
-{
-        reg32_write(&pChipcHw->SoftStraps, strapOptions);
-}
-/****************************************************************************/
-/**
-*  @brief   Get Pin Strap Options
-*
-*  This function returns the raw boot strap options
-*
-*  @return  strap options
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getPinStraps(void)
-{
-        return pChipcHw->PinStraps;
-}
-/****************************************************************************/
-/**
-*  @brief   Get Valid Strap Options
-*
-*  This function returns the valid raw boot strap options
-*
-*  @return  strap options
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getValidStraps(void)
-{
-        uint32_t softStraps;
-        /*
-         ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps
-         ** which copies HW straps to soft straps if there is no override
-         */
-        softStraps = chipcHw_getSoftStraps();
-        return softStraps;
-}
-/****************************************************************************/
-/**
-*  @brief    Initialize valid pin strap options
-*
-*  Retrieves valid pin strap options by copying HW strap options to soft register
-*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_initValidStraps(void)
-{
-        uint32_t softStraps;
-        REG_LOCAL_IRQ_SAVE;
-        softStraps = chipcHw_getSoftStraps();
-        if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) {
-                /* Copy HW straps to software straps */
-                chipcHw_setSoftStraps(chipcHw_getPinStraps());
-        }
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Get boot device
-*
-*  This function returns the device type used in booting the system
-*
-*  @return  Boot device of type chipcHw_BOOT_DEVICE
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void)
-{
-        return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK;
-}
-/****************************************************************************/
-/**
-*  @brief   Get boot mode
-*
-*  This function returns the way the system was booted
-*
-*  @return  Boot mode of type chipcHw_BOOT_MODE
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void)
-{
-        return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK;
-}
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash page size
-*
-*  This function returns the NAND device page size
-*
-*  @return  Boot NAND device page size
-*
-*/
-/****************************************************************************/
-static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void)
-{
-        return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK;
-}
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash address cycle configuration
-*
-*  This function returns the NAND flash address cycle configuration
-*
-*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
-*
-*/
-/****************************************************************************/
-static inline int chipcHw_getNandExtraCycle(void)
-{
-        if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) {
-                return 1;
-        } else {
-                return 0;
-        }
-}
-/****************************************************************************/
-/**
-*  @brief   Activates PIF interface
-*
-*  This function activates PIF interface by taking control of LCD pins
-*
-*  @note
-*       When activated, LCD pins will be defined as follows for PIF operation
-*
-*       CLD[17:0]  = pif_data[17:0]
-*       CLD[23:18] = pif_address[5:0]
-*       CLPOWER    = pif_wr_str
-*       CLCP       = pif_rd_str
-*       CLAC       = pif_hat1
-*       CLFP       = pif_hrdy1
-*       CLLP       = pif_hat2
-*       GPIO[42]   = pif_hrdy2
-*
-*       In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_activatePifInterface(void)
-{
-        reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE);
-}
-/****************************************************************************/
-/**
-*  @brief   Activates LCD interface
-*
-*  This function activates LCD interface
-*
-*  @note
-*       When activated, LCD pins will be defined as follows
-*
-*       CLD[17:0]  = LCD data
-*       CLD[23:18] = LCD data
-*       CLPOWER    = LCD power
-*       CLCP       =
-*       CLAC       = LCD ack
-*       CLFP       =
-*       CLLP       =
-*/
-/****************************************************************************/
-static inline void chipcHw_activateLcdInterface(void)
-{
-        reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE);
-}
-/****************************************************************************/
-/**
-*  @brief   Deactivates PIF/LCD interface
-*
-*  This function deactivates PIF/LCD interface
-*
-*  @note
-*       When deactivated LCD pins will be in rti-stated
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_deactivatePifLcdInterface(void)
-{
-        reg32_write(&pChipcHw->LcdPifMode, 0);
-}
-/****************************************************************************/
-/**
-*  @brief   Select GE2
-*
-*  This function select GE2 as the graphic engine
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_selectGE2(void)
-{
-        reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL);
-}
-/****************************************************************************/
-/**
-*  @brief   Select GE3
-*
-*  This function select GE3 as the graphic engine
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_selectGE3(void)
-{
-        reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL);
-}
-/****************************************************************************/
-/**
-*  @brief   Get to know the configuration of GPIO pin
-*
-*/
-/****************************************************************************/
-static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
-{
-        return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
-                (chipcHw_REG_GPIO_MUX_MASK <<
-                 chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
-            chipcHw_REG_GPIO_MUX_POSITION(pin);
-}
-/****************************************************************************/
-/**
-*  @brief   Configure GPIO pin function
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setGpioPinFunction(int pin,
-                                              chipcHw_GPIO_FUNCTION_e func)
-{
-        REG_LOCAL_IRQ_SAVE;
-        *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &=
-            ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin));
-        *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |=
-            func << chipcHw_REG_GPIO_MUX_POSITION(pin);
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Set Pin slew rate
-*
-*  This function sets the slew of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinSlewRate(uint32_t pin,
-                                          chipcHw_PIN_SLEW_RATE_e slewRate)
-{
-        REG_LOCAL_IRQ_SAVE;
-        *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &=
-            ~(chipcHw_REG_SLEW_RATE_MASK <<
-              chipcHw_REG_SLEW_RATE_POSITION(pin));
-        *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |=
-            (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin);
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Set Pin output drive current
-*
-*  This function sets output drive current of individual pin
-*
-*  Note: Avoid the use of the word 'current' since linux headers define this
-*        to be the current task.
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinOutputCurrent(uint32_t pin,
-                                               chipcHw_PIN_CURRENT_STRENGTH_e
-                                               curr)
-{
-        REG_LOCAL_IRQ_SAVE;
-        *((uint32_t *) chipcHw_REG_CURRENT(pin)) &=
-            ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin));
-        *((uint32_t *) chipcHw_REG_CURRENT(pin)) |=
-            (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin);
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Set Pin pullup register
-*
-*  This function sets pullup register of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinPullup(uint32_t pin, chipcHw_PIN_PULL_e pullup)
-{
-        REG_LOCAL_IRQ_SAVE;
-        *((uint32_t *) chipcHw_REG_PULLUP(pin)) &=
-            ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin));
-        *((uint32_t *) chipcHw_REG_PULLUP(pin)) |=
-            (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin);
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Set Pin input type
-*
-*  This function sets input type of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinInputType(uint32_t pin,
-                                           chipcHw_PIN_INPUTTYPE_e inputType)
-{
-        REG_LOCAL_IRQ_SAVE;
-        *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &=
-            ~(chipcHw_REG_INPUTTYPE_MASK <<
-              chipcHw_REG_INPUTTYPE_POSITION(pin));
-        *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |=
-            (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin);
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Power up the USB PHY
-*
-*  This function powers up the USB PHY
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_powerUpUsbPhy(void)
-{
-        reg32_modify_and(&pChipcHw->MiscCtrl,
-                         chipcHw_REG_MISC_CTRL_USB_POWERON);
-}
-/****************************************************************************/
-/**
-*  @brief   Power down the USB PHY
-*
-*  This function powers down the USB PHY
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_powerDownUsbPhy(void)
-{
-        reg32_modify_or(&pChipcHw->MiscCtrl,
-                        chipcHw_REG_MISC_CTRL_USB_POWEROFF);
-}
-/****************************************************************************/
-/**
-*  @brief   Set the 2nd USB as host
-*
-*  This function sets the 2nd USB as host
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setUsbHost(void)
-{
-        reg32_modify_or(&pChipcHw->MiscCtrl,
-                        chipcHw_REG_MISC_CTRL_USB_MODE_HOST);
-}
-/****************************************************************************/
-/**
-*  @brief   Set the 2nd USB as device
-*
-*  This function sets the 2nd USB as device
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setUsbDevice(void)
-{
-        reg32_modify_and(&pChipcHw->MiscCtrl,
-                         chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE);
-}
-/****************************************************************************/
-/**
-*  @brief   Lower layer function to enable/disable a clock of a certain device
-*
-*  This function enables/disables a core clock
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
-                                    chipcHw_OPTYPE_e type, int mode)
-{
-        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-        switch (clock) {
-        case chipcHw_CLOCK_DDR:
-                pPLLReg = &pChipcHw->DDRClock;
-                break;
-        case chipcHw_CLOCK_ARM:
-                pPLLReg = &pChipcHw->ARMClock;
-                break;
-        case chipcHw_CLOCK_ESW:
-                pPLLReg = &pChipcHw->ESWClock;
-                break;
-        case chipcHw_CLOCK_VPM:
-                pPLLReg = &pChipcHw->VPMClock;
-                break;
-        case chipcHw_CLOCK_ESW125:
-                pPLLReg = &pChipcHw->ESW125Clock;
-                break;
-        case chipcHw_CLOCK_UART:
-                pPLLReg = &pChipcHw->UARTClock;
-                break;
-        case chipcHw_CLOCK_SDIO0:
-                pPLLReg = &pChipcHw->SDIO0Clock;
-                break;
-        case chipcHw_CLOCK_SDIO1:
-                pPLLReg = &pChipcHw->SDIO1Clock;
-                break;
-        case chipcHw_CLOCK_SPI:
-                pPLLReg = &pChipcHw->SPIClock;
-                break;
-        case chipcHw_CLOCK_ETM:
-                pPLLReg = &pChipcHw->ETMClock;
-                break;
-        case chipcHw_CLOCK_USB:
-                pPLLReg = &pChipcHw->USBClock;
-                if (type == chipcHw_OPTYPE_OUTPUT) {
-                        if (mode) {
-                                reg32_modify_and(pPLLReg,
-                                                 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-                        } else {
-                                reg32_modify_or(pPLLReg,
-                                                chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-                        }
-                }
-                break;
-        case chipcHw_CLOCK_LCD:
-                pPLLReg = &pChipcHw->LCDClock;
-                if (type == chipcHw_OPTYPE_OUTPUT) {
-                        if (mode) {
-                                reg32_modify_and(pPLLReg,
-                                                 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-                        } else {
-                                reg32_modify_or(pPLLReg,
-                                                chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-                        }
-                }
-                break;
-        case chipcHw_CLOCK_APM:
-                pPLLReg = &pChipcHw->APMClock;
-                if (type == chipcHw_OPTYPE_OUTPUT) {
-                        if (mode) {
-                                reg32_modify_and(pPLLReg,
-                                                 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-                        } else {
-                                reg32_modify_or(pPLLReg,
-                                                chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-                        }
-                }
-                break;
-        case chipcHw_CLOCK_BUS:
-                pClockCtrl = &pChipcHw->ACLKClock;
-                break;
-        case chipcHw_CLOCK_OTP:
-                pClockCtrl = &pChipcHw->OTPClock;
-                break;
-        case chipcHw_CLOCK_I2C:
-                pClockCtrl = &pChipcHw->I2CClock;
-                break;
-        case chipcHw_CLOCK_I2S0:
-                pClockCtrl = &pChipcHw->I2S0Clock;
-                break;
-        case chipcHw_CLOCK_RTBUS:
-                pClockCtrl = &pChipcHw->RTBUSClock;
-                break;
-        case chipcHw_CLOCK_APM100:
-                pClockCtrl = &pChipcHw->APM100Clock;
-                break;
-        case chipcHw_CLOCK_TSC:
-                pClockCtrl = &pChipcHw->TSCClock;
-                break;
-        case chipcHw_CLOCK_LED:
-                pClockCtrl = &pChipcHw->LEDClock;
-                break;
-        case chipcHw_CLOCK_I2S1:
-                pClockCtrl = &pChipcHw->I2S1Clock;
-                break;
-        }
-        if (pPLLReg) {
-                switch (type) {
-                case chipcHw_OPTYPE_OUTPUT:
-                        /* PLL clock output enable/disable */
-                        if (mode) {
-                                if (clock == chipcHw_CLOCK_DDR) {
-                                        /* DDR clock enable is inverted */
-                                        reg32_modify_and(pPLLReg,
-                                                         ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-                                } else {
-                                        reg32_modify_or(pPLLReg,
-                                                        chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-                                }
-                        } else {
-                                if (clock == chipcHw_CLOCK_DDR) {
-                                        /* DDR clock disable is inverted */
-                                        reg32_modify_or(pPLLReg,
-                                                        chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-                                } else {
-                                        reg32_modify_and(pPLLReg,
-                                                         ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-                                }
-                        }
-                        break;
-                case chipcHw_OPTYPE_BYPASS:
-                        /* PLL clock bypass enable/disable */
-                        if (mode) {
-                                reg32_modify_or(pPLLReg,
-                                                chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-                        } else {
-                                reg32_modify_and(pPLLReg,
-                                                 ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-                        }
-                        break;
-                }
-        } else if (pClockCtrl) {
-                switch (type) {
-                case chipcHw_OPTYPE_OUTPUT:
-                        if (mode) {
-                                reg32_modify_or(pClockCtrl,
-                                                chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
-                        } else {
-                                reg32_modify_and(pClockCtrl,
-                                                 ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
-                        }
-                        break;
-                case chipcHw_OPTYPE_BYPASS:
-                        if (mode) {
-                                reg32_modify_or(pClockCtrl,
-                                                chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-                        } else {
-                                reg32_modify_and(pClockCtrl,
-                                                 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-                        }
-                        break;
-                }
-        }
-}
-/****************************************************************************/
-/**
-*  @brief   Disables a core clock of a certain device
-*
-*  This function disables a core clock
-*
-*  @note    no change in power consumption
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock)
-{
-        /* Disable output of the clock */
-        chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0);
-}
-/****************************************************************************/
-/**
-*  @brief   Enable a core clock of a certain device
-*
-*  This function enables a core clock
-*
-*  @note    no change in power consumption
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock)
-{
-        /* Enable output of the clock */
-        chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1);
-}
-/****************************************************************************/
-/**
-*  @brief   Enables bypass clock of a certain device
-*
-*  This function enables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock)
-{
-        /* Enable bypass clock */
-        chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1);
-}
-/****************************************************************************/
-/**
-*  @brief   Disabled bypass clock of a certain device
-*
-*  This function disables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
-{
-        /* Disable bypass clock */
-        chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0);
-}
-/****************************************************************************/
-/**  @brief Checks if software strap is enabled
- *
- *   @return 1 : When enable
- *           0 : When disable
- */
-/****************************************************************************/
-static inline int chipcHw_isSoftwareStrapsEnable(void)
-{
-        return pChipcHw->SoftStraps & 0x00000001;
-}
-/****************************************************************************/
-/**  @brief Enable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsEnable(void)
-{
-        reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001);
-}
-/****************************************************************************/
-/**  @brief Disable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsDisable(void)
-{
-        reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001));
-}
-/****************************************************************************/
-/**  @brief PLL test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestEnable(void)
-{
-        reg32_modify_or(&pChipcHw->PLLConfig,
-                        chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-/****************************************************************************/
-/**  @brief PLL2 test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestEnable(void)
-{
-        reg32_modify_or(&pChipcHw->PLLConfig2,
-                        chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-/****************************************************************************/
-/**  @brief PLL test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestDisable(void)
-{
-        reg32_modify_and(&pChipcHw->PLLConfig,
-                         ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-/****************************************************************************/
-/**  @brief PLL2 test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestDisable(void)
-{
-        reg32_modify_and(&pChipcHw->PLLConfig2,
-                         ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-/****************************************************************************/
-/**  @brief Get PLL test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPllTestEnable(void)
-{
-        return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
-}
-/****************************************************************************/
-/**  @brief Get PLL2 test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPll2TestEnable(void)
-{
-        return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
-}
-/****************************************************************************/
-/**  @brief PLL test select
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestSelect(uint32_t val)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
-        pChipcHw->PLLConfig |=
-            (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**  @brief PLL2 test select
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestSelect(uint32_t val)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
-        pChipcHw->PLLConfig2 |=
-            (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**  @brief Get PLL test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPllTestSelected(void)
-{
-        return (uint8_t) ((pChipcHw->
-                           PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
-                          >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
-}
-/****************************************************************************/
-/**  @brief Get PLL2 test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPll2TestSelected(void)
-{
-        return (uint8_t) ((pChipcHw->
-                           PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
-                          >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
-}
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL1
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll1Disable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL2
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll2Disable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Enables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Disables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Set VPM SW phase alignment interrupt mode
-*
-*  This function sets VPM phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void
-chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode)
-{
-        REG_LOCAL_IRQ_SAVE;
-        if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) {
-                pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
-        } else {
-                pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
-        }
-        pChipcHw->VPMPhaseCtrl2 =
-            (pChipcHw->
-             VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK <<
-                               chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignEnable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignDisable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignEnable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignDisable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignEnable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignDisable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignEnable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignDisable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Set DDR phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin)
-{
-        uint32_t ge = 0;
-        uint32_t le = 0;
-        switch (margin) {
-        case chipcHw_DDR_HW_PHASE_MARGIN_STRICT:
-                ge = 0x0F;
-                le = 0x0F;
-                break;
-        case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM:
-                ge = 0x03;
-                le = 0x3F;
-                break;
-        case chipcHw_DDR_HW_PHASE_MARGIN_WIDE:
-                ge = 0x01;
-                le = 0x7F;
-                break;
-        }
-        {
-                REG_LOCAL_IRQ_SAVE;
-                pChipcHw->DDRPhaseCtrl1 &=
-                    ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK <<
-                       chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
-                      || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK <<
-                          chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
-                pChipcHw->DDRPhaseCtrl1 |=
-                    ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
-                     || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
-                REG_LOCAL_IRQ_RESTORE;
-        }
-}
-/****************************************************************************/
-/**
-*  @brief   Set VPM phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
-{
-        uint32_t ge = 0;
-        uint32_t le = 0;
-        switch (margin) {
-        case chipcHw_VPM_HW_PHASE_MARGIN_STRICT:
-                ge = 0x0F;
-                le = 0x0F;
-                break;
-        case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM:
-                ge = 0x03;
-                le = 0x3F;
-                break;
-        case chipcHw_VPM_HW_PHASE_MARGIN_WIDE:
-                ge = 0x01;
-                le = 0x7F;
-                break;
-        }
-        {
-                REG_LOCAL_IRQ_SAVE;
-                pChipcHw->VPMPhaseCtrl1 &=
-                    ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK <<
-                       chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
-                      || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK <<
-                          chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
-                pChipcHw->VPMPhaseCtrl1 |=
-                    ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
-                     || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
-                REG_LOCAL_IRQ_RESTORE;
-        }
-}
-/****************************************************************************/
-/**
-*  @brief   Checks DDR phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
-{
-        return (pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Checks VPM phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
-{
-        return (pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
-}
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
-{
-        return (pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
-            chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
-}
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
-{
-        return (pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
-            chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
-}
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrPhaseControl(void)
-{
-        return (pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
-            chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
-}
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmPhaseControl(void)
-{
-        return (pChipcHw->
-                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
-            chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
-}
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a DDR phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->DDRPhaseCtrl2 &=
-            ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK <<
-              chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT);
-        pChipcHw->DDRPhaseCtrl2 |=
-            (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) <<
-            chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a VPM phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->VPMPhaseCtrl2 &=
-            ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK <<
-              chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT);
-        pChipcHw->VPMPhaseCtrl2 |=
-            (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) <<
-            chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Clear DDR phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        /* Clear timeout interrupt service bit */
-        pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED;
-        pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   Clear VPM phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        /* Clear timeout interrupt service bit */
-        pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED;
-        pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
-        /* Enable timeout interrupt */
-        pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
-        /* Enable timeout interrupt */
-        pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-#endif /* CHIPC_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
deleted file mode 100644
index b162448f613c..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
+++ /dev/null
@@ -1,530 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    chipcHw_reg.h
-*
-*  @brief   Definitions for low level chip control registers
-*
-*/
-/****************************************************************************/
-#ifndef CHIPCHW_REG_H
-#define CHIPCHW_REG_H
-#include <mach/csp/mm_io.h>
-#include <csp/reg.h>
-#include <mach/csp/ddrcReg.h>
-#define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
-typedef struct {
-        uint32_t ChipId;        /* Chip ID */
-        uint32_t DDRClock;      /* PLL1 Channel 1 for DDR clock */
-        uint32_t ARMClock;      /* PLL1 Channel 2 for ARM clock */
-        uint32_t ESWClock;      /* PLL1 Channel 3 for ESW system clock */
-        uint32_t VPMClock;      /* PLL1 Channel 4 for VPM clock */
-        uint32_t ESW125Clock;   /* PLL1 Channel 5 for ESW 125MHz clock */
-        uint32_t UARTClock;     /* PLL1 Channel 6 for UART clock */
-        uint32_t SDIO0Clock;    /* PLL1 Channel 7 for SDIO 0 clock */
-        uint32_t SDIO1Clock;    /* PLL1 Channel 8 for SDIO 1 clock */
-        uint32_t SPIClock;      /* PLL1 Channel 9 for SPI master Clock  */
-        uint32_t ETMClock;      /* PLL1 Channel 10 for ARM ETM Clock  */
-        uint32_t ACLKClock;     /* ACLK Clock (Divider) */
-        uint32_t OTPClock;      /* OTP Clock  (Divider) */
-        uint32_t I2CClock;      /* I2C Clock (CK_13m) (Divider) */
-        uint32_t I2S0Clock;     /* I2S0 Clock (Divider) */
-        uint32_t RTBUSClock;    /* RTBUS (DDR PHY Config.) Clock (Divider) */
-        uint32_t pad1;
-        uint32_t APM100Clock;   /* APM 100MHz CLK Clock (Divider) */
-        uint32_t TSCClock;      /* TSC Clock (Divider) */
-        uint32_t LEDClock;      /* LED Clock (Divider) */
-        uint32_t USBClock;      /* PLL2 Channel 1 for USB clock */
-        uint32_t LCDClock;      /* PLL2 Channel 2 for LCD clock */
-        uint32_t APMClock;      /* PLL2 Channel 3 for APM 200 MHz clock */
-        uint32_t BusIntfClock;  /* Bus interface clock */
-        uint32_t PLLStatus;     /* PLL status register (PLL1) */
-        uint32_t PLLConfig;     /* PLL configuration register  (PLL1) */
-        uint32_t PLLPreDivider; /* PLL pre-divider control register (PLL1) */
-        uint32_t PLLDivider;    /* PLL divider control register (PLL1) */
-        uint32_t PLLControl1;   /* PLL analog control register #1 (PLL1) */
-        uint32_t PLLControl2;   /* PLL analog control register #2 (PLL1) */
-        uint32_t I2S1Clock;     /* I2S1 Clock  */
-        uint32_t AudioEnable;   /* Enable/ disable audio channel */
-        uint32_t SoftReset1;    /* Reset blocks */
-        uint32_t SoftReset2;    /* Reset blocks */
-        uint32_t Spare1;        /* Phase align interrupts */
-        uint32_t Sticky;        /* Sticky bits */
-        uint32_t MiscCtrl;      /* Misc. control */
-        uint32_t pad3[3];
-        uint32_t PLLStatus2;    /* PLL status register (PLL2) */
-        uint32_t PLLConfig2;    /* PLL configuration register  (PLL2) */
-        uint32_t PLLPreDivider2;        /* PLL pre-divider control register (PLL2) */
-        uint32_t PLLDivider2;   /* PLL divider control register (PLL2) */
-        uint32_t PLLControl12;  /* PLL analog control register #1 (PLL2) */
-        uint32_t PLLControl22;  /* PLL analog control register #2 (PLL2) */
-        uint32_t DDRPhaseCtrl1; /* DDR Clock Phase Alignment control1 */
-        uint32_t VPMPhaseCtrl1; /* VPM Clock Phase Alignment control1 */
-        uint32_t PhaseAlignStatus;      /* DDR/VPM Clock Phase Alignment Status */
-        uint32_t PhaseCtrlStatus;       /* DDR/VPM Clock HW DDR/VPM ph_ctrl and load_ch Status */
-        uint32_t DDRPhaseCtrl2; /* DDR Clock Phase Alignment control2 */
-        uint32_t VPMPhaseCtrl2; /* VPM Clock Phase Alignment control2 */
-        uint32_t pad4[9];
-        uint32_t SoftOTP1;      /* Software OTP control */
-        uint32_t SoftOTP2;      /* Software OTP control */
-        uint32_t SoftStraps;    /* Software strap */
-        uint32_t PinStraps;     /* Pin Straps */
-        uint32_t DiffOscCtrl;   /* Diff oscillator control */
-        uint32_t DiagsCtrl;     /* Diagnostic control */
-        uint32_t DiagsOutputCtrl;       /* Diagnostic output enable */
-        uint32_t DiagsReadBackCtrl;     /* Diagnostic read back control */
-        uint32_t LcdPifMode;    /* LCD/PIF Pin Sharing MUX Mode */
-        uint32_t GpioMux_0_7;   /* Pin Sharing MUX0 Control */
-        uint32_t GpioMux_8_15;  /* Pin Sharing MUX1 Control */
-        uint32_t GpioMux_16_23; /* Pin Sharing MUX2 Control */
-        uint32_t GpioMux_24_31; /* Pin Sharing MUX3 Control */
-        uint32_t GpioMux_32_39; /* Pin Sharing MUX4 Control */
-        uint32_t GpioMux_40_47; /* Pin Sharing MUX5 Control */
-        uint32_t GpioMux_48_55; /* Pin Sharing MUX6 Control */
-        uint32_t GpioMux_56_63; /* Pin Sharing MUX7 Control */
-        uint32_t GpioSR_0_7;    /* Slew rate for GPIO 0 - 7 */
-        uint32_t GpioSR_8_15;   /* Slew rate for GPIO 8 - 15 */
-        uint32_t GpioSR_16_23;  /* Slew rate for GPIO 16 - 23 */
-        uint32_t GpioSR_24_31;  /* Slew rate for GPIO 24 - 31 */
-        uint32_t GpioSR_32_39;  /* Slew rate for GPIO 32 - 39 */
-        uint32_t GpioSR_40_47;  /* Slew rate for GPIO 40 - 47 */
-        uint32_t GpioSR_48_55;  /* Slew rate for GPIO 48 - 55 */
-        uint32_t GpioSR_56_63;  /* Slew rate for GPIO 56 - 63 */
-        uint32_t MiscSR_0_7;    /* Slew rate for MISC 0 - 7 */
-        uint32_t MiscSR_8_15;   /* Slew rate for MISC 8 - 15 */
-        uint32_t GpioPull_0_15; /* Pull up registers for GPIO 0 - 15 */
-        uint32_t GpioPull_16_31;        /* Pull up registers for GPIO 16 - 31 */
-        uint32_t GpioPull_32_47;        /* Pull up registers for GPIO 32 - 47 */
-        uint32_t GpioPull_48_63;        /* Pull up registers for GPIO 48 - 63 */
-        uint32_t MiscPull_0_15; /* Pull up registers for MISC 0 - 15 */
-        uint32_t GpioInput_0_31;        /* Input type for GPIO 0 - 31 */
-        uint32_t GpioInput_32_63;       /* Input type for GPIO 32 - 63 */
-        uint32_t MiscInput_0_15;        /* Input type for MISC 0 - 16 */
-} chipcHw_REG_t;
-#define pChipcHw  ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
-#define pChipcPhysical  ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
-#define chipcHw_REG_CHIPID_BASE_MASK                    0xFFFFF000
-#define chipcHw_REG_CHIPID_BASE_SHIFT                   12
-#define chipcHw_REG_CHIPID_REV_MASK                     0x00000FFF
-#define chipcHw_REG_REV_A0                              0xA00
-#define chipcHw_REG_REV_B0                              0x0B0
-#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE           0x80000000      /* Allow controlling PLL registers */
-#define chipcHw_REG_PLL_STATUS_LOCKED                   0x00000001      /* PLL is settled */
-#define chipcHw_REG_PLL_CONFIG_D_RESET                  0x00000008      /* Digital reset */
-#define chipcHw_REG_PLL_CONFIG_A_RESET                  0x00000004      /* Analog reset */
-#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE            0x00000020      /* Bypass enable */
-#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE            0x00000010      /* Output enable */
-#define chipcHw_REG_PLL_CONFIG_POWER_DOWN               0x00000001      /* Power down */
-#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ           1600000000      /* 1.6GHz VCO split frequency */
-#define chipcHw_REG_PLL_CONFIG_VCO_800_1600             0x00000000      /* VCO range 800-1600 MHz */
-#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200            0x00000080      /* VCO range 1601-3200 MHz */
-#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE              0x00010000      /* PLL test output enable */
-#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK         0x003E0000      /* Mask to set test values */
-#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT        17
-#define chipcHw_REG_PLL_CLOCK_PHASE_COMP                0x00800000      /* Phase comparator output */
-#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK         0x00300000      /* Clock to bus ratio mask */
-#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT        20      /* Number of bits to be shifted */
-#define chipcHw_REG_PLL_CLOCK_POWER_DOWN                0x00080000      /* PLL channel power down */
-#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO               0x00040000      /* Use GPIO as source */
-#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT             0x00020000      /* Select bypass clock */
-#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE             0x00010000      /* Clock gated ON */
-#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE       0x00008000      /* Clock phase update enable */
-#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT       8       /* Number of bits to be shifted */
-#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK        0x00003F00      /* Phase control mask */
-#define chipcHw_REG_PLL_CLOCK_MDIV_MASK                 0x000000FF      /* Clock post divider mask
-                                                                           00000000 = divide-by-256
-                                                                           00000001 = divide-by-1
-                                                                           00000010 = divide-by-2
-                                                                           00000011 = divide-by-3
-                                                                           00000100 = divide-by-4
-                                                                           00000101 = divide-by-5
-                                                                           00000110 = divide-by-6
-                                                                           .
-                                                                           .
-                                                                           11111011 = divide-by-251
-                                                                           11111100 = divide-by-252
-                                                                           11111101 = divide-by-253
-                                                                           11111110 = divide-by-254
-                                                                         */
-#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER              0x00040000      /* NON-PLL clock source select */
-#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT             0x00020000      /* NON-PLL clock bypass enable */
-#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE             0x00010000      /* NON-PLL clock output enable */
-#define chipcHw_REG_DIV_CLOCK_DIV_MASK                  0x000000FF      /* NON-PLL clock post-divide mask */
-#define chipcHw_REG_DIV_CLOCK_DIV_256                   0x00000000      /* NON-PLL clock post-divide by 256 */
-#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT             0
-#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT             4
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT           8
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK            0x0001FF00
-#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN           0x02000000
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK       0x00700000      /* Divider mask */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER    0x00000000      /* Integer-N Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT  0x00100000      /* MASH Sigma-Delta Modulator Unit Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT   0x00200000      /* MFB Sigma-Delta Modulator Unit Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8   0x00300000      /* MASH Sigma-Delta Modulator 1/8 Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8    0x00400000      /* MFB Sigma-Delta Modulator 1/8 Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco)          ((vco) / chipcHw_XTAL_FREQ_Hz)
-#define chipcHw_REG_PLL_PREDIVIDER_P1                   1
-#define chipcHw_REG_PLL_PREDIVIDER_P2                   1
-#define chipcHw_REG_PLL_DIVIDER_M1DIV                   0x03000000
-#define chipcHw_REG_PLL_DIVIDER_FRAC                    0x00FFFFFF      /* Fractional divider */
-#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS               (0x00FFFFFF)    /* To attain spread with max frequency */
-#define chipcHw_REG_PLL_DIVIDER_NDIV_f                  0       /* ndiv_frac = chipcHw_REG_PLL_DIVIDER_NDIV_f /
-                                                                   chipcHw_REG_PLL_DIVIDER_FRAC
-                                                                   = 0, when SS is disable
-                                                                 */
-#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz)           ((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz)))
-#define chipcHw_REG_ACLKClock_CLK_DIV_MASK              0x3
-/* System booting strap options */
-#define chipcHw_STRAPS_SOFT_OVERRIDE                    0x00000001      /* Software Strap Override */
-#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8         0x00000000      /* 8 bit NAND FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16         0x00000002      /* 16 bit NOR FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH         0x00000004      /* Serial FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16        0x00000006      /* 16 bit NAND FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_UART                 0x00000008      /* UART Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_MASK                 0x0000000E      /* Mask */
-/* System boot option */
-#define chipcHw_STRAPS_BOOT_OPTION_BROM                 0x00000000      /* Boot from Boot ROM */
-#define chipcHw_STRAPS_BOOT_OPTION_ARAM                 0x00000020      /* Boot from ARAM */
-#define chipcHw_STRAPS_BOOT_OPTION_NOR                  0x00000030      /* Boot from NOR flash */
-/* NAND Flash page size strap options */
-#define chipcHw_STRAPS_NAND_PAGESIZE_512                0x00000000      /* NAND FLASH page size of 512 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_2048               0x00000040      /* NAND FLASH page size of 2048 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_4096               0x00000080      /* NAND FLASH page size of 4096 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_EXT                0x000000C0      /* NAND FLASH page of extened size */
-#define chipcHw_STRAPS_NAND_PAGESIZE_MASK               0x000000C0      /* Mask */
-#define chipcHw_STRAPS_NAND_EXTRA_CYCLE                 0x00000400      /* NAND FLASH address cycle configuration */
-#define chipcHw_STRAPS_REBOOT_TO_UART                   0x00000800      /* Reboot to UART on error */
-/* Secure boot mode strap options */
-#define chipcHw_STRAPS_BOOT_MODE_NORMAL                 0x00000000      /* Normal Boot */
-#define chipcHw_STRAPS_BOOT_MODE_DBG_SW                 0x00000100      /* Software debugging Boot */
-#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT               0x00000200      /* Boot rom debugging Boot */
-#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET           0x00000300      /* Normal Boot (Quiet BootRom) */
-#define chipcHw_STRAPS_BOOT_MODE_MASK                   0x00000300      /* Mask */
-/* Slave Mode straps */
-#define chipcHw_STRAPS_I2CS                             0x02000000      /* I2C Slave  */
-#define chipcHw_STRAPS_SPIS                             0x01000000      /* SPI Slave  */
-/* Strap pin options */
-#define chipcHw_REG_SW_STRAPS                           ((pChipcHw->PinStraps & 0x0000FC00) >> 10)
-/* PIF/LCD pin sharing defines */
-#define chipcHw_REG_LCD_PIN_ENABLE                      0x00000001      /* LCD Controller is used and the pins have LCD functions */
-#define chipcHw_REG_PIF_PIN_ENABLE                      0x00000002      /* LCD pins are used to perform PIF functions  */
-#define chipcHw_GPIO_COUNT                              61      /* Number of GPIO pin accessible thorugh CHIPC */
-/* NOTE: Any changes to these constants will require a corresponding change to chipcHw_str.c */
-#define chipcHw_REG_GPIO_MUX_KEYPAD                     0x00000001      /* GPIO mux for Keypad */
-#define chipcHw_REG_GPIO_MUX_I2CH                       0x00000002      /* GPIO mux for I2CH */
-#define chipcHw_REG_GPIO_MUX_SPI                        0x00000003      /* GPIO mux for SPI */
-#define chipcHw_REG_GPIO_MUX_UART                       0x00000004      /* GPIO mux for UART */
-#define chipcHw_REG_GPIO_MUX_LEDMTXP                    0x00000005      /* GPIO mux for LEDMTXP */
-#define chipcHw_REG_GPIO_MUX_LEDMTXS                    0x00000006      /* GPIO mux for LEDMTXS */
-#define chipcHw_REG_GPIO_MUX_SDIO0                      0x00000007      /* GPIO mux for SDIO0 */
-#define chipcHw_REG_GPIO_MUX_SDIO1                      0x00000008      /* GPIO mux for SDIO1 */
-#define chipcHw_REG_GPIO_MUX_PCM                        0x00000009      /* GPIO mux for PCM */
-#define chipcHw_REG_GPIO_MUX_I2S                        0x0000000A      /* GPIO mux for I2S */
-#define chipcHw_REG_GPIO_MUX_ETM                        0x0000000B      /* GPIO mux for ETM */
-#define chipcHw_REG_GPIO_MUX_DEBUG                      0x0000000C      /* GPIO mux for DEBUG */
-#define chipcHw_REG_GPIO_MUX_MISC                       0x0000000D      /* GPIO mux for MISC */
-#define chipcHw_REG_GPIO_MUX_GPIO                       0x00000000      /* GPIO mux for GPIO */
-#define chipcHw_REG_GPIO_MUX(pin)                       (&pChipcHw->GpioMux_0_7 + ((pin) >> 3))
-#define chipcHw_REG_GPIO_MUX_POSITION(pin)              (((pin) & 0x00000007) << 2)
-#define chipcHw_REG_GPIO_MUX_MASK                       0x0000000F      /* Mask */
-#define chipcHw_REG_SLEW_RATE_HIGH                      0x00000000      /* High speed slew rate */
-#define chipcHw_REG_SLEW_RATE_NORMAL                    0x00000008      /* Normal slew rate */
-                                                        /* Pins beyond 42 are defined by skipping 8 bits within the register */
-#define chipcHw_REG_SLEW_RATE(pin)                      (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
-#define chipcHw_REG_SLEW_RATE_POSITION(pin)             (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
-#define chipcHw_REG_SLEW_RATE_MASK                      0x00000008      /* Mask */
-#define chipcHw_REG_CURRENT_STRENGTH_2mA                0x00000001      /* Current driving strength 2 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_4mA                0x00000002      /* Current driving strength 4 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_6mA                0x00000004      /* Current driving strength 6 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_8mA                0x00000005      /* Current driving strength 8 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_10mA               0x00000006      /* Current driving strength 10 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_12mA               0x00000007      /* Current driving strength 12 milli ampere */
-#define chipcHw_REG_CURRENT_MASK                        0x00000007      /* Mask */
-                                                        /* Pins beyond 42 are defined by skipping 8 bits */
-#define chipcHw_REG_CURRENT(pin)                        (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
-#define chipcHw_REG_CURRENT_POSITION(pin)               (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
-#define chipcHw_REG_PULL_NONE                           0x00000000      /* No pull up register */
-#define chipcHw_REG_PULL_UP                             0x00000001      /* Pull up register enable */
-#define chipcHw_REG_PULL_DOWN                           0x00000002      /* Pull down register enable */
-#define chipcHw_REG_PULLUP_MASK                         0x00000003      /* Mask */
-                                                        /* Pins beyond 42 are defined by skipping 4 bits */
-#define chipcHw_REG_PULLUP(pin)                         (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChipcHw->GpioPull_0_15 + ((pin) >> 4)))
-#define chipcHw_REG_PULLUP_POSITION(pin)                (((pin) > 42) ? ((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1))
-#define chipcHw_REG_INPUTTYPE_CMOS                      0x00000000      /* Normal CMOS logic */
-#define chipcHw_REG_INPUTTYPE_ST                        0x00000001      /* High speed Schmitt Trigger */
-#define chipcHw_REG_INPUTTYPE_MASK                      0x00000001      /* Mask */
-                                                        /* Pins beyond 42 are defined by skipping 2 bits */
-#define chipcHw_REG_INPUTTYPE(pin)                      (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&pChipcHw->GpioInput_0_31 + ((pin) >> 5)))
-#define chipcHw_REG_INPUTTYPE_POSITION(pin)             (((pin) > 42) ? ((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F)))
-/* Device connected to the bus clock */
-#define chipcHw_REG_BUS_CLOCK_ARM                       0x00000001      /* Bus interface clock for ARM */
-#define chipcHw_REG_BUS_CLOCK_VDEC                      0x00000002      /* Bus interface clock for VDEC */
-#define chipcHw_REG_BUS_CLOCK_ARAM                      0x00000004      /* Bus interface clock for ARAM */
-#define chipcHw_REG_BUS_CLOCK_HPM                       0x00000008      /* Bus interface clock for HPM */
-#define chipcHw_REG_BUS_CLOCK_DDRC                      0x00000010      /* Bus interface clock for DDRC */
-#define chipcHw_REG_BUS_CLOCK_DMAC0                     0x00000020      /* Bus interface clock for DMAC0 */
-#define chipcHw_REG_BUS_CLOCK_DMAC1                     0x00000040      /* Bus interface clock for DMAC1 */
-#define chipcHw_REG_BUS_CLOCK_NVI                       0x00000080      /* Bus interface clock for NVI */
-#define chipcHw_REG_BUS_CLOCK_ESW                       0x00000100      /* Bus interface clock for ESW */
-#define chipcHw_REG_BUS_CLOCK_GE                        0x00000200      /* Bus interface clock for GE */
-#define chipcHw_REG_BUS_CLOCK_I2CH                      0x00000400      /* Bus interface clock for I2CH */
-#define chipcHw_REG_BUS_CLOCK_I2S0                      0x00000800      /* Bus interface clock for I2S0 */
-#define chipcHw_REG_BUS_CLOCK_I2S1                      0x00001000      /* Bus interface clock for I2S1 */
-#define chipcHw_REG_BUS_CLOCK_VRAM                      0x00002000      /* Bus interface clock for VRAM */
-#define chipcHw_REG_BUS_CLOCK_CLCD                      0x00004000      /* Bus interface clock for CLCD */
-#define chipcHw_REG_BUS_CLOCK_LDK                       0x00008000      /* Bus interface clock for LDK */
-#define chipcHw_REG_BUS_CLOCK_LED                       0x00010000      /* Bus interface clock for LED */
-#define chipcHw_REG_BUS_CLOCK_OTP                       0x00020000      /* Bus interface clock for OTP */
-#define chipcHw_REG_BUS_CLOCK_PIF                       0x00040000      /* Bus interface clock for PIF */
-#define chipcHw_REG_BUS_CLOCK_SPU                       0x00080000      /* Bus interface clock for SPU */
-#define chipcHw_REG_BUS_CLOCK_SDIO0                     0x00100000      /* Bus interface clock for SDIO0 */
-#define chipcHw_REG_BUS_CLOCK_SDIO1                     0x00200000      /* Bus interface clock for SDIO1 */
-#define chipcHw_REG_BUS_CLOCK_SPIH                      0x00400000      /* Bus interface clock for SPIH */
-#define chipcHw_REG_BUS_CLOCK_SPIS                      0x00800000      /* Bus interface clock for SPIS */
-#define chipcHw_REG_BUS_CLOCK_UART0                     0x01000000      /* Bus interface clock for UART0 */
-#define chipcHw_REG_BUS_CLOCK_UART1                     0x02000000      /* Bus interface clock for UART1 */
-#define chipcHw_REG_BUS_CLOCK_BBL                       0x04000000      /* Bus interface clock for BBL */
-#define chipcHw_REG_BUS_CLOCK_I2CS                      0x08000000      /* Bus interface clock for I2CS */
-#define chipcHw_REG_BUS_CLOCK_USBH                      0x10000000      /* Bus interface clock for USB Host */
-#define chipcHw_REG_BUS_CLOCK_USBD                      0x20000000      /* Bus interface clock for USB Device */
-#define chipcHw_REG_BUS_CLOCK_BROM                      0x40000000      /* Bus interface clock for Boot ROM */
-#define chipcHw_REG_BUS_CLOCK_TSC                       0x80000000      /* Bus interface clock for Touch screen */
-/* Software resets defines */
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD          0x0000000080000000ULL   /* Reset Global VPM and hold */
-#define chipcHw_REG_SOFT_RESET_VPM_HOLD                 0x0000000040000000ULL   /* Reset VPM and hold */
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL               0x0000000020000000ULL   /* Reset Global VPM */
-#define chipcHw_REG_SOFT_RESET_VPM                      0x0000000010000000ULL   /* Reset VPM */
-#define chipcHw_REG_SOFT_RESET_KEYPAD                   0x0000000008000000ULL   /* Reset Key pad */
-#define chipcHw_REG_SOFT_RESET_LED                      0x0000000004000000ULL   /* Reset LED */
-#define chipcHw_REG_SOFT_RESET_SPU                      0x0000000002000000ULL   /* Reset SPU */
-#define chipcHw_REG_SOFT_RESET_RNG                      0x0000000001000000ULL   /* Reset RNG */
-#define chipcHw_REG_SOFT_RESET_PKA                      0x0000000000800000ULL   /* Reset PKA */
-#define chipcHw_REG_SOFT_RESET_LCD                      0x0000000000400000ULL   /* Reset LCD */
-#define chipcHw_REG_SOFT_RESET_PIF                      0x0000000000200000ULL   /* Reset PIF */
-#define chipcHw_REG_SOFT_RESET_I2CS                     0x0000000000100000ULL   /* Reset I2C Slave */
-#define chipcHw_REG_SOFT_RESET_I2CH                     0x0000000000080000ULL   /* Reset I2C Host */
-#define chipcHw_REG_SOFT_RESET_SDIO1                    0x0000000000040000ULL   /* Reset SDIO 1 */
-#define chipcHw_REG_SOFT_RESET_SDIO0                    0x0000000000020000ULL   /* Reset SDIO 0 */
-#define chipcHw_REG_SOFT_RESET_BBL                      0x0000000000010000ULL   /* Reset BBL */
-#define chipcHw_REG_SOFT_RESET_I2S1                     0x0000000000008000ULL   /* Reset I2S1 */
-#define chipcHw_REG_SOFT_RESET_I2S0                     0x0000000000004000ULL   /* Reset I2S0 */
-#define chipcHw_REG_SOFT_RESET_SPIS                     0x0000000000002000ULL   /* Reset SPI Slave */
-#define chipcHw_REG_SOFT_RESET_SPIH                     0x0000000000001000ULL   /* Reset SPI Host */
-#define chipcHw_REG_SOFT_RESET_GPIO1                    0x0000000000000800ULL   /* Reset GPIO block 1 */
-#define chipcHw_REG_SOFT_RESET_GPIO0                    0x0000000000000400ULL   /* Reset GPIO block 0 */
-#define chipcHw_REG_SOFT_RESET_UART1                    0x0000000000000200ULL   /* Reset UART 1 */
-#define chipcHw_REG_SOFT_RESET_UART0                    0x0000000000000100ULL   /* Reset UART 0 */
-#define chipcHw_REG_SOFT_RESET_NVI                      0x0000000000000080ULL   /* Reset NVI */
-#define chipcHw_REG_SOFT_RESET_WDOG                     0x0000000000000040ULL   /* Reset Watch dog */
-#define chipcHw_REG_SOFT_RESET_TMR                      0x0000000000000020ULL   /* Reset Timer */
-#define chipcHw_REG_SOFT_RESET_ETM                      0x0000000000000010ULL   /* Reset ETM */
-#define chipcHw_REG_SOFT_RESET_ARM_HOLD                 0x0000000000000008ULL   /* Reset ARM and HOLD */
-#define chipcHw_REG_SOFT_RESET_ARM                      0x0000000000000004ULL   /* Reset ARM */
-#define chipcHw_REG_SOFT_RESET_CHIP_WARM                0x0000000000000002ULL   /* Chip warm reset */
-#define chipcHw_REG_SOFT_RESET_CHIP_SOFT                0x0000000000000001ULL   /* Chip soft reset */
-#define chipcHw_REG_SOFT_RESET_VDEC                     0x0000100000000000ULL   /* Video decoder */
-#define chipcHw_REG_SOFT_RESET_GE                       0x0000080000000000ULL   /* Graphics engine */
-#define chipcHw_REG_SOFT_RESET_OTP                      0x0000040000000000ULL   /* Reset OTP */
-#define chipcHw_REG_SOFT_RESET_USB2                     0x0000020000000000ULL   /* Reset USB2 */
-#define chipcHw_REG_SOFT_RESET_USB1                     0x0000010000000000ULL   /* Reset USB 1 */
-#define chipcHw_REG_SOFT_RESET_USB                      0x0000008000000000ULL   /* Reset USB 1 and USB2 soft reset */
-#define chipcHw_REG_SOFT_RESET_ESW                      0x0000004000000000ULL   /* Reset Ethernet switch */
-#define chipcHw_REG_SOFT_RESET_ESWCLK                   0x0000002000000000ULL   /* Reset Ethernet switch clock */
-#define chipcHw_REG_SOFT_RESET_DDRPHY                   0x0000001000000000ULL   /* Reset DDR Physical */
-#define chipcHw_REG_SOFT_RESET_DDR                      0x0000000800000000ULL   /* Reset DDR Controller */
-#define chipcHw_REG_SOFT_RESET_TSC                      0x0000000400000000ULL   /* Reset Touch screen */
-#define chipcHw_REG_SOFT_RESET_PCM                      0x0000000200000000ULL   /* Reset PCM device */
-#define chipcHw_REG_SOFT_RESET_APM                      0x0000200100000000ULL   /* Reset APM device */
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD        0x8000000000000000ULL   /* Unhold Global VPM */
-#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD               0x4000000000000000ULL   /* Unhold VPM */
-#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD               0x2000000000000000ULL   /* Unhold ARM reset  */
-#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK              0xF000000000000000ULL   /* Mask to handle unhold request */
-/* Audio channel control defines */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL            0x00000001      /* Enable all audio channel */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A              0x00000002      /* Enable channel A */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B              0x00000004      /* Enable channel B */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C              0x00000008      /* Enable channel C */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK      0x00000010      /* Enable NTP clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK     0x00000020      /* Enable PCM0 clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK     0x00000040      /* Enable PCM1 clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK      0x00000080      /* Enable APM clock */
-/* Misc. chip control defines */
-#define chipcHw_REG_MISC_CTRL_GE_SEL                    0x00040000      /* Select GE2/GE3 */
-#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP         0x00000000      /* Use on chip clock for I2S1 */
-#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO           0x00020000      /* Use external clock via GPIO pin 26 for I2S1 */
-#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP         0x00000000      /* Use on chip clock for I2S0 */
-#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO           0x00010000      /* Use external clock via GPIO pin 45 for I2S0 */
-#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE          0x00008000      /* Disable ARM CP15 bit */
-#define chipcHw_REG_MISC_CTRL_RTC_DISABLE               0x00000008      /* Disable RTC registers */
-#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE             0x00000004      /* Disable Battery Backed RAM */
-#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST             0x00000002      /* Set USB as host */
-#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE           0xFFFFFFFD      /* Set USB as device */
-#define chipcHw_REG_MISC_CTRL_USB_POWERON               0xFFFFFFFE      /* Power up USB */
-#define chipcHw_REG_MISC_CTRL_USB_POWEROFF              0x00000001      /* Power down USB */
-/* OTP configuration defines */
-#define chipcHw_REG_OTP_SECURITY_OFF                    0x0000020000000000ULL   /* Security support is OFF */
-#define chipcHw_REG_OTP_SPU_SLOW                        0x0000010000000000ULL   /* Limited SPU throughput */
-#define chipcHw_REG_OTP_LCD_SPEED                       0x0000000600000000ULL   /* Set VPM speed one */
-#define chipcHw_REG_OTP_VPM_SPEED_1                     0x0000000100000000ULL   /* Set VPM speed one */
-#define chipcHw_REG_OTP_VPM_SPEED_0                     0x0000000080000000ULL   /* Set VPM speed zero */
-#define chipcHw_REG_OTP_AXI_SPEED                       0x0000000060000000ULL   /* Set maximum AXI bus speed */
-#define chipcHw_REG_OTP_APM_DISABLE                     0x000000001F000000ULL   /* Disable APM */
-#define chipcHw_REG_OTP_PIF_DISABLE                     0x0000000000200000ULL   /* Disable PIF */
-#define chipcHw_REG_OTP_VDEC_DISABLE                    0x0000000000100000ULL   /* Disable Video decoder */
-#define chipcHw_REG_OTP_BBL_DISABLE                     0x0000000000080000ULL   /* Disable RTC and BBRAM */
-#define chipcHw_REG_OTP_LED_DISABLE                     0x0000000000040000ULL   /* Disable LED */
-#define chipcHw_REG_OTP_GE_DISABLE                      0x0000000000020000ULL   /* Disable Graphics Engine */
-#define chipcHw_REG_OTP_LCD_DISABLE                     0x0000000000010000ULL   /* Disable LCD */
-#define chipcHw_REG_OTP_KEYPAD_DISABLE                  0x0000000000008000ULL   /* Disable keypad */
-#define chipcHw_REG_OTP_UART_DISABLE                    0x0000000000004000ULL   /* Disable UART */
-#define chipcHw_REG_OTP_SDIOH_DISABLE                   0x0000000000003000ULL   /* Disable SDIO host */
-#define chipcHw_REG_OTP_HSS_DISABLE                     0x0000000000000C00ULL   /* Disable HSS */
-#define chipcHw_REG_OTP_TSC_DISABLE                     0x0000000000000200ULL   /* Disable touch screen */
-#define chipcHw_REG_OTP_USB_DISABLE                     0x0000000000000180ULL   /* Disable USB */
-#define chipcHw_REG_OTP_SGMII_DISABLE                   0x0000000000000060ULL   /* Disable SGMII */
-#define chipcHw_REG_OTP_ETH_DISABLE                     0x0000000000000018ULL   /* Disable gigabit ethernet */
-#define chipcHw_REG_OTP_ETH_PHY_DISABLE                 0x0000000000000006ULL   /* Disable ethernet PHY */
-#define chipcHw_REG_OTP_VPM_DISABLE                     0x0000000000000001ULL   /* Disable VPM */
-/* Sticky bit defines */
-#define chipcHw_REG_STICKY_BOOT_DONE                    0x00000001      /* Boot done */
-#define chipcHw_REG_STICKY_SOFT_RESET                   0x00000002      /* ARM soft reset */
-#define chipcHw_REG_STICKY_GENERAL_1                    0x00000004      /* General purpose bit 1 */
-#define chipcHw_REG_STICKY_GENERAL_2                    0x00000008      /* General purpose bit 2 */
-#define chipcHw_REG_STICKY_GENERAL_3                    0x00000010      /* General purpose bit 3 */
-#define chipcHw_REG_STICKY_GENERAL_4                    0x00000020      /* General purpose bit 4 */
-#define chipcHw_REG_STICKY_GENERAL_5                    0x00000040      /* General purpose bit 5 */
-#define chipcHw_REG_STICKY_POR_BROM                     0x00000080      /* Special sticky bit for security - set in BROM to avoid other modes being entered */
-#define chipcHw_REG_STICKY_ARM_RESET                    0x00000100      /* ARM reset */
-#define chipcHw_REG_STICKY_CHIP_SOFT_RESET              0x00000200      /* Chip soft reset */
-#define chipcHw_REG_STICKY_CHIP_WARM_RESET              0x00000400      /* Chip warm reset */
-#define chipcHw_REG_STICKY_WDOG_RESET                   0x00000800      /* Watchdog reset */
-#define chipcHw_REG_STICKY_OTP_RESET                    0x00001000      /* OTP reset */
-                                                        /* HW phase alignment defines *//* Spare1 register definitions */
-#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE        0x80000000      /* Enable DDR phase align panic interrupt */
-#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE        0x40000000      /* Enable VPM phase align panic interrupt */
-#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE        0x00000002      /* Enable access to VPM using system BUS */
-#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE        0x00000001      /* Enable access to DDR using system BUS */
-                                                        /* DDRPhaseCtrl1 register definitions */
-#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE            0x80000000      /* Enable DDR SW phase alignment */
-#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE            0x40000000      /* Enable DDR HW phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK             0x0000007F      /* DDR lower threshold for phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT            23
-#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK             0x0000007F      /* DDR upper threshold for phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT            16
-#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF      /* BUS Cycle to wait to run next DDR phase alignment */
-#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
-                                                        /* VPMPhaseCtrl1 register definitions */
-#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE            0x80000000      /* Enable VPM SW phase alignment */
-#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE            0x40000000      /* Enable VPM HW phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK             0x0000007F      /* VPM lower threshold for phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT            23
-#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK             0x0000007F      /* VPM upper threshold for phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT            16
-#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF      /* BUS Cycle to wait to complete the VPM phase alignment */
-#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
-                                                        /* PhaseAlignStatus register definitions */
-#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS             0x80000000      /* DDR time out interrupt status */
-#define chipcHw_REG_DDR_PHASE_STATUS_MASK               0x0000007F      /* DDR phase status value */
-#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT              24
-#define chipcHw_REG_DDR_PHASE_ALIGNED                   0x00800000      /* DDR Phase aligned status */
-#define chipcHw_REG_DDR_LOAD                            0x00400000      /* Load DDR phase status */
-#define chipcHw_REG_DDR_PHASE_CTRL_MASK                 0x0000003F      /* DDR phase control value */
-#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT                16
-#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS             0x80000000      /* VPM time out interrupt status */
-#define chipcHw_REG_VPM_PHASE_STATUS_MASK               0x0000007F      /* VPM phase status value */
-#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT              8
-#define chipcHw_REG_VPM_PHASE_ALIGNED                   0x00000080      /* VPM Phase aligned status */
-#define chipcHw_REG_VPM_LOAD                            0x00000040      /* Load VPM phase status */
-#define chipcHw_REG_VPM_PHASE_CTRL_MASK                 0x0000003F      /* VPM phase control value */
-#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT                0
-                                                        /* DDRPhaseCtrl2 register definitions */
-#define chipcHw_REG_DDR_INTR_SERVICED                   0x02000000      /* Acknowledge that interrupt was serviced */
-#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE             0x01000000      /* Enable time out interrupt */
-#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F      /* Wait before toggling load_ch */
-#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT     20
-#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F      /* Total wait to settle ph_ctrl and load_ch */
-#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
-#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF      /* Time out value for DDR HW phase alignment */
-#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT       0
-                                                        /* VPMPhaseCtrl2 register definitions */
-#define chipcHw_REG_VPM_INTR_SELECT_MASK                0x00000003      /* Interrupt select */
-#define chipcHw_REG_VPM_INTR_SELECT_SHIFT               26
-#define chipcHw_REG_VPM_INTR_DISABLE                    0x00000000
-#define chipcHw_REG_VPM_INTR_FAST                       (0x1 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_MEDIUM                     (0x2 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_SLOW                       (0x3 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_SERVICED                   0x02000000      /* Acknowledge that interrupt was serviced */
-#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE             0x01000000      /* Enable time out interrupt */
-#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F      /* Wait before toggling load_ch */
-#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT     20
-#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F      /* Total wait cycle to settle ph_ctrl and load_ch */
-#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
-#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF      /* Time out value for VPM HW phase alignment */
-#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT       0
-#endif /* CHIPCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
deleted file mode 100644
index f1b68e26fa6d..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
+++ /dev/null
@@ -1,872 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    ddrcReg.h
-*
-*  @brief   Register definitions for BCMRING DDR2 Controller and PHY
-*
-*/
-/****************************************************************************/
-#ifndef DDRC_REG_H
-#define DDRC_REG_H
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
-#include <csp/stdint.h>
-#include <mach/csp/mm_io.h>
-/* ---- Public Constants and Types --------------------------------------- */
-/*********************************************************************/
-/* DDR2 Controller (ARM PL341) register definitions */
-/*********************************************************************/
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 DDR2 configuration registers, offset 0x000 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-        typedef struct {
-                uint32_t memcStatus;
-                uint32_t memcCmd;
-                uint32_t directCmd;
-                uint32_t memoryCfg;
-                uint32_t refreshPrd;
-                uint32_t casLatency;
-                uint32_t writeLatency;
-                uint32_t tMrd;
-                uint32_t tRas;
-                uint32_t tRc;
-                uint32_t tRcd;
-                uint32_t tRfc;
-                uint32_t tRp;
-                uint32_t tRrd;
-                uint32_t tWr;
-                uint32_t tWtr;
-                uint32_t tXp;
-                uint32_t tXsr;
-                uint32_t tEsr;
-                uint32_t memoryCfg2;
-                uint32_t memoryCfg3;
-                uint32_t tFaw;
-        } ddrcReg_CTLR_MEMC_REG_t;
-#define ddrcReg_CTLR_MEMC_REG_OFFSET                    0x0000
-#define ddrcReg_CTLR_MEMC_REGP                          ((volatile ddrcReg_CTLR_MEMC_REG_t *)  (MM_IO_BASE_DDRC + ddrcReg_CTLR_MEMC_REG_OFFSET))
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK             (0x3 << 12)
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_4                (0x0 << 12)
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_8                (0x3 << 12)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK          (0x3 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0             (0x0 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1             (0x1 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2             (0x2 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4             (0x3 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK             (0x3 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1                (0x0 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2                (0x1 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3                (0x2 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4                (0x3 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK              (0x7 << 4)
-#define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2              (0x5 << 4)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK             (0x3 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16               (0x0 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32               (0x1 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64               (0x2 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128              (0x3 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK             (0x3 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG           (0x0 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_READY            (0x1 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED           (0x2 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR           (0x3 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_MEMC_CMD_MASK                      (0x7 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_GO                        (0x0 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_SLEEP                     (0x1 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_WAKEUP                    (0x2 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_PAUSE                     (0x3 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_CONFIGURE                 (0x4 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE              (0x7 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT              20
-#define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK               (0x3 << ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL       (0x0 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH        (0x1 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG            (0x2 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP                (0x3 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT              16
-#define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK               (0x3 << ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT)
-#define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT              0
-#define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK               (0x1ffff << ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK           (0x3 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1              (0x0 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2              (0x1 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3              (0x2 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4              (0x3 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK           (0x7 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0            (0x0 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1            (0x1 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2            (0x2 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3            (0x3 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4            (0x4 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5            (0x5 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6            (0x6 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7           (0x7 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK          (0x7 << 15)
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4             (0x2 << 15)
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8             (0x3 << 15)     /* @note Not supported in PL341 */
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE          (0x1 << 13)
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT    7
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK     (0x3f << ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK       (0x7 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11         (0x0 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12         (0x1 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13         (0x2 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14         (0x3 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15         (0x4 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16         (0x5 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK       (0x7 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9          (0x1 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10         (0x2 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11         (0x3 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_REFRESH_PRD_SHIFT                  0
-#define ddrcReg_CTLR_REFRESH_PRD_MASK                   (0x7fff << ddrcReg_CTLR_REFRESH_PRD_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_CAS_LATENCY_SHIFT                  1
-#define ddrcReg_CTLR_CAS_LATENCY_MASK                   (0x7 << ddrcReg_CTLR_CAS_LATENCY_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_WRITE_LATENCY_SHIFT                0
-#define ddrcReg_CTLR_WRITE_LATENCY_MASK                 (0x7 << ddrcReg_CTLR_WRITE_LATENCY_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_T_MRD_SHIFT                        0
-#define ddrcReg_CTLR_T_MRD_MASK                         (0x7f << ddrcReg_CTLR_T_MRD_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_T_RAS_SHIFT                        0
-#define ddrcReg_CTLR_T_RAS_MASK                         (0x1f << ddrcReg_CTLR_T_RAS_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_T_RC_SHIFT                         0
-#define ddrcReg_CTLR_T_RC_MASK                          (0x1f << ddrcReg_CTLR_T_RC_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK          (0x7 << ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT)
-#define ddrcReg_CTLR_T_RCD_SHIFT                        0
-#define ddrcReg_CTLR_T_RCD_MASK                         (0x7 << ddrcReg_CTLR_T_RCD_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK          (0x7f << ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT)
-#define ddrcReg_CTLR_T_RFC_SHIFT                        0
-#define ddrcReg_CTLR_T_RFC_MASK                         (0x7f << ddrcReg_CTLR_T_RFC_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT          8
-#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK           (0x7 << ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT)
-#define ddrcReg_CTLR_T_RP_SHIFT                         0
-#define ddrcReg_CTLR_T_RP_MASK                          (0xf << ddrcReg_CTLR_T_RP_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_T_RRD_SHIFT                        0
-#define ddrcReg_CTLR_T_RRD_MASK                         (0xf << ddrcReg_CTLR_T_RRD_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_T_WR_SHIFT                         0
-#define ddrcReg_CTLR_T_WR_MASK                          (0x7 << ddrcReg_CTLR_T_WR_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_T_WTR_SHIFT                        0
-#define ddrcReg_CTLR_T_WTR_MASK                         (0x7 << ddrcReg_CTLR_T_WTR_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_T_XP_SHIFT                         0
-#define ddrcReg_CTLR_T_XP_MASK                          (0xff << ddrcReg_CTLR_T_XP_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_T_XSR_SHIFT                        0
-#define ddrcReg_CTLR_T_XSR_MASK                         (0xff << ddrcReg_CTLR_T_XSR_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_T_ESR_SHIFT                        0
-#define ddrcReg_CTLR_T_ESR_MASK                         (0xff << ddrcReg_CTLR_T_ESR_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK             (0x3 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS           (0 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS           (1 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS           (2 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK     (0x3 << 4)
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2        (0 << 4)
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3        (3 << 4)
-#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW     (0 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH    (1 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW     (0 << 2)
-#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH    (1 << 2)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK               (0x3 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC              (0 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M        (1 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M        (3 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT       0
-#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK        (0x7 << ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK          (0x1f << ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT)
-#define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT                 0
-#define ddrcReg_CTLR_T_FAW_PERIOD_MASK                  (0x1f << ddrcReg_CTLR_T_FAW_PERIOD_SHIFT)
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-#define ddrcReg_CTLR_QOS_CNT                            16
-#define ddrcReg_CTLR_QOS_MAX                            (ddrcReg_CTLR_QOS_CNT - 1)
-        typedef struct {
-                uint32_t cfg[ddrcReg_CTLR_QOS_CNT];
-        } ddrcReg_CTLR_QOS_REG_t;
-#define ddrcReg_CTLR_QOS_REG_OFFSET                     0x100
-#define ddrcReg_CTLR_QOS_REGP                           ((volatile ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET))
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT                  2
-#define ddrcReg_CTLR_QOS_CFG_MAX_MASK                   (0xff << ddrcReg_CTLR_QOS_CFG_MAX_SHIFT)
-#define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT                  1
-#define ddrcReg_CTLR_QOS_CFG_MIN_MASK                   (1 << ddrcReg_CTLR_QOS_CFG_MIN_SHIFT)
-#define ddrcReg_CTLR_QOS_CFG_ENABLE                     (1 << 0)
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 Memory chip configuration registers, offset 0x200 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-#define ddrcReg_CTLR_CHIP_CNT                           4
-#define ddrcReg_CTLR_CHIP_MAX                           (ddrcReg_CTLR_CHIP_CNT - 1)
-        typedef struct {
-                uint32_t cfg[ddrcReg_CTLR_CHIP_CNT];
-        } ddrcReg_CTLR_CHIP_REG_t;
-#define ddrcReg_CTLR_CHIP_REG_OFFSET                    0x200
-#define ddrcReg_CTLR_CHIP_REGP                          ((volatile ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET))
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK              (1 << 16)
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL      (0 << 16)
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL      (1 << 16)
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT      8
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK       (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT)
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT       0
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK        (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT)
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 User configuration registers, offset 0x300 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-#define ddrcReg_CTLR_USER_OUTPUT_CNT                    2
-        typedef struct {
-                uint32_t input;
-                uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT];
-                uint32_t feature;
-        } ddrcReg_CTLR_USER_REG_t;
-#define ddrcReg_CTLR_USER_REG_OFFSET                    0x300
-#define ddrcReg_CTLR_USER_REGP                          ((volatile ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET))
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT            0
-#define ddrcReg_CTLR_USER_INPUT_STATUS_MASK             (0xff << ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT              0
-#define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK               (0xff << ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT      1
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK       (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134      (0 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301      (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE        (1 << 2)
-#define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE    (1 << 0)
-/*********************************************************************/
-/* Broadcom DDR23 PHY register definitions */
-/*********************************************************************/
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* Broadcom DDR23 PHY Address and Control register definitions */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-        typedef struct {
-                uint32_t revision;
-                uint32_t pmCtl;
-                 REG32_RSVD(0x0008, 0x0010);
-                uint32_t pllStatus;
-                uint32_t pllCfg;
-                uint32_t pllPreDiv;
-                uint32_t pllDiv;
-                uint32_t pllCtl1;
-                uint32_t pllCtl2;
-                uint32_t ssCtl;
-                uint32_t ssCfg;
-                uint32_t vdlStatic;
-                uint32_t vdlDynamic;
-                uint32_t padIdle;
-                uint32_t pvtComp;
-                uint32_t padDrive;
-                uint32_t clkRgltrCtl;
-        } ddrcReg_PHY_ADDR_CTL_REG_t;
-#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET                 0x0400
-#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
-/* @todo These SS definitions are duplicates of ones below */
-#define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE                 0x00000001
-#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK     0xFFFF0000
-#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT    16
-#define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK      10      /* Higher the value, lower the SS modulation frequency */
-#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK     0x0000FFFF
-#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT    0
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT       8
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK        (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK        (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED          (1 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET     (1 << 31)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT     17
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK      (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE        (1 << 16)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG            (1 << 7)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN         (1 << 6)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE      (1 << 5)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE      (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET            (1 << 3)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET            (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN             (1 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB     (1 << 26)
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN         (1 << 25)
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT     20
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT      8
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK       (0x1ff << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT       4
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT           24
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK            (0xff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT         0
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK          (0xffffff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT       30
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK        (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT     27
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT     24
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT      22
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER          (0x1 << 21)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT          19
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT          17
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT          15
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT          13
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT          10
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK           (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT        5
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK         (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT     0
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK      (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT    4
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK     (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT    2
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK     (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE     (0x1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE     (0x1 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE           (0x1 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT  16
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK   (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT      0
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK       (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE           (1 << 20)
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE          (1 << 16)
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT      12
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT      8
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT      0
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK       (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE         (1 << 16)
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK      (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT     8
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK      (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT     0
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK      (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE            (1u << 31)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE     (1 << 8)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE  (1 << 6)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE   (1 << 5)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE   (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE  (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE   (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE   (1 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE           (1 << 30)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE           (1 << 29)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE       (1 << 28)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE    (1 << 27)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE     (1 << 26)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE   (1 << 25)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE     (1 << 24)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT          20
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK           (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT          16
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK           (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT     8
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT       4
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B            (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18       (1 << 3)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI      (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV         (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW             (1 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF     (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF      (1 << 0)
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* Broadcom DDR23 PHY Byte Lane register definitions */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-#define ddrcReg_PHY_BYTE_LANE_CNT                       2
-#define ddrcReg_PHY_BYTE_LANE_MAX                       (ddrcReg_CTLR_BYTE_LANE_CNT - 1)
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT               8
-        typedef struct {
-                uint32_t revision;
-                uint32_t vdlCalibrate;
-                uint32_t vdlStatus;
-                 REG32_RSVD(0x000c, 0x0010);
-                uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT];
-                uint32_t readCtl;
-                uint32_t readStatus;
-                uint32_t readClear;
-                uint32_t padIdleCtl;
-                uint32_t padDriveCtl;
-                uint32_t padClkCtl;
-                uint32_t writeCtl;
-                uint32_t clkRegCtl;
-        } ddrcReg_PHY_BYTE_LANE_REG_t;
-/* There are 2 instances of the byte Lane registers, one for each byte lane. */
-#define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET              0x0500
-#define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET              0x0600
-#define ddrcReg_PHY_BYTE_LANE_1_REGP                    ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET))
-#define ddrcReg_PHY_BYTE_LANE_2_REGP                    ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET))
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT      8
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK       (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT)
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT      0
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK       (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE      (1 << 4)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE      (0 << 4)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST            (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS          (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE            (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST            (1 << 0)
-/* ----------------------------------------------------- */
-/* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step value, [3:2] fine fall */
-/* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 in the VDL status */
-/* register. The fine rise and fall are no longer used, so add some definitions for just */
-/* the step setting to simplify things. */
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT     8
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK      (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT)
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT    4
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK     (0x3ff << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT)
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK           (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE           (1 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE            (1 << 16)
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT        12
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK         (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT)
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT        8
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK         (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT)
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT        0
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK         (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT)
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P     0
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N     1
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN        2
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM   3
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P    4
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N    5
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN       6
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM  7
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT      8
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK       (0x3 << ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE    (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST    (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE    (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST    (1 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT   0
-#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK    (0xf << ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS         (1 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE                   (1u << 31)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE         (1 << 19)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE          (1 << 18)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE           (1 << 17)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE           (1 << 16)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE         (1 << 15)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE          (1 << 14)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE           (1 << 13)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE           (1 << 12)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE   (1 << 11)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE    (1 << 10)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE     (1 << 9)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE     (1 << 8)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE        (1 << 7)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE         (1 << 6)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE          (1 << 5)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE          (1 << 4)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE        (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE         (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE          (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE          (1 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB      (1 << 5)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B                   (1 << 4)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18              (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI             (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV                (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW                    (1 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE                   (1 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3               (1 << 0)
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF                  (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF                   (1 << 0)
-/*********************************************************************/
-/* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */
-/*********************************************************************/
-        typedef struct {
-                uint32_t cfg;
-                uint32_t actMonCnt;
-                uint32_t ctl;
-                uint32_t lbistCtl;
-                uint32_t lbistSeed;
-                uint32_t lbistStatus;
-                uint32_t tieOff;
-                uint32_t actMonClear;
-                uint32_t status;
-                uint32_t user;
-        } ddrcReg_CTLR_PHY_GLUE_REG_t;
-#define ddrcReg_CTLR_PHY_GLUE_OFFSET                            0x0700
-#define ddrcReg_CTLR_PHY_GLUE_REGP                              ((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_PHY_GLUE_OFFSET))
-/* ----------------------------------------------------- */
-/* DDR2 / AXI block phase alignment interrupt control */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT                     18
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK                      (0x3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF                       (0 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT                  (1 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM                 (2 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE                  (3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT              17
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK               (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL       (0 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS               (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT            16
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK             (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP             (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW          (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED   ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT             15
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK              (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134             (0 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301             (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED        ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301
-/* Software control of PHY VDL updates from control register settings. Bit 13 enables the use of Bit 14. */
-/* If software control is not enabled, then updates occur when a refresh command is issued by the hardware */
-/* controller. If 2 chips selects are being used, then software control must be enabled. */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD    (1 << 14)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE  (1 << 13)
-/* Use these to bypass a pipeline stage. By default the ADDR is off but the BYTE LANE in / out are on. */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE (1 << 12)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10)
-/* Chip select count */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT                  9
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK                   (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1                      (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2                      (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT                     8
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC                     (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC                      (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT                7
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW                  (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH                 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT                6
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW                  (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH                 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT             0
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK              (0x7 << ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT)
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT                0
-#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK                 (0x7f << ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT)
-/* ---- Public Function Prototypes --------------------------------------- */
-#ifdef __cplusplus
-}                               /* end extern "C" */
-#endif
-#endif                          /* DDRC_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
deleted file mode 100644
index d67e2f8c22de..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    dmacHw_priv.h
-*
-*  @brief   Private Definitions for low level DMA driver
-*
-*/
-/****************************************************************************/
-#ifndef _DMACHW_PRIV_H
-#define _DMACHW_PRIV_H
-#include <csp/stdint.h>
-/* Data type for DMA Link List Item */
-typedef struct {
-        uint32_t sar;           /* Source Address Register.
-                                   Address must be aligned to CTLx.SRC_TR_WIDTH.             */
-        uint32_t dar;           /* Destination Address Register.
-                                   Address must be aligned to CTLx.DST_TR_WIDTH.             */
-        uint32_t llpPhy;        /* LLP contains the physical address of the next descriptor for block chaining using linked lists.
-                                   Address MUST be aligned to a 32-bit boundary.             */
-        dmacHw_REG64_t ctl;     /* Control Register. 64 bits */
-        uint32_t sstat;         /* Source Status Register */
-        uint32_t dstat;         /* Destination Status Register */
-        uint32_t devCtl;        /* Device specific control information */
-        uint32_t llp;           /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */
-} dmacHw_DESC_t;
-/*
- *  Descriptor ring pointers
- */
-typedef struct {
-        int num;                /* Number of link items */
-        dmacHw_DESC_t *pHead;   /* Head of descriptor ring (for writing) */
-        dmacHw_DESC_t *pTail;   /* Tail of descriptor ring (for reading) */
-        dmacHw_DESC_t *pProg;   /* Descriptor to program the channel (for programming the channel register) */
-        dmacHw_DESC_t *pEnd;    /* End of current descriptor chain */
-        dmacHw_DESC_t *pFree;   /* Descriptor to free memory (freeing dynamic memory) */
-        uint32_t virt2PhyOffset;        /* Virtual to physical address offset for the descriptor ring */
-} dmacHw_DESC_RING_t;
-/*
- *  DMA channel control block
- */
-typedef struct {
-        uint32_t module;        /* DMA controller module (0-1) */
-        uint32_t channel;       /* DMA channel (0-7) */
-        volatile uint32_t varDataStarted;       /* Flag indicating variable data channel is enabled */
-        volatile uint32_t descUpdated;  /* Flag to indicate descriptor update is complete */
-        void *userData;         /* Channel specifc user data */
-} dmacHw_CBLK_t;
-#define dmacHw_ASSERT(a)                  if (!(a)) while (1)
-#define dmacHw_MAX_CHANNEL_COUNT          16
-#define dmacHw_FREE_USER_MEMORY           0xFFFFFFFF
-#define dmacHw_DESC_FREE                  dmacHw_REG_CTL_DONE
-#define dmacHw_DESC_INIT                  ((dmacHw_DESC_t *) 0xFFFFFFFF)
-#define dmacHw_MAX_BLOCKSIZE              4064
-#define dmacHw_GET_DESC_RING(addr)        (dmacHw_DESC_RING_t *)(addr)
-#define dmacHw_ADDRESS_MASK(byte)         ((byte) - 1)
-#define dmacHw_NEXT_DESC(rp, dp)           ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp)
-#define dmacHw_HANDLE_TO_CBLK(handle)     ((dmacHw_CBLK_t *) (handle))
-#define dmacHw_CBLK_TO_HANDLE(cblkp)      ((dmacHw_HANDLE_t) (cblkp))
-#define dmacHw_DST_IS_MEMORY(tt)          (((tt) ==  dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
-/****************************************************************************/
-/**
-*  @brief   Get next available transaction width
-*
-*
-*  @return  On success  : Next available transaction width
-*           On failure : dmacHw_TRANSACTION_WIDTH_8
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw    /*   [ IN ] Current transaction width */
-    ) {
-        if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
-                return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
-                         1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
-        } else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
-                return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
-                         1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
-        }
-        /* Default return  */
-        return dmacHw_SRC_TRANSACTION_WIDTH_8;
-}
-/****************************************************************************/
-/**
-*  @brief   Get number of bytes per transaction
-*
-*  @return  Number of bytes per transaction
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw        /*   [ IN ]  Transaction width */
-    ) {
-        int width = 1;
-        switch (tw) {
-        case dmacHw_SRC_TRANSACTION_WIDTH_8:
-                width = 1;
-                break;
-        case dmacHw_SRC_TRANSACTION_WIDTH_16:
-        case dmacHw_DST_TRANSACTION_WIDTH_16:
-                width = 2;
-                break;
-        case dmacHw_SRC_TRANSACTION_WIDTH_32:
-        case dmacHw_DST_TRANSACTION_WIDTH_32:
-                width = 4;
-                break;
-        case dmacHw_SRC_TRANSACTION_WIDTH_64:
-        case dmacHw_DST_TRANSACTION_WIDTH_64:
-                width = 8;
-                break;
-        default:
-                dmacHw_ASSERT(0);
-        }
-        /* Default transaction width */
-        return width;
-}
-#endif /* _DMACHW_PRIV_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
deleted file mode 100644
index f1ecf96f2da5..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    dmacHw_reg.h
-*
-*  @brief   Definitions for low level DMA registers
-*
-*/
-/****************************************************************************/
-#ifndef _DMACHW_REG_H
-#define _DMACHW_REG_H
-#include <csp/stdint.h>
-#include <mach/csp/mm_io.h>
-/* Data type for 64 bit little endian register */
-typedef struct {
-        volatile uint32_t lo;   /* Lower 32 bit in little endian mode */
-        volatile uint32_t hi;   /* Upper 32 bit in little endian mode */
-} dmacHw_REG64_t;
-/* Data type representing DMA channel registers */
-typedef struct {
-        dmacHw_REG64_t ChannelSar;      /*  Source Address Register. 64 bits (upper 32 bits are reserved)
-                                           Address must be aligned to CTLx.SRC_TR_WIDTH.
-                                         */
-        dmacHw_REG64_t ChannelDar;      /*  Destination Address Register.64 bits (upper 32 bits are reserved)
-                                           Address must be aligned to CTLx.DST_TR_WIDTH.
-                                         */
-        dmacHw_REG64_t ChannelLlp;      /*  Link List Pointer.64 bits (upper 32 bits are reserved)
-                                           LLP contains the pointer to the next LLI for block chaining using linked lists.
-                                           If LLPis set to 0x0, then transfers using linked lists are not enabled.
-                                           Address MUST be aligned to a 32-bit boundary.
-                                         */
-        dmacHw_REG64_t ChannelCtl;      /* Control Register. 64 bits */
-        dmacHw_REG64_t ChannelSstat;    /* Source Status Register */
-        dmacHw_REG64_t ChannelDstat;    /* Destination Status Register */
-        dmacHw_REG64_t ChannelSstatAddr;        /* Source Status Address Register */
-        dmacHw_REG64_t ChannelDstatAddr;        /* Destination Status Address Register */
-        dmacHw_REG64_t ChannelConfig;   /* Channel Configuration Register */
-        dmacHw_REG64_t SrcGather;       /* Source gather register */
-        dmacHw_REG64_t DstScatter;      /* Destination scatter register */
-} dmacHw_CH_REG_t;
-/* Data type for RAW interrupt status registers */
-typedef struct {
-        dmacHw_REG64_t RawTfr;  /* Raw Status for IntTfr Interrupt */
-        dmacHw_REG64_t RawBlock;        /* Raw Status for IntBlock Interrupt */
-        dmacHw_REG64_t RawSrcTran;      /* Raw Status for IntSrcTran Interrupt */
-        dmacHw_REG64_t RawDstTran;      /* Raw Status for IntDstTran Interrupt */
-        dmacHw_REG64_t RawErr;  /* Raw Status for IntErr Interrupt */
-} dmacHw_INT_RAW_t;
-/* Data type for interrupt status registers */
-typedef struct {
-        dmacHw_REG64_t StatusTfr;       /* Status for IntTfr Interrupt */
-        dmacHw_REG64_t StatusBlock;     /* Status for IntBlock Interrupt */
-        dmacHw_REG64_t StatusSrcTran;   /* Status for IntSrcTran Interrupt */
-        dmacHw_REG64_t StatusDstTran;   /* Status for IntDstTran Interrupt */
-        dmacHw_REG64_t StatusErr;       /* Status for IntErr Interrupt */
-} dmacHw_INT_STATUS_t;
-/* Data type for interrupt mask registers*/
-typedef struct {
-        dmacHw_REG64_t MaskTfr; /* Mask for IntTfr Interrupt */
-        dmacHw_REG64_t MaskBlock;       /* Mask for IntBlock Interrupt */
-        dmacHw_REG64_t MaskSrcTran;     /* Mask for IntSrcTran Interrupt */
-        dmacHw_REG64_t MaskDstTran;     /* Mask for IntDstTran Interrupt */
-        dmacHw_REG64_t MaskErr; /* Mask for IntErr Interrupt */
-} dmacHw_INT_MASK_t;
-/* Data type for interrupt clear registers */
-typedef struct {
-        dmacHw_REG64_t ClearTfr;        /* Clear for IntTfr Interrupt */
-        dmacHw_REG64_t ClearBlock;      /* Clear for IntBlock Interrupt */
-        dmacHw_REG64_t ClearSrcTran;    /* Clear for IntSrcTran Interrupt */
-        dmacHw_REG64_t ClearDstTran;    /* Clear for IntDstTran Interrupt */
-        dmacHw_REG64_t ClearErr;        /* Clear for IntErr Interrupt */
-        dmacHw_REG64_t StatusInt;       /* Status for each interrupt type */
-} dmacHw_INT_CLEAR_t;
-/* Data type for software handshaking registers */
-typedef struct {
-        dmacHw_REG64_t ReqSrcReg;       /* Source Software Transaction Request Register */
-        dmacHw_REG64_t ReqDstReg;       /* Destination Software Transaction Request Register */
-        dmacHw_REG64_t SglReqSrcReg;    /* Single Source Transaction Request Register */
-        dmacHw_REG64_t SglReqDstReg;    /* Single Destination Transaction Request Register */
-        dmacHw_REG64_t LstSrcReg;       /* Last Source Transaction Request Register */
-        dmacHw_REG64_t LstDstReg;       /* Last Destination Transaction Request Register */
-} dmacHw_SW_HANDSHAKE_t;
-/* Data type for misc. registers */
-typedef struct {
-        dmacHw_REG64_t DmaCfgReg;       /* DMA Configuration Register */
-        dmacHw_REG64_t ChEnReg; /* DMA Channel Enable Register */
-        dmacHw_REG64_t DmaIdReg;        /* DMA ID Register */
-        dmacHw_REG64_t DmaTestReg;      /* DMA Test Register */
-        dmacHw_REG64_t Reserved0;       /* Reserved */
-        dmacHw_REG64_t Reserved1;       /* Reserved */
-        dmacHw_REG64_t CompParm6;       /* Component Parameter 6 */
-        dmacHw_REG64_t CompParm5;       /* Component Parameter 5 */
-        dmacHw_REG64_t CompParm4;       /* Component Parameter 4 */
-        dmacHw_REG64_t CompParm3;       /* Component Parameter 3 */
-        dmacHw_REG64_t CompParm2;       /* Component Parameter 2 */
-        dmacHw_REG64_t CompParm1;       /* Component Parameter 1 */
-        dmacHw_REG64_t CompId;  /* Compoent ID */
-} dmacHw_MISC_t;
-/* Base registers */
-#define dmacHw_0_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA0       /* DMAC 0 module's base address */
-#define dmacHw_1_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA1       /* DMAC 1 module's base address */
-extern uint32_t dmaChannelCount_0;
-extern uint32_t dmaChannelCount_1;
-/* Define channel specific registers */
-#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
-/* Raw interrupt status registers */
-#define dmacHw_REG_INT_RAW_BASE(module)         ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
-#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
-#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
-#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
-#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
-#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
-/* Interrupt status registers */
-#define dmacHw_REG_INT_STAT_BASE(module)        ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
-#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
-#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
-#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
-#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
-#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
-/* Interrupt status registers */
-#define dmacHw_REG_INT_MASK_BASE(module)        ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
-#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
-#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
-#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
-#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
-#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
-/* Interrupt clear registers */
-#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
-#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
-#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
-#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
-#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
-#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
-#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
-/* Software handshaking registers */
-#define dmacHw_REG_SW_HS_BASE(module)           ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
-#define dmacHw_REG_SW_HS_SRC_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
-/* Miscellaneous registers */
-#define dmacHw_REG_MISC_BASE(module)            ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
-#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
-#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
-#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
-#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
-#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
-#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
-#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
-#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
-#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
-#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
-#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
-#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
-#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
-#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
-/* Channel control registers */
-#define dmacHw_REG_SAR(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
-#define dmacHw_REG_DAR(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo)
-#define dmacHw_REG_LLP(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo)
-#define dmacHw_REG_CTL_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo)
-#define dmacHw_REG_CTL_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi)
-#define dmacHw_REG_SSTAT(module, chan)          (dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo)
-#define dmacHw_REG_DSTAT(module, chan)          (dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo)
-#define dmacHw_REG_SSTATAR(module, chan)        (dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo)
-#define dmacHw_REG_DSTATAR(module, chan)        (dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo)
-#define dmacHw_REG_CFG_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo)
-#define dmacHw_REG_CFG_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi)
-#define dmacHw_REG_SGR_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo)
-#define dmacHw_REG_SGR_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi)
-#define dmacHw_REG_DSR_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo)
-#define dmacHw_REG_DSR_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi)
-#define INT_STATUS_MASK(channel)                (0x00000001 << (channel))
-#define CHANNEL_BUSY(mod, channel)              (dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel)))
-/* Bit mask for REG_DMACx_CTL_LO */
-#define dmacHw_REG_CTL_INT_EN                       0x00000001  /* Channel interrupt enable */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK            0x0000000E  /* Destination transaction width mask */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT           1
-#define dmacHw_REG_CTL_DST_TR_WIDTH_8               0x00000000  /* Destination transaction width 8 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_16              0x00000002  /* Destination transaction width 16 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_32              0x00000004  /* Destination transaction width 32 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_64              0x00000006  /* Destination transaction width 64 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK            0x00000070  /* Source transaction width mask */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT           4
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_8               0x00000000  /* Source transaction width 8 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_16              0x00000010  /* Source transaction width 16 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_32              0x00000020  /* Source transaction width 32 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_64              0x00000030  /* Source transaction width 64 bit */
-#define dmacHw_REG_CTL_DS_ENABLE                    0x00040000  /* Destination scatter enable */
-#define dmacHw_REG_CTL_SG_ENABLE                    0x00020000  /* Source gather enable */
-#define dmacHw_REG_CTL_DINC_MASK                    0x00000180  /* Destination address inc/dec mask */
-#define dmacHw_REG_CTL_DINC_INC                     0x00000000  /* Destination address increment */
-#define dmacHw_REG_CTL_DINC_DEC                     0x00000080  /* Destination address decrement */
-#define dmacHw_REG_CTL_DINC_NC                      0x00000100  /* Destination address no change */
-#define dmacHw_REG_CTL_SINC_MASK                    0x00000600  /* Source address inc/dec mask */
-#define dmacHw_REG_CTL_SINC_INC                     0x00000000  /* Source address increment */
-#define dmacHw_REG_CTL_SINC_DEC                     0x00000200  /* Source address decrement */
-#define dmacHw_REG_CTL_SINC_NC                      0x00000400  /* Source address no change */
-#define dmacHw_REG_CTL_DST_MSIZE_MASK               0x00003800  /* Destination burst transaction length */
-#define dmacHw_REG_CTL_DST_MSIZE_0                  0x00000000  /* No Destination burst */
-#define dmacHw_REG_CTL_DST_MSIZE_4                  0x00000800  /* Destination burst transaction length 4 */
-#define dmacHw_REG_CTL_DST_MSIZE_8                  0x00001000  /* Destination burst transaction length 8 */
-#define dmacHw_REG_CTL_DST_MSIZE_16                 0x00001800  /* Destination burst transaction length 16 */
-#define dmacHw_REG_CTL_SRC_MSIZE_MASK               0x0001C000  /* Source burst transaction length */
-#define dmacHw_REG_CTL_SRC_MSIZE_0                  0x00000000  /* No Source burst */
-#define dmacHw_REG_CTL_SRC_MSIZE_4                  0x00004000  /* Source burst transaction length 4 */
-#define dmacHw_REG_CTL_SRC_MSIZE_8                  0x00008000  /* Source burst transaction length 8 */
-#define dmacHw_REG_CTL_SRC_MSIZE_16                 0x0000C000  /* Source burst transaction length 16 */
-#define dmacHw_REG_CTL_TTFC_MASK                    0x00700000  /* Transfer type and flow controller */
-#define dmacHw_REG_CTL_TTFC_MM_DMAC                 0x00000000  /* Memory to Memory with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_MP_DMAC                 0x00100000  /* Memory to Peripheral with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PM_DMAC                 0x00200000  /* Peripheral to Memory with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_DMAC                 0x00300000  /* Peripheral to Peripheral with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PM_PERI                 0x00400000  /* Peripheral to Memory with Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_SPERI                0x00500000  /* Peripheral to Peripheral with Source Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_MP_PERI                 0x00600000  /* Memory to Peripheral with Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_DPERI                0x00700000  /* Peripheral to Peripheral with Destination Peripheral as flow controller */
-#define dmacHw_REG_CTL_DMS_MASK                     0x01800000  /* Destination AHB master interface */
-#define dmacHw_REG_CTL_DMS_1                        0x00000000  /* Destination AHB master interface 1 */
-#define dmacHw_REG_CTL_DMS_2                        0x00800000  /* Destination AHB master interface 2 */
-#define dmacHw_REG_CTL_SMS_MASK                     0x06000000  /* Source AHB master interface */
-#define dmacHw_REG_CTL_SMS_1                        0x00000000  /* Source AHB master interface 1 */
-#define dmacHw_REG_CTL_SMS_2                        0x02000000  /* Source AHB master interface 2 */
-#define dmacHw_REG_CTL_LLP_DST_EN                   0x08000000  /* Block chaining enable for destination side */
-#define dmacHw_REG_CTL_LLP_SRC_EN                   0x10000000  /* Block chaining enable for source side */
-/* Bit mask for REG_DMACx_CTL_HI */
-#define dmacHw_REG_CTL_BLOCK_TS_MASK                0x00000FFF  /* Block transfer size */
-#define dmacHw_REG_CTL_DONE                         0x00001000  /* Block trasnfer done */
-/* Bit mask for REG_DMACx_CFG_LO */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT                  5  /* Channel priority shift */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK          0x000000E0  /* Channel priority mask */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_0             0x00000000  /* Channel priority 0 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_1             0x00000020  /* Channel priority 1 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_2             0x00000040  /* Channel priority 2 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_3             0x00000060  /* Channel priority 3 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_4             0x00000080  /* Channel priority 4 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_5             0x000000A0  /* Channel priority 5 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_6             0x000000C0  /* Channel priority 6 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_7             0x000000E0  /* Channel priority 7 */
-#define dmacHw_REG_CFG_LO_CH_SUSPEND                0x00000100  /* Channel suspend */
-#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY             0x00000200  /* Channel FIFO empty */
-#define dmacHw_REG_CFG_LO_DST_CH_SW_HS              0x00000400  /* Destination channel SW handshaking */
-#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS              0x00000800  /* Source channel SW handshaking */
-#define dmacHw_REG_CFG_LO_CH_LOCK_MASK              0x00003000  /* Channel locking mask */
-#define dmacHw_REG_CFG_LO_CH_LOCK_DMA               0x00000000  /* Channel lock over the entire DMA transfer operation */
-#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK             0x00001000  /* Channel lock over the block transfer operation */
-#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS             0x00002000  /* Channel lock over the transaction */
-#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE            0x00010000  /* Channel lock enable */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK             0x0000C000  /* Bus locking mask */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA              0x00000000  /* Bus lock over the entire DMA transfer operation */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK            0x00004000  /* Bus lock over the block transfer operation */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS            0x00008000  /* Bus lock over the transaction */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE           0x00020000  /* Bus lock enable */
-#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW       0x00040000  /* Destination channel handshaking signal polarity low */
-#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW       0x00080000  /* Source channel handshaking signal polarity low */
-#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK   0x3FF00000  /* Maximum AMBA burst length */
-#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC           0x40000000  /* Source address auto reload */
-#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST           0x80000000  /* Destination address auto reload */
-/* Bit mask for REG_DMACx_CFG_HI */
-#define dmacHw_REG_CFG_HI_FC_DST_READY              0x00000001  /* Source transaction request is serviced when destination is ready */
-#define dmacHw_REG_CFG_HI_FIFO_ENOUGH               0x00000002  /* Initiate burst transaction when enough data in available in FIFO */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK            0x0000001C  /* AHB protection mask */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_1               0x00000004  /* AHB protection 1 */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_2               0x00000008  /* AHB protection 2 */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_3               0x00000010  /* AHB protection 3 */
-#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT           0x00000020  /* Destination status update enable */
-#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT           0x00000040  /* Source status update enable */
-#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK        0x00000780  /* Source peripheral hardware interface mask */
-#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK        0x00007800  /* Destination peripheral hardware interface mask */
-/* DMA Configuration Parameters */
-#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS          0x00000700  /* Number of channels */
-#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE         0x00001800  /* Number of master interface */
-#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE          0x0000000f  /* Maximum brust size */
-#define dmacHw_REG_COMP_PARAM_DATA_WIDTH            0x00006000  /* Data transfer width */
-/* Define GET/SET macros to program the registers */
-#define dmacHw_SET_SAR(module, channel, addr)          (dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_DAR(module, channel, addr)          (dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_LLP(module, channel, ptr)           (dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr))
-#define dmacHw_GET_SSTAT(module, channel)              (dmacHw_REG_SSTAT((module), (channel)))
-#define dmacHw_GET_DSTAT(module, channel)              (dmacHw_REG_DSTAT((module), (channel)))
-#define dmacHw_SET_SSTATAR(module, channel, addr)      (dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_DSTATAR(module, channel, addr)      (dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_CONTROL_LO(module, channel, ctl)    (dmacHw_REG_CTL_LO((module), (channel)) |= (ctl))
-#define dmacHw_RESET_CONTROL_LO(module, channel)       (dmacHw_REG_CTL_LO((module), (channel)) = 0)
-#define dmacHw_GET_CONTROL_LO(module, channel)         (dmacHw_REG_CTL_LO((module), (channel)))
-#define dmacHw_SET_CONTROL_HI(module, channel, ctl)    (dmacHw_REG_CTL_HI((module), (channel)) |= (ctl))
-#define dmacHw_RESET_CONTROL_HI(module, channel)       (dmacHw_REG_CTL_HI((module), (channel)) = 0)
-#define dmacHw_GET_CONTROL_HI(module, channel)         (dmacHw_REG_CTL_HI((module), (channel)))
-#define dmacHw_GET_BLOCK_SIZE(module, channel)         (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK)
-#define dmacHw_DMA_COMPLETE(module, channel)           (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE)
-#define dmacHw_SET_CONFIG_LO(module, channel, cfg)     (dmacHw_REG_CFG_LO((module), (channel)) |= (cfg))
-#define dmacHw_RESET_CONFIG_LO(module, channel)        (dmacHw_REG_CFG_LO((module), (channel)) = 0)
-#define dmacHw_GET_CONFIG_LO(module, channel)          (dmacHw_REG_CFG_LO((module), (channel)))
-#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len)    (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK))
-#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio))
-#define dmacHw_SET_AHB_HPROT(module, channel, protect)  (dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect))
-#define dmacHw_SET_CONFIG_HI(module, channel, cfg)      (dmacHw_REG_CFG_HI((module), (channel)) |= (cfg))
-#define dmacHw_RESET_CONFIG_HI(module, channel)         (dmacHw_REG_CFG_HI((module), (channel)) = 0)
-#define dmacHw_GET_CONFIG_HI(module, channel)           (dmacHw_REG_CFG_HI((module), (channel)))
-#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK))
-#define dmacHw_SRC_PERI_INTF(intf)                      (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)
-#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK))
-#define dmacHw_DST_PERI_INTF(intf)                      (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)
-#define dmacHw_DMA_START(module, channel)              (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
-#define dmacHw_DMA_STOP(module, channel)               (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_DMA_ENABLE(module)                      (dmacHw_REG_MISC_CFG((module)) = 1)
-#define dmacHw_DMA_DISABLE(module)                     (dmacHw_REG_MISC_CFG((module)) = 0)
-#define dmacHw_TRAN_INT_ENABLE(module, channel)        (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
-#define dmacHw_BLOCK_INT_ENABLE(module, channel)       (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
-#define dmacHw_ERROR_INT_ENABLE(module, channel)       (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
-#define dmacHw_TRAN_INT_DISABLE(module, channel)       (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_BLOCK_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_ERROR_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_STRAN_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_DTRAN_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_TRAN_INT_CLEAR(module, channel)         (dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel)))
-#define dmacHw_BLOCK_INT_CLEAR(module, channel)        (dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel)))
-#define dmacHw_ERROR_INT_CLEAR(module, channel)        (dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel)))
-#define dmacHw_GET_NUM_CHANNEL(module)                 (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1)
-#define dmacHw_GET_NUM_INTERFACE(module)               (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1)
-#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel)     ((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE)
-#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13)
-#endif /* _DMACHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
deleted file mode 100644
index cfa91bed9d34..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef CSP_HW_CFG_H
-#define CSP_HW_CFG_H
-/* ---- Include Files ---------------------------------------------------- */
-#include <cfg_global.h>
-#include <mach/csp/cap_inline.h>
-#if defined(__KERNEL__)
-#include <mach/memory_settings.h>
-#else
-#include <hw_cfg.h>
-#endif
-/* Some items that can be defined externally, but will be set to default values */
-/* if they are not defined. */
-/*      HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE   Default undefined and SS is enabled. */
-/*      HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
-/*      HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
-/*      HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values [400,533,667,800] */
-/*      HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules [8,16] */
-/*      HW_CFG_SDRAM_ADDR_BRC                Default undefined and Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */
-/*      HW_CFG_SDRAM_CLK_ASYNC               Default undefined and DDR clock is synchronous with AXI BUS clock. Define for ASYNC mode. */
-#if defined(CFG_GLOBAL_CHIP)
-  #if (CFG_GLOBAL_CHIP == FPGA11107)
-     #define HW_CFG_BUS_CLK_HZ            5000000
-     #define HW_CFG_DDR_CTLR_CLK_HZ      10000000
-     #define HW_CFG_DDR_PHY_OMIT
-     #define HW_CFG_UART_CLK_HZ           7500000
-  #else
-     #define HW_CFG_PLL_VCO_HZ           2000000000
-     #define HW_CFG_PLL2_VCO_HZ          1800000000
-     #define HW_CFG_ARM_CLK_HZ            CAP_HW_CFG_ARM_CLK_HZ
-     #define HW_CFG_BUS_CLK_HZ            166666666
-     #define HW_CFG_DDR_CTLR_CLK_HZ       333333333
-     #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
-     #define HW_CFG_UART_CLK_HZ           142857142
-     #define HW_CFG_VPM_CLK_HZ            CAP_HW_CFG_VPM_CLK_HZ
-  #endif
-#else
-   #define HW_CFG_PLL_VCO_HZ           1800000000
-   #define HW_CFG_PLL2_VCO_HZ          1800000000
-   #define HW_CFG_ARM_CLK_HZ            450000000
-   #define HW_CFG_BUS_CLK_HZ            150000000
-   #define HW_CFG_DDR_CTLR_CLK_HZ       300000000
-   #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
-   #define HW_CFG_UART_CLK_HZ           150000000
-   #define HW_CFG_VPM_CLK_HZ            300000000
-#endif
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-#endif /* CSP_HW_CFG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
deleted file mode 100644
index 0aeb6a6fe7f8..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    intcHw_reg.h
-*
-*  @brief   platform specific interrupt controller bit assignments
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-#ifndef _INTCHW_REG_H
-#define _INTCHW_REG_H
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/reg.h>
-#include <mach/csp/mm_io.h>
-/* ---- Public Constants and Types --------------------------------------- */
-#define INTCHW_NUM_IRQ_PER_INTC   32    /* Maximum number of interrupt controllers */
-#define INTCHW_NUM_INTC           3
-/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
-#define INTCHW_INTC0    ((void *)MM_IO_BASE_INTC0)
-#define INTCHW_INTC1    ((void *)MM_IO_BASE_INTC1)
-#define INTCHW_SINTC    ((void *)MM_IO_BASE_SINTC)
-/* INTC0 - interrupt controller 0 */
-#define INTCHW_INTC0_PIF_BITNUM           31    /* Peripheral interface interrupt */
-#define INTCHW_INTC0_CLCD_BITNUM          30    /* LCD Controller interrupt */
-#define INTCHW_INTC0_GE_BITNUM            29    /* Graphic engine interrupt */
-#define INTCHW_INTC0_APM_BITNUM           28    /* Audio process module interrupt */
-#define INTCHW_INTC0_ESW_BITNUM           27    /* Ethernet switch interrupt */
-#define INTCHW_INTC0_SPIH_BITNUM          26    /* SPI host interrupt */
-#define INTCHW_INTC0_TIMER3_BITNUM        25    /* Timer3 interrupt */
-#define INTCHW_INTC0_TIMER2_BITNUM        24    /* Timer2 interrupt */
-#define INTCHW_INTC0_TIMER1_BITNUM        23    /* Timer1 interrupt */
-#define INTCHW_INTC0_TIMER0_BITNUM        22    /* Timer0 interrupt */
-#define INTCHW_INTC0_SDIOH1_BITNUM        21    /* SDIO1 host interrupt */
-#define INTCHW_INTC0_SDIOH0_BITNUM        20    /* SDIO0 host interrupt */
-#define INTCHW_INTC0_USBD_BITNUM          19    /* USB device interrupt */
-#define INTCHW_INTC0_USBH1_BITNUM         18    /* USB1 host interrupt */
-#define INTCHW_INTC0_USBHD2_BITNUM        17    /* USB host2/device2 interrupt */
-#define INTCHW_INTC0_VPM_BITNUM           16    /* Voice process module interrupt */
-#define INTCHW_INTC0_DMA1C7_BITNUM        15    /* DMA1 channel 7 interrupt */
-#define INTCHW_INTC0_DMA1C6_BITNUM        14    /* DMA1 channel 6 interrupt */
-#define INTCHW_INTC0_DMA1C5_BITNUM        13    /* DMA1 channel 5 interrupt */
-#define INTCHW_INTC0_DMA1C4_BITNUM        12    /* DMA1 channel 4 interrupt */
-#define INTCHW_INTC0_DMA1C3_BITNUM        11    /* DMA1 channel 3 interrupt */
-#define INTCHW_INTC0_DMA1C2_BITNUM        10    /* DMA1 channel 2 interrupt */
-#define INTCHW_INTC0_DMA1C1_BITNUM         9    /* DMA1 channel 1 interrupt */
-#define INTCHW_INTC0_DMA1C0_BITNUM         8    /* DMA1 channel 0 interrupt */
-#define INTCHW_INTC0_DMA0C7_BITNUM         7    /* DMA0 channel 7 interrupt */
-#define INTCHW_INTC0_DMA0C6_BITNUM         6    /* DMA0 channel 6 interrupt */
-#define INTCHW_INTC0_DMA0C5_BITNUM         5    /* DMA0 channel 5 interrupt */
-#define INTCHW_INTC0_DMA0C4_BITNUM         4    /* DMA0 channel 4 interrupt */
-#define INTCHW_INTC0_DMA0C3_BITNUM         3    /* DMA0 channel 3 interrupt */
-#define INTCHW_INTC0_DMA0C2_BITNUM         2    /* DMA0 channel 2 interrupt */
-#define INTCHW_INTC0_DMA0C1_BITNUM         1    /* DMA0 channel 1 interrupt */
-#define INTCHW_INTC0_DMA0C0_BITNUM         0    /* DMA0 channel 0 interrupt */
-#define INTCHW_INTC0_PIF                  (1<<INTCHW_INTC0_PIF_BITNUM)
-#define INTCHW_INTC0_CLCD                 (1<<INTCHW_INTC0_CLCD_BITNUM)
-#define INTCHW_INTC0_GE                   (1<<INTCHW_INTC0_GE_BITNUM)
-#define INTCHW_INTC0_APM                  (1<<INTCHW_INTC0_APM_BITNUM)
-#define INTCHW_INTC0_ESW                  (1<<INTCHW_INTC0_ESW_BITNUM)
-#define INTCHW_INTC0_SPIH                 (1<<INTCHW_INTC0_SPIH_BITNUM)
-#define INTCHW_INTC0_TIMER3               (1<<INTCHW_INTC0_TIMER3_BITNUM)
-#define INTCHW_INTC0_TIMER2               (1<<INTCHW_INTC0_TIMER2_BITNUM)
-#define INTCHW_INTC0_TIMER1               (1<<INTCHW_INTC0_TIMER1_BITNUM)
-#define INTCHW_INTC0_TIMER0               (1<<INTCHW_INTC0_TIMER0_BITNUM)
-#define INTCHW_INTC0_SDIOH1               (1<<INTCHW_INTC0_SDIOH1_BITNUM)
-#define INTCHW_INTC0_SDIOH0               (1<<INTCHW_INTC0_SDIOH0_BITNUM)
-#define INTCHW_INTC0_USBD                 (1<<INTCHW_INTC0_USBD_BITNUM)
-#define INTCHW_INTC0_USBH1                (1<<INTCHW_INTC0_USBH1_BITNUM)
-#define INTCHW_INTC0_USBHD2               (1<<INTCHW_INTC0_USBHD2_BITNUM)
-#define INTCHW_INTC0_VPM                  (1<<INTCHW_INTC0_VPM_BITNUM)
-#define INTCHW_INTC0_DMA1C7               (1<<INTCHW_INTC0_DMA1C7_BITNUM)
-#define INTCHW_INTC0_DMA1C6               (1<<INTCHW_INTC0_DMA1C6_BITNUM)
-#define INTCHW_INTC0_DMA1C5               (1<<INTCHW_INTC0_DMA1C5_BITNUM)
-#define INTCHW_INTC0_DMA1C4               (1<<INTCHW_INTC0_DMA1C4_BITNUM)
-#define INTCHW_INTC0_DMA1C3               (1<<INTCHW_INTC0_DMA1C3_BITNUM)
-#define INTCHW_INTC0_DMA1C2               (1<<INTCHW_INTC0_DMA1C2_BITNUM)
-#define INTCHW_INTC0_DMA1C1               (1<<INTCHW_INTC0_DMA1C1_BITNUM)
-#define INTCHW_INTC0_DMA1C0               (1<<INTCHW_INTC0_DMA1C0_BITNUM)
-#define INTCHW_INTC0_DMA0C7               (1<<INTCHW_INTC0_DMA0C7_BITNUM)
-#define INTCHW_INTC0_DMA0C6               (1<<INTCHW_INTC0_DMA0C6_BITNUM)
-#define INTCHW_INTC0_DMA0C5               (1<<INTCHW_INTC0_DMA0C5_BITNUM)
-#define INTCHW_INTC0_DMA0C4               (1<<INTCHW_INTC0_DMA0C4_BITNUM)
-#define INTCHW_INTC0_DMA0C3               (1<<INTCHW_INTC0_DMA0C3_BITNUM)
-#define INTCHW_INTC0_DMA0C2               (1<<INTCHW_INTC0_DMA0C2_BITNUM)
-#define INTCHW_INTC0_DMA0C1               (1<<INTCHW_INTC0_DMA0C1_BITNUM)
-#define INTCHW_INTC0_DMA0C0               (1<<INTCHW_INTC0_DMA0C0_BITNUM)
-/* INTC1 - interrupt controller 1 */
-#define INTCHW_INTC1_DDRVPMP_BITNUM       27    /* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRVPMT_BITNUM       26    /* DDR and VPM HW phase align timeout interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRP_BITNUM          26    /* DDR and PLL clock phase relationship interrupt (For A0 only)) */
-#define INTCHW_INTC1_RTC2_BITNUM          25    /* Real time clock tamper interrupt */
-#define INTCHW_INTC1_VDEC_BITNUM          24    /* Hantro Video Decoder interrupt */
-/* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */
-#define INTCHW_INTC1_SPUM_BITNUM          23    /* Secure process module interrupt */
-#define INTCHW_INTC1_RTC1_BITNUM          22    /* Real time clock one-shot interrupt */
-#define INTCHW_INTC1_RTC0_BITNUM          21    /* Real time clock periodic interrupt */
-#define INTCHW_INTC1_RNG_BITNUM           20    /* Random number generator interrupt */
-#define INTCHW_INTC1_FMPU_BITNUM          19    /* Flash memory parition unit interrupt */
-#define INTCHW_INTC1_VMPU_BITNUM          18    /* VRAM memory partition interrupt */
-#define INTCHW_INTC1_DMPU_BITNUM          17    /* DDR2 memory partition interrupt */
-#define INTCHW_INTC1_KEYC_BITNUM          16    /* Key pad controller interrupt */
-#define INTCHW_INTC1_TSC_BITNUM           15    /* Touch screen controller interrupt */
-#define INTCHW_INTC1_UART0_BITNUM         14    /* UART 0 */
-#define INTCHW_INTC1_WDOG_BITNUM          13    /* Watchdog timer interrupt */
-#define INTCHW_INTC1_UART1_BITNUM         12    /* UART 1 */
-#define INTCHW_INTC1_PMUIRQ_BITNUM        11    /* ARM performance monitor interrupt */
-#define INTCHW_INTC1_COMMRX_BITNUM        10    /* ARM DDC receive interrupt */
-#define INTCHW_INTC1_COMMTX_BITNUM         9    /* ARM DDC transmit interrupt */
-#define INTCHW_INTC1_FLASHC_BITNUM         8    /* Flash controller interrupt */
-#define INTCHW_INTC1_GPHY_BITNUM           7    /* Gigabit Phy interrupt */
-#define INTCHW_INTC1_SPIS_BITNUM           6    /* SPI slave interrupt */
-#define INTCHW_INTC1_I2CS_BITNUM           5    /* I2C slave interrupt */
-#define INTCHW_INTC1_I2CH_BITNUM           4    /* I2C host interrupt */
-#define INTCHW_INTC1_I2S1_BITNUM           3    /* I2S1 interrupt */
-#define INTCHW_INTC1_I2S0_BITNUM           2    /* I2S0 interrupt */
-#define INTCHW_INTC1_GPIO1_BITNUM          1    /* GPIO bit 64//32 combined interrupt */
-#define INTCHW_INTC1_GPIO0_BITNUM          0    /* GPIO bit 31//0 combined interrupt */
-#define INTCHW_INTC1_DDRVPMT              (1<<INTCHW_INTC1_DDRVPMT_BITNUM)
-#define INTCHW_INTC1_DDRVPMP              (1<<INTCHW_INTC1_DDRVPMP_BITNUM)
-#define INTCHW_INTC1_DDRP                 (1<<INTCHW_INTC1_DDRP_BITNUM)
-#define INTCHW_INTC1_VDEC                 (1<<INTCHW_INTC1_VDEC_BITNUM)
-#define INTCHW_INTC1_SPUM                 (1<<INTCHW_INTC1_SPUM_BITNUM)
-#define INTCHW_INTC1_RTC2                 (1<<INTCHW_INTC1_RTC2_BITNUM)
-#define INTCHW_INTC1_RTC1                 (1<<INTCHW_INTC1_RTC1_BITNUM)
-#define INTCHW_INTC1_RTC0                 (1<<INTCHW_INTC1_RTC0_BITNUM)
-#define INTCHW_INTC1_RNG                  (1<<INTCHW_INTC1_RNG_BITNUM)
-#define INTCHW_INTC1_FMPU                 (1<<INTCHW_INTC1_FMPU_BITNUM)
-#define INTCHW_INTC1_IMPU                 (1<<INTCHW_INTC1_IMPU_BITNUM)
-#define INTCHW_INTC1_DMPU                 (1<<INTCHW_INTC1_DMPU_BITNUM)
-#define INTCHW_INTC1_KEYC                 (1<<INTCHW_INTC1_KEYC_BITNUM)
-#define INTCHW_INTC1_TSC                  (1<<INTCHW_INTC1_TSC_BITNUM)
-#define INTCHW_INTC1_UART0                (1<<INTCHW_INTC1_UART0_BITNUM)
-#define INTCHW_INTC1_WDOG                 (1<<INTCHW_INTC1_WDOG_BITNUM)
-#define INTCHW_INTC1_UART1                (1<<INTCHW_INTC1_UART1_BITNUM)
-#define INTCHW_INTC1_PMUIRQ               (1<<INTCHW_INTC1_PMUIRQ_BITNUM)
-#define INTCHW_INTC1_COMMRX               (1<<INTCHW_INTC1_COMMRX_BITNUM)
-#define INTCHW_INTC1_COMMTX               (1<<INTCHW_INTC1_COMMTX_BITNUM)
-#define INTCHW_INTC1_FLASHC               (1<<INTCHW_INTC1_FLASHC_BITNUM)
-#define INTCHW_INTC1_GPHY                 (1<<INTCHW_INTC1_GPHY_BITNUM)
-#define INTCHW_INTC1_SPIS                 (1<<INTCHW_INTC1_SPIS_BITNUM)
-#define INTCHW_INTC1_I2CS                 (1<<INTCHW_INTC1_I2CS_BITNUM)
-#define INTCHW_INTC1_I2CH                 (1<<INTCHW_INTC1_I2CH_BITNUM)
-#define INTCHW_INTC1_I2S1                 (1<<INTCHW_INTC1_I2S1_BITNUM)
-#define INTCHW_INTC1_I2S0                 (1<<INTCHW_INTC1_I2S0_BITNUM)
-#define INTCHW_INTC1_GPIO1                (1<<INTCHW_INTC1_GPIO1_BITNUM)
-#define INTCHW_INTC1_GPIO0                (1<<INTCHW_INTC1_GPIO0_BITNUM)
-/* SINTC secure int controller */
-#define INTCHW_SINTC_RTC2_BITNUM          15    /* Real time clock tamper interrupt */
-#define INTCHW_SINTC_TIMER3_BITNUM        14    /* Secure timer3 interrupt */
-#define INTCHW_SINTC_TIMER2_BITNUM        13    /* Secure timer2 interrupt */
-#define INTCHW_SINTC_TIMER1_BITNUM        12    /* Secure timer1 interrupt */
-#define INTCHW_SINTC_TIMER0_BITNUM        11    /* Secure timer0 interrupt */
-#define INTCHW_SINTC_SPUM_BITNUM          10    /* Secure process module interrupt */
-#define INTCHW_SINTC_RTC1_BITNUM           9    /* Real time clock one-shot interrupt */
-#define INTCHW_SINTC_RTC0_BITNUM           8    /* Real time clock periodic interrupt */
-#define INTCHW_SINTC_RNG_BITNUM            7    /* Random number generator interrupt */
-#define INTCHW_SINTC_FMPU_BITNUM           6    /* Flash memory parition unit interrupt */
-#define INTCHW_SINTC_VMPU_BITNUM           5    /* VRAM memory partition interrupt */
-#define INTCHW_SINTC_DMPU_BITNUM           4    /* DDR2 memory partition interrupt */
-#define INTCHW_SINTC_KEYC_BITNUM           3    /* Key pad controller interrupt */
-#define INTCHW_SINTC_TSC_BITNUM            2    /* Touch screen controller interrupt */
-#define INTCHW_SINTC_UART0_BITNUM          1    /* UART0 interrupt */
-#define INTCHW_SINTC_WDOG_BITNUM           0    /* Watchdog timer interrupt */
-#define INTCHW_SINTC_TIMER3               (1<<INTCHW_SINTC_TIMER3_BITNUM)
-#define INTCHW_SINTC_TIMER2               (1<<INTCHW_SINTC_TIMER2_BITNUM)
-#define INTCHW_SINTC_TIMER1               (1<<INTCHW_SINTC_TIMER1_BITNUM)
-#define INTCHW_SINTC_TIMER0               (1<<INTCHW_SINTC_TIMER0_BITNUM)
-#define INTCHW_SINTC_SPUM                 (1<<INTCHW_SINTC_SPUM_BITNUM)
-#define INTCHW_SINTC_RTC2                 (1<<INTCHW_SINTC_RTC2_BITNUM)
-#define INTCHW_SINTC_RTC1                 (1<<INTCHW_SINTC_RTC1_BITNUM)
-#define INTCHW_SINTC_RTC0                 (1<<INTCHW_SINTC_RTC0_BITNUM)
-#define INTCHW_SINTC_RNG                  (1<<INTCHW_SINTC_RNG_BITNUM)
-#define INTCHW_SINTC_FMPU                 (1<<INTCHW_SINTC_FMPU_BITNUM)
-#define INTCHW_SINTC_IMPU                 (1<<INTCHW_SINTC_IMPU_BITNUM)
-#define INTCHW_SINTC_DMPU                 (1<<INTCHW_SINTC_DMPU_BITNUM)
-#define INTCHW_SINTC_KEYC                 (1<<INTCHW_SINTC_KEYC_BITNUM)
-#define INTCHW_SINTC_TSC                  (1<<INTCHW_SINTC_TSC_BITNUM)
-#define INTCHW_SINTC_UART0                (1<<INTCHW_SINTC_UART0_BITNUM)
-#define INTCHW_SINTC_WDOG                 (1<<INTCHW_SINTC_WDOG_BITNUM)
-/* PL192 Vectored Interrupt Controller (VIC) layout */
-#define INTCHW_IRQSTATUS      0x00      /* IRQ status register */
-#define INTCHW_FIQSTATUS      0x04      /* FIQ status register */
-#define INTCHW_RAWINTR        0x08      /* Raw Interrupt Status register */
-#define INTCHW_INTSELECT      0x0c      /* Interrupt Select Register */
-#define INTCHW_INTENABLE      0x10      /* Interrupt Enable Register */
-#define INTCHW_INTENCLEAR     0x14      /* Interrupt Enable Clear Register */
-#define INTCHW_SOFTINT        0x18      /* Soft Interrupt Register */
-#define INTCHW_SOFTINTCLEAR   0x1c      /* Soft Interrupt Clear Register */
-#define INTCHW_PROTECTION     0x20      /* Protection Enable Register */
-#define INTCHW_SWPRIOMASK     0x24      /* Software Priority Mask Register */
-#define INTCHW_PRIODAISY      0x28      /* Priority Daisy Chain Register */
-#define INTCHW_VECTADDR0      0x100     /* Vector Address Registers */
-#define INTCHW_VECTPRIO0      0x200     /* Vector Priority Registers 0-31 */
-#define INTCHW_ADDRESS        0xf00     /* Vector Address Register 0-31 */
-#define INTCHW_PID            0xfe0     /* Peripheral ID Register 0-3 */
-#define INTCHW_PCELLID        0xff0     /* PrimeCell ID Register 0-3 */
-/* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
-/*                intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
-/*                uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */
-/*                uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-/* Clear one or more IRQ interrupts. */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask)
-{
-        __REG32(basep + INTCHW_INTENCLEAR) = mask;
-}
-/* Enables one or more IRQ interrupts. */
-static inline void intcHw_irq_enable(void *basep, uint32_t mask)
-{
-        __REG32(basep + INTCHW_INTENABLE) = mask;
-}
-#endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
deleted file mode 100644
index ad58cf873377..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    mm_addr.h
-*
-*  @brief   Memory Map address definitions
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-#ifndef _MM_ADDR_H
-#define _MM_ADDR_H
-/* ---- Include Files ---------------------------------------------------- */
-#if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
-#endif
-/* ---- Public Constants and Types --------------------------------------- */
-/*  Memory Map address definitions */
-#define MM_ADDR_DDR                0x00000000
-#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000   /* 16 MB - Reserved external memory for VPM use */
-#define MM_ADDR_IO_FLASHC          0x20000000
-#define MM_ADDR_IO_BROM            0x30000000
-#define MM_ADDR_IO_ARAM            0x30100000   /* 64 KB - extra cycle latency - WS switch */
-#define MM_ADDR_IO_DMA0            0x30200000
-#define MM_ADDR_IO_DMA1            0x30300000
-#define MM_ADDR_IO_ESW             0x30400000
-#define MM_ADDR_IO_CLCD            0x30500000
-#define MM_ADDR_IO_PIF             0x30580000
-#define MM_ADDR_IO_APM             0x30600000
-#define MM_ADDR_IO_SPUM            0x30700000
-#define MM_ADDR_IO_VPM_PROG        0x30800000
-#define MM_ADDR_IO_VPM_DATA        0x30A00000
-#define MM_ADDR_IO_VRAM            0x40000000   /* 64 KB  - security block in front of it */
-#define MM_ADDR_IO_CHIPC           0x80000000
-#define MM_ADDR_IO_UMI             0x80001000
-#define MM_ADDR_IO_NAND            0x80001800
-#define MM_ADDR_IO_LEDM            0x80002000
-#define MM_ADDR_IO_PWM             0x80002040
-#define MM_ADDR_IO_VINTC           0x80003000
-#define MM_ADDR_IO_GPIO0           0x80004000
-#define MM_ADDR_IO_GPIO1           0x80004800
-#define MM_ADDR_IO_I2CS            0x80005000
-#define MM_ADDR_IO_SPIS            0x80006000
-#define MM_ADDR_IO_HPM             0x80007400
-#define MM_ADDR_IO_HPM_REMAP       0x80007800
-#define MM_ADDR_IO_TZPC            0x80008000
-#define MM_ADDR_IO_MPU             0x80009000
-#define MM_ADDR_IO_SPUMP           0x8000a000
-#define MM_ADDR_IO_PKA             0x8000b000
-#define MM_ADDR_IO_RNG             0x8000c000
-#define MM_ADDR_IO_KEYC            0x8000d000
-#define MM_ADDR_IO_BBL             0x8000e000
-#define MM_ADDR_IO_OTP             0x8000f000
-#define MM_ADDR_IO_I2S0            0x80010000
-#define MM_ADDR_IO_I2S1            0x80011000
-#define MM_ADDR_IO_UARTA           0x80012000
-#define MM_ADDR_IO_UARTB           0x80013000
-#define MM_ADDR_IO_I2CH            0x80014020
-#define MM_ADDR_IO_SPIH            0x80015000
-#define MM_ADDR_IO_TSC             0x80016000
-#define MM_ADDR_IO_TMR             0x80017000
-#define MM_ADDR_IO_WATCHDOG        0x80017800
-#define MM_ADDR_IO_ETM             0x80018000
-#define MM_ADDR_IO_DDRC            0x80019000
-#define MM_ADDR_IO_SINTC           0x80100000
-#define MM_ADDR_IO_INTC0           0x80200000
-#define MM_ADDR_IO_INTC1           0x80201000
-#define MM_ADDR_IO_GE              0x80300000
-#define MM_ADDR_IO_USB_CTLR0       0x80400000
-#define MM_ADDR_IO_USB_CTLR1       0x80410000
-#define MM_ADDR_IO_USB_PHY         0x80420000
-#define MM_ADDR_IO_SDIOH0          0x80500000
-#define MM_ADDR_IO_SDIOH1          0x80600000
-#define MM_ADDR_IO_VDEC            0x80700000
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-#endif /* _MM_ADDR_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
deleted file mode 100644
index de92ec6a01aa..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    mm_io.h
-*
-*  @brief   Memory Map I/O definitions
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-#ifndef _MM_IO_H
-#define _MM_IO_H
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/mm_addr.h>
-#if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
-#endif
-/* ---- Public Constants and Types --------------------------------------- */
-#if defined(CONFIG_MMU)
-/* This macro is referenced in <mach/io.h>
- * Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx
- * This macro is referenced in <asm/arch/io.h>
- *
- * Assume VPM address is the last x MB of memory.  For VPM, map to
- * 0xf0000000 and up.
- */
-#ifndef MM_IO_PHYS_TO_VIRT
-#ifdef __ASSEMBLY__
-#define MM_IO_PHYS_TO_VIRT(phys)       (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
-#else
-#define MM_IO_PHYS_TO_VIRT(phys)       (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
-                        (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
-#endif
-#endif
-/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */
-#ifndef MM_IO_VIRT_TO_PHYS
-#ifdef __ASSEMBLY__
-#define MM_IO_VIRT_TO_PHYS(virt)       ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
-#else
-#define MM_IO_VIRT_TO_PHYS(virt)       (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
-                        ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
-#endif
-#endif
-#else
-#ifndef MM_IO_PHYS_TO_VIRT
-#define MM_IO_PHYS_TO_VIRT(phys)       (phys)
-#endif
-#ifndef MM_IO_VIRT_TO_PHYS
-#define MM_IO_VIRT_TO_PHYS(virt)       (virt)
-#endif
-#endif
-/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */
-#define MM_IO_BASE_FLASHC              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC)
-#define MM_IO_BASE_NAND                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND)
-#define MM_IO_BASE_UMI                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI)
-#define MM_IO_START MM_ADDR_IO_FLASHC   /* Physical beginning of IO mapped memory */
-#define MM_IO_BASE  MM_IO_BASE_FLASHC   /* Virtual beginning of IO mapped memory */
-#define MM_IO_BASE_BROM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM)
-#define MM_IO_BASE_ARAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM)
-#define MM_IO_BASE_DMA0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0)
-#define MM_IO_BASE_DMA1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1)
-#define MM_IO_BASE_ESW                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW)
-#define MM_IO_BASE_CLCD                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD)
-#define MM_IO_BASE_PIF                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF)
-#define MM_IO_BASE_APM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM)
-#define MM_IO_BASE_SPUM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM)
-#define MM_IO_BASE_VPM_PROG            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG)
-#define MM_IO_BASE_VPM_DATA            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA)
-#define MM_IO_BASE_VRAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM)
-#define MM_IO_BASE_CHIPC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC)
-#define MM_IO_BASE_DDRC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC)
-#define MM_IO_BASE_LEDM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM)
-#define MM_IO_BASE_PWM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM)
-#define MM_IO_BASE_VINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC)
-#define MM_IO_BASE_GPIO0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0)
-#define MM_IO_BASE_GPIO1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1)
-#define MM_IO_BASE_TMR                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR)
-#define MM_IO_BASE_WATCHDOG            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG)
-#define MM_IO_BASE_ETM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM)
-#define MM_IO_BASE_HPM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM)
-#define MM_IO_BASE_HPM_REMAP           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP)
-#define MM_IO_BASE_TZPC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC)
-#define MM_IO_BASE_MPU                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU)
-#define MM_IO_BASE_SPUMP               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP)
-#define MM_IO_BASE_PKA                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA)
-#define MM_IO_BASE_RNG                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG)
-#define MM_IO_BASE_KEYC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC)
-#define MM_IO_BASE_BBL                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL)
-#define MM_IO_BASE_OTP                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP)
-#define MM_IO_BASE_I2S0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0)
-#define MM_IO_BASE_I2S1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1)
-#define MM_IO_BASE_UARTA               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA)
-#define MM_IO_BASE_UARTB               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB)
-#define MM_IO_BASE_I2CH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH)
-#define MM_IO_BASE_SPIH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH)
-#define MM_IO_BASE_TSC                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC)
-#define MM_IO_BASE_I2CS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS)
-#define MM_IO_BASE_SPIS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS)
-#define MM_IO_BASE_SINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC)
-#define MM_IO_BASE_INTC0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0)
-#define MM_IO_BASE_INTC1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1)
-#define MM_IO_BASE_GE                  MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE)
-#define MM_IO_BASE_USB_CTLR0           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0)
-#define MM_IO_BASE_USB_CTLR1           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1)
-#define MM_IO_BASE_USB_PHY             MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY)
-#define MM_IO_BASE_SDIOH0              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0)
-#define MM_IO_BASE_SDIOH1              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1)
-#define MM_IO_BASE_VDEC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC)
-#define MM_IO_BASE_VPM_EXTMEM_RSVD     MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD)
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-#endif /* _MM_IO_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
deleted file mode 100644
index d15f5f3ec2d8..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    secHw_def.h
-*
-*  @brief   Definitions for configuring/testing secure blocks
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-#ifndef SECHW_DEF_H
-#define SECHW_DEF_H
-#include <mach/csp/mm_io.h>
-/* Bit mask for various secure device */
-#define secHw_BLK_MASK_CHIP_CONTROL     0x00000001
-#define secHw_BLK_MASK_KEY_SCAN         0x00000002
-#define secHw_BLK_MASK_TOUCH_SCREEN     0x00000004
-#define secHw_BLK_MASK_UART0            0x00000008
-#define secHw_BLK_MASK_UART1            0x00000010
-#define secHw_BLK_MASK_WATCHDOG         0x00000020
-#define secHw_BLK_MASK_SPUM             0x00000040
-#define secHw_BLK_MASK_DDR2             0x00000080
-#define secHw_BLK_MASK_EXT_MEM          0x00000100
-#define secHw_BLK_MASK_ESW              0x00000200
-#define secHw_BLK_MASK_SPU              0x00010000
-#define secHw_BLK_MASK_PKA              0x00020000
-#define secHw_BLK_MASK_RNG              0x00040000
-#define secHw_BLK_MASK_RTC              0x00080000
-#define secHw_BLK_MASK_OTP              0x00100000
-#define secHw_BLK_MASK_BOOT             0x00200000
-#define secHw_BLK_MASK_MPU              0x00400000
-#define secHw_BLK_MASK_TZCTRL           0x00800000
-#define secHw_BLK_MASK_INTR             0x01000000
-/* Trustzone register set */
-typedef struct {
-        volatile uint32_t status;       /* read only - reflects status of writes of 2 write registers */
-        volatile uint32_t setUnsecure;  /* write only. reads back as 0 */
-        volatile uint32_t setSecure;    /* write only. reads back as 0 */
-} secHw_TZREG_t;
-/* There are 2 register sets. The first is for the lower 16 bits, the 2nd */
-/* is for the higher 16 bits. */
-typedef enum {
-        secHw_IDX_LS = 0,
-        secHw_IDX_MS = 1,
-        secHw_IDX_NUM
-} secHw_IDX_e;
-typedef struct {
-        volatile secHw_TZREG_t reg[secHw_IDX_NUM];
-} secHw_REGS_t;
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setSecure(uint32_t mask        /*  mask of type secHw_BLK_MASK_XXXXXX */
-    );
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a non-secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setUnsecure(uint32_t mask      /*  mask of type secHw_BLK_MASK_XXXXXX */
-    );
-/****************************************************************************/
-/**
-*  @brief  Get the trustzone status for all components. 1 = non-secure, 0 = secure
-*
-*/
-/****************************************************************************/
-static inline uint32_t secHw_getStatus(void);
-#include <mach/csp/secHw_inline.h>
-#endif /* SECHW_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
deleted file mode 100644
index 9cd6a032ab71..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    secHw_inline.h
-*
-*  @brief   Definitions for configuring/testing secure blocks
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-#ifndef SECHW_INLINE_H
-#define SECHW_INLINE_H
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setSecure(uint32_t mask        /*  mask of type secHw_BLK_MASK_XXXXXX */
-    ) {
-        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-        if (mask & 0x0000FFFF) {
-                regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
-        }
-        if (mask & 0xFFFF0000) {
-                regp->reg[secHw_IDX_MS].setSecure = mask >> 16;
-        }
-}
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a non-secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setUnsecure(uint32_t mask      /*  mask of type secHw_BLK_MASK_XXXXXX */
-    ) {
-        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-        if (mask & 0x0000FFFF) {
-                regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
-        }
-        if (mask & 0xFFFF0000) {
-                regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
-        }
-}
-/****************************************************************************/
-/**
-*  @brief  Get the trustzone status for all components. 1 = non-secure, 0 = secure
-*
-*/
-/****************************************************************************/
-static inline uint32_t secHw_getStatus(void)
-{
-        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-        return (regp->reg[1].status << 16) + regp->reg[0].status;
-}
-#endif /* SECHW_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
deleted file mode 100644
index 3080ac7239a1..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    tmrHw_reg.h
-*
-*  @brief   Definitions for low level Timer registers
-*
-*/
-/****************************************************************************/
-#ifndef _TMRHW_REG_H
-#define _TMRHW_REG_H
-#include <mach/csp/mm_io.h>
-#include <mach/csp/hw_cfg.h>
-/* Base address */
-#define tmrHw_MODULE_BASE_ADDR          MM_IO_BASE_TMR
-/*
-This platform has four different timers running at different clock speed
-Timer one   (Timer ID 0) runs at  25 MHz
-Timer two   (Timer ID 1) runs at  25 MHz
-Timer three (Timer ID 2) runs at 150 MHz
-Timer four  (Timer ID 3) runs at 150 MHz
-*/
-#define tmrHw_LOW_FREQUENCY_MHZ         25      /* Always 25MHz from XTAL */
-#define tmrHw_LOW_FREQUENCY_HZ          25000000
-#if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107)
-#define tmrHw_HIGH_FREQUENCY_MHZ        150     /* Always 150MHz for FPGA */
-#define tmrHw_HIGH_FREQUENCY_HZ         150000000
-#else
-#define tmrHw_HIGH_FREQUENCY_HZ         HW_CFG_BUS_CLK_HZ
-#define tmrHw_HIGH_FREQUENCY_MHZ        (HW_CFG_BUS_CLK_HZ / 1000000)
-#endif
-#define tmrHw_LOW_RESOLUTION_CLOCK      tmrHw_LOW_FREQUENCY_HZ
-#define tmrHw_HIGH_RESOLUTION_CLOCK     tmrHw_HIGH_FREQUENCY_HZ
-#define tmrHw_MAX_COUNT                 (0xFFFFFFFF)    /* maximum number of count a timer can count */
-#define tmrHw_TIMER_NUM_COUNT           (4)     /* Number of timer module supported */
-typedef struct {
-        uint32_t LoadValue;     /* Load value for timer */
-        uint32_t CurrentValue;  /* Current value for timer */
-        uint32_t Control;       /* Control register */
-        uint32_t InterruptClear;        /* Interrupt clear register */
-        uint32_t RawInterruptStatus;    /* Raw interrupt status */
-        uint32_t InterruptStatus;       /* Masked interrupt status */
-        uint32_t BackgroundLoad;        /* Background load value */
-        uint32_t padding;       /* Padding register */
-} tmrHw_REG_t;
-/* Control bot masks */
-#define tmrHw_CONTROL_TIMER_ENABLE            0x00000080
-#define tmrHw_CONTROL_PERIODIC                0x00000040
-#define tmrHw_CONTROL_INTERRUPT_ENABLE        0x00000020
-#define tmrHw_CONTROL_PRESCALE_MASK           0x0000000C
-#define tmrHw_CONTROL_PRESCALE_1              0x00000000
-#define tmrHw_CONTROL_PRESCALE_16             0x00000004
-#define tmrHw_CONTROL_PRESCALE_256            0x00000008
-#define tmrHw_CONTROL_32BIT                   0x00000002
-#define tmrHw_CONTROL_ONESHOT                 0x00000001
-#define tmrHw_CONTROL_FREE_RUNNING            0x00000000
-#define tmrHw_CONTROL_MODE_MASK               (tmrHw_CONTROL_PERIODIC | tmrHw_CONTROL_ONESHOT)
-#define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR)
-#endif /* _TMRHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h
deleted file mode 100644
index 72543781207b..000000000000
--- a/arch/arm/mach-bcmring/include/mach/dma.h
+++ /dev/null
@@ -1,630 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*   @file   dma.h
-*
-*   @brief  API definitions for the linux DMA interface.
-*/
-/****************************************************************************/
-#if !defined(ASM_ARM_ARCH_BCMRING_DMA_H)
-#define ASM_ARM_ARCH_BCMRING_DMA_H
-/* ---- Include Files ---------------------------------------------------- */
-#include <linux/kernel.h>
-#include <linux/semaphore.h>
-#include <csp/dmacHw.h>
-#include <mach/timer.h>
-/* ---- Constants and Types ---------------------------------------------- */
-/* If DMA_DEBUG_TRACK_RESERVATION is set to a non-zero value, then the filename */
-/* and line number of the reservation request will be recorded in the channel table */
-#define DMA_DEBUG_TRACK_RESERVATION   1
-#define DMA_NUM_CONTROLLERS     2
-#define DMA_NUM_CHANNELS        8       /* per controller */
-typedef enum {
-        DMA_DEVICE_MEM_TO_MEM,  /* For memory to memory transfers */
-        DMA_DEVICE_I2S0_DEV_TO_MEM,
-        DMA_DEVICE_I2S0_MEM_TO_DEV,
-        DMA_DEVICE_I2S1_DEV_TO_MEM,
-        DMA_DEVICE_I2S1_MEM_TO_DEV,
-        DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM,
-        DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV,
-        DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM,
-        DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV,
-        DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM,      /* Additional mic input for beam-forming */
-        DMA_DEVICE_APM_PCM0_DEV_TO_MEM,
-        DMA_DEVICE_APM_PCM0_MEM_TO_DEV,
-        DMA_DEVICE_APM_PCM1_DEV_TO_MEM,
-        DMA_DEVICE_APM_PCM1_MEM_TO_DEV,
-        DMA_DEVICE_SPUM_DEV_TO_MEM,
-        DMA_DEVICE_SPUM_MEM_TO_DEV,
-        DMA_DEVICE_SPIH_DEV_TO_MEM,
-        DMA_DEVICE_SPIH_MEM_TO_DEV,
-        DMA_DEVICE_UART_A_DEV_TO_MEM,
-        DMA_DEVICE_UART_A_MEM_TO_DEV,
-        DMA_DEVICE_UART_B_DEV_TO_MEM,
-        DMA_DEVICE_UART_B_MEM_TO_DEV,
-        DMA_DEVICE_PIF_MEM_TO_DEV,
-        DMA_DEVICE_PIF_DEV_TO_MEM,
-        DMA_DEVICE_ESW_DEV_TO_MEM,
-        DMA_DEVICE_ESW_MEM_TO_DEV,
-        DMA_DEVICE_VPM_MEM_TO_MEM,
-        DMA_DEVICE_CLCD_MEM_TO_MEM,
-        DMA_DEVICE_NAND_MEM_TO_MEM,
-        DMA_DEVICE_MEM_TO_VRAM,
-        DMA_DEVICE_VRAM_TO_MEM,
-        /* Add new entries before this line. */
-        DMA_NUM_DEVICE_ENTRIES,
-        DMA_DEVICE_NONE = 0xff, /* Special value to indicate that no device is currently assigned. */
-} DMA_Device_t;
-/****************************************************************************
-*
-*   The DMA_Handle_t is the primary object used by callers of the API.
-*
-*****************************************************************************/
-#define DMA_INVALID_HANDLE  ((DMA_Handle_t) -1)
-typedef int DMA_Handle_t;
-/****************************************************************************
-*
-*   The DMA_DescriptorRing_t contains a ring of descriptors which is used
-*   to point to regions of memory.
-*
-*****************************************************************************/
-typedef struct {
-        void *virtAddr;         /* Virtual Address of the descriptor ring */
-        dma_addr_t physAddr;    /* Physical address of the descriptor ring */
-        int descriptorsAllocated;       /* Number of descriptors allocated in the descriptor ring */
-        size_t bytesAllocated;  /* Number of bytes allocated in the descriptor ring */
-} DMA_DescriptorRing_t;
-/****************************************************************************
-*
-*   The DMA_DeviceAttribute_t contains information which describes a
-*   particular DMA device (or peripheral).
-*
-*   It is anticipated that the arrary of DMA_DeviceAttribute_t's will be
-*   statically initialized.
-*
-*****************************************************************************/
-/* The device handler is called whenever a DMA operation completes. The reaon */
-/* for it to be called will be a bitmask with one or more of the following bits */
-/* set. */
-#define DMA_HANDLER_REASON_BLOCK_COMPLETE       dmacHw_INTERRUPT_STATUS_BLOCK
-#define DMA_HANDLER_REASON_TRANSFER_COMPLETE    dmacHw_INTERRUPT_STATUS_TRANS
-#define DMA_HANDLER_REASON_ERROR                dmacHw_INTERRUPT_STATUS_ERROR
-typedef void (*DMA_DeviceHandler_t) (DMA_Device_t dev, int reason,
-                                     void *userData);
-#define DMA_DEVICE_FLAG_ON_DMA0             0x00000001
-#define DMA_DEVICE_FLAG_ON_DMA1             0x00000002
-#define DMA_DEVICE_FLAG_PORT_PER_DMAC       0x00000004  /* If set, it means that the port used on DMAC0 is different from the port used on DMAC1 */
-#define DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST    0x00000008  /* If set, allocate from DMA1 before allocating from DMA0 */
-#define DMA_DEVICE_FLAG_IS_DEDICATED        0x00000100
-#define DMA_DEVICE_FLAG_NO_ISR              0x00000200
-#define DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO    0x00000400
-#define DMA_DEVICE_FLAG_IN_USE              0x00000800  /* If set, device is in use on a channel */
-/* Note: Some DMA devices can be used from multiple DMA Controllers. The bitmask is used to */
-/*       determine which DMA controllers a given device can be used from, and the interface */
-/*       array determeines the actual interface number to use for a given controller. */
-typedef struct {
-        uint32_t flags;         /* Bitmask of DMA_DEVICE_FLAG_xxx constants */
-        uint8_t dedicatedController;    /* Controller number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
-        uint8_t dedicatedChannel;       /* Channel number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
-        const char *name;       /* Will show up in the /proc entry */
-        uint32_t dmacPort[DMA_NUM_CONTROLLERS]; /* Specifies the port number when DMA_DEVICE_FLAG_PORT_PER_DMAC flag is set */
-        dmacHw_CONFIG_t config; /* Configuration to use when DMA'ing using this device */
-        void *userData;         /* Passed to the devHandler */
-        DMA_DeviceHandler_t devHandler; /* Called when DMA operations finish. */
-        timer_tick_count_t transferStartTime;   /* Time the current transfer was started */
-        /* The following statistical information will be collected and presented in a proc entry. */
-        /* Note: With a contiuous bandwidth of 1 Gb/sec, it would take 584 years to overflow */
-        /*       a 64 bit counter. */
-        uint64_t numTransfers;  /* Number of DMA transfers performed */
-        uint64_t transferTicks; /* Total time spent doing DMA transfers (measured in timer_tick_count_t's) */
-        uint64_t transferBytes; /* Total bytes transferred */
-        uint32_t timesBlocked;  /* Number of times a channel was unavailable */
-        uint32_t numBytes;      /* Last transfer size */
-        /* It's not possible to free memory which is allocated for the descriptors from within */
-        /* the ISR. So make the presumption that a given device will tend to use the */
-        /* same sized buffers over and over again, and we keep them around. */
-        DMA_DescriptorRing_t ring;      /* Ring of descriptors allocated for this device */
-        /* We stash away some of the information from the previous transfer. If back-to-back */
-        /* transfers are performed from the same buffer, then we don't have to keep re-initializing */
-        /* the descriptor buffers. */
-        uint32_t prevNumBytes;
-        dma_addr_t prevSrcData;
-        dma_addr_t prevDstData;
-} DMA_DeviceAttribute_t;
-/****************************************************************************
-*
-*   DMA_Channel_t, DMA_Controller_t, and DMA_State_t are really internal
-*   data structures and don't belong in this header file, but are included
-*   merely for discussion.
-*
-*   By the time this is implemented, these structures will be moved out into
-*   the appropriate C source file instead.
-*
-*****************************************************************************/
-/****************************************************************************
-*
-*   The DMA_Channel_t contains state information about each DMA channel. Some
-*   of the channels are dedicated. Non-dedicated channels are shared
-*   amongst the other devices.
-*
-*****************************************************************************/
-#define DMA_CHANNEL_FLAG_IN_USE         0x00000001
-#define DMA_CHANNEL_FLAG_IS_DEDICATED   0x00000002
-#define DMA_CHANNEL_FLAG_NO_ISR         0x00000004
-#define DMA_CHANNEL_FLAG_LARGE_FIFO     0x00000008
-typedef struct {
-        uint32_t flags;         /* bitmask of DMA_CHANNEL_FLAG_xxx constants */
-        DMA_Device_t devType;   /* Device this channel is currently reserved for */
-        DMA_Device_t lastDevType;       /* Device type that used this previously */
-        char name[20];          /* Name passed onto request_irq */
-#if (DMA_DEBUG_TRACK_RESERVATION)
-        const char *fileName;   /* Place where channel reservation took place */
-        int lineNum;            /* Place where channel reservation took place */
-#endif
-        dmacHw_HANDLE_t dmacHwHandle;   /* low level channel handle. */
-} DMA_Channel_t;
-/****************************************************************************
-*
-*   The DMA_Controller_t contains state information about each DMA controller.
-*
-*   The freeChannelQ is stored in the controller data structure rather than
-*   the channel data structure since several of the devices are accessible
-*   from multiple controllers, and there is no way to know which controller
-*   will become available first.
-*
-*****************************************************************************/
-typedef struct {
-        DMA_Channel_t channel[DMA_NUM_CHANNELS];
-} DMA_Controller_t;
-/****************************************************************************
-*
-*   The DMA_Global_t contains all of the global state information used by
-*   the DMA code.
-*
-*   Callers which need to allocate a shared channel will be queued up
-*   on the freeChannelQ until a channel becomes available.
-*
-*****************************************************************************/
-typedef struct {
-        struct semaphore lock;  /* acquired when manipulating table entries */
-        wait_queue_head_t freeChannelQ;
-        DMA_Controller_t controller[DMA_NUM_CONTROLLERS];
-} DMA_Global_t;
-/* ---- Variable Externs ------------------------------------------------- */
-extern DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES];
-/* ---- Function Prototypes ---------------------------------------------- */
-#if defined(__KERNEL__)
-/****************************************************************************/
-/**
-*   Initializes the DMA module.
-*
-*   @return
-*       0       - Success
-*       < 0     - Error
-*/
-/****************************************************************************/
-int dma_init(void);
-#if (DMA_DEBUG_TRACK_RESERVATION)
-DMA_Handle_t dma_request_channel_dbg(DMA_Device_t dev, const char *fileName,
-                                     int lineNum);
-#define dma_request_channel(dev)  dma_request_channel_dbg(dev, __FILE__, __LINE__)
-#else
-/****************************************************************************/
-/**
-*   Reserves a channel for use with @a dev. If the device is setup to use
-*   a shared channel, then this function will block until a free channel
-*   becomes available.
-*
-*   @return
-*       >= 0    - A valid DMA Handle.
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-DMA_Handle_t dma_request_channel(DMA_Device_t dev       /* Device to use with the allocated channel. */
-    );
-#endif
-/****************************************************************************/
-/**
-*   Frees a previously allocated DMA Handle.
-*
-*   @return
-*        0      - DMA Handle was released successfully.
-*       -EINVAL - Invalid DMA handle
-*/
-/****************************************************************************/
-int dma_free_channel(DMA_Handle_t channel       /* DMA handle. */
-    );
-/****************************************************************************/
-/**
-*   Determines if a given device has been configured as using a shared
-*   channel.
-*
-*   @return boolean
-*       0           Device uses a dedicated channel
-*       non-zero    Device uses a shared channel
-*/
-/****************************************************************************/
-int dma_device_is_channel_shared(DMA_Device_t dev       /* Device to check. */
-    );
-/****************************************************************************/
-/**
-*   Allocates memory to hold a descriptor ring. The descriptor ring then
-*   needs to be populated by making one or more calls to
-*   dna_add_descriptors.
-*
-*   The returned descriptor ring will be automatically initialized.
-*
-*   @return
-*       0           Descriptor ring was allocated successfully
-*       -ENOMEM     Unable to allocate memory for the desired number of descriptors.
-*/
-/****************************************************************************/
-int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,       /* Descriptor ring to populate */
-                              int numDescriptors        /* Number of descriptors that need to be allocated. */
-    );
-/****************************************************************************/
-/**
-*   Releases the memory which was previously allocated for a descriptor ring.
-*/
-/****************************************************************************/
-void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring        /* Descriptor to release */
-    );
-/****************************************************************************/
-/**
-*   Initializes a descriptor ring, so that descriptors can be added to it.
-*   Once a descriptor ring has been allocated, it may be reinitialized for
-*   use with additional/different regions of memory.
-*
-*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
-*   initialize the ring with a smaller number of descriptors. The amount
-*   of memory allocated for the descriptor ring will not be reduced, and
-*   the descriptor ring may be reinitialized later
-*
-*   @return
-*       0           Descriptor ring was initialized successfully
-*       -ENOMEM     The descriptor which was passed in has insufficient space
-*                   to hold the desired number of descriptors.
-*/
-/****************************************************************************/
-int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,        /* Descriptor ring to initialize */
-                             int numDescriptors /* Number of descriptors to initialize. */
-    );
-/****************************************************************************/
-/**
-*   Determines the number of descriptors which would be required for a
-*   transfer of the indicated memory region.
-*
-*   This function also needs to know which DMA device this transfer will
-*   be destined for, so that the appropriate DMA configuration can be retrieved.
-*   DMA parameters such as transfer width, and whether this is a memory-to-memory
-*   or memory-to-peripheral, etc can all affect the actual number of descriptors
-*   required.
-*
-*   @return
-*       > 0     Returns the number of descriptors required for the indicated transfer
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */
-                                   dma_addr_t srcData,  /* Place to get data to write to device */
-                                   dma_addr_t dstData,  /* Pointer to device data address */
-                                   size_t numBytes      /* Number of bytes to transfer to the device */
-    );
-/****************************************************************************/
-/**
-*   Adds a region of memory to the descriptor ring. Note that it may take
-*   multiple descriptors for each region of memory. It is the callers
-*   responsibility to allocate a sufficiently large descriptor ring.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-int dma_add_descriptors(DMA_DescriptorRing_t *ring,     /* Descriptor ring to add descriptors to */
-                        DMA_Device_t device,    /* DMA Device that descriptors are for */
-                        dma_addr_t srcData,     /* Place to get data (memory or device) */
-                        dma_addr_t dstData,     /* Place to put data (memory or device) */
-                        size_t numBytes /* Number of bytes to transfer to the device */
-    );
-/****************************************************************************/
-/**
-*   Sets the descriptor ring associated with a device.
-*
-*   Once set, the descriptor ring will be associated with the device, even
-*   across channel request/free calls. Passing in a NULL descriptor ring
-*   will release any descriptor ring currently associated with the device.
-*
-*   Note: If you call dma_transfer, or one of the other dma_alloc_ functions
-*         the descriptor ring may be released and reallocated.
-*
-*   Note: This function will release the descriptor memory for any current
-*         descriptor ring associated with this device.
-*/
-/****************************************************************************/
-int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */
-                                   DMA_DescriptorRing_t *ring   /* Descriptor ring to add descriptors to */
-    );
-/****************************************************************************/
-/**
-*   Retrieves the descriptor ring associated with a device.
-*/
-/****************************************************************************/
-int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */
-                                   DMA_DescriptorRing_t *ring   /* Place to store retrieved ring */
-    );
-/****************************************************************************/
-/**
-*   Allocates buffers for the descriptors. This is normally done automatically
-*   but needs to be done explicitly when initiating a dma from interrupt
-*   context.
-*
-*   @return
-*       0       Descriptors were allocated successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-int dma_alloc_descriptors(DMA_Handle_t handle,  /* DMA Handle */
-                          dmacHw_TRANSFER_TYPE_e transferType,  /* Type of transfer being performed */
-                          dma_addr_t srcData,   /* Place to get data to write to device */
-                          dma_addr_t dstData,   /* Pointer to device data address */
-                          size_t numBytes       /* Number of bytes to transfer to the device */
-    );
-/****************************************************************************/
-/**
-*   Allocates and sets up descriptors for a double buffered circular buffer.
-*
-*   This is primarily intended to be used for things like the ingress samples
-*   from a microphone.
-*
-*   @return
-*       > 0     Number of descriptors actually allocated.
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,       /* DMA Handle */
-                                     dma_addr_t srcData,        /* Physical address of source data */
-                                     dma_addr_t dstData1,       /* Physical address of first destination buffer */
-                                     dma_addr_t dstData2,       /* Physical address of second destination buffer */
-                                     size_t numBytes    /* Number of bytes in each destination buffer */
-    );
-/****************************************************************************/
-/**
-*   Initiates a transfer when the descriptors have already been setup.
-*
-*   This is a special case, and normally, the dma_transfer_xxx functions should
-*   be used.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-int dma_start_transfer(DMA_Handle_t handle);
-/****************************************************************************/
-/**
-*   Stops a previously started DMA transfer.
-*
-*   @return
-*       0       Transfer was stopped successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-int dma_stop_transfer(DMA_Handle_t handle);
-/****************************************************************************/
-/**
-*   Waits for a DMA to complete by polling. This function is only intended
-*   to be used for testing. Interrupts should be used for most DMA operations.
-*/
-/****************************************************************************/
-int dma_wait_transfer_done(DMA_Handle_t handle);
-/****************************************************************************/
-/**
-*   Initiates a DMA transfer
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*/
-/****************************************************************************/
-int dma_transfer(DMA_Handle_t handle,   /* DMA Handle */
-                 dmacHw_TRANSFER_TYPE_e transferType,   /* Type of transfer being performed */
-                 dma_addr_t srcData,    /* Place to get data to write to device */
-                 dma_addr_t dstData,    /* Pointer to device data address */
-                 size_t numBytes        /* Number of bytes to transfer to the device */
-    );
-/****************************************************************************/
-/**
-*   Initiates a transfer from memory to a device.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
-*/
-/****************************************************************************/
-static inline int dma_transfer_to_device(DMA_Handle_t handle,   /* DMA Handle */
-                                         dma_addr_t srcData,    /* Place to get data to write to device (physical address) */
-                                         dma_addr_t dstData,    /* Pointer to device data address (physical address) */
-                                         size_t numBytes        /* Number of bytes to transfer to the device */
-    ) {
-        return dma_transfer(handle,
-                            dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                            srcData, dstData, numBytes);
-}
-/****************************************************************************/
-/**
-*   Initiates a transfer from a device to memory.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*/
-/****************************************************************************/
-static inline int dma_transfer_from_device(DMA_Handle_t handle, /* DMA Handle */
-                                           dma_addr_t srcData,  /* Pointer to the device data address (physical address) */
-                                           dma_addr_t dstData,  /* Place to store data retrieved from the device (physical address) */
-                                           size_t numBytes      /* Number of bytes to retrieve from the device */
-    ) {
-        return dma_transfer(handle,
-                            dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                            srcData, dstData, numBytes);
-}
-/****************************************************************************/
-/**
-*   Initiates a memory to memory transfer.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device wasn't DMA_DEVICE_MEM_TO_MEM)
-*/
-/****************************************************************************/
-static inline int dma_transfer_mem_to_mem(DMA_Handle_t handle,  /* DMA Handle */
-                                          dma_addr_t srcData,   /* Place to transfer data from (physical address) */
-                                          dma_addr_t dstData,   /* Place to transfer data to (physical address) */
-                                          size_t numBytes       /* Number of bytes to transfer */
-    ) {
-        return dma_transfer(handle,
-                            dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-                            srcData, dstData, numBytes);
-}
-/****************************************************************************/
-/**
-*   Set the callback function which will be called when a transfer completes.
-*   If a NULL callback function is set, then no callback will occur.
-*
-*   @note   @a devHandler will be called from IRQ context.
-*
-*   @return
-*       0       - Success
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-int dma_set_device_handler(DMA_Device_t dev,    /* Device to set the callback for. */
-                           DMA_DeviceHandler_t devHandler,      /* Function to call when the DMA completes */
-                           void *userData       /* Pointer which will be passed to devHandler. */
-    );
-#endif
-#endif /* ASM_ARM_ARCH_BCMRING_DMA_H */
diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S b/arch/arm/mach-bcmring/include/mach/entry-macro.S
deleted file mode 100644
index 2f316f0e6e69..000000000000
--- a/arch/arm/mach-bcmring/include/mach/entry-macro.S
+++ /dev/null
@@ -1,76 +0,0 @@
-/*****************************************************************************
-* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/*
- *
- * Low-level IRQ helper macros for BCMRing-based platforms
- *
- */
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =(MM_IO_BASE_INTC0)
-                ldr     \irqstat, [\base, #0]           @ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
-                ands    \irqstat, \irqstat, \irqnr
-                mov     \irqnr, #IRQ_INTC0_START
-                cmp     \irqstat, #0
-                bne     1001f
-                ldr     \base, =(MM_IO_BASE_INTC1)
-                ldr     \irqstat, [\base, #0]           @ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
-                ands    \irqstat, \irqstat, \irqnr
-                mov     \irqnr, #IRQ_INTC1_START
-                cmp     \irqstat, #0
-                bne     1001f
-                ldr     \base, =(MM_IO_BASE_SINTC)
-                ldr     \irqstat, [\base, #0]           @ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
-                ands    \irqstat, \irqstat, \irqnr
-                mov     \irqnr, #0xffffffff             @ code meaning no interrupt bits set
-                cmp     \irqstat, #0
-                beq     1002f
-                mov     \irqnr, #IRQ_SINTC_START        @ something is set, so fixup return value
-1001:
-                movs    \tmp, \irqstat, lsl #16
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #16
-                movs    \tmp, \irqstat, lsl #8
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #8
-                movs    \tmp, \irqstat, lsl #4
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #4
-                movs    \tmp, \irqstat, lsl #2
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #2
-                movs    \tmp, \irqstat, lsl #1
-                addeq   \irqnr, \irqnr, #1
-                orrs    \base, \base, #1
-1002:           @ irqnr will be set to 0xffffffff if no irq bits are set
-                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h
deleted file mode 100644
index 6ae20a649a97..000000000000
--- a/arch/arm/mach-bcmring/include/mach/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *
- *  This file contains the hardware definitions of the BCMRing.
- *
- *  Copyright (C) 1999 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-#include <asm/sizes.h>
-#include <cfg_global.h>
-#include <mach/csp/mm_io.h>
-/* Hardware addresses of major areas.
- *  *_START is the physical address
- *  *_SIZE  is the size of the region
- *  *_BASE  is the virtual address
- */
-#define RAM_START               PHYS_OFFSET
-#define RAM_SIZE                (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
-#define RAM_BASE                PAGE_OFFSET
-/* Macros to make managing spinlocks a bit more controlled in terms of naming. */
-/* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */
-#if defined(__KERNEL__)
-#define HW_DECLARE_SPINLOCK(name)  DEFINE_SPINLOCK(bcmring_##name##_reg_lock);
-#define HW_EXTERN_SPINLOCK(name)   extern spinlock_t bcmring_##name##_reg_lock;
-#define HW_IRQ_SAVE(name, val)     spin_lock_irqsave(&bcmring_##name##_reg_lock, (val))
-#define HW_IRQ_RESTORE(name, val)  spin_unlock_irqrestore(&bcmring_##name##_reg_lock, (val))
-#else
-#define HW_DECLARE_SPINLOCK(name)
-#define HW_EXTERN_SPINLOCK(name)
-#define HW_IRQ_SAVE(name, val)     {(void)(name); (void)(val); }
-#define HW_IRQ_RESTORE(name, val)  {(void)(name); (void)(val); }
-#endif
-#ifndef HW_IO_PHYS_TO_VIRT
-#define HW_IO_PHYS_TO_VIRT MM_IO_PHYS_TO_VIRT
-#endif
-#define HW_IO_VIRT_TO_PHYS MM_IO_VIRT_TO_PHYS
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/irqs.h b/arch/arm/mach-bcmring/include/mach/irqs.h
deleted file mode 100644
index b279b825d4a7..000000000000
--- a/arch/arm/mach-bcmring/include/mach/irqs.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- *  Copyright (C) 2007 Broadcom
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#if !defined(ARCH_BCMRING_IRQS_H)
-#define ARCH_BCMRING_IRQS_H
-/* INTC0 - interrupt controller 0 */
-#define IRQ_INTC0_START     0
-#define IRQ_DMA0C0          0   /* DMA0 channel 0 interrupt */
-#define IRQ_DMA0C1          1   /* DMA0 channel 1 interrupt */
-#define IRQ_DMA0C2          2   /* DMA0 channel 2 interrupt */
-#define IRQ_DMA0C3          3   /* DMA0 channel 3 interrupt */
-#define IRQ_DMA0C4          4   /* DMA0 channel 4 interrupt */
-#define IRQ_DMA0C5          5   /* DMA0 channel 5 interrupt */
-#define IRQ_DMA0C6          6   /* DMA0 channel 6 interrupt */
-#define IRQ_DMA0C7          7   /* DMA0 channel 7 interrupt */
-#define IRQ_DMA1C0          8   /* DMA1 channel 0 interrupt */
-#define IRQ_DMA1C1          9   /* DMA1 channel 1 interrupt */
-#define IRQ_DMA1C2         10   /* DMA1 channel 2 interrupt */
-#define IRQ_DMA1C3         11   /* DMA1 channel 3 interrupt */
-#define IRQ_DMA1C4         12   /* DMA1 channel 4 interrupt */
-#define IRQ_DMA1C5         13   /* DMA1 channel 5 interrupt */
-#define IRQ_DMA1C6         14   /* DMA1 channel 6 interrupt */
-#define IRQ_DMA1C7         15   /* DMA1 channel 7 interrupt */
-#define IRQ_VPM            16   /* Voice process module interrupt */
-#define IRQ_USBHD2         17   /* USB host2/device2 interrupt */
-#define IRQ_USBH1          18   /* USB1 host interrupt */
-#define IRQ_USBD           19   /* USB device interrupt */
-#define IRQ_SDIOH0         20   /* SDIO0 host interrupt */
-#define IRQ_SDIOH1         21   /* SDIO1 host interrupt */
-#define IRQ_TIMER0         22   /* Timer0 interrupt */
-#define IRQ_TIMER1         23   /* Timer1 interrupt */
-#define IRQ_TIMER2         24   /* Timer2 interrupt */
-#define IRQ_TIMER3         25   /* Timer3 interrupt */
-#define IRQ_SPIH           26   /* SPI host interrupt */
-#define IRQ_ESW            27   /* Ethernet switch interrupt */
-#define IRQ_APM            28   /* Audio process module interrupt */
-#define IRQ_GE             29   /* Graphic engine interrupt */
-#define IRQ_CLCD           30   /* LCD Controller interrupt */
-#define IRQ_PIF            31   /* Peripheral interface interrupt */
-#define IRQ_INTC0_END      31
-/* INTC1 - interrupt controller 1 */
-#define IRQ_INTC1_START    32
-#define IRQ_GPIO0          32   /*  0 GPIO bit 31//0 combined interrupt */
-#define IRQ_GPIO1          33   /*  1 GPIO bit 64//32 combined interrupt */
-#define IRQ_I2S0           34   /*  2 I2S0 interrupt */
-#define IRQ_I2S1           35   /*  3 I2S1 interrupt */
-#define IRQ_I2CH           36   /*  4 I2C host interrupt */
-#define IRQ_I2CS           37   /*  5 I2C slave interrupt */
-#define IRQ_SPIS           38   /*  6 SPI slave interrupt */
-#define IRQ_GPHY           39   /*  7 Gigabit Phy interrupt */
-#define IRQ_FLASHC         40   /*  8 Flash controller interrupt */
-#define IRQ_COMMTX         41   /*  9 ARM DDC transmit interrupt */
-#define IRQ_COMMRX         42   /* 10 ARM DDC receive interrupt */
-#define IRQ_PMUIRQ         43   /* 11 ARM performance monitor interrupt */
-#define IRQ_UARTB          44   /* 12 UARTB */
-#define IRQ_WATCHDOG       45   /* 13 Watchdog timer interrupt */
-#define IRQ_UARTA          46   /* 14 UARTA */
-#define IRQ_TSC            47   /* 15 Touch screen controller interrupt */
-#define IRQ_KEYC           48   /* 16 Key pad controller interrupt */
-#define IRQ_DMPU           49   /* 17 DDR2 memory partition interrupt */
-#define IRQ_VMPU           50   /* 18 VRAM memory partition interrupt */
-#define IRQ_FMPU           51   /* 19 Flash memory parition unit interrupt */
-#define IRQ_RNG            52   /* 20 Random number generator interrupt */
-#define IRQ_RTC0           53   /* 21 Real time clock periodic interrupt */
-#define IRQ_RTC1           54   /* 22 Real time clock one-shot interrupt */
-#define IRQ_SPUM           55   /* 23 Secure process module interrupt */
-#define IRQ_VDEC           56   /* 24 Hantro video decoder interrupt */
-#define IRQ_RTC2           57   /* 25 Real time clock tamper interrupt */
-#define IRQ_DDRP           58   /* 26 DDR Panic interrupt */
-#define IRQ_INTC1_END      58
-/* SINTC secure int controller */
-#define IRQ_SINTC_START    59
-#define IRQ_SEC_WATCHDOG   59   /*  0 Watchdog timer interrupt */
-#define IRQ_SEC_UARTA      60   /*  1 UARTA interrupt */
-#define IRQ_SEC_TSC        61   /*  2 Touch screen controller interrupt */
-#define IRQ_SEC_KEYC       62   /*  3 Key pad controller interrupt */
-#define IRQ_SEC_DMPU       63   /*  4 DDR2 memory partition interrupt */
-#define IRQ_SEC_VMPU       64   /*  5 VRAM memory partition interrupt */
-#define IRQ_SEC_FMPU       65   /*  6 Flash memory parition unit interrupt */
-#define IRQ_SEC_RNG        66   /*  7 Random number generator interrupt */
-#define IRQ_SEC_RTC0       67   /*  8 Real time clock periodic interrupt */
-#define IRQ_SEC_RTC1       68   /*  9 Real time clock one-shot interrupt */
-#define IRQ_SEC_SPUM       69   /* 10 Secure process module interrupt */
-#define IRQ_SEC_TIMER0     70   /* 11 Secure timer0 interrupt */
-#define IRQ_SEC_TIMER1     71   /* 12 Secure timer1 interrupt */
-#define IRQ_SEC_TIMER2     72   /* 13 Secure timer2 interrupt */
-#define IRQ_SEC_TIMER3     73   /* 14 Secure timer3 interrupt */
-#define IRQ_SEC_RTC2       74   /* 15 Real time clock tamper interrupt */
-#define IRQ_SINTC_END      74
-/* Note: there are 3 INTC registers of 32 bits each. So internal IRQs could go from 0-95 */
-/*       Since IRQs are typically viewed in decimal, we start the gpio based IRQs off at 100 */
-/*       to make the mapping easy for humans to decipher. */
-#define IRQ_GPIO_0                  100
-#define NUM_INTERNAL_IRQS          (IRQ_SINTC_END+1)
-/* I couldn't get the gpioHw_reg.h file to be included cleanly, so I hardcoded it */
-/* define NUM_GPIO_IRQS               GPIOHW_TOTAL_NUM_PINS */
-#define NUM_GPIO_IRQS               62
-#define NR_IRQS                     (IRQ_GPIO_0 + NUM_GPIO_IRQS)
-#define IRQ_UNKNOWN                 -1
-/* Tune these bits to preclude noisy or unsupported interrupt sources as required. */
-#define IRQ_INTC0_VALID_MASK        0xffffffff
-#define IRQ_INTC1_VALID_MASK        0x07ffffff
-#define IRQ_SINTC_VALID_MASK        0x0000ffff
-#endif /* ARCH_BCMRING_IRQS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/memory_settings.h b/arch/arm/mach-bcmring/include/mach/memory_settings.h
deleted file mode 100644
index ce5cd16f2ac4..000000000000
--- a/arch/arm/mach-bcmring/include/mach/memory_settings.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef MEMORY_SETTINGS_H
-#define MEMORY_SETTINGS_H
-/* ---- Include Files ---------------------------------------- */
-/* ---- Constants and Types ---------------------------------- */
-/* Memory devices */
-/* NAND Flash timing for 166 MHz setting */
-#define HW_CFG_NAND_tBTA  (5 << 16)     /* Bus turnaround cycle (n)        0-7  (30 ns) */
-#define HW_CFG_NAND_tWP   (4 << 11)     /* Write pulse width cycle (n+1)   0-31 (25 ns) */
-#define HW_CFG_NAND_tWR   (1 << 9)      /* Write recovery cycle (n+1)      0-3  (10 ns) */
-#define HW_CFG_NAND_tAS   (0 << 7)      /* Write address setup cycle (n+1) 0-3  ( 0 ns) */
-#define HW_CFG_NAND_tOE   (3 << 5)      /* Output enable delay cycle (n)   0-3  (15 ns) */
-#define HW_CFG_NAND_tRC   (7 << 0)      /* Read access cycle (n+2)         0-31 (50 ns) */
-#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \
-        | HW_CFG_NAND_tWP  \
-        | HW_CFG_NAND_tWR  \
-        | HW_CFG_NAND_tAS  \
-        | HW_CFG_NAND_tOE  \
-        | HW_CFG_NAND_tRC)
-/* NOR Flash timing for 166 MHz setting */
-#define HW_CFG_NOR_TPRC_TWLC (0 << 19)  /* Page read access cycle / Burst write latency (n+2 / n+1) (max 25ns) */
-#define HW_CFG_NOR_TBTA      (0 << 16)  /* Bus turnaround cycle (n)                                 (DNA)      */
-#define HW_CFG_NOR_TWP       (6 << 11)  /* Write pulse width cycle (n+1)                            (35ns)     */
-#define HW_CFG_NOR_TWR       (0 << 9)   /* Write recovery cycle (n+1)                               (0ns)      */
-#define HW_CFG_NOR_TAS       (0 << 7)   /* Write address setup cycle (n+1)                          (0ns)      */
-#define HW_CFG_NOR_TOE       (0 << 5)   /* Output enable delay cycle (n)                            (max 25ns) */
-#define HW_CFG_NOR_TRC_TLC   (0x10 << 0)        /* Read access cycle / Burst read latency (n+2 / n+1)       (100ns)    */
-#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \
-        | HW_CFG_NOR_TBTA      \
-        | HW_CFG_NOR_TWP       \
-        | HW_CFG_NOR_TWR       \
-        | HW_CFG_NOR_TAS       \
-        | HW_CFG_NOR_TOE       \
-        | HW_CFG_NOR_TRC_TLC)
-#define HW_CFG_FLASH1_TCR    HW_CFG_FLASH0_TCR
-#define HW_CFG_FLASH2_TCR    HW_CFG_FLASH0_TCR
-/* SDRAM Settings */
-/* #define HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
-/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
-/* #define HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values [400,533,667,800] */
-/* #define HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules [8,16] */
-#define HW_CFG_SDRAM_SIZE_BYTES         0x10000000      /* Total memory, not per device size */
-/* ---- Variable Externs ------------------------------------- */
-/* ---- Function Prototypes ---------------------------------- */
-#endif /* MEMORY_SETTINGS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h b/arch/arm/mach-bcmring/include/mach/reg_nand.h
deleted file mode 100644
index 387376ffb56b..000000000000
--- a/arch/arm/mach-bcmring/include/mach/reg_nand.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/*
-*
-*****************************************************************************
-*
-*  REG_NAND.h
-*
-*  PURPOSE:
-*
-*     This file contains definitions for the nand registers:
-*
-*  NOTES:
-*
-*****************************************************************************/
-#if !defined(__ASM_ARCH_REG_NAND_H)
-#define __ASM_ARCH_REG_NAND_H
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
-#include <mach/reg_umi.h>
-/* ---- Constants and Types ---------------------------------------------- */
-#define HW_NAND_BASE       MM_IO_BASE_NAND      /* NAND Flash */
-/* DMA accesses by the bootstrap need hard nonvirtual addresses */
-#define REG_NAND_CMD            __REG16(HW_NAND_BASE + 0)
-#define REG_NAND_ADDR           __REG16(HW_NAND_BASE + 4)
-#define REG_NAND_PHYS_DATA16   (HW_NAND_BASE + 8)
-#define REG_NAND_PHYS_DATA8    (HW_NAND_BASE + 8)
-#define REG_NAND_DATA16         __REG16(REG_NAND_PHYS_DATA16)
-#define REG_NAND_DATA8          __REG8(REG_NAND_PHYS_DATA8)
-/* use appropriate offset to make sure it start at the 1K boundary */
-#define REG_NAND_PHYS_DATA_DMA   (HW_NAND_BASE + 0x400)
-#define REG_NAND_DATA_DMA         __REG32(REG_NAND_PHYS_DATA_DMA)
-/* Linux DMA requires physical address of the data register */
-#define REG_NAND_DATA16_PADDR    HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA16)
-#define REG_NAND_DATA8_PADDR     HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA8)
-#define REG_NAND_DATA_PADDR      HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA_DMA)
-#define NAND_BUS_16BIT()        (0)
-#define NAND_BUS_8BIT()         (!NAND_BUS_16BIT())
-/* Register offsets */
-#define REG_NAND_CMD_OFFSET     (0)
-#define REG_NAND_ADDR_OFFSET    (4)
-#define REG_NAND_DATA8_OFFSET   (8)
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h
deleted file mode 100644
index 0992842caa77..000000000000
--- a/arch/arm/mach-bcmring/include/mach/reg_umi.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*****************************************************************************
-* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/*
-*
-*****************************************************************************
-*
-*  REG_UMI.h
-*
-*  PURPOSE:
-*
-*     This file contains definitions for the nand registers:
-*
-*  NOTES:
-*
-*****************************************************************************/
-#if !defined(__ASM_ARCH_REG_UMI_H)
-#define __ASM_ARCH_REG_UMI_H
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
-#include <mach/csp/mm_io.h>
-/* ---- Constants and Types ---------------------------------------------- */
-/* Unified Memory Interface Ctrl Register */
-#define HW_UMI_BASE       MM_IO_BASE_UMI
-/* Flash bank 0 timing and control register */
-#define REG_UMI_FLASH0_TCR         __REG32(HW_UMI_BASE  + 0x00)
-/* Flash bank 1 timing and control register */
-#define REG_UMI_FLASH1_TCR         __REG32(HW_UMI_BASE  + 0x04)
-/* Flash bank 2 timing and control register */
-#define REG_UMI_FLASH2_TCR         __REG32(HW_UMI_BASE  + 0x08)
-/* MMD interface and control register */
-#define REG_UMI_MMD_ICR            __REG32(HW_UMI_BASE  + 0x0c)
-/* NAND timing and control register */
-#define REG_UMI_NAND_TCR           __REG32(HW_UMI_BASE  + 0x18)
-/* NAND ready/chip select register */
-#define REG_UMI_NAND_RCSR          __REG32(HW_UMI_BASE  + 0x1c)
-/* NAND ECC control & status register */
-#define REG_UMI_NAND_ECC_CSR       __REG32(HW_UMI_BASE  + 0x20)
-/* NAND ECC data register XXB2B1B0 */
-#define REG_UMI_NAND_ECC_DATA      __REG32(HW_UMI_BASE  + 0x24)
-/* BCH ECC Parameter N */
-#define REG_UMI_BCH_N              __REG32(HW_UMI_BASE  + 0x40)
-/* BCH ECC Parameter T */
-#define REG_UMI_BCH_K              __REG32(HW_UMI_BASE  + 0x44)
-/* BCH ECC Parameter K */
-#define REG_UMI_BCH_T              __REG32(HW_UMI_BASE  + 0x48)
-/* BCH ECC Contro Status */
-#define REG_UMI_BCH_CTRL_STATUS    __REG32(HW_UMI_BASE  + 0x4C)
-/* BCH WR ECC 31:0 */
-#define REG_UMI_BCH_WR_ECC_0       __REG32(HW_UMI_BASE  + 0x50)
-/* BCH WR ECC 63:32 */
-#define REG_UMI_BCH_WR_ECC_1       __REG32(HW_UMI_BASE  + 0x54)
-/* BCH WR ECC 95:64 */
-#define REG_UMI_BCH_WR_ECC_2       __REG32(HW_UMI_BASE  + 0x58)
-/* BCH WR ECC 127:96 */
-#define REG_UMI_BCH_WR_ECC_3       __REG32(HW_UMI_BASE  + 0x5c)
-/* BCH WR ECC 155:128 */
-#define REG_UMI_BCH_WR_ECC_4       __REG32(HW_UMI_BASE  + 0x60)
-/* BCH Read Error Location 1,0 */
-#define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE  + 0x64)
-/* BCH Read Error Location 3,2 */
-#define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE  + 0x68)
-/* BCH Read Error Location 5,4 */
-#define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE  + 0x6c)
-/* BCH Read Error Location 7,6 */
-#define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE  + 0x70)
-/* BCH Read Error Location 9,8 */
-#define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE  + 0x74)
-/* BCH Read Error Location 11,10 */
-#define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE  + 0x78)
-/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */
-/* Enable wait pin during burst write or read */
-#define REG_UMI_TCR_WAITEN              0x80000000
-/* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */
-#define REG_UMI_TCR_LOWFREQ             0x40000000
-/* 1=synch write, 0=async write */
-#define REG_UMI_TCR_MEMTYPE_SYNCWRITE   0x20000000
-/* 1=synch read, 0=async read */
-#define REG_UMI_TCR_MEMTYPE_SYNCREAD    0x10000000
-/* 1=page mode read, 0=normal mode read */
-#define REG_UMI_TCR_MEMTYPE_PAGEREAD    0x08000000
-/* page size/burst size (wrap only) */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_MASK   0x07000000
-/* 4 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_4      0x00000000
-/* 8 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_8      0x01000000
-/* 16 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_16     0x02000000
-/* 32 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_32     0x03000000
-/* 64 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_64     0x04000000
-/* 128 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_128    0x05000000
-/* 256 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_256    0x06000000
-/* 512 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_512    0x07000000
-/* Page read access cycle / Burst write latency (n+2 / n+1) */
-#define REG_UMI_TCR_TPRC_TWLC_MASK      0x00f80000
-/* Bus turnaround cycle (n) */
-#define REG_UMI_TCR_TBTA_MASK           0x00070000
-/* Write pulse width cycle (n+1) */
-#define REG_UMI_TCR_TWP_MASK            0x0000f800
-/* Write recovery cycle (n+1) */
-#define REG_UMI_TCR_TWR_MASK            0x00000600
-/* Write address setup cycle (n+1) */
-#define REG_UMI_TCR_TAS_MASK            0x00000180
-/* Output enable delay cycle (n) */
-#define REG_UMI_TCR_TOE_MASK            0x00000060
-/* Read access cycle / Burst read latency (n+2 / n+1) */
-#define REG_UMI_TCR_TRC_TLC_MASK        0x0000001f
-/* REG_UMI_MMD_ICR bits */
-/* Flash write protection pin control */
-#define REG_UMI_MMD_ICR_FLASH_WP            0x8000
-/* Extend hold time for sram0, sram1 csn (39 MHz operation) */
-#define REG_UMI_MMD_ICR_XHCS                0x4000
-/* Enable SDRAM 2 interface control */
-#define REG_UMI_MMD_ICR_SDRAM2EN            0x2000
-/* Enable merge of flash banks 0/1 to 512 MBit bank */
-#define REG_UMI_MMD_ICR_INST512             0x1000
-/* Enable merge of flash banks 1/2 to 512 MBit bank */
-#define REG_UMI_MMD_ICR_DATA512             0x0800
-/* Enable SDRAM interface control */
-#define REG_UMI_MMD_ICR_SDRAMEN             0x0400
-/* Polarity of busy state of Burst Wait Signal */
-#define REG_UMI_MMD_ICR_WAITPOL             0x0200
-/* Enable burst clock stopped when not accessing external burst flash/sram */
-#define REG_UMI_MMD_ICR_BCLKSTOP            0x0100
-/* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */
-#define REG_UMI_MMD_ICR_PERI1EN             0x0080
-/* Enable the peri2_csn to replace sdram_csn */
-#define REG_UMI_MMD_ICR_PERI2EN             0x0040
-/* Enable the peri3_csn to replace sdram2_csn */
-#define REG_UMI_MMD_ICR_PERI3EN             0x0020
-/* Enable sram bank1 for H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSB1               0x0010
-/* Enable sram bank0 for H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSB0               0x0008
-/* Polarity for assert3ed state of H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSPOL              0x0004
-/* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */
-/* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */
-#define REG_UMI_MMD_ICR_MRSMODE             0x0002
-/* MRS state for S/W controlled mode */
-#define REG_UMI_MMD_ICR_MRSSTATE            0x0001
-/* REG_UMI_NAND_TCR bits */
-/* Enable software to control CS */
-#define REG_UMI_NAND_TCR_CS_SWCTRL          0x80000000
-/* 16-bit nand wordsize if set */
-#define REG_UMI_NAND_TCR_WORD16             0x40000000
-/* Bus turnaround cycle (n) */
-#define REG_UMI_NAND_TCR_TBTA_MASK          0x00070000
-/* Write pulse width cycle (n+1) */
-#define REG_UMI_NAND_TCR_TWP_MASK           0x0000f800
-/* Write recovery cycle (n+1) */
-#define REG_UMI_NAND_TCR_TWR_MASK           0x00000600
-/* Write address setup cycle (n+1) */
-#define REG_UMI_NAND_TCR_TAS_MASK           0x00000180
-/* Output enable delay cycle (n) */
-#define REG_UMI_NAND_TCR_TOE_MASK           0x00000060
-/* Read access cycle (n+2) */
-#define REG_UMI_NAND_TCR_TRC_TLC_MASK       0x0000001f
-/* REG_UMI_NAND_RCSR bits */
-/* Status: Ready=1, Busy=0 */
-#define REG_UMI_NAND_RCSR_RDY               0x02
-/* Keep CS asserted during operation */
-#define REG_UMI_NAND_RCSR_CS_ASSERTED       0x01
-/* REG_UMI_NAND_ECC_CSR bits */
-/* Interrupt status - read-only */
-#define REG_UMI_NAND_ECC_CSR_NANDINT        0x80000000
-/* Read: Status of ECC done, Write: clear ECC interrupt */
-#define REG_UMI_NAND_ECC_CSR_ECCINT_RAW     0x00800000
-/* Read: Status of R/B, Write: clear R/B interrupt */
-#define REG_UMI_NAND_ECC_CSR_RBINT_RAW      0x00400000
-/* 1 = Enable ECC Interrupt */
-#define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE  0x00008000
-/* 1 = Assert interrupt at rising edge of R/B_ */
-#define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE   0x00004000
-/* Calculate ECC by 0=512 bytes, 1=256 bytes */
-#define REG_UMI_NAND_ECC_CSR_256BYTE        0x00000080
-/* Enable ECC in hardware */
-#define REG_UMI_NAND_ECC_CSR_ECC_ENABLE     0x00000001
-/* REG_UMI_BCH_CTRL_STATUS bits */
-/* Shift to Indicate Number of correctable errors detected */
-#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20
-/* Indicate Number of correctable errors detected */
-#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000
-/* Indicate Errors detected during read but uncorrectable */
-#define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR    0x00080000
-/* Indicate Errors detected during read and are correctable */
-#define REG_UMI_BCH_CTRL_STATUS_CORR_ERR      0x00040000
-/* Flag indicates BCH's ECC status of read process are valid */
-#define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID  0x00020000
-/* Flag indicates BCH's ECC status of write process are valid */
-#define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID  0x00010000
-/* Pause ECC calculation */
-#define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010
-/* Enable Interrupt */
-#define REG_UMI_BCH_CTRL_STATUS_INT_EN        0x00000004
-/* Enable ECC during read */
-#define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN     0x00000002
-/* Enable ECC during write */
-#define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN     0x00000001
-/* Mask for location */
-#define REG_UMI_BCH_ERR_LOC_MASK              0x00001FFF
-/* location within a byte */
-#define REG_UMI_BCH_ERR_LOC_BYTE              0x00000007
-/* location within a word */
-#define REG_UMI_BCH_ERR_LOC_WORD              0x00000018
-/* location within a page (512 byte) */
-#define REG_UMI_BCH_ERR_LOC_PAGE              0x00001FE0
-#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/timer.h b/arch/arm/mach-bcmring/include/mach/timer.h
deleted file mode 100644
index 5a94bbb032b6..000000000000
--- a/arch/arm/mach-bcmring/include/mach/timer.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/*
-*
-*****************************************************************************
-*
-*  timer.h
-*
-*  PURPOSE:
-*
-*
-*
-*  NOTES:
-*
-*****************************************************************************/
-#if !defined(BCM_LINUX_TIMER_H)
-#define BCM_LINUX_TIMER_H
-#if defined(__KERNEL__)
-/* ---- Include Files ---------------------------------------------------- */
-/* ---- Constants and Types ---------------------------------------------- */
-typedef unsigned int timer_tick_count_t;
-typedef unsigned int timer_tick_rate_t;
-typedef unsigned int timer_msec_t;
-/* ---- Variable Externs ------------------------------------------------- */
-/* ---- Function Prototypes ---------------------------------------------- */
-/****************************************************************************
-*
-*  timer_get_tick_count
-*
-*
-***************************************************************************/
-timer_tick_count_t timer_get_tick_count(void);
-/****************************************************************************
-*
-*  timer_get_tick_rate
-*
-*
-***************************************************************************/
-timer_tick_rate_t timer_get_tick_rate(void);
-/****************************************************************************
-*
-*  timer_get_msec
-*
-*
-***************************************************************************/
-timer_msec_t timer_get_msec(void);
-/****************************************************************************
-*
-*  timer_ticks_to_msec
-*
-*
-***************************************************************************/
-timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks);
-#endif /* __KERNEL__ */
-#endif /* BCM_LINUX_TIMER_H */
diff --git a/arch/arm/mach-bcmring/include/mach/timex.h b/arch/arm/mach-bcmring/include/mach/timex.h
deleted file mode 100644
index 40d033ec5892..000000000000
--- a/arch/arm/mach-bcmring/include/mach/timex.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *
- *  Integrator architecture timex specifications
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/*
- * Specifies the number of ticks per second
- */
-#define CLOCK_TICK_RATE         100000 /* REG_SMT_TICKS_PER_SEC */
diff --git a/arch/arm/mach-bcmring/include/mach/uncompress.h b/arch/arm/mach-bcmring/include/mach/uncompress.h
deleted file mode 100644
index 9c9821b77977..000000000000
--- a/arch/arm/mach-bcmring/include/mach/uncompress.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*****************************************************************************
-* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <mach/csp/mm_addr.h>
-#define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
-#define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18))
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-        /* Send out UARTA */
-        while (BCMRING_UART_0_FR & (1 << 5))
-                ;
-        BCMRING_UART_0_DR = c;
-}
-static inline void flush(void)
-{
-        /* Wait for the tx fifo to be empty */
-        while ((BCMRING_UART_0_FR & (1 << 7)) == 0)
-                ;
-        /* Wait for the final character to be sent on the txd line */
-        while (BCMRING_UART_0_FR & (1 << 3))
-                ;
-}
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
deleted file mode 100644
index 437fa683bcb2..000000000000
--- a/arch/arm/mach-bcmring/irq.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/stddef.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-#include <mach/csp/intcHw_reg.h>
-#include <mach/csp/mm_io.h>
-static void bcmring_mask_irq0(struct irq_data *d)
-{
-        writel(1 << (d->irq - IRQ_INTC0_START),
-               MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR);
-}
-static void bcmring_unmask_irq0(struct irq_data *d)
-{
-        writel(1 << (d->irq - IRQ_INTC0_START),
-               MM_IO_BASE_INTC0 + INTCHW_INTENABLE);
-}
-static void bcmring_mask_irq1(struct irq_data *d)
-{
-        writel(1 << (d->irq - IRQ_INTC1_START),
-               MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR);
-}
-static void bcmring_unmask_irq1(struct irq_data *d)
-{
-        writel(1 << (d->irq - IRQ_INTC1_START),
-               MM_IO_BASE_INTC1 + INTCHW_INTENABLE);
-}
-static void bcmring_mask_irq2(struct irq_data *d)
-{
-        writel(1 << (d->irq - IRQ_SINTC_START),
-               MM_IO_BASE_SINTC + INTCHW_INTENCLEAR);
-}
-static void bcmring_unmask_irq2(struct irq_data *d)
-{
-        writel(1 << (d->irq - IRQ_SINTC_START),
-               MM_IO_BASE_SINTC + INTCHW_INTENABLE);
-}
-static struct irq_chip bcmring_irq0_chip = {
-        .name = "ARM-INTC0",
-        .irq_ack = bcmring_mask_irq0,
-        .irq_mask = bcmring_mask_irq0,  /* mask a specific interrupt, blocking its delivery. */
-        .irq_unmask = bcmring_unmask_irq0,      /* unmaks an interrupt */
-};
-static struct irq_chip bcmring_irq1_chip = {
-        .name = "ARM-INTC1",
-        .irq_ack = bcmring_mask_irq1,
-        .irq_mask = bcmring_mask_irq1,
-        .irq_unmask = bcmring_unmask_irq1,
-};
-static struct irq_chip bcmring_irq2_chip = {
-        .name = "ARM-SINTC",
-        .irq_ack = bcmring_mask_irq2,
-        .irq_mask = bcmring_mask_irq2,
-        .irq_unmask = bcmring_unmask_irq2,
-};
-static void vic_init(void __iomem *base, struct irq_chip *chip,
-                     unsigned int irq_start, unsigned int vic_sources)
-{
-        unsigned int i;
-        for (i = 0; i < 32; i++) {
-                unsigned int irq = irq_start + i;
-                irq_set_chip(irq, chip);
-                irq_set_chip_data(irq, base);
-                if (vic_sources & (1 << i)) {
-                        irq_set_handler(irq, handle_level_irq);
-                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-                }
-        }
-        writel(0, base + INTCHW_INTSELECT);
-        writel(0, base + INTCHW_INTENABLE);
-        writel(~0, base + INTCHW_INTENCLEAR);
-        writel(0, base + INTCHW_IRQSTATUS);
-        writel(~0, base + INTCHW_SOFTINTCLEAR);
-}
-void __init bcmring_init_irq(void)
-{
-        vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip,
-                 IRQ_INTC0_START, IRQ_INTC0_VALID_MASK);
-        vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip,
-                 IRQ_INTC1_START, IRQ_INTC1_VALID_MASK);
-        vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip,
-                 IRQ_SINTC_START, IRQ_SINTC_VALID_MASK);
-        /* special cases */
-        if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
-                irq_set_handler(IRQ_GPIO0, handle_simple_irq);
-        }
-        if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
-                irq_set_handler(IRQ_GPIO1, handle_simple_irq);
-        }
-}
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
deleted file mode 100644
index 1adec78ec940..000000000000
--- a/arch/arm/mach-bcmring/mm.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-#define IO_DESC(va, sz) { .virtual = va, \
-        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
-        .length = sz, \
-        .type = MT_DEVICE }
-#define MEM_DESC(va, sz) { .virtual = va, \
-        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
-        .length = sz, \
-        .type = MT_MEMORY }
-static struct map_desc bcmring_io_desc[] __initdata = {
-        IO_DESC(MM_IO_BASE_NAND, SZ_64K),       /* phys:0x28000000-0x28000FFF  virt:0xE8000000-0xE8000FFF  size:0x00010000 */
-        IO_DESC(MM_IO_BASE_UMI, SZ_64K),        /* phys:0x2C000000-0x2C000FFF  virt:0xEC000000-0xEC000FFF  size:0x00010000 */
-        IO_DESC(MM_IO_BASE_BROM, SZ_64K),       /* phys:0x30000000-0x3000FFFF  virt:0xF3000000-0xF300FFFF  size:0x00010000 */
-        MEM_DESC(MM_IO_BASE_ARAM, SZ_1M),       /* phys:0x31000000-0x31FFFFFF  virt:0xF3100000-0xF31FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_DMA0, SZ_1M),        /* phys:0x32000000-0x32FFFFFF  virt:0xF3200000-0xF32FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_DMA1, SZ_1M),        /* phys:0x33000000-0x33FFFFFF  virt:0xF3300000-0xF33FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_ESW, SZ_1M), /* phys:0x34000000-0x34FFFFFF  virt:0xF3400000-0xF34FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_CLCD, SZ_1M),        /* phys:0x35000000-0x35FFFFFF  virt:0xF3500000-0xF35FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_APM, SZ_1M), /* phys:0x36000000-0x36FFFFFF  virt:0xF3600000-0xF36FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_SPUM, SZ_1M),        /* phys:0x37000000-0x37FFFFFF  virt:0xF3700000-0xF37FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M),    /* phys:0x38000000-0x38FFFFFF  virt:0xF3800000-0xF38FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M),    /* phys:0x3A000000-0x3AFFFFFF  virt:0xF3A00000-0xF3AFFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_VRAM, SZ_64K),       /* phys:0x40000000-0x4000FFFF  virt:0xF4000000-0xF400FFFF  size:0x00010000 */
-        IO_DESC(MM_IO_BASE_CHIPC, SZ_16M),      /* phys:0x80000000-0x80FFFFFF  virt:0xF8000000-0xF8FFFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
-                SZ_16M),        /* phys:0x0F000000-0x0FFFFFFF  virt:0xF0000000-0xF0FFFFFF  size:0x01000000 */
-};
-void __init bcmring_map_io(void)
-{
-        iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
-        /* Maximum DMA memory allowed is 14M */
-        init_consistent_dma_size(14 << 20);
-}
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
deleted file mode 100644
index af9c3d7e2a0c..000000000000
--- a/arch/arm/mach-bcmring/timer.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <linux/types.h>
-#include <linux/module.h>
-#include <csp/tmrHw.h>
-#include <mach/timer.h>
-/* The core.c file initializes timers 1 and 3 as a linux clocksource. */
-/* The real time clock should probably be the real linux clocksource. */
-/* In the meantime, this file should agree with core.c as to the */
-/* profiling timer. If the clocksource is moved to rtc later, then */
-/* we can init the profiling timer here instead. */
-/* Timer 1 provides 25MHz resolution syncrhonized to scheduling and APM timing */
-/* Timer 3 provides bus freqeuncy sychronized to ACLK, but spread spectrum will */
-/* affect synchronization with scheduling and APM timing. */
-#define PROF_TIMER 1
-timer_tick_rate_t timer_get_tick_rate(void)
-{
-        return tmrHw_getCountRate(PROF_TIMER);
-}
-timer_tick_count_t timer_get_tick_count(void)
-{
-        return tmrHw_GetCurrentCount(PROF_TIMER);       /* change downcounter to upcounter */
-}
-timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks)
-{
-        static int tickRateMsec;
-        if (tickRateMsec == 0) {
-                tickRateMsec = timer_get_tick_rate() / 1000;
-        }
-        return ticks / tickRateMsec;
-}
-timer_msec_t timer_get_msec(void)
-{
-        return timer_ticks_to_msec(timer_get_tick_count());
-}
-EXPORT_SYMBOL(timer_get_tick_count);
-EXPORT_SYMBOL(timer_ticks_to_msec);
-EXPORT_SYMBOL(timer_get_tick_rate);
-EXPORT_SYMBOL(timer_get_msec);
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index ea036d621581..e6135363765a 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -16,12 +16,6 @@ config ARCH_CDB89712
          The board includes 2 serial ports, Ethernet, IRDA, and expansion
          headers.  It comes with 16 MB SDRAM and 8 MB flash ROM.
-config ARCH_CEIVA
-        bool "CEIVA"
-        help
-          Say Y here if you intend to run this kernel on the Ceiva/Polaroid
-          PhotoMax Digital Picture Frame.
 config ARCH_CLEP7312
        bool "CLEP7312"
        help
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index f2f0256232e3..6da6940b3656 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -9,12 +9,9 @@ obj-m			:=
 obj-n                   :=
 obj-                    :=
-obj-$(CONFIG_ARCH_CEIVA) += ceiva.o
 obj-$(CONFIG_ARCH_AUTCPU12) += autcpu12.o
 obj-$(CONFIG_ARCH_CDB89712) += cdb89712.o
 obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o
 obj-$(CONFIG_ARCH_EDB7211)  += edb7211-arch.o edb7211-mm.o
 obj-$(CONFIG_ARCH_FORTUNET) += fortunet.o
 obj-$(CONFIG_ARCH_P720T)    += p720t.o
-leds-$(CONFIG_ARCH_P720T)   += p720t-leds.o
-obj-$(CONFIG_LEDS)          += $(leds-y)
diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
index 3fb79a1d0bde..32871918bb6e 100644
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ b/arch/arm/mach-clps711x/autcpu12.c
@@ -23,6 +23,8 @@
 #include <linux/string.h>
 #include <linux/mm.h>
 #include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
 #include <mach/hardware.h>
 #include <asm/sizes.h>
@@ -62,9 +64,26 @@ void __init autcpu12_map_io(void)
        iotable_init(autcpu12_io_desc, ARRAY_SIZE(autcpu12_io_desc));
 }
+static struct resource autcpu12_nvram_resource[] __initdata = {
+        DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
+};
+static struct platform_device autcpu12_nvram_pdev __initdata = {
+        .name           = "autcpu12_nvram",
+        .id             = -1,
+        .resource       = autcpu12_nvram_resource,
+        .num_resources  = ARRAY_SIZE(autcpu12_nvram_resource),
+};
+static void __init autcpu12_init(void)
+{
+        platform_device_register(&autcpu12_nvram_pdev);
+}
 MACHINE_START(AUTCPU12, "autronix autcpu12")
        /* Maintainer: Thomas Gleixner */
        .atag_offset    = 0x20000,
+        .init_machine   = autcpu12_init,
        .map_io         = autcpu12_map_io,
        .init_irq       = clps711x_init_irq,
        .timer          = &clps711x_timer,
diff --git a/arch/arm/mach-clps711x/ceiva.c b/arch/arm/mach-clps711x/ceiva.c
deleted file mode 100644
index a70147e347ac..000000000000
--- a/arch/arm/mach-clps711x/ceiva.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/arch-ceiva.c
- *
- *  Copyright (C) 2002, Rob Scott <rscott@mtrob.fdns.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <linux/kernel.h>
-#include <mach/hardware.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/sizes.h>
-#include <asm/mach/map.h>
-#include "common.h"
-static struct map_desc ceiva_io_desc[] __initdata = {
-        /* SED1355 controlled video RAM & registers */
-        {
-                .virtual        = CEIVA_VIRT_SED1355,
-                .pfn            = __phys_to_pfn(CEIVA_PHYS_SED1355),
-                .length         = SZ_2M,
-                .type           = MT_DEVICE
-        }
-};
-static void __init ceiva_map_io(void)
-{
-        clps711x_map_io();
-        iotable_init(ceiva_io_desc, ARRAY_SIZE(ceiva_io_desc));
-}
-MACHINE_START(CEIVA, "CEIVA/Polaroid Photo MAX Digital Picture Frame")
-        /* Maintainer: Rob Scott */
-        .atag_offset    = 0x100,
-        .map_io         = ceiva_map_io,
-        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
-        .restart        = clps711x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index f15293bd7974..509243d89a32 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -19,24 +19,25 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#include <linux/kernel.h>
+#include <linux/io.h>
-#include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
-#include <linux/io.h>
 #include <linux/irq.h>
-#include <linux/sched.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
 #include <asm/sizes.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/leds.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
+#include <mach/hardware.h>
+static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
+                  *clk_tint, *clk_spi;
+static unsigned long latch;
 /*
 * This maps the generic CLPS711x registers
 */
@@ -166,8 +167,8 @@ void __init clps711x_init_irq(void)
 static unsigned long clps711x_gettimeoffset(void)
 {
        unsigned long hwticks;
-        hwticks = LATCH - (clps_readl(TC2D) & 0xffff);  /* since last underflow */
+        hwticks = latch - (clps_readl(TC2D) & 0xffff);
-        return (hwticks * (tick_nsec / 1000)) / LATCH;
+        return (hwticks * (tick_nsec / 1000)) / latch;
 }
 /*
@@ -185,15 +186,71 @@ static struct irqaction clps711x_timer_irq = {
        .handler        = p720t_timer_interrupt,
 };
+static void add_fixed_clk(struct clk *clk, const char *name, int rate)
+{
+        clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+        clk_register_clkdev(clk, name, NULL);
+}
 static void __init clps711x_timer_init(void)
 {
-        unsigned int syscon;
+        int osc, ext, pll, cpu, bus, timl, timh, uart, spi;
+        u32 tmp;
+        osc = 3686400;
+        ext = 13000000;
+        tmp = clps_readl(PLLR) >> 24;
+        if (tmp)
+                pll = (osc * tmp) / 2;
+        else
+                pll = 73728000; /* Default value */
+        tmp = clps_readl(SYSFLG2);
+        if (tmp & SYSFLG2_CKMODE) {
+                cpu = ext;
+                bus = cpu;
+                spi = 135400;
+        } else {
+                cpu = pll;
+                if (cpu >= 36864000)
+                        bus = cpu / 2;
+                else
+                        bus = 36864000 / 2;
+                spi = cpu / 576;
+        }
+        uart = bus / 10;
+        if (tmp & SYSFLG2_CKMODE) {
+                tmp = clps_readl(SYSCON2);
+                if (tmp & SYSCON2_OSTB)
+                        timh = ext / 26;
+                else
+                        timh = 541440;
+        } else
+                timh = cpu / 144;
+        timl = timh / 256;
+        /* All clocks are fixed */
+        add_fixed_clk(clk_pll, "pll", pll);
+        add_fixed_clk(clk_bus, "bus", bus);
+        add_fixed_clk(clk_uart, "uart", uart);
+        add_fixed_clk(clk_timerl, "timer_lf", timl);
+        add_fixed_clk(clk_timerh, "timer_hf", timh);
+        add_fixed_clk(clk_tint, "tint", 64);
+        add_fixed_clk(clk_spi, "spi", spi);
+        pr_info("CPU frequency set at %i Hz.\n", cpu);
+        latch = (timh + HZ / 2) / HZ;
-        syscon = clps_readl(SYSCON1);
+        tmp = clps_readl(SYSCON1);
-        syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
+        tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
-        clps_writel(syscon, SYSCON1);
+        clps_writel(tmp, SYSCON1);
-        clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
+        clps_writel(latch - 1, TC2D);
        setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 1dd806f2847e..c82e21ca49c7 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -31,8 +31,8 @@
 #define PBDDR           (0x0041)
 #define PCDDR           (0x0042)
 #define PDDDR           (0x0043)
-#define PEDR            (0x0080)
+#define PEDR            (0x0083)
-#define PEDDR           (0x00c0)
+#define PEDDR           (0x00c3)
 #define SYSCON1         (0x0100)
 #define SYSFLG1         (0x0140)
 #define MEMCFG1         (0x0180)
@@ -77,7 +77,7 @@
 #define KBDEOI          (0x1700)
 #define DAIR            (0x2000)
-#define DAIR0           (0x2040)
+#define DAIDR0          (0x2040)
 #define DAIDR1          (0x2080)
 #define DAIDR2          (0x20c0)
 #define DAISR           (0x2100)
@@ -191,8 +191,7 @@
 #define UBRLCR_WRDLEN8          (3 << 17)
 #define UBRLCR_WRDLEN_MASK      (3 << 17)
-#define SYNCIO_FRMLEN(x)        (((x) & 0x3f) << 7)
+#define SYNCIO_FRMLEN(x)        (((x) & 0x1f) << 8)
-#define SYNCIO_CFGLEN(x)        ((x) & 0x7f)
 #define SYNCIO_SMCKEN           (1 << 13)
 #define SYNCIO_TXFRMEN          (1 << 14)
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S
index 118b3d930573..cb3684f8dae0 100644
--- a/arch/arm/mach-clps711x/include/mach/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S
@@ -28,17 +28,11 @@
                .endm
                .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #0x0140]     @ SYSFLGx
-                tst     \rd, #1 << 11           @ UBUSYx
-                bne     1001b
                .endm
                .macro  busyuart,rd,rx
-                tst     \rx, #0x1000            @ UART2 does not have CTS here
-                bne     1002f
 1001:           ldr     \rd, [\rx, #0x0140]     @ SYSFLGx
-                tst     \rd, #1 << 8            @ CTS
+                tst     \rd, #1 << 11           @ UBUSYx
                bne     1001b
-1002:
                .endm
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 13a64fcd7dd1..8497775d6ee5 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -116,7 +116,6 @@
 #endif /* CONFIG_ARCH_EDB7211 */
 /*
 * Relevant bits in port D, which controls power to the various parts of
 * the LCD on the EDB7211.
@@ -125,51 +124,4 @@
 #define EDB_PD2_LCDEN           (1<<2)
 #define EDB_PD3_LCDBL           (1<<3)
-#if defined (CONFIG_ARCH_CEIVA)
-/*
- * The two flash banks are wired to chip selects 0 and 1. This is the mapping
- * for them.
- *
- * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
- * in jumpered boot mode.
- */
-#define CEIVA_PHYS_FLASH1       CS0_PHYS_BASE   /* physical */
-#define CEIVA_PHYS_FLASH2       CS1_PHYS_BASE   /* physical */
-#define CEIVA_VIRT_FLASH1       (0xfa000000)    /* virtual */
-#define CEIVA_VIRT_FLASH2       (0xfb000000)    /* virtual */
-#define CEIVA_FLASH_SIZE        0x100000
-#define CEIVA_FLASH_WIDTH       2
-/*
- * SED1355 LCD controller
- */
-#define CEIVA_PHYS_SED1355      CS2_PHYS_BASE
-#define CEIVA_VIRT_SED1355      (0xfc000000)
-/*
- * Relevant bits in port D, which controls power to the various parts of
- * the LCD on the Ceiva Photo Max, and reset to the LCD controller.
- */
-// Reset line to SED1355 (must be high to operate)
-#define CEIVA_PD1_LCDRST        (1<<1)
-// LCD panel enable (set to one, to enable LCD)
-#define CEIVA_PD4_LCDEN         (1<<4)
-// Backlight (set to one, to turn on backlight
-#define CEIVA_PD5_LCDBL         (1<<5)
-/*
- * Relevant bits in port B, which report the status of the buttons.
- */
-// White button
-#define CEIVA_PB4_WHT_BTN       (1<<4)
-// Black button
-#define CEIVA_PB0_BLK_BTN       (1<<0)
-#endif // #if defined (CONFIG_ARCH_CEIVA)
 #endif
diff --git a/arch/arm/mach-clps711x/include/mach/timex.h b/arch/arm/mach-clps711x/include/mach/timex.h
index ac8823ccff93..de6fd192d1c3 100644
--- a/arch/arm/mach-clps711x/include/mach/timex.h
+++ b/arch/arm/mach-clps711x/include/mach/timex.h
@@ -1,23 +1,2 @@
-/*
+/* Bogus value */
- *  arch/arm/mach-clps711x/include/mach/timex.h
- *
- *  Prospector 720T architecture timex specifications
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
 #define CLOCK_TICK_RATE 512000
diff --git a/arch/arm/mach-clps711x/p720t-leds.c b/arch/arm/mach-clps711x/p720t-leds.c
deleted file mode 100644
index bbc449fbe14a..000000000000
--- a/arch/arm/mach-clps711x/p720t-leds.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/leds.c
- *
- *  Integrator LED control routines
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-static void p720t_leds_event(led_event_t ledevt)
-{
-        unsigned long flags;
-        u32 pddr;
-        local_irq_save(flags);
-        switch(ledevt) {
-        case led_idle_start:
-                break;
-        case led_idle_end:
-                break;
-        case led_timer:
-                pddr = clps_readb(PDDR);
-                clps_writeb(pddr ^ 1, PDDR);
-                break;
-        default:
-                break;
-        }
-        local_irq_restore(flags);
-}
-static int __init leds_init(void)
-{
-        if (machine_is_p720t())
-                leds_event = p720t_leds_event;
-        return 0;
-}
-arch_initcall(leds_init);
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index f266d90b9efc..b752b586fc2f 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -23,6 +23,8 @@
 #include <linux/string.h>
 #include <linux/mm.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 #include <mach/hardware.h>
 #include <asm/pgtable.h>
@@ -34,6 +36,8 @@
 #include <asm/mach/map.h>
 #include <mach/syspld.h>
+#include <asm/hardware/clps7111.h>
 #include "common.h"
 /*
@@ -107,6 +111,64 @@ static void __init p720t_init_early(void)
        }
 }
+/*
+ * LED controled by CPLD
+ */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+static void p720t_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
+{
+        u8 reg = clps_readb(PDDR);
+        if (b != LED_OFF)
+                reg |= 0x1;
+        else
+                reg &= ~0x1;
+        clps_writeb(reg, PDDR);
+}
+static enum led_brightness p720t_led_get(struct led_classdev *cdev)
+{
+        u8 reg = clps_readb(PDDR);
+        return (reg & 0x1) ? LED_FULL : LED_OFF;
+}
+static int __init p720t_leds_init(void)
+{
+        struct led_classdev *cdev;
+        int ret;
+        if (!machine_is_p720t())
+                return -ENODEV;
+        cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
+        if (!cdev)
+                return -ENOMEM;
+        cdev->name = "p720t:0";
+        cdev->brightness_set = p720t_led_set;
+        cdev->brightness_get = p720t_led_get;
+        cdev->default_trigger = "heartbeat";
+        ret = led_classdev_register(NULL, cdev);
+        if (ret < 0) {
+                kfree(cdev);
+                return ret;
+        }
+        return 0;
+}
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(p720t_leds_init);
+#endif
 MACHINE_START(P720T, "ARM-Prospector720T")
        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
        .atag_offset    = 0x100,
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index ab99c3c3b752..026b4b277ae5 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -186,6 +186,13 @@ config DA850_UI_RMII
          NOTE: Please take care while choosing this option, MII PHY will
          not be functional if RMII mode is selected.
+config DA850_UI_SD_VIDEO_PORT
+        bool "Video Port Interface"
+        help
+          Say Y if you want to use Video Port Interface (VPIF) on the
+          DA850/OMAP-L138 EVM. The Video decoders/encoders are found on the
+          UI daughter card that is supplied with the EVM.
 endchoice
 config DA850_WL12XX
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c
index 1ce70a91f2e9..f091a9010c2f 100644
--- a/arch/arm/mach-davinci/aemif.c
+++ b/arch/arm/mach-davinci/aemif.c
@@ -15,7 +15,7 @@
 #include <linux/module.h>
 #include <linux/time.h>
-#include <mach/aemif.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
 /* Timing value configuration */
diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h
new file mode 100644
index 000000000000..d9b2acd12393
--- /dev/null
+++ b/arch/arm/mach-davinci/asp.h
@@ -0,0 +1,49 @@
+/*
+ * TI DaVinci Audio definitions
+ */
+#ifndef __ASM_ARCH_DAVINCI_ASP_H
+#define __ASM_ARCH_DAVINCI_ASP_H
+/* Bases of dm644x and dm355 register banks */
+#define DAVINCI_ASP0_BASE       0x01E02000
+#define DAVINCI_ASP1_BASE       0x01E04000
+/* Bases of dm365 register banks */
+#define DAVINCI_DM365_ASP0_BASE 0x01D02000
+/* Bases of dm646x register banks */
+#define DAVINCI_DM646X_MCASP0_REG_BASE          0x01D01000
+#define DAVINCI_DM646X_MCASP1_REG_BASE          0x01D01800
+/* Bases of da850/da830 McASP0  register banks */
+#define DAVINCI_DA8XX_MCASP0_REG_BASE   0x01D00000
+/* Bases of da830 McASP1 register banks */
+#define DAVINCI_DA830_MCASP1_REG_BASE   0x01D04000
+/* EDMA channels of dm644x and dm355 */
+#define DAVINCI_DMA_ASP0_TX     2
+#define DAVINCI_DMA_ASP0_RX     3
+#define DAVINCI_DMA_ASP1_TX     8
+#define DAVINCI_DMA_ASP1_RX     9
+/* EDMA channels of dm646x */
+#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0        6
+#define DAVINCI_DM646X_DMA_MCASP0_AREVT0        9
+#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1        12
+/* EDMA channels of da850/da830 McASP0 */
+#define DAVINCI_DA8XX_DMA_MCASP0_AREVT  0
+#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT  1
+/* EDMA channels of da830 McASP1 */
+#define DAVINCI_DA830_DMA_MCASP1_AREVT  2
+#define DAVINCI_DA830_DMA_MCASP1_AXEVT  3
+/* Interrupts */
+#define DAVINCI_ASP0_RX_INT     IRQ_MBRINT
+#define DAVINCI_ASP0_TX_INT     IRQ_MBXINT
+#define DAVINCI_ASP1_RX_INT     IRQ_MBRINT
+#define DAVINCI_ASP1_TX_INT     IRQ_MBXINT
+#endif /* __ASM_ARCH_DAVINCI_ASP_H */
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 0031864e7f11..95b5e102ceb1 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -28,11 +28,11 @@
 #include <mach/cp_intc.h>
 #include <mach/mux.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-davinci.h>
 #include <mach/da8xx.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-davinci.h>
-#include <mach/aemif.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
-#include <mach/spi.h>
+#include <linux/platform_data/spi-davinci.h>
 #define DA830_EVM_PHY_ID                ""
 /*
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 0149fb453be3..32ee3f895967 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -40,10 +40,13 @@
 #include <mach/cp_intc.h>
 #include <mach/da8xx.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-davinci.h>
 #include <mach/mux.h>
-#include <mach/aemif.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
-#include <mach/spi.h>
+#include <linux/platform_data/spi-davinci.h>
+#include <media/tvp514x.h>
+#include <media/adv7343.h>
 #define DA850_EVM_PHY_ID                "davinci_mdio-0:00"
 #define DA850_LCD_PWR_PIN               GPIO_TO_PIN(2, 8)
@@ -452,6 +455,15 @@ static void da850_evm_ui_keys_init(unsigned gpio)
        }
 }
+#ifdef CONFIG_DA850_UI_SD_VIDEO_PORT
+static inline void da850_evm_setup_video_port(int video_sel)
+{
+        gpio_set_value_cansleep(video_sel, 0);
+}
+#else
+static inline void da850_evm_setup_video_port(int video_sel) { }
+#endif
 static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
                                                unsigned ngpio, void *c)
 {
@@ -497,6 +509,8 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
        da850_evm_setup_emac_rmii(sel_a);
+        da850_evm_setup_video_port(sel_c);
        return 0;
 exp_setup_keys_fail:
@@ -1149,6 +1163,169 @@ static __init int da850_evm_init_cpufreq(void)
 static __init int da850_evm_init_cpufreq(void) { return 0; }
 #endif
+#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)
+#define TVP5147_CH0             "tvp514x-0"
+#define TVP5147_CH1             "tvp514x-1"
+/* VPIF capture configuration */
+static struct tvp514x_platform_data tvp5146_pdata = {
+                .clk_polarity = 0,
+                .hs_polarity  = 1,
+                .vs_polarity  = 1,
+};
+#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
+static const struct vpif_input da850_ch0_inputs[] = {
+        {
+                .input = {
+                        .index = 0,
+                        .name  = "Composite",
+                        .type  = V4L2_INPUT_TYPE_CAMERA,
+                        .capabilities = V4L2_IN_CAP_STD,
+                        .std   = TVP514X_STD_ALL,
+                },
+                .input_route = INPUT_CVBS_VI2B,
+                .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
+                .subdev_name = TVP5147_CH0,
+        },
+};
+static const struct vpif_input da850_ch1_inputs[] = {
+        {
+                .input = {
+                        .index = 0,
+                        .name  = "S-Video",
+                        .type  = V4L2_INPUT_TYPE_CAMERA,
+                        .capabilities = V4L2_IN_CAP_STD,
+                        .std   = TVP514X_STD_ALL,
+                },
+                .input_route = INPUT_SVIDEO_VI2C_VI1C,
+                .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
+                .subdev_name = TVP5147_CH1,
+        },
+};
+static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = {
+        {
+                .name = TVP5147_CH0,
+                .board_info = {
+                        I2C_BOARD_INFO("tvp5146", 0x5d),
+                        .platform_data = &tvp5146_pdata,
+                },
+        },
+        {
+                .name = TVP5147_CH1,
+                .board_info = {
+                        I2C_BOARD_INFO("tvp5146", 0x5c),
+                        .platform_data = &tvp5146_pdata,
+                },
+        },
+};
+static struct vpif_capture_config da850_vpif_capture_config = {
+        .subdev_info = da850_vpif_capture_sdev_info,
+        .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info),
+        .chan_config[0] = {
+                .inputs = da850_ch0_inputs,
+                .input_count = ARRAY_SIZE(da850_ch0_inputs),
+                .vpif_if = {
+                        .if_type = VPIF_IF_BT656,
+                        .hd_pol  = 1,
+                        .vd_pol  = 1,
+                        .fid_pol = 0,
+                },
+        },
+        .chan_config[1] = {
+                .inputs = da850_ch1_inputs,
+                .input_count = ARRAY_SIZE(da850_ch1_inputs),
+                .vpif_if = {
+                        .if_type = VPIF_IF_BT656,
+                        .hd_pol  = 1,
+                        .vd_pol  = 1,
+                        .fid_pol = 0,
+                },
+        },
+        .card_name = "DA850/OMAP-L138 Video Capture",
+};
+/* VPIF display configuration */
+static struct vpif_subdev_info da850_vpif_subdev[] = {
+        {
+                .name = "adv7343",
+                .board_info = {
+                        I2C_BOARD_INFO("adv7343", 0x2a),
+                },
+        },
+};
+static const struct vpif_output da850_ch0_outputs[] = {
+        {
+                .output = {
+                        .index = 0,
+                        .name = "Composite",
+                        .type = V4L2_OUTPUT_TYPE_ANALOG,
+                        .capabilities = V4L2_OUT_CAP_STD,
+                        .std = V4L2_STD_ALL,
+                },
+                .subdev_name = "adv7343",
+                .output_route = ADV7343_COMPOSITE_ID,
+        },
+        {
+                .output = {
+                        .index = 1,
+                        .name = "S-Video",
+                        .type = V4L2_OUTPUT_TYPE_ANALOG,
+                        .capabilities = V4L2_OUT_CAP_STD,
+                        .std = V4L2_STD_ALL,
+                },
+                .subdev_name = "adv7343",
+                .output_route = ADV7343_SVIDEO_ID,
+        },
+};
+static struct vpif_display_config da850_vpif_display_config = {
+        .subdevinfo   = da850_vpif_subdev,
+        .subdev_count = ARRAY_SIZE(da850_vpif_subdev),
+        .chan_config[0] = {
+                .outputs = da850_ch0_outputs,
+                .output_count = ARRAY_SIZE(da850_ch0_outputs),
+        },
+        .card_name    = "DA850/OMAP-L138 Video Display",
+};
+static __init void da850_vpif_init(void)
+{
+        int ret;
+        ret = da850_register_vpif();
+        if (ret)
+                pr_warn("da850_evm_init: VPIF setup failed: %d\n", ret);
+        ret = davinci_cfg_reg_list(da850_vpif_capture_pins);
+        if (ret)
+                pr_warn("da850_evm_init: VPIF capture mux setup failed: %d\n",
+                        ret);
+        ret = da850_register_vpif_capture(&da850_vpif_capture_config);
+        if (ret)
+                pr_warn("da850_evm_init: VPIF capture setup failed: %d\n", ret);
+        ret = davinci_cfg_reg_list(da850_vpif_display_pins);
+        if (ret)
+                pr_warn("da850_evm_init: VPIF display mux setup failed: %d\n",
+                        ret);
+        ret = da850_register_vpif_display(&da850_vpif_display_config);
+        if (ret)
+                pr_warn("da850_evm_init: VPIF display setup failed: %d\n", ret);
+}
+#else
+static __init void da850_vpif_init(void) {}
+#endif
 #ifdef CONFIG_DA850_WL12XX
 static void wl12xx_set_power(int index, bool power_on)
@@ -1375,6 +1552,8 @@ static __init void da850_evm_init(void)
                pr_warning("da850_evm_init: suspend registration failed: %d\n",
                                ret);
+        da850_vpif_init();
        ret = da8xx_register_spi(1, da850evm_spi_info,
                                 ARRAY_SIZE(da850evm_spi_info));
        if (ret)
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 1c7b1f46a8f3..88ebea89abdf 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -26,11 +26,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 #include <mach/serial.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-davinci.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-davinci.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-davinci.h>
 #include "davinci.h"
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 8e7703213b08..2f88103c6459 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -23,11 +23,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 #include <mach/serial.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-davinci.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-davinci.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-davinci.h>
 #include "davinci.h"
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 688a9c556dc9..1b4a8adcfdc9 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -33,11 +33,11 @@
 #include <mach/mux.h>
 #include <mach/common.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 #include <mach/serial.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-davinci.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-davinci.h>
-#include <mach/keyscan.h>
+#include <linux/platform_data/keyscan-davinci.h>
 #include <media/tvp514x.h>
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index d34ed55912b2..f22572cee49d 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -23,6 +23,7 @@
 #include <linux/phy.h>
 #include <linux/clk.h>
 #include <linux/videodev2.h>
+#include <linux/v4l2-dv-timings.h>
 #include <linux/export.h>
 #include <media/tvp514x.h>
@@ -31,13 +32,13 @@
 #include <asm/mach/arch.h>
 #include <mach/common.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 #include <mach/serial.h>
 #include <mach/mux.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-davinci.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-davinci.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-davinci.h>
-#include <mach/aemif.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
 #include "davinci.h"
@@ -620,7 +621,7 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
        {
                .name           = "ntsc",
                .timings_type   = VPBE_ENC_STD,
-                .timings        = {V4L2_STD_525_60},
+                .std_id         = V4L2_STD_525_60,
                .interlaced     = 1,
                .xres           = 720,
                .yres           = 480,
@@ -632,7 +633,7 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
        {
                .name           = "pal",
                .timings_type   = VPBE_ENC_STD,
-                .timings        = {V4L2_STD_625_50},
+                .std_id         = V4L2_STD_625_50,
                .interlaced     = 1,
                .xres           = 720,
                .yres           = 576,
@@ -647,8 +648,8 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
 static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
        {
                .name           = "480p59_94",
-                .timings_type   = VPBE_ENC_DV_PRESET,
+                .timings_type   = VPBE_ENC_CUSTOM_TIMINGS,
-                .timings        = {V4L2_DV_480P59_94},
+                .dv_timings     = V4L2_DV_BT_CEA_720X480P59_94,
                .interlaced     = 0,
                .xres           = 720,
                .yres           = 480,
@@ -659,8 +660,8 @@ static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
        },
        {
                .name           = "576p50",
-                .timings_type   = VPBE_ENC_DV_PRESET,
+                .timings_type   = VPBE_ENC_CUSTOM_TIMINGS,
-                .timings        = {V4L2_DV_576P50},
+                .dv_timings     = V4L2_DV_BT_CEA_720X576P50,
                .interlaced     = 0,
                .xres           = 720,
                .yres           = 576,
@@ -698,7 +699,7 @@ static struct vpbe_output dm644xevm_vpbe_outputs[] = {
                        .index          = 1,
                        .name           = "Component",
                        .type           = V4L2_OUTPUT_TYPE_ANALOG,
-                        .capabilities   = V4L2_OUT_CAP_PRESETS,
+                        .capabilities   = V4L2_OUT_CAP_DV_TIMINGS,
                },
                .subdev_name    = VPBE_VENC_SUBDEV_NAME,
                .default_mode   = "480p59_94",
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 958679a20e13..1dbf85beed1b 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -26,6 +26,7 @@
 #include <linux/i2c/pcf857x.h>
 #include <media/tvp514x.h>
+#include <media/adv7343.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -38,11 +39,11 @@
 #include <mach/common.h>
 #include <mach/serial.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-davinci.h>
 #include <mach/clock.h>
 #include <mach/cdce949.h>
-#include <mach/aemif.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
 #include "davinci.h"
 #include "clock.h"
@@ -496,18 +497,49 @@ static struct vpif_subdev_info dm646x_vpif_subdev[] = {
        },
 };
-static const char *output[] = {
+static const struct vpif_output dm6467_ch0_outputs[] = {
-        "Composite",
+        {
-        "Component",
+                .output = {
-        "S-Video",
+                        .index = 0,
+                        .name = "Composite",
+                        .type = V4L2_OUTPUT_TYPE_ANALOG,
+                        .capabilities = V4L2_OUT_CAP_STD,
+                        .std = V4L2_STD_ALL,
+                },
+                .subdev_name = "adv7343",
+                .output_route = ADV7343_COMPOSITE_ID,
+        },
+        {
+                .output = {
+                        .index = 1,
+                        .name = "Component",
+                        .type = V4L2_OUTPUT_TYPE_ANALOG,
+                        .capabilities = V4L2_OUT_CAP_CUSTOM_TIMINGS,
+                },
+                .subdev_name = "adv7343",
+                .output_route = ADV7343_COMPONENT_ID,
+        },
+        {
+                .output = {
+                        .index = 2,
+                        .name = "S-Video",
+                        .type = V4L2_OUTPUT_TYPE_ANALOG,
+                        .capabilities = V4L2_OUT_CAP_STD,
+                        .std = V4L2_STD_ALL,
+                },
+                .subdev_name = "adv7343",
+                .output_route = ADV7343_SVIDEO_ID,
+        },
 };
 static struct vpif_display_config dm646x_vpif_display_config = {
        .set_clock      = set_vpif_clock,
        .subdevinfo     = dm646x_vpif_subdev,
        .subdev_count   = ARRAY_SIZE(dm646x_vpif_subdev),
-        .output         = output,
+        .chan_config[0] = {
-        .output_count   = ARRAY_SIZE(output),
+                .outputs = dm6467_ch0_outputs,
+                .output_count = ARRAY_SIZE(dm6467_ch0_outputs),
+        },
        .card_name      = "DM646x EVM",
 };
@@ -601,15 +633,6 @@ static struct vpif_subdev_info vpif_capture_sdev_info[] = {
                        I2C_BOARD_INFO("tvp5146", 0x5d),
                        .platform_data = &tvp5146_pdata,
                },
-                .input = INPUT_CVBS_VI2B,
-                .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
-                .can_route = 1,
-                .vpif_if = {
-                        .if_type = VPIF_IF_BT656,
-                        .hd_pol = 1,
-                        .vd_pol = 1,
-                        .fid_pol = 0,
-                },
        },
        {
                .name   = TVP5147_CH1,
@@ -617,15 +640,6 @@ static struct vpif_subdev_info vpif_capture_sdev_info[] = {
                        I2C_BOARD_INFO("tvp5146", 0x5c),
                        .platform_data = &tvp5146_pdata,
                },
-                .input = INPUT_SVIDEO_VI2C_VI1C,
-                .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
-                .can_route = 1,
-                .vpif_if = {
-                        .if_type = VPIF_IF_BT656,
-                        .hd_pol = 1,
-                        .vd_pol = 1,
-                        .fid_pol = 0,
-                },
        },
 };
@@ -635,9 +649,12 @@ static const struct vpif_input dm6467_ch0_inputs[] = {
                        .index = 0,
                        .name = "Composite",
                        .type = V4L2_INPUT_TYPE_CAMERA,
+                        .capabilities = V4L2_IN_CAP_STD,
                        .std = TVP514X_STD_ALL,
                },
                .subdev_name = TVP5147_CH0,
+                .input_route = INPUT_CVBS_VI2B,
+                .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
        },
 };
@@ -647,9 +664,12 @@ static const struct vpif_input dm6467_ch1_inputs[] = {
                        .index = 0,
                        .name = "S-Video",
                        .type = V4L2_INPUT_TYPE_CAMERA,
+                        .capabilities = V4L2_IN_CAP_STD,
                        .std = TVP514X_STD_ALL,
                },
                .subdev_name = TVP5147_CH1,
+                .input_route = INPUT_SVIDEO_VI2C_VI1C,
+                .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
        },
 };
@@ -661,10 +681,22 @@ static struct vpif_capture_config dm646x_vpif_capture_cfg = {
        .chan_config[0] = {
                .inputs = dm6467_ch0_inputs,
                .input_count = ARRAY_SIZE(dm6467_ch0_inputs),
+                .vpif_if = {
+                        .if_type = VPIF_IF_BT656,
+                        .hd_pol = 1,
+                        .vd_pol = 1,
+                        .fid_pol = 0,
+                },
        },
        .chan_config[1] = {
                .inputs = dm6467_ch1_inputs,
                .input_count = ARRAY_SIZE(dm6467_ch1_inputs),
+                .vpif_if = {
+                        .if_type = VPIF_IF_BT656,
+                        .hd_pol = 1,
+                        .vd_pol = 1,
+                        .fid_pol = 0,
+                },
        },
 };
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index beecde3a1d2f..43e4a0d663fa 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -26,9 +26,9 @@
 #include <mach/common.h>
 #include <mach/cp_intc.h>
 #include <mach/da8xx.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-davinci.h>
 #include <mach/mux.h>
-#include <mach/spi.h>
+#include <linux/platform_data/spi-davinci.h>
 #define MITYOMAPL138_PHY_ID             ""
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index f6b9fc70161b..144bf31d68dd 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -31,12 +31,12 @@
 #include <asm/mach/arch.h>
 #include <mach/common.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 #include <mach/serial.h>
 #include <mach/mux.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-davinci.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-davinci.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-davinci.h>
 #include "davinci.h"
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 9078acf94bac..6957787fa7f3 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -36,10 +36,10 @@
 #include <asm/mach/flash.h>
 #include <mach/common.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 #include <mach/serial.h>
 #include <mach/mux.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-davinci.h>
 #include "davinci.h"
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index ac4e003ad863..be3099733b1f 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -88,7 +88,7 @@ static struct davinci_mmc_config mmc_config = {
        .version        = MMC_CTLR_VERSION_1,
 };
-static const short sdio1_pins[] __initdata = {
+static const short sdio1_pins[] __initconst = {
        TNETV107X_SDIO1_CLK_1,          TNETV107X_SDIO1_CMD_1,
        TNETV107X_SDIO1_DATA0_1,        TNETV107X_SDIO1_DATA1_1,
        TNETV107X_SDIO1_DATA2_1,        TNETV107X_SDIO1_DATA3_1,
@@ -96,12 +96,12 @@ static const short sdio1_pins[] __initdata = {
        -1
 };
-static const short uart1_pins[] __initdata = {
+static const short uart1_pins[] __initconst = {
        TNETV107X_UART1_RD,             TNETV107X_UART1_TD,
        -1
 };
-static const short ssp_pins[] __initdata = {
+static const short ssp_pins[] __initconst = {
        TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
        TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
        TNETV107X_SSP1_3, -1
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index deee5c2da754..510648e0394b 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -838,7 +838,7 @@ static const struct mux_config da830_pins[] = {
 #endif
 };
-const short da830_emif25_pins[] __initdata = {
+const short da830_emif25_pins[] __initconst = {
        DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
        DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
        DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11,
@@ -853,19 +853,19 @@ const short da830_emif25_pins[] __initdata = {
        -1
 };
-const short da830_spi0_pins[] __initdata = {
+const short da830_spi0_pins[] __initconst = {
        DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA,
        DA830_NSPI0_SCS_0,
        -1
 };
-const short da830_spi1_pins[] __initdata = {
+const short da830_spi1_pins[] __initconst = {
        DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA,
        DA830_NSPI1_SCS_0,
        -1
 };
-const short da830_mmc_sd_pins[] __initdata = {
+const short da830_mmc_sd_pins[] __initconst = {
        DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
        DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
        DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
@@ -873,32 +873,32 @@ const short da830_mmc_sd_pins[] __initdata = {
        -1
 };
-const short da830_uart0_pins[] __initdata = {
+const short da830_uart0_pins[] __initconst = {
        DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD,
        -1
 };
-const short da830_uart1_pins[] __initdata = {
+const short da830_uart1_pins[] __initconst = {
        DA830_UART1_RXD, DA830_UART1_TXD,
        -1
 };
-const short da830_uart2_pins[] __initdata = {
+const short da830_uart2_pins[] __initconst = {
        DA830_UART2_RXD, DA830_UART2_TXD,
        -1
 };
-const short da830_usb20_pins[] __initdata = {
+const short da830_usb20_pins[] __initconst = {
        DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN,
        -1
 };
-const short da830_usb11_pins[] __initdata = {
+const short da830_usb11_pins[] __initconst = {
        DA830_USB_REFCLKIN,
        -1
 };
-const short da830_uhpi_pins[] __initdata = {
+const short da830_uhpi_pins[] __initconst = {
        DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3,
        DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7,
        DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11,
@@ -909,14 +909,14 @@ const short da830_uhpi_pins[] __initdata = {
        -1
 };
-const short da830_cpgmac_pins[] __initdata = {
+const short da830_cpgmac_pins[] __initconst = {
        DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV,
        DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK,
        DA830_MDIO_D,
        -1
 };
-const short da830_emif3c_pins[] __initdata = {
+const short da830_emif3c_pins[] __initconst = {
        DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0,
        DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1,
        DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2,
@@ -935,7 +935,7 @@ const short da830_emif3c_pins[] __initdata = {
        -1
 };
-const short da830_mcasp0_pins[] __initdata = {
+const short da830_mcasp0_pins[] __initconst = {
        DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0,
        DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0,
        DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3,
@@ -945,7 +945,7 @@ const short da830_mcasp0_pins[] __initdata = {
        -1
 };
-const short da830_mcasp1_pins[] __initdata = {
+const short da830_mcasp1_pins[] __initconst = {
        DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1,
        DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1,
        DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3,
@@ -954,24 +954,24 @@ const short da830_mcasp1_pins[] __initdata = {
        -1
 };
-const short da830_mcasp2_pins[] __initdata = {
+const short da830_mcasp2_pins[] __initconst = {
        DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2,
        DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2,
        DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3,
        -1
 };
-const short da830_i2c0_pins[] __initdata = {
+const short da830_i2c0_pins[] __initconst = {
        DA830_I2C0_SDA, DA830_I2C0_SCL,
        -1
 };
-const short da830_i2c1_pins[] __initdata = {
+const short da830_i2c1_pins[] __initconst = {
        DA830_I2C1_SCL, DA830_I2C1_SDA,
        -1
 };
-const short da830_lcdcntl_pins[] __initdata = {
+const short da830_lcdcntl_pins[] __initconst = {
        DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3,
        DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7,
        DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11,
@@ -981,34 +981,34 @@ const short da830_lcdcntl_pins[] __initdata = {
        -1
 };
-const short da830_pwm_pins[] __initdata = {
+const short da830_pwm_pins[] __initconst = {
        DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A,
        DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ,
        DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A,
        -1
 };
-const short da830_ecap0_pins[] __initdata = {
+const short da830_ecap0_pins[] __initconst = {
        DA830_ECAP0_APWM0,
        -1
 };
-const short da830_ecap1_pins[] __initdata = {
+const short da830_ecap1_pins[] __initconst = {
        DA830_ECAP1_APWM1,
        -1
 };
-const short da830_ecap2_pins[] __initdata = {
+const short da830_ecap2_pins[] __initconst = {
        DA830_ECAP2_APWM2,
        -1
 };
-const short da830_eqep0_pins[] __initdata = {
+const short da830_eqep0_pins[] __initconst = {
        DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B,
        -1
 };
-const short da830_eqep1_pins[] __initdata = {
+const short da830_eqep1_pins[] __initconst = {
        DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B,
        -1
 };
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index b44dc844e15e..b90c172d5541 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -347,6 +347,13 @@ static struct clk spi1_clk = {
        .flags          = DA850_CLK_ASYNC3,
 };
+static struct clk vpif_clk = {
+        .name           = "vpif",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA850_LPSC1_VPIF,
+        .gpsc           = 1,
+};
 static struct clk sata_clk = {
        .name           = "sata",
        .parent         = &pll0_sysclk2,
@@ -397,6 +404,7 @@ static struct clk_lookup da850_clks[] = {
        CLK(NULL,               "usb20",        &usb20_clk),
        CLK("spi_davinci.0",    NULL,           &spi0_clk),
        CLK("spi_davinci.1",    NULL,           &spi1_clk),
+        CLK("vpif",             NULL,           &vpif_clk),
        CLK("ahci",             NULL,           &sata_clk),
        CLK(NULL,               NULL,           NULL),
 };
@@ -573,20 +581,60 @@ static const struct mux_config da850_pins[] = {
        MUX_CFG(DA850, GPIO6_10,        13,     20,     15,     8,      false)
        MUX_CFG(DA850, GPIO6_13,        13,     8,      15,     8,      false)
        MUX_CFG(DA850, RTC_ALARM,       0,      28,     15,     2,      false)
+        /* VPIF Capture */
+        MUX_CFG(DA850, VPIF_DIN0,       15,     4,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN1,       15,     0,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN2,       14,     28,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN3,       14,     24,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN4,       14,     20,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN5,       14,     16,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN6,       14,     12,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN7,       14,     8,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN8,       16,     4,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN9,       16,     0,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN10,      15,     28,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN11,      15,     24,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN12,      15,     20,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN13,      15,     16,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN14,      15,     12,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DIN15,      15,     8,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_CLKIN0,     14,     0,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_CLKIN1,     14,     4,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_CLKIN2,     19,     8,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_CLKIN3,     19,     16,     15,     1,      false)
+        /* VPIF Display */
+        MUX_CFG(DA850, VPIF_DOUT0,      17,     4,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT1,      17,     0,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT2,      16,     28,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT3,      16,     24,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT4,      16,     20,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT5,      16,     16,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT6,      16,     12,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT7,      16,     8,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT8,      18,     4,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT9,      18,     0,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT10,     17,     28,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT11,     17,     24,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT12,     17,     20,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT13,     17,     16,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT14,     17,     12,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_DOUT15,     17,     8,      15,     1,      false)
+        MUX_CFG(DA850, VPIF_CLKO2,      19,     12,     15,     1,      false)
+        MUX_CFG(DA850, VPIF_CLKO3,      19,     20,     15,     1,      false)
 #endif
 };
-const short da850_i2c0_pins[] __initdata = {
+const short da850_i2c0_pins[] __initconst = {
        DA850_I2C0_SDA, DA850_I2C0_SCL,
        -1
 };
-const short da850_i2c1_pins[] __initdata = {
+const short da850_i2c1_pins[] __initconst = {
        DA850_I2C1_SCL, DA850_I2C1_SDA,
        -1
 };
-const short da850_lcdcntl_pins[] __initdata = {
+const short da850_lcdcntl_pins[] __initconst = {
        DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
        DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
        DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
@@ -595,6 +643,26 @@ const short da850_lcdcntl_pins[] __initdata = {
        -1
 };
+const short da850_vpif_capture_pins[] __initdata = {
+        DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
+        DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
+        DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
+        DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
+        DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
+        DA850_VPIF_CLKIN3,
+        -1
+};
+const short da850_vpif_display_pins[] __initdata = {
+        DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
+        DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
+        DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
+        DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
+        DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
+        DA850_VPIF_CLKO3,
+        -1
+};
 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
        [IRQ_DA8XX_COMMTX]              = 7,
@@ -939,7 +1007,7 @@ static struct platform_device da850_cpufreq_device = {
 unsigned int da850_max_speed = 300000;
-int __init da850_register_cpufreq(char *async_clk)
+int da850_register_cpufreq(char *async_clk)
 {
        int i;
@@ -1064,6 +1132,90 @@ no_ddrpll_mem:
        return ret;
 }
+/* VPIF resource, platform data */
+static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
+static struct resource da850_vpif_resource[] = {
+        {
+                .start = DA8XX_VPIF_BASE,
+                .end   = DA8XX_VPIF_BASE + 0xfff,
+                .flags = IORESOURCE_MEM,
+        }
+};
+static struct platform_device da850_vpif_dev = {
+        .name           = "vpif",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &da850_vpif_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = da850_vpif_resource,
+        .num_resources  = ARRAY_SIZE(da850_vpif_resource),
+};
+static struct resource da850_vpif_display_resource[] = {
+        {
+                .start = IRQ_DA850_VPIFINT,
+                .end   = IRQ_DA850_VPIFINT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device da850_vpif_display_dev = {
+        .name           = "vpif_display",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &da850_vpif_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = da850_vpif_display_resource,
+        .num_resources  = ARRAY_SIZE(da850_vpif_display_resource),
+};
+static struct resource da850_vpif_capture_resource[] = {
+        {
+                .start = IRQ_DA850_VPIFINT,
+                .end   = IRQ_DA850_VPIFINT,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_DA850_VPIFINT,
+                .end   = IRQ_DA850_VPIFINT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device da850_vpif_capture_dev = {
+        .name           = "vpif_capture",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &da850_vpif_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = da850_vpif_capture_resource,
+        .num_resources  = ARRAY_SIZE(da850_vpif_capture_resource),
+};
+int __init da850_register_vpif(void)
+{
+        return platform_device_register(&da850_vpif_dev);
+}
+int __init da850_register_vpif_display(struct vpif_display_config
+                                                *display_config)
+{
+        da850_vpif_display_dev.dev.platform_data = display_config;
+        return platform_device_register(&da850_vpif_display_dev);
+}
+int __init da850_register_vpif_capture(struct vpif_capture_config
+                                                        *capture_config)
+{
+        da850_vpif_capture_dev.dev.platform_data = capture_config;
+        return platform_device_register(&da850_vpif_capture_dev);
+}
 static struct davinci_soc_info davinci_soc_info_da850 = {
        .io_desc                = da850_io_desc,
        .io_desc_num            = ARRAY_SIZE(da850_io_desc),
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 8db0fc6809dd..12d544befcfa 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -22,10 +22,10 @@
 #include <linux/davinci_emac.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/davinci_asp.h>
-#include <mach/asp.h>
+#include <linux/platform_data/keyscan-davinci.h>
-#include <mach/keyscan.h>
 #include <mach/hardware.h>
+#include <mach/edma.h>
 #include <media/davinci/vpfe_capture.h>
 #include <media/davinci/vpif_types.h>
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 783eab6845c4..bd2f72b414bc 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -24,6 +24,7 @@
 #include <mach/cpuidle.h>
 #include "clock.h"
+#include "asp.h"
 #define DA8XX_TPCC_BASE                 0x01c00000
 #define DA8XX_TPTC0_BASE                0x01c08000
@@ -505,15 +506,8 @@ static struct platform_device da850_mcasp_device = {
        .resource       = da850_mcasp_resources,
 };
-static struct platform_device davinci_pcm_device = {
-        .name   = "davinci-pcm-audio",
-        .id     = -1,
-};
 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
 {
-        platform_device_register(&davinci_pcm_device);
        /* DA830/OMAP-L137 has 3 instances of McASP */
        if (cpu_is_davinci_da830() && id == 1) {
                da830_mcasp1_device.dev.platform_data = pdata;
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index d2f9666284a7..4c48a36ee567 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -15,12 +15,12 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-davinci.h>
 #include <mach/irqs.h>
 #include <mach/cputype.h>
 #include <mach/mux.h>
 #include <mach/edma.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-davinci.h>
 #include <mach/time.h>
 #include "davinci.h"
@@ -313,16 +313,6 @@ static void davinci_init_wdt(void)
 /*-------------------------------------------------------------------------*/
-static struct platform_device davinci_pcm_device = {
-        .name           = "davinci-pcm-audio",
-        .id             = -1,
-};
-static void davinci_init_pcm(void)
-{
-        platform_device_register(&davinci_pcm_device);
-}
 /*-------------------------------------------------------------------------*/
 struct davinci_timer_instance davinci_timer_instance[2] = {
@@ -345,7 +335,6 @@ static int __init davinci_init_devices(void)
        /* please keep these calls, and their implementations above,
         * in alphabetical order so they're easier to sort through.
         */
-        davinci_init_pcm();
        davinci_init_wdt();
        return 0;
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 678cd99b7336..a255434908db 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -26,13 +26,13 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
+#include <linux/platform_data/spi-davinci.h>
-#include <mach/spi.h>
 #include <mach/gpio-davinci.h>
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 #define DM355_UART2_BASE        (IO_PHYS + 0x206000)
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index a50d49de1883..b680c832e0ba 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -29,14 +29,14 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
+#include <linux/platform_data/keyscan-davinci.h>
-#include <mach/keyscan.h>
+#include <linux/platform_data/spi-davinci.h>
-#include <mach/spi.h>
 #include <mach/gpio-davinci.h>
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index c8b866657fcb..cd0c8b1e1ecf 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -23,12 +23,12 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
 #include <mach/gpio-davinci.h>
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 /*
 * Device specific clocks
@@ -701,7 +701,7 @@ static struct resource dm644x_venc_resources[] = {
 #define DM644X_VPSS_DACCLKEN                  BIT(4)
 static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
-                                   unsigned int mode)
+                                   unsigned int pclock)
 {
        int ret = 0;
        u32 v = DM644X_VPSS_VENCLKEN;
@@ -711,27 +711,18 @@ static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
                v |= DM644X_VPSS_DACCLKEN;
                writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
                break;
-        case VPBE_ENC_DV_PRESET:
+        case VPBE_ENC_CUSTOM_TIMINGS:
-                switch (mode) {
+                if (pclock <= 27000000) {
-                case V4L2_DV_480P59_94:
-                case V4L2_DV_576P50:
                        v |= DM644X_VPSS_MUXSEL_PLL2_MODE |
                             DM644X_VPSS_DACCLKEN;
                        writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
-                        break;
+                } else {
-                case V4L2_DV_720P60:
-                case V4L2_DV_1080I60:
-                case V4L2_DV_1080P30:
                        /*
                         * For HD, use external clock source since
                         * HD requires higher clock rate
                         */
                        v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
                        writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
-                        break;
-                default:
-                        ret = -EINVAL;
-                        break;
                }
                break;
        default:
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 9eb87c1d1edd..97c0f8e555bd 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -24,12 +24,12 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
 #include <mach/gpio-davinci.h>
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 #define DAVINCI_VPIF_BASE       (0x01C12000)
diff --git a/arch/arm/mach-davinci/include/mach/aemif.h b/arch/arm/mach-davinci/include/mach/aemif.h
deleted file mode 100644
index 05b293443097..000000000000
--- a/arch/arm/mach-davinci/include/mach/aemif.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * TI DaVinci AEMIF support
- *
- * Copyright 2010 (C) Texas Instruments, Inc. http://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-#ifndef _MACH_DAVINCI_AEMIF_H
-#define _MACH_DAVINCI_AEMIF_H
-#define NRCSR_OFFSET            0x00
-#define AWCCR_OFFSET            0x04
-#define A1CR_OFFSET             0x10
-#define ACR_ASIZE_MASK          0x3
-#define ACR_EW_MASK             BIT(30)
-#define ACR_SS_MASK             BIT(31)
-/* All timings in nanoseconds */
-struct davinci_aemif_timing {
-        u8      wsetup;
-        u8      wstrobe;
-        u8      whold;
-        u8      rsetup;
-        u8      rstrobe;
-        u8      rhold;
-        u8      ta;
-};
-int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
-                                        void __iomem *base, unsigned cs);
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
deleted file mode 100644
index 9aa240909a2c..000000000000
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * <mach/asp.h> - DaVinci Audio Serial Port support
- */
-#ifndef __ASM_ARCH_DAVINCI_ASP_H
-#define __ASM_ARCH_DAVINCI_ASP_H
-#include <mach/irqs.h>
-#include <mach/edma.h>
-/* Bases of dm644x and dm355 register banks */
-#define DAVINCI_ASP0_BASE       0x01E02000
-#define DAVINCI_ASP1_BASE       0x01E04000
-/* Bases of dm365 register banks */
-#define DAVINCI_DM365_ASP0_BASE 0x01D02000
-/* Bases of dm646x register banks */
-#define DAVINCI_DM646X_MCASP0_REG_BASE          0x01D01000
-#define DAVINCI_DM646X_MCASP1_REG_BASE          0x01D01800
-/* Bases of da850/da830 McASP0  register banks */
-#define DAVINCI_DA8XX_MCASP0_REG_BASE   0x01D00000
-/* Bases of da830 McASP1 register banks */
-#define DAVINCI_DA830_MCASP1_REG_BASE   0x01D04000
-/* EDMA channels of dm644x and dm355 */
-#define DAVINCI_DMA_ASP0_TX     2
-#define DAVINCI_DMA_ASP0_RX     3
-#define DAVINCI_DMA_ASP1_TX     8
-#define DAVINCI_DMA_ASP1_RX     9
-/* EDMA channels of dm646x */
-#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0        6
-#define DAVINCI_DM646X_DMA_MCASP0_AREVT0        9
-#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1        12
-/* EDMA channels of da850/da830 McASP0 */
-#define DAVINCI_DA8XX_DMA_MCASP0_AREVT  0
-#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT  1
-/* EDMA channels of da830 McASP1 */
-#define DAVINCI_DA830_DMA_MCASP1_AREVT  2
-#define DAVINCI_DA830_DMA_MCASP1_AXEVT  3
-/* Interrupts */
-#define DAVINCI_ASP0_RX_INT     IRQ_MBRINT
-#define DAVINCI_ASP0_TX_INT     IRQ_MBXINT
-#define DAVINCI_ASP1_RX_INT     IRQ_MBRINT
-#define DAVINCI_ASP1_TX_INT     IRQ_MBXINT
-struct snd_platform_data {
-        u32 tx_dma_offset;
-        u32 rx_dma_offset;
-        enum dma_event_q asp_chan_q;    /* event queue number for ASP channel */
-        enum dma_event_q ram_chan_q;    /* event queue number for RAM channel */
-        unsigned int codec_fmt;
-        /*
-         * Allowing this is more efficient and eliminates left and right swaps
-         * caused by underruns, but will swap the left and right channels
-         * when compared to previous behavior.
-         */
-        unsigned enable_channel_combine:1;
-        unsigned sram_size_playback;
-        unsigned sram_size_capture;
-        /*
-         * If McBSP peripheral gets the clock from an external pin,
-         * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
-         * and MCBSP_CLKS.
-         * Depending on different hardware connections it is possible
-         * to use this setting to change the behaviour of McBSP
-         * driver. The dm365_clk_input_pin enum is available for dm365
-         */
-        int clk_input_pin;
-        /*
-         * This flag works when both clock and FS are outputs for the cpu
-         * and makes clock more accurate (FS is not symmetrical and the
-         * clock is very fast.
-         * The clock becoming faster is named
-         * i2s continuous serial clock (I2S_SCK) and it is an externally
-         * visible bit clock.
-         *
-         * first line : WordSelect
-         * second line : ContinuousSerialClock
-         * third line: SerialData
-         *
-         * SYMMETRICAL APPROACH:
-         *   _______________________          LEFT
-         * _|         RIGHT         |______________________|
-         *     _   _         _   _   _   _         _   _
-         *   _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
-         *     _   _         _   _   _   _         _   _
-         *   _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
-         *    \_/ \_/       \_/ \_/ \_/ \_/       \_/ \_/
-         *
-         * ACCURATE CLOCK APPROACH:
-         *   ______________          LEFT
-         * _|     RIGHT    |_______________________________|
-         *     _         _   _         _   _   _   _   _   _
-         *   _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
-         *     _         _   _          _      dummy cycles
-         *   _/ \_ ... _/ \_/ \_  ... _/ \__________________
-         *    \_/       \_/ \_/        \_/
-         *
-         */
-        bool i2s_accurate_sck;
-        /* McASP specific fields */
-        int tdm_slots;
-        u8 op_mode;
-        u8 num_serializer;
-        u8 *serial_dir;
-        u8 version;
-        u8 txnumevt;
-        u8 rxnumevt;
-};
-enum {
-        MCASP_VERSION_1 = 0,    /* DM646x */
-        MCASP_VERSION_2,        /* DA8xx/OMAPL1x */
-};
-enum dm365_clk_input_pin {
-        MCBSP_CLKR = 0,         /* DM365 */
-        MCBSP_CLKS,
-};
-#define INACTIVE_MODE   0
-#define TX_MODE         1
-#define RX_MODE         2
-#define DAVINCI_MCASP_IIS_MODE  0
-#define DAVINCI_MCASP_DIT_MODE  1
-#endif /* __ASM_ARCH_DAVINCI_ASP_H */
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index a2f1f274f189..aaccdc4528fc 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -16,15 +16,18 @@
 #include <linux/platform_device.h>
 #include <linux/davinci_emac.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/davinci_asp.h>
+#include <linux/videodev2.h>
 #include <mach/serial.h>
 #include <mach/edma.h>
-#include <mach/i2c.h>
-#include <mach/asp.h>
-#include <mach/mmc.h>
-#include <mach/usb.h>
 #include <mach/pm.h>
-#include <mach/spi.h>
+#include <linux/platform_data/i2c-davinci.h>
+#include <linux/platform_data/mmc-davinci.h>
+#include <linux/platform_data/usb-davinci.h>
+#include <linux/platform_data/spi-davinci.h>
+#include <media/davinci/vpif_types.h>
 extern void __iomem *da8xx_syscfg0_base;
 extern void __iomem *da8xx_syscfg1_base;
@@ -63,6 +66,7 @@ extern unsigned int da850_max_speed;
 #define DA8XX_PLL0_BASE         0x01c11000
 #define DA8XX_TIMER64P0_BASE    0x01c20000
 #define DA8XX_TIMER64P1_BASE    0x01c21000
+#define DA8XX_VPIF_BASE         0x01e17000
 #define DA8XX_GPIO_BASE         0x01e26000
 #define DA8XX_PSC1_BASE         0x01e27000
 #define DA8XX_AEMIF_CS2_BASE    0x60000000
@@ -92,6 +96,11 @@ int da8xx_register_cpuidle(void);
 void __iomem * __init da8xx_get_mem_ctlr(void);
 int da850_register_pm(struct platform_device *pdev);
 int __init da850_register_sata(unsigned long refclkpn);
+int __init da850_register_vpif(void);
+int __init da850_register_vpif_display
+                        (struct vpif_display_config *display_config);
+int __init da850_register_vpif_capture
+                        (struct vpif_capture_config *capture_config);
 void da8xx_restart(char mode, const char *cmd);
 extern struct platform_device da8xx_serial_device;
@@ -126,6 +135,8 @@ extern const short da830_ecap1_pins[];
 extern const short da830_ecap2_pins[];
 extern const short da830_eqep0_pins[];
 extern const short da830_eqep1_pins[];
+extern const short da850_vpif_capture_pins[];
+extern const short da850_vpif_display_pins[];
 extern const short da850_i2c0_pins[];
 extern const short da850_i2c1_pins[];
diff --git a/arch/arm/mach-davinci/include/mach/i2c.h b/arch/arm/mach-davinci/include/mach/i2c.h
deleted file mode 100644
index 2312d197dfb7..000000000000
--- a/arch/arm/mach-davinci/include/mach/i2c.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * DaVinci I2C controller platform_device info
- *
- * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
-*/
-#ifndef __ASM_ARCH_I2C_H
-#define __ASM_ARCH_I2C_H
-/* All frequencies are expressed in kHz */
-struct davinci_i2c_platform_data {
-        unsigned int    bus_freq;       /* standard bus frequency (kHz) */
-        unsigned int    bus_delay;      /* post-transaction delay (usec) */
-        unsigned int    sda_pin;        /* GPIO pin ID to use for SDA */
-        unsigned int    scl_pin;        /* GPIO pin ID to use for SCL */
-};
-/* for board setup code */
-void davinci_init_i2c(struct davinci_i2c_platform_data *);
-#endif /* __ASM_ARCH_I2C_H */
diff --git a/arch/arm/mach-davinci/include/mach/keyscan.h b/arch/arm/mach-davinci/include/mach/keyscan.h
deleted file mode 100644
index 7a560e05bda8..000000000000
--- a/arch/arm/mach-davinci/include/mach/keyscan.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments, Inc
- *
- * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef DAVINCI_KEYSCAN_H
-#define DAVINCI_KEYSCAN_H
-#include <linux/io.h>
-enum davinci_matrix_types {
-        DAVINCI_KEYSCAN_MATRIX_4X4,
-        DAVINCI_KEYSCAN_MATRIX_5X3,
-};
-struct davinci_ks_platform_data {
-        int             (*device_enable)(struct device *dev);
-        unsigned short  *keymap;
-        u32             keymapsize;
-        u8              rep:1;
-        u8              strobe;
-        u8              interval;
-        u8              matrix_type;
-};
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/mmc.h b/arch/arm/mach-davinci/include/mach/mmc.h
deleted file mode 100644
index 5ba6b22ce338..000000000000
--- a/arch/arm/mach-davinci/include/mach/mmc.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  Board-specific MMC configuration
- */
-#ifndef _DAVINCI_MMC_H
-#define _DAVINCI_MMC_H
-#include <linux/types.h>
-#include <linux/mmc/host.h>
-struct davinci_mmc_config {
-        /* get_cd()/get_wp() may sleep */
-        int     (*get_cd)(int module);
-        int     (*get_ro)(int module);
-        void    (*set_power)(int module, bool on);
-        /* wires == 0 is equivalent to wires == 4 (4-bit parallel) */
-        u8      wires;
-        u32     max_freq;
-        /* any additional host capabilities: OR'd in to mmc->f_caps */
-        u32     caps;
-        /* Version of the MMC/SD controller */
-        u8      version;
-        /* Number of sg segments */
-        u8      nr_sg;
-};
-void davinci_setup_mmc(int module, struct davinci_mmc_config *config);
-enum {
-        MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
-        MMC_CTLR_VERSION_2,     /* DA830 */
-};
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index a7e92fca32e6..9e95b8a1edb6 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -928,6 +928,48 @@ enum davinci_da850_index {
        DA850_GPIO6_10,
        DA850_GPIO6_13,
        DA850_RTC_ALARM,
+        /* VPIF Capture */
+        DA850_VPIF_DIN0,
+        DA850_VPIF_DIN1,
+        DA850_VPIF_DIN2,
+        DA850_VPIF_DIN3,
+        DA850_VPIF_DIN4,
+        DA850_VPIF_DIN5,
+        DA850_VPIF_DIN6,
+        DA850_VPIF_DIN7,
+        DA850_VPIF_DIN8,
+        DA850_VPIF_DIN9,
+        DA850_VPIF_DIN10,
+        DA850_VPIF_DIN11,
+        DA850_VPIF_DIN12,
+        DA850_VPIF_DIN13,
+        DA850_VPIF_DIN14,
+        DA850_VPIF_DIN15,
+        DA850_VPIF_CLKIN0,
+        DA850_VPIF_CLKIN1,
+        DA850_VPIF_CLKIN2,
+        DA850_VPIF_CLKIN3,
+        /* VPIF Display */
+        DA850_VPIF_DOUT0,
+        DA850_VPIF_DOUT1,
+        DA850_VPIF_DOUT2,
+        DA850_VPIF_DOUT3,
+        DA850_VPIF_DOUT4,
+        DA850_VPIF_DOUT5,
+        DA850_VPIF_DOUT6,
+        DA850_VPIF_DOUT7,
+        DA850_VPIF_DOUT8,
+        DA850_VPIF_DOUT9,
+        DA850_VPIF_DOUT10,
+        DA850_VPIF_DOUT11,
+        DA850_VPIF_DOUT12,
+        DA850_VPIF_DOUT13,
+        DA850_VPIF_DOUT14,
+        DA850_VPIF_DOUT15,
+        DA850_VPIF_CLKO2,
+        DA850_VPIF_CLKO3,
 };
 enum davinci_tnetv107x_index {
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h
deleted file mode 100644
index 1cf555aef896..000000000000
--- a/arch/arm/mach-davinci/include/mach/nand.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * mach-davinci/nand.h
- *
- * Copyright © 2006 Texas Instruments.
- *
- * Ported to 2.6.23 Copyright © 2008 by
- *   Sander Huijsen <Shuijsen@optelecom-nkf.com>
- *   Troy Kisky <troy.kisky@boundarydevices.com>
- *   Dirk Behme <Dirk.Behme@gmail.com>
- *
- * --------------------------------------------------------------------------
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ARCH_ARM_DAVINCI_NAND_H
-#define __ARCH_ARM_DAVINCI_NAND_H
-#include <linux/mtd/nand.h>
-#define NANDFCR_OFFSET          0x60
-#define NANDFSR_OFFSET          0x64
-#define NANDF1ECC_OFFSET        0x70
-/* 4-bit ECC syndrome registers */
-#define NAND_4BIT_ECC_LOAD_OFFSET       0xbc
-#define NAND_4BIT_ECC1_OFFSET           0xc0
-#define NAND_4BIT_ECC2_OFFSET           0xc4
-#define NAND_4BIT_ECC3_OFFSET           0xc8
-#define NAND_4BIT_ECC4_OFFSET           0xcc
-#define NAND_ERR_ADD1_OFFSET            0xd0
-#define NAND_ERR_ADD2_OFFSET            0xd4
-#define NAND_ERR_ERRVAL1_OFFSET         0xd8
-#define NAND_ERR_ERRVAL2_OFFSET         0xdc
-/* NOTE:  boards don't need to use these address bits
- * for ALE/CLE unless they support booting from NAND.
- * They're used unless platform data overrides them.
- */
-#define MASK_ALE                0x08
-#define MASK_CLE                0x10
-struct davinci_nand_pdata {             /* platform_data */
-        uint32_t                mask_ale;
-        uint32_t                mask_cle;
-        /* for packages using two chipselects */
-        uint32_t                mask_chipsel;
-        /* board's default static partition info */
-        struct mtd_partition    *parts;
-        unsigned                nr_parts;
-        /* none  == NAND_ECC_NONE (strongly *not* advised!!)
-         * soft  == NAND_ECC_SOFT
-         * else  == NAND_ECC_HW, according to ecc_bits
-         *
-         * All DaVinci-family chips support 1-bit hardware ECC.
-         * Newer ones also support 4-bit ECC, but are awkward
-         * using it with large page chips.
-         */
-        nand_ecc_modes_t        ecc_mode;
-        u8                      ecc_bits;
-        /* e.g. NAND_BUSWIDTH_16 */
-        unsigned                options;
-        /* e.g. NAND_BBT_USE_FLASH */
-        unsigned                bbt_options;
-        /* Main and mirror bbt descriptor overrides */
-        struct nand_bbt_descr   *bbt_td;
-        struct nand_bbt_descr   *bbt_md;
-        /* Access timings */
-        struct davinci_aemif_timing     *timing;
-};
-#endif  /* __ARCH_ARM_DAVINCI_NAND_H */
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 405318e35bf6..40a0027838e8 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -166,6 +166,7 @@
 #define DA830_LPSC1_McASP1              8
 #define DA850_LPSC1_SATA                8
 #define DA830_LPSC1_McASP2              9
+#define DA850_LPSC1_VPIF                9
 #define DA8XX_LPSC1_SPI1                10
 #define DA8XX_LPSC1_I2C                 11
 #define DA8XX_LPSC1_UART1               12
diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h
deleted file mode 100644
index 7af305b37868..000000000000
--- a/arch/arm/mach-davinci/include/mach/spi.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2009 Texas Instruments.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ARCH_ARM_DAVINCI_SPI_H
-#define __ARCH_ARM_DAVINCI_SPI_H
-#include <mach/edma.h>
-#define SPI_INTERN_CS   0xFF
-enum {
-        SPI_VERSION_1, /* For DM355/DM365/DM6467 */
-        SPI_VERSION_2, /* For DA8xx */
-};
-/**
- * davinci_spi_platform_data - Platform data for SPI master device on DaVinci
- *
- * @version:    version of the SPI IP. Different DaVinci devices have slightly
- *              varying versions of the same IP.
- * @num_chipselect: number of chipselects supported by this SPI master
- * @intr_line:  interrupt line used to connect the SPI IP to the ARM interrupt
- *              controller withn the SoC. Possible values are 0 and 1.
- * @chip_sel:   list of GPIOs which can act as chip-selects for the SPI.
- *              SPI_INTERN_CS denotes internal SPI chip-select. Not necessary
- *              to populate if all chip-selects are internal.
- * @cshold_bug: set this to true if the SPI controller on your chip requires
- *              a write to CSHOLD bit in between transfers (like in DM355).
- * @dma_event_q: DMA event queue to use if SPI_IO_TYPE_DMA is used for any
- *              device on the bus.
- */
-struct davinci_spi_platform_data {
-        u8                      version;
-        u8                      num_chipselect;
-        u8                      intr_line;
-        u8                      *chip_sel;
-        bool                    cshold_bug;
-        enum dma_event_q        dma_event_q;
-};
-/**
- * davinci_spi_config - Per-chip-select configuration for SPI slave devices
- *
- * @wdelay:     amount of delay between transmissions. Measured in number of
- *              SPI module clocks.
- * @odd_parity: polarity of parity flag at the end of transmit data stream.
- *              0 - odd parity, 1 - even parity.
- * @parity_enable: enable transmission of parity at end of each transmit
- *              data stream.
- * @io_type:    type of IO transfer. Choose between polled, interrupt and DMA.
- * @timer_disable: disable chip-select timers (setup and hold)
- * @c2tdelay:   chip-select setup time. Measured in number of SPI module clocks.
- * @t2cdelay:   chip-select hold time. Measured in number of SPI module clocks.
- * @t2edelay:   transmit data finished to SPI ENAn pin inactive time. Measured
- *              in number of SPI clocks.
- * @c2edelay:   chip-select active to SPI ENAn signal active time. Measured in
- *              number of SPI clocks.
- */
-struct davinci_spi_config {
-        u8      wdelay;
-        u8      odd_parity;
-        u8      parity_enable;
-#define SPI_IO_TYPE_INTR        0
-#define SPI_IO_TYPE_POLL        1
-#define SPI_IO_TYPE_DMA         2
-        u8      io_type;
-        u8      timer_disable;
-        u8      c2tdelay;
-        u8      t2cdelay;
-        u8      t2edelay;
-        u8      c2edelay;
-};
-#endif  /* __ARCH_ARM_DAVINCI_SPI_H */
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 83e5926f3c46..1656a02e3eda 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -36,8 +36,8 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/mfd/ti_ssp.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-davinci.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-davinci.h>
 #include <mach/serial.h>
 struct tnetv107x_device_info {
diff --git a/arch/arm/mach-davinci/include/mach/usb.h b/arch/arm/mach-davinci/include/mach/usb.h
deleted file mode 100644
index e0bc4abe69c2..000000000000
--- a/arch/arm/mach-davinci/include/mach/usb.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * USB related definitions
- *
- * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-#ifndef __ASM_ARCH_USB_H
-#define __ASM_ARCH_USB_H
-/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
-#define CFGCHIP2_PHYCLKGD       (1 << 17)
-#define CFGCHIP2_VBUSSENSE      (1 << 16)
-#define CFGCHIP2_RESET          (1 << 15)
-#define CFGCHIP2_OTGMODE        (3 << 13)
-#define CFGCHIP2_NO_OVERRIDE    (0 << 13)
-#define CFGCHIP2_FORCE_HOST     (1 << 13)
-#define CFGCHIP2_FORCE_DEVICE   (2 << 13)
-#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
-#define CFGCHIP2_USB1PHYCLKMUX  (1 << 12)
-#define CFGCHIP2_USB2PHYCLKMUX  (1 << 11)
-#define CFGCHIP2_PHYPWRDN       (1 << 10)
-#define CFGCHIP2_OTGPWRDN       (1 << 9)
-#define CFGCHIP2_DATPOL         (1 << 8)
-#define CFGCHIP2_USB1SUSPENDM   (1 << 7)
-#define CFGCHIP2_PHY_PLLON      (1 << 6)        /* override PLL suspend */
-#define CFGCHIP2_SESENDEN       (1 << 5)        /* Vsess_end comparator */
-#define CFGCHIP2_VBDTCTEN       (1 << 4)        /* Vbus comparator */
-#define CFGCHIP2_REFFREQ        (0xf << 0)
-#define CFGCHIP2_REFFREQ_12MHZ  (1 << 0)
-#define CFGCHIP2_REFFREQ_24MHZ  (2 << 0)
-#define CFGCHIP2_REFFREQ_48MHZ  (3 << 0)
-struct  da8xx_ohci_root_hub;
-typedef void (*da8xx_ocic_handler_t)(struct da8xx_ohci_root_hub *hub,
-                                     unsigned port);
-/* Passed as the platform data to the OHCI driver */
-struct  da8xx_ohci_root_hub {
-        /* Switch the port power on/off */
-        int     (*set_power)(unsigned port, int on);
-        /* Read the port power status */
-        int     (*get_power)(unsigned port);
-        /* Read the port over-current indicator */
-        int     (*get_oci)(unsigned port);
-        /* Over-current indicator change notification (pass NULL to disable) */
-        int     (*ocic_notify)(da8xx_ocic_handler_t handler);
-        /* Time from power on to power good (in 2 ms units) */
-        u8      potpgt;
-};
-void davinci_setup_usb(unsigned mA, unsigned potpgt_ms);
-#endif  /* ifndef __ASM_ARCH_USB_H */
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 23d2b6d9fa63..f77b95336e2b 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -10,7 +10,7 @@
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/cputype.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-davinci.h>
 #define DAVINCI_USB_OTG_BASE    0x01c64000
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index dd937c526a45..00154e74ce6b 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -15,6 +15,13 @@ config MACH_CM_A510
          Say 'Y' here if you want your kernel to support the
          CompuLab CM-A510 Board.
+config MACH_DOVE_DT
+        bool "Marvell Dove Flattened Device Tree"
+        select USE_OF
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell Dove using flattened device tree.
 endmenu
 endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index fa0f01856060..5e683baf96cf 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,4 +1,4 @@
-obj-y                           += common.o addr-map.o irq.o pcie.o mpp.o
+obj-y                           += common.o addr-map.o irq.o mpp.o
+obj-$(CONFIG_PCI)               += pcie.o
 obj-$(CONFIG_MACH_DOVE_DB)      += dove-db-setup.o
 obj-$(CONFIG_MACH_CM_A510)      += cm-a510.o
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 6321567d8eaa..b37bef1d5ffa 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,6 +16,8 @@
 #include <linux/clk-provider.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/timex.h>
@@ -24,41 +26,30 @@
 #include <asm/mach/time.h>
 #include <asm/mach/pci.h>
 #include <mach/dove.h>
+#include <mach/pm.h>
 #include <mach/bridge-regs.h>
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
 #include <plat/time.h>
-#include <plat/ehci-orion.h>
+#include <linux/platform_data/usb-ehci-orion.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
 #include "common.h"
-static int get_tclk(void);
 /*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
 static struct map_desc dove_io_desc[] __initdata = {
        {
-                .virtual        = DOVE_SB_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
                .pfn            = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
                .length         = DOVE_SB_REGS_SIZE,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = DOVE_NB_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
                .pfn            = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
                .length         = DOVE_NB_REGS_SIZE,
                .type           = MT_DEVICE,
-        }, {
-                .virtual        = DOVE_PCIE0_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
-                .length         = DOVE_PCIE0_IO_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = DOVE_PCIE1_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
-                .length         = DOVE_PCIE1_IO_SIZE,
-                .type           = MT_DEVICE,
        },
 };
@@ -70,14 +61,69 @@ void __init dove_map_io(void)
 /*****************************************************************************
 * CLK tree
 ****************************************************************************/
+static int dove_tclk;
+static DEFINE_SPINLOCK(gating_lock);
 static struct clk *tclk;
-static void __init clk_init(void)
+static struct clk __init *dove_register_gate(const char *name,
+                                             const char *parent, u8 bit_idx)
 {
-        tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
+        return clk_register_gate(NULL, name, parent, 0,
-                                       get_tclk());
+                                 (void __iomem *)CLOCK_GATING_CONTROL,
+                                 bit_idx, 0, &gating_lock);
+}
-        orion_clkdev_init(tclk);
+static void __init dove_clk_init(void)
+{
+        struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
+        struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
+        struct clk *xor0, *xor1, *ge, *gephy;
+        tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
+                                       dove_tclk);
+        usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
+        usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
+        sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
+        pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
+        pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
+        sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
+        sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
+        nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
+        camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
+        i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
+        i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
+        crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
+        ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
+        pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
+        xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
+        xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
+        gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
+        ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
+        orion_clkdev_add(NULL, "orion_spi.0", tclk);
+        orion_clkdev_add(NULL, "orion_spi.1", tclk);
+        orion_clkdev_add(NULL, "orion_wdt", tclk);
+        orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
+        orion_clkdev_add(NULL, "orion-ehci.0", usb0);
+        orion_clkdev_add(NULL, "orion-ehci.1", usb1);
+        orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
+        orion_clkdev_add("0", "sata_mv.0", sata);
+        orion_clkdev_add("0", "pcie", pex0);
+        orion_clkdev_add("1", "pcie", pex1);
+        orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
+        orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
+        orion_clkdev_add(NULL, "orion_nand", nand);
+        orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
+        orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
+        orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
+        orion_clkdev_add(NULL, "mv_crypto", crypto);
+        orion_clkdev_add(NULL, "dove-ac97", ac97);
+        orion_clkdev_add(NULL, "dove-pdma", pdma);
+        orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);
+        orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);
 }
 /*****************************************************************************
@@ -188,16 +234,16 @@ void __init dove_init_early(void)
        orion_time_set_base(TIMER_VIRT_BASE);
 }
-static int get_tclk(void)
+static int __init dove_find_tclk(void)
 {
-        /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
        return 166666667;
 }
 static void __init dove_timer_init(void)
 {
+        dove_tclk = dove_find_tclk();
        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
-                        IRQ_DOVE_BRIDGE, get_tclk());
+                        IRQ_DOVE_BRIDGE, dove_tclk);
 }
 struct sys_timer dove_timer = {
@@ -205,6 +251,15 @@ struct sys_timer dove_timer = {
 };
 /*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+void __init dove_crypto_init(void)
+{
+        orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
+                          DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
+}
+/*****************************************************************************
 * XOR 0
 ****************************************************************************/
 void __init dove_xor0_init(void)
@@ -285,16 +340,16 @@ void __init dove_sdio1_init(void)
 void __init dove_init(void)
 {
-        printk(KERN_INFO "Dove 88AP510 SoC, ");
+        pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
-        printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
+                (dove_tclk + 499999) / 1000000);
 #ifdef CONFIG_CACHE_TAUROS2
-        tauros2_init();
+        tauros2_init(0);
 #endif
        dove_setup_cpu_mbus();
        /* Setup root of clk tree */
-        clk_init();
+        dove_clk_init();
        /* internal devices that every board has */
        dove_rtc_init();
@@ -317,3 +372,67 @@ void dove_restart(char mode, const char *cmd)
        while (1)
                ;
 }
+#if defined(CONFIG_MACH_DOVE_DT)
+/*
+ * Auxdata required until real OF clock provider
+ */
+struct of_dev_auxdata dove_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
+        OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL),
+        OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
+        OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
+                       NULL),
+        OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL),
+        OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL),
+        OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL),
+        {},
+};
+static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
+        .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
+};
+static void __init dove_dt_init(void)
+{
+        pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+                (dove_tclk + 499999) / 1000000);
+#ifdef CONFIG_CACHE_TAUROS2
+        tauros2_init();
+#endif
+        dove_setup_cpu_mbus();
+        /* Setup root of clk tree */
+        dove_clk_init();
+        /* Internal devices not ported to DT yet */
+        dove_rtc_init();
+        dove_xor0_init();
+        dove_xor1_init();
+        dove_ge00_init(&dove_dt_ge00_data);
+        dove_ehci0_init();
+        dove_ehci1_init();
+        dove_pcie_init(1, 1);
+        dove_crypto_init();
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             dove_auxdata_lookup, NULL);
+}
+static const char * const dove_dt_board_compat[] = {
+        "marvell,dove",
+        NULL
+};
+DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
+        .map_io         = dove_map_io,
+        .init_early     = dove_init_early,
+        .init_irq       = orion_dt_init_irq,
+        .timer          = &dove_timer,
+        .init_machine   = dove_dt_init,
+        .restart        = dove_restart,
+        .dt_compat      = dove_dt_board_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index 6432a3ba864b..1a233404b735 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -26,7 +26,11 @@ void dove_init_irq(void);
 void dove_setup_cpu_mbus(void);
 void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void dove_sata_init(struct mv_sata_platform_data *sata_data);
+#ifdef CONFIG_PCI
 void dove_pcie_init(int init_port0, int init_port1);
+#else
+static inline void dove_pcie_init(int init_port0, int init_port1) { }
+#endif
 void dove_ehci0_init(void);
 void dove_ehci1_init(void);
 void dove_uart0_init(void);
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index f953bb54aa9d..99f259e8cf33 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -13,22 +13,22 @@
 #include <mach/dove.h>
-#define CPU_CONFIG              (BRIDGE_VIRT_BASE | 0x0000)
+#define CPU_CONFIG              (BRIDGE_VIRT_BASE + 0x0000)
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
 #define  CPU_CTRL_PCIE0_LINK    0x00000001
 #define  CPU_RESET              0x00000002
 #define  CPU_CTRL_PCIE1_LINK    0x00000008
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
 #define  SOFT_RESET_OUT_EN      0x00000004
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define  SOFT_RESET             0x00000001
 #define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_LOW_OFF       0x0000
 #define IRQ_MASK_LOW_OFF        0x0004
 #define FIQ_MASK_LOW_OFF        0x0008
@@ -47,9 +47,9 @@
 #define ENDPOINT_MASK_HIGH      (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
 #define PCIE_INTERRUPT_MASK     (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
-#define POWER_MANAGEMENT        (BRIDGE_VIRT_BASE | 0x011c)
+#define POWER_MANAGEMENT        (BRIDGE_VIRT_BASE + 0x011c)
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
 #endif
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index d52b0ef313b7..661725e3115a 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -25,7 +25,7 @@
 */
 #define DOVE_CESA_PHYS_BASE             0xc8000000
-#define DOVE_CESA_VIRT_BASE             0xfdb00000
+#define DOVE_CESA_VIRT_BASE             IOMEM(0xfdb00000)
 #define DOVE_CESA_SIZE                  SZ_1M
 #define DOVE_PCIE0_MEM_PHYS_BASE        0xe0000000
@@ -38,101 +38,99 @@
 #define DOVE_BOOTROM_SIZE               SZ_128M
 #define DOVE_SCRATCHPAD_PHYS_BASE       0xf0000000
-#define DOVE_SCRATCHPAD_VIRT_BASE       0xfdd00000
+#define DOVE_SCRATCHPAD_VIRT_BASE       IOMEM(0xfdd00000)
 #define DOVE_SCRATCHPAD_SIZE            SZ_1M
 #define DOVE_SB_REGS_PHYS_BASE          0xf1000000
-#define DOVE_SB_REGS_VIRT_BASE          0xfde00000
+#define DOVE_SB_REGS_VIRT_BASE          IOMEM(0xfde00000)
 #define DOVE_SB_REGS_SIZE               SZ_8M
 #define DOVE_NB_REGS_PHYS_BASE          0xf1800000
-#define DOVE_NB_REGS_VIRT_BASE          0xfe600000
+#define DOVE_NB_REGS_VIRT_BASE          IOMEM(0xfe600000)
 #define DOVE_NB_REGS_SIZE               SZ_8M
 #define DOVE_PCIE0_IO_PHYS_BASE         0xf2000000
-#define DOVE_PCIE0_IO_VIRT_BASE         0xfee00000
 #define DOVE_PCIE0_IO_BUS_BASE          0x00000000
-#define DOVE_PCIE0_IO_SIZE              SZ_1M
+#define DOVE_PCIE0_IO_SIZE              SZ_64K
 #define DOVE_PCIE1_IO_PHYS_BASE         0xf2100000
-#define DOVE_PCIE1_IO_VIRT_BASE         0xfef00000
+#define DOVE_PCIE1_IO_BUS_BASE          0x00010000
-#define DOVE_PCIE1_IO_BUS_BASE          0x00100000
+#define DOVE_PCIE1_IO_SIZE              SZ_64K
-#define DOVE_PCIE1_IO_SIZE              SZ_1M
 /*
 * Dove Core Registers Map
 */
 /* SPI, I2C, UART */
-#define DOVE_I2C_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0x11000)
+#define DOVE_I2C_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0x11000)
-#define DOVE_UART0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12000)
+#define DOVE_UART0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12000)
-#define DOVE_UART0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12000)
+#define DOVE_UART0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12000)
-#define DOVE_UART1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12100)
+#define DOVE_UART1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12100)
-#define DOVE_UART1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12100)
+#define DOVE_UART1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12100)
-#define DOVE_UART2_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12200)
+#define DOVE_UART2_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12200)
-#define DOVE_UART2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12200)
+#define DOVE_UART2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12200)
-#define DOVE_UART3_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12300)
+#define DOVE_UART3_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12300)
-#define DOVE_UART3_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12300)
+#define DOVE_UART3_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12300)
-#define DOVE_SPI0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x10600)
+#define DOVE_SPI0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x10600)
-#define DOVE_SPI1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x14600)
+#define DOVE_SPI1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x14600)
 /* North-South Bridge */
-#define BRIDGE_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x20000)
+#define BRIDGE_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x20000)
-#define BRIDGE_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x20000)
+#define BRIDGE_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x20000)
 /* Cryptographic Engine */
-#define DOVE_CRYPT_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x30000)
+#define DOVE_CRYPT_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x30000)
 /* PCIe 0 */
-#define DOVE_PCIE0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x40000)
+#define DOVE_PCIE0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x40000)
 /* USB */
-#define DOVE_USB0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x50000)
+#define DOVE_USB0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x50000)
-#define DOVE_USB1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x51000)
+#define DOVE_USB1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x51000)
 /* XOR 0 Engine */
-#define DOVE_XOR0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x60800)
+#define DOVE_XOR0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x60800)
-#define DOVE_XOR0_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0x60800)
+#define DOVE_XOR0_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0x60800)
-#define DOVE_XOR0_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x60A00)
+#define DOVE_XOR0_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
-#define DOVE_XOR0_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x60A00)
+#define DOVE_XOR0_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
 /* XOR 1 Engine */
-#define DOVE_XOR1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x60900)
+#define DOVE_XOR1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x60900)
-#define DOVE_XOR1_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0x60900)
+#define DOVE_XOR1_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0x60900)
-#define DOVE_XOR1_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x60B00)
+#define DOVE_XOR1_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
-#define DOVE_XOR1_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x60B00)
+#define DOVE_XOR1_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
 /* Gigabit Ethernet */
-#define DOVE_GE00_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x70000)
+#define DOVE_GE00_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x70000)
 /* PCIe 1 */
-#define DOVE_PCIE1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x80000)
+#define DOVE_PCIE1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x80000)
 /* CAFE */
-#define DOVE_SDIO0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x92000)
+#define DOVE_SDIO0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x92000)
-#define DOVE_SDIO1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x90000)
+#define DOVE_SDIO1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x90000)
-#define DOVE_CAM_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0x94000)
+#define DOVE_CAM_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0x94000)
-#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000)
+#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
 /* SATA */
-#define DOVE_SATA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xa0000)
+#define DOVE_SATA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
 /* I2S/SPDIF */
-#define DOVE_AUD0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xb0000)
+#define DOVE_AUD0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
-#define DOVE_AUD1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xb4000)
+#define DOVE_AUD1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
 /* NAND Flash Controller */
-#define DOVE_NFC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xc0000)
+#define DOVE_NFC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
 /* MPP, GPIO, Reset Sampling */
-#define DOVE_MPP_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
+#define DOVE_MPP_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
 #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
-#define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE | 0x014)
+#define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE + 0x014)
-#define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE | 0x018)
+#define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE + 0x018)
-#define DOVE_GPIO_LO_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_GPIO_LO_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
-#define DOVE_GPIO_HI_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
+#define DOVE_GPIO_HI_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
-#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
+#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
-#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
+#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
 #define  DOVE_AU1_SPDIFO_GPIO_EN        (1 << 1)
 #define  DOVE_NAND_GPIO_EN              (1 << 0)
 #define DOVE_MPP_CTRL4_VIRT_BASE        (DOVE_GPIO_LO_VIRT_BASE + 0x40)
@@ -144,44 +142,44 @@
 #define  DOVE_SD0_GPIO_SEL              (1 << 0)
 /* Power Management */
-#define DOVE_PMU_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
+#define DOVE_PMU_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
 #define DOVE_PMU_SIG_CTRL       (DOVE_PMU_VIRT_BASE + 0x802c)
 /* Real Time Clock */
-#define DOVE_RTC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
+#define DOVE_RTC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
 /* AC97 */
-#define DOVE_AC97_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xe0000)
+#define DOVE_AC97_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
-#define DOVE_AC97_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xe0000)
+#define DOVE_AC97_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
 /* Peripheral DMA */
-#define DOVE_PDMA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xe4000)
+#define DOVE_PDMA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
-#define DOVE_PDMA_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xe4000)
+#define DOVE_PDMA_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
-#define DOVE_GLOBAL_CONFIG_1    (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define DOVE_GLOBAL_CONFIG_1    (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
 #define  DOVE_TWSI_ENABLE_OPTION1       (1 << 7)
-#define DOVE_GLOBAL_CONFIG_2    (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define DOVE_GLOBAL_CONFIG_2    (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
 #define  DOVE_TWSI_ENABLE_OPTION2       (1 << 20)
 #define  DOVE_TWSI_ENABLE_OPTION3       (1 << 21)
 #define  DOVE_TWSI_OPTION3_GPIO         (1 << 22)
-#define DOVE_SSP_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xec000)
+#define DOVE_SSP_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xec000)
-#define DOVE_SSP_CTRL_STATUS_1  (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
+#define DOVE_SSP_CTRL_STATUS_1  (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
 #define  DOVE_SSP_ON_AU1                (1 << 0)
 #define  DOVE_SSP_CLOCK_ENABLE          (1 << 1)
 #define  DOVE_SSP_BPB_CLOCK_SRC_SSP     (1 << 11)
 /* Memory Controller */
-#define DOVE_MC_VIRT_BASE       (DOVE_NB_REGS_VIRT_BASE | 0x00000)
+#define DOVE_MC_VIRT_BASE       (DOVE_NB_REGS_VIRT_BASE + 0x00000)
 /* LCD Controller */
-#define DOVE_LCD_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x10000)
+#define DOVE_LCD_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x10000)
-#define DOVE_LCD1_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE | 0x20000)
+#define DOVE_LCD1_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE + 0x20000)
-#define DOVE_LCD2_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE | 0x10000)
+#define DOVE_LCD2_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE + 0x10000)
-#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000)
+#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
 /* Graphic Engine */
-#define DOVE_GPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x40000)
+#define DOVE_GPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x40000)
 /* Video Engine */
-#define DOVE_VPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x400000)
+#define DOVE_VPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x400000)
 #endif
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h
deleted file mode 100644
index e7e5101e35a5..000000000000
--- a/arch/arm/mach-dove/include/mach/gpio.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * arch/arm/mach-dove/include/mach/gpio.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <plat/gpio.h>
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
deleted file mode 100644
index 29c8b85355a5..000000000000
--- a/arch/arm/mach-dove/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-dove/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-#include "dove.h"
-#define IO_SPACE_LIMIT          0xffffffff
-#define __io(a)         ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
-                                                 DOVE_PCIE0_IO_VIRT_BASE))
-#endif
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
index 3ad9f946a9e8..7bcd0dfce4b1 100644
--- a/arch/arm/mach-dove/include/mach/pm.h
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -13,24 +13,42 @@
 #include <mach/irqs.h>
 #define CLOCK_GATING_CONTROL    (DOVE_PMU_VIRT_BASE + 0x38)
-#define  CLOCK_GATING_USB0_MASK         (1 << 0)
+#define  CLOCK_GATING_BIT_USB0          0
-#define  CLOCK_GATING_USB1_MASK         (1 << 1)
+#define  CLOCK_GATING_BIT_USB1          1
-#define  CLOCK_GATING_GBE_MASK          (1 << 2)
+#define  CLOCK_GATING_BIT_GBE           2
-#define  CLOCK_GATING_SATA_MASK         (1 << 3)
+#define  CLOCK_GATING_BIT_SATA          3
-#define  CLOCK_GATING_PCIE0_MASK        (1 << 4)
+#define  CLOCK_GATING_BIT_PCIE0         4
-#define  CLOCK_GATING_PCIE1_MASK        (1 << 5)
+#define  CLOCK_GATING_BIT_PCIE1         5
-#define  CLOCK_GATING_SDIO0_MASK        (1 << 8)
+#define  CLOCK_GATING_BIT_SDIO0         8
-#define  CLOCK_GATING_SDIO1_MASK        (1 << 9)
+#define  CLOCK_GATING_BIT_SDIO1         9
-#define  CLOCK_GATING_NAND_MASK         (1 << 10)
+#define  CLOCK_GATING_BIT_NAND          10
-#define  CLOCK_GATING_CAMERA_MASK       (1 << 11)
+#define  CLOCK_GATING_BIT_CAMERA        11
-#define  CLOCK_GATING_I2S0_MASK         (1 << 12)
+#define  CLOCK_GATING_BIT_I2S0          12
-#define  CLOCK_GATING_I2S1_MASK         (1 << 13)
+#define  CLOCK_GATING_BIT_I2S1          13
-#define  CLOCK_GATING_CRYPTO_MASK       (1 << 15)
+#define  CLOCK_GATING_BIT_CRYPTO        15
-#define  CLOCK_GATING_AC97_MASK         (1 << 21)
+#define  CLOCK_GATING_BIT_AC97          21
-#define  CLOCK_GATING_PDMA_MASK         (1 << 22)
+#define  CLOCK_GATING_BIT_PDMA          22
-#define  CLOCK_GATING_XOR0_MASK         (1 << 23)
+#define  CLOCK_GATING_BIT_XOR0          23
-#define  CLOCK_GATING_XOR1_MASK         (1 << 24)
+#define  CLOCK_GATING_BIT_XOR1          24
-#define  CLOCK_GATING_GIGA_PHY_MASK     (1 << 30)
+#define  CLOCK_GATING_BIT_GIGA_PHY      30
+#define  CLOCK_GATING_USB0_MASK         (1 << CLOCK_GATING_BIT_USB0)
+#define  CLOCK_GATING_USB1_MASK         (1 << CLOCK_GATING_BIT_USB1)
+#define  CLOCK_GATING_GBE_MASK          (1 << CLOCK_GATING_BIT_GBE)
+#define  CLOCK_GATING_SATA_MASK         (1 << CLOCK_GATING_BIT_SATA)
+#define  CLOCK_GATING_PCIE0_MASK        (1 << CLOCK_GATING_BIT_PCIE0)
+#define  CLOCK_GATING_PCIE1_MASK        (1 << CLOCK_GATING_BIT_PCIE1)
+#define  CLOCK_GATING_SDIO0_MASK        (1 << CLOCK_GATING_BIT_SDIO0)
+#define  CLOCK_GATING_SDIO1_MASK        (1 << CLOCK_GATING_BIT_SDIO1)
+#define  CLOCK_GATING_NAND_MASK         (1 << CLOCK_GATING_BIT_NAND)
+#define  CLOCK_GATING_CAMERA_MASK       (1 << CLOCK_GATING_BIT_CAMERA)
+#define  CLOCK_GATING_I2S0_MASK         (1 << CLOCK_GATING_BIT_I2S0)
+#define  CLOCK_GATING_I2S1_MASK         (1 << CLOCK_GATING_BIT_I2S1)
+#define  CLOCK_GATING_CRYPTO_MASK       (1 << CLOCK_GATING_BIT_CRYPTO)
+#define  CLOCK_GATING_AC97_MASK         (1 << CLOCK_GATING_BIT_AC97)
+#define  CLOCK_GATING_PDMA_MASK         (1 << CLOCK_GATING_BIT_PDMA)
+#define  CLOCK_GATING_XOR0_MASK         (1 << CLOCK_GATING_BIT_XOR0)
+#define  CLOCK_GATING_XOR1_MASK         (1 << CLOCK_GATING_BIT_XOR1)
+#define  CLOCK_GATING_GIGA_PHY_MASK     (1 << CLOCK_GATING_BIT_GIGA_PHY)
 #define PMU_INTERRUPT_CAUSE     (DOVE_PMU_VIRT_BASE + 0x50)
 #define PMU_INTERRUPT_MASK      (DOVE_PMU_VIRT_BASE + 0x54)
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 9bc97a5baaa8..087711524e8a 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -18,6 +18,7 @@
 #include <asm/mach/irq.h>
 #include <mach/pm.h>
 #include <mach/bridge-regs.h>
+#include <plat/orion-gpio.h>
 #include "common.h"
 static void pmu_irq_mask(struct irq_data *d)
@@ -99,19 +100,19 @@ void __init dove_init_irq(void)
 {
        int i;
-        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
+        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
-        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
        /*
         * Initialize gpiolib for GPIOs 0-71.
         */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)DOVE_GPIO_LO_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
                        IRQ_DOVE_GPIO_START, gpio0_irqs);
-        orion_gpio_init(NULL, 32, 32, (void __iomem *)DOVE_GPIO_HI_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
                        IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
-        orion_gpio_init(NULL, 64, 8, (void __iomem *)DOVE_GPIO2_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
                        IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
        /*
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index 7f70afc26f91..60bd729a1ba5 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -13,6 +13,7 @@
 #include <linux/io.h>
 #include <plat/mpp.h>
 #include <mach/dove.h>
+#include <plat/orion-gpio.h>
 #include "mpp.h"
 struct dove_mpp_grp {
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 47921b0cdc65..bb15b26041cb 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -26,9 +26,8 @@ struct pcie_port {
        u8                      root_bus_nr;
        void __iomem            *base;
        spinlock_t              conf_lock;
-        char                    io_space_name[16];
        char                    mem_space_name[16];
-        struct resource         res[2];
+        struct resource         res;
 };
 static struct pcie_port pcie_port[2];
@@ -53,24 +52,10 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
        orion_pcie_setup(pp->base);
-        /*
+        if (pp->index == 0)
-         * IORESOURCE_IO
+                pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
-         */
+        else
-        snprintf(pp->io_space_name, sizeof(pp->io_space_name),
+                pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);
-                 "PCIe %d I/O", pp->index);
-        pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
-        pp->res[0].name = pp->io_space_name;
-        if (pp->index == 0) {
-                pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
-                pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
-        } else {
-                pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
-                pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
-        }
-        pp->res[0].flags = IORESOURCE_IO;
-        if (request_resource(&ioport_resource, &pp->res[0]))
-                panic("Request PCIe IO resource failed\n");
-        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
        /*
         * IORESOURCE_MEM
@@ -78,18 +63,18 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
        snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
                 "PCIe %d MEM", pp->index);
        pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
-        pp->res[1].name = pp->mem_space_name;
+        pp->res.name = pp->mem_space_name;
        if (pp->index == 0) {
-                pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
+                pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
-                pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
+                pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
        } else {
-                pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
+                pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
-                pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
+                pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
        }
-        pp->res[1].flags = IORESOURCE_MEM;
+        pp->res.flags = IORESOURCE_MEM;
-        if (request_resource(&iomem_resource, &pp->res[1]))
+        if (request_resource(&iomem_resource, &pp->res))
                panic("Request PCIe Memory resource failed\n");
-        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
        return 1;
 }
@@ -197,20 +182,20 @@ static struct hw_pci dove_pci __initdata = {
        .map_irq        = dove_pcie_map_irq,
 };
-static void __init add_pcie_port(int index, unsigned long base)
+static void __init add_pcie_port(int index, void __iomem *base)
 {
        printk(KERN_INFO "Dove PCIe port %d: ", index);
-        if (orion_pcie_link_up((void __iomem *)base)) {
+        if (orion_pcie_link_up(base)) {
                struct pcie_port *pp = &pcie_port[num_pcie_ports++];
                printk(KERN_INFO "link up\n");
                pp->index = index;
                pp->root_bus_nr = -1;
-                pp->base = (void __iomem *)base;
+                pp->base = base;
                spin_lock_init(&pp->conf_lock);
-                memset(pp->res, 0, sizeof(pp->res));
+                memset(&pp->res, 0, sizeof(pp->res));
        } else {
                printk(KERN_INFO "link down, ignoring\n");
        }
diff --git a/arch/arm/mach-ebsa110/Makefile b/arch/arm/mach-ebsa110/Makefile
index 6520ac835802..935e4af01a27 100644
--- a/arch/arm/mach-ebsa110/Makefile
+++ b/arch/arm/mach-ebsa110/Makefile
@@ -4,9 +4,7 @@
 # Object file lists.
-obj-y                   := core.o io.o
+obj-y                   := core.o io.o leds.o
 obj-m                   :=
 obj-n                   :=
 obj-                    :=
-obj-$(CONFIG_LEDS)      += leds.o
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 6f8068692edf..f0fe6b5350e2 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -74,22 +74,22 @@ static struct map_desc ebsa110_io_desc[] __initdata = {
         * sparse external-decode ISAIO space
         */
        {       /* IRQ_STAT/IRQ_MCLR */
-                .virtual        = IRQ_STAT,
+                .virtual        = (unsigned long)IRQ_STAT,
                .pfn            = __phys_to_pfn(TRICK4_PHYS),
                .length         = TRICK4_SIZE,
                .type           = MT_DEVICE
        }, {    /* IRQ_MASK/IRQ_MSET */
-                .virtual        = IRQ_MASK,
+                .virtual        = (unsigned long)IRQ_MASK,
                .pfn            = __phys_to_pfn(TRICK3_PHYS),
                .length         = TRICK3_SIZE,
                .type           = MT_DEVICE
        }, {    /* SOFT_BASE */
-                .virtual        = SOFT_BASE,
+                .virtual        = (unsigned long)SOFT_BASE,
                .pfn            = __phys_to_pfn(TRICK1_PHYS),
                .length         = TRICK1_SIZE,
                .type           = MT_DEVICE
        }, {    /* PIT_BASE */
-                .virtual        = PIT_BASE,
+                .virtual        = (unsigned long)PIT_BASE,
                .pfn            = __phys_to_pfn(TRICK0_PHYS),
                .length         = TRICK0_SIZE,
                .type           = MT_DEVICE
diff --git a/arch/arm/mach-ebsa110/core.h b/arch/arm/mach-ebsa110/core.h
index c93c9e43012d..afe137ee172e 100644
--- a/arch/arm/mach-ebsa110/core.h
+++ b/arch/arm/mach-ebsa110/core.h
@@ -31,11 +31,11 @@
 #define TRICK7_PHYS             0xf3c00000
 /* Virtual addresses */
-#define PIT_BASE                0xfc000000      /* trick 0 */
+#define PIT_BASE                IOMEM(0xfc000000)       /* trick 0 */
-#define SOFT_BASE               0xfd000000      /* trick 1 */
+#define SOFT_BASE               IOMEM(0xfd000000)       /* trick 1 */
-#define IRQ_MASK                0xfe000000      /* trick 3 - read */
+#define IRQ_MASK                IOMEM(0xfe000000)       /* trick 3 - read */
-#define IRQ_MSET                0xfe000000      /* trick 3 - write */
+#define IRQ_MSET                IOMEM(0xfe000000)       /* trick 3 - write */
-#define IRQ_STAT                0xff000000      /* trick 4 - read */
+#define IRQ_STAT                IOMEM(0xff000000)       /* trick 4 - read */
-#define IRQ_MCLR                0xff000000      /* trick 4 - write */
+#define IRQ_MCLR                IOMEM(0xff000000)       /* trick 4 - write */
 #endif
diff --git a/arch/arm/mach-ebsa110/leds.c b/arch/arm/mach-ebsa110/leds.c
index 99e14e362500..0398258c20cd 100644
--- a/arch/arm/mach-ebsa110/leds.c
+++ b/arch/arm/mach-ebsa110/leds.c
@@ -1,52 +1,71 @@
 /*
- *  linux/arch/arm/mach-ebsa110/leds.c
+ * Driver for the LED found on the EBSA110 machine
+ * Based on Versatile and RealView machine LED code
 *
- *  Copyright (C) 1998 Russell King
+ * License terms: GNU General Public License (GPL) version 2
- *
+ * Author: Bryan Wu <bryan.wu@canonical.com>
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  EBSA-110 LED control routines.  We use the led as follows:
- *
- *   - Red - toggles state every 50 timer interrupts
 */
-#include <linux/module.h>
+#include <linux/kernel.h>
-#include <linux/spinlock.h>
 #include <linux/init.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include "core.h"
-static spinlock_t leds_lock;
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+static void ebsa110_led_set(struct led_classdev *cdev,
-static void ebsa110_leds_event(led_event_t ledevt)
+                              enum led_brightness b)
 {
-        unsigned long flags;
+        u8 reg = __raw_readb(SOFT_BASE);
-        spin_lock_irqsave(&leds_lock, flags);
+        if (b != LED_OFF)
+                reg |= 0x80;
+        else
+                reg &= ~0x80;
-        switch(ledevt) {
+        __raw_writeb(reg, SOFT_BASE);
-        case led_timer:
+}
-                *(volatile unsigned char *)SOFT_BASE ^= 128;
-                break;
-        default:
+static enum led_brightness ebsa110_led_get(struct led_classdev *cdev)
-                break;
+{
-        }
+        u8 reg = __raw_readb(SOFT_BASE);
-        spin_unlock_irqrestore(&leds_lock, flags);
+        return (reg & 0x80) ? LED_FULL : LED_OFF;
 }
-static int __init leds_init(void)
+static int __init ebsa110_leds_init(void)
 {
-        if (machine_is_ebsa110())
-                leds_event = ebsa110_leds_event;
+        struct led_classdev *cdev;
+        int ret;
+        if (!machine_is_ebsa110())
+                return -ENODEV;
+        cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
+        if (!cdev)
+                return -ENOMEM;
+        cdev->name = "ebsa110:0";
+        cdev->brightness_set = ebsa110_led_set;
+        cdev->brightness_get = ebsa110_led_get;
+        cdev->default_trigger = "heartbeat";
+        ret = led_classdev_register(NULL, cdev);
+        if (ret < 0) {
+                kfree(cdev);
+                return ret;
+        }
        return 0;
 }
-__initcall(leds_init);
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(ebsa110_leds_init);
+#endif
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index a472777e9eba..41383bf03d4b 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/sizes.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 4afe52aaaff3..e85bf17f2d2a 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -36,9 +36,9 @@
 #include <linux/export.h>
 #include <mach/hardware.h>
-#include <mach/fb.h>
+#include <linux/platform_data/video-ep93xx.h>
-#include <mach/ep93xx_keypad.h>
+#include <linux/platform_data/keypad-ep93xx.h>
-#include <mach/ep93xx_spi.h>
+#include <linux/platform_data/spi-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-ep93xx/dma.c b/arch/arm/mach-ep93xx/dma.c
index 16976d7bdc8a..d8bfd02f5047 100644
--- a/arch/arm/mach-ep93xx/dma.c
+++ b/arch/arm/mach-ep93xx/dma.c
@@ -25,7 +25,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
-#include <mach/dma.h>
+#include <linux/platform_data/dma-ep93xx.h>
 #include <mach/hardware.h>
 #include "soc.h"
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 337ab7cf4c16..b8f53d57a299 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -35,8 +35,8 @@
 #include <sound/cs4271.h>
 #include <mach/hardware.h>
-#include <mach/fb.h>
+#include <linux/platform_data/video-ep93xx.h>
-#include <mach/ep93xx_spi.h>
+#include <linux/platform_data/spi-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
 #include <asm/hardware/vic.h>
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index 437c34111155..7fd705b5efe4 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/sizes.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h
deleted file mode 100644
index e82c642fa53c..000000000000
--- a/arch/arm/mach-ep93xx/include/mach/dma.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-#include <linux/types.h>
-#include <linux/dmaengine.h>
-#include <linux/dma-mapping.h>
-/*
- * M2P channels.
- *
- * Note that these values are also directly used for setting the PPALLOC
- * register.
- */
-#define EP93XX_DMA_I2S1         0
-#define EP93XX_DMA_I2S2         1
-#define EP93XX_DMA_AAC1         2
-#define EP93XX_DMA_AAC2         3
-#define EP93XX_DMA_AAC3         4
-#define EP93XX_DMA_I2S3         5
-#define EP93XX_DMA_UART1        6
-#define EP93XX_DMA_UART2        7
-#define EP93XX_DMA_UART3        8
-#define EP93XX_DMA_IRDA         9
-/* M2M channels */
-#define EP93XX_DMA_SSP          10
-#define EP93XX_DMA_IDE          11
-/**
- * struct ep93xx_dma_data - configuration data for the EP93xx dmaengine
- * @port: peripheral which is requesting the channel
- * @direction: TX/RX channel
- * @name: optional name for the channel, this is displayed in /proc/interrupts
- *
- * This information is passed as private channel parameter in a filter
- * function. Note that this is only needed for slave/cyclic channels.  For
- * memcpy channels %NULL data should be passed.
- */
-struct ep93xx_dma_data {
-        int                             port;
-        enum dma_transfer_direction     direction;
-        const char                      *name;
-};
-/**
- * struct ep93xx_dma_chan_data - platform specific data for a DMA channel
- * @name: name of the channel, used for getting the right clock for the channel
- * @base: mapped registers
- * @irq: interrupt number used by this channel
- */
-struct ep93xx_dma_chan_data {
-        const char                      *name;
-        void __iomem                    *base;
-        int                             irq;
-};
-/**
- * struct ep93xx_dma_platform_data - platform data for the dmaengine driver
- * @channels: array of channels which are passed to the driver
- * @num_channels: number of channels in the array
- *
- * This structure is passed to the DMA engine driver via platform data. For
- * M2P channels, contract is that even channels are for TX and odd for RX.
- * There is no requirement for the M2M channels.
- */
-struct ep93xx_dma_platform_data {
-        struct ep93xx_dma_chan_data     *channels;
-        size_t                          num_channels;
-};
-static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan)
-{
-        return !strcmp(dev_name(chan->device->dev), "ep93xx-dma-m2p");
-}
-/**
- * ep93xx_dma_chan_direction - returns direction the channel can be used
- * @chan: channel
- *
- * This function can be used in filter functions to find out whether the
- * channel supports given DMA direction. Only M2P channels have such
- * limitation, for M2M channels the direction is configurable.
- */
-static inline enum dma_transfer_direction
-ep93xx_dma_chan_direction(struct dma_chan *chan)
-{
-        if (!ep93xx_dma_chan_is_m2p(chan))
-                return DMA_NONE;
-        /* even channels are for TX, odd for RX */
-        return (chan->chan_id % 2 == 0) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
-}
-#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h b/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h
deleted file mode 100644
index 1e2f4e97f428..000000000000
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h
- */
-#ifndef __ASM_ARCH_EP93XX_KEYPAD_H
-#define __ASM_ARCH_EP93XX_KEYPAD_H
-struct matrix_keymap_data;
-/* flags for the ep93xx_keypad driver */
-#define EP93XX_KEYPAD_DISABLE_3_KEY     (1<<0)  /* disable 3-key reset */
-#define EP93XX_KEYPAD_DIAG_MODE         (1<<1)  /* diagnostic mode */
-#define EP93XX_KEYPAD_BACK_DRIVE        (1<<2)  /* back driving mode */
-#define EP93XX_KEYPAD_TEST_MODE         (1<<3)  /* scan only column 0 */
-#define EP93XX_KEYPAD_KDIV              (1<<4)  /* 1/4 clock or 1/16 clock */
-#define EP93XX_KEYPAD_AUTOREPEAT        (1<<5)  /* enable key autorepeat */
-/**
- * struct ep93xx_keypad_platform_data - platform specific device structure
- * @keymap_data:        pointer to &matrix_keymap_data
- * @debounce:           debounce start count; terminal count is 0xff
- * @prescale:           row/column counter pre-scaler load value
- * @flags:              see above
- */
-struct ep93xx_keypad_platform_data {
-        struct matrix_keymap_data *keymap_data;
-        unsigned int    debounce;
-        unsigned int    prescale;
-        unsigned int    flags;
-};
-#define EP93XX_MATRIX_ROWS              (8)
-#define EP93XX_MATRIX_COLS              (8)
-#endif  /* __ASM_ARCH_EP93XX_KEYPAD_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h b/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h
deleted file mode 100644
index 9bb63ac13f04..000000000000
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef __ASM_MACH_EP93XX_SPI_H
-#define __ASM_MACH_EP93XX_SPI_H
-struct spi_device;
-/**
- * struct ep93xx_spi_info - EP93xx specific SPI descriptor
- * @num_chipselect: number of chip selects on this board, must be
- *                  at least one
- * @use_dma: use DMA for the transfers
- */
-struct ep93xx_spi_info {
-        int     num_chipselect;
-        bool    use_dma;
-};
-/**
- * struct ep93xx_spi_chip_ops - operation callbacks for SPI slave device
- * @setup: setup the chip select mechanism
- * @cleanup: cleanup the chip select mechanism
- * @cs_control: control the device chip select
- */
-struct ep93xx_spi_chip_ops {
-        int     (*setup)(struct spi_device *spi);
-        void    (*cleanup)(struct spi_device *spi);
-        void    (*cs_control)(struct spi_device *spi, int value);
-};
-#endif /* __ASM_MACH_EP93XX_SPI_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/fb.h b/arch/arm/mach-ep93xx/include/mach/fb.h
deleted file mode 100644
index d5ae11d7c453..000000000000
--- a/arch/arm/mach-ep93xx/include/mach/fb.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/include/mach/fb.h
- */
-#ifndef __ASM_ARCH_EP93XXFB_H
-#define __ASM_ARCH_EP93XXFB_H
-struct platform_device;
-struct fb_videomode;
-struct fb_info;
-#define EP93XXFB_USE_MODEDB             0
-/* VideoAttributes flags */
-#define EP93XXFB_STATE_MACHINE_ENABLE   (1 << 0)
-#define EP93XXFB_PIXEL_CLOCK_ENABLE     (1 << 1)
-#define EP93XXFB_VSYNC_ENABLE           (1 << 2)
-#define EP93XXFB_PIXEL_DATA_ENABLE      (1 << 3)
-#define EP93XXFB_COMPOSITE_SYNC         (1 << 4)
-#define EP93XXFB_SYNC_VERT_HIGH         (1 << 5)
-#define EP93XXFB_SYNC_HORIZ_HIGH        (1 << 6)
-#define EP93XXFB_SYNC_BLANK_HIGH        (1 << 7)
-#define EP93XXFB_PCLK_FALLING           (1 << 8)
-#define EP93XXFB_ENABLE_AC              (1 << 9)
-#define EP93XXFB_ENABLE_LCD             (1 << 10)
-#define EP93XXFB_ENABLE_CCIR            (1 << 12)
-#define EP93XXFB_USE_PARALLEL_INTERFACE (1 << 13)
-#define EP93XXFB_ENABLE_INTERRUPT       (1 << 14)
-#define EP93XXFB_USB_INTERLACE          (1 << 16)
-#define EP93XXFB_USE_EQUALIZATION       (1 << 17)
-#define EP93XXFB_USE_DOUBLE_HORZ        (1 << 18)
-#define EP93XXFB_USE_DOUBLE_VERT        (1 << 19)
-#define EP93XXFB_USE_BLANK_PIXEL        (1 << 20)
-#define EP93XXFB_USE_SDCSN0             (0 << 21)
-#define EP93XXFB_USE_SDCSN1             (1 << 21)
-#define EP93XXFB_USE_SDCSN2             (2 << 21)
-#define EP93XXFB_USE_SDCSN3             (3 << 21)
-#define EP93XXFB_ENABLE                 (EP93XXFB_STATE_MACHINE_ENABLE  | \
-                                         EP93XXFB_PIXEL_CLOCK_ENABLE    | \
-                                         EP93XXFB_VSYNC_ENABLE          | \
-                                         EP93XXFB_PIXEL_DATA_ENABLE)
-struct ep93xxfb_mach_info {
-        unsigned int                    num_modes;
-        const struct fb_videomode       *modes;
-        const struct fb_videomode       *default_mode;
-        int                             bpp;
-        unsigned int                    flags;
-        int     (*setup)(struct platform_device *pdev);
-        void    (*teardown)(struct platform_device *pdev);
-        void    (*blank)(int blank_mode, struct fb_info *info);
-};
-#endif /* __ASM_ARCH_EP93XXFB_H */
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 33dc07917417..0eb3f17a6fa2 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -22,7 +22,7 @@
 #include <linux/i2c-gpio.h>
 #include <mach/hardware.h>
-#include <mach/fb.h>
+#include <linux/platform_data/video-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
 #include <asm/hardware/vic.h>
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index 01abd3516a77..50043eef1cf2 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -28,7 +28,7 @@
 #include <linux/mtd/nand.h>
 #include <mach/hardware.h>
-#include <mach/fb.h>
+#include <linux/platform_data/video-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
 #include <asm/hardware/vic.h>
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 75cab2d7ec73..3c4c233391dc 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -21,7 +21,6 @@
 #include <linux/mtd/partitions.h>
 #include <mach/hardware.h>
-#include <mach/ts72xx.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
@@ -29,30 +28,31 @@
 #include <asm/mach/arch.h>
 #include "soc.h"
+#include "ts72xx.h"
 static struct map_desc ts72xx_io_desc[] __initdata = {
        {
-                .virtual        = TS72XX_MODEL_VIRT_BASE,
+                .virtual        = (unsigned long)TS72XX_MODEL_VIRT_BASE,
                .pfn            = __phys_to_pfn(TS72XX_MODEL_PHYS_BASE),
                .length         = TS72XX_MODEL_SIZE,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = TS72XX_OPTIONS_VIRT_BASE,
+                .virtual        = (unsigned long)TS72XX_OPTIONS_VIRT_BASE,
                .pfn            = __phys_to_pfn(TS72XX_OPTIONS_PHYS_BASE),
                .length         = TS72XX_OPTIONS_SIZE,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = TS72XX_OPTIONS2_VIRT_BASE,
+                .virtual        = (unsigned long)TS72XX_OPTIONS2_VIRT_BASE,
                .pfn            = __phys_to_pfn(TS72XX_OPTIONS2_PHYS_BASE),
                .length         = TS72XX_OPTIONS2_SIZE,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = TS72XX_RTC_INDEX_VIRT_BASE,
+                .virtual        = (unsigned long)TS72XX_RTC_INDEX_VIRT_BASE,
                .pfn            = __phys_to_pfn(TS72XX_RTC_INDEX_PHYS_BASE),
                .length         = TS72XX_RTC_INDEX_SIZE,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = TS72XX_RTC_DATA_VIRT_BASE,
+                .virtual        = (unsigned long)TS72XX_RTC_DATA_VIRT_BASE,
                .pfn            = __phys_to_pfn(TS72XX_RTC_DATA_PHYS_BASE),
                .length         = TS72XX_RTC_DATA_SIZE,
                .type           = MT_DEVICE,
diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/ts72xx.h
index f1397a13e76b..071feaa30adc 100644
--- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h
+++ b/arch/arm/mach-ep93xx/ts72xx.h
@@ -14,7 +14,7 @@
 */
 #define TS72XX_MODEL_PHYS_BASE          0x22000000
-#define TS72XX_MODEL_VIRT_BASE          0xfebff000
+#define TS72XX_MODEL_VIRT_BASE          IOMEM(0xfebff000)
 #define TS72XX_MODEL_SIZE               0x00001000
 #define TS72XX_MODEL_TS7200             0x00
@@ -26,7 +26,7 @@
 #define TS72XX_OPTIONS_PHYS_BASE        0x22400000
-#define TS72XX_OPTIONS_VIRT_BASE        0xfebfe000
+#define TS72XX_OPTIONS_VIRT_BASE        IOMEM(0xfebfe000)
 #define TS72XX_OPTIONS_SIZE             0x00001000
 #define TS72XX_OPTIONS_COM2_RS485       0x02
@@ -34,18 +34,18 @@
 #define TS72XX_OPTIONS2_PHYS_BASE       0x22800000
-#define TS72XX_OPTIONS2_VIRT_BASE       0xfebfd000
+#define TS72XX_OPTIONS2_VIRT_BASE       IOMEM(0xfebfd000)
 #define TS72XX_OPTIONS2_SIZE            0x00001000
 #define TS72XX_OPTIONS2_TS9420          0x04
 #define TS72XX_OPTIONS2_TS9420_BOOT     0x02
-#define TS72XX_RTC_INDEX_VIRT_BASE      0xfebf9000
+#define TS72XX_RTC_INDEX_VIRT_BASE      IOMEM(0xfebf9000)
 #define TS72XX_RTC_INDEX_PHYS_BASE      0x10800000
 #define TS72XX_RTC_INDEX_SIZE           0x00001000
-#define TS72XX_RTC_DATA_VIRT_BASE       0xfebf8000
+#define TS72XX_RTC_DATA_VIRT_BASE       IOMEM(0xfebf8000)
 #define TS72XX_RTC_DATA_PHYS_BASE       0x11700000
 #define TS72XX_RTC_DATA_SIZE            0x00001000
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index 2905a4929bdc..ba92e25e3016 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -30,8 +30,8 @@
 #include <linux/mmc/host.h>
 #include <mach/hardware.h>
-#include <mach/fb.h>
+#include <linux/platform_data/video-ep93xx.h>
-#include <mach/ep93xx_spi.h>
+#include <linux/platform_data/spi-ep93xx.h>
 #include <mach/gpio-ep93xx.h>
 #include <asm/hardware/vic.h>
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index b5b4c8c9db11..4372075c551f 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -221,6 +221,7 @@ config MACH_SMDKV310
        select EXYNOS4_SETUP_KEYPAD
        select EXYNOS4_SETUP_SDHCI
        select EXYNOS4_SETUP_USB_PHY
+        select S3C24XX_PWM
        help
          Machine support for Samsung SMDKV310
@@ -348,6 +349,7 @@ config MACH_ORIGEN
        select EXYNOS4_SETUP_FIMD0
        select EXYNOS4_SETUP_SDHCI
        select EXYNOS4_SETUP_USB_PHY
+        select S3C24XX_PWM
        help
          Machine support for ORIGEN based on Samsung EXYNOS4210
@@ -383,6 +385,7 @@ config MACH_SMDK4212
        select EXYNOS4_SETUP_KEYPAD
        select EXYNOS4_SETUP_SDHCI
        select EXYNOS4_SETUP_USB_PHY
+        select S3C24XX_PWM
        help
          Machine support for Samsung SMDK4212
@@ -405,6 +408,8 @@ config MACH_EXYNOS4_DT
        select USE_OF
        select ARM_AMBA
        select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
+        select PINCTRL
+        select PINCTRL_EXYNOS4
        help
          Machine support for Samsung Exynos4 machine with device tree enabled.
          Select this if a fdt blob is available for the Exynos4 SoC based board.
@@ -418,8 +423,8 @@ config MACH_EXYNOS5_DT
        select USE_OF
        select ARM_AMBA
        help
-          Machine support for Samsung Exynos4 machine with device tree enabled.
+          Machine support for Samsung EXYNOS5 machine with device tree enabled.
-          Select this if a fdt blob is available for the EXYNOS4 SoC based board.
+          Select this if a fdt blob is available for the EXYNOS5 SoC based board.
 if ARCH_EXYNOS4
diff --git a/arch/arm/mach-exynos/Makefile.boot b/arch/arm/mach-exynos/Makefile.boot
index 31bd181b0514..b9862e22bf10 100644
--- a/arch/arm/mach-exynos/Makefile.boot
+++ b/arch/arm/mach-exynos/Makefile.boot
@@ -1,5 +1,2 @@
   zreladdr-y   += 0x40008000
 params_phys-y   := 0x40000100
-dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb
-dtb-$(CONFIG_MACH_EXYNOS5_DT) += exynos5250-smdk5250.dtb
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 2f51293c1875..6a45c9a9abe9 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -501,6 +501,10 @@ static struct clk exynos4_init_clocks_off[] = {
                .enable         = exynos4_clk_ip_cam_ctrl,
                .ctrlbit        = (1 << 3),
        }, {
+                .name           = "tsi",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
                .name           = "hsmmc",
                .devname        = "exynos4-sdhci.0",
                .parent         = &exynos4_clk_aclk_133.clk,
@@ -530,6 +534,14 @@ static struct clk exynos4_init_clocks_off[] = {
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 9),
        }, {
+                .name           = "onenand",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 15),
+        }, {
+                .name           = "nfcon",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
                .name           = "dac",
                .devname        = "s5p-sdo",
                .enable         = exynos4_clk_ip_tv_ctrl,
@@ -615,6 +627,25 @@ static struct clk exynos4_init_clocks_off[] = {
                .enable         = exynos4_clk_ip_peril_ctrl,
                .ctrlbit        = (1 << 21),
        }, {
+                .name           = "pcm",
+                .devname        = "samsung-pcm.1",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 22),
+        }, {
+                .name           = "pcm",
+                .devname        = "samsung-pcm.2",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 23),
+        }, {
+                .name           = "slimbus",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "spdif",
+                .devname        = "samsung-spdif",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 26),
+        }, {
                .name           = "ac97",
                .devname        = "samsung-ac97",
                .enable         = exynos4_clk_ip_peril_ctrl,
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c67066..c44ca1ee1b8d 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -166,11 +166,6 @@ static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
 }
-static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
-}
 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 {
        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
@@ -552,6 +547,68 @@ static struct clksrc_clk exynos5_clk_aclk_66 = {
        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
 };
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
+        .clk    = {
+                .name           = "mout_aclk_300_gscl_mid",
+        },
+        .sources = &exynos5_clkset_aclk,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
+};
+static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
+        [0] = &exynos5_clk_sclk_vpll.clk,
+        [1] = &exynos5_clk_mout_cpll.clk,
+};
+static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
+        .sources        = exynos5_clkset_aclk_300_mid1_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
+};
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
+        .clk    = {
+                .name           = "mout_aclk_300_gscl_mid1",
+        },
+        .sources = &exynos5_clkset_aclk_300_gscl_mid1,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
+};
+static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
+        [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
+        [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
+};
+static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
+        .sources        = exynos5_clkset_aclk_300_gscl_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
+};
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
+        .clk    = {
+                .name           = "mout_aclk_300_gscl",
+        },
+        .sources = &exynos5_clkset_aclk_300_gscl,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
+};
+static struct clk *exynos5_clk_src_gscl_300_list[] = {
+        [0] = &clk_ext_xtal_mux,
+        [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
+};
+static struct clksrc_sources exynos5_clk_src_gscl_300 = {
+        .sources        = exynos5_clk_src_gscl_300_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
+};
+static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
+        .clk    = {
+                .name           = "aclk_300_gscl",
+        },
+        .sources = &exynos5_clk_src_gscl_300,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
+};
 static struct clk exynos5_init_clocks_off[] = {
        {
                .name           = "timers",
@@ -569,35 +626,30 @@ static struct clk exynos5_init_clocks_off[] = {
                .enable         = exynos5_clk_ip_peris_ctrl,
                .ctrlbit        = (1 << 19),
        }, {
-                .name           = "hsmmc",
+                .name           = "biu",        /* bus interface unit clock */
-                .devname        = "exynos4-sdhci.0",
+                .devname        = "dw_mmc.0",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 12),
        }, {
-                .name           = "hsmmc",
+                .name           = "biu",
-                .devname        = "exynos4-sdhci.1",
+                .devname        = "dw_mmc.1",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 13),
        }, {
-                .name           = "hsmmc",
+                .name           = "biu",
-                .devname        = "exynos4-sdhci.2",
+                .devname        = "dw_mmc.2",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 14),
        }, {
-                .name           = "hsmmc",
+                .name           = "biu",
-                .devname        = "exynos4-sdhci.3",
+                .devname        = "dw_mmc.3",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 15),
        }, {
-                .name           = "dwmci",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
                .name           = "sata",
                .devname        = "ahci",
                .enable         = exynos5_clk_ip_fsys_ctrl,
@@ -672,10 +724,6 @@ static struct clk exynos5_init_clocks_off[] = {
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 7),
        }, {
-                .name           = "gps",
-                .enable         = exynos5_clk_ip_gps_ctrl,
-                .ctrlbit        = ((1 << 3) | (1 << 2) | (1 << 0)),
-        }, {
                .name           = "nfcon",
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 22),
@@ -764,6 +812,26 @@ static struct clk exynos5_init_clocks_off[] = {
                .enable         = exynos5_clk_ip_peric_ctrl,
                .ctrlbit        = (1 << 18),
        }, {
+                .name           = "gscl",
+                .devname        = "exynos-gsc.0",
+                .enable         = exynos5_clk_ip_gscl_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "gscl",
+                .devname        = "exynos-gsc.1",
+                .enable         = exynos5_clk_ip_gscl_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "gscl",
+                .devname        = "exynos-gsc.2",
+                .enable         = exynos5_clk_ip_gscl_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "gscl",
+                .devname        = "exynos-gsc.3",
+                .enable         = exynos5_clk_ip_gscl_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
                .name           = SYSMMU_CLOCK_NAME,
                .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
                .enable         = &exynos5_clk_ip_mfc_ctrl,
@@ -891,6 +959,13 @@ static struct clk exynos5_clk_mdma1 = {
        .ctrlbit        = (1 << 4),
 };
+static struct clk exynos5_clk_fimd1 = {
+        .name           = "fimd",
+        .devname        = "exynos5-fb.1",
+        .enable         = exynos5_clk_ip_disp1_ctrl,
+        .ctrlbit        = (1 << 0),
+};
 struct clk *exynos5_clkset_group_list[] = {
        [0] = &clk_ext_xtal_mux,
        [1] = NULL,
@@ -1015,8 +1090,8 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
        .clk    = {
-                .name           = "sclk_mmc",
+                .name           = "ciu",        /* card interface unit clock */
-                .devname        = "exynos4-sdhci.0",
+                .devname        = "dw_mmc.0",
                .parent         = &exynos5_clk_dout_mmc0.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 0),
@@ -1026,8 +1101,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
        .clk    = {
-                .name           = "sclk_mmc",
+                .name           = "ciu",
-                .devname        = "exynos4-sdhci.1",
+                .devname        = "dw_mmc.1",
                .parent         = &exynos5_clk_dout_mmc1.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 4),
@@ -1037,8 +1112,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
        .clk    = {
-                .name           = "sclk_mmc",
+                .name           = "ciu",
-                .devname        = "exynos4-sdhci.2",
+                .devname        = "dw_mmc.2",
                .parent         = &exynos5_clk_dout_mmc2.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 8),
@@ -1048,8 +1123,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
        .clk    = {
-                .name           = "sclk_mmc",
+                .name           = "ciu",
-                .devname        = "exynos4-sdhci.3",
+                .devname        = "dw_mmc.3",
                .parent         = &exynos5_clk_dout_mmc3.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 12),
@@ -1120,27 +1195,21 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
 };
+struct clksrc_clk exynos5_clk_sclk_fimd1 = {
+        .clk    = {
+                .name           = "sclk_fimd",
+                .devname        = "exynos5-fb.1",
+                .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+};
 static struct clksrc_clk exynos5_clksrcs[] = {
        {
                .clk    = {
-                        .name           = "sclk_dwmci",
-                        .parent         = &exynos5_clk_dout_mmc4.clk,
-                        .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimd",
-                        .devname        = "s3cfb.1",
-                        .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
                        .name           = "aclk_266_gscl",
                },
                .sources = &clk_src_gscl_266,
@@ -1225,6 +1294,10 @@ static struct clksrc_clk *exynos5_sysclks[] = {
        &exynos5_clk_aclk_266,
        &exynos5_clk_aclk_200,
        &exynos5_clk_aclk_166,
+        &exynos5_clk_aclk_300_gscl,
+        &exynos5_clk_mout_aclk_300_gscl,
+        &exynos5_clk_mout_aclk_300_gscl_mid,
+        &exynos5_clk_mout_aclk_300_gscl_mid1,
        &exynos5_clk_aclk_66_pre,
        &exynos5_clk_aclk_66,
        &exynos5_clk_dout_mmc0,
@@ -1240,12 +1313,14 @@ static struct clksrc_clk *exynos5_sysclks[] = {
        &exynos5_clk_mdout_spi0,
        &exynos5_clk_mdout_spi1,
        &exynos5_clk_mdout_spi2,
+        &exynos5_clk_sclk_fimd1,
 };
 static struct clk *exynos5_clk_cdev[] = {
        &exynos5_clk_pdma0,
        &exynos5_clk_pdma1,
        &exynos5_clk_mdma1,
+        &exynos5_clk_fimd1,
 };
 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
@@ -1274,6 +1349,7 @@ static struct clk_lookup exynos5_clk_lookup[] = {
        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
+        CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
 };
 static unsigned long exynos5_epll_get_rate(struct clk *clk)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4eb39cdf75ea..715b690e5009 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -980,6 +980,32 @@ static int __init exynos_init_irq_eint(void)
 {
        int irq;
+#ifdef CONFIG_PINCTRL_SAMSUNG
+        /*
+         * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
+         * functionality along with support for external gpio and wakeup
+         * interrupts. If the samsung pinctrl driver is enabled and includes
+         * the wakeup interrupt support, then the setting up external wakeup
+         * interrupts here can be skipped. This check here is temporary to
+         * allow exynos4 platforms that do not use Samsung pinctrl driver to
+         * co-exist with platforms that do. When all of the Samsung Exynos4
+         * platforms switch over to using the pinctrl driver, the wakeup
+         * interrupt support code here can be completely removed.
+         */
+        struct device_node *pctrl_np, *wkup_np;
+        const char *pctrl_compat = "samsung,pinctrl-exynos4210";
+        const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
+        for_each_compatible_node(pctrl_np, NULL, pctrl_compat) {
+                if (of_device_is_available(pctrl_np)) {
+                        wkup_np = of_find_compatible_node(pctrl_np, NULL,
+                                                        wkup_compat);
+                        if (wkup_np)
+                                return -ENODEV;
+                }
+        }
+#endif
        if (soc_is_exynos5250())
                exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
        else
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index aed2eeb06517..dac146df79ac 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -14,6 +14,7 @@
 extern struct sys_timer exynos4_timer;
+struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
 void exynos5_init_irq(void);
@@ -59,4 +60,8 @@ void exynos4212_register_clocks(void);
 #define exynos4212_register_clocks()
 #endif
+extern struct smp_operations exynos_smp_ops;
+extern void exynos_cpu_die(unsigned int cpu);
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
index b33a5b67b547..ae321c7cb15f 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -16,7 +16,7 @@
 #include <linux/gpio.h>
 #include <plat/gpio-cfg.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 #include <mach/map.h>
 #include <mach/dma.h>
diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c
index b8e75300c77d..14ed7951a2c6 100644
--- a/arch/arm/mach-exynos/dev-ohci.c
+++ b/arch/arm/mach-exynos/dev-ohci.c
@@ -15,7 +15,7 @@
 #include <mach/irqs.h>
 #include <mach/map.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-exynos.h>
 #include <plat/devs.h>
 #include <plat/usb-phy.h>
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index f60b66dbcf84..21d568b3b149 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -303,10 +303,12 @@ static int __init exynos_dma_init(void)
        dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
        dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
+        dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask);
        amba_device_register(&exynos_pdma0_device, &iomem_resource);
        dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
        dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
+        dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask);
        amba_device_register(&exynos_pdma1_device, &iomem_resource);
        dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 9c17a0a43858..f4d7dd20cdac 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -21,7 +21,7 @@
 #include <mach/regs-pmu.h>
-extern volatile int pen_release;
+#include "common.h"
 static inline void cpu_enter_lowpower(void)
 {
@@ -95,17 +95,12 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
        }
 }
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
 /*
 * platform-specific code to shutdown a CPU
 *
 * Called with IRQs disabled
 */
-void platform_cpu_die(unsigned int cpu)
+void __ref exynos_cpu_die(unsigned int cpu)
 {
        int spurious = 0;
@@ -124,12 +119,3 @@ void platform_cpu_die(unsigned int cpu)
        if (spurious)
                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 }
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72b675b3e4b..8480849affb9 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -89,7 +89,7 @@
 #define EXYNOS4_PA_L2CC                 0x10502000
 #define EXYNOS4_PA_MDMA0                0x10810000
-#define EXYNOS4_PA_MDMA1                0x12840000
+#define EXYNOS4_PA_MDMA1                0x12850000
 #define EXYNOS4_PA_PDMA0                0x12680000
 #define EXYNOS4_PA_PDMA1                0x12690000
 #define EXYNOS5_PA_MDMA0                0x10800000
@@ -121,6 +121,11 @@
 #define EXYNOS4_PA_SYSMMU_MFC_L         0x13620000
 #define EXYNOS4_PA_SYSMMU_MFC_R         0x13630000
+#define EXYNOS5_PA_GSC0                 0x13E00000
+#define EXYNOS5_PA_GSC1                 0x13E10000
+#define EXYNOS5_PA_GSC2                 0x13E20000
+#define EXYNOS5_PA_GSC3                 0x13E30000
 #define EXYNOS5_PA_SYSMMU_MDMA1         0x10A40000
 #define EXYNOS5_PA_SYSMMU_SSS           0x10A50000
 #define EXYNOS5_PA_SYSMMU_2D            0x10A60000
@@ -131,7 +136,6 @@
 #define EXYNOS5_PA_SYSMMU_JPEG          0x11F20000
 #define EXYNOS5_PA_SYSMMU_IOP           0x12360000
 #define EXYNOS5_PA_SYSMMU_RTIC          0x12370000
-#define EXYNOS5_PA_SYSMMU_GPS           0x12630000
 #define EXYNOS5_PA_SYSMMU_ISP           0x13260000
 #define EXYNOS5_PA_SYSMMU_DRC           0x12370000
 #define EXYNOS5_PA_SYSMMU_SCALERC       0x13280000
@@ -173,6 +177,10 @@
 #define EXYNOS4_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
 #define EXYNOS4_PA_DWMCI                0x12550000
+#define EXYNOS5_PA_DWMCI0               0x12200000
+#define EXYNOS5_PA_DWMCI1               0x12210000
+#define EXYNOS5_PA_DWMCI2               0x12220000
+#define EXYNOS5_PA_DWMCI3               0x12230000
 #define EXYNOS4_PA_HSOTG                0x12480000
 #define EXYNOS4_PA_USB_HSPHY            0x125B0000
diff --git a/arch/arm/mach-exynos/include/mach/ohci.h b/arch/arm/mach-exynos/include/mach/ohci.h
deleted file mode 100644
index c256c595be5e..000000000000
--- a/arch/arm/mach-exynos/include/mach/ohci.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co.Ltd
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef __MACH_EXYNOS_OHCI_H
-#define __MACH_EXYNOS_OHCI_H
-struct exynos4_ohci_platdata {
-        int (*phy_init)(struct platform_device *pdev, int type);
-        int (*phy_exit)(struct platform_device *pdev, int type);
-};
-extern void exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd);
-#endif /* __MACH_EXYNOS_OHCI_H */
diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h
index 998daf2add92..88a4543b0001 100644
--- a/arch/arm/mach-exynos/include/mach/sysmmu.h
+++ b/arch/arm/mach-exynos/include/mach/sysmmu.h
@@ -58,7 +58,7 @@ static inline void platform_set_sysmmu(
 #endif
 #else /* !CONFIG_EXYNOS_DEV_SYSMMU */
-#define platform_set_sysmmu(dev, sysmmu) do { } while (0)
+#define platform_set_sysmmu(sysmmu, dev) do { } while (0)
 #endif
 #define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index 5a3daa0168d8..3f37a5e8a1f4 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -199,6 +199,7 @@ static void __init armlex4210_machine_init(void)
 MACHINE_START(ARMLEX4210, "ARMLEX4210")
        /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
        .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = armlex4210_map_io,
        .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index b2b5d5faa748..e58d786faf78 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -1,5 +1,5 @@
 /*
- * Samsung's Exynos4210 flattened device tree enabled machine
+ * Samsung's EXYNOS4 flattened device tree enabled machine
 *
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com
@@ -36,7 +36,7 @@
 * at some point, the drivers should be capable of parsing all the platform
 * data from the device tree.
 */
-static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
+static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
                                "exynos4210-uart.0", NULL),
        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
@@ -55,6 +55,20 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
                                "exynos4-sdhci.3", NULL),
        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
                                "s3c2440-i2c.0", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
+                                "s3c2440-i2c.1", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
+                                "s3c2440-i2c.2", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
+                                "s3c2440-i2c.3", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
+                                "s3c2440-i2c.4", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
+                                "s3c2440-i2c.5", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
+                                "s3c2440-i2c.6", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
+                                "s3c2440-i2c.7", NULL),
        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
                                "exynos4210-spi.0", NULL),
        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
@@ -66,19 +80,19 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
        {},
 };
-static void __init exynos4210_dt_map_io(void)
+static void __init exynos4_dt_map_io(void)
 {
        exynos_init_io(NULL, 0);
        s3c24xx_init_clocks(24000000);
 }
-static void __init exynos4210_dt_machine_init(void)
+static void __init exynos4_dt_machine_init(void)
 {
        of_platform_populate(NULL, of_default_bus_match_table,
-                                exynos4210_auxdata_lookup, NULL);
+                                exynos4_auxdata_lookup, NULL);
 }
-static char const *exynos4210_dt_compat[] __initdata = {
+static char const *exynos4_dt_compat[] __initdata = {
        "samsung,exynos4210",
        NULL
 };
@@ -86,11 +100,11 @@ static char const *exynos4210_dt_compat[] __initdata = {
 DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
        /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
        .init_irq       = exynos4_init_irq,
-        .map_io         = exynos4210_dt_map_io,
+        .map_io         = exynos4_dt_map_io,
        .handle_irq     = gic_handle_irq,
-        .init_machine   = exynos4210_dt_machine_init,
+        .init_machine   = exynos4_dt_machine_init,
        .init_late      = exynos_init_late,
        .timer          = &exynos4_timer,
-        .dt_compat      = exynos4210_dt_compat,
+        .dt_compat      = exynos4_dt_compat,
        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index ef770bc2318f..db1cd8eacf28 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -47,6 +47,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                                "s3c2440-i2c.0", NULL),
        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
                                "s3c2440-i2c.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
+                                "dw_mmc.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
+                                "dw_mmc.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
+                                "dw_mmc.2", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
+                                "dw_mmc.3", NULL),
        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
                                "exynos4210-spi.0", NULL),
        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
@@ -56,6 +64,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
+                                "exynos-gsc.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
+                                "exynos-gsc.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
+                                "exynos-gsc.2", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
+                                "exynos-gsc.3", NULL),
        {},
 };
@@ -79,6 +95,7 @@ static char const *exynos5250_dt_compat[] __initdata = {
 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
        .init_irq       = exynos5_init_irq,
+        .smp            = smp_ops(exynos_smp_ops),
        .map_io         = exynos5250_dt_map_io,
        .handle_irq     = gic_handle_irq,
        .init_machine   = exynos5250_dt_machine_init,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index ea785fcaf6c3..c05d7aa84031 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -29,6 +29,7 @@
 #include <drm/exynos_drm.h>
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include <media/m5mols.h>
 #include <media/s5k6aa.h>
 #include <media/s5p_fimc.h>
@@ -39,20 +40,19 @@
 #include <asm/mach-types.h>
 #include <plat/adc.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/regs-serial.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
-#include <plat/ehci.h>
+#include <linux/platform_data/usb-ehci-s5p.h>
 #include <plat/clock.h>
 #include <plat/gpio-cfg.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/mfc.h>
 #include <plat/fimc-core.h>
 #include <plat/camport.h>
-#include <plat/mipi_csis.h>
+#include <linux/platform_data/mipi-csis.h>
 #include <mach/map.h>
@@ -378,10 +378,10 @@ static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
 };
 static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* USB */
-        REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
+        REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */
 };
 static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
-        REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
+        REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
 };
 static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
        REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
@@ -1180,9 +1180,7 @@ static struct platform_device cam_8m_12v_fixed_rdev = {
 static struct s5p_platform_mipi_csis mipi_csis_platdata = {
        .clk_rate       = 166000000UL,
        .lanes          = 2,
-        .alignment      = 32,
        .hs_settle      = 12,
-        .phy_enable     = s5p_csis_phy_enable,
 };
 #define GPIO_CAM_MEGA_RST       EXYNOS4_GPY3(7) /* ISP_RESET */
@@ -1226,7 +1224,6 @@ static struct s5p_fimc_isp_info nuri_camera_sensors[] = {
                .bus_type       = FIMC_MIPI_CSI2,
                .board_info     = &m5mols_board_info,
                .clk_frequency  = 24000000UL,
-                .csi_data_align = 32,
        },
 };
@@ -1383,6 +1380,7 @@ static void __init nuri_machine_init(void)
 MACHINE_START(NURI, "NURI")
        /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
        .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = nuri_map_io,
        .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 4e574c24581c..9adf491674ea 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -15,6 +15,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/input.h>
+#include <linux/pwm.h>
 #include <linux/pwm_backlight.h>
 #include <linux/gpio_keys.h>
 #include <linux/i2c.h>
@@ -29,14 +30,14 @@
 #include <asm/mach-types.h>
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include <plat/regs-serial.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/sdhci.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/ehci.h>
+#include <linux/platform_data/usb-ehci-s5p.h>
 #include <plat/clock.h>
 #include <plat/gpio-cfg.h>
 #include <plat/backlight.h>
@@ -44,7 +45,7 @@
 #include <plat/mfc.h>
 #include <plat/hdmi.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-exynos.h>
 #include <mach/map.h>
 #include <drm/exynos_drm.h>
@@ -96,12 +97,12 @@ static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
 };
 static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
-        REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
+        REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */
        REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
        REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
 };
 static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
-        REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
+        REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
 };
 static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
        REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
@@ -614,6 +615,10 @@ static struct platform_device origen_lcd_hv070wsa = {
        .dev.platform_data      = &origen_lcd_hv070wsa_data,
 };
+static struct pwm_lookup origen_pwm_lookup[] = {
+        PWM_LOOKUP("s3c24xx-pwm.0", 0, "pwm-backlight.0", NULL),
+};
 #ifdef CONFIG_DRM_EXYNOS
 static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
        .panel  = {
@@ -798,6 +803,7 @@ static void __init origen_machine_init(void)
        platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
+        pwm_add_table(origen_pwm_lookup, ARRAY_SIZE(origen_pwm_lookup));
        samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
        origen_bt_setup();
@@ -806,6 +812,7 @@ static void __init origen_machine_init(void)
 MACHINE_START(ORIGEN, "ORIGEN")
        /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
        .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = origen_map_io,
        .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index b26beb13ebef..730f1ac65928 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -17,6 +17,7 @@
 #include <linux/mfd/max8997.h>
 #include <linux/mmc/host.h>
 #include <linux/platform_device.h>
+#include <linux/pwm.h>
 #include <linux/pwm_backlight.h>
 #include <linux/regulator/machine.h>
 #include <linux/serial_core.h>
@@ -26,16 +27,16 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
+#include <video/samsung_fimd.h>
 #include <plat/backlight.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/keypad.h>
 #include <plat/mfc.h>
-#include <plat/regs-fb.h>
 #include <plat/regs-serial.h>
 #include <plat/sdhci.h>
@@ -222,6 +223,10 @@ static struct platform_pwm_backlight_data smdk4x12_bl_data = {
        .pwm_period_ns  = 1000,
 };
+static struct pwm_lookup smdk4x12_pwm_lookup[] = {
+        PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL),
+};
 static uint32_t smdk4x12_keymap[] __initdata = {
        /* KEY(row, col, keycode) */
        KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3),
@@ -349,6 +354,7 @@ static void __init smdk4x12_machine_init(void)
                                ARRAY_SIZE(smdk4x12_i2c_devs7));
        samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
+        pwm_add_table(smdk4x12_pwm_lookup, ARRAY_SIZE(smdk4x12_pwm_lookup));
        samsung_keypad_set_platdata(&smdk4x12_keypad_data);
@@ -370,6 +376,7 @@ static void __init smdk4x12_machine_init(void)
 MACHINE_START(SMDK4212, "SMDK4212")
        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
        .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = smdk4x12_map_io,
        .handle_irq     = gic_handle_irq,
@@ -383,6 +390,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
        /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
        .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = smdk4x12_map_io,
        .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 73f2bce097e1..ee4fb1a9cb72 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -18,6 +18,7 @@
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/input.h>
+#include <linux/pwm.h>
 #include <linux/pwm_backlight.h>
 #include <linux/platform_data/s3c-hsotg.h>
@@ -26,24 +27,24 @@
 #include <asm/mach-types.h>
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-srom.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 #include <plat/backlight.h>
 #include <plat/mfc.h>
-#include <plat/ehci.h>
+#include <linux/platform_data/usb-ehci-s5p.h>
 #include <plat/clock.h>
 #include <plat/hdmi.h>
 #include <mach/map.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-exynos.h>
 #include <drm/exynos_drm.h>
 #include "common.h"
@@ -360,6 +361,10 @@ static struct i2c_board_info hdmiphy_info = {
        I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
 };
+static struct pwm_lookup smdkv310_pwm_lookup[] = {
+        PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL),
+};
 static void s5p_tv_setup(void)
 {
        /* direct HPD to HDMI chip */
@@ -399,6 +404,8 @@ static void __init smdkv310_machine_init(void)
        samsung_keypad_set_platdata(&smdkv310_keypad_data);
        samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
+        pwm_add_table(smdkv310_pwm_lookup, ARRAY_SIZE(smdkv310_pwm_lookup));
 #ifdef CONFIG_DRM_EXYNOS
        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
        exynos4_fimd0_gpio_setup_24bpp();
@@ -417,6 +424,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
        /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
        .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = smdkv310_map_io,
        .handle_irq     = gic_handle_irq,
@@ -429,6 +437,7 @@ MACHINE_END
 MACHINE_START(SMDKC210, "SMDKC210")
        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
        .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = smdkv310_map_io,
        .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 4d1f40d44ed1..ebc9dd339a38 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -30,20 +30,20 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
+#include <video/samsung_fimd.h>
 #include <plat/regs-serial.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 #include <plat/fb.h>
 #include <plat/mfc.h>
 #include <plat/sdhci.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/fimc-core.h>
 #include <plat/s5p-time.h>
 #include <plat/camport.h>
-#include <plat/mipi_csis.h>
+#include <linux/platform_data/mipi-csis.h>
 #include <mach/map.h>
@@ -209,7 +209,7 @@ static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
        REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
        REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
-        REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
+        REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"),
 };
 static struct regulator_init_data lp3974_ldo3_data = {
@@ -273,7 +273,7 @@ static struct regulator_init_data lp3974_ldo6_data = {
 };
 static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
-        REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"),
+        REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"),
 };
 static struct regulator_init_data lp3974_ldo7_data = {
@@ -942,9 +942,7 @@ static struct platform_device cam_s_if_fixed_reg_dev = {
 static struct s5p_platform_mipi_csis mipi_csis_platdata = {
        .clk_rate       = 166000000UL,
        .lanes          = 2,
-        .alignment      = 32,
        .hs_settle      = 12,
-        .phy_enable     = s5p_csis_phy_enable,
 };
 #define GPIO_CAM_LEVEL_EN(n)    EXYNOS4_GPE4(n + 3)
@@ -1008,7 +1006,6 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = {
                .board_info     = &m5mols_board_info,
                .i2c_bus_num    = 0,
                .clk_frequency  = 24000000UL,
-                .csi_data_align = 32,
        },
 };
@@ -1155,6 +1152,7 @@ static void __init universal_machine_init(void)
 MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
        /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
        .atag_offset    = 0x100,
+        .smp            = smp_ops(exynos_smp_ops),
        .init_irq       = exynos4_init_irq,
        .map_io         = universal_map_io,
        .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 36c3984aaa47..f93d820ecab5 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -32,19 +32,14 @@
 #include <plat/cpu.h>
+#include "common.h"
 extern void exynos4_secondary_startup(void);
 #define CPU1_BOOT_REG           (samsung_rev() == EXYNOS4210_REV_1_1 ? \
                                S5P_INFORM5 : S5P_VA_SYSRAM)
 /*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-volatile int __cpuinitdata pen_release = -1;
-/*
 * Write pen_release in a way that is guaranteed to be visible to all
 * observers, irrespective of whether they're taking part in coherency
 * or not.  This is necessary for the hotplug code to work reliably.
@@ -64,7 +59,7 @@ static void __iomem *scu_base_addr(void)
 static DEFINE_SPINLOCK(boot_lock);
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit exynos_secondary_init(unsigned int cpu)
 {
        /*
         * if any interrupts are already enabled for the primary
@@ -86,7 +81,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
        spin_unlock(&boot_lock);
 }
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        unsigned long timeout;
@@ -139,7 +134,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
                __raw_writel(virt_to_phys(exynos4_secondary_startup),
                        CPU1_BOOT_REG);
-                gic_raise_softirq(cpumask_of(cpu), 1);
+                gic_raise_softirq(cpumask_of(cpu), 0);
                if (pen_release == -1)
                        break;
@@ -161,7 +156,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 * which may be present or become present in the system.
 */
-void __init smp_init_cpus(void)
+static void __init exynos_smp_init_cpus(void)
 {
        void __iomem *scu_base = scu_base_addr();
        unsigned int i, ncores;
@@ -184,7 +179,7 @@ void __init smp_init_cpus(void)
        set_smp_cross_call(gic_raise_softirq);
 }
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 {
        if (!soc_is_exynos5250())
                scu_enable(scu_base_addr());
@@ -198,3 +193,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
        __raw_writel(virt_to_phys(exynos4_secondary_startup),
                        CPU1_BOOT_REG);
 }
+struct smp_operations exynos_smp_ops __initdata = {
+        .smp_init_cpus          = exynos_smp_init_cpus,
+        .smp_prepare_cpus       = exynos_smp_prepare_cpus,
+        .smp_secondary_init     = exynos_secondary_init,
+        .smp_boot_secondary     = exynos_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = exynos_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-exynos/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c
index 07a6dbeecdd0..5665bb4e980b 100644
--- a/arch/arm/mach-exynos/setup-fimd0.c
+++ b/arch/arm/mach-exynos/setup-fimd0.c
@@ -13,8 +13,8 @@
 #include <linux/fb.h>
 #include <linux/gpio.h>
+#include <video/samsung_fimd.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-fb-v4.h>
 #include <mach/map.h>
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
index b90d94c17f7c..5700f23629f7 100644
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -14,7 +14,7 @@
 struct platform_device; /* don't need the contents */
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-exynos/setup-i2c1.c b/arch/arm/mach-exynos/setup-i2c1.c
index fd7235a43f6e..8d2279cc85dc 100644
--- a/arch/arm/mach-exynos/setup-i2c1.c
+++ b/arch/arm/mach-exynos/setup-i2c1.c
@@ -13,7 +13,7 @@
 struct platform_device; /* don't need the contents */
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-exynos/setup-i2c2.c b/arch/arm/mach-exynos/setup-i2c2.c
index 2694b19e8b37..0ed62fc42a77 100644
--- a/arch/arm/mach-exynos/setup-i2c2.c
+++ b/arch/arm/mach-exynos/setup-i2c2.c
@@ -13,7 +13,7 @@
 struct platform_device; /* don't need the contents */
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 void s3c_i2c2_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-exynos/setup-i2c3.c b/arch/arm/mach-exynos/setup-i2c3.c
index 379bd306993f..7787fd26076b 100644
--- a/arch/arm/mach-exynos/setup-i2c3.c
+++ b/arch/arm/mach-exynos/setup-i2c3.c
@@ -13,7 +13,7 @@
 struct platform_device; /* don't need the contents */
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 void s3c_i2c3_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-exynos/setup-i2c4.c b/arch/arm/mach-exynos/setup-i2c4.c
index 9f3c04855b76..edc847f89826 100644
--- a/arch/arm/mach-exynos/setup-i2c4.c
+++ b/arch/arm/mach-exynos/setup-i2c4.c
@@ -13,7 +13,7 @@
 struct platform_device; /* don't need the contents */
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 void s3c_i2c4_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-exynos/setup-i2c5.c b/arch/arm/mach-exynos/setup-i2c5.c
index 77e1a1e57c76..d88af7f75954 100644
--- a/arch/arm/mach-exynos/setup-i2c5.c
+++ b/arch/arm/mach-exynos/setup-i2c5.c
@@ -13,7 +13,7 @@
 struct platform_device; /* don't need the contents */
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 void s3c_i2c5_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-exynos/setup-i2c6.c b/arch/arm/mach-exynos/setup-i2c6.c
index 284d12b7af0e..c590286c9d3a 100644
--- a/arch/arm/mach-exynos/setup-i2c6.c
+++ b/arch/arm/mach-exynos/setup-i2c6.c
@@ -13,7 +13,7 @@
 struct platform_device; /* don't need the contents */
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 void s3c_i2c6_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-exynos/setup-i2c7.c b/arch/arm/mach-exynos/setup-i2c7.c
index b7611ee359a2..1bba75568a5f 100644
--- a/arch/arm/mach-exynos/setup-i2c7.c
+++ b/arch/arm/mach-exynos/setup-i2c7.c
@@ -13,7 +13,7 @@
 struct platform_device; /* don't need the contents */
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 void s3c_i2c7_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-footbridge/Makefile b/arch/arm/mach-footbridge/Makefile
index 3afb1b25946f..0b64dd430d61 100644
--- a/arch/arm/mach-footbridge/Makefile
+++ b/arch/arm/mach-footbridge/Makefile
@@ -14,15 +14,11 @@ pci-$(CONFIG_ARCH_EBSA285_HOST) += ebsa285-pci.o
 pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o
 pci-$(CONFIG_ARCH_PERSONAL_SERVER) += personal-pci.o
-leds-$(CONFIG_ARCH_EBSA285) += ebsa285-leds.o
-leds-$(CONFIG_ARCH_NETWINDER) += netwinder-leds.o
 obj-$(CONFIG_ARCH_CATS) += cats-hw.o isa-timer.o
 obj-$(CONFIG_ARCH_EBSA285) += ebsa285.o dc21285-timer.o
 obj-$(CONFIG_ARCH_NETWINDER) += netwinder-hw.o isa-timer.o
 obj-$(CONFIG_ARCH_PERSONAL_SERVER) += personal.o dc21285-timer.o
 obj-$(CONFIG_PCI)       +=$(pci-y)
-obj-$(CONFIG_LEDS)      +=$(leds-y)
 obj-$(CONFIG_ISA)       += isa.o isa-rtc.o
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 3e6aaa6361da..a42b369bc439 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/spinlock.h>
- 
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/irq.h>
@@ -26,6 +26,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include "common.h"
@@ -175,11 +176,6 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = {
                .pfn            = __phys_to_pfn(DC21285_PCI_IACK),
                .length         = PCIIACK_SIZE,
                .type           = MT_DEVICE,
-        }, {
-                .virtual        = PCIO_BASE,
-                .pfn            = __phys_to_pfn(DC21285_PCI_IO),
-                .length         = PCIO_SIZE,
-                .type           = MT_DEVICE,
        },
 #endif
 };
@@ -196,8 +192,10 @@ void __init footbridge_map_io(void)
         * Now, work out what we've got to map in addition on this
         * platform.
         */
-        if (footbridge_cfn_mode())
+        if (footbridge_cfn_mode()) {
                iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
+                pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
+        }
 }
 void footbridge_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 9d62e3381024..a7cd2cf5e08d 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -276,8 +276,8 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
        sys->mem_offset  = DC21285_PCI_MEM;
-        pci_add_resource_offset(&sys->resources,
+        pci_ioremap_io(0, DC21285_PCI_IO);
-                                &ioport_resource, sys->io_offset);
        pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
@@ -298,7 +298,7 @@ void __init dc21285_preinit(void)
        mem_size = (unsigned int)high_memory - PAGE_OFFSET;
        for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
                if (mem_mask >= mem_size)
-                        break;          
+                        break;
        /*
         * These registers need to be set up whether we're the
@@ -350,14 +350,6 @@ void __init dc21285_preinit(void)
                            "PCI data parity", NULL);
        if (cfn_mode) {
-                static struct resource csrio;
-                csrio.flags  = IORESOURCE_IO;
-                csrio.name   = "Footbridge";
-                allocate_resource(&ioport_resource, &csrio, 128,
-                                  0xff00, 0xffff, 128, NULL, NULL);
                /*
                 * Map our SDRAM at a known address in PCI space, just in case
                 * the firmware had other ideas.  Using a nonzero base is
@@ -365,7 +357,7 @@ void __init dc21285_preinit(void)
                 * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
                 */
                *CSR_PCICSRBASE       = 0xf4000000;
-                *CSR_PCICSRIOBASE     = csrio.start;
+                *CSR_PCICSRIOBASE     = 0;
                *CSR_PCISDRAMBASE     = __virt_to_bus(PAGE_OFFSET);
                *CSR_PCIROMBASE       = 0;
                *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
diff --git a/arch/arm/mach-footbridge/ebsa285-leds.c b/arch/arm/mach-footbridge/ebsa285-leds.c
deleted file mode 100644
index 5bd266754b95..000000000000
--- a/arch/arm/mach-footbridge/ebsa285-leds.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- *  linux/arch/arm/mach-footbridge/ebsa285-leds.c
- *
- *  Copyright (C) 1998-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- * EBSA-285 control routines.
- *
- * The EBSA-285 uses the leds as follows:
- *  - Green - toggles state every 50 timer interrupts
- *  - Amber - On if system is not idle
- *  - Red   - currently unused
- *
- * Changelog:
- *   02-05-1999 RMK     Various cleanups
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-static char led_state;
-static char hw_led_state;
-static DEFINE_SPINLOCK(leds_lock);
-static void ebsa285_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&leds_lock, flags);
-        switch (evt) {
-        case led_start:
-                hw_led_state = XBUS_LED_RED | XBUS_LED_GREEN;
-#ifndef CONFIG_LEDS_CPU
-                hw_led_state |= XBUS_LED_AMBER;
-#endif
-                led_state |= LED_STATE_ENABLED;
-                break;
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = XBUS_LED_RED | XBUS_LED_GREEN | XBUS_LED_AMBER;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = XBUS_LED_RED | XBUS_LED_GREEN | XBUS_LED_AMBER;
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= XBUS_LED_GREEN;
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= XBUS_LED_AMBER;
-                break;
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~XBUS_LED_AMBER;
-                break;
-#endif
-        case led_halted:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~XBUS_LED_RED;
-                break;
-        case led_green_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~XBUS_LED_GREEN;
-                break;
-        case led_green_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= XBUS_LED_GREEN;
-                break;
-        case led_amber_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~XBUS_LED_AMBER;
-                break;
-        case led_amber_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= XBUS_LED_AMBER;
-                break;
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~XBUS_LED_RED;
-                break;
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= XBUS_LED_RED;
-                break;
-        default:
-                break;
-        }
-        if  (led_state & LED_STATE_ENABLED)
-                *XBUS_LEDS = hw_led_state;
-        spin_unlock_irqrestore(&leds_lock, flags);
-}
-static int __init leds_init(void)
-{
-        if (machine_is_ebsa285())
-                leds_event = ebsa285_leds_event;
-        leds_event(led_start);
-        return 0;
-}
-__initcall(leds_init);
diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c
index 27716a7e5fc1..b09551ef89ca 100644
--- a/arch/arm/mach-footbridge/ebsa285.c
+++ b/arch/arm/mach-footbridge/ebsa285.c
@@ -5,6 +5,8 @@
 */
 #include <linux/init.h>
 #include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 #include <asm/hardware/dec21285.h>
 #include <asm/mach-types.h>
@@ -13,6 +15,85 @@
 #include "common.h"
+/* LEDs */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct ebsa285_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} ebsa285_leds[] = {
+        { "ebsa285:amber", "heartbeat", },
+        { "ebsa285:green", "cpu0", },
+        { "ebsa285:red",},
+};
+static void ebsa285_led_set(struct led_classdev *cdev,
+                enum led_brightness b)
+{
+        struct ebsa285_led *led = container_of(cdev,
+                        struct ebsa285_led, cdev);
+        if (b != LED_OFF)
+                *XBUS_LEDS |= led->mask;
+        else
+                *XBUS_LEDS &= ~led->mask;
+}
+static enum led_brightness ebsa285_led_get(struct led_classdev *cdev)
+{
+        struct ebsa285_led *led = container_of(cdev,
+                        struct ebsa285_led, cdev);
+        return (*XBUS_LEDS & led->mask) ? LED_FULL : LED_OFF;
+}
+static int __init ebsa285_leds_init(void)
+{
+        int i;
+        if (machine_is_ebsa285())
+                return -ENODEV;
+        /* 3 LEDS All ON */
+        *XBUS_LEDS |= XBUS_LED_AMBER | XBUS_LED_GREEN | XBUS_LED_RED;
+        for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) {
+                struct ebsa285_led *led;
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+                led->cdev.name = ebsa285_leds[i].name;
+                led->cdev.brightness_set = ebsa285_led_set;
+                led->cdev.brightness_get = ebsa285_led_get;
+                led->cdev.default_trigger = ebsa285_leds[i].trigger;
+                led->mask = BIT(i);
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+        return 0;
+}
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(ebsa285_leds_init);
+#endif
 MACHINE_START(EBSA285, "EBSA285")
        /* Maintainer: Russell King */
        .atag_offset    = 0x100,
diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S
index e5acde25ffc5..c169f0c99b2a 100644
--- a/arch/arm/mach-footbridge/include/mach/debug-macro.S
+++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S
@@ -17,7 +17,8 @@
        /* For NetWinder debugging */
                .macro  addruart, rp, rv, tmp
                mov     \rp, #0x000003f8
-                orr     \rv, \rp, #0xff000000   @ virtual
+                orr     \rv, \rp, #0xfe000000   @ virtual
+                orr     \rv, \rv, #0x00e00000   @ virtual
                orr     \rp, \rp, #0x7c000000   @ physical
                .endm
diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h
index aba531eebbc6..aba46388cc0c 100644
--- a/arch/arm/mach-footbridge/include/mach/io.h
+++ b/arch/arm/mach-footbridge/include/mach/io.h
@@ -14,18 +14,10 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
-#ifdef CONFIG_MMU
-#define MMU_IO(a, b)    (a)
-#else
-#define MMU_IO(a, b)    (b)
-#endif
-#define PCIO_SIZE       0x00100000
-#define PCIO_BASE       MMU_IO(0xff000000, 0x7c000000)
 /*
- * Translation of various region addresses to virtual addresses
+ * Translation of various i/o addresses to host addresses for !CONFIG_MMU
 */
+#define PCIO_BASE       0x7c000000
 #define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
 #endif
diff --git a/arch/arm/mach-footbridge/include/mach/irqs.h b/arch/arm/mach-footbridge/include/mach/irqs.h
index 400551e43e4e..61c714c4920e 100644
--- a/arch/arm/mach-footbridge/include/mach/irqs.h
+++ b/arch/arm/mach-footbridge/include/mach/irqs.h
@@ -89,8 +89,6 @@
 #define IRQ_NETWINDER_VGA       _ISA_IRQ(11)
 #define IRQ_NETWINDER_SOUND     _ISA_IRQ(12)
-#undef RTC_IRQ
-#define RTC_IRQ         IRQ_ISA_RTC_ALARM
 #define I8042_KBD_IRQ   IRQ_ISA_KEYBOARD
 #define I8042_AUX_IRQ   (machine_is_netwinder() ? IRQ_NETWINDER_PS2MOUSE : IRQ_ISA_PS2MOUSE)
 #define IRQ_FLOPPYDISK  IRQ_ISA_FLOPPY
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index cac9f67e7da7..d2d14339c6c4 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -12,9 +12,10 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 #include <asm/hardware/dec21285.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
 #include <asm/system_misc.h>
@@ -27,13 +28,6 @@
 #define GP1_IO_BASE             0x338
 #define GP2_IO_BASE             0x33a
-#ifdef CONFIG_LEDS
-#define DEFAULT_LEDS    0
-#else
-#define DEFAULT_LEDS    GPIO_GREEN_LED
-#endif
 /*
 * Winbond WB83977F accessibility stuff
 */
@@ -611,15 +605,9 @@ static void __init rwa010_init(void)
 static int __init nw_hw_init(void)
 {
        if (machine_is_netwinder()) {
-                unsigned long flags;
                wb977_init();
                cpld_init();
                rwa010_init();
-                raw_spin_lock_irqsave(&nw_gpio_lock, flags);
-                nw_gpio_modify_op(GPIO_RED_LED|GPIO_GREEN_LED, DEFAULT_LEDS);
-                raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
        }
        return 0;
 }
@@ -672,6 +660,102 @@ static void netwinder_restart(char mode, const char *cmd)
        }
 }
+/* LEDs */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct netwinder_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} netwinder_leds[] = {
+        { "netwinder:green", "heartbeat", },
+        { "netwinder:red", "cpu0", },
+};
+/*
+ * The LED control in Netwinder is reversed:
+ *  - setting bit means turn off LED
+ *  - clearing bit means turn on LED
+ */
+static void netwinder_led_set(struct led_classdev *cdev,
+                enum led_brightness b)
+{
+        struct netwinder_led *led = container_of(cdev,
+                        struct netwinder_led, cdev);
+        unsigned long flags;
+        u32 reg;
+        spin_lock_irqsave(&nw_gpio_lock, flags);
+        reg = nw_gpio_read();
+        if (b != LED_OFF)
+                reg &= ~led->mask;
+        else
+                reg |= led->mask;
+        nw_gpio_modify_op(led->mask, reg);
+        spin_unlock_irqrestore(&nw_gpio_lock, flags);
+}
+static enum led_brightness netwinder_led_get(struct led_classdev *cdev)
+{
+        struct netwinder_led *led = container_of(cdev,
+                        struct netwinder_led, cdev);
+        unsigned long flags;
+        u32 reg;
+        spin_lock_irqsave(&nw_gpio_lock, flags);
+        reg = nw_gpio_read();
+        spin_unlock_irqrestore(&nw_gpio_lock, flags);
+        return (reg & led->mask) ? LED_OFF : LED_FULL;
+}
+static int __init netwinder_leds_init(void)
+{
+        int i;
+        if (!machine_is_netwinder())
+                return -ENODEV;
+        for (i = 0; i < ARRAY_SIZE(netwinder_leds); i++) {
+                struct netwinder_led *led;
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+                led->cdev.name = netwinder_leds[i].name;
+                led->cdev.brightness_set = netwinder_led_set;
+                led->cdev.brightness_get = netwinder_led_get;
+                led->cdev.default_trigger = netwinder_leds[i].trigger;
+                if (i == 0)
+                        led->mask = GPIO_GREEN_LED;
+                else
+                        led->mask = GPIO_RED_LED;
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+        return 0;
+}
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(netwinder_leds_init);
+#endif
 MACHINE_START(NETWINDER, "Rebel-NetWinder")
        /* Maintainer: Russell King/Rebel.com */
        .atag_offset    = 0x100,
diff --git a/arch/arm/mach-footbridge/netwinder-leds.c b/arch/arm/mach-footbridge/netwinder-leds.c
deleted file mode 100644
index 5a2bd89cbdca..000000000000
--- a/arch/arm/mach-footbridge/netwinder-leds.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- *  linux/arch/arm/mach-footbridge/netwinder-leds.c
- *
- *  Copyright (C) 1998-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * NetWinder LED control routines.
- *
- * The Netwinder uses the leds as follows:
- *  - Green - toggles state every 50 timer interrupts
- *  - Red   - On if the system is not idle
- *
- * Changelog:
- *   02-05-1999 RMK     Various cleanups
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-static char led_state;
-static char hw_led_state;
-static DEFINE_RAW_SPINLOCK(leds_lock);
-static void netwinder_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        raw_spin_lock_irqsave(&leds_lock, flags);
-        switch (evt) {
-        case led_start:
-                led_state |= LED_STATE_ENABLED;
-                hw_led_state = GPIO_GREEN_LED;
-                break;
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= GPIO_GREEN_LED;
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~GPIO_RED_LED;
-                break;
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= GPIO_RED_LED;
-                break;
-#endif
-        case led_halted:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= GPIO_RED_LED;
-                break;
-        case led_green_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= GPIO_GREEN_LED;
-                break;
-        case led_green_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~GPIO_GREEN_LED;
-                break;
-        case led_amber_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= GPIO_GREEN_LED | GPIO_RED_LED;
-                break;
-        case led_amber_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~(GPIO_GREEN_LED | GPIO_RED_LED);
-                break;
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= GPIO_RED_LED;
-                break;
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~GPIO_RED_LED;
-                break;
-        default:
-                break;
-        }
-        raw_spin_unlock_irqrestore(&leds_lock, flags);
-        if  (led_state & LED_STATE_ENABLED) {
-                raw_spin_lock_irqsave(&nw_gpio_lock, flags);
-                nw_gpio_modify_op(GPIO_RED_LED | GPIO_GREEN_LED, hw_led_state);
-                raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
-        }
-}
-static int __init leds_init(void)
-{
-        if (machine_is_netwinder())
-                leds_event = netwinder_leds_event;
-        leds_event(led_start);
-        return 0;
-}
-__initcall(leds_init);
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
new file mode 100644
index 000000000000..0e1d0a42a3ea
--- /dev/null
+++ b/arch/arm/mach-highbank/Kconfig
@@ -0,0 +1,15 @@
+config ARCH_HIGHBANK
+        bool "Calxeda ECX-1000 (Highbank)" if ARCH_MULTI_V7
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_AMBA
+        select ARM_GIC
+        select ARM_TIMER_SP804
+        select CACHE_L2X0
+        select CLKDEV_LOOKUP
+        select COMMON_CLK
+        select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select HAVE_ARM_SCU
+        select HAVE_SMP
+        select SPARSE_IRQ
+        select USE_OF
diff --git a/arch/arm/mach-highbank/Makefile.boot b/arch/arm/mach-highbank/Makefile.boot
deleted file mode 100644
index dae9661a7689..000000000000
--- a/arch/arm/mach-highbank/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
-zreladdr-y      := 0x00008000
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 141ed5171826..286ec82a4f63 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -8,4 +8,13 @@ extern void highbank_lluart_map_io(void);
 static inline void highbank_lluart_map_io(void) {}
 #endif
+#ifdef CONFIG_PM_SLEEP
+extern void highbank_pm_init(void);
+#else
+static inline void highbank_pm_init(void) {}
+#endif
 extern void highbank_smc1(int fn, int arg);
+extern void highbank_cpu_die(unsigned int cpu);
+extern struct smp_operations highbank_smp_ops;
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index d75b0a78d88a..40e36a50304c 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -15,6 +15,7 @@
 */
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/dma-mapping.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
@@ -23,6 +24,7 @@
 #include <linux/of_platform.h>
 #include <linux/of_address.h>
 #include <linux/smp.h>
+#include <linux/amba/bus.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
@@ -149,9 +151,60 @@ static void highbank_power_off(void)
                cpu_do_idle();
 }
+static int highbank_platform_notifier(struct notifier_block *nb,
+                                  unsigned long event, void *__dev)
+{
+        struct resource *res;
+        int reg = -1;
+        struct device *dev = __dev;
+        if (event != BUS_NOTIFY_ADD_DEVICE)
+                return NOTIFY_DONE;
+        if (of_device_is_compatible(dev->of_node, "calxeda,hb-ahci"))
+                reg = 0xc;
+        else if (of_device_is_compatible(dev->of_node, "calxeda,hb-sdhci"))
+                reg = 0x18;
+        else if (of_device_is_compatible(dev->of_node, "arm,pl330"))
+                reg = 0x20;
+        else if (of_device_is_compatible(dev->of_node, "calxeda,hb-xgmac")) {
+                res = platform_get_resource(to_platform_device(dev),
+                                            IORESOURCE_MEM, 0);
+                if (res) {
+                        if (res->start == 0xfff50000)
+                                reg = 0;
+                        else if (res->start == 0xfff51000)
+                                reg = 4;
+                }
+        }
+        if (reg < 0)
+                return NOTIFY_DONE;
+        if (of_property_read_bool(dev->of_node, "dma-coherent")) {
+                writel(0xff31, sregs_base + reg);
+                set_dma_ops(dev, &arm_coherent_dma_ops);
+        } else
+                writel(0, sregs_base + reg);
+        return NOTIFY_OK;
+}
+static struct notifier_block highbank_amba_nb = {
+        .notifier_call = highbank_platform_notifier,
+};
+static struct notifier_block highbank_platform_nb = {
+        .notifier_call = highbank_platform_notifier,
+};
 static void __init highbank_init(void)
 {
        pm_power_off = highbank_power_off;
+        highbank_pm_init();
+        bus_register_notifier(&platform_bus_type, &highbank_platform_nb);
+        bus_register_notifier(&amba_bustype, &highbank_amba_nb);
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
@@ -162,6 +215,7 @@ static const char *highbank_match[] __initconst = {
 };
 DT_MACHINE_START(HIGHBANK, "Highbank")
+        .smp            = smp_ops(highbank_smp_ops),
        .map_io         = highbank_map_io,
        .init_irq       = highbank_init_irq,
        .timer          = &highbank_timer,
diff --git a/arch/arm/mach-highbank/hotplug.c b/arch/arm/mach-highbank/hotplug.c
index 977cebbea580..2c1b8c3c8e45 100644
--- a/arch/arm/mach-highbank/hotplug.c
+++ b/arch/arm/mach-highbank/hotplug.c
@@ -24,16 +24,11 @@
 extern void secondary_startup(void);
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
 /*
 * platform-specific code to shutdown a CPU
 *
 */
-void platform_cpu_die(unsigned int cpu)
+void __ref highbank_cpu_die(unsigned int cpu)
 {
        flush_cache_all();
@@ -45,12 +40,3 @@ void platform_cpu_die(unsigned int cpu)
        /* We should never return from idle */
        panic("highbank: cpu %d unexpectedly exit from shutdown\n", cpu);
 }
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * CPU0 should not be shut down via hotplug.  cpu_idle can WFI
-         * or a proper shutdown or hibernate should be used.
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-highbank/include/mach/gpio.h b/arch/arm/mach-highbank/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-highbank/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-highbank/include/mach/timex.h b/arch/arm/mach-highbank/include/mach/timex.h
deleted file mode 100644
index 88dac7a55a97..000000000000
--- a/arch/arm/mach-highbank/include/mach/timex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-#define CLOCK_TICK_RATE         1000000
-#endif
diff --git a/arch/arm/mach-highbank/include/mach/uncompress.h b/arch/arm/mach-highbank/include/mach/uncompress.h
deleted file mode 100644
index bbe20e696325..000000000000
--- a/arch/arm/mach-highbank/include/mach/uncompress.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __MACH_UNCOMPRESS_H
-#define __MACH_UNCOMPRESS_H
-#define putc(c)
-#define flush()
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
-#endif
diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
index d01364c72b45..fa9560ec6e70 100644
--- a/arch/arm/mach-highbank/platsmp.c
+++ b/arch/arm/mach-highbank/platsmp.c
@@ -25,12 +25,12 @@
 extern void secondary_startup(void);
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit highbank_secondary_init(unsigned int cpu)
 {
        gic_secondary_init(0);
 }
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        gic_raise_softirq(cpumask_of(cpu), 0);
        return 0;
@@ -40,7 +40,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 * Initialise the CPU possible map early - this describes the CPUs
 * which may be present or become present in the system.
 */
-void __init smp_init_cpus(void)
+static void __init highbank_smp_init_cpus(void)
 {
        unsigned int i, ncores;
@@ -61,7 +61,7 @@ void __init smp_init_cpus(void)
        set_smp_cross_call(gic_raise_softirq);
 }
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
 {
        int i;
@@ -76,3 +76,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
        for (i = 1; i < max_cpus; i++)
                highbank_set_cpu_jump(i, secondary_startup);
 }
+struct smp_operations highbank_smp_ops __initdata = {
+        .smp_init_cpus          = highbank_smp_init_cpus,
+        .smp_prepare_cpus       = highbank_smp_prepare_cpus,
+        .smp_secondary_init     = highbank_secondary_init,
+        .smp_boot_secondary     = highbank_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = highbank_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c
index 33b3beb89982..de866f21331f 100644
--- a/arch/arm/mach-highbank/pm.c
+++ b/arch/arm/mach-highbank/pm.c
@@ -47,9 +47,7 @@ static const struct platform_suspend_ops highbank_pm_ops = {
        .valid = suspend_valid_only_mem,
 };
-static int __init highbank_pm_init(void)
+void __init highbank_pm_init(void)
 {
        suspend_set_ops(&highbank_pm_ops);
-        return 0;
 }
-module_init(highbank_pm_init);
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index afd542ad6f97..32197c117afe 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -101,13 +101,8 @@ config	SOC_IMX51
        select SOC_IMX5
        select ARCH_MX5
        select ARCH_MX51
+        select PINCTRL
-config  SOC_IMX53
+        select PINCTRL_IMX51
-        bool
-        select SOC_IMX5
-        select ARCH_MX5
-        select ARCH_MX53
-        select HAVE_CAN_FLEXCAN if CAN
 if ARCH_IMX_V4_V5
@@ -303,6 +298,7 @@ config MACH_MX27_3DS
        select IMX_HAVE_PLATFORM_IMX_FB
        select IMX_HAVE_PLATFORM_IMX_I2C
        select IMX_HAVE_PLATFORM_IMX_KEYPAD
+        select IMX_HAVE_PLATFORM_IMX_SSI
        select IMX_HAVE_PLATFORM_IMX_UART
        select IMX_HAVE_PLATFORM_MX2_CAMERA
        select IMX_HAVE_PLATFORM_MXC_EHCI
@@ -561,7 +557,6 @@ config MACH_BUG
 config MACH_IMX31_DT
        bool "Support i.MX31 platforms from device tree"
        select SOC_IMX31
-        select USE_OF
        help
          Include support for Freescale i.MX31 based platforms
          using the device tree for discovery.
@@ -737,95 +732,19 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
 endchoice
-config MX51_EFIKA_COMMON
+comment "Device tree only"
-        bool
-        select SOC_IMX51
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_PATA_IMX
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
-config MACH_MX51_EFIKAMX
+config  SOC_IMX53
-        bool "Support MX51 Genesi Efika MX nettop"
+        bool "i.MX53 support"
-        select LEDS_GPIO_REGISTER
+        select SOC_IMX5
-        select MX51_EFIKA_COMMON
+        select ARCH_MX5
-        help
+        select ARCH_MX53
-          Include support for Genesi Efika MX nettop. This includes specific
+        select HAVE_CAN_FLEXCAN if CAN
-          configurations for the board and its peripherals.
+        select PINCTRL
+        select PINCTRL_IMX53
-config MACH_MX51_EFIKASB
-        bool "Support MX51 Genesi Efika Smartbook"
-        select LEDS_GPIO_REGISTER
-        select MX51_EFIKA_COMMON
-        help
-          Include support for Genesi Efika Smartbook. This includes specific
-          configurations for the board and its peripherals.
-comment "i.MX53 machines:"
-config MACH_IMX53_DT
-        bool "Support i.MX53 platforms from device tree"
-        select SOC_IMX53
-        select MACH_MX53_ARD
-        select MACH_MX53_EVK
-        select MACH_MX53_LOCO
-        select MACH_MX53_SMD
-        help
-          Include support for Freescale i.MX53 based platforms
-          using the device tree for discovery
-config MACH_MX53_EVK
-        bool "Support MX53 EVK platforms"
-        select SOC_IMX53
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select LEDS_GPIO_REGISTER
-        help
-          Include support for MX53 EVK platform. This includes specific
-          configurations for the board and its peripherals.
-config MACH_MX53_SMD
-        bool "Support MX53 SMD platforms"
-        select SOC_IMX53
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        help
-          Include support for MX53 SMD platform. This includes specific
-          configurations for the board and its peripherals.
-config MACH_MX53_LOCO
-        bool "Support MX53 LOCO platforms"
-        select SOC_IMX53
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_GPIO_KEYS
-        select LEDS_GPIO_REGISTER
-        help
-          Include support for MX53 LOCO platform. This includes specific
-          configurations for the board and its peripherals.
-config MACH_MX53_ARD
-        bool "Support MX53 ARD platforms"
-        select SOC_IMX53
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_GPIO_KEYS
        help
-          Include support for MX53 ARD platform. This includes specific
+          This enables support for Freescale i.MX53 processor.
-          configurations for the board and its peripherals.
-comment "i.MX6 family:"
 config SOC_IMX6Q
        bool "i.MX6 Quad support"
@@ -839,7 +758,7 @@ config SOC_IMX6Q
        select HAVE_IMX_MMDC
        select HAVE_IMX_SRC
        select HAVE_SMP
-        select MFD_ANATOP
+        select MFD_SYSCON
        select PINCTRL
        select PINCTRL_IMX6Q
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d004d37ad9d8..895754aeb4f3 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -13,7 +13,7 @@ imx5-pm-$(CONFIG_PM) += pm-imx5.o
 obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
-                            clk-pfd.o clk-busy.o
+                            clk-pfd.o clk-busy.o clk.o
 # Support for CMOS sensor interface
 obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
@@ -83,16 +83,9 @@ endif
 # i.MX5 based machines
 obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
 obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
-obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o
-obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o
-obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o
-obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
-obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
-obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o
-obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o
 obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
-obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
+obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 05541cf4a878..b27815de8473 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -37,10 +37,3 @@ initrd_phys-$(CONFIG_SOC_IMX53)	:= 0x70800000
 zreladdr-$(CONFIG_SOC_IMX6Q)    += 0x10008000
 params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
 initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
-dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
-dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \
-                               imx53-qsb.dtb imx53-smd.dtb
-dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
-                           imx6q-sabrelite.dtb \
-                           imx6q-sabresd.dtb \
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index ea13e61bd5f3..cf65148bc519 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -23,7 +23,6 @@
 #include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/module.h>
-#include <linux/clkdev.h>
 #include <linux/err.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index f69ca4680049..3b6b640eed24 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -239,8 +239,8 @@ int __init mx27_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
        clk_register_clkdev(clk[nfc_baud_gate], NULL, "mxc_nand.0");
-        clk_register_clkdev(clk[vpu_baud_gate], "per", "imx-vpu");
+        clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
-        clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "imx-vpu");
+        clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
        clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx-dma");
        clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx-dma");
        clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 65fb8bcd86cb..177259b523cd 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -62,8 +62,8 @@ enum mx35_clks {
        kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate,
        rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,
        ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,
-        wdog_gate, max_gate, admux_gate, csi_gate, iim_gate, gpu2d_gate,
+        wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
-        clk_max
+        gpu2d_gate, clk_max
 };
 static struct clk *clk[clk_max];
@@ -142,6 +142,9 @@ int __init mx35_clocks_init()
        clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
+        clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel));
+        clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6);
        clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0,  0);
        clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0,  2);
        clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0,  4);
@@ -192,7 +195,7 @@ int __init mx35_clocks_init()
        clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
        clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
-        clk[csi_gate] = imx_clk_gate2("csi_gate", "ipg", base + MX35_CCM_CGR3,  0);
+        clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3,  0);
        clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3,  2);
        clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3,  4);
@@ -228,6 +231,7 @@ int __init mx35_clocks_init()
        clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
        clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
        clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
+        clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
        clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
        clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
        clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
@@ -253,6 +257,7 @@ int __init mx35_clocks_init()
        clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
        clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
        clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0");
+        clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
        clk_prepare_enable(clk[spba_gate]);
        clk_prepare_enable(clk[gpio1_gate]);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 4bdcaa97bd98..a0bf84803eac 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -39,16 +39,17 @@ static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
 static const char *emi_slow_sel[] = { "main_bus", "ahb", };
 static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
 static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
-static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0", };
+static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
 static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
 static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
-static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1", };
+static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
 static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
 static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
 static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
 static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", };
 static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
 static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
+static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
 enum imx5_clks {
        dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
@@ -82,6 +83,7 @@ enum imx5_clks {
        ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
        ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
        epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
+        can_sel, can1_serial_gate, can1_ipg_gate,
        clk_max
 };
@@ -367,6 +369,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
+        clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
        /* set the usboh3 parent to pll2_sw */
        clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
@@ -421,8 +424,12 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
        clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
        clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
        clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
-        clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "ipg", MXC_CCM_CCGR4, 6);
+        clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
-        clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8);
+                                mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
+        clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
+        clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
+        clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
+        clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
        clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
        for (i = 0; i < ARRAY_SIZE(clk); i++)
@@ -455,6 +462,11 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
+        clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
+        clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
+        clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
+        clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
+        clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
        /* set SDHC root clock to 200MHZ*/
        clk_set_rate(clk[esdhc_a_podf], 200000000);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4233d9e3531d..3ec242f3341e 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -157,6 +157,7 @@ enum mx6q_clks {
 };
 static struct clk *clk[clk_max];
+static struct clk_onecell_data clk_data;
 static enum mx6q_clks const clks_init_on[] __initconst = {
        mmdc_ch0_axi, rom,
@@ -394,52 +395,24 @@ int __init mx6q_clocks_init(void)
                        pr_err("i.MX6q clk %d: register failed with %ld\n",
                                i, PTR_ERR(clk[i]));
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
        clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
        clk_register_clkdev(clk[twd], NULL, "smp_twd");
-        clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
-        clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
-        clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
-        clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
-        clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
-        clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
-        clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
-        clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
-        clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
-        clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
-        clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
-        clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
-        clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
-        clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
-        clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
-        clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
-        clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
-        clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
-        clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
-        clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
-        clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
-        clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc");
-        clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c");
-        clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c");
-        clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c");
-        clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi");
-        clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi");
-        clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
-        clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
-        clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
-        clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
-        clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
-        clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
-        clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi");
        clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
        clk_register_clkdev(clk[ahb], "ahb", NULL);
        clk_register_clkdev(clk[cko1], "cko1", NULL);
+        /*
+         * The gpmi needs 100MHz frequency in the EDO/Sync mode,
+         * We can not get the 100MHz from the pll2_pfd0_352m.
+         * So choose pll2_pfd2_396m as enfc_sel's parent.
+         */
+        clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                clk_prepare_enable(clk[clks_init_on[i]]);
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index 2d856f9ccf59..02be73178912 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -6,7 +6,7 @@
 #include <linux/err.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/clock.h>
 #include "clk.h"
 /**
@@ -29,8 +29,53 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
                unsigned long parent_rate)
 {
        struct clk_pllv1 *pll = to_clk_pllv1(hw);
+        long long ll;
+        int mfn_abs;
+        unsigned int mfi, mfn, mfd, pd;
+        u32 reg;
+        unsigned long rate;
+        reg = readl(pll->base);
+        /*
+         * Get the resulting clock rate from a PLL register value and the input
+         * frequency. PLLs with this register layout can be found on i.MX1,
+         * i.MX21, i.MX27 and i,MX31
+         *
+         *                  mfi + mfn / (mfd + 1)
+         *  f = 2 * f_ref * --------------------
+         *                        pd + 1
+         */
+        mfi = (reg >> 10) & 0xf;
+        mfn = reg & 0x3ff;
+        mfd = (reg >> 16) & 0x3ff;
+        pd =  (reg >> 26) & 0xf;
+        mfi = mfi <= 5 ? 5 : mfi;
+        mfn_abs = mfn;
+        /*
+         * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
+         * 2's complements number
+         */
+        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+                mfn_abs = 0x400 - mfn;
+        rate = parent_rate * 2;
+        rate /= pd + 1;
+        ll = (unsigned long long)rate * mfn_abs;
+        do_div(ll, mfd + 1);
+        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+                ll = -ll;
+        ll = (rate * mfi) + ll;
-        return mxc_decode_pll(readl(pll->base), parent_rate);
+        return ll;
 }
 struct clk_ops clk_pllv1_ops = {
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
new file mode 100644
index 000000000000..f5e8be8e7f11
--- /dev/null
+++ b/arch/arm/mach-imx/clk.c
@@ -0,0 +1,3 @@
+#include <linux/spinlock.h>
+DEFINE_SPINLOCK(imx_ccm_lock);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 1bf64fe2523c..5f2d8acca25f 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -3,7 +3,8 @@
 #include <linux/spinlock.h>
 #include <linux/clk-provider.h>
-#include <mach/clock.h>
+extern spinlock_t imx_ccm_lock;
 struct clk *imx_clk_pllv1(const char *name, const char *parent,
                void __iomem *base);
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 436c5720fe6a..04822932cdd1 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -17,6 +17,10 @@ extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data;
 #define imx27_add_fsl_usb2_udc(pdata)   \
        imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
+extern const struct imx_imx27_coda_data imx27_coda_data;
+#define imx27_add_coda()        \
+        imx_add_imx27_coda(&imx27_coda_data)
 extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data;
 #define imx27_add_imx2_wdt()    \
        imx_add_imx2_wdt(&imx27_imx2_wdt_data)
diff --git a/arch/arm/mach-imx/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h
deleted file mode 100644
index 77e0db96c448..000000000000
--- a/arch/arm/mach-imx/devices-imx53.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx53.h>
-#include <mach/devices-common.h>
-extern const struct imx_fec_data imx53_fec_data;
-#define imx53_add_fec(pdata)   \
-        imx_add_fec(&imx53_fec_data, pdata)
-extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
-#define imx53_add_imx_uart(id, pdata)   \
-        imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
-extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
-#define imx53_add_imx_i2c(id, pdata)    \
-        imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
-extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
-#define imx53_add_sdhci_esdhc_imx(id, pdata)    \
-        imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
-extern const struct imx_spi_imx_data imx53_ecspi_data[];
-#define imx53_add_ecspi(id, pdata)      \
-        imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
-extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
-#define imx53_add_imx2_wdt(id)  \
-        imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
-extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
-#define imx53_add_imx_ssi(id, pdata)    \
-        imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
-extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
-#define imx53_add_imx_keypad(pdata)     \
-        imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
-extern const struct imx_pata_imx_data imx53_pata_imx_data;
-#define imx53_add_pata_imx() \
-        imx_add_pata_imx(&imx53_pata_imx_data)
-extern struct platform_device *__init imx53_add_ahci_imx(void);
diff --git a/arch/arm/mach-imx/efika.h b/arch/arm/mach-imx/efika.h
deleted file mode 100644
index 014aa985faae..000000000000
--- a/arch/arm/mach-imx/efika.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _EFIKA_H
-#define _EFIKA_H
-#define EFIKA_WLAN_EN           IMX_GPIO_NR(2, 16)
-#define EFIKA_WLAN_RESET        IMX_GPIO_NR(2, 10)
-#define EFIKA_USB_PHY_RESET     IMX_GPIO_NR(2, 9)
-void __init efika_board_common_init(void);
-#endif
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
index 05bb41d99728..412c583a24b0 100644
--- a/arch/arm/mach-imx/ehci-imx25.c
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
+#include <linux/platform_data/usb-ehci-mxc.h>
 #define USBCTRL_OTGBASE_OFFSET  0x600
diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c
index fa69419eabdd..cd6e1f81508d 100644
--- a/arch/arm/mach-imx/ehci-imx27.c
+++ b/arch/arm/mach-imx/ehci-imx27.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
+#include <linux/platform_data/usb-ehci-mxc.h>
 #define USBCTRL_OTGBASE_OFFSET  0x600
diff --git a/arch/arm/mach-imx/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c
index faad0f15ac7f..9a880c78af34 100644
--- a/arch/arm/mach-imx/ehci-imx31.c
+++ b/arch/arm/mach-imx/ehci-imx31.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
+#include <linux/platform_data/usb-ehci-mxc.h>
 #define USBCTRL_OTGBASE_OFFSET  0x600
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
index 73574c30cf50..779e16eb65cb 100644
--- a/arch/arm/mach-imx/ehci-imx35.c
+++ b/arch/arm/mach-imx/ehci-imx35.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
+#include <linux/platform_data/usb-ehci-mxc.h>
 #define USBCTRL_OTGBASE_OFFSET  0x600
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c
index a6a4afb0ad62..cf8d00e5cce1 100644
--- a/arch/arm/mach-imx/ehci-imx5.c
+++ b/arch/arm/mach-imx/ehci-imx5.c
@@ -17,7 +17,7 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
+#include <linux/platform_data/usb-ehci-mxc.h>
 #define MXC_OTG_OFFSET                  0
 #define MXC_H1_OFFSET                   0x200
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index fd3177f9e79a..98aef571b9f8 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -348,4 +348,5 @@ void __init eukrea_mbimx27_baseboard_init(void)
        imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data);
        gpio_led_register_device(-1, &eukrea_mbimx27_gpio_led_info);
+        imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
 }
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index dfd2da87c2df..0b84666792f0 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -306,4 +306,5 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
        gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
        imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
+        imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
 }
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 6e9dd12a6961..c6532a007d46 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -315,4 +315,5 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
        gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
        imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
+        imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
 }
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
index 96a24b73dc23..8b0de30d7a3f 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
@@ -228,4 +228,5 @@ void __init eukrea_mbimxsd51_baseboard_init(void)
        gpio_led_register_device(-1, &eukrea_mbimxsd51_led_info);
        imx_add_gpio_keys(&eukrea_mbimxsd51_button_data);
+        imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
 }
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index f8f7437c83b8..b07b778dc9a8 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -15,11 +15,6 @@
 #include <asm/cp15.h>
 #include <mach/common.h>
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
 static inline void cpu_enter_lowpower(void)
 {
        unsigned int v;
@@ -47,7 +42,7 @@ static inline void cpu_enter_lowpower(void)
 *
 * Called with IRQs disabled
 */
-void platform_cpu_die(unsigned int cpu)
+void imx_cpu_die(unsigned int cpu)
 {
        cpu_enter_lowpower();
        imx_enable_cpu(cpu, false);
@@ -56,12 +51,3 @@ void platform_cpu_die(unsigned int cpu)
        while (1)
                ;
 }
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index d4067fe36357..f233b4bb2342 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -13,7 +13,6 @@
 #include <linux/irq.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
@@ -44,27 +43,8 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
        { /* sentinel */ }
 };
-static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
-        { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
-        { /* sentinel */ }
-};
 static void __init imx51_dt_init(void)
 {
-        struct device_node *node;
-        const struct of_device_id *of_id;
-        void (*func)(void);
-        pinctrl_provide_dummies();
-        node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
-        if (node) {
-                of_id = of_match_node(imx51_iomuxc_of_match, node);
-                func = of_id->data;
-                func();
-                of_node_put(node);
-        }
        of_platform_populate(NULL, of_default_bus_match_table,
                             imx51_auxdata_lookup, NULL);
 }
@@ -79,7 +59,6 @@ static struct sys_timer imx51_timer = {
 };
 static const char *imx51_dt_board_compat[] __initdata = {
-        "fsl,imx51-babbage",
        "fsl,imx51",
        NULL
 };
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index f264ddddd47c..141756f00ae5 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -32,13 +32,14 @@
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/leds.h>
-#include <linux/memblock.h>
+#include <linux/platform_data/asoc-mx27vis.h>
 #include <media/soc_camera.h>
 #include <sound/tlv320aic32x4.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/system_info.h>
+#include <asm/memblock.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
@@ -58,6 +59,11 @@
 #define EXPBOARD_BIT1           (GPIO_PORTD + 27)
 #define EXPBOARD_BIT0           (GPIO_PORTD + 28)
+#define AMP_GAIN_0              (GPIO_PORTF + 9)
+#define AMP_GAIN_1              (GPIO_PORTF + 8)
+#define AMP_MUTE_SDL            (GPIO_PORTE + 5)
+#define AMP_MUTE_SDR            (GPIO_PORTF + 7)
 static const int visstrim_m10_pins[] __initconst = {
        /* UART1 (console) */
        PE12_PF_UART1_TXD,
@@ -139,6 +145,11 @@ static const int visstrim_m10_pins[] __initconst = {
        EXPBOARD_BIT2 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
        EXPBOARD_BIT1 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
        EXPBOARD_BIT0 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
+        /* Audio AMP control */
+        AMP_GAIN_0 | GPIO_GPIO | GPIO_OUT,
+        AMP_GAIN_1 | GPIO_GPIO | GPIO_OUT,
+        AMP_MUTE_SDL | GPIO_GPIO | GPIO_OUT,
+        AMP_MUTE_SDR | GPIO_GPIO | GPIO_OUT,
 };
 static struct gpio visstrim_m10_version_gpios[] = {
@@ -166,6 +177,26 @@ static const struct gpio visstrim_m10_gpios[] __initconst = {
                .flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW,
                .label = "usbotg_cs",
        },
+        {
+                .gpio = AMP_GAIN_0,
+                .flags = GPIOF_DIR_OUT,
+                .label = "amp-gain-0",
+        },
+        {
+                .gpio = AMP_GAIN_1,
+                .flags = GPIOF_DIR_OUT,
+                .label = "amp-gain-1",
+        },
+        {
+                .gpio = AMP_MUTE_SDL,
+                .flags = GPIOF_DIR_OUT,
+                .label = "amp-mute-sdl",
+        },
+        {
+                .gpio = AMP_MUTE_SDR,
+                .flags = GPIOF_DIR_OUT,
+                .label = "amp-mute-sdr",
+        },
 };
 /* Camera */
@@ -233,10 +264,8 @@ static void __init visstrim_camera_init(void)
 static void __init visstrim_reserve(void)
 {
        /* reserve 4 MiB for mx2-camera */
-        mx2_camera_base = memblock_alloc(MX2_CAMERA_BUF_SIZE,
+        mx2_camera_base = arm_memblock_steal(3 * MX2_CAMERA_BUF_SIZE,
                        MX2_CAMERA_BUF_SIZE);
-        memblock_free(mx2_camera_base, MX2_CAMERA_BUF_SIZE);
-        memblock_remove(mx2_camera_base, MX2_CAMERA_BUF_SIZE);
 }
 /* GPIOs used as events for applications */
@@ -405,6 +434,55 @@ static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = {
        .flags                  = IMX_SSI_DMA | IMX_SSI_SYN,
 };
+/* coda */
+static void __init visstrim_coda_init(void)
+{
+        struct platform_device *pdev;
+        int dma;
+        pdev = imx27_add_coda();
+        dma = dma_declare_coherent_memory(&pdev->dev,
+                                          mx2_camera_base + MX2_CAMERA_BUF_SIZE,
+                                          mx2_camera_base + MX2_CAMERA_BUF_SIZE,
+                                          MX2_CAMERA_BUF_SIZE,
+                                          DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+        if (!(dma & DMA_MEMORY_MAP))
+                return;
+}
+/* DMA deinterlace */
+static struct platform_device visstrim_deinterlace = {
+        .name = "m2m-deinterlace",
+        .id = 0,
+};
+static void __init visstrim_deinterlace_init(void)
+{
+        int ret = -ENOMEM;
+        struct platform_device *pdev = &visstrim_deinterlace;
+        int dma;
+        ret = platform_device_register(pdev);
+        dma = dma_declare_coherent_memory(&pdev->dev,
+                                          mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
+                                          mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
+                                          MX2_CAMERA_BUF_SIZE,
+                                          DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+        if (!(dma & DMA_MEMORY_MAP))
+                return;
+}
+/* Audio */
+static const struct snd_mx27vis_platform_data snd_mx27vis_pdata __initconst = {
+        .amp_gain0_gpio = AMP_GAIN_0,
+        .amp_gain1_gpio = AMP_GAIN_1,
+        .amp_mutel_gpio = AMP_MUTE_SDL,
+        .amp_muter_gpio = AMP_MUTE_SDR,
+};
 static void __init visstrim_m10_revision(void)
 {
        int exp_version = 0;
@@ -463,11 +541,14 @@ static void __init visstrim_m10_board_init(void)
        imx27_add_fec(NULL);
        imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        imx_add_platform_device("mx27vis", 0, NULL, 0, NULL, 0);
+        imx_add_platform_device("mx27vis", 0, NULL, 0, &snd_mx27vis_pdata,
+                                sizeof(snd_mx27vis_pdata));
        platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
                                      &iclink_tvp5150, sizeof(iclink_tvp5150));
        gpio_led_register_device(0, &visstrim_m10_led_data);
+        visstrim_deinterlace_init();
        visstrim_camera_init();
+        visstrim_coda_init();
 }
 static void __init visstrim_m10_timer_init(void)
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/mach-imx53.c
index 1b7a2fc36591..29711e95579f 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -17,7 +17,6 @@
 #include <linux/irq.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
@@ -51,14 +50,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
        { /* sentinel */ }
 };
-static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
-        { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
-        { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
-        { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
-        { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
-        { /* sentinel */ }
-};
 static void __init imx53_qsb_init(void)
 {
        struct clk *clk;
@@ -74,20 +65,6 @@ static void __init imx53_qsb_init(void)
 static void __init imx53_dt_init(void)
 {
-        struct device_node *node;
-        const struct of_device_id *of_id;
-        void (*func)(void);
-        pinctrl_provide_dummies();
-        node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
-        if (node) {
-                of_id = of_match_node(imx53_iomuxc_of_match, node);
-                func = of_id->data;
-                func();
-                of_node_put(node);
-        }
        if (of_machine_is_compatible("fsl,imx53-qsb"))
                imx53_qsb_init();
@@ -105,10 +82,6 @@ static struct sys_timer imx53_timer = {
 };
 static const char *imx53_dt_board_compat[] __initdata = {
-        "fsl,imx53-ard",
-        "fsl,imx53-evk",
-        "fsl,imx53-qsb",
-        "fsl,imx53-smd",
        "fsl,imx53",
        NULL
 };
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 045b3f6a387d..47c91f7185d2 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -22,10 +22,10 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
 #include <linux/phy.h>
+#include <linux/regmap.h>
 #include <linux/micrel_phy.h>
-#include <linux/mfd/anatop.h>
+#include <linux/mfd/syscon.h>
 #include <asm/cpuidle.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -100,7 +100,6 @@ static void __init imx6q_sabrelite_cko1_setup(void)
        clk_set_parent(cko1_sel, ahb);
        rate = clk_round_rate(cko1, 16000000);
        clk_set_rate(cko1, rate);
-        clk_register_clkdev(cko1, NULL, "0-000a");
 put_clk:
        if (!IS_ERR(cko1_sel))
                clk_put(cko1_sel);
@@ -120,20 +119,7 @@ static void __init imx6q_sabrelite_init(void)
 static void __init imx6q_usb_init(void)
 {
-        struct device_node *np;
+        struct regmap *anatop;
-        struct platform_device *pdev = NULL;
-        struct anatop *adata = NULL;
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
-        if (np)
-                pdev = of_find_device_by_node(np);
-        if (pdev)
-                adata = platform_get_drvdata(pdev);
-        if (!adata) {
-                if (np)
-                        of_node_put(np);
-                return;
-        }
 #define HW_ANADIG_USB1_CHRG_DETECT              0x000001b0
 #define HW_ANADIG_USB2_CHRG_DETECT              0x00000210
@@ -141,30 +127,25 @@ static void __init imx6q_usb_init(void)
 #define BM_ANADIG_USB_CHRG_DETECT_EN_B          0x00100000
 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B    0x00080000
-        /*
+        anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
-         * The external charger detector needs to be disabled,
+        if (!IS_ERR(anatop)) {
-         * or the signal at DP will be poor
+                /*
-         */
+                 * The external charger detector needs to be disabled,
-        anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT,
+                 * or the signal at DP will be poor
-                        BM_ANADIG_USB_CHRG_DETECT_EN_B
+                 */
-                        | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
+                regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
-                        ~0);
+                                BM_ANADIG_USB_CHRG_DETECT_EN_B
-        anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT,
+                                | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
-                        BM_ANADIG_USB_CHRG_DETECT_EN_B |
+                regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
-                        BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
+                                BM_ANADIG_USB_CHRG_DETECT_EN_B |
-                        ~0);
+                                BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+        } else {
-        of_node_put(np);
+                pr_warn("failed to find fsl,imx6q-anatop regmap\n");
+        }
 }
 static void __init imx6q_init_machine(void)
 {
-        /*
-         * This should be removed when all imx6q boards have pinctrl
-         * states for devices defined in device tree.
-         */
-        pinctrl_provide_dummies();
        if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
                imx6q_sabrelite_init();
@@ -218,14 +199,12 @@ static struct sys_timer imx6q_timer = {
 };
 static const char *imx6q_dt_compat[] __initdata = {
-        "fsl,imx6q-arm2",
-        "fsl,imx6q-sabrelite",
-        "fsl,imx6q-sabresd",
        "fsl,imx6q",
        NULL,
 };
 DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
+        .smp            = smp_ops(imx_smp_ops),
        .map_io         = imx6q_map_io,
        .init_irq       = imx6q_init_irq,
        .handle_irq     = imx6q_handle_irq,
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 5d08533ab2c7..0330078ff788 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -36,7 +36,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <mach/clock.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
@@ -259,13 +258,13 @@ static void __init kzm_board_init(void)
 */
 static struct map_desc kzm_io_desc[] __initdata = {
        {
-                .virtual        = MX31_CS4_BASE_ADDR_VIRT,
+                .virtual        = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
                .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
                .length         = MX31_CS4_SIZE,
                .type           = MT_DEVICE
        },
        {
-                .virtual        = MX31_CS5_BASE_ADDR_VIRT,
+                .virtual        = (unsigned long)MX31_CS5_BASE_ADDR_VIRT,
                .pfn            = __phys_to_pfn(MX31_CS5_BASE_ADDR),
                .length         = MX31_CS5_SIZE,
                .type           = MT_DEVICE
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 58c24c1a7ab7..05996f39005c 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -158,6 +158,11 @@ static const int mx27pdk_pins[] __initconst = {
        PB21_PF_CSI_HSYNC,
        CSI_PWRDWN | GPIO_GPIO | GPIO_OUT,
        CSI_RESET | GPIO_GPIO | GPIO_OUT,
+        /* SSI4 */
+        PC16_PF_SSI4_FS,
+        PC17_PF_SSI4_RXD,
+        PC18_PF_SSI4_TXD,
+        PC19_PF_SSI4_CLK,
 };
 static struct gpio mx27_3ds_camera_gpios[] = {
@@ -329,13 +334,24 @@ static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
 };
 /* MC13783 */
+static struct mc13xxx_codec_platform_data mx27_3ds_codec = {
+        .dac_ssi_port = MC13783_SSI1_PORT,
+        .adc_ssi_port = MC13783_SSI1_PORT,
+};
 static struct mc13xxx_platform_data mc13783_pdata = {
        .regulators = {
                .regulators = mx27_3ds_regulators,
                .num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
        },
-        .flags  = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC,
+        .flags  = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC |
+                                                MC13XXX_USE_CODEC,
+        .codec = &mx27_3ds_codec,
+};
+static struct imx_ssi_platform_data mx27_3ds_ssi_pdata = {
+        .flags = IMX_SSI_DMA | IMX_SSI_NET,
 };
 /* SPI */
@@ -512,6 +528,9 @@ static void __init mx27pdk_init(void)
        }
        imx27_add_mx2_camera(&mx27_3ds_cam_pdata);
+        imx27_add_imx_ssi(0, &mx27_3ds_ssi_pdata);
+        imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
 }
 static void __init mx27pdk_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index d37f4809c556..e774b07f48d3 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -540,7 +540,7 @@ static void __init mxc_init_audio(void)
 */
 static struct map_desc mx31ads_io_desc[] __initdata = {
        {
-                .virtual        = MX31_CS4_BASE_ADDR_VIRT,
+                .virtual        = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
                .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
                .length         = CS4_CS8900_MMIO_START,
                .type           = MT_DEVICE
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index c8785b39eaed..ef57cff5abfb 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -207,7 +207,7 @@ static struct platform_device physmap_flash_device = {
 */
 static struct map_desc mx31lite_io_desc[] __initdata = {
        {
-                .virtual = MX31_CS4_BASE_ADDR_VIRT,
+                .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
                .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
                .length = MX31_CS4_SIZE,
                .type = MT_DEVICE
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index d46290b288ed..459e754ef8c9 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -47,7 +47,7 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ulpi.h>
-#include <mach/ssi.h>
+#include <linux/platform_data/asoc-imx-ssi.h>
 #include "devices-imx31.h"
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
deleted file mode 100644
index 8d09c0126cab..000000000000
--- a/arch/arm/mach-imx/mach-mx51_efikamx.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * Copyright (C) 2010 Linaro Limited
- *
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-#include <asm/setup.h>
-#include <asm/system_info.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include "devices-imx51.h"
-#include "efika.h"
-#define EFIKAMX_PCBID0          IMX_GPIO_NR(3, 16)
-#define EFIKAMX_PCBID1          IMX_GPIO_NR(3, 17)
-#define EFIKAMX_PCBID2          IMX_GPIO_NR(3, 11)
-#define EFIKAMX_BLUE_LED        IMX_GPIO_NR(3, 13)
-#define EFIKAMX_GREEN_LED       IMX_GPIO_NR(3, 14)
-#define EFIKAMX_RED_LED         IMX_GPIO_NR(3, 15)
-#define EFIKAMX_POWER_KEY       IMX_GPIO_NR(2, 31)
-/* board 1.1 doesn't have same reset gpio */
-#define EFIKAMX_RESET1_1        IMX_GPIO_NR(3, 2)
-#define EFIKAMX_RESET           IMX_GPIO_NR(1, 4)
-#define EFIKAMX_POWEROFF        IMX_GPIO_NR(4, 13)
-#define EFIKAMX_PMIC            IMX_GPIO_NR(1, 6)
-/* the pci ids pin have pull up. they're driven low according to board id */
-#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
-static iomux_v3_cfg_t mx51efikamx_pads[] = {
-        /* board id */
-        MX51_PAD_PCBID0,
-        MX51_PAD_PCBID1,
-        MX51_PAD_PCBID2,
-        /* leds */
-        MX51_PAD_CSI1_D9__GPIO3_13,
-        MX51_PAD_CSI1_VSYNC__GPIO3_14,
-        MX51_PAD_CSI1_HSYNC__GPIO3_15,
-        /* power key */
-        MX51_PAD_PWRKEY,
-        /* reset */
-        MX51_PAD_DI1_PIN13__GPIO3_2,
-        MX51_PAD_GPIO1_4__GPIO1_4,
-        /* power off */
-        MX51_PAD_CSI2_VSYNC__GPIO4_13,
-};
-/*   PCBID2  PCBID1 PCBID0  STATE
-        1       1      1    ER1:rev1.1
-        1       1      0    ER2:rev1.2
-        1       0      1    ER3:rev1.3
-        1       0      0    ER4:rev1.4
-*/
-static void __init mx51_efikamx_board_id(void)
-{
-        int id;
-        /* things are taking time to settle */
-        msleep(150);
-        gpio_request(EFIKAMX_PCBID0, "pcbid0");
-        gpio_direction_input(EFIKAMX_PCBID0);
-        gpio_request(EFIKAMX_PCBID1, "pcbid1");
-        gpio_direction_input(EFIKAMX_PCBID1);
-        gpio_request(EFIKAMX_PCBID2, "pcbid2");
-        gpio_direction_input(EFIKAMX_PCBID2);
-        id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0;
-        id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1;
-        id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2;
-        switch (id) {
-        case 7:
-                system_rev = 0x11;
-                break;
-        case 6:
-                system_rev = 0x12;
-                break;
-        case 5:
-                system_rev = 0x13;
-                break;
-        case 4:
-                system_rev = 0x14;
-                break;
-        default:
-                system_rev = 0x10;
-                break;
-        }
-        if ((system_rev == 0x10)
-                || (system_rev == 0x12)
-                || (system_rev == 0x14)) {
-                printk(KERN_WARNING
-                        "EfikaMX: Unsupported board revision 1.%u!\n",
-                        system_rev & 0xf);
-        }
-}
-static struct gpio_led mx51_efikamx_leds[] __initdata = {
-        {
-                .name = "efikamx:green",
-                .default_trigger = "default-on",
-                .gpio = EFIKAMX_GREEN_LED,
-        },
-        {
-                .name = "efikamx:red",
-                .default_trigger = "ide-disk",
-                .gpio = EFIKAMX_RED_LED,
-        },
-        {
-                .name = "efikamx:blue",
-                .default_trigger = "mmc0",
-                .gpio = EFIKAMX_BLUE_LED,
-        },
-};
-static const struct gpio_led_platform_data
-                mx51_efikamx_leds_data __initconst = {
-        .leds = mx51_efikamx_leds,
-        .num_leds = ARRAY_SIZE(mx51_efikamx_leds),
-};
-static struct esdhc_platform_data sd_pdata = {
-        .cd_type = ESDHC_CD_CONTROLLER,
-        .wp_type = ESDHC_WP_CONTROLLER,
-};
-static struct gpio_keys_button mx51_efikamx_powerkey[] = {
-        {
-                .code = KEY_POWER,
-                .gpio = EFIKAMX_POWER_KEY,
-                .type = EV_PWR,
-                .desc = "Power Button (CM)",
-                .wakeup = 1,
-                .debounce_interval = 10, /* ms */
-        },
-};
-static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
-        .buttons = mx51_efikamx_powerkey,
-        .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
-};
-static void mx51_efikamx_restart(char mode, const char *cmd)
-{
-        if (system_rev == 0x11)
-                gpio_direction_output(EFIKAMX_RESET1_1, 0);
-        else
-                gpio_direction_output(EFIKAMX_RESET, 0);
-}
-static struct regulator *pwgt1, *pwgt2, *coincell;
-static void mx51_efikamx_power_off(void)
-{
-        if (!IS_ERR(coincell))
-                regulator_disable(coincell);
-        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-                regulator_disable(pwgt2);
-                regulator_disable(pwgt1);
-        }
-        gpio_direction_output(EFIKAMX_POWEROFF, 1);
-}
-static int __init mx51_efikamx_power_init(void)
-{
-        pwgt1 = regulator_get(NULL, "pwgt1");
-        pwgt2 = regulator_get(NULL, "pwgt2");
-        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-                regulator_enable(pwgt1);
-                regulator_enable(pwgt2);
-        }
-        gpio_request(EFIKAMX_POWEROFF, "poweroff");
-        pm_power_off = mx51_efikamx_power_off;
-        /* enable coincell charger. maybe need a small power driver ? */
-        coincell = regulator_get(NULL, "coincell");
-        if (!IS_ERR(coincell)) {
-                regulator_set_voltage(coincell, 3000000, 3000000);
-                regulator_enable(coincell);
-        }
-        regulator_has_full_constraints();
-        return 0;
-}
-static void __init mx51_efikamx_init_late(void)
-{
-        imx51_init_late();
-        mx51_efikamx_power_init();
-}
-static void __init mx51_efikamx_init(void)
-{
-        imx51_soc_init();
-        mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
-                                        ARRAY_SIZE(mx51efikamx_pads));
-        efika_board_common_init();
-        mx51_efikamx_board_id();
-        /* on < 1.2 boards both SD controllers are used */
-        if (system_rev < 0x12) {
-                imx51_add_sdhci_esdhc_imx(0, NULL);
-                imx51_add_sdhci_esdhc_imx(1, &sd_pdata);
-                mx51_efikamx_leds[2].default_trigger = "mmc1";
-        } else
-                imx51_add_sdhci_esdhc_imx(0, &sd_pdata);
-        gpio_led_register_device(-1, &mx51_efikamx_leds_data);
-        imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
-        if (system_rev == 0x11) {
-                gpio_request(EFIKAMX_RESET1_1, "reset");
-                gpio_direction_output(EFIKAMX_RESET1_1, 1);
-        } else {
-                gpio_request(EFIKAMX_RESET, "reset");
-                gpio_direction_output(EFIKAMX_RESET, 1);
-        }
-        /*
-         * enable wifi by default only on mx
-         * sb and mx have same wlan pin but the value to enable it are
-         * different :/
-         */
-        gpio_request(EFIKA_WLAN_EN, "wlan_en");
-        gpio_direction_output(EFIKA_WLAN_EN, 0);
-        msleep(10);
-        gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
-        gpio_direction_output(EFIKA_WLAN_RESET, 0);
-        msleep(10);
-        gpio_set_value(EFIKA_WLAN_RESET, 1);
-}
-static void __init mx51_efikamx_timer_init(void)
-{
-        mx51_clocks_init(32768, 24000000, 22579200, 24576000);
-}
-static struct sys_timer mx51_efikamx_timer = {
-        .init = mx51_efikamx_timer_init,
-};
-MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)")
-        .atag_offset = 0x100,
-        .map_io = mx51_map_io,
-        .init_early = imx51_init_early,
-        .init_irq = mx51_init_irq,
-        .handle_irq = imx51_handle_irq,
-        .timer = &mx51_efikamx_timer,
-        .init_machine = mx51_efikamx_init,
-        .init_late = mx51_efikamx_init_late,
-        .restart = mx51_efikamx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
deleted file mode 100644
index fdbd181b97ef..000000000000
--- a/arch/arm/mach-imx/mach-mx51_efikasb.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
- *
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <mach/ulpi.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-#include <asm/setup.h>
-#include <asm/system_info.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include "devices-imx51.h"
-#include "efika.h"
-#define EFIKASB_USBH2_STP       IMX_GPIO_NR(2, 20)
-#define EFIKASB_GREEN_LED       IMX_GPIO_NR(1, 3)
-#define EFIKASB_WHITE_LED       IMX_GPIO_NR(2, 25)
-#define EFIKASB_PCBID0          IMX_GPIO_NR(2, 28)
-#define EFIKASB_PCBID1          IMX_GPIO_NR(2, 29)
-#define EFIKASB_PWRKEY          IMX_GPIO_NR(2, 31)
-#define EFIKASB_LID             IMX_GPIO_NR(3, 14)
-#define EFIKASB_POWEROFF        IMX_GPIO_NR(4, 13)
-#define EFIKASB_RFKILL          IMX_GPIO_NR(3, 1)
-#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
-#define MX51_PAD_SD1_CD IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-static iomux_v3_cfg_t mx51efikasb_pads[] = {
-        /* USB HOST2 */
-        MX51_PAD_EIM_D16__USBH2_DATA0,
-        MX51_PAD_EIM_D17__USBH2_DATA1,
-        MX51_PAD_EIM_D18__USBH2_DATA2,
-        MX51_PAD_EIM_D19__USBH2_DATA3,
-        MX51_PAD_EIM_D20__USBH2_DATA4,
-        MX51_PAD_EIM_D21__USBH2_DATA5,
-        MX51_PAD_EIM_D22__USBH2_DATA6,
-        MX51_PAD_EIM_D23__USBH2_DATA7,
-        MX51_PAD_EIM_A24__USBH2_CLK,
-        MX51_PAD_EIM_A25__USBH2_DIR,
-        MX51_PAD_EIM_A26__USBH2_STP,
-        MX51_PAD_EIM_A27__USBH2_NXT,
-        /* leds */
-        MX51_PAD_EIM_CS0__GPIO2_25,
-        MX51_PAD_GPIO1_3__GPIO1_3,
-        /* pcb id */
-        MX51_PAD_EIM_CS3__GPIO2_28,
-        MX51_PAD_EIM_CS4__GPIO2_29,
-        /* lid */
-        MX51_PAD_CSI1_VSYNC__GPIO3_14,
-        /* power key*/
-        MX51_PAD_PWRKEY,
-        /* wifi/bt button */
-        MX51_PAD_DI1_PIN12__GPIO3_1,
-        /* power off */
-        MX51_PAD_CSI2_VSYNC__GPIO4_13,
-        /* wdog reset */
-        MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
-        /* BT */
-        MX51_PAD_EIM_A17__GPIO2_11,
-        MX51_PAD_SD1_CD,
-};
-static int initialize_usbh2_port(struct platform_device *pdev)
-{
-        iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
-        iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
-        mxc_iomux_v3_setup_pad(usbh2gpio);
-        gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
-        gpio_direction_output(EFIKASB_USBH2_STP, 0);
-        msleep(1);
-        gpio_set_value(EFIKASB_USBH2_STP, 1);
-        msleep(1);
-        gpio_free(EFIKASB_USBH2_STP);
-        mxc_iomux_v3_setup_pad(usbh2stp);
-        mdelay(10);
-        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
-}
-static struct mxc_usbh_platform_data usbh2_config __initdata = {
-        .init   = initialize_usbh2_port,
-        .portsc = MXC_EHCI_MODE_ULPI,
-};
-static void __init mx51_efikasb_usb(void)
-{
-        usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                        ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
-        if (usbh2_config.otg)
-                imx51_add_mxc_ehci_hs(2, &usbh2_config);
-}
-static const struct gpio_led mx51_efikasb_leds[] __initconst = {
-        {
-                .name = "efikasb:green",
-                .default_trigger = "default-on",
-                .gpio = EFIKASB_GREEN_LED,
-                .active_low = 1,
-        },
-        {
-                .name = "efikasb:white",
-                .default_trigger = "caps",
-                .gpio = EFIKASB_WHITE_LED,
-        },
-};
-static const struct gpio_led_platform_data
-                mx51_efikasb_leds_data __initconst = {
-        .leds = mx51_efikasb_leds,
-        .num_leds = ARRAY_SIZE(mx51_efikasb_leds),
-};
-static struct gpio_keys_button mx51_efikasb_keys[] = {
-        {
-                .code = KEY_POWER,
-                .gpio = EFIKASB_PWRKEY,
-                .type = EV_KEY,
-                .desc = "Power Button",
-                .wakeup = 1,
-                .active_low = 1,
-        },
-        {
-                .code = SW_LID,
-                .gpio = EFIKASB_LID,
-                .type = EV_SW,
-                .desc = "Lid Switch",
-                .active_low = 1,
-        },
-        {
-                .code = KEY_RFKILL,
-                .gpio = EFIKASB_RFKILL,
-                .type = EV_KEY,
-                .desc = "rfkill",
-                .active_low = 1,
-        },
-};
-static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
-        .buttons = mx51_efikasb_keys,
-        .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
-};
-static struct esdhc_platform_data sd0_pdata = {
-#define EFIKASB_SD1_CD  IMX_GPIO_NR(2, 27)
-        .cd_gpio = EFIKASB_SD1_CD,
-        .cd_type = ESDHC_CD_GPIO,
-        .wp_type = ESDHC_WP_CONTROLLER,
-};
-static struct esdhc_platform_data sd1_pdata = {
-        .cd_type = ESDHC_CD_CONTROLLER,
-        .wp_type = ESDHC_WP_CONTROLLER,
-};
-static struct regulator *pwgt1, *pwgt2;
-static void mx51_efikasb_power_off(void)
-{
-        gpio_set_value(EFIKA_USB_PHY_RESET, 0);
-        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-                regulator_disable(pwgt2);
-                regulator_disable(pwgt1);
-        }
-        gpio_direction_output(EFIKASB_POWEROFF, 1);
-}
-static int __init mx51_efikasb_power_init(void)
-{
-        pwgt1 = regulator_get(NULL, "pwgt1");
-        pwgt2 = regulator_get(NULL, "pwgt2");
-        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-                regulator_enable(pwgt1);
-                regulator_enable(pwgt2);
-        }
-        gpio_request(EFIKASB_POWEROFF, "poweroff");
-        pm_power_off = mx51_efikasb_power_off;
-        regulator_has_full_constraints();
-        return 0;
-}
-static void __init mx51_efikasb_init_late(void)
-{
-        imx51_init_late();
-        mx51_efikasb_power_init();
-}
-/* 01     R1.3 board
-   10     R2.0 board */
-static void __init mx51_efikasb_board_id(void)
-{
-        int id;
-        gpio_request(EFIKASB_PCBID0, "pcb id0");
-        gpio_direction_input(EFIKASB_PCBID0);
-        gpio_request(EFIKASB_PCBID1, "pcb id1");
-        gpio_direction_input(EFIKASB_PCBID1);
-        id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0;
-        id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1;
-        switch (id) {
-        default:
-                break;
-        case 1:
-                system_rev = 0x13;
-                break;
-        case 2:
-                system_rev = 0x20;
-                break;
-        }
-}
-static void __init efikasb_board_init(void)
-{
-        imx51_soc_init();
-        mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
-                                        ARRAY_SIZE(mx51efikasb_pads));
-        efika_board_common_init();
-        mx51_efikasb_board_id();
-        mx51_efikasb_usb();
-        imx51_add_sdhci_esdhc_imx(0, &sd0_pdata);
-        imx51_add_sdhci_esdhc_imx(1, &sd1_pdata);
-        gpio_led_register_device(-1, &mx51_efikasb_leds_data);
-        imx_add_gpio_keys(&mx51_efikasb_keys_data);
-}
-static void __init mx51_efikasb_timer_init(void)
-{
-        mx51_clocks_init(32768, 24000000, 22579200, 24576000);
-}
-static struct sys_timer mx51_efikasb_timer = {
-        .init   = mx51_efikasb_timer_init,
-};
-MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)")
-        .atag_offset = 0x100,
-        .map_io = mx51_map_io,
-        .init_early = imx51_init_early,
-        .init_irq = mx51_init_irq,
-        .handle_irq = imx51_handle_irq,
-        .init_machine =  efikasb_board_init,
-        .init_late = mx51_efikasb_init_late,
-        .timer = &mx51_efikasb_timer,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
deleted file mode 100644
index 6c28e65f424d..000000000000
--- a/arch/arm/mach-imx/mach-mx53_ard.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/smsc911x.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include "devices-imx53.h"
-#define ARD_ETHERNET_INT_B      IMX_GPIO_NR(2, 31)
-#define ARD_SD1_CD              IMX_GPIO_NR(1, 1)
-#define ARD_SD1_WP              IMX_GPIO_NR(1, 9)
-#define ARD_I2CPORTEXP_B        IMX_GPIO_NR(2, 3)
-#define ARD_VOLUMEDOWN          IMX_GPIO_NR(4, 0)
-#define ARD_HOME                        IMX_GPIO_NR(5, 10)
-#define ARD_BACK                        IMX_GPIO_NR(5, 11)
-#define ARD_PROG                        IMX_GPIO_NR(5, 12)
-#define ARD_VOLUMEUP            IMX_GPIO_NR(5, 13)
-static iomux_v3_cfg_t mx53_ard_pads[] = {
-        /* UART1 */
-        MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
-        MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
-        /* WEIM for CS1 */
-        MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
-        MX53_PAD_EIM_D16__EMI_WEIM_D_16,
-        MX53_PAD_EIM_D17__EMI_WEIM_D_17,
-        MX53_PAD_EIM_D18__EMI_WEIM_D_18,
-        MX53_PAD_EIM_D19__EMI_WEIM_D_19,
-        MX53_PAD_EIM_D20__EMI_WEIM_D_20,
-        MX53_PAD_EIM_D21__EMI_WEIM_D_21,
-        MX53_PAD_EIM_D22__EMI_WEIM_D_22,
-        MX53_PAD_EIM_D23__EMI_WEIM_D_23,
-        MX53_PAD_EIM_D24__EMI_WEIM_D_24,
-        MX53_PAD_EIM_D25__EMI_WEIM_D_25,
-        MX53_PAD_EIM_D26__EMI_WEIM_D_26,
-        MX53_PAD_EIM_D27__EMI_WEIM_D_27,
-        MX53_PAD_EIM_D28__EMI_WEIM_D_28,
-        MX53_PAD_EIM_D29__EMI_WEIM_D_29,
-        MX53_PAD_EIM_D30__EMI_WEIM_D_30,
-        MX53_PAD_EIM_D31__EMI_WEIM_D_31,
-        MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
-        MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
-        MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
-        MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
-        MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
-        MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
-        MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
-        MX53_PAD_EIM_OE__EMI_WEIM_OE,
-        MX53_PAD_EIM_RW__EMI_WEIM_RW,
-        MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
-        /* SDHC1 */
-        MX53_PAD_SD1_CMD__ESDHC1_CMD,
-        MX53_PAD_SD1_CLK__ESDHC1_CLK,
-        MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-        MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-        MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-        MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-        MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
-        MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
-        MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
-        MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
-        MX53_PAD_GPIO_1__GPIO1_1,
-        MX53_PAD_GPIO_9__GPIO1_9,
-        /* I2C2 */
-        MX53_PAD_EIM_EB2__I2C2_SCL,
-        MX53_PAD_KEY_ROW3__I2C2_SDA,
-        /* I2C3 */
-        MX53_PAD_GPIO_3__I2C3_SCL,
-        MX53_PAD_GPIO_16__I2C3_SDA,
-        /* GPIO */
-        MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */
-        MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */
-        MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */
-        MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */
-        MX53_PAD_GPIO_10__GPIO4_0,              /* vol down */
-};
-#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)    \
-{                                                       \
-        .gpio           = gpio_num,                             \
-        .type           = EV_KEY,                               \
-        .code           = ev_code,                              \
-        .active_low     = act_low,                              \
-        .desc           = "btn " descr,                 \
-        .wakeup         = wake,                                 \
-}
-static struct gpio_keys_button ard_buttons[] = {
-        GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
-        GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
-        GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
-        GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
-        GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
-};
-static const struct gpio_keys_platform_data ard_button_data __initconst = {
-        .buttons        = ard_buttons,
-        .nbuttons       = ARRAY_SIZE(ard_buttons),
-};
-static struct resource ard_smsc911x_resources[] = {
-        {
-                .start = MX53_CS1_64MB_BASE_ADDR,
-                .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                /* irq number is run-time assigned */
-                .flags = IORESOURCE_IRQ,
-        },
-};
-struct smsc911x_platform_config ard_smsc911x_config = {
-        .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .flags = SMSC911X_USE_32BIT,
-};
-static struct platform_device ard_smsc_lan9220_device = {
-        .name = "smsc911x",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(ard_smsc911x_resources),
-        .resource = ard_smsc911x_resources,
-        .dev = {
-                .platform_data = &ard_smsc911x_config,
-        },
-};
-static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
-        .cd_gpio = ARD_SD1_CD,
-        .wp_gpio = ARD_SD1_WP,
-};
-static struct imxi2c_platform_data mx53_ard_i2c2_data = {
-        .bitrate = 50000,
-};
-static struct imxi2c_platform_data mx53_ard_i2c3_data = {
-        .bitrate = 400000,
-};
-static void __init mx53_ard_io_init(void)
-{
-        gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
-        gpio_direction_input(ARD_ETHERNET_INT_B);
-        gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
-        gpio_direction_output(ARD_I2CPORTEXP_B, 1);
-}
-/* Config CS1 settings for ethernet controller */
-static int weim_cs_config(void)
-{
-        u32 reg;
-        void __iomem *weim_base, *iomuxc_base;
-        weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
-        if (!weim_base)
-                return -ENOMEM;
-        iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
-        if (!iomuxc_base) {
-                iounmap(weim_base);
-                return -ENOMEM;
-        }
-        /* CS1 timings for LAN9220 */
-        writel(0x20001, (weim_base + 0x18));
-        writel(0x0, (weim_base + 0x1C));
-        writel(0x16000202, (weim_base + 0x20));
-        writel(0x00000002, (weim_base + 0x24));
-        writel(0x16002082, (weim_base + 0x28));
-        writel(0x00000000, (weim_base + 0x2C));
-        writel(0x00000000, (weim_base + 0x90));
-        /* specify 64 MB on CS1 and CS0 on GPR1 */
-        reg = readl(iomuxc_base + 0x4);
-        reg &= ~0x3F;
-        reg |= 0x1B;
-        writel(reg, (iomuxc_base + 0x4));
-        iounmap(iomuxc_base);
-        iounmap(weim_base);
-        return 0;
-}
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-void __init imx53_ard_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
-                                         ARRAY_SIZE(mx53_ard_pads));
-        weim_cs_config();
-}
-static struct platform_device *devices[] __initdata = {
-        &ard_smsc_lan9220_device,
-};
-static void __init mx53_ard_board_init(void)
-{
-        imx53_soc_init();
-        imx53_add_imx_uart(0, NULL);
-        imx53_ard_common_init();
-        mx53_ard_io_init();
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-        ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B);
-        ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-        imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
-        imx53_add_imx2_wdt(0);
-        imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
-        imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
-        imx_add_gpio_keys(&ard_button_data);
-        imx53_add_ahci_imx();
-}
-static void __init mx53_ard_timer_init(void)
-{
-        mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-static struct sys_timer mx53_ard_timer = {
-        .init   = mx53_ard_timer_init,
-};
-MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
-        .map_io = mx53_map_io,
-        .init_early = imx53_init_early,
-        .init_irq = mx53_init_irq,
-        .handle_irq = imx53_handle_irq,
-        .timer = &mx53_ard_timer,
-        .init_machine = mx53_ard_board_init,
-        .init_late      = imx53_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c
deleted file mode 100644
index 09fe2197b491..000000000000
--- a/arch/arm/mach-imx/mach-mx53_evk.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
- */
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <mach/iomux-mx53.h>
-#define MX53_EVK_FEC_PHY_RST    IMX_GPIO_NR(7, 6)
-#define EVK_ECSPI1_CS0          IMX_GPIO_NR(2, 30)
-#define EVK_ECSPI1_CS1          IMX_GPIO_NR(3, 19)
-#define MX53EVK_LED             IMX_GPIO_NR(7, 7)
-#include "devices-imx53.h"
-static iomux_v3_cfg_t mx53_evk_pads[] = {
-        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-        MX53_PAD_PATA_DIOR__UART2_RTS,
-        MX53_PAD_PATA_INTRQ__UART2_CTS,
-        MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
-        MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
-        MX53_PAD_EIM_D16__ECSPI1_SCLK,
-        MX53_PAD_EIM_D17__ECSPI1_MISO,
-        MX53_PAD_EIM_D18__ECSPI1_MOSI,
-        /* ecspi chip select lines */
-        MX53_PAD_EIM_EB2__GPIO2_30,
-        MX53_PAD_EIM_D19__GPIO3_19,
-        /* LED */
-        MX53_PAD_PATA_DA_1__GPIO7_7,
-};
-static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static const struct gpio_led mx53evk_leds[] __initconst = {
-        {
-                .name                   = "green",
-                .default_trigger        = "heartbeat",
-                .gpio                   = MX53EVK_LED,
-        },
-};
-static const struct gpio_led_platform_data mx53evk_leds_data __initconst = {
-        .leds           = mx53evk_leds,
-        .num_leds       = ARRAY_SIZE(mx53evk_leds),
-};
-static inline void mx53_evk_init_uart(void)
-{
-        imx53_add_imx_uart(0, NULL);
-        imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
-        imx53_add_imx_uart(2, NULL);
-}
-static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-static inline void mx53_evk_fec_reset(void)
-{
-        int ret;
-        /* reset FEC PHY */
-        ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW,
-                                                        "fec-phy-reset");
-        if (ret) {
-                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-                return;
-        }
-        msleep(1);
-        gpio_set_value(MX53_EVK_FEC_PHY_RST, 1);
-}
-static const struct fec_platform_data mx53_evk_fec_pdata __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-static struct spi_board_info mx53_evk_spi_board_info[] __initdata = {
-        {
-                .modalias = "mtd_dataflash",
-                .max_speed_hz = 25000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .mode = SPI_MODE_0,
-                .platform_data = NULL,
-        },
-};
-static int mx53_evk_spi_cs[] = {
-        EVK_ECSPI1_CS0,
-        EVK_ECSPI1_CS1,
-};
-static const struct spi_imx_master mx53_evk_spi_data __initconst = {
-        .chipselect     = mx53_evk_spi_cs,
-        .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
-};
-void __init imx53_evk_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
-                                         ARRAY_SIZE(mx53_evk_pads));
-}
-static void __init mx53_evk_board_init(void)
-{
-        imx53_soc_init();
-        imx53_evk_common_init();
-        mx53_evk_init_uart();
-        mx53_evk_fec_reset();
-        imx53_add_fec(&mx53_evk_fec_pdata);
-        imx53_add_imx_i2c(0, &mx53_evk_i2c_data);
-        imx53_add_imx_i2c(1, &mx53_evk_i2c_data);
-        imx53_add_sdhci_esdhc_imx(0, NULL);
-        imx53_add_sdhci_esdhc_imx(1, NULL);
-        spi_register_board_info(mx53_evk_spi_board_info,
-                ARRAY_SIZE(mx53_evk_spi_board_info));
-        imx53_add_ecspi(0, &mx53_evk_spi_data);
-        imx53_add_imx2_wdt(0);
-        gpio_led_register_device(-1, &mx53evk_leds_data);
-}
-static void __init mx53_evk_timer_init(void)
-{
-        mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-static struct sys_timer mx53_evk_timer = {
-        .init   = mx53_evk_timer_init,
-};
-MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
-        .map_io = mx53_map_io,
-        .init_early = imx53_init_early,
-        .init_irq = mx53_init_irq,
-        .handle_irq = imx53_handle_irq,
-        .timer = &mx53_evk_timer,
-        .init_machine = mx53_evk_board_init,
-        .init_late      = imx53_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c
deleted file mode 100644
index 8abe23c1d3c8..000000000000
--- a/arch/arm/mach-imx/mach-mx53_loco.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include "devices-imx53.h"
-#define MX53_LOCO_POWER                 IMX_GPIO_NR(1, 8)
-#define MX53_LOCO_UI1                   IMX_GPIO_NR(2, 14)
-#define MX53_LOCO_UI2                   IMX_GPIO_NR(2, 15)
-#define LOCO_FEC_PHY_RST                IMX_GPIO_NR(7, 6)
-#define LOCO_LED                        IMX_GPIO_NR(7, 7)
-#define LOCO_SD3_CD                     IMX_GPIO_NR(3, 11)
-#define LOCO_SD3_WP                     IMX_GPIO_NR(3, 12)
-#define LOCO_SD1_CD                     IMX_GPIO_NR(3, 13)
-#define LOCO_ACCEL_EN                   IMX_GPIO_NR(6, 14)
-static iomux_v3_cfg_t mx53_loco_pads[] = {
-        /* FEC */
-        MX53_PAD_FEC_MDC__FEC_MDC,
-        MX53_PAD_FEC_MDIO__FEC_MDIO,
-        MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
-        MX53_PAD_FEC_RX_ER__FEC_RX_ER,
-        MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
-        MX53_PAD_FEC_RXD1__FEC_RDATA_1,
-        MX53_PAD_FEC_RXD0__FEC_RDATA_0,
-        MX53_PAD_FEC_TX_EN__FEC_TX_EN,
-        MX53_PAD_FEC_TXD1__FEC_TDATA_1,
-        MX53_PAD_FEC_TXD0__FEC_TDATA_0,
-        /* FEC_nRST */
-        MX53_PAD_PATA_DA_0__GPIO7_6,
-        /* FEC_nINT */
-        MX53_PAD_PATA_DATA4__GPIO2_4,
-        /* AUDMUX5 */
-        MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
-        MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
-        MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
-        MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
-        /* I2C1 */
-        MX53_PAD_CSI0_DAT8__I2C1_SDA,
-        MX53_PAD_CSI0_DAT9__I2C1_SCL,
-        MX53_PAD_NANDF_CS1__GPIO6_14,   /* Accelerometer Enable */
-        /* I2C2 */
-        MX53_PAD_KEY_COL3__I2C2_SCL,
-        MX53_PAD_KEY_ROW3__I2C2_SDA,
-        /* SD1 */
-        MX53_PAD_SD1_CMD__ESDHC1_CMD,
-        MX53_PAD_SD1_CLK__ESDHC1_CLK,
-        MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-        MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-        MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-        MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-        /* SD1_CD */
-        MX53_PAD_EIM_DA13__GPIO3_13,
-        /* SD3 */
-        MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
-        MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
-        MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
-        MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
-        MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
-        MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
-        MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
-        MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
-        MX53_PAD_PATA_IORDY__ESDHC3_CLK,
-        MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-        /* SD3_CD */
-        MX53_PAD_EIM_DA11__GPIO3_11,
-        /* SD3_WP */
-        MX53_PAD_EIM_DA12__GPIO3_12,
-        /* VGA */
-        MX53_PAD_EIM_OE__IPU_DI1_PIN7,
-        MX53_PAD_EIM_RW__IPU_DI1_PIN8,
-        /* DISPLB */
-        MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
-        MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
-        MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
-        MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
-        /* DISP0_POWER_EN */
-        MX53_PAD_EIM_D24__GPIO3_24,
-        /* DISP0 DET INT */
-        MX53_PAD_EIM_D31__GPIO3_31,
-        /* LVDS */
-        MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
-        MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
-        MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
-        MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
-        MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
-        MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
-        MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
-        MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
-        MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
-        MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
-        /* I2C1 */
-        MX53_PAD_CSI0_DAT8__I2C1_SDA,
-        MX53_PAD_CSI0_DAT9__I2C1_SCL,
-        /* UART1 */
-        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-        /* CSI0 */
-        MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
-        MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
-        MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
-        MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
-        MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
-        MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
-        MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
-        MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
-        MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
-        MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
-        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
-        /* DISPLAY */
-        MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
-        MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
-        MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
-        MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
-        MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
-        MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
-        MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
-        MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
-        MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
-        MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
-        MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
-        MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
-        MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
-        MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
-        MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
-        MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
-        MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
-        MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
-        MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
-        MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
-        MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
-        MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
-        MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
-        MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
-        MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
-        MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
-        MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
-        MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
-        /* Audio CLK*/
-        MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
-        /* PWM */
-        MX53_PAD_GPIO_1__PWM2_PWMO,
-        /* SPDIF */
-        MX53_PAD_GPIO_7__SPDIF_PLOCK,
-        MX53_PAD_GPIO_17__SPDIF_OUT1,
-        /* GPIO */
-        MX53_PAD_PATA_DA_1__GPIO7_7,            /* LED */
-        MX53_PAD_PATA_DA_2__GPIO7_8,
-        MX53_PAD_PATA_DATA5__GPIO2_5,
-        MX53_PAD_PATA_DATA6__GPIO2_6,
-        MX53_PAD_PATA_DATA14__GPIO2_14,
-        MX53_PAD_PATA_DATA15__GPIO2_15,
-        MX53_PAD_PATA_INTRQ__GPIO7_2,
-        MX53_PAD_EIM_WAIT__GPIO5_0,
-        MX53_PAD_NANDF_WP_B__GPIO6_9,
-        MX53_PAD_NANDF_RB0__GPIO6_10,
-        MX53_PAD_NANDF_CS1__GPIO6_14,
-        MX53_PAD_NANDF_CS2__GPIO6_15,
-        MX53_PAD_NANDF_CS3__GPIO6_16,
-        MX53_PAD_GPIO_5__GPIO1_5,
-        MX53_PAD_GPIO_16__GPIO7_11,
-        MX53_PAD_GPIO_8__GPIO1_8,
-};
-#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)    \
-{                                                               \
-        .gpio           = gpio_num,                             \
-        .type           = EV_KEY,                               \
-        .code           = ev_code,                              \
-        .active_low     = act_low,                              \
-        .desc           = "btn " descr,                         \
-        .wakeup         = wake,                                 \
-}
-static struct gpio_keys_button loco_buttons[] = {
-        GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
-        GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
-        GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
-};
-static const struct gpio_keys_platform_data loco_button_data __initconst = {
-        .buttons        = loco_buttons,
-        .nbuttons       = ARRAY_SIZE(loco_buttons),
-};
-static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
-        .cd_gpio = LOCO_SD1_CD,
-        .cd_type = ESDHC_CD_GPIO,
-        .wp_type = ESDHC_WP_NONE,
-};
-static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
-        .cd_gpio = LOCO_SD3_CD,
-        .wp_gpio = LOCO_SD3_WP,
-        .cd_type = ESDHC_CD_GPIO,
-        .wp_type = ESDHC_WP_GPIO,
-};
-static inline void mx53_loco_fec_reset(void)
-{
-        int ret;
-        /* reset FEC PHY */
-        ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
-        if (ret) {
-                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-                return;
-        }
-        gpio_direction_output(LOCO_FEC_PHY_RST, 0);
-        msleep(1);
-        gpio_set_value(LOCO_FEC_PHY_RST, 1);
-}
-static const struct fec_platform_data mx53_loco_fec_data __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-static const struct gpio_led mx53loco_leds[] __initconst = {
-        {
-                .name                   = "green",
-                .default_trigger        = "heartbeat",
-                .gpio                   = LOCO_LED,
-        },
-};
-static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
-        .leds           = mx53loco_leds,
-        .num_leds       = ARRAY_SIZE(mx53loco_leds),
-};
-void __init imx53_qsb_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
-                                         ARRAY_SIZE(mx53_loco_pads));
-}
-static struct i2c_board_info mx53loco_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("mma8450", 0x1C),
-        },
-};
-static void __init mx53_loco_board_init(void)
-{
-        int ret;
-        imx53_soc_init();
-        imx53_qsb_common_init();
-        imx53_add_imx_uart(0, NULL);
-        mx53_loco_fec_reset();
-        imx53_add_fec(&mx53_loco_fec_data);
-        imx53_add_imx2_wdt(0);
-        ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en");
-        if (ret)
-                pr_err("Cannot request ACCEL_EN pin: %d\n", ret);
-        i2c_register_board_info(0, mx53loco_i2c_devices,
-                                ARRAY_SIZE(mx53loco_i2c_devices));
-        imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
-        imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
-        imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
-        imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
-        imx_add_gpio_keys(&loco_button_data);
-        gpio_led_register_device(-1, &mx53loco_leds_data);
-        imx53_add_ahci_imx();
-}
-static void __init mx53_loco_timer_init(void)
-{
-        mx53_clocks_init(32768, 24000000, 0, 0);
-}
-static struct sys_timer mx53_loco_timer = {
-        .init   = mx53_loco_timer_init,
-};
-MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
-        .map_io = mx53_map_io,
-        .init_early = imx53_init_early,
-        .init_irq = mx53_init_irq,
-        .handle_irq = imx53_handle_irq,
-        .timer = &mx53_loco_timer,
-        .init_machine = mx53_loco_board_init,
-        .init_late      = imx53_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c
deleted file mode 100644
index b15d6a6d3b68..000000000000
--- a/arch/arm/mach-imx/mach-mx53_smd.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include "devices-imx53.h"
-#define SMD_FEC_PHY_RST         IMX_GPIO_NR(7, 6)
-#define MX53_SMD_SATA_PWR_EN    IMX_GPIO_NR(3, 3)
-static iomux_v3_cfg_t mx53_smd_pads[] = {
-        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-        MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
-        MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
-        MX53_PAD_PATA_DA_1__UART3_CTS,
-        MX53_PAD_PATA_DA_2__UART3_RTS,
-        /* I2C1 */
-        MX53_PAD_CSI0_DAT8__I2C1_SDA,
-        MX53_PAD_CSI0_DAT9__I2C1_SCL,
-        /* SD1 */
-        MX53_PAD_SD1_CMD__ESDHC1_CMD,
-        MX53_PAD_SD1_CLK__ESDHC1_CLK,
-        MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-        MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-        MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-        MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-        /* SD2 */
-        MX53_PAD_SD2_CMD__ESDHC2_CMD,
-        MX53_PAD_SD2_CLK__ESDHC2_CLK,
-        MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
-        MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
-        MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
-        MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
-        /* SD3 */
-        MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
-        MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
-        MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
-        MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
-        MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
-        MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
-        MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
-        MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
-        MX53_PAD_PATA_IORDY__ESDHC3_CLK,
-        MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-};
-static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static inline void mx53_smd_init_uart(void)
-{
-        imx53_add_imx_uart(0, NULL);
-        imx53_add_imx_uart(1, NULL);
-        imx53_add_imx_uart(2, &mx53_smd_uart_data);
-}
-static inline void mx53_smd_fec_reset(void)
-{
-        int ret;
-        /* reset FEC PHY */
-        ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
-        if (ret) {
-                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-                return;
-        }
-        gpio_direction_output(SMD_FEC_PHY_RST, 0);
-        msleep(1);
-        gpio_set_value(SMD_FEC_PHY_RST, 1);
-}
-static const struct fec_platform_data mx53_smd_fec_data __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-static inline void mx53_smd_ahci_pwr_on(void)
-{
-        int ret;
-        /* Enable SATA PWR */
-        ret = gpio_request_one(MX53_SMD_SATA_PWR_EN,
-                        GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr");
-        if (ret) {
-                pr_err("failed to enable SATA_PWR_EN: %d\n", ret);
-                return;
-        }
-}
-void __init imx53_smd_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
-                                         ARRAY_SIZE(mx53_smd_pads));
-}
-static void __init mx53_smd_board_init(void)
-{
-        imx53_soc_init();
-        imx53_smd_common_init();
-        mx53_smd_init_uart();
-        mx53_smd_fec_reset();
-        imx53_add_fec(&mx53_smd_fec_data);
-        imx53_add_imx2_wdt(0);
-        imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
-        imx53_add_sdhci_esdhc_imx(0, NULL);
-        imx53_add_sdhci_esdhc_imx(1, NULL);
-        imx53_add_sdhci_esdhc_imx(2, NULL);
-        mx53_smd_ahci_pwr_on();
-        imx53_add_ahci_imx();
-}
-static void __init mx53_smd_timer_init(void)
-{
-        mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-static struct sys_timer mx53_smd_timer = {
-        .init   = mx53_smd_timer_init,
-};
-MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
-        .map_io = mx53_map_io,
-        .init_early = imx53_init_early,
-        .init_irq = mx53_init_irq,
-        .handle_irq = imx53_handle_irq,
-        .timer = &mx53_smd_timer,
-        .init_machine = mx53_smd_board_init,
-        .init_late      = imx53_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 52d8f534be10..acb0aadb4255 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -128,25 +128,6 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = {
        .script_addrs = &imx51_sdma_script,
 };
-static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
-        .ap_2_ap_addr = 642,
-        .app_2_mcu_addr = 683,
-        .mcu_2_app_addr = 747,
-        .uart_2_mcu_addr = 817,
-        .shp_2_mcu_addr = 891,
-        .mcu_2_shp_addr = 960,
-        .uartsh_2_mcu_addr = 1032,
-        .spdif_2_mcu_addr = 1100,
-        .mcu_2_spdif_addr = 1134,
-        .firi_2_mcu_addr = 1193,
-        .mcu_2_firi_addr = 1290,
-};
-static struct sdma_platform_data imx53_sdma_pdata __initdata = {
-        .fw_name = "sdma-imx53.bin",
-        .script_addrs = &imx53_sdma_script,
-};
 static const struct resource imx50_audmux_res[] __initconst = {
        DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
 };
@@ -155,10 +136,6 @@ static const struct resource imx51_audmux_res[] __initconst = {
        DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
 };
-static const struct resource imx53_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K),
-};
 void __init imx50_soc_init(void)
 {
        /* i.mx50 has the i.mx35 type gpio */
@@ -196,30 +173,6 @@ void __init imx51_soc_init(void)
                                        ARRAY_SIZE(imx51_audmux_res));
 }
-void __init imx53_soc_init(void)
-{
-        /* i.mx53 has the i.mx35 type gpio */
-        mxc_register_gpio("imx35-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx35-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx35-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx35-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
-        mxc_register_gpio("imx35-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
-        mxc_register_gpio("imx35-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
-        mxc_register_gpio("imx35-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
-        pinctrl_provide_dummies();
-        /* i.mx53 has the i.mx35 type sdma */
-        imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
-        /* Setup AIPS registers */
-        imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
-        imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
-        /* i.mx53 has the i.mx31 type audmux */
-        platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
-                                        ARRAY_SIZE(imx53_audmux_res));
-}
 void __init imx51_init_late(void)
 {
        mx51_neon_fixup();
diff --git a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
index b09ee12a4ff0..fb38436ca67f 100644
--- a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
+++ b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
@@ -11,7 +11,7 @@
 #include <linux/platform_device.h>
 #include <linux/module.h>
-#include <mach/mx1_camera.h>
+#include <linux/platform_data/camera-mx1.h>
 /* IMX camera FIQ handler */
 EXPORT_SYMBOL(mx1_camera_sof_fiq_start);
diff --git a/arch/arm/mach-imx/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c
deleted file mode 100644
index ee870c49bc63..000000000000
--- a/arch/arm/mach-imx/mx51_efika.c
+++ /dev/null
@@ -1,633 +0,0 @@
-/*
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <mach/ulpi.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include "devices-imx51.h"
-#include "efika.h"
-#include "cpu_op-mx51.h"
-#define MX51_USB_CTRL_1_OFFSET          0x10
-#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
-#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
-#define EFIKAMX_USB_HUB_RESET   IMX_GPIO_NR(1, 5)
-#define EFIKAMX_USBH1_STP       IMX_GPIO_NR(1, 27)
-#define EFIKAMX_SPI_CS0         IMX_GPIO_NR(4, 24)
-#define EFIKAMX_SPI_CS1         IMX_GPIO_NR(4, 25)
-#define EFIKAMX_PMIC            IMX_GPIO_NR(1, 6)
-static iomux_v3_cfg_t mx51efika_pads[] = {
-        /* UART1 */
-        MX51_PAD_UART1_RXD__UART1_RXD,
-        MX51_PAD_UART1_TXD__UART1_TXD,
-        MX51_PAD_UART1_RTS__UART1_RTS,
-        MX51_PAD_UART1_CTS__UART1_CTS,
-        /* SD 1 */
-        MX51_PAD_SD1_CMD__SD1_CMD,
-        MX51_PAD_SD1_CLK__SD1_CLK,
-        MX51_PAD_SD1_DATA0__SD1_DATA0,
-        MX51_PAD_SD1_DATA1__SD1_DATA1,
-        MX51_PAD_SD1_DATA2__SD1_DATA2,
-        MX51_PAD_SD1_DATA3__SD1_DATA3,
-        /* SD 2 */
-        MX51_PAD_SD2_CMD__SD2_CMD,
-        MX51_PAD_SD2_CLK__SD2_CLK,
-        MX51_PAD_SD2_DATA0__SD2_DATA0,
-        MX51_PAD_SD2_DATA1__SD2_DATA1,
-        MX51_PAD_SD2_DATA2__SD2_DATA2,
-        MX51_PAD_SD2_DATA3__SD2_DATA3,
-        /* SD/MMC WP/CD */
-        MX51_PAD_GPIO1_0__SD1_CD,
-        MX51_PAD_GPIO1_1__SD1_WP,
-        MX51_PAD_GPIO1_7__SD2_WP,
-        MX51_PAD_GPIO1_8__SD2_CD,
-        /* spi */
-        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
-        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-        MX51_PAD_CSPI1_SS0__GPIO4_24,
-        MX51_PAD_CSPI1_SS1__GPIO4_25,
-        MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
-        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
-        MX51_PAD_GPIO1_6__GPIO1_6,
-        /* USB HOST1 */
-        MX51_PAD_USBH1_CLK__USBH1_CLK,
-        MX51_PAD_USBH1_DIR__USBH1_DIR,
-        MX51_PAD_USBH1_NXT__USBH1_NXT,
-        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
-        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
-        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
-        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
-        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
-        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
-        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
-        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-        /* USB HUB RESET */
-        MX51_PAD_GPIO1_5__GPIO1_5,
-        /* WLAN */
-        MX51_PAD_EIM_A22__GPIO2_16,
-        MX51_PAD_EIM_A16__GPIO2_10,
-        /* USB PHY RESET */
-        MX51_PAD_EIM_D27__GPIO2_9,
-};
-/* Serial ports */
-static const struct imxuart_platform_data uart_pdata = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-/* This function is board specific as the bit mask for the plldiv will also
- * be different for other Freescale SoCs, thus a common bitmask is not
- * possible and cannot get place in /plat-mxc/ehci.c.
- */
-static int initialize_otg_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
-        /* Set the PHY clock to 19.2MHz */
-        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-        v |= MX51_USB_PLL_DIV_19_2_MHZ;
-        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        iounmap(usb_base);
-        mdelay(10);
-        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
-}
-static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
-        .init   = initialize_otg_port,
-        .portsc = MXC_EHCI_UTMI_16BIT,
-};
-static int initialize_usbh1_port(struct platform_device *pdev)
-{
-        iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
-        iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *socregs_base;
-        mxc_iomux_v3_setup_pad(usbh1gpio);
-        gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
-        gpio_direction_output(EFIKAMX_USBH1_STP, 0);
-        msleep(1);
-        gpio_set_value(EFIKAMX_USBH1_STP, 1);
-        msleep(1);
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
-        /* The clock for the USBH1 ULPI port will come externally */
-        /* from the PHY. */
-        v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
-        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
-                        socregs_base + MX51_USB_CTRL_1_OFFSET);
-        iounmap(usb_base);
-        gpio_free(EFIKAMX_USBH1_STP);
-        mxc_iomux_v3_setup_pad(usbh1stp);
-        mdelay(10);
-        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
-}
-static struct mxc_usbh_platform_data usbh1_config __initdata = {
-        .init   = initialize_usbh1_port,
-        .portsc = MXC_EHCI_MODE_ULPI,
-};
-static void mx51_efika_hubreset(void)
-{
-        gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
-        gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
-        msleep(1);
-        gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
-        msleep(1);
-        gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
-}
-static void __init mx51_efika_usb(void)
-{
-        mx51_efika_hubreset();
-        /* pulling it low, means no USB at all... */
-        gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
-        gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
-        msleep(1);
-        gpio_set_value(EFIKA_USB_PHY_RESET, 1);
-        usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                        ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
-        imx51_add_mxc_ehci_otg(&dr_utmi_config);
-        if (usbh1_config.otg)
-                imx51_add_mxc_ehci_hs(1, &usbh1_config);
-}
-static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
-        {
-         .name = "u-boot",
-         .offset = 0,
-         .size = SZ_256K,
-        },
-        {
-          .name = "config",
-          .offset = MTDPART_OFS_APPEND,
-          .size = SZ_64K,
-        },
-};
-static struct flash_platform_data mx51_efika_spi_flash_data = {
-        .name           = "spi_flash",
-        .parts          = mx51_efika_spi_nor_partitions,
-        .nr_parts       = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
-        .type           = "sst25vf032b",
-};
-static struct regulator_consumer_supply sw1_consumers[] = {
-        {
-                .supply = "cpu_vcc",
-        }
-};
-static struct regulator_consumer_supply vdig_consumers[] = {
-        /* sgtl5000 */
-        REGULATOR_SUPPLY("VDDA", "1-000a"),
-        REGULATOR_SUPPLY("VDDD", "1-000a"),
-};
-static struct regulator_consumer_supply vvideo_consumers[] = {
-        /* sgtl5000 */
-        REGULATOR_SUPPLY("VDDIO", "1-000a"),
-};
-static struct regulator_consumer_supply vsd_consumers[] = {
-        REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
-        REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
-};
-static struct regulator_consumer_supply pwgt1_consumer[] = {
-        {
-                .supply = "pwgt1",
-        }
-};
-static struct regulator_consumer_supply pwgt2_consumer[] = {
-        {
-                .supply = "pwgt2",
-        }
-};
-static struct regulator_consumer_supply coincell_consumer[] = {
-        {
-                .supply = "coincell",
-        }
-};
-static struct regulator_init_data sw1_init = {
-        .constraints = {
-                .name = "SW1",
-                .min_uV = 600000,
-                .max_uV = 1375000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .valid_modes_mask = 0,
-                .always_on = 1,
-                .boot_on = 1,
-                .state_mem = {
-                        .uV = 850000,
-                        .mode = REGULATOR_MODE_NORMAL,
-                        .enabled = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
-        .consumer_supplies = sw1_consumers,
-};
-static struct regulator_init_data sw2_init = {
-        .constraints = {
-                .name = "SW2",
-                .min_uV = 900000,
-                .max_uV = 1850000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on = 1,
-                .boot_on = 1,
-                .state_mem = {
-                        .uV = 950000,
-                        .mode = REGULATOR_MODE_NORMAL,
-                        .enabled = 1,
-                },
-        }
-};
-static struct regulator_init_data sw3_init = {
-        .constraints = {
-                .name = "SW3",
-                .min_uV = 1100000,
-                .max_uV = 1850000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on = 1,
-                .boot_on = 1,
-        }
-};
-static struct regulator_init_data sw4_init = {
-        .constraints = {
-                .name = "SW4",
-                .min_uV = 1100000,
-                .max_uV = 1850000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on = 1,
-                .boot_on = 1,
-        }
-};
-static struct regulator_init_data viohi_init = {
-        .constraints = {
-                .name = "VIOHI",
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-static struct regulator_init_data vusb_init = {
-        .constraints = {
-                .name = "VUSB",
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-static struct regulator_init_data swbst_init = {
-        .constraints = {
-                .name = "SWBST",
-        }
-};
-static struct regulator_init_data vdig_init = {
-        .constraints = {
-                .name = "VDIG",
-                .min_uV = 1050000,
-                .max_uV = 1800000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
-        .consumer_supplies = vdig_consumers,
-};
-static struct regulator_init_data vpll_init = {
-        .constraints = {
-                .name = "VPLL",
-                .min_uV = 1050000,
-                .max_uV = 1800000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-static struct regulator_init_data vusb2_init = {
-        .constraints = {
-                .name = "VUSB2",
-                .min_uV = 2400000,
-                .max_uV = 2775000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-static struct regulator_init_data vvideo_init = {
-        .constraints = {
-                .name = "VVIDEO",
-                .min_uV = 2775000,
-                .max_uV = 2775000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .apply_uV = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
-        .consumer_supplies = vvideo_consumers,
-};
-static struct regulator_init_data vaudio_init = {
-        .constraints = {
-                .name = "VAUDIO",
-                .min_uV = 2300000,
-                .max_uV = 3000000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-        }
-};
-static struct regulator_init_data vsd_init = {
-        .constraints = {
-                .name = "VSD",
-                .min_uV = 1800000,
-                .max_uV = 3150000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE,
-                .boot_on = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
-        .consumer_supplies = vsd_consumers,
-};
-static struct regulator_init_data vcam_init = {
-        .constraints = {
-                .name = "VCAM",
-                .min_uV = 2500000,
-                .max_uV = 3000000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE |
-                        REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
-                .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-                .boot_on = 1,
-        }
-};
-static struct regulator_init_data vgen1_init = {
-        .constraints = {
-                .name = "VGEN1",
-                .min_uV = 1200000,
-                .max_uV = 3150000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-static struct regulator_init_data vgen2_init = {
-        .constraints = {
-                .name = "VGEN2",
-                .min_uV = 1200000,
-                .max_uV = 3150000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-static struct regulator_init_data vgen3_init = {
-        .constraints = {
-                .name = "VGEN3",
-                .min_uV = 1800000,
-                .max_uV = 2900000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-static struct regulator_init_data gpo1_init = {
-        .constraints = {
-                .name = "GPO1",
-        }
-};
-static struct regulator_init_data gpo2_init = {
-        .constraints = {
-                .name = "GPO2",
-        }
-};
-static struct regulator_init_data gpo3_init = {
-        .constraints = {
-                .name = "GPO3",
-        }
-};
-static struct regulator_init_data gpo4_init = {
-        .constraints = {
-                .name = "GPO4",
-        }
-};
-static struct regulator_init_data pwgt1_init = {
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
-        .consumer_supplies = pwgt1_consumer,
-};
-static struct regulator_init_data pwgt2_init = {
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
-        .consumer_supplies = pwgt2_consumer,
-};
-static struct regulator_init_data vcoincell_init = {
-        .constraints = {
-                .name = "COINCELL",
-                .min_uV = 3000000,
-                .max_uV = 3000000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
-        .consumer_supplies = coincell_consumer,
-};
-static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
-        { .id = MC13892_SW1,            .init_data =  &sw1_init },
-        { .id = MC13892_SW2,            .init_data =  &sw2_init },
-        { .id = MC13892_SW3,            .init_data =  &sw3_init },
-        { .id = MC13892_SW4,            .init_data =  &sw4_init },
-        { .id = MC13892_SWBST,          .init_data =  &swbst_init },
-        { .id = MC13892_VIOHI,          .init_data =  &viohi_init },
-        { .id = MC13892_VPLL,           .init_data =  &vpll_init },
-        { .id = MC13892_VDIG,           .init_data =  &vdig_init },
-        { .id = MC13892_VSD,            .init_data =  &vsd_init },
-        { .id = MC13892_VUSB2,          .init_data =  &vusb2_init },
-        { .id = MC13892_VVIDEO,         .init_data =  &vvideo_init },
-        { .id = MC13892_VAUDIO,         .init_data =  &vaudio_init },
-        { .id = MC13892_VCAM,           .init_data =  &vcam_init },
-        { .id = MC13892_VGEN1,          .init_data =  &vgen1_init },
-        { .id = MC13892_VGEN2,          .init_data =  &vgen2_init },
-        { .id = MC13892_VGEN3,          .init_data =  &vgen3_init },
-        { .id = MC13892_VUSB,           .init_data =  &vusb_init },
-        { .id = MC13892_GPO1,           .init_data =  &gpo1_init },
-        { .id = MC13892_GPO2,           .init_data =  &gpo2_init },
-        { .id = MC13892_GPO3,           .init_data =  &gpo3_init },
-        { .id = MC13892_GPO4,           .init_data =  &gpo4_init },
-        { .id = MC13892_PWGT1SPI,       .init_data = &pwgt1_init },
-        { .id = MC13892_PWGT2SPI,       .init_data = &pwgt2_init },
-        { .id = MC13892_VCOINCELL,      .init_data = &vcoincell_init },
-};
-static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
-        .flags = MC13XXX_USE_RTC,
-        .regulators = {
-                .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
-                .regulators = mx51_efika_regulators,
-        },
-};
-static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
-        {
-                .modalias = "m25p80",
-                .max_speed_hz = 25000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .platform_data = &mx51_efika_spi_flash_data,
-                .irq = -1,
-        },
-        {
-                .modalias = "mc13892",
-                .max_speed_hz = 1000000,
-                .bus_num = 0,
-                .chip_select = 0,
-                .platform_data = &mx51_efika_mc13892_data,
-                /* irq number is run-time assigned */
-        },
-};
-static int mx51_efika_spi_cs[] = {
-        EFIKAMX_SPI_CS0,
-        EFIKAMX_SPI_CS1,
-};
-static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
-        .chipselect     = mx51_efika_spi_cs,
-        .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
-};
-void __init efika_board_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
-                                        ARRAY_SIZE(mx51efika_pads));
-        imx51_add_imx_uart(0, &uart_pdata);
-        mx51_efika_usb();
-        /* FIXME: comes from original code. check this. */
-        if (mx51_revision() < IMX_CHIP_REVISION_2_0)
-                sw2_init.constraints.state_mem.uV = 1100000;
-        else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
-                sw2_init.constraints.state_mem.uV = 1250000;
-                sw1_init.constraints.state_mem.uV = 1000000;
-        }
-        if (machine_is_mx51_efikasb())
-                vgen1_init.constraints.max_uV = 1200000;
-        gpio_request(EFIKAMX_PMIC, "pmic irq");
-        gpio_direction_input(EFIKAMX_PMIC);
-        mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC);
-        spi_register_board_info(mx51_efika_spi_board_info,
-                ARRAY_SIZE(mx51_efika_spi_board_info));
-        imx51_add_ecspi(0, &mx51_efika_spi_pdata);
-        imx51_add_pata_imx();
-#if defined(CONFIG_CPU_FREQ_IMX)
-        get_cpu_op = mx51_get_cpu_op;
-#endif
-}
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index ab98c6fec9eb..2ac43e1a2dfd 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -41,7 +41,7 @@ void __init imx_scu_map_io(void)
        scu_base = IMX_IO_ADDRESS(base);
 }
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit imx_secondary_init(unsigned int cpu)
 {
        /*
         * if any interrupts are already enabled for the primary
@@ -51,7 +51,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
        gic_secondary_init(0);
 }
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        imx_set_cpu_jump(cpu, v7_secondary_startup);
        imx_enable_cpu(cpu, true);
@@ -62,7 +62,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 * Initialise the CPU possible map early - this describes the CPUs
 * which may be present or become present in the system.
 */
-void __init smp_init_cpus(void)
+static void __init imx_smp_init_cpus(void)
 {
        int i, ncores;
@@ -79,7 +79,17 @@ void imx_smp_prepare(void)
        scu_enable(scu_base);
 }
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
 {
        imx_smp_prepare();
 }
+struct smp_operations  imx_smp_ops __initdata = {
+        .smp_init_cpus          = imx_smp_init_cpus,
+        .smp_prepare_cpus       = imx_smp_prepare_cpus,
+        .smp_secondary_init     = imx_secondary_init,
+        .smp_boot_secondary     = imx_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = imx_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index ebeef966e1f5..5521d18bf19a 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -4,11 +4,10 @@
 # Object file lists.
-obj-y                                   := core.o lm.o
+obj-y                                   := core.o lm.o leds.o
 obj-$(CONFIG_ARCH_INTEGRATOR_AP)        += integrator_ap.o
 obj-$(CONFIG_ARCH_INTEGRATOR_CP)        += integrator_cp.o
-obj-$(CONFIG_LEDS)                      += leds.o
 obj-$(CONFIG_PCI)                       += pci_v3.o pci.o
 obj-$(CONFIG_CPU_FREQ_INTEGRATOR)       += cpu.o
 obj-$(CONFIG_INTEGRATOR_IMPD1)          += impd1.o
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index 899561d8db28..c3ff21b5ea24 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,3 +1,6 @@
+#include <linux/amba/serial.h>
+extern struct amba_pl010_data integrator_uart_data;
 void integrator_init_early(void);
+int integrator_init(bool is_cp);
 void integrator_reserve(void);
 void integrator_restart(char, const char *);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 3fa6c51390da..ea22a17246d7 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -28,12 +28,13 @@
 #include <mach/cm.h>
 #include <mach/irqs.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/time.h>
 #include <asm/pgtable.h>
-static struct amba_pl010_data integrator_uart_data;
+#include "common.h"
+#ifdef CONFIG_ATAGS
 #define INTEGRATOR_RTC_IRQ      { IRQ_RTCINT }
 #define INTEGRATOR_UART0_IRQ    { IRQ_UARTINT0 }
@@ -61,7 +62,7 @@ static struct amba_device *amba_devs[] __initdata = {
        &kmi1_device,
 };
-static int __init integrator_init(void)
+int __init integrator_init(bool is_cp)
 {
        int i;
@@ -70,7 +71,7 @@ static int __init integrator_init(void)
         * hard-code them. The Integator/CP and forward have proper cell IDs.
         * Else we leave them undefined to the bus driver can autoprobe them.
         */
-        if (machine_is_integrator()) {
+        if (!is_cp) {
                rtc_device.periphid     = 0x00041030;
                uart0_device.periphid   = 0x00041010;
                uart1_device.periphid   = 0x00041010;
@@ -86,7 +87,7 @@ static int __init integrator_init(void)
        return 0;
 }
-arch_initcall(integrator_init);
+#endif
 /*
 * On the Integrator platform, the port RTS and DTR are provided by
@@ -95,17 +96,20 @@ arch_initcall(integrator_init);
 *  UART0  7    6
 *  UART1  5    4
 */
-#define SC_CTRLC        IO_ADDRESS(INTEGRATOR_SC_CTRLC)
+#define SC_CTRLC        __io_address(INTEGRATOR_SC_CTRLC)
-#define SC_CTRLS        IO_ADDRESS(INTEGRATOR_SC_CTRLS)
+#define SC_CTRLS        __io_address(INTEGRATOR_SC_CTRLS)
 static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
 {
        unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
+        u32 phybase = dev->res.start;
-        if (dev == &uart0_device) {
+        if (phybase == INTEGRATOR_UART0_BASE) {
+                /* UART0 */
                rts_mask = 1 << 4;
                dtr_mask = 1 << 5;
        } else {
+                /* UART1 */
                rts_mask = 1 << 6;
                dtr_mask = 1 << 7;
        }
@@ -124,12 +128,10 @@ static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *bas
        __raw_writel(ctrlc, SC_CTRLC);
 }
-static struct amba_pl010_data integrator_uart_data = {
+struct amba_pl010_data integrator_uart_data = {
        .set_mctrl = integrator_uart_set_mctrl,
 };
-#define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_CTRL)
 static DEFINE_RAW_SPINLOCK(cm_lock);
 /**
diff --git a/arch/arm/mach-integrator/cpu.c b/arch/arm/mach-integrator/cpu.c
index fbb457779895..590c192cdf4d 100644
--- a/arch/arm/mach-integrator/cpu.c
+++ b/arch/arm/mach-integrator/cpu.c
@@ -25,10 +25,10 @@
 static struct cpufreq_driver integrator_driver;
-#define CM_ID   IO_ADDRESS(INTEGRATOR_HDR_ID)
+#define CM_ID   __io_address(INTEGRATOR_HDR_ID)
-#define CM_OSC  IO_ADDRESS(INTEGRATOR_HDR_OSC)
+#define CM_OSC  __io_address(INTEGRATOR_HDR_OSC)
-#define CM_STAT IO_ADDRESS(INTEGRATOR_HDR_STAT)
+#define CM_STAT __io_address(INTEGRATOR_HDR_STAT)
-#define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK)
+#define CM_LOCK __io_address(INTEGRATOR_HDR_LOCK)
 static const struct icst_params lclk_params = {
        .ref            = 24000000,
diff --git a/arch/arm/mach-integrator/include/mach/cm.h b/arch/arm/mach-integrator/include/mach/cm.h
index 445d57adb043..202e6a57f100 100644
--- a/arch/arm/mach-integrator/include/mach/cm.h
+++ b/arch/arm/mach-integrator/include/mach/cm.h
@@ -3,6 +3,8 @@
 */
 void cm_control(u32, u32);
+#define CM_CTRL __io_address(INTEGRATOR_HDR_CTRL)
 #define CM_CTRL_LED                     (1 << 0)
 #define CM_CTRL_nMBDET                  (1 << 1)
 #define CM_CTRL_REMAP                   (1 << 2)
diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h
deleted file mode 100644
index 8de70de3dd0a..000000000000
--- a/arch/arm/mach-integrator/include/mach/io.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/mach-integrator/include/mach/io.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-/*
- * WARNING: this has to mirror definitions in platform.h
- */
-#define PCI_MEMORY_VADDR        0xe8000000
-#define PCI_CONFIG_VADDR        0xec000000
-#define PCI_V3_VADDR            0xed000000
-#define PCI_IO_VADDR            0xee000000
-#define __io(a)                 ((void __iomem *)(PCI_IO_VADDR + (a)))
-#endif
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index ec467baade09..efeac5d0bc9e 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -324,6 +324,10 @@
 */
 #define PHYS_PCI_V3_BASE                0x62000000
+#define PCI_MEMORY_VADDR                IOMEM(0xe8000000)
+#define PCI_CONFIG_VADDR                IOMEM(0xec000000)
+#define PCI_V3_VADDR                    IOMEM(0xed000000)
 /* ------------------------------------------------------------------------
 *  Integrator Interrupt Controllers
 * ------------------------------------------------------------------------
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 3b2267529f5e..e6617c134faf 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -34,6 +34,9 @@
 #include <linux/mtd/physmap.h>
 #include <linux/clk.h>
 #include <linux/platform_data/clk-integrator.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
 #include <video/vga.h>
 #include <mach/hardware.h>
@@ -50,6 +53,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include <asm/mach/time.h>
 #include <plat/fpga-irq.h>
@@ -73,7 +77,7 @@
 * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
 * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
 * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
- * ee000000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
+ * fee00000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
 * ef000000                     Cache flush
 * f1000000     10000000        Core module registers
 * f1100000     11000000        System controller registers
@@ -133,49 +137,28 @@ static struct map_desc ap_io_desc[] __initdata = {
                .length         = SZ_4K,
                .type           = MT_DEVICE
        }, {
-                .virtual        = PCI_MEMORY_VADDR,
+                .virtual        = (unsigned long)PCI_MEMORY_VADDR,
                .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
        }, {
-                .virtual        = PCI_CONFIG_VADDR,
+                .virtual        = (unsigned long)PCI_CONFIG_VADDR,
                .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
        }, {
-                .virtual        = PCI_V3_VADDR,
+                .virtual        = (unsigned long)PCI_V3_VADDR,
                .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
                .length         = SZ_64K,
                .type           = MT_DEVICE
-        }, {
-                .virtual        = PCI_IO_VADDR,
-                .pfn            = __phys_to_pfn(PHYS_PCI_IO_BASE),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE
        }
 };
 static void __init ap_map_io(void)
 {
        iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
-        vga_base = PCI_MEMORY_VADDR;
+        vga_base = (unsigned long)PCI_MEMORY_VADDR;
-}
+        pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
-#define INTEGRATOR_SC_VALID_INT 0x003fffff
-static void __init ap_init_irq(void)
-{
-        /* Disable all interrupts initially. */
-        /* Do the core module ones */
-        writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
-        /* do the header card stuff next */
-        writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
-        writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
-        fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
-                -1, INTEGRATOR_SC_VALID_INT, NULL);
-        integrator_clk_init(false);
 }
 #ifdef CONFIG_PM
@@ -270,56 +253,12 @@ static struct physmap_flash_data ap_flash_data = {
        .set_vpp        = ap_flash_set_vpp,
 };
-static struct resource cfi_flash_resource = {
-        .start          = INTEGRATOR_FLASH_BASE,
-        .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device cfi_flash_device = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &ap_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &cfi_flash_resource,
-};
-static void __init ap_init(void)
-{
-        unsigned long sc_dec;
-        int i;
-        platform_device_register(&cfi_flash_device);
-        sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
-        for (i = 0; i < 4; i++) {
-                struct lm_device *lmdev;
-                if ((sc_dec & (16 << i)) == 0)
-                        continue;
-                lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
-                if (!lmdev)
-                        continue;
-                lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
-                lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
-                lmdev->resource.flags = IORESOURCE_MEM;
-                lmdev->irq = IRQ_AP_EXPINT0 + i;
-                lmdev->id = i;
-                lm_device_register(lmdev);
-        }
-}
 /*
 * Where is the timer (VA)?
 */
-#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
+#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
-#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
+#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
-#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
+#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
 static unsigned long timer_reload;
@@ -328,9 +267,9 @@ static u32 notrace integrator_read_sched_clock(void)
        return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
 }
-static void integrator_clocksource_init(unsigned long inrate)
+static void integrator_clocksource_init(unsigned long inrate,
+                                        void __iomem *base)
 {
-        void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
        u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
        unsigned long rate = inrate;
@@ -347,7 +286,7 @@ static void integrator_clocksource_init(unsigned long inrate)
        setup_sched_clock(integrator_read_sched_clock, 16, rate);
 }
-static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
+static void __iomem * clkevt_base;
 /*
 * IRQ handler for the timer
@@ -419,11 +358,13 @@ static struct irqaction integrator_timer_irq = {
        .dev_id         = &integrator_clockevent,
 };
-static void integrator_clockevent_init(unsigned long inrate)
+static void integrator_clockevent_init(unsigned long inrate,
+                                void __iomem *base, int irq)
 {
        unsigned long rate = inrate;
        unsigned int ctrl = 0;
+        clkevt_base = base;
        /* Calculate and program a divisor */
        if (rate > 0x100000 * HZ) {
                rate /= 256;
@@ -435,7 +376,7 @@ static void integrator_clockevent_init(unsigned long inrate)
        timer_reload = rate / HZ;
        writel(ctrl, clkevt_base + TIMER_CTRL);
-        setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
+        setup_irq(irq, &integrator_timer_irq);
        clockevents_config_and_register(&integrator_clockevent,
                                        rate,
                                        1,
@@ -446,9 +387,153 @@ void __init ap_init_early(void)
 {
 }
+#ifdef CONFIG_OF
+static void __init ap_init_timer_of(void)
+{
+        struct device_node *node;
+        const char *path;
+        void __iomem *base;
+        int err;
+        int irq;
+        struct clk *clk;
+        unsigned long rate;
+        clk = clk_get_sys("ap_timer", NULL);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
+        rate = clk_get_rate(clk);
+        err = of_property_read_string(of_aliases,
+                                "arm,timer-primary", &path);
+        if (WARN_ON(err))
+                return;
+        node = of_find_node_by_path(path);
+        base = of_iomap(node, 0);
+        if (WARN_ON(!base))
+                return;
+        writel(0, base + TIMER_CTRL);
+        integrator_clocksource_init(rate, base);
+        err = of_property_read_string(of_aliases,
+                                "arm,timer-secondary", &path);
+        if (WARN_ON(err))
+                return;
+        node = of_find_node_by_path(path);
+        base = of_iomap(node, 0);
+        if (WARN_ON(!base))
+                return;
+        irq = irq_of_parse_and_map(node, 0);
+        writel(0, base + TIMER_CTRL);
+        integrator_clockevent_init(rate, base, irq);
+}
+static struct sys_timer ap_of_timer = {
+        .init           = ap_init_timer_of,
+};
+static const struct of_device_id fpga_irq_of_match[] __initconst = {
+        { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
+        { /* Sentinel */ }
+};
+static void __init ap_init_irq_of(void)
+{
+        /* disable core module IRQs */
+        writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+        of_irq_init(fpga_irq_of_match);
+        integrator_clk_init(false);
+}
+/* For the Device Tree, add in the UART callbacks as AUXDATA */
+static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
+                "rtc", NULL),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
+                "uart0", &integrator_uart_data),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
+                "uart1", &integrator_uart_data),
+        OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
+                "kmi0", NULL),
+        OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
+                "kmi1", NULL),
+        OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
+                "physmap-flash", &ap_flash_data),
+        { /* sentinel */ },
+};
+static void __init ap_init_of(void)
+{
+        unsigned long sc_dec;
+        int i;
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        ap_auxdata_lookup, NULL);
+        sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+        for (i = 0; i < 4; i++) {
+                struct lm_device *lmdev;
+                if ((sc_dec & (16 << i)) == 0)
+                        continue;
+                lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
+                if (!lmdev)
+                        continue;
+                lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
+                lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
+                lmdev->resource.flags = IORESOURCE_MEM;
+                lmdev->irq = IRQ_AP_EXPINT0 + i;
+                lmdev->id = i;
+                lm_device_register(lmdev);
+        }
+}
+static const char * ap_dt_board_compat[] = {
+        "arm,integrator-ap",
+        NULL,
+};
+DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
+        .reserve        = integrator_reserve,
+        .map_io         = ap_map_io,
+        .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
+        .init_early     = ap_init_early,
+        .init_irq       = ap_init_irq_of,
+        .handle_irq     = fpga_handle_irq,
+        .timer          = &ap_of_timer,
+        .init_machine   = ap_init_of,
+        .restart        = integrator_restart,
+        .dt_compat      = ap_dt_board_compat,
+MACHINE_END
+#endif
+#ifdef CONFIG_ATAGS
 /*
- * Set up timer(s).
+ * This is where non-devicetree initialization code is collected and stashed
+ * for eventual deletion.
 */
+static struct resource cfi_flash_resource = {
+        .start          = INTEGRATOR_FLASH_BASE,
+        .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
+        .flags          = IORESOURCE_MEM,
+};
+static struct platform_device cfi_flash_device = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &ap_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &cfi_flash_resource,
+};
 static void __init ap_init_timer(void)
 {
        struct clk *clk;
@@ -463,14 +548,62 @@ static void __init ap_init_timer(void)
        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
        writel(0, TIMER2_VA_BASE + TIMER_CTRL);
-        integrator_clocksource_init(rate);
+        integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
-        integrator_clockevent_init(rate);
+        integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
+                                IRQ_TIMERINT1);
 }
 static struct sys_timer ap_timer = {
        .init           = ap_init_timer,
 };
+#define INTEGRATOR_SC_VALID_INT 0x003fffff
+static void __init ap_init_irq(void)
+{
+        /* Disable all interrupts initially. */
+        /* Do the core module ones */
+        writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+        /* do the header card stuff next */
+        writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
+        writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
+        fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
+                -1, INTEGRATOR_SC_VALID_INT, NULL);
+        integrator_clk_init(false);
+}
+static void __init ap_init(void)
+{
+        unsigned long sc_dec;
+        int i;
+        platform_device_register(&cfi_flash_device);
+        sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+        for (i = 0; i < 4; i++) {
+                struct lm_device *lmdev;
+                if ((sc_dec & (16 << i)) == 0)
+                        continue;
+                lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
+                if (!lmdev)
+                        continue;
+                lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
+                lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
+                lmdev->resource.flags = IORESOURCE_MEM;
+                lmdev->irq = IRQ_AP_EXPINT0 + i;
+                lmdev->id = i;
+                lm_device_register(lmdev);
+        }
+        integrator_init(false);
+}
 MACHINE_START(INTEGRATOR, "ARM-Integrator")
        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
        .atag_offset    = 0x100,
@@ -484,3 +617,5 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
        .init_machine   = ap_init,
        .restart        = integrator_restart,
 MACHINE_END
+#endif
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 82d5c837cc74..5b08e8e4cc83 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -23,6 +23,9 @@
 #include <linux/gfp.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_data/clk-integrator.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -49,17 +52,10 @@
 #include "common.h"
 #define INTCP_PA_FLASH_BASE             0x24000000
-#define INTCP_FLASH_SIZE                SZ_32M
 #define INTCP_PA_CLCD_BASE              0xc0000000
-#define INTCP_VA_CIC_BASE               __io_address(INTEGRATOR_HDR_BASE + 0x40)
+#define INTCP_VA_CTRL_BASE              __io_address(INTEGRATOR_CP_CTL_BASE)
-#define INTCP_VA_PIC_BASE               __io_address(INTEGRATOR_IC_BASE)
-#define INTCP_VA_SIC_BASE               __io_address(INTEGRATOR_CP_SIC_BASE)
-#define INTCP_ETH_SIZE                  0x10
-#define INTCP_VA_CTRL_BASE              IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
 #define INTCP_FLASHPROG                 0x04
 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
@@ -143,37 +139,6 @@ static void __init intcp_map_io(void)
        iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 }
-static void __init intcp_init_irq(void)
-{
-        u32 pic_mask, cic_mask, sic_mask;
-        /* These masks are for the HW IRQ registers */
-        pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
-        pic_mask |= (~((~0u) << (29 - 22))) << 22;
-        cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
-        sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
-        /*
-         * Disable all interrupt sources
-         */
-        writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
-        writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
-        writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
-        writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
-        writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
-        writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
-        fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
-                      -1, pic_mask, NULL);
-        fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
-                      -1, cic_mask, NULL);
-        fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
-                      IRQ_CP_CPPLDINT, sic_mask, NULL);
-        integrator_clk_init(true);
-}
 /*
 * Flash handling.
 */
@@ -216,47 +181,6 @@ static struct physmap_flash_data intcp_flash_data = {
        .set_vpp        = intcp_flash_set_vpp,
 };
-static struct resource intcp_flash_resource = {
-        .start          = INTCP_PA_FLASH_BASE,
-        .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device intcp_flash_device = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &intcp_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &intcp_flash_resource,
-};
-static struct resource smc91x_resources[] = {
-        [0] = {
-                .start  = INTEGRATOR_CP_ETH_BASE,
-                .end    = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_CP_ETHINT,
-                .end    = IRQ_CP_ETHINT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device smc91x_device = {
-        .name           = "smc91x",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(smc91x_resources),
-        .resource       = smc91x_resources,
-};
-static struct platform_device *intcp_devs[] __initdata = {
-        &intcp_flash_device,
-        &smc91x_device,
-};
 /*
 * It seems that the card insertion interrupt remains active after
 * we've acknowledged it.  We therefore ignore the interrupt, and
@@ -265,8 +189,8 @@ static struct platform_device *intcp_devs[] __initdata = {
 */
 static unsigned int mmc_status(struct device *dev)
 {
-        unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
+        unsigned int status = readl(__io_address(0xca000000 + 4));
-        writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
+        writel(8, __io_address(INTEGRATOR_CP_CTL_BASE + 8));
        return status & 8;
 }
@@ -278,16 +202,6 @@ static struct mmci_platform_data mmc_data = {
        .gpio_cd        = -1,
 };
-#define INTEGRATOR_CP_MMC_IRQS  { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
-#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
-static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
-        INTEGRATOR_CP_MMC_IRQS, &mmc_data);
-static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
-        INTEGRATOR_CP_AACI_IRQS, NULL);
 /*
 * CLCD support
 */
@@ -338,15 +252,6 @@ static struct clcd_board clcd_data = {
        .remove         = versatile_clcd_remove_dma,
 };
-static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
-        { IRQ_CP_CLCDCINT }, &clcd_data);
-static struct amba_device *amba_devs[] __initdata = {
-        &mmc_device,
-        &aaci_device,
-        &clcd_device,
-};
 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
 static void __init intcp_init_early(void)
@@ -356,16 +261,193 @@ static void __init intcp_init_early(void)
 #endif
 }
-static void __init intcp_init(void)
+#ifdef CONFIG_OF
+static void __init intcp_timer_init_of(void)
 {
-        int i;
+        struct device_node *node;
+        const char *path;
+        void __iomem *base;
+        int err;
+        int irq;
+        err = of_property_read_string(of_aliases,
+                                "arm,timer-primary", &path);
+        if (WARN_ON(err))
+                return;
+        node = of_find_node_by_path(path);
+        base = of_iomap(node, 0);
+        if (WARN_ON(!base))
+                return;
+        writel(0, base + TIMER_CTRL);
+        sp804_clocksource_init(base, node->name);
+        err = of_property_read_string(of_aliases,
+                                "arm,timer-secondary", &path);
+        if (WARN_ON(err))
+                return;
+        node = of_find_node_by_path(path);
+        base = of_iomap(node, 0);
+        if (WARN_ON(!base))
+                return;
+        irq = irq_of_parse_and_map(node, 0);
+        writel(0, base + TIMER_CTRL);
+        sp804_clockevents_init(base, irq, node->name);
+}
-        platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
+static struct sys_timer cp_of_timer = {
+        .init           = intcp_timer_init_of,
+};
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+static const struct of_device_id fpga_irq_of_match[] __initconst = {
-                struct amba_device *d = amba_devs[i];
+        { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
-                amba_device_register(d, &iomem_resource);
+        { /* Sentinel */ }
-        }
+};
+static void __init intcp_init_irq_of(void)
+{
+        of_irq_init(fpga_irq_of_match);
+        integrator_clk_init(true);
+}
+/*
+ * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
+ * and enforce the bus names since these are used for clock lookups.
+ */
+static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
+                "rtc", NULL),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
+                "uart0", &integrator_uart_data),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
+                "uart1", &integrator_uart_data),
+        OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
+                "kmi0", NULL),
+        OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
+                "kmi1", NULL),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
+                "mmci", &mmc_data),
+        OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
+                "aaci", &mmc_data),
+        OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
+                "clcd", &clcd_data),
+        OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
+                "physmap-flash", &intcp_flash_data),
+        { /* sentinel */ },
+};
+static void __init intcp_init_of(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        intcp_auxdata_lookup, NULL);
+}
+static const char * intcp_dt_board_compat[] = {
+        "arm,integrator-cp",
+        NULL,
+};
+DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
+        .reserve        = integrator_reserve,
+        .map_io         = intcp_map_io,
+        .nr_irqs        = NR_IRQS_INTEGRATOR_CP,
+        .init_early     = intcp_init_early,
+        .init_irq       = intcp_init_irq_of,
+        .handle_irq     = fpga_handle_irq,
+        .timer          = &cp_of_timer,
+        .init_machine   = intcp_init_of,
+        .restart        = integrator_restart,
+        .dt_compat      = intcp_dt_board_compat,
+MACHINE_END
+#endif
+#ifdef CONFIG_ATAGS
+/*
+ * This is where non-devicetree initialization code is collected and stashed
+ * for eventual deletion.
+ */
+#define INTCP_FLASH_SIZE                SZ_32M
+static struct resource intcp_flash_resource = {
+        .start          = INTCP_PA_FLASH_BASE,
+        .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
+        .flags          = IORESOURCE_MEM,
+};
+static struct platform_device intcp_flash_device = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &intcp_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &intcp_flash_resource,
+};
+#define INTCP_ETH_SIZE                  0x10
+static struct resource smc91x_resources[] = {
+        [0] = {
+                .start  = INTEGRATOR_CP_ETH_BASE,
+                .end    = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_CP_ETHINT,
+                .end    = IRQ_CP_ETHINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device smc91x_device = {
+        .name           = "smc91x",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(smc91x_resources),
+        .resource       = smc91x_resources,
+};
+static struct platform_device *intcp_devs[] __initdata = {
+        &intcp_flash_device,
+        &smc91x_device,
+};
+#define INTCP_VA_CIC_BASE               __io_address(INTEGRATOR_HDR_BASE + 0x40)
+#define INTCP_VA_PIC_BASE               __io_address(INTEGRATOR_IC_BASE)
+#define INTCP_VA_SIC_BASE               __io_address(INTEGRATOR_CP_SIC_BASE)
+static void __init intcp_init_irq(void)
+{
+        u32 pic_mask, cic_mask, sic_mask;
+        /* These masks are for the HW IRQ registers */
+        pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
+        pic_mask |= (~((~0u) << (29 - 22))) << 22;
+        cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
+        sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
+        /*
+         * Disable all interrupt sources
+         */
+        writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
+        writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
+        writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
+        writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
+        writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
+        writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
+        fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
+                      -1, pic_mask, NULL);
+        fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
+                      -1, cic_mask, NULL);
+        fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
+                      IRQ_CP_CPPLDINT, sic_mask, NULL);
+        integrator_clk_init(true);
 }
 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
@@ -386,6 +468,37 @@ static struct sys_timer cp_timer = {
        .init           = intcp_timer_init,
 };
+#define INTEGRATOR_CP_MMC_IRQS  { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
+#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
+static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
+        INTEGRATOR_CP_MMC_IRQS, &mmc_data);
+static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
+        INTEGRATOR_CP_AACI_IRQS, NULL);
+static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
+        { IRQ_CP_CLCDCINT }, &clcd_data);
+static struct amba_device *amba_devs[] __initdata = {
+        &mmc_device,
+        &aaci_device,
+        &clcd_device,
+};
+static void __init intcp_init(void)
+{
+        int i;
+        platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                struct amba_device *d = amba_devs[i];
+                amba_device_register(d, &iomem_resource);
+        }
+        integrator_init(true);
+}
 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
        .atag_offset    = 0x100,
@@ -399,3 +512,5 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
        .init_machine   = intcp_init,
        .restart        = integrator_restart,
 MACHINE_END
+#endif
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index 466defa97842..7a7f6d3273bf 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -1,90 +1,125 @@
 /*
- *  linux/arch/arm/mach-integrator/leds.c
+ * Driver for the 4 user LEDs found on the Integrator AP/CP baseboard
+ * Based on Versatile and RealView machine LED code
 *
- *  Integrator/AP and Integrator/CP LED control routines
+ * License terms: GNU General Public License (GPL) version 2
- *
+ * Author: Bryan Wu <bryan.wu@canonical.com>
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/spinlock.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
+#include <mach/cm.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-#include <mach/cm.h>
-static int saved_leds;
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+#define ALPHA_REG __io_address(INTEGRATOR_DBG_BASE)
+#define LEDREG  (__io_address(INTEGRATOR_DBG_BASE) + INTEGRATOR_DBG_LEDS_OFFSET)
-static void integrator_leds_event(led_event_t ledevt)
+struct integrator_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} integrator_leds[] = {
+        { "integrator:green0", "heartbeat", },
+        { "integrator:yellow", },
+        { "integrator:red", },
+        { "integrator:green1", },
+        { "integrator:core_module", "cpu0", },
+};
+static void integrator_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
 {
-        unsigned long flags;
+        struct integrator_led *led = container_of(cdev,
-        const unsigned int dbg_base = IO_ADDRESS(INTEGRATOR_DBG_BASE);
+                                                 struct integrator_led, cdev);
-        unsigned int update_alpha_leds;
+        u32 reg = __raw_readl(LEDREG);
-        // yup, change the LEDs
+        if (b != LED_OFF)
-        local_irq_save(flags);
+                reg |= led->mask;
-        update_alpha_leds = 0;
+        else
+                reg &= ~led->mask;
-        switch(ledevt) {
+        while (__raw_readl(ALPHA_REG) & 1)
-        case led_idle_start:
+                cpu_relax();
-                cm_control(CM_CTRL_LED, 0);
-                break;
-        case led_idle_end:
+        __raw_writel(reg, LEDREG);
-                cm_control(CM_CTRL_LED, CM_CTRL_LED);
+}
-                break;
-        case led_timer:
+static enum led_brightness integrator_led_get(struct led_classdev *cdev)
-                saved_leds ^= GREEN_LED;
+{
-                update_alpha_leds = 1;
+        struct integrator_led *led = container_of(cdev,
-                break;
+                                                 struct integrator_led, cdev);
+        u32 reg = __raw_readl(LEDREG);
-        case led_red_on:
+        return (reg & led->mask) ? LED_FULL : LED_OFF;
-                saved_leds |= RED_LED;
+}
-                update_alpha_leds = 1;
-                break;
-        case led_red_off:
+static void cm_led_set(struct led_classdev *cdev,
-                saved_leds &= ~RED_LED;
+                              enum led_brightness b)
-                update_alpha_leds = 1;
+{
-                break;
+        if (b != LED_OFF)
+                cm_control(CM_CTRL_LED, CM_CTRL_LED);
+        else
+                cm_control(CM_CTRL_LED, 0);
+}
-        default:
+static enum led_brightness cm_led_get(struct led_classdev *cdev)
-                break;
+{
-        }
+        u32 reg = readl(CM_CTRL);
-        if (update_alpha_leds) {
+        return (reg & CM_CTRL_LED) ? LED_FULL : LED_OFF;
-                while (__raw_readl(dbg_base + INTEGRATOR_DBG_ALPHA_OFFSET) & 1);
-                __raw_writel(saved_leds, dbg_base + INTEGRATOR_DBG_LEDS_OFFSET);
-        }
-        local_irq_restore(flags);
 }
-static int __init leds_init(void)
+static int __init integrator_leds_init(void)
 {
-        if (machine_is_integrator() || machine_is_cintegrator())
+        int i;
-                leds_event = integrator_leds_event;
+        for (i = 0; i < ARRAY_SIZE(integrator_leds); i++) {
+                struct integrator_led *led;
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+                led->cdev.name = integrator_leds[i].name;
+                if (i == 4) { /* Setting for LED in core module */
+                        led->cdev.brightness_set = cm_led_set;
+                        led->cdev.brightness_get = cm_led_get;
+                } else {
+                        led->cdev.brightness_set = integrator_led_set;
+                        led->cdev.brightness_get = integrator_led_get;
+                }
+                led->cdev.default_trigger = integrator_leds[i].trigger;
+                led->mask = BIT(i);
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
        return 0;
 }
-core_initcall(leds_init);
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(integrator_leds_init);
+#endif
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index b866880e82ac..bbeca59df66b 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -41,61 +41,61 @@
 /*
 * The V3 PCI interface chip in Integrator provides several windows from
 * local bus memory into the PCI memory areas.   Unfortunately, there
- * are not really enough windows for our usage, therefore we reuse 
+ * are not really enough windows for our usage, therefore we reuse
 * one of the windows for access to PCI configuration space.  The
 * memory map is as follows:
- * 
+ *
 * Local Bus Memory         Usage
- * 
+ *
 * 40000000 - 4FFFFFFF      PCI memory.  256M non-prefetchable
 * 50000000 - 5FFFFFFF      PCI memory.  256M prefetchable
 * 60000000 - 60FFFFFF      PCI IO.  16M
 * 61000000 - 61FFFFFF      PCI Configuration. 16M
- * 
+ *
 * There are three V3 windows, each described by a pair of V3 registers.
 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
 * Base0 and Base1 can be used for any type of PCI memory access.   Base2
 * can be used either for PCI I/O or for I20 accesses.  By default, uHAL
 * uses this only for PCI IO space.
- * 
+ *
 * Normally these spaces are mapped using the following base registers:
- * 
+ *
 * Usage Local Bus Memory         Base/Map registers used
- * 
+ *
 * Mem   40000000 - 4FFFFFFF      LB_BASE0/LB_MAP0
 * Mem   50000000 - 5FFFFFFF      LB_BASE1/LB_MAP1
 * IO    60000000 - 60FFFFFF      LB_BASE2/LB_MAP2
 * Cfg   61000000 - 61FFFFFF
- * 
+ *
 * This means that I20 and PCI configuration space accesses will fail.
- * When PCI configuration accesses are needed (via the uHAL PCI 
+ * When PCI configuration accesses are needed (via the uHAL PCI
 * configuration space primitives) we must remap the spaces as follows:
- * 
+ *
 * Usage Local Bus Memory         Base/Map registers used
- * 
+ *
 * Mem   40000000 - 4FFFFFFF      LB_BASE0/LB_MAP0
 * Mem   50000000 - 5FFFFFFF      LB_BASE0/LB_MAP0
 * IO    60000000 - 60FFFFFF      LB_BASE2/LB_MAP2
 * Cfg   61000000 - 61FFFFFF      LB_BASE1/LB_MAP1
- * 
+ *
 * To make this work, the code depends on overlapping windows working.
- * The V3 chip translates an address by checking its range within 
+ * The V3 chip translates an address by checking its range within
 * each of the BASE/MAP pairs in turn (in ascending register number
 * order).  It will use the first matching pair.   So, for example,
 * if the same address is mapped by both LB_BASE0/LB_MAP0 and
- * LB_BASE1/LB_MAP1, the V3 will use the translation from 
+ * LB_BASE1/LB_MAP1, the V3 will use the translation from
 * LB_BASE0/LB_MAP0.
- * 
+ *
 * To allow PCI Configuration space access, the code enlarges the
 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M.  This occludes
 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
 * be remapped for use by configuration cycles.
- * 
+ *
- * At the end of the PCI Configuration space accesses, 
+ * At the end of the PCI Configuration space accesses,
 * LB_BASE1/LB_MAP1 is reset to map PCI Memory.  Finally the window
 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
 * reveal the now restored LB_BASE1/LB_MAP1 window.
- * 
+ *
 * NOTE: We do not set up I2O mapping.  I suspect that this is only
 * for an intelligent (target) device.  Using I2O disables most of
 * the mappings into PCI memory.
@@ -127,8 +127,8 @@
 *
 * returns:     configuration address to play on the PCI bus
 *
- * To generate the appropriate PCI configuration cycles in the PCI 
+ * To generate the appropriate PCI configuration cycles in the PCI
- * configuration address space, you present the V3 with the following pattern 
+ * configuration address space, you present the V3 with the following pattern
 * (which is very nearly a type 1 (except that the lower two bits are 00 and
 * not 01).   In order for this mapping to work you need to set up one of
 * the local to PCI aperatures to 16Mbytes in length translating to
@@ -138,7 +138,7 @@
 *
 * Type 0:
 *
- *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
+ *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
 *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
@@ -150,7 +150,7 @@
 *
 * Type 1:
 *
- *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
+ *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
 *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
@@ -161,7 +161,7 @@
 *      15:11   Device number (5 bits)
 *      10:8    function number
 *       7:2    register number
- *  
+ *
 */
 static DEFINE_RAW_SPINLOCK(v3_lock);
@@ -181,7 +181,7 @@ static DEFINE_RAW_SPINLOCK(v3_lock);
 #undef V3_LB_BASE_PREFETCH
 #define V3_LB_BASE_PREFETCH 0
-static unsigned long v3_open_config_window(struct pci_bus *bus,
+static void __iomem *v3_open_config_window(struct pci_bus *bus,
                                           unsigned int devfn, int offset)
 {
        unsigned int address, mapaddress, busnr;
@@ -280,7 +280,7 @@ static void v3_close_config_window(void)
 static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
                          int size, u32 *val)
 {
-        unsigned long addr;
+        void __iomem *addr;
        unsigned long flags;
        u32 v;
@@ -311,7 +311,7 @@ static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
 static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
                           int size, u32 val)
 {
-        unsigned long addr;
+        void __iomem *addr;
        unsigned long flags;
        raw_spin_lock_irqsave(&v3_lock, flags);
@@ -374,12 +374,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
        }
        /*
-         * the IO resource for this bus
         * the mem resource for this bus
         * the prefetch mem resource for this bus
         */
-        pci_add_resource_offset(&sys->resources,
-                                &ioport_resource, sys->io_offset);
        pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
        pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
@@ -391,9 +388,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
 * means I can't get additional information on the reason for the pm2fb
 * problems.  I suppose I'll just have to mind-meld with the machine. ;)
 */
-#define SC_PCI     IO_ADDRESS(INTEGRATOR_SC_PCIENABLE)
+#define SC_PCI     __io_address(INTEGRATOR_SC_PCIENABLE)
-#define SC_LBFADDR IO_ADDRESS(INTEGRATOR_SC_BASE + 0x20)
+#define SC_LBFADDR __io_address(INTEGRATOR_SC_BASE + 0x20)
-#define SC_LBFCODE IO_ADDRESS(INTEGRATOR_SC_BASE + 0x24)
+#define SC_LBFCODE __io_address(INTEGRATOR_SC_BASE + 0x24)
 static int
 v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
@@ -498,7 +495,6 @@ void __init pci_v3_preinit(void)
        unsigned int temp;
        int ret;
-        pcibios_min_io = 0x6000;
        pcibios_min_mem = 0x00100000;
        /*
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
deleted file mode 100644
index f13188518025..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * iop13xx custom ioremap implementation
- * Copyright (c) 2005-2006, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-#define IO_SPACE_LIMIT 0xffffffff
-#define __io(a) __iop13xx_io(a)
-extern void __iomem * __iop13xx_io(unsigned long io_addr);
-#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index e190dcd7d72d..7480f58267aa 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -69,21 +69,11 @@ extern unsigned long get_iop_tick_rate(void);
 * 0x8000.0000 + 928M   0x2.8000.0000   (ioremap)       PCIE outbound memory window
 *
 * IO MAP
- * 0x1000 + 64K 0x0.fffb.1000   0xfec6.1000     PCIX outbound i/o window
+ * 0x00000 + 64K        0x0.fffb.0000   0xfee0.0000     PCIX outbound i/o window
- * 0x1000 + 64K 0x0.fffd.1000   0xfed7.1000     PCIE outbound i/o window
+ * 0x10000 + 64K        0x0.fffd.0000   0xfee1.0000     PCIE outbound i/o window
 */
-#define IOP13XX_PCIX_IO_WINDOW_SIZE   0x10000UL
 #define IOP13XX_PCIX_LOWER_IO_PA      0xfffb0000UL
-#define IOP13XX_PCIX_LOWER_IO_VA      0xfec60000UL
 #define IOP13XX_PCIX_LOWER_IO_BA      0x0UL /* OIOTVR */
-#define IOP13XX_PCIX_IO_BUS_OFFSET    0x1000UL
-#define IOP13XX_PCIX_UPPER_IO_PA      (IOP13XX_PCIX_LOWER_IO_PA +\
-                                       IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIX_UPPER_IO_VA      (IOP13XX_PCIX_LOWER_IO_VA +\
-                                       IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
-                                           (IOP13XX_PCIX_LOWER_IO_PA\
-                                           - IOP13XX_PCIX_LOWER_IO_VA))
 #define IOP13XX_PCIX_MEM_PHYS_OFFSET  0x100000000ULL
 #define IOP13XX_PCIX_MEM_WINDOW_SIZE  0x3a000000UL
@@ -103,20 +93,8 @@ extern unsigned long get_iop_tick_rate(void);
                                        IOP13XX_PCIX_LOWER_MEM_BA)
 /* PCI-E ranges */
-#define IOP13XX_PCIE_IO_WINDOW_SIZE      0x10000UL
 #define IOP13XX_PCIE_LOWER_IO_PA         0xfffd0000UL
-#define IOP13XX_PCIE_LOWER_IO_VA         0xfed70000UL
+#define IOP13XX_PCIE_LOWER_IO_BA         0x10000UL  /* OIOTVR */
-#define IOP13XX_PCIE_LOWER_IO_BA         0x0UL  /* OIOTVR */
-#define IOP13XX_PCIE_IO_BUS_OFFSET       0x1000UL
-#define IOP13XX_PCIE_UPPER_IO_PA         (IOP13XX_PCIE_LOWER_IO_PA +\
-                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIE_UPPER_IO_VA         (IOP13XX_PCIE_LOWER_IO_VA +\
-                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIE_UPPER_IO_BA         (IOP13XX_PCIE_LOWER_IO_BA +\
-                                         IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
-                                           (IOP13XX_PCIE_LOWER_IO_PA\
-                                           - IOP13XX_PCIE_LOWER_IO_VA))
 #define IOP13XX_PCIE_MEM_PHYS_OFFSET     0x200000000ULL
 #define IOP13XX_PCIE_MEM_WINDOW_SIZE     0x3a000000UL
@@ -148,18 +126,16 @@ extern unsigned long get_iop_tick_rate(void);
 * IOP13XX chipset registers
 */
 #define IOP13XX_PMMR_PHYS_MEM_BASE         0xffd80000UL  /* PMMR phys. address */
-#define IOP13XX_PMMR_VIRT_MEM_BASE         0xfee80000UL  /* PMMR phys. address */
+#define IOP13XX_PMMR_VIRT_MEM_BASE         (void __iomem *)(0xfee80000UL)  /* PMMR phys. address */
 #define IOP13XX_PMMR_MEM_WINDOW_SIZE       0x80000
 #define IOP13XX_PMMR_UPPER_MEM_VA          (IOP13XX_PMMR_VIRT_MEM_BASE +\
                                           IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
 #define IOP13XX_PMMR_UPPER_MEM_PA          (IOP13XX_PMMR_PHYS_MEM_BASE +\
                                           IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
-#define IOP13XX_PMMR_VIRT_TO_PHYS(addr)   (u32) ((u32) addr +\
+#define IOP13XX_PMMR_VIRT_TO_PHYS(addr)   (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\
-                                           (IOP13XX_PMMR_PHYS_MEM_BASE\
+                                           + IOP13XX_PMMR_PHYS_MEM_BASE)
-                                           - IOP13XX_PMMR_VIRT_MEM_BASE))
+#define IOP13XX_PMMR_PHYS_TO_VIRT(addr)   (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\
-#define IOP13XX_PMMR_PHYS_TO_VIRT(addr)   (u32) ((u32) addr -\
+                                           + IOP13XX_PMMR_VIRT_MEM_BASE)
-                                           (IOP13XX_PMMR_PHYS_MEM_BASE\
-                                           - IOP13XX_PMMR_VIRT_MEM_BASE))
 #define IOP13XX_REG_ADDR32(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 #define IOP13XX_REG_ADDR16(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 #define IOP13XX_REG_ADDR8(reg)             (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
@@ -169,10 +145,10 @@ extern unsigned long get_iop_tick_rate(void);
 #define IOP13XX_PMMR_SIZE                  0x00080000
 /*=================== Defines for Platform Devices =====================*/
-#define IOP13XX_UART0_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
+#define IOP13XX_UART0_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300)
-#define IOP13XX_UART1_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
+#define IOP13XX_UART1_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340)
-#define IOP13XX_UART0_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
+#define IOP13XX_UART0_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300)
-#define IOP13XX_UART1_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
+#define IOP13XX_UART1_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340)
 #define IOP13XX_I2C0_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
 #define IOP13XX_I2C1_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
index 1afa99ef97fa..7c032d0ab24a 100644
--- a/arch/arm/mach-iop13xx/include/mach/memory.h
+++ b/arch/arm/mach-iop13xx/include/mach/memory.h
@@ -16,12 +16,12 @@
 #define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
 #define IOP13XX_PMMR_P_END   (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
-static inline dma_addr_t __virt_to_lbus(unsigned long x)
+static inline dma_addr_t __virt_to_lbus(void __iomem *x)
 {
        return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE;
 }
-static inline unsigned long __lbus_to_virt(dma_addr_t x)
+static inline void __iomem *__lbus_to_virt(dma_addr_t x)
 {
        return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE;
 }
@@ -38,23 +38,23 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
 #define __arch_dma_to_virt(dev, addr)                                   \
        ({                                                              \
-                unsigned long __virt;                                   \
+                void * __virt;                                          \
                dma_addr_t __dma = addr;                                \
                if (is_lbus_device(dev) && __is_lbus_dma(__dma))        \
                        __virt = __lbus_to_virt(__dma);                 \
                else                                                    \
-                        __virt = __phys_to_virt(__dma);                 \
+                        __virt = (void *)__phys_to_virt(__dma);         \
-                (void *)__virt;                                         \
+                __virt;                                                 \
        })
 #define __arch_virt_to_dma(dev, addr)                                   \
        ({                                                              \
-                unsigned long __virt = (unsigned long)addr;             \
+                void * __virt = addr;                                   \
                dma_addr_t __dma;                                       \
                if (is_lbus_device(dev) && __is_lbus_virt(__virt))      \
                        __dma = __virt_to_lbus(__virt);                 \
                else                                                    \
-                        __dma = __virt_to_phys(__virt);                 \
+                        __dma = __virt_to_phys((unsigned long)__virt);  \
                __dma;                                                  \
        })
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 3c364198db9c..183dc8b5511b 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -23,25 +23,6 @@
 #include "pci.h"
-void * __iomem __iop13xx_io(unsigned long io_addr)
-{
-        void __iomem * io_virt;
-        switch (io_addr) {
-        case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
-                io_virt = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(io_addr);
-                break;
-        case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
-                io_virt = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(io_addr);
-                break;
-        default:
-                BUG();
-        }
-        return io_virt;
-}
-EXPORT_SYMBOL(__iop13xx_io);
 static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
        size_t size, unsigned int mtype, void *caller)
 {
@@ -52,14 +33,14 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
                if (unlikely(!iop13xx_atux_mem_base))
                        retval = NULL;
                else
-                        retval = (void *)(iop13xx_atux_mem_base +
+                        retval = (iop13xx_atux_mem_base +
                                 (cookie - IOP13XX_PCIX_LOWER_MEM_RA));
                break;
        case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
                if (unlikely(!iop13xx_atue_mem_base))
                        retval = NULL;
                else
-                        retval = (void *)(iop13xx_atue_mem_base +
+                        retval = (iop13xx_atue_mem_base +
                                 (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
                break;
        case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
@@ -67,14 +48,8 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
                                       (cookie - IOP13XX_PBI_LOWER_MEM_RA),
                                       size, mtype, __builtin_return_address(0));
                break;
-        case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
-                retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
-                break;
-        case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
-                retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
-                break;
        case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
-                retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
+                retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
                break;
        default:
                retval = __arm_ioremap_caller(cookie, size, mtype,
@@ -99,9 +74,7 @@ static void __iop13xx_iounmap(volatile void __iomem *addr)
                    goto skip;
        switch ((u32) addr) {
-        case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA:
+        case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA:
-        case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
-        case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
                goto skip;
        }
        __iounmap(addr);
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index 060cddde2fd4..e94744111634 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -30,7 +30,7 @@
 extern int init_atu;
 static int __init
-iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
+iq81340sc_atux_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
 {
        WARN_ON(idsel < 1 || idsel > 2);
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 861cb12ef436..2f28018c4447 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -36,8 +36,8 @@ u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
 u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
 static struct pci_bus *pci_bus_atux = 0;
 static struct pci_bus *pci_bus_atue = 0;
-u32 iop13xx_atue_mem_base;
+void __iomem *iop13xx_atue_mem_base;
-u32 iop13xx_atux_mem_base;
+void __iomem *iop13xx_atux_mem_base;
 size_t iop13xx_atue_mem_size;
 size_t iop13xx_atux_mem_size;
@@ -88,8 +88,7 @@ void iop13xx_map_pci_memory(void)
                                }
                                if (end) {
-                                        iop13xx_atux_mem_base =
+                                        iop13xx_atux_mem_base = __arm_ioremap_pfn(
-                                        (u32) __arm_ioremap_pfn(
                                        __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
                                        , 0, iop13xx_atux_mem_size, MT_DEVICE);
                                        if (!iop13xx_atux_mem_base) {
@@ -99,7 +98,7 @@ void iop13xx_map_pci_memory(void)
                                        }
                                } else
                                        iop13xx_atux_mem_size = 0;
-                                PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
+                                PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
                                __func__, atu, iop13xx_atux_mem_size,
                                iop13xx_atux_mem_base);
                                break;
@@ -114,8 +113,7 @@ void iop13xx_map_pci_memory(void)
                                }
                                if (end) {
-                                        iop13xx_atue_mem_base =
+                                        iop13xx_atue_mem_base = __arm_ioremap_pfn(
-                                        (u32) __arm_ioremap_pfn(
                                        __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
                                        , 0, iop13xx_atue_mem_size, MT_DEVICE);
                                        if (!iop13xx_atue_mem_base) {
@@ -125,13 +123,13 @@ void iop13xx_map_pci_memory(void)
                                        }
                                } else
                                        iop13xx_atue_mem_size = 0;
-                                PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
+                                PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
                                __func__, atu, iop13xx_atue_mem_size,
                                iop13xx_atue_mem_base);
                                break;
                        }
-                        printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
+                        printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n",
                        atu ? "ATUE" : "ATUX",
                        (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
                        SZ_1M,
@@ -506,7 +504,7 @@ iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 /* Scan an IOP13XX PCI bus.  nr selects which ATU we use.
 */
-struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
+struct pci_bus * __devinit iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
 {
        int which_atu;
        struct pci_bus *bus = NULL;
@@ -970,7 +968,6 @@ void __init iop13xx_pci_init(void)
        __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
        /* Setup the Min Address for PCI memory... */
-        pcibios_min_io = 0;
        pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
        /* if Linux is given control of an ATU
@@ -1003,7 +1000,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
        if (nr > 1)
                return 0;
-        res = kcalloc(2, sizeof(struct resource), GFP_KERNEL);
+        res = kzalloc(sizeof(struct resource), GFP_KERNEL);
        if (!res)
                panic("PCI: unable to alloc resources");
@@ -1042,17 +1039,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                                  << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
                __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
-                res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET;
+                pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA);
-                res[0].end   = IOP13XX_PCIX_UPPER_IO_PA;
-                res[0].name  = "IQ81340 ATUX PCI I/O Space";
-                res[0].flags = IORESOURCE_IO;
-                res[1].start = IOP13XX_PCIX_LOWER_MEM_RA;
+                res->start = IOP13XX_PCIX_LOWER_MEM_RA;
-                res[1].end   = IOP13XX_PCIX_UPPER_MEM_RA;
+                res->end   = IOP13XX_PCIX_UPPER_MEM_RA;
-                res[1].name  = "IQ81340 ATUX PCI Memory Space";
+                res->name  = "IQ81340 ATUX PCI Memory Space";
-                res[1].flags = IORESOURCE_MEM;
+                res->flags = IORESOURCE_MEM;
                sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
-                sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA;
                break;
        case IOP13XX_INIT_ATU_ATUE:
                /* Note: the function number field in the PCSR is ro */
@@ -1063,17 +1056,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
-                res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET;
+                pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA);
-                res[0].end   = IOP13XX_PCIE_UPPER_IO_PA;
-                res[0].name  = "IQ81340 ATUE PCI I/O Space";
-                res[0].flags = IORESOURCE_IO;
-                res[1].start = IOP13XX_PCIE_LOWER_MEM_RA;
+                res->start = IOP13XX_PCIE_LOWER_MEM_RA;
-                res[1].end   = IOP13XX_PCIE_UPPER_MEM_RA;
+                res->end   = IOP13XX_PCIE_UPPER_MEM_RA;
-                res[1].name  = "IQ81340 ATUE PCI Memory Space";
+                res->name  = "IQ81340 ATUE PCI Memory Space";
-                res[1].flags = IORESOURCE_MEM;
+                res->flags = IORESOURCE_MEM;
                sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
-                sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA;
                sys->map_irq = iop13xx_pcie_map_irq;
                break;
        default:
@@ -1081,11 +1070,9 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                return 0;
        }
-        request_resource(&ioport_resource, &res[0]);
+        request_resource(&iomem_resource, res);
-        request_resource(&iomem_resource, &res[1]);
-        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
+        pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
-        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
        return 1;
 }
diff --git a/arch/arm/mach-iop13xx/pci.h b/arch/arm/mach-iop13xx/pci.h
index c70cf5b41e31..d45a80b3080e 100644
--- a/arch/arm/mach-iop13xx/pci.h
+++ b/arch/arm/mach-iop13xx/pci.h
@@ -1,6 +1,6 @@
 #include <linux/types.h>
-extern u32 iop13xx_atue_mem_base;
+extern void __iomem *iop13xx_atue_mem_base;
-extern u32 iop13xx_atux_mem_base;
+extern void __iomem *iop13xx_atux_mem_base;
 extern size_t iop13xx_atue_mem_size;
 extern size_t iop13xx_atux_mem_size;
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index daabb1fa6c2c..3181f61ea63e 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -36,20 +36,10 @@
 */
 static struct map_desc iop13xx_std_desc[] __initdata = {
        {    /* mem mapped registers */
-                .virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
+                .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
                .pfn     = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
                .length  = IOP13XX_PMMR_SIZE,
                .type    = MT_DEVICE,
-        }, { /* PCIE IO space */
-                .virtual = IOP13XX_PCIE_LOWER_IO_VA,
-                .pfn     = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
-                .length  = IOP13XX_PCIX_IO_WINDOW_SIZE,
-                .type    = MT_DEVICE,
-        }, { /* PCIX IO space */
-                .virtual = IOP13XX_PCIX_LOWER_IO_VA,
-                .pfn     = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
-                .length  = IOP13XX_PCIX_IO_WINDOW_SIZE,
-                .type    = MT_DEVICE,
        },
 };
@@ -81,8 +71,8 @@ static struct resource iop13xx_uart1_resources[] = {
 static struct plat_serial8250_port iop13xx_uart0_data[] = {
        {
-       .membase     = (char*)(IOP13XX_UART0_VIRT),
+       .membase     = IOP13XX_UART0_VIRT,
-       .mapbase     = (IOP13XX_UART0_PHYS),
+       .mapbase     = IOP13XX_UART0_PHYS,
       .irq         = IRQ_IOP13XX_UART0,
       .uartclk     = IOP13XX_UART_XTAL,
       .regshift    = 2,
@@ -94,8 +84,8 @@ static struct plat_serial8250_port iop13xx_uart0_data[] = {
 static struct plat_serial8250_port iop13xx_uart1_data[] = {
        {
-       .membase     = (char*)(IOP13XX_UART1_VIRT),
+       .membase     = IOP13XX_UART1_VIRT,
-       .mapbase     = (IOP13XX_UART1_PHYS),
+       .mapbase     = IOP13XX_UART1_PHYS,
       .irq         = IRQ_IOP13XX_UART1,
       .uartclk     = IOP13XX_UART_XTAL,
       .regshift    = 2,
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index c15a100ba779..02e20c3912ba 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -183,7 +183,7 @@ static struct i2c_board_info __initdata glantank_i2c_devices[] = {
 static void glantank_power_off(void)
 {
-        __raw_writeb(0x01, 0xfe8d0004);
+        __raw_writeb(0x01, IOMEM(0xfe8d0004));
        while (1)
                ;
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
deleted file mode 100644
index e2ada265bb8d..000000000000
--- a/arch/arm/mach-iop32x/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-iop32x/include/mach/io.h
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __IO_H
-#define __IO_H
-#include <asm/hardware/iop3xx.h>
-#define IO_SPACE_LIMIT          0xffffffff
-#define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
-#endif
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
deleted file mode 100644
index f7c1b6595660..000000000000
--- a/arch/arm/mach-iop33x/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-iop33x/include/mach/io.h
- *
- * Copyright (C) 2001  MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __IO_H
-#define __IO_H
-#include <asm/hardware/iop3xx.h>
-#define IO_SPACE_LIMIT          0xffffffff
-#define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
-#endif
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index a9f80943d01f..fdf91a160884 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -53,24 +53,24 @@ static struct clock_event_device clockevent_ixp4xx;
 *************************************************************************/
 static struct map_desc ixp4xx_io_desc[] __initdata = {
        {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
-                .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
+                .virtual        = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
                .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
                .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
                .type           = MT_DEVICE
        }, {    /* Expansion Bus Config Registers */
-                .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
+                .virtual        = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
                .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
                .length         = IXP4XX_EXP_CFG_REGION_SIZE,
                .type           = MT_DEVICE
        }, {    /* PCI Registers */
-                .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
+                .virtual        = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
                .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
                .length         = IXP4XX_PCI_CFG_REGION_SIZE,
                .type           = MT_DEVICE
        },
 #ifdef CONFIG_DEBUG_LL
        {       /* Debug UART mapping */
-                .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
+                .virtual        = (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT,
                .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
                .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
                .type           = MT_DEVICE
diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h
index b2ef65db0e91..ebc0ba31ce85 100644
--- a/arch/arm/mach-ixp4xx/include/mach/cpu.h
+++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
@@ -14,6 +14,7 @@
 #ifndef __ASM_ARCH_CPU_H__
 #define __ASM_ARCH_CPU_H__
+#include <linux/io.h>
 #include <asm/cputype.h>
 /* Processor id value in CP15 Register 0 */
@@ -37,7 +38,7 @@
 static inline u32 ixp4xx_read_feature_bits(void)
 {
-        u32 val = ~*IXP4XX_EXP_CFG2;
+        u32 val = ~__raw_readl(IXP4XX_EXP_CFG2);
        if (cpu_is_ixp42x_rev_a0())
                return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
@@ -51,7 +52,7 @@ static inline u32 ixp4xx_read_feature_bits(void)
 static inline void ixp4xx_write_feature_bits(u32 value)
 {
-        *IXP4XX_EXP_CFG2 = ~value;
+        __raw_writel(~value, IXP4XX_EXP_CFG2);
 }
 #endif  /* _ASM_ARCH_CPU_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/gpio.h b/arch/arm/mach-ixp4xx/include/mach/gpio.h
deleted file mode 100644
index ef37f2635b0e..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/gpio.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
index 97c530f66e78..eb68b61ce975 100644
--- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
@@ -49,21 +49,21 @@
 * Expansion BUS Configuration registers
 */
 #define IXP4XX_EXP_CFG_BASE_PHYS        (0xC4000000)
-#define IXP4XX_EXP_CFG_BASE_VIRT        (0xFFBFE000)
+#define IXP4XX_EXP_CFG_BASE_VIRT        IOMEM(0xFFBFE000)
 #define IXP4XX_EXP_CFG_REGION_SIZE      (0x00001000)
 /*
 * PCI Config registers
 */
 #define IXP4XX_PCI_CFG_BASE_PHYS        (0xC0000000)
-#define IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFF000)
+#define IXP4XX_PCI_CFG_BASE_VIRT        IOMEM(0xFFBFF000)
 #define IXP4XX_PCI_CFG_REGION_SIZE      (0x00001000)
 /*
 * Peripheral space
 */
 #define IXP4XX_PERIPHERAL_BASE_PHYS     (0xC8000000)
-#define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBEB000)
+#define IXP4XX_PERIPHERAL_BASE_VIRT     IOMEM(0xFFBEB000)
 #define IXP4XX_PERIPHERAL_REGION_SIZE   (0x00013000)
 /*
@@ -73,7 +73,7 @@
 * aligned so that it * can be used with the low-level debug code.
 */
 #define IXP4XX_DEBUG_UART_BASE_PHYS     (0xC8000000)
-#define IXP4XX_DEBUG_UART_BASE_VIRT     (0xffb00000)
+#define IXP4XX_DEBUG_UART_BASE_VIRT     IOMEM(0xffb00000)
 #define IXP4XX_DEBUG_UART_REGION_SIZE   (0x00001000)
 #define IXP4XX_EXP_CS0_OFFSET   0x00
@@ -92,7 +92,7 @@
 /*
 * Expansion Bus Controller registers.
 */
-#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
+#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
 #define IXP4XX_EXP_CS0      IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
 #define IXP4XX_EXP_CS1      IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ca5c15a4e626..50bca5032b7e 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -94,6 +94,13 @@ config MACH_TS219_DT
          or MV6282. If you have the wrong one, the buttons will not
          work.
+config MACH_DOCKSTAR_DT
+        bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Seagate FreeAgent Dockstar (Flattened Device Tree).
 config MACH_GOFLEXNET_DT
        bool "Seagate GoFlex Net (Flattened Device Tree)"
        select ARCH_KIRKWOOD_DT
@@ -109,6 +116,20 @@ config MACH_LSXL_DT
          Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
          Flattened Device Tree.
+config MACH_IOMEGA_IX2_200_DT
+        bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Iomega StorCenter ix2-200 (Flattened Device Tree).
+config MACH_KM_KIRKWOOD_DT
+        bool "Keymile Kirkwood Reference Design (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
 config MACH_TS219
        bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
        help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 055c85a1cc46..294779f892d9 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -26,5 +26,8 @@ obj-$(CONFIG_MACH_ICONNECT_DT)		+= board-iconnect.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)    += board-dnskw.o
 obj-$(CONFIG_MACH_IB62X0_DT)            += board-ib62x0.o
 obj-$(CONFIG_MACH_TS219_DT)             += board-ts219.o tsx1x-common.o
+obj-$(CONFIG_MACH_DOCKSTAR_DT)          += board-dockstar.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)         += board-goflexnet.o
 obj-$(CONFIG_MACH_LSXL_DT)              += board-lsxl.o
+obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)    += board-iomega_ix2_200.o
+obj-$(CONFIG_MACH_KM_KIRKWOOD_DT)       += board-km_kirkwood.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index a13299d758e1..760a0efe7580 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -1,14 +1,3 @@
   zreladdr-y   += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
-dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb
-dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb
-dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb
-dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
-dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb
-dtb-$(CONFIG_MACH_TS219_DT)     += kirkwood-ts219-6281.dtb
-dtb-$(CONFIG_MACH_TS219_DT)     += kirkwood-ts219-6282.dtb
-dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
-dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
-dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index e9a7180863d9..8f0d162a1e1d 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -86,5 +86,6 @@ void __init kirkwood_setup_cpu_mbus(void)
        /*
         * Setup MBUS dram target info.
         */
-        orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
+        orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                    (void __iomem *) DDR_WINDOW_CPU_BASE);
 }
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index 4ab35065a144..43d16d6714b8 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -14,18 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/of.h>
 #include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/gpio-fan.h>
-#include <linux/leds.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/kirkwood.h>
-#include <mach/bridge-regs.h>
 #include "common.h"
 #include "mpp.h"
@@ -67,29 +57,6 @@ static unsigned int dnskw_mpp_config[] __initdata = {
        0
 };
-/* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
-static struct gpio_fan_speed dnskw_fan_speed[] = {
-        {    0,  0 },
-        { 3000,  1 },
-        { 6000,  2 },
-};
-static unsigned dnskw_fan_pins[] = {46, 45};
-static struct gpio_fan_platform_data dnskw_fan_data = {
-        .num_ctrl       = ARRAY_SIZE(dnskw_fan_pins),
-        .ctrl           = dnskw_fan_pins,
-        .num_speed      = ARRAY_SIZE(dnskw_fan_speed),
-        .speed          = dnskw_fan_speed,
-};
-static struct platform_device dnskw_fan_device = {
-        .name   = "gpio-fan",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &dnskw_fan_data,
-        },
-};
 static void dnskw_power_off(void)
 {
        gpio_set_value(36, 1);
@@ -114,8 +81,6 @@ void __init dnskw_init(void)
        kirkwood_ehci_init();
        kirkwood_ge00_init(&dnskw_ge00_data);
-        platform_device_register(&dnskw_fan_device);
        /* Register power-off GPIO. */
        if (gpio_request(36, "dnskw:power:off") == 0
            && gpio_direction_output(36, 0) == 0)
diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c
new file mode 100644
index 000000000000..f2fbb023e679
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dockstar.c
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/mach-kirkwood/board-dockstar.c
+ *
+ * Seagate FreeAgent Dockstar Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Copied and modified for Seagate GoFlex Net support by
+ * Joshua Coombs <josh.coombs@gmail.com> based on ArchLinux ARM's
+ * GoFlex kernel patches.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
+#include <linux/platform_data/mmc-mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+static struct mv643xx_eth_platform_data dockstar_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+static unsigned int dockstar_mpp_config[] __initdata = {
+        MPP29_GPIO,     /* USB Power Enable */
+        MPP46_GPIO,     /* LED green */
+        MPP47_GPIO,     /* LED orange */
+        0
+};
+void __init dockstar_dt_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(dockstar_mpp_config);
+        if (gpio_request(29, "USB Power Enable") != 0 ||
+            gpio_direction_output(29, 1) != 0)
+                pr_err("can't setup GPIO 29 (USB Power Enable)\n");
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&dockstar_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
index aeb234d0d0e3..20af53a56c0e 100644
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -30,7 +30,7 @@
 #include <asm/mach/map.h>
 #include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e4eb450de301..70c5a2882409 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -33,6 +33,7 @@ struct of_dev_auxdata kirkwood_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
        OF_DEV_AUXDATA("marvell,orion-sata", 0xf1080000, "sata_mv.0", NULL),
        OF_DEV_AUXDATA("marvell,orion-nand", 0xf4000000, "orion_nand", NULL),
+        OF_DEV_AUXDATA("marvell,orion-crypto", 0xf1030000, "mv_crypto", NULL),
        {},
 };
@@ -60,7 +61,6 @@ static void __init kirkwood_dt_init(void)
        /* internal devices that every board has */
        kirkwood_xor0_init();
        kirkwood_xor1_init();
-        kirkwood_crypto_init();
 #ifdef CONFIG_KEXEC
        kexec_reinit = kirkwood_enable_pcie;
@@ -81,12 +81,21 @@ static void __init kirkwood_dt_init(void)
        if (of_machine_is_compatible("qnap,ts219"))
                qnap_dt_ts219_init();
+        if (of_machine_is_compatible("seagate,dockstar"))
+                dockstar_dt_init();
        if (of_machine_is_compatible("seagate,goflexnet"))
                goflexnet_init();
        if (of_machine_is_compatible("buffalo,lsxl"))
                lsxl_init();
+        if (of_machine_is_compatible("iom,ix2-200"))
+                iomega_ix2_200_init();
+        if (of_machine_is_compatible("keymile,km_kirkwood"))
+                km_kirkwood_init();
        of_platform_populate(NULL, kirkwood_dt_match_table,
                             kirkwood_auxdata_lookup, NULL);
 }
@@ -98,8 +107,11 @@ static const char *kirkwood_dt_board_compat[] = {
        "iom,iconnect",
        "raidsonic,ib-nas62x0",
        "qnap,ts219",
+        "seagate,dockstar",
        "seagate,goflexnet",
        "buffalo,lsxl",
+        "iom,ix2-200",
+        "keymile,km_kirkwood",
        NULL
 };
diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c
index 413e2c8ef5fe..001ca8c96980 100644
--- a/arch/arm/mach-kirkwood/board-goflexnet.c
+++ b/arch/arm/mach-kirkwood/board-goflexnet.c
@@ -32,7 +32,7 @@
 #include <asm/mach/map.h>
 #include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index d7a9198ed300..d084b1e2943a 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -16,11 +16,8 @@
 #include <linux/of_fdt.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/mtd/partitions.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include "common.h"
@@ -44,57 +41,12 @@ static unsigned int iconnect_mpp_config[] __initdata = {
        0
 };
-static struct mtd_partition iconnect_nand_parts[] = {
-        {
-                .name = "flash",
-                .offset = 0,
-                .size = MTDPART_SIZ_FULL,
-        },
-};
-/* yikes... theses are the original input buttons */
-/* but I'm not convinced by the sw event choices  */
-static struct gpio_keys_button iconnect_buttons[] = {
-        {
-                .type           = EV_SW,
-                .code           = SW_LID,
-                .gpio           = 12,
-                .desc           = "Reset Button",
-                .active_low     = 1,
-                .debounce_interval = 100,
-        }, {
-                .type           = EV_SW,
-                .code           = SW_TABLET_MODE,
-                .gpio           = 35,
-                .desc           = "OTB Button",
-                .active_low     = 1,
-                .debounce_interval = 100,
-        },
-};
-static struct gpio_keys_platform_data iconnect_button_data = {
-        .buttons        = iconnect_buttons,
-        .nbuttons       = ARRAY_SIZE(iconnect_buttons),
-};
-static struct platform_device iconnect_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev        = {
-                .platform_data  = &iconnect_button_data,
-        },
-};
 void __init iconnect_init(void)
 {
        kirkwood_mpp_conf(iconnect_mpp_config);
-        kirkwood_nand_init(ARRAY_AND_SIZE(iconnect_nand_parts), 25);
        kirkwood_ehci_init();
        kirkwood_ge00_init(&iconnect_ge00_data);
-        platform_device_register(&iconnect_button_device);
 }
 static int __init iconnect_pci_init(void)
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
new file mode 100644
index 000000000000..158fb97d0397
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+ *
+ * Iomega StorCenter ix2-200
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_NONE,
+        .speed          = SPEED_1000,
+        .duplex         = DUPLEX_FULL,
+};
+static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
+        MPP12_GPIO,                     /* Reset Button */
+        MPP14_GPIO,                     /* Power Button */
+        MPP15_GPIO,                     /* Backup LED (blue) */
+        MPP16_GPIO,                     /* Power LED (white) */
+        MPP35_GPIO,                     /* OTB Button */
+        MPP36_GPIO,                     /* Rebuild LED (white) */
+        MPP37_GPIO,                     /* Health LED (red) */
+        MPP38_GPIO,                     /* SATA LED brightness control 1 */
+        MPP39_GPIO,                     /* SATA LED brightness control 2 */
+        MPP40_GPIO,                     /* Backup LED brightness control 1 */
+        MPP41_GPIO,                     /* Backup LED brightness control 2 */
+        MPP42_GPIO,                     /* Power LED brightness control 1 */
+        MPP43_GPIO,                     /* Power LED brightness control 2 */
+        MPP44_GPIO,                     /* Health LED brightness control 1 */
+        MPP45_GPIO,                     /* Health LED brightness control 2 */
+        MPP46_GPIO,                     /* Rebuild LED brightness control 1 */
+        MPP47_GPIO,                     /* Rebuild LED brightness control 2 */
+        0
+};
+void __init iomega_ix2_200_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
+        kirkwood_ehci_init();
+        kirkwood_ge01_init(&iomega_ix2_200_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
new file mode 100644
index 000000000000..f7d32834b757
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2012 2012 KEYMILE AG, CH-3097 Bern
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * arch/arm/mach-kirkwood/board-km_kirkwood.c
+ *
+ * Keymile km_kirkwood Reference Desing Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include "common.h"
+#include "mpp.h"
+static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+static unsigned int km_kirkwood_mpp_config[] __initdata = {
+        MPP8_GPIO,      /* I2C SDA */
+        MPP9_GPIO,      /* I2C SCL */
+        0
+};
+void __init km_kirkwood_init(void)
+{
+        struct clk *sata_clk;
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(km_kirkwood_mpp_config);
+        /*
+         * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
+         * SATA bits (14-15) of the Clock Gating Control Register. Since these
+         * devices are also not present in this variant, their clocks get
+         * disabled because unused when clk_disable_unused() gets called.
+         * That's why we change the flags to these clocks to CLK_IGNORE_UNUSED
+         */
+        sata_clk = clk_get_sys("sata_mv.0", "0");
+        if (!IS_ERR(sata_clk))
+                sata_clk->flags |= CLK_IGNORE_UNUSED;
+        sata_clk = clk_get_sys("sata_mv.0", "1");
+        if (!IS_ERR(sata_clk))
+                sata_clk->flags |= CLK_IGNORE_UNUSED;
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&km_kirkwood_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 1201191d7f1b..3991077f58a2 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -26,15 +26,15 @@
 #include <asm/mach/time.h>
 #include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-kirkwood.h>
 #include <plat/cache-feroceon-l2.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
-#include <plat/orion_nand.h>
+#include <linux/platform_data/mtd-orion_nand.h>
-#include <plat/ehci-orion.h>
+#include <linux/platform_data/usb-ehci-orion.h>
 #include <plat/common.h>
 #include <plat/time.h>
 #include <plat/addr-map.h>
-#include <plat/mv_xor.h>
+#include <linux/platform_data/dma-mv_xor.h>
 #include "common.h"
 /*****************************************************************************
@@ -42,17 +42,7 @@
 ****************************************************************************/
 static struct map_desc kirkwood_io_desc[] __initdata = {
        {
-                .virtual        = KIRKWOOD_PCIE_IO_VIRT_BASE,
+                .virtual        = (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
-                .pfn            = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
-                .length         = KIRKWOOD_PCIE_IO_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = KIRKWOOD_PCIE1_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
-                .length         = KIRKWOOD_PCIE1_IO_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = KIRKWOOD_REGS_VIRT_BASE,
                .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
                .length         = KIRKWOOD_REGS_SIZE,
                .type           = MT_DEVICE,
@@ -215,8 +205,7 @@ static struct clk *tclk;
 static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
 {
-        return clk_register_gate(NULL, name, "tclk", 0,
+        return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
-                                 (void __iomem *)CLOCK_GATING_CTRL,
                                 bit_idx, 0, &gating_lock);
 }
@@ -225,8 +214,7 @@ static struct clk __init *kirkwood_register_gate_fn(const char *name,
                                                    void (*fn_en)(void),
                                                    void (*fn_dis)(void))
 {
-        return clk_register_gate_fn(NULL, name, "tclk", 0,
+        return clk_register_gate_fn(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
-                                    (void __iomem *)CLOCK_GATING_CTRL,
                                    bit_idx, 0, &gating_lock, fn_en, fn_dis);
 }
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 304dd1abfdca..bcffd7ca1ca2 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -82,6 +82,12 @@ void ib62x0_init(void);
 static inline void ib62x0_init(void) {};
 #endif
+#ifdef CONFIG_MACH_DOCKSTAR_DT
+void dockstar_dt_init(void);
+#else
+static inline void dockstar_dt_init(void) {};
+#endif
 #ifdef CONFIG_MACH_GOFLEXNET_DT
 void goflexnet_init(void);
 #else
@@ -94,6 +100,18 @@ void lsxl_init(void);
 static inline void lsxl_init(void) {};
 #endif
+#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
+void iomega_ix2_200_init(void);
+#else
+static inline void iomega_ix2_200_init(void) {};
+#endif
+#ifdef CONFIG_MACH_KM_KIRKWOOD_DT
+void km_kirkwood_init(void);
+#else
+static inline void km_kirkwood_init(void) {};
+#endif
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
index 6e1bac929ab5..2c1a453df201 100644
--- a/arch/arm/mach-kirkwood/d2net_v2-setup.c
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -32,7 +32,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <mach/leds-ns2.h>
+#include <linux/platform_data/leds-kirkwood-ns2.h>
 #include "common.h"
 #include "mpp.h"
 #include "lacie_v2-common.h"
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index be90b7d0e10b..c49b177c1523 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -18,7 +18,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
index 61d9a552a054..23dcb19cc2a7 100644
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -19,7 +19,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index bdaed3867d13..7cb55f982243 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -19,7 +19,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index a115142f8690..5c82b7dce4e2 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -13,37 +13,37 @@
 #include <mach/kirkwood.h>
-#define CPU_CONFIG              (BRIDGE_VIRT_BASE | 0x0100)
+#define CPU_CONFIG              (BRIDGE_VIRT_BASE + 0x0100)
 #define CPU_CONFIG_ERROR_PROP   0x00000004
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
 #define CPU_RESET               0x00000002
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
 #define WDT_RESET_OUT_EN        0x00000002
 #define SOFT_RESET_OUT_EN       0x00000004
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET              0x00000001
-#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
+#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE + 0x0110)
 #define WDT_INT_REQ             0x0008
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_LOW_OFF       0x0000
 #define IRQ_MASK_LOW_OFF        0x0004
 #define IRQ_CAUSE_HIGH_OFF      0x0010
 #define IRQ_MASK_HIGH_OFF       0x0014
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
-#define L2_CONFIG_REG           (BRIDGE_VIRT_BASE | 0x0128)
+#define L2_CONFIG_REG           (BRIDGE_VIRT_BASE + 0x0128)
 #define L2_WRITETHROUGH         0x00000010
-#define CLOCK_GATING_CTRL       (BRIDGE_VIRT_BASE | 0x11c)
+#define CLOCK_GATING_CTRL       (BRIDGE_VIRT_BASE + 0x11c)
 #define CGC_BIT_GE0             (0)
 #define CGC_BIT_PEX0            (2)
 #define CGC_BIT_USB0            (3)
diff --git a/arch/arm/mach-kirkwood/include/mach/gpio.h b/arch/arm/mach-kirkwood/include/mach/gpio.h
deleted file mode 100644
index 84f340b546c0..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/gpio.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * arch/asm-arm/mach-kirkwood/include/mach/gpio.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <plat/gpio.h>
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
deleted file mode 100644
index 5d0ab61700d2..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/io.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-#include "kirkwood.h"
-#define IO_SPACE_LIMIT          0xffffffff
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_BUS_BASE)
-                                        + KIRKWOOD_PCIE_IO_VIRT_BASE);
-}
-#define __io(a)                 __io(a)
-#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index c5b68510776b..041653a04a9c 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -37,17 +37,15 @@
 #define KIRKWOOD_NAND_MEM_SIZE          SZ_1K
 #define KIRKWOOD_PCIE1_IO_PHYS_BASE     0xf3000000
-#define KIRKWOOD_PCIE1_IO_VIRT_BASE     0xfef00000
+#define KIRKWOOD_PCIE1_IO_BUS_BASE      0x00010000
-#define KIRKWOOD_PCIE1_IO_BUS_BASE      0x00100000
+#define KIRKWOOD_PCIE1_IO_SIZE          SZ_64K
-#define KIRKWOOD_PCIE1_IO_SIZE          SZ_1M
 #define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
-#define KIRKWOOD_PCIE_IO_VIRT_BASE      0xfee00000
 #define KIRKWOOD_PCIE_IO_BUS_BASE       0x00000000
-#define KIRKWOOD_PCIE_IO_SIZE           SZ_1M
+#define KIRKWOOD_PCIE_IO_SIZE           SZ_64K
 #define KIRKWOOD_REGS_PHYS_BASE         0xf1000000
-#define KIRKWOOD_REGS_VIRT_BASE         0xfed00000
+#define KIRKWOOD_REGS_VIRT_BASE         IOMEM(0xfed00000)
 #define KIRKWOOD_REGS_SIZE              SZ_1M
 #define KIRKWOOD_PCIE_MEM_PHYS_BASE     0xe0000000
@@ -61,61 +59,61 @@
 /*
 * Register Map
 */
-#define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
+#define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
-#define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE | 0x1500)
+#define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE + 0x1500)
-#define DDR_OPERATION_BASE      (DDR_VIRT_BASE | 0x1418)
+#define DDR_OPERATION_BASE      (DDR_VIRT_BASE + 0x1418)
-#define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
-#define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
-#define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE | 0x0030)
+#define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE + 0x0030)
-#define  DEVICE_ID              (DEV_BUS_VIRT_BASE | 0x0034)
+#define  DEVICE_ID              (DEV_BUS_VIRT_BASE + 0x0034)
-#define  GPIO_LOW_VIRT_BASE     (DEV_BUS_VIRT_BASE | 0x0100)
+#define  GPIO_LOW_VIRT_BASE     (DEV_BUS_VIRT_BASE + 0x0100)
-#define  GPIO_HIGH_VIRT_BASE    (DEV_BUS_VIRT_BASE | 0x0140)
+#define  GPIO_HIGH_VIRT_BASE    (DEV_BUS_VIRT_BASE + 0x0140)
-#define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0300)
+#define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x0300)
-#define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0600)
+#define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x0600)
-#define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x1000)
+#define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x1000)
-#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2000)
-#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2000)
-#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2100)
-#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2100)
-#define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
+#define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
-#define BRIDGE_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE | 0x20000)
+#define BRIDGE_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
-#define CRYPTO_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE | 0x30000)
+#define CRYPTO_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
-#define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
+#define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x40000)
-#define PCIE_LINK_CTRL          (PCIE_VIRT_BASE | 0x70)
+#define PCIE_LINK_CTRL          (PCIE_VIRT_BASE + 0x70)
-#define PCIE_STATUS             (PCIE_VIRT_BASE | 0x1a04)
+#define PCIE_STATUS             (PCIE_VIRT_BASE + 0x1a04)
-#define PCIE1_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
+#define PCIE1_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0x44000)
-#define PCIE1_LINK_CTRL         (PCIE1_VIRT_BASE | 0x70)
+#define PCIE1_LINK_CTRL         (PCIE1_VIRT_BASE + 0x70)
-#define PCIE1_STATUS            (PCIE1_VIRT_BASE | 0x1a04)
+#define PCIE1_STATUS            (PCIE1_VIRT_BASE + 0x1a04)
-#define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
+#define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE + 0x50000)
-#define XOR0_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x60800)
+#define XOR0_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x60800)
-#define XOR0_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x60800)
+#define XOR0_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x60800)
-#define XOR1_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x60900)
+#define XOR1_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x60900)
-#define XOR1_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x60900)
+#define XOR1_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x60900)
-#define XOR0_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE | 0x60A00)
+#define XOR0_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE + 0x60A00)
-#define XOR0_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE | 0x60A00)
+#define XOR0_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE + 0x60A00)
-#define XOR1_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE | 0x60B00)
+#define XOR1_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
-#define XOR1_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE | 0x60B00)
+#define XOR1_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE + 0x60B00)
-#define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
+#define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x70000)
-#define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
+#define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x74000)
-#define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
+#define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x80000)
-#define SATA_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x80000)
+#define SATA_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x80000)
-#define SATA0_IF_CTRL           (SATA_VIRT_BASE | 0x2050)
+#define SATA0_IF_CTRL           (SATA_VIRT_BASE + 0x2050)
-#define SATA0_PHY_MODE_2        (SATA_VIRT_BASE | 0x2330)
+#define SATA0_PHY_MODE_2        (SATA_VIRT_BASE + 0x2330)
-#define SATA1_IF_CTRL           (SATA_VIRT_BASE | 0x4050)
+#define SATA1_IF_CTRL           (SATA_VIRT_BASE + 0x4050)
-#define SATA1_PHY_MODE_2        (SATA_VIRT_BASE | 0x4330)
+#define SATA1_PHY_MODE_2        (SATA_VIRT_BASE + 0x4330)
-#define SDIO_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
+#define SDIO_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x90000)
-#define AUDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0xA0000)
+#define AUDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE + 0xA0000)
-#define AUDIO_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0xA0000)
+#define AUDIO_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0xA0000)
 /*
 * Supported devices and revisions.
diff --git a/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h b/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
deleted file mode 100644
index 24b536ebdf13..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
- *
- * Platform data structure for netxbig LED driver
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_LEDS_NETXBIG_H
-#define __MACH_LEDS_NETXBIG_H
-struct netxbig_gpio_ext {
-        unsigned        *addr;
-        int             num_addr;
-        unsigned        *data;
-        int             num_data;
-        unsigned        enable;
-};
-enum netxbig_led_mode {
-        NETXBIG_LED_OFF,
-        NETXBIG_LED_ON,
-        NETXBIG_LED_SATA,
-        NETXBIG_LED_TIMER1,
-        NETXBIG_LED_TIMER2,
-        NETXBIG_LED_MODE_NUM,
-};
-#define NETXBIG_LED_INVALID_MODE NETXBIG_LED_MODE_NUM
-struct netxbig_led_timer {
-        unsigned long           delay_on;
-        unsigned long           delay_off;
-        enum netxbig_led_mode   mode;
-};
-struct netxbig_led {
-        const char      *name;
-        const char      *default_trigger;
-        int             mode_addr;
-        int             *mode_val;
-        int             bright_addr;
-};
-struct netxbig_led_platform_data {
-        struct netxbig_gpio_ext *gpio_ext;
-        struct netxbig_led_timer *timer;
-        int                     num_timer;
-        struct netxbig_led      *leds;
-        int                     num_leds;
-};
-#endif /* __MACH_LEDS_NETXBIG_H */
diff --git a/arch/arm/mach-kirkwood/include/mach/leds-ns2.h b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
deleted file mode 100644
index e21272e5f668..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/leds-ns2.h
- *
- * Platform data structure for Network Space v2 LED driver
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_LEDS_NS2_H
-#define __MACH_LEDS_NS2_H
-struct ns2_led {
-        const char      *name;
-        const char      *default_trigger;
-        unsigned        cmd;
-        unsigned        slow;
-};
-struct ns2_led_platform_data {
-        int             num_leds;
-        struct ns2_led  *leds;
-};
-#endif /* __MACH_LEDS_NS2_H */
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 720063ffa19d..884703535a0a 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -10,7 +10,9 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
+#include <plat/orion-gpio.h>
 #include <plat/irq.h>
 static int __initdata gpio0_irqs[4] = {
@@ -29,14 +31,14 @@ static int __initdata gpio1_irqs[4] = {
 void __init kirkwood_init_irq(void)
 {
-        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
+        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
-        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
        /*
         * Initialize gpiolib for GPIOs 0-49.
         */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_LOW_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 0, 32, GPIO_LOW_VIRT_BASE, 0,
                        IRQ_KIRKWOOD_GPIO_START, gpio0_irqs);
-        orion_gpio_init(NULL, 32, 18, (void __iomem *)GPIO_HIGH_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 32, 18, GPIO_HIGH_VIRT_BASE, 0,
                        IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs);
 }
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index e6bba01bae38..88b0788bacae 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -34,7 +34,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <mach/leds-ns2.h>
+#include <linux/platform_data/leds-kirkwood-ns2.h>
 #include "common.h"
 #include "mpp.h"
 #include "lacie_v2-common.h"
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 31ae8de34e93..a3b091470b8a 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -32,7 +32,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <mach/leds-netxbig.h>
+#include <linux/platform_data/leds-kirkwood-netxbig.h>
 #include "common.h"
 #include "mpp.h"
 #include "lacie_v2-common.h"
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 7e99c3f340fc..134ef50d58fc 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -20,7 +20,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 6e8b2efa3c35..ec544918b12c 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -47,8 +47,8 @@ void kirkwood_enable_pcie(void)
 void kirkwood_pcie_id(u32 *dev, u32 *rev)
 {
        kirkwood_enable_pcie();
-        *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
+        *dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
-        *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
+        *rev = orion_pcie_rev(PCIE_VIRT_BASE);
 }
 struct pcie_port {
@@ -56,7 +56,7 @@ struct pcie_port {
        void __iomem            *base;
        spinlock_t              conf_lock;
        int                     irq;
-        struct resource         res[2];
+        struct resource         res;
 };
 static int pcie_port_map[2];
@@ -133,46 +133,30 @@ static struct pci_ops pcie_ops = {
 static void __init pcie0_ioresources_init(struct pcie_port *pp)
 {
-        pp->base = (void __iomem *)PCIE_VIRT_BASE;
+        pp->base = PCIE_VIRT_BASE;
        pp->irq = IRQ_KIRKWOOD_PCIE;
        /*
-         * IORESOURCE_IO
-         */
-        pp->res[0].name = "PCIe 0 I/O Space";
-        pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
-        pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
-        pp->res[0].flags = IORESOURCE_IO;
-        /*
         * IORESOURCE_MEM
         */
-        pp->res[1].name = "PCIe 0 MEM";
+        pp->res.name = "PCIe 0 MEM";
-        pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+        pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
-        pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+        pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
-        pp->res[1].flags = IORESOURCE_MEM;
+        pp->res.flags = IORESOURCE_MEM;
 }
 static void __init pcie1_ioresources_init(struct pcie_port *pp)
 {
-        pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+        pp->base = PCIE1_VIRT_BASE;
        pp->irq = IRQ_KIRKWOOD_PCIE1;
        /*
-         * IORESOURCE_IO
-         */
-        pp->res[0].name = "PCIe 1 I/O Space";
-        pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
-        pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
-        pp->res[0].flags = IORESOURCE_IO;
-        /*
         * IORESOURCE_MEM
         */
-        pp->res[1].name = "PCIe 1 MEM";
+        pp->res.name = "PCIe 1 MEM";
-        pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+        pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
-        pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+        pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
-        pp->res[1].flags = IORESOURCE_MEM;
+        pp->res.flags = IORESOURCE_MEM;
 }
 static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
@@ -197,23 +181,21 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
        case 0:
                kirkwood_enable_pcie_clk("0");
                pcie0_ioresources_init(pp);
+                pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
                break;
        case 1:
                kirkwood_enable_pcie_clk("1");
                pcie1_ioresources_init(pp);
+                pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE1_IO_PHYS_BASE);
                break;
        default:
                panic("PCIe setup: invalid controller %d", index);
        }
-        if (request_resource(&ioport_resource, &pp->res[0]))
+        if (request_resource(&iomem_resource, &pp->res))
-                panic("Request PCIe%d IO resource failed\n", index);
-        if (request_resource(&iomem_resource, &pp->res[1]))
                panic("Request PCIe%d Memory resource failed\n", index);
-        sys->io_offset = 0;
+        pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
-        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
-        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
        /*
         * Generic PCIe unit setup.
@@ -273,11 +255,11 @@ static struct hw_pci kirkwood_pci __initdata = {
        .map_irq        = kirkwood_pcie_map_irq,
 };
-static void __init add_pcie_port(int index, unsigned long base)
+static void __init add_pcie_port(int index, void __iomem *base)
 {
        printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
-        if (orion_pcie_link_up((void __iomem *)base)) {
+        if (orion_pcie_link_up(base)) {
                printk(KERN_INFO "link up\n");
                pcie_port_map[num_pcie_ports++] = index;
        } else
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index f742a66a7045..19072c84008f 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -19,6 +19,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
+#include <plat/orion-gpio.h>
 #include "common.h"
 #define RD88F6192_GPIO_USB_VBUS         10
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index ef922079348b..9717101a7437 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -20,7 +20,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index 4ea70e5f7137..28d0abaf4bd9 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -19,7 +19,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
+#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 5bbca2680442..367a9400f532 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -20,6 +20,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/io.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
@@ -161,7 +162,7 @@ static int __init ts41x_pci_init(void)
                 * (Marvell 88sx7042/sata_mv) is known to stop working
                 * after a few minutes.
                 */
-                orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
+                orion_pcie_reset(PCIE_VIRT_BASE);
                kirkwood_pcie_id(&dev, &rev);
                if (dev == MV88F6282_DEV_ID)
diff --git a/arch/arm/mach-ks8695/Kconfig b/arch/arm/mach-ks8695/Kconfig
index f5c39a8c2b00..a545976bdbd6 100644
--- a/arch/arm/mach-ks8695/Kconfig
+++ b/arch/arm/mach-ks8695/Kconfig
@@ -21,6 +21,67 @@ config MACH_ACS5K
          say 'Y' here if you want your kernel to run on the Brivo
          Systems LLC, ACS-5000 Master board.
+config MACH_LITE300
+        bool "SecureComputing SG300"
+        help
+          Say 'Y' here if you want your kernel to support the
+          SecureComputing / SnapGear SG300 VPN Internet Router.
+          See http://www.securecomputing.com for more details.
+config MACH_SG310
+        bool "McAfee SG310"
+        help
+          Say 'Y' here if you want your kernel to support the
+          McAfee / SnapGear SG310 VPN Internet Router.
+          See http://www.mcafee.com for more details.
+config MACH_SE4200
+        bool "SecureComputing SE4200"
+        help
+          Say 'Y' here if you want your kernel to support the
+          SecureComputing / SnapGear SE4200 Secure Wireless VPN
+          Internet Router.
+          See http://www.securecomputing.com for more details.
+config MACH_CM4002
+        bool "OpenGear CM4002"
+        help
+          Say 'Y' here if you want your kernel to support the OpenGear
+          CM4002 Secure Access Server. See http://www.opengear.com for
+          more details.
+config MACH_CM4008
+        bool "OpenGear CM4008"
+        select MIGHT_HAVE_PCI
+        help
+          Say 'Y' here if you want your kernel to support the OpenGear
+          CM4008 Console Server. See http://www.opengear.com for more
+          details.
+config MACH_CM41xx
+        bool "OpenGear CM41xx"
+        select MIGHT_HAVE_PCI
+        help
+          Say 'Y' here if you want your kernel to support the OpenGear
+          CM4016 or CM4048 Console Servers. See http://www.opengear.com for
+          more details.
+config MACH_IM4004
+        bool "OpenGear IM4004"
+        select MIGHT_HAVE_PCI
+        help
+          Say 'Y' here if you want your kernel to support the OpenGear
+          IM4004 Secure Access Server. See http://www.opengear.com for
+          more details.
+config MACH_IM42xx
+        bool "OpenGear IM42xx"
+        select MIGHT_HAVE_PCI
+        help
+          Say 'Y' here if you want your kernel to support the OpenGear
+          IM4216 or IM4248 Console Servers. See http://www.opengear.com for
+          more details.
 endmenu
 endif
diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile
index 853efd9133c6..e370caf0c91b 100644
--- a/arch/arm/mach-ks8695/Makefile
+++ b/arch/arm/mach-ks8695/Makefile
@@ -11,10 +11,15 @@ obj-				:=
 # PCI support is optional
 obj-$(CONFIG_PCI)               += pci.o
-# LEDs
-obj-$(CONFIG_LEDS)              += leds.o
 # Board-specific support
 obj-$(CONFIG_MACH_KS8695)       += board-micrel.o
 obj-$(CONFIG_MACH_DSM320)       += board-dsm320.o
 obj-$(CONFIG_MACH_ACS5K)        += board-acs5k.o
+obj-$(CONFIG_MACH_LITE300)      += board-sg.o
+obj-$(CONFIG_MACH_SG310)        += board-sg.o
+obj-$(CONFIG_MACH_SE4200)       += board-sg.o
+obj-$(CONFIG_MACH_CM4002)       += board-og.o
+obj-$(CONFIG_MACH_CM4008)       += board-og.o
+obj-$(CONFIG_MACH_CM41xx)       += board-og.o
+obj-$(CONFIG_MACH_IM4004)       += board-og.o
+obj-$(CONFIG_MACH_IM42xx)       += board-og.o
diff --git a/arch/arm/mach-ks8695/board-og.c b/arch/arm/mach-ks8695/board-og.c
new file mode 100644
index 000000000000..1623ba461e47
--- /dev/null
+++ b/arch/arm/mach-ks8695/board-og.c
@@ -0,0 +1,199 @@
+/*
+ * board-og.c -- support for the OpenGear KS8695 based boards.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/devices.h>
+#include <mach/regs-gpio.h>
+#include <mach/gpio-ks8695.h>
+#include "generic.h"
+static int og_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        if (machine_is_im4004() && (slot == 8))
+                return KS8695_IRQ_EXTERN1;
+        return KS8695_IRQ_EXTERN0;
+}
+static struct ks8695_pci_cfg __initdata og_pci = {
+        .mode           = KS8695_MODE_PCI,
+        .map_irq        = og_pci_map_irq,
+};
+static void __init og_register_pci(void)
+{
+        /* Initialize the GPIO lines for interrupt mode */
+        ks8695_gpio_interrupt(KS8695_GPIO_0, IRQ_TYPE_LEVEL_LOW);
+        /* Cardbus Slot */
+        if (machine_is_im4004())
+                ks8695_gpio_interrupt(KS8695_GPIO_1, IRQ_TYPE_LEVEL_LOW);
+        ks8695_init_pci(&og_pci);
+}
+/*
+ * The PCI bus reset is driven by a dedicated GPIO line. Toggle it here
+ * and bring the PCI bus out of reset.
+ */
+static void __init og_pci_bus_reset(void)
+{
+        unsigned int rstline = 1;
+        /* Some boards use a different GPIO as the PCI reset line */
+        if (machine_is_im4004())
+                rstline = 2;
+        else if (machine_is_im42xx())
+                rstline = 0;
+        gpio_request(rstline, "PCI reset");
+        gpio_direction_output(rstline, 0);
+        /* Drive a reset on the PCI reset line */
+        gpio_set_value(rstline, 1);
+        gpio_set_value(rstline, 0);
+        mdelay(100);
+        gpio_set_value(rstline, 1);
+        mdelay(100);
+}
+/*
+ * Direct connect serial ports (non-PCI that is).
+ */
+#define S8250_PHYS      0x03800000
+#define S8250_VIRT      0xf4000000
+#define S8250_SIZE      0x00100000
+static struct __initdata map_desc og_io_desc[] = {
+        {
+                .virtual        = S8250_VIRT,
+                .pfn            = __phys_to_pfn(S8250_PHYS),
+                .length         = S8250_SIZE,
+                .type           = MT_DEVICE,
+        }
+};
+static struct resource og_uart_resources[] = {
+        {
+                .start          = S8250_VIRT,
+                .end            = S8250_VIRT + S8250_SIZE,
+                .flags          = IORESOURCE_MEM
+        },
+};
+static struct plat_serial8250_port og_uart_data[] = {
+        {
+                .mapbase        = S8250_VIRT,
+                .membase        = (char *) S8250_VIRT,
+                .irq            = 3,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 115200 * 16,
+        },
+        { },
+};
+static struct platform_device og_uart = {
+        .name                   = "serial8250",
+        .id                     = 0,
+        .dev.platform_data      = og_uart_data,
+        .num_resources          = 1,
+        .resource               = og_uart_resources
+};
+static struct platform_device *og_devices[] __initdata = {
+        &og_uart
+};
+static void __init og_init(void)
+{
+        ks8695_register_gpios();
+        if (machine_is_cm4002()) {
+                ks8695_gpio_interrupt(KS8695_GPIO_1, IRQ_TYPE_LEVEL_HIGH);
+                iotable_init(og_io_desc, ARRAY_SIZE(og_io_desc));
+                platform_add_devices(og_devices, ARRAY_SIZE(og_devices));
+        } else {
+                og_pci_bus_reset();
+                og_register_pci();
+        }
+        ks8695_add_device_lan();
+        ks8695_add_device_wan();
+}
+#ifdef CONFIG_MACH_CM4002
+MACHINE_START(CM4002, "OpenGear/CM4002")
+        /* OpenGear Inc. */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = og_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_CM4008
+MACHINE_START(CM4008, "OpenGear/CM4008")
+        /* OpenGear Inc. */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = og_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_CM41xx
+MACHINE_START(CM41XX, "OpenGear/CM41xx")
+        /* OpenGear Inc. */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = og_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_IM4004
+MACHINE_START(IM4004, "OpenGear/IM4004")
+        /* OpenGear Inc. */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = og_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_IM42xx
+MACHINE_START(IM42XX, "OpenGear/IM42xx")
+        /* OpenGear Inc. */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = og_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-ks8695/board-sg.c b/arch/arm/mach-ks8695/board-sg.c
new file mode 100644
index 000000000000..f35b98b5bf37
--- /dev/null
+++ b/arch/arm/mach-ks8695/board-sg.c
@@ -0,0 +1,121 @@
+/*
+ * board-sg.c -- support for the SnapGear KS8695 based boards
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/partitions.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/devices.h>
+#include "generic.h"
+/*
+ * The SG310 machine type is fitted with a conventional 8MB Strataflash
+ * device. Define its partitioning.
+ */
+#define FL_BASE         0x02000000
+#define FL_SIZE         SZ_8M
+static struct mtd_partition sg_mtd_partitions[] = {
+        [0] = {
+                .name   = "SnapGear Boot Loader",
+                .size   = SZ_128K,
+        },
+        [1] = {
+                .name   = "SnapGear non-volatile configuration",
+                .size   = SZ_512K,
+                .offset = SZ_256K,
+        },
+        [2] = {
+                .name   = "SnapGear image",
+                .offset = SZ_512K + SZ_256K,
+        },
+        [3] = {
+                .name   = "SnapGear StrataFlash",
+        },
+        [4] = {
+                .name   = "SnapGear Boot Tags",
+                .size   = SZ_128K,
+                .offset = SZ_128K,
+        },
+};
+static struct physmap_flash_data sg_mtd_pdata = {
+        .width          = 1,
+        .nr_parts       = ARRAY_SIZE(sg_mtd_partitions),
+        .parts          = sg_mtd_partitions,
+};
+static struct resource sg_mtd_resource[] = {
+        [0] = {
+                .start = FL_BASE,
+                .end   = FL_BASE + FL_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+static struct platform_device sg_mtd_device = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(sg_mtd_resource),
+        .resource       = sg_mtd_resource,
+        .dev            = {
+                .platform_data = &sg_mtd_pdata,
+        },
+};
+static void __init sg_init(void)
+{
+        ks8695_add_device_lan();
+        ks8695_add_device_wan();
+        if (machine_is_sg310())
+                platform_device_register(&sg_mtd_device);
+}
+#ifdef CONFIG_MACH_LITE300
+MACHINE_START(LITE300, "SecureComputing/SG300")
+        /* SnapGear */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = sg_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_SG310
+MACHINE_START(SG310, "McAfee/SG310")
+        /* SnapGear */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = sg_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_SE4200
+MACHINE_START(SE4200, "SecureComputing/SE4200")
+        /* SnapGear */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = sg_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-ks8695/cpu.c b/arch/arm/mach-ks8695/cpu.c
index 7f3f24053a00..ddb24222918e 100644
--- a/arch/arm/mach-ks8695/cpu.c
+++ b/arch/arm/mach-ks8695/cpu.c
@@ -36,7 +36,7 @@
 static struct __initdata map_desc ks8695_io_desc[] = {
        {
-                .virtual        = KS8695_IO_VA,
+                .virtual        = (unsigned long)KS8695_IO_VA,
                .pfn            = __phys_to_pfn(KS8695_IO_PA),
                .length         = KS8695_IO_SIZE,
                .type           = MT_DEVICE,
diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c
index 73bd63812878..47399bc3c024 100644
--- a/arch/arm/mach-ks8695/devices.c
+++ b/arch/arm/mach-ks8695/devices.c
@@ -182,27 +182,6 @@ static void __init ks8695_add_device_watchdog(void)
 }
-/* --------------------------------------------------------------------
- *  LEDs
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_LEDS)
-short ks8695_leds_cpu = -1;
-short ks8695_leds_timer = -1;
-void __init ks8695_init_leds(u8 cpu_led, u8 timer_led)
-{
-        /* Enable GPIO to access the LEDs */
-        gpio_direction_output(cpu_led, 1);
-        gpio_direction_output(timer_led, 1);
-        ks8695_leds_cpu   = cpu_led;
-        ks8695_leds_timer = timer_led;
-}
-#else
-void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) {}
-#endif
 /* -------------------------------------------------------------------- */
 /*
diff --git a/arch/arm/mach-ks8695/include/mach/devices.h b/arch/arm/mach-ks8695/include/mach/devices.h
index 85a3c9aa7d13..1e6594a0f297 100644
--- a/arch/arm/mach-ks8695/include/mach/devices.h
+++ b/arch/arm/mach-ks8695/include/mach/devices.h
@@ -18,11 +18,6 @@ extern void __init ks8695_add_device_wan(void);
 extern void __init ks8695_add_device_lan(void);
 extern void __init ks8695_add_device_hpna(void);
- /* LEDs */
-extern short ks8695_leds_cpu;
-extern short ks8695_leds_timer;
-extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led);
 /* PCI */
 #define KS8695_MODE_PCI         0
 #define KS8695_MODE_MINIPCI     1
diff --git a/arch/arm/mach-ks8695/include/mach/hardware.h b/arch/arm/mach-ks8695/include/mach/hardware.h
index 5e0c388143da..5090338c0db2 100644
--- a/arch/arm/mach-ks8695/include/mach/hardware.h
+++ b/arch/arm/mach-ks8695/include/mach/hardware.h
@@ -33,7 +33,7 @@
 * head debug code as the initial MMU setup only deals in L1 sections.
 */
 #define KS8695_IO_PA            0x03F00000
-#define KS8695_IO_VA            0xF0000000
+#define KS8695_IO_VA            IOMEM(0xF0000000)
 #define KS8695_IO_SIZE          SZ_1M
 #define KS8695_PCIMEM_PA        0x60000000
diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h
index f7e1b9bce345..95e731a7ed6a 100644
--- a/arch/arm/mach-ks8695/include/mach/memory.h
+++ b/arch/arm/mach-ks8695/include/mach/memory.h
@@ -34,7 +34,8 @@ extern struct bus_type platform_bus_type;
 #define __arch_dma_to_virt(dev, x)      ({ (void *) (is_lbus_device(dev) ? \
                                        __phys_to_virt(x) : __bus_to_virt(x)); })
 #define __arch_virt_to_dma(dev, x)      ({ is_lbus_device(dev) ? \
-                                        (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); })
+                                        (dma_addr_t)__virt_to_phys((unsigned long)x) \
+                                        : (dma_addr_t)__virt_to_bus(x); })
 #define __arch_pfn_to_dma(dev, pfn)     \
        ({ dma_addr_t __dma = __pfn_to_phys(pfn); \
           if (!is_lbus_device(dev)) \
diff --git a/arch/arm/mach-ks8695/include/mach/regs-timer.h b/arch/arm/mach-ks8695/include/mach/regs-timer.h
deleted file mode 100644
index e620cda99d2d..000000000000
--- a/arch/arm/mach-ks8695/include/mach/regs-timer.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * arch/arm/mach-ks8695/include/mach/regs-timer.h
- *
- * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * KS8695 - Timer registers and bit definitions.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef KS8695_TIMER_H
-#define KS8695_TIMER_H
-#define KS8695_TMR_OFFSET       (0xF0000 + 0xE400)
-#define KS8695_TMR_VA           (KS8695_IO_VA + KS8695_TMR_OFFSET)
-#define KS8695_TMR_PA           (KS8695_IO_PA + KS8695_TMR_OFFSET)
-/*
- * Timer registers
- */
-#define KS8695_TMCON            (0x00)          /* Timer Control Register */
-#define KS8695_T1TC             (0x04)          /* Timer 1 Timeout Count Register */
-#define KS8695_T0TC             (0x08)          /* Timer 0 Timeout Count Register */
-#define KS8695_T1PD             (0x0C)          /* Timer 1 Pulse Count Register */
-#define KS8695_T0PD             (0x10)          /* Timer 0 Pulse Count Register */
-/* Timer Control Register */
-#define TMCON_T1EN              (1 << 1)        /* Timer 1 Enable */
-#define TMCON_T0EN              (1 << 0)        /* Timer 0 Enable */
-/* Timer0 Timeout Counter Register */
-#define T0TC_WATCHDOG           (0xff)          /* Enable watchdog mode */
-#endif
diff --git a/arch/arm/mach-ks8695/include/mach/uncompress.h b/arch/arm/mach-ks8695/include/mach/uncompress.h
index 9495cb4d701a..8879d610308a 100644
--- a/arch/arm/mach-ks8695/include/mach/uncompress.h
+++ b/arch/arm/mach-ks8695/include/mach/uncompress.h
@@ -19,15 +19,15 @@
 static void putc(char c)
 {
-        while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
+        while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
                barrier();
-        __raw_writel(c, KS8695_UART_PA + KS8695_URTH);
+        __raw_writel(c, (void __iomem*)KS8695_UART_PA + KS8695_URTH);
 }
 static inline void flush(void)
 {
-        while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
+        while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
                barrier();
 }
diff --git a/arch/arm/mach-ks8695/leds.c b/arch/arm/mach-ks8695/leds.c
deleted file mode 100644
index 4bd707547293..000000000000
--- a/arch/arm/mach-ks8695/leds.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * LED driver for KS8695-based boards.
- *
- * Copyright (C) Andrew Victor
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <asm/leds.h>
-#include <mach/devices.h>
-static inline void ks8695_led_on(unsigned int led)
-{
-        gpio_set_value(led, 0);
-}
-static inline void ks8695_led_off(unsigned int led)
-{
-        gpio_set_value(led, 1);
-}
-static inline void ks8695_led_toggle(unsigned int led)
-{
-        unsigned long is_off = gpio_get_value(led);
-        if (is_off)
-                ks8695_led_on(led);
-        else
-                ks8695_led_off(led);
-}
-/*
- * Handle LED events.
- */
-static void ks8695_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        switch(evt) {
-        case led_start:         /* System startup */
-                ks8695_led_on(ks8695_leds_cpu);
-                break;
-        case led_stop:          /* System stop / suspend */
-                ks8695_led_off(ks8695_leds_cpu);
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:         /* Every 50 timer ticks */
-                ks8695_led_toggle(ks8695_leds_timer);
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:    /* Entering idle state */
-                ks8695_led_off(ks8695_leds_cpu);
-                break;
-        case led_idle_end:      /* Exit idle state */
-                ks8695_led_on(ks8695_leds_cpu);
-                break;
-#endif
-        default:
-                break;
-        }
-        local_irq_restore(flags);
-}
-static int __init leds_init(void)
-{
-        if ((ks8695_leds_timer == -1) || (ks8695_leds_cpu == -1))
-                return -ENODEV;
-        leds_event = ks8695_leds_event;
-        leds_event(led_start);
-        return 0;
-}
-__initcall(leds_init);
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index ec783a3070ae..46c84bc7792c 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -25,53 +25,98 @@
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/io.h>
+#include <linux/clockchips.h>
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
-#include <mach/regs-timer.h>
 #include <mach/regs-irq.h>
 #include "generic.h"
+#define KS8695_TMR_OFFSET       (0xF0000 + 0xE400)
+#define KS8695_TMR_VA           (KS8695_IO_VA + KS8695_TMR_OFFSET)
+#define KS8695_TMR_PA           (KS8695_IO_PA + KS8695_TMR_OFFSET)
 /*
- * Returns number of ms since last clock interrupt.  Note that interrupts
+ * Timer registers
- * will have been disabled by do_gettimeoffset()
 */
-static unsigned long ks8695_gettimeoffset (void)
+#define KS8695_TMCON            (0x00)          /* Timer Control Register */
+#define KS8695_T1TC             (0x04)          /* Timer 1 Timeout Count Register */
+#define KS8695_T0TC             (0x08)          /* Timer 0 Timeout Count Register */
+#define KS8695_T1PD             (0x0C)          /* Timer 1 Pulse Count Register */
+#define KS8695_T0PD             (0x10)          /* Timer 0 Pulse Count Register */
+/* Timer Control Register */
+#define TMCON_T1EN              (1 << 1)        /* Timer 1 Enable */
+#define TMCON_T0EN              (1 << 0)        /* Timer 0 Enable */
+/* Timer0 Timeout Counter Register */
+#define T0TC_WATCHDOG           (0xff)          /* Enable watchdog mode */
+static void ks8695_set_mode(enum clock_event_mode mode,
+                            struct clock_event_device *evt)
 {
-        unsigned long elapsed, tick2, intpending;
+        u32 tmcon;
-        /*
+        if (mode == CLOCK_EVT_FEAT_PERIODIC) {
-         * Get the current number of ticks.  Note that there is a race
+                u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
-         * condition between us reading the timer and checking for an
+                u32 half = DIV_ROUND_CLOSEST(rate, 2);
-         * interrupt.  We solve this by ensuring that the counter has not
-         * reloaded between our two reads.
+                /* Disable timer 1 */
-         */
+                tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
-        elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
+                tmcon &= ~TMCON_T1EN;
-        do {
+                writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
-                tick2 = elapsed;
-                intpending = __raw_readl(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1);
+                /* Both registers need to count down */
-                elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
+                writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
-        } while (elapsed > tick2);
+                writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
-        /* Convert to number of ticks expired (not remaining) */
+                /* Re-enable timer1 */
-        elapsed = (CLOCK_TICK_RATE / HZ) - elapsed;
+                tmcon |= TMCON_T1EN;
+                writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
-        /* Is interrupt pending?  If so, then timer has been reloaded already. */
+        }
-        if (intpending)
-                elapsed += (CLOCK_TICK_RATE / HZ);
-        /* Convert ticks to usecs */
-        return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
 }
+static int ks8695_set_next_event(unsigned long cycles,
+                                 struct clock_event_device *evt)
+{
+        u32 half = DIV_ROUND_CLOSEST(cycles, 2);
+        u32 tmcon;
+        /* Disable timer 1 */
+        tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+        tmcon &= ~TMCON_T1EN;
+        writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+        /* Both registers need to count down */
+        writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
+        writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
+        /* Re-enable timer1 */
+        tmcon |= TMCON_T1EN;
+        writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+        return 0;
+}
+static struct clock_event_device clockevent_ks8695 = {
+        .name           = "ks8695_t1tc",
+        .rating         = 300, /* Reasonably fast and accurate clock event */
+        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+        .set_next_event = ks8695_set_next_event,
+        .set_mode       = ks8695_set_mode,
+};
 /*
 * IRQ handler for the timer.
 */
 static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
 {
-        timer_tick();
+        struct clock_event_device *evt = &clockevent_ks8695;
+        evt->event_handler(evt);
        return IRQ_HANDLED;
 }
@@ -83,18 +128,22 @@ static struct irqaction ks8695_timer_irq = {
 static void ks8695_timer_setup(void)
 {
-        unsigned long tmout = CLOCK_TICK_RATE / HZ;
        unsigned long tmcon;
-        /* disable timer1 */
+        /* Disable timer 0 and 1 */
-        tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
+        tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
-        __raw_writel(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
+        tmcon &= ~TMCON_T0EN;
+        tmcon &= ~TMCON_T1EN;
-        __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1TC);
+        writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
-        __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1PD);
-        /* re-enable timer1 */
+        /*
-        __raw_writel(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
+         * Use timer 1 to fire IRQs on the timeline, minimum 2 cycles
+         * (one on each counter) maximum 2*2^32, but the API will only
+         * accept up to a 32bit full word (0xFFFFFFFFU).
+         */
+        clockevents_config_and_register(&clockevent_ks8695,
+                                        KS8695_CLOCK_RATE, 2,
+                                        0xFFFFFFFFU);
 }
 static void __init ks8695_timer_init (void)
@@ -107,8 +156,6 @@ static void __init ks8695_timer_init (void)
 struct sys_timer ks8695_timer = {
        .init           = ks8695_timer_init,
-        .offset         = ks8695_gettimeoffset,
-        .resume         = ks8695_timer_setup,
 };
 void ks8695_restart(char mode, const char *cmd)
@@ -119,12 +166,12 @@ void ks8695_restart(char mode, const char *cmd)
                soft_restart(0);
        /* disable timer0 */
-        reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
+        reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
-        __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+        writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
        /* enable watchdog mode */
-        __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
+        writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
        /* re-enable timer0 */
-        __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+        writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
 }
diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot
index 697323b5f92d..d7392a475247 100644
--- a/arch/arm/mach-lpc32xx/Makefile.boot
+++ b/arch/arm/mach-lpc32xx/Makefile.boot
@@ -1,5 +1,3 @@
   zreladdr-y   += 0x80008000
 params_phys-y   := 0x80000100
 initrd_phys-y   := 0x82000000
-dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index a48dc2dec485..0d4db8c544b5 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -177,25 +177,25 @@ u32 clk_get_pclk_div(void)
 static struct map_desc lpc32xx_io_desc[] __initdata = {
        {
-                .virtual        = IO_ADDRESS(LPC32XX_AHB0_START),
+                .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
                .pfn            = __phys_to_pfn(LPC32XX_AHB0_START),
                .length         = LPC32XX_AHB0_SIZE,
                .type           = MT_DEVICE
        },
        {
-                .virtual        = IO_ADDRESS(LPC32XX_AHB1_START),
+                .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START),
                .pfn            = __phys_to_pfn(LPC32XX_AHB1_START),
                .length         = LPC32XX_AHB1_SIZE,
                .type           = MT_DEVICE
        },
        {
-                .virtual        = IO_ADDRESS(LPC32XX_FABAPB_START),
+                .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START),
                .pfn            = __phys_to_pfn(LPC32XX_FABAPB_START),
                .length         = LPC32XX_FABAPB_SIZE,
                .type           = MT_DEVICE
        },
        {
-                .virtual        = IO_ADDRESS(LPC32XX_IRAM_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE),
                .pfn            = __phys_to_pfn(LPC32XX_IRAM_BASE),
                .length         = (LPC32XX_IRAM_BANK_SIZE * 2),
                .type           = MT_DEVICE
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h b/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
index 1816e22a3479..a544e962a818 100644
--- a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
@@ -30,7 +30,7 @@
 #define LPC32XX_GPIO_P1_MAX 24
 #define LPC32XX_GPIO_P2_MAX 13
 #define LPC32XX_GPIO_P3_MAX 6
-#define LPC32XX_GPI_P3_MAX 28
+#define LPC32XX_GPI_P3_MAX 29
 #define LPC32XX_GPO_P3_MAX 24
 #define LPC32XX_GPIO_P0_GRP 0
diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h
index 33e1dde37bd9..69065de97a3d 100644
--- a/arch/arm/mach-lpc32xx/include/mach/hardware.h
+++ b/arch/arm/mach-lpc32xx/include/mach/hardware.h
@@ -25,7 +25,7 @@
 /*
 * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
 */
-#define IO_ADDRESS(x)   (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
+#define IO_ADDRESS(x)   IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
                         IO_BASE)
 #define io_p2v(x)       ((void __iomem *) (unsigned long) IO_ADDRESS(x))
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 5b1cc35e6fba..3c6332753358 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -283,21 +283,25 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
        case IRQ_TYPE_EDGE_RISING:
                /* Rising edge sensitive */
                __lpc32xx_set_irq_type(d->hwirq, 1, 1);
+                __irq_set_handler_locked(d->hwirq, handle_edge_irq);
                break;
        case IRQ_TYPE_EDGE_FALLING:
                /* Falling edge sensitive */
                __lpc32xx_set_irq_type(d->hwirq, 0, 1);
+                __irq_set_handler_locked(d->hwirq, handle_edge_irq);
                break;
        case IRQ_TYPE_LEVEL_LOW:
                /* Low level sensitive */
                __lpc32xx_set_irq_type(d->hwirq, 0, 0);
+                __irq_set_handler_locked(d->hwirq, handle_level_irq);
                break;
        case IRQ_TYPE_LEVEL_HIGH:
                /* High level sensitive */
                __lpc32xx_set_irq_type(d->hwirq, 1, 0);
+                __irq_set_handler_locked(d->hwirq, handle_level_irq);
                break;
        /* Other modes are not supported */
@@ -305,9 +309,6 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
                return -EINVAL;
        }
-        /* Ok to use the level handler for all types */
-        irq_set_handler(d->hwirq, handle_level_irq);
        return 0;
 }
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index b07dcc90829d..e8ff4c3f0566 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -24,12 +24,9 @@
 #include <linux/irq.h>
 #include <linux/dma-mapping.h>
 #include <linux/device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/eeprom.h>
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
-#include <linux/amba/pl022.h>
 #include <linux/amba/pl08x.h>
 #include <linux/amba/mmci.h>
 #include <linux/of.h>
@@ -37,6 +34,8 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/clk.h>
+#include <linux/mtd/lpc32xx_slc.h>
+#include <linux/mtd/lpc32xx_mlc.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -156,21 +155,6 @@ static struct clcd_board lpc32xx_clcd_data = {
        .remove         = lpc32xx_clcd_remove,
 };
-/*
- * AMBA SSP (SPI)
- */
-static struct pl022_ssp_controller lpc32xx_ssp0_data = {
-        .bus_id                 = 0,
-        .num_chipselect         = 1,
-        .enable_dma             = 0,
-};
-static struct pl022_ssp_controller lpc32xx_ssp1_data = {
-        .bus_id                 = 1,
-        .num_chipselect         = 1,
-        .enable_dma             = 0,
-};
 static struct pl08x_channel_data pl08x_slave_channels[] = {
        {
                .bus_id = "nand-slc",
@@ -223,13 +207,25 @@ static struct mmci_platform_data lpc32xx_mmci_data = {
         * gather, and the MMCI driver doesn't do it this way */
 };
+static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
+        .dma_filter = pl08x_filter_id,
+};
+static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
+        .dma_filter = pl08x_filter_id,
+};
 static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
+        OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL),
-        OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
+        OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL),
        OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
        OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
        OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
                       &lpc32xx_mmci_data),
+        OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
+                       &lpc32xx_slc_data),
+        OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
+                       &lpc32xx_mlc_data),
        { }
 };
@@ -253,12 +249,6 @@ static void __init lpc3250_machine_init(void)
        of_platform_populate(NULL, of_default_bus_match_table,
                             lpc32xx_auxdata_lookup, NULL);
-        /* Register GPIOs used on this board */
-        if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
-                pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO);
-        else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
-                pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO);
 }
 static char const *lpc32xx_dt_compat[] __initdata = {
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 7fddd01b85b9..d697d07a1bf0 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -108,18 +108,21 @@ endmenu
 config CPU_PXA168
        bool
        select CPU_MOHAWK
+        select COMMON_CLK
        help
          Select code specific to PXA168
 config CPU_PXA910
        bool
        select CPU_MOHAWK
+        select COMMON_CLK
        help
          Select code specific to PXA910
 config CPU_MMP2
        bool
        select CPU_PJ4
+        select COMMON_CLK
        help
          Select code specific to MMP2. MMP2 is ARMv7 compatible.
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index b786f7e6cd1f..095c155d6fb8 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,13 +2,19 @@
 # Makefile for Marvell's PXA168 processors line
 #
-obj-y                           += common.o clock.o devices.o time.o irq.o
+obj-y                           += common.o devices.o time.o irq.o
 # SoC support
 obj-$(CONFIG_CPU_PXA168)        += pxa168.o
 obj-$(CONFIG_CPU_PXA910)        += pxa910.o
 obj-$(CONFIG_CPU_MMP2)          += mmp2.o sram.o
+ifeq ($(CONFIG_COMMON_CLK), )
+obj-y                           += clock.o
+obj-$(CONFIG_CPU_PXA168)        += clock-pxa168.o
+obj-$(CONFIG_CPU_PXA910)        += clock-pxa910.o
+obj-$(CONFIG_CPU_MMP2)          += clock-mmp2.o
+endif
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_CPU_PXA910)        += pm-pxa910.o
 obj-$(CONFIG_CPU_MMP2)          += pm-mmp2.o
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 223090b1444d..e5dba9c5dc54 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -27,7 +27,7 @@
 #include <mach/irqs.h>
 #include <video/pxa168fb.h>
 #include <linux/input.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include "common.h"
diff --git a/arch/arm/mach-mmp/clock-mmp2.c b/arch/arm/mach-mmp/clock-mmp2.c
new file mode 100644
index 000000000000..21d22002cd19
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-mmp2.c
@@ -0,0 +1,111 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <mach/addr-map.h>
+#include "common.h"
+#include "clock.h"
+/*
+ * APB Clock register offsets for MMP2
+ */
+#define APBC_RTC        APBC_REG(0x000)
+#define APBC_TWSI1      APBC_REG(0x004)
+#define APBC_TWSI2      APBC_REG(0x008)
+#define APBC_TWSI3      APBC_REG(0x00c)
+#define APBC_TWSI4      APBC_REG(0x010)
+#define APBC_KPC        APBC_REG(0x018)
+#define APBC_UART1      APBC_REG(0x02c)
+#define APBC_UART2      APBC_REG(0x030)
+#define APBC_UART3      APBC_REG(0x034)
+#define APBC_GPIO       APBC_REG(0x038)
+#define APBC_PWM0       APBC_REG(0x03c)
+#define APBC_PWM1       APBC_REG(0x040)
+#define APBC_PWM2       APBC_REG(0x044)
+#define APBC_PWM3       APBC_REG(0x048)
+#define APBC_SSP0       APBC_REG(0x04c)
+#define APBC_SSP1       APBC_REG(0x050)
+#define APBC_SSP2       APBC_REG(0x054)
+#define APBC_SSP3       APBC_REG(0x058)
+#define APBC_SSP4       APBC_REG(0x05c)
+#define APBC_SSP5       APBC_REG(0x060)
+#define APBC_TWSI5      APBC_REG(0x07c)
+#define APBC_TWSI6      APBC_REG(0x080)
+#define APBC_UART4      APBC_REG(0x088)
+#define APMU_USB        APMU_REG(0x05c)
+#define APMU_NAND       APMU_REG(0x060)
+#define APMU_SDH0       APMU_REG(0x054)
+#define APMU_SDH1       APMU_REG(0x058)
+#define APMU_SDH2       APMU_REG(0x0e8)
+#define APMU_SDH3       APMU_REG(0x0ec)
+static void sdhc_clk_enable(struct clk *clk)
+{
+        uint32_t clk_rst;
+        clk_rst  =  __raw_readl(clk->clk_rst);
+        clk_rst |= clk->enable_val;
+        __raw_writel(clk_rst, clk->clk_rst);
+}
+static void sdhc_clk_disable(struct clk *clk)
+{
+        uint32_t clk_rst;
+        clk_rst  =  __raw_readl(clk->clk_rst);
+        clk_rst &= ~clk->enable_val;
+        __raw_writel(clk_rst, clk->clk_rst);
+}
+struct clkops sdhc_clk_ops = {
+        .enable         = sdhc_clk_enable,
+        .disable        = sdhc_clk_disable,
+};
+/* APB peripheral clocks */
+static APBC_CLK(uart1, UART1, 1, 26000000);
+static APBC_CLK(uart2, UART2, 1, 26000000);
+static APBC_CLK(uart3, UART3, 1, 26000000);
+static APBC_CLK(uart4, UART4, 1, 26000000);
+static APBC_CLK(twsi1, TWSI1, 0, 26000000);
+static APBC_CLK(twsi2, TWSI2, 0, 26000000);
+static APBC_CLK(twsi3, TWSI3, 0, 26000000);
+static APBC_CLK(twsi4, TWSI4, 0, 26000000);
+static APBC_CLK(twsi5, TWSI5, 0, 26000000);
+static APBC_CLK(twsi6, TWSI6, 0, 26000000);
+static APBC_CLK(gpio, GPIO, 0, 26000000);
+static APMU_CLK(nand, NAND, 0xbf, 100000000);
+static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
+static struct clk_lookup mmp2_clkregs[] = {
+        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+        INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
+        INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
+        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
+        INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
+        INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
+        INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
+        INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
+        INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
+        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
+};
+void __init mmp2_clk_init(void)
+{
+        clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
+}
diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c
new file mode 100644
index 000000000000..5e6c18ccebd4
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-pxa168.c
@@ -0,0 +1,91 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <mach/addr-map.h>
+#include "common.h"
+#include "clock.h"
+/*
+ * APB clock register offsets for PXA168
+ */
+#define APBC_UART1      APBC_REG(0x000)
+#define APBC_UART2      APBC_REG(0x004)
+#define APBC_GPIO       APBC_REG(0x008)
+#define APBC_PWM1       APBC_REG(0x00c)
+#define APBC_PWM2       APBC_REG(0x010)
+#define APBC_PWM3       APBC_REG(0x014)
+#define APBC_PWM4       APBC_REG(0x018)
+#define APBC_RTC        APBC_REG(0x028)
+#define APBC_TWSI0      APBC_REG(0x02c)
+#define APBC_KPC        APBC_REG(0x030)
+#define APBC_TWSI1      APBC_REG(0x06c)
+#define APBC_UART3      APBC_REG(0x070)
+#define APBC_SSP1       APBC_REG(0x81c)
+#define APBC_SSP2       APBC_REG(0x820)
+#define APBC_SSP3       APBC_REG(0x84c)
+#define APBC_SSP4       APBC_REG(0x858)
+#define APBC_SSP5       APBC_REG(0x85c)
+#define APMU_NAND       APMU_REG(0x060)
+#define APMU_LCD        APMU_REG(0x04c)
+#define APMU_ETH        APMU_REG(0x0fc)
+#define APMU_USB        APMU_REG(0x05c)
+/* APB peripheral clocks */
+static APBC_CLK(uart1, UART1, 1, 14745600);
+static APBC_CLK(uart2, UART2, 1, 14745600);
+static APBC_CLK(uart3, UART3, 1, 14745600);
+static APBC_CLK(twsi0, TWSI0, 1, 33000000);
+static APBC_CLK(twsi1, TWSI1, 1, 33000000);
+static APBC_CLK(pwm1, PWM1, 1, 13000000);
+static APBC_CLK(pwm2, PWM2, 1, 13000000);
+static APBC_CLK(pwm3, PWM3, 1, 13000000);
+static APBC_CLK(pwm4, PWM4, 1, 13000000);
+static APBC_CLK(ssp1, SSP1, 4, 0);
+static APBC_CLK(ssp2, SSP2, 4, 0);
+static APBC_CLK(ssp3, SSP3, 4, 0);
+static APBC_CLK(ssp4, SSP4, 4, 0);
+static APBC_CLK(ssp5, SSP5, 4, 0);
+static APBC_CLK(gpio, GPIO, 0, 13000000);
+static APBC_CLK(keypad, KPC, 0, 32000);
+static APBC_CLK(rtc, RTC, 8, 32768);
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
+static APMU_CLK(lcd, LCD, 0x7f, 312000000);
+static APMU_CLK(eth, ETH, 0x09, 0);
+static APMU_CLK(usb, USB, 0x12, 0);
+/* device and clock bindings */
+static struct clk_lookup pxa168_clkregs[] = {
+        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+        INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
+        INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
+        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
+        INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
+        INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
+        INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
+        INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
+        INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
+        INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
+        INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
+        INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
+        INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
+        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
+        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
+        INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
+        INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
+        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
+};
+void __init pxa168_clk_init(void)
+{
+        clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
+}
diff --git a/arch/arm/mach-mmp/clock-pxa910.c b/arch/arm/mach-mmp/clock-pxa910.c
new file mode 100644
index 000000000000..933ea71d0b56
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-pxa910.c
@@ -0,0 +1,67 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <mach/addr-map.h>
+#include "common.h"
+#include "clock.h"
+/*
+ * APB Clock register offsets for PXA910
+ */
+#define APBC_UART0      APBC_REG(0x000)
+#define APBC_UART1      APBC_REG(0x004)
+#define APBC_GPIO       APBC_REG(0x008)
+#define APBC_PWM1       APBC_REG(0x00c)
+#define APBC_PWM2       APBC_REG(0x010)
+#define APBC_PWM3       APBC_REG(0x014)
+#define APBC_PWM4       APBC_REG(0x018)
+#define APBC_SSP1       APBC_REG(0x01c)
+#define APBC_SSP2       APBC_REG(0x020)
+#define APBC_RTC        APBC_REG(0x028)
+#define APBC_TWSI0      APBC_REG(0x02c)
+#define APBC_KPC        APBC_REG(0x030)
+#define APBC_SSP3       APBC_REG(0x04c)
+#define APBC_TWSI1      APBC_REG(0x06c)
+#define APMU_NAND       APMU_REG(0x060)
+#define APMU_USB        APMU_REG(0x05c)
+static APBC_CLK(uart1, UART0, 1, 14745600);
+static APBC_CLK(uart2, UART1, 1, 14745600);
+static APBC_CLK(twsi0, TWSI0, 1, 33000000);
+static APBC_CLK(twsi1, TWSI1, 1, 33000000);
+static APBC_CLK(pwm1, PWM1, 1, 13000000);
+static APBC_CLK(pwm2, PWM2, 1, 13000000);
+static APBC_CLK(pwm3, PWM3, 1, 13000000);
+static APBC_CLK(pwm4, PWM4, 1, 13000000);
+static APBC_CLK(gpio, GPIO, 0, 13000000);
+static APBC_CLK(rtc, RTC, 8, 32768);
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
+static APMU_CLK(u2o, USB, 0x1b, 480000000);
+/* device and clock bindings */
+static struct clk_lookup pxa910_clkregs[] = {
+        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+        INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
+        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
+        INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
+        INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
+        INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
+        INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
+        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
+        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
+};
+void __init pxa910_clk_init(void)
+{
+        clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
+}
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 1c9d6c1ea97a..bd453274fca2 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -7,3 +7,6 @@ extern void timer_init(int irq);
 extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
 extern void mmp_restart(char, const char *);
+extern void __init pxa168_clk_init(void);
+extern void __init pxa910_clk_init(void);
+extern void __init mmp2_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
index b6f14d203c25..5c3cc29688ab 100644
--- a/arch/arm/mach-mmp/include/mach/debug-macro.S
+++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
@@ -9,13 +9,21 @@
 * published by the Free Software Foundation.
 */
+#if defined(CONFIG_DEBUG_MMP_UART2)
+#define MMP_UART_OFFSET 0x00017000
+#elif defined(CONFIG_DEBUG_MMP_UART3)
+#define MMP_UART_OFFSET 0x00018000
+#else
+#error "Select uart for DEBUG_LL"
+#endif
 #include <mach/addr-map.h>
                .macro  addruart, rp, rv, tmp
                ldr     \rp, =APB_PHYS_BASE             @ physical
                ldr     \rv, =APB_VIRT_BASE             @ virtual
-                orr     \rp, \rp, #0x00017000
+                orr     \rp, \rp, #MMP_UART_OFFSET
-                orr     \rv, \rv, #0x00017000
+                orr     \rv, \rv, #MMP_UART_OFFSET
                .endm
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h
index cba22fed2265..c4ca4d17194a 100644
--- a/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -13,7 +13,7 @@ extern void mmp2_clear_pmic_int(void);
 #include <linux/i2c.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <mach/devices.h>
-#include <mach/sram.h>
+#include <linux/platform_data/dma-mmp_tdma.h>
 extern struct pxa_device_desc mmp2_device_uart1;
 extern struct pxa_device_desc mmp2_device_uart2;
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 09dcd6e2b6a8..37632d964d50 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -11,9 +11,9 @@ extern void pxa168_clear_keypad_wakeup(void);
 #include <linux/i2c.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <mach/devices.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 #include <video/pxa168fb.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/cputype.h>
 #include <linux/pxa168_eth.h>
 #include <linux/platform_data/mv_usb.h>
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index 793634c837ef..3b58a3b2d7df 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -9,7 +9,7 @@ extern void __init pxa910_init_irq(void);
 #include <linux/i2c.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <mach/devices.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 extern struct pxa_device_desc pxa910_device_uart1;
 extern struct pxa_device_desc pxa910_device_uart2;
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 68b0c93ec6a1..ddc812f40341 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -13,101 +13,6 @@
 #include <mach/addr-map.h>
-/*
- * APB clock register offsets for PXA168
- */
-#define APBC_PXA168_UART1       APBC_REG(0x000)
-#define APBC_PXA168_UART2       APBC_REG(0x004)
-#define APBC_PXA168_GPIO        APBC_REG(0x008)
-#define APBC_PXA168_PWM1        APBC_REG(0x00c)
-#define APBC_PXA168_PWM2        APBC_REG(0x010)
-#define APBC_PXA168_PWM3        APBC_REG(0x014)
-#define APBC_PXA168_PWM4        APBC_REG(0x018)
-#define APBC_PXA168_RTC         APBC_REG(0x028)
-#define APBC_PXA168_TWSI0       APBC_REG(0x02c)
-#define APBC_PXA168_KPC         APBC_REG(0x030)
-#define APBC_PXA168_TIMERS      APBC_REG(0x034)
-#define APBC_PXA168_AIB         APBC_REG(0x03c)
-#define APBC_PXA168_SW_JTAG     APBC_REG(0x040)
-#define APBC_PXA168_ONEWIRE     APBC_REG(0x048)
-#define APBC_PXA168_ASFAR       APBC_REG(0x050)
-#define APBC_PXA168_ASSAR       APBC_REG(0x054)
-#define APBC_PXA168_TWSI1       APBC_REG(0x06c)
-#define APBC_PXA168_UART3       APBC_REG(0x070)
-#define APBC_PXA168_AC97        APBC_REG(0x084)
-#define APBC_PXA168_SSP1        APBC_REG(0x81c)
-#define APBC_PXA168_SSP2        APBC_REG(0x820)
-#define APBC_PXA168_SSP3        APBC_REG(0x84c)
-#define APBC_PXA168_SSP4        APBC_REG(0x858)
-#define APBC_PXA168_SSP5        APBC_REG(0x85c)
-/*
- * APB Clock register offsets for PXA910
- */
-#define APBC_PXA910_UART0       APBC_REG(0x000)
-#define APBC_PXA910_UART1       APBC_REG(0x004)
-#define APBC_PXA910_GPIO        APBC_REG(0x008)
-#define APBC_PXA910_PWM1        APBC_REG(0x00c)
-#define APBC_PXA910_PWM2        APBC_REG(0x010)
-#define APBC_PXA910_PWM3        APBC_REG(0x014)
-#define APBC_PXA910_PWM4        APBC_REG(0x018)
-#define APBC_PXA910_SSP1        APBC_REG(0x01c)
-#define APBC_PXA910_SSP2        APBC_REG(0x020)
-#define APBC_PXA910_IPC         APBC_REG(0x024)
-#define APBC_PXA910_RTC         APBC_REG(0x028)
-#define APBC_PXA910_TWSI0       APBC_REG(0x02c)
-#define APBC_PXA910_KPC         APBC_REG(0x030)
-#define APBC_PXA910_TIMERS      APBC_REG(0x034)
-#define APBC_PXA910_TBROT       APBC_REG(0x038)
-#define APBC_PXA910_AIB         APBC_REG(0x03c)
-#define APBC_PXA910_SW_JTAG     APBC_REG(0x040)
-#define APBC_PXA910_TIMERS1     APBC_REG(0x044)
-#define APBC_PXA910_ONEWIRE     APBC_REG(0x048)
-#define APBC_PXA910_SSP3        APBC_REG(0x04c)
-#define APBC_PXA910_ASFAR       APBC_REG(0x050)
-#define APBC_PXA910_ASSAR       APBC_REG(0x054)
-/*
- * APB Clock register offsets for MMP2
- */
-#define APBC_MMP2_RTC           APBC_REG(0x000)
-#define APBC_MMP2_TWSI1         APBC_REG(0x004)
-#define APBC_MMP2_TWSI2         APBC_REG(0x008)
-#define APBC_MMP2_TWSI3         APBC_REG(0x00c)
-#define APBC_MMP2_TWSI4         APBC_REG(0x010)
-#define APBC_MMP2_ONEWIRE       APBC_REG(0x014)
-#define APBC_MMP2_KPC           APBC_REG(0x018)
-#define APBC_MMP2_TB_ROTARY     APBC_REG(0x01c)
-#define APBC_MMP2_SW_JTAG       APBC_REG(0x020)
-#define APBC_MMP2_TIMERS        APBC_REG(0x024)
-#define APBC_MMP2_UART1         APBC_REG(0x02c)
-#define APBC_MMP2_UART2         APBC_REG(0x030)
-#define APBC_MMP2_UART3         APBC_REG(0x034)
-#define APBC_MMP2_GPIO          APBC_REG(0x038)
-#define APBC_MMP2_PWM0          APBC_REG(0x03c)
-#define APBC_MMP2_PWM1          APBC_REG(0x040)
-#define APBC_MMP2_PWM2          APBC_REG(0x044)
-#define APBC_MMP2_PWM3          APBC_REG(0x048)
-#define APBC_MMP2_SSP0          APBC_REG(0x04c)
-#define APBC_MMP2_SSP1          APBC_REG(0x050)
-#define APBC_MMP2_SSP2          APBC_REG(0x054)
-#define APBC_MMP2_SSP3          APBC_REG(0x058)
-#define APBC_MMP2_SSP4          APBC_REG(0x05c)
-#define APBC_MMP2_SSP5          APBC_REG(0x060)
-#define APBC_MMP2_AIB           APBC_REG(0x064)
-#define APBC_MMP2_ASFAR         APBC_REG(0x068)
-#define APBC_MMP2_ASSAR         APBC_REG(0x06c)
-#define APBC_MMP2_USIM          APBC_REG(0x070)
-#define APBC_MMP2_MPMU          APBC_REG(0x074)
-#define APBC_MMP2_IPC           APBC_REG(0x078)
-#define APBC_MMP2_TWSI5         APBC_REG(0x07c)
-#define APBC_MMP2_TWSI6         APBC_REG(0x080)
-#define APBC_MMP2_TWSI_INTSTS   APBC_REG(0x084)
-#define APBC_MMP2_UART4         APBC_REG(0x088)
-#define APBC_MMP2_RIPC          APBC_REG(0x08c)
-#define APBC_MMP2_THSENS1       APBC_REG(0x090) /* Thermal Sensor */
-#define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4)
 /* Common APB clock register bit definitions */
 #define APBC_APBCLK     (1 << 0)  /* APB Bus Clock Enable */
 #define APBC_FNCLK      (1 << 1)  /* Functional Clock Enable */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 7af8deb63e83..93c8d0e29bb9 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -13,21 +13,6 @@
 #include <mach/addr-map.h>
-/* Clock Reset Control */
-#define APMU_IRE        APMU_REG(0x048)
-#define APMU_LCD        APMU_REG(0x04c)
-#define APMU_CCIC       APMU_REG(0x050)
-#define APMU_SDH0       APMU_REG(0x054)
-#define APMU_SDH1       APMU_REG(0x058)
-#define APMU_USB        APMU_REG(0x05c)
-#define APMU_NAND       APMU_REG(0x060)
-#define APMU_DMA        APMU_REG(0x064)
-#define APMU_GEU        APMU_REG(0x068)
-#define APMU_BUS        APMU_REG(0x06c)
-#define APMU_SDH2       APMU_REG(0x0e8)
-#define APMU_SDH3       APMU_REG(0x0ec)
-#define APMU_ETH        APMU_REG(0x0fc)
 #define APMU_FNCLK_EN   (1 << 4)
 #define APMU_AXICLK_EN  (1 << 3)
 #define APMU_FNRST_DIS  (1 << 1)
diff --git a/arch/arm/mach-mmp/include/mach/sram.h b/arch/arm/mach-mmp/include/mach/sram.h
deleted file mode 100644
index 239e0fc1bb1f..000000000000
--- a/arch/arm/mach-mmp/include/mach/sram.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *  linux/arch/arm/mach-mmp/include/mach/sram.h
- *
- *  SRAM Memory Management
- *
- *  Copyright (c) 2011 Marvell Semiconductors Inc.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- *
- */
-#ifndef __ASM_ARCH_SRAM_H
-#define __ASM_ARCH_SRAM_H
-#include <linux/genalloc.h>
-/* ARBITRARY:  SRAM allocations are multiples of this 2^N size */
-#define SRAM_GRANULARITY        512
-enum sram_type {
-        MMP_SRAM_UNDEFINED = 0,
-        MMP_ASRAM,
-        MMP_ISRAM,
-};
-struct sram_platdata {
-        char *pool_name;
-        int granularity;
-};
-extern struct gen_pool *sram_get_gpool(char *pool_name);
-#endif /* __ASM_ARCH_SRAM_H */
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c
index e60c7d98922b..3c71246cd994 100644
--- a/arch/arm/mach-mmp/irq.c
+++ b/arch/arm/mach-mmp/irq.c
@@ -153,10 +153,8 @@ static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
                status = readl_relaxed(data->reg_status) & ~mask;
                if (status == 0)
                        break;
-                n = find_first_bit(&status, BITS_PER_LONG);
+                for_each_set_bit(n, &status, BITS_PER_LONG) {
-                while (n < BITS_PER_LONG) {
                        generic_handle_irq(icu_data[i].virq_base + n);
-                        n = find_next_bit(&status, BITS_PER_LONG, n + 1);
                }
        }
 }
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index c709a24a9d25..3a3768c7a191 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -20,7 +20,6 @@
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
-#include <mach/regs-apmu.h>
 #include <mach/cputype.h>
 #include <mach/irqs.h>
 #include <mach/dma.h>
@@ -29,7 +28,6 @@
 #include <mach/mmp2.h>
 #include "common.h"
-#include "clock.h"
 #define MFPR_VIRT_BASE  (APB_VIRT_BASE + 0x1e000)
@@ -98,95 +96,36 @@ void __init mmp2_init_irq(void)
        mmp2_init_icu();
 }
-static void sdhc_clk_enable(struct clk *clk)
-{
-        uint32_t clk_rst;
-        clk_rst  =  __raw_readl(clk->clk_rst);
-        clk_rst |= clk->enable_val;
-        __raw_writel(clk_rst, clk->clk_rst);
-}
-static void sdhc_clk_disable(struct clk *clk)
-{
-        uint32_t clk_rst;
-        clk_rst  =  __raw_readl(clk->clk_rst);
-        clk_rst &= ~clk->enable_val;
-        __raw_writel(clk_rst, clk->clk_rst);
-}
-struct clkops sdhc_clk_ops = {
-        .enable         = sdhc_clk_enable,
-        .disable        = sdhc_clk_disable,
-};
-/* APB peripheral clocks */
-static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
-static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
-static APBC_CLK(uart3, MMP2_UART3, 1, 26000000);
-static APBC_CLK(uart4, MMP2_UART4, 1, 26000000);
-static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000);
-static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000);
-static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
-static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
-static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
-static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
-static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000);
-static APMU_CLK(nand, NAND, 0xbf, 100000000);
-static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
-static struct clk_lookup mmp2_clkregs[] = {
-        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
-        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
-        INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
-        INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
-        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
-        INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
-        INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
-        INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
-        INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
-        INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
-        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
-        INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
-        INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
-        INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
-        INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
-};
 static int __init mmp2_init(void)
 {
        if (cpu_is_mmp2()) {
 #ifdef CONFIG_CACHE_TAUROS2
-                tauros2_init();
+                tauros2_init(0);
 #endif
                mfp_init_base(MFPR_VIRT_BASE);
                mfp_init_addr(mmp2_addr_map);
                pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16);
-                clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
+                mmp2_clk_init();
        }
        return 0;
 }
 postcore_initcall(mmp2_init);
+#define APBC_TIMERS     APBC_REG(0x024)
 static void __init mmp2_timer_init(void)
 {
        unsigned long clk_rst;
-        __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS);
+        __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
        /*
         * enable bus/functional clock, enable 6.5MHz (divider 4),
         * release reset
         */
        clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
-        __raw_writel(clk_rst, APBC_MMP2_TIMERS);
+        __raw_writel(clk_rst, APBC_TIMERS);
        timer_init(IRQ_MMP2_TIMER1);
 }
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 62d787c34475..b7f074f15498 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -18,8 +18,8 @@
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
-#include <mach/addr-map.h>
 #include <mach/cputype.h>
+#include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
 #include <mach/regs-apmu.h>
 #include <mach/irqs.h>
@@ -50,62 +50,13 @@ void __init pxa168_init_irq(void)
        icu_init_irq();
 }
-/* APB peripheral clocks */
-static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
-static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
-static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
-static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
-static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
-static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
-static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
-static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
-static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
-static APBC_CLK(ssp1, PXA168_SSP1, 4, 0);
-static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
-static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
-static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
-static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
-static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
-static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
-static APBC_CLK(rtc, PXA168_RTC, 8, 32768);
-static APMU_CLK(nand, NAND, 0x19b, 156000000);
-static APMU_CLK(lcd, LCD, 0x7f, 312000000);
-static APMU_CLK(eth, ETH, 0x09, 0);
-static APMU_CLK(usb, USB, 0x12, 0);
-/* device and clock bindings */
-static struct clk_lookup pxa168_clkregs[] = {
-        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
-        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
-        INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
-        INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
-        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
-        INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
-        INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
-        INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
-        INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
-        INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
-        INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
-        INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
-        INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
-        INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
-        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-        INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
-        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
-        INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
-        INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
-        INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
-        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
-};
 static int __init pxa168_init(void)
 {
        if (cpu_is_pxa168()) {
                mfp_init_base(MFPR_VIRT_BASE);
                mfp_init_addr(pxa168_mfp_addr_map);
                pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
-                clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
+                pxa168_clk_init();
        }
        return 0;
@@ -114,6 +65,7 @@ postcore_initcall(pxa168_init);
 /* system timer - clock enabled, 3.25MHz */
 #define TIMER_CLK_RST   (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
+#define APBC_TIMERS     APBC_REG(0x34)
 static void __init pxa168_timer_init(void)
 {
@@ -121,10 +73,10 @@ static void __init pxa168_timer_init(void)
         * ourselves instead of using clk_* API. Clock rate is defined
         * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
         */
-        __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS);
+        __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
        /* 3.25MHz, bus/functional clock enabled, release reset */
-        __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS);
+        __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
        timer_init(IRQ_PXA168_TIMER1);
 }
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 6da52e9f2bdc..8b1e16fbb7a5 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -14,10 +14,10 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <asm/hardware/cache-tauros2.h>
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
-#include <mach/regs-apmu.h>
 #include <mach/cputype.h>
 #include <mach/irqs.h>
 #include <mach/dma.h>
@@ -25,7 +25,6 @@
 #include <mach/devices.h>
 #include "common.h"
-#include "clock.h"
 #define MFPR_VIRT_BASE  (APB_VIRT_BASE + 0x1e000)
@@ -82,44 +81,16 @@ void __init pxa910_init_irq(void)
        icu_init_irq();
 }
-/* APB peripheral clocks */
-static APBC_CLK(uart1, PXA910_UART0, 1, 14745600);
-static APBC_CLK(uart2, PXA910_UART1, 1, 14745600);
-static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
-static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
-static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000);
-static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
-static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
-static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
-static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000);
-static APBC_CLK(rtc, PXA910_RTC, 8, 32768);
-static APMU_CLK(nand, NAND, 0x19b, 156000000);
-static APMU_CLK(u2o, USB, 0x1b, 480000000);
-/* device and clock bindings */
-static struct clk_lookup pxa910_clkregs[] = {
-        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
-        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
-        INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
-        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
-        INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
-        INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
-        INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
-        INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
-        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
-        INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
-        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
-};
 static int __init pxa910_init(void)
 {
        if (cpu_is_pxa910()) {
+#ifdef CONFIG_CACHE_TAUROS2
+                tauros2_init(0);
+#endif
                mfp_init_base(MFPR_VIRT_BASE);
                mfp_init_addr(pxa910_mfp_addr_map);
                pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
-                clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
+                pxa910_clk_init();
        }
        return 0;
@@ -128,12 +99,13 @@ postcore_initcall(pxa910_init);
 /* system timer - clock enabled, 3.25MHz */
 #define TIMER_CLK_RST   (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
+#define APBC_TIMERS     APBC_REG(0x34)
 static void __init pxa910_timer_init(void)
 {
        /* reset and configure */
-        __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS);
+        __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
-        __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS);
+        __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
        timer_init(IRQ_PXA910_AP1_TIMER1);
 }
diff --git a/arch/arm/mach-mmp/sram.c b/arch/arm/mach-mmp/sram.c
index 7e8a5a2e1ec7..a6c08ede4491 100644
--- a/arch/arm/mach-mmp/sram.c
+++ b/arch/arm/mach-mmp/sram.c
@@ -22,7 +22,7 @@
 #include <linux/slab.h>
 #include <linux/genalloc.h>
-#include <mach/sram.h>
+#include <linux/platform_data/dma-mmp_tdma.h>
 struct sram_bank_info {
        char *pool_name;
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
index 42bef6674ecf..dd30ea74785c 100644
--- a/arch/arm/mach-mmp/teton_bga.c
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -17,7 +17,7 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <linux/i2c.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 7a7de2b12a62..ce55fd8821c4 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -177,12 +177,22 @@ static struct mv_usb_platform_data ttc_usb_pdata = {
 #endif
 #endif
+#ifdef CONFIG_MTD_NAND_PXA3xx
+static struct pxa3xx_nand_platform_data dkb_nand_info = {
+        .enable_arbiter = 1,
+        .num_cs = 1,
+};
+#endif
 static void __init ttc_dkb_init(void)
 {
        mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
        /* on-chip devices */
        pxa910_add_uart(1);
+#ifdef CONFIG_MTD_NAND_PXA3xx
+        pxa910_add_nand(&dkb_nand_info);
+#endif
        /* off-chip devices */
        pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 1cd40ad301d3..7902de151cc5 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1,8 +1,12 @@
 if ARCH_MSM
+comment "Qualcomm MSM SoC Type"
+        depends on (ARCH_MSM8X60 || ARCH_MSM8960)
 choice
        prompt "Qualcomm MSM SoC Type"
        default ARCH_MSM7X00A
+        depends on !(ARCH_MSM8X60 || ARCH_MSM8960)
 config ARCH_MSM7X00A
        bool "MSM7x00A / MSM7x01A"
@@ -36,10 +40,10 @@ config ARCH_QSD8X50
        select GPIO_MSM_V1
        select MSM_PROC_COMM
+endchoice
 config ARCH_MSM8X60
        bool "MSM8X60"
-        select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
-                                  && !MACH_MSM8X60_FFA)
        select ARCH_MSM_SCORPIONMP
        select ARM_GIC
        select CPU_V7
@@ -47,18 +51,17 @@ config ARCH_MSM8X60
        select GPIO_MSM_V2
        select MSM_GPIOMUX
        select MSM_SCM if SMP
+        select USE_OF
 config ARCH_MSM8960
        bool "MSM8960"
        select ARCH_MSM_SCORPIONMP
-        select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3)
        select ARM_GIC
        select CPU_V7
        select MSM_V2_TLMM
        select MSM_GPIOMUX
        select MSM_SCM if SMP
+        select USE_OF
-endchoice
 config MSM_HAS_DEBUG_UART_HS
        bool
@@ -112,42 +115,6 @@ config MACH_QSD8X50A_ST1_5
        help
          Support for the Qualcomm ST1.5.
-config MACH_MSM8X60_RUMI3
-        depends on ARCH_MSM8X60
-        bool "MSM8x60 RUMI3"
-        help
-          Support for the Qualcomm MSM8x60 RUMI3 emulator.
-config MACH_MSM8X60_SURF
-        depends on ARCH_MSM8X60
-        bool "MSM8x60 SURF"
-        help
-          Support for the Qualcomm MSM8x60 SURF eval board.
-config MACH_MSM8X60_SIM
-        depends on ARCH_MSM8X60
-        bool "MSM8x60 Simulator"
-        help
-          Support for the Qualcomm MSM8x60 simulator.
-config MACH_MSM8X60_FFA
-        depends on ARCH_MSM8X60
-        bool "MSM8x60 FFA"
-        help
-          Support for the Qualcomm MSM8x60 FFA eval board.
-config MACH_MSM8960_SIM
-        depends on ARCH_MSM8960
-        bool "MSM8960 Simulator"
-        help
-          Support for the Qualcomm MSM8960 simulator.
-config MACH_MSM8960_RUMI3
-        depends on ARCH_MSM8960
-        bool "MSM8960 RUMI3"
-        help
-          Support for the Qualcomm MSM8960 RUMI3 emulator.
 endmenu
 config MSM_SMD_PKG3
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 4ad3969b9881..17519faf082f 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,11 +1,11 @@
-obj-y += io.o idle.o timer.o
+obj-y += io.o timer.o
 obj-y += clock.o
 obj-$(CONFIG_DEBUG_FS) += clock-debug.o
 obj-$(CONFIG_MSM_VIC) += irq-vic.o
 obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
-obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
+obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o
 obj-$(CONFIG_ARCH_MSM7X30) += dma.o
 obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
@@ -25,8 +25,8 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o b
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
-obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
+obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o
-obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o
+obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o
 obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c
deleted file mode 100644
index 805d4ee53f7e..000000000000
--- a/arch/arm/mach-msm/acpuclock-arm11.c
+++ /dev/null
@@ -1,525 +0,0 @@
-/* arch/arm/mach-msm/acpuclock.c
- *
- * MSM architecture clock driver
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007 QUALCOMM Incorporated
- * Author: San Mehat <san@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/cpufreq.h>
-#include <linux/mutex.h>
-#include <linux/io.h>
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-#include "proc_comm.h"
-#include "acpuclock.h"
-#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
-#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
-#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
-/*
- * ARM11 clock configuration for specific ACPU speeds
- */
-#define ACPU_PLL_TCXO   -1
-#define ACPU_PLL_0      0
-#define ACPU_PLL_1      1
-#define ACPU_PLL_2      2
-#define ACPU_PLL_3      3
-#define PERF_SWITCH_DEBUG 0
-#define PERF_SWITCH_STEP_DEBUG 0
-struct clock_state
-{
-        struct clkctl_acpu_speed        *current_speed;
-        struct mutex                    lock;
-        uint32_t                        acpu_switch_time_us;
-        uint32_t                        max_speed_delta_khz;
-        uint32_t                        vdd_switch_time_us;
-        unsigned long                   power_collapse_khz;
-        unsigned long                   wait_for_irq_khz;
-};
-static struct clk *ebi1_clk;
-static struct clock_state drv_state = { 0 };
-static void __init acpuclk_init(void);
-/* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */
-enum {
-        VDD_0 = 0,
-        VDD_1 = 1,
-        VDD_2 = 2,
-        VDD_3 = 3,
-        VDD_4 = 3,
-        VDD_5 = 3,
-        VDD_6 = 3,
-        VDD_7 = 7,
-        VDD_END
-};
-struct clkctl_acpu_speed {
-        unsigned int    a11clk_khz;
-        int             pll;
-        unsigned int    a11clk_src_sel;
-        unsigned int    a11clk_src_div;
-        unsigned int    ahbclk_khz;
-        unsigned int    ahbclk_div;
-        int             vdd;
-        unsigned int    axiclk_khz;
-        unsigned long   lpj; /* loops_per_jiffy */
-/* Index in acpu_freq_tbl[] for steppings. */
-        short           down;
-        short           up;
-};
-/*
- * ACPU speed table. Complete table is shown but certain speeds are commented
- * out to optimized speed switching. Initialize loops_per_jiffy to 0.
- *
- * Table stepping up/down is optimized for 256mhz jumps while staying on the
- * same PLL.
- */
-#if (0)
-static struct clkctl_acpu_speed  acpu_freq_tbl[] = {
-        { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 },
-        { 61440, ACPU_PLL_0,  4, 3, 61440,  0, VDD_0, 30720,  0, 0, 8 },
-        { 81920, ACPU_PLL_0,  4, 2, 40960,  1, VDD_0, 61440,  0, 0, 8 },
-        { 96000, ACPU_PLL_1,  1, 7, 48000,  1, VDD_0, 61440,  0, 0, 9 },
-        { 122880, ACPU_PLL_0, 4, 1, 61440,  1, VDD_3, 61440,  0, 0, 8 },
-        { 128000, ACPU_PLL_1, 1, 5, 64000,  1, VDD_3, 61440,  0, 0, 12 },
-        { 176000, ACPU_PLL_2, 2, 5, 88000,  1, VDD_3, 61440,  0, 0, 11 },
-        { 192000, ACPU_PLL_1, 1, 3, 64000,  2, VDD_3, 61440,  0, 0, 12 },
-        { 245760, ACPU_PLL_0, 4, 0, 81920,  2, VDD_4, 61440,  0, 0, 12 },
-        { 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 },
-        { 264000, ACPU_PLL_2, 2, 3, 88000,  2, VDD_5, 128000, 0, 6, 13 },
-        { 352000, ACPU_PLL_2, 2, 2, 88000,  3, VDD_5, 128000, 0, 6, 13 },
-        { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 },
-        { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 },
-        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-};
-#else /* Table of freq we currently use. */
-static struct clkctl_acpu_speed  acpu_freq_tbl[] = {
-        { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 },
-        { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 },
-        { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 },
-        { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 },
-        { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 },
-        { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 },
-        { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 },
-        { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 },
-        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-};
-#endif
-#ifdef CONFIG_CPU_FREQ_TABLE
-static struct cpufreq_frequency_table freq_table[] = {
-        { 0, 122880 },
-        { 1, 128000 },
-        { 2, 245760 },
-        { 3, 384000 },
-        { 4, 528000 },
-        { 5, CPUFREQ_TABLE_END },
-};
-#endif
-static int pc_pll_request(unsigned id, unsigned on)
-{
-        int res;
-        on = !!on;
-#if PERF_SWITCH_DEBUG
-        if (on)
-                printk(KERN_DEBUG "Enabling PLL %d\n", id);
-        else
-                printk(KERN_DEBUG "Disabling PLL %d\n", id);
-#endif
-        res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on);
-        if (res < 0)
-                return res;
-#if PERF_SWITCH_DEBUG
-        if (on)
-                printk(KERN_DEBUG "PLL %d enabled\n", id);
-        else
-                printk(KERN_DEBUG "PLL %d disabled\n", id);
-#endif
-        return res;
-}
-/*----------------------------------------------------------------------------
- * ARM11 'owned' clock control
- *---------------------------------------------------------------------------*/
-unsigned long acpuclk_power_collapse(void) {
-        int ret = acpuclk_get_rate();
-        ret *= 1000;
-        if (ret > drv_state.power_collapse_khz)
-                acpuclk_set_rate(drv_state.power_collapse_khz, 1);
-        return ret;
-}
-unsigned long acpuclk_get_wfi_rate(void)
-{
-        return drv_state.wait_for_irq_khz;
-}
-unsigned long acpuclk_wait_for_irq(void) {
-        int ret = acpuclk_get_rate();
-        ret *= 1000;
-        if (ret > drv_state.wait_for_irq_khz)
-                acpuclk_set_rate(drv_state.wait_for_irq_khz, 1);
-        return ret;
-}
-static int acpuclk_set_vdd_level(int vdd)
-{
-        uint32_t current_vdd;
-        current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07;
-#if PERF_SWITCH_DEBUG
-        printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n",
-               current_vdd, vdd);
-#endif
-        writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR);
-        udelay(drv_state.vdd_switch_time_us);
-        if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) {
-#if PERF_SWITCH_DEBUG
-                printk(KERN_ERR "acpuclock: VDD set failed\n");
-#endif
-                return -EIO;
-        }
-#if PERF_SWITCH_DEBUG
-        printk(KERN_DEBUG "acpuclock: VDD switched\n");
-#endif
-        return 0;
-}
-/* Set proper dividers for the given clock speed. */
-static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) {
-        uint32_t reg_clkctl, reg_clksel, clk_div;
-        /* AHB_CLK_DIV */
-        clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03;
-        /*
-         * If the new clock divider is higher than the previous, then
-         * program the divider before switching the clock
-         */
-        if (hunt_s->ahbclk_div > clk_div) {
-                reg_clksel = readl(A11S_CLK_SEL_ADDR);
-                reg_clksel &= ~(0x3 << 1);
-                reg_clksel |= (hunt_s->ahbclk_div << 1);
-                writel(reg_clksel, A11S_CLK_SEL_ADDR);
-        }
-        if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) {
-                /* SRC0 */
-                /* Program clock source */
-                reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-                reg_clkctl &= ~(0x07 << 4);
-                reg_clkctl |= (hunt_s->a11clk_src_sel << 4);
-                writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-                /* Program clock divider */
-                reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-                reg_clkctl &= ~0xf;
-                reg_clkctl |= hunt_s->a11clk_src_div;
-                writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-                /* Program clock source selection */
-                reg_clksel = readl(A11S_CLK_SEL_ADDR);
-                reg_clksel |= 1; /* CLK_SEL_SRC1NO  == SRC1 */
-                writel(reg_clksel, A11S_CLK_SEL_ADDR);
-        } else {
-                /* SRC1 */
-                /* Program clock source */
-                reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-                reg_clkctl &= ~(0x07 << 12);
-                reg_clkctl |= (hunt_s->a11clk_src_sel << 12);
-                writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-                /* Program clock divider */
-                reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-                reg_clkctl &= ~(0xf << 8);
-                reg_clkctl |= (hunt_s->a11clk_src_div << 8);
-                writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-                /* Program clock source selection */
-                reg_clksel = readl(A11S_CLK_SEL_ADDR);
-                reg_clksel &= ~1; /* CLK_SEL_SRC1NO  == SRC0 */
-                writel(reg_clksel, A11S_CLK_SEL_ADDR);
-        }
-        /*
-         * If the new clock divider is lower than the previous, then
-         * program the divider after switching the clock
-         */
-        if (hunt_s->ahbclk_div < clk_div) {
-                reg_clksel = readl(A11S_CLK_SEL_ADDR);
-                reg_clksel &= ~(0x3 << 1);
-                reg_clksel |= (hunt_s->ahbclk_div << 1);
-                writel(reg_clksel, A11S_CLK_SEL_ADDR);
-        }
-}
-int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
-{
-        uint32_t reg_clkctl;
-        struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s;
-        int rc = 0;
-        unsigned int plls_enabled = 0, pll;
-        strt_s = cur_s = drv_state.current_speed;
-        WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n");
-        if (cur_s == NULL)
-                return -ENOENT;
-        if (rate == (cur_s->a11clk_khz * 1000))
-                return 0;
-        for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) {
-                if (tgt_s->a11clk_khz == (rate / 1000))
-                        break;
-        }
-        if (tgt_s->a11clk_khz == 0)
-                return -EINVAL;
-        /* Choose the highest speed speed at or below 'rate' with same PLL. */
-        if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) {
-                while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll)
-                        tgt_s--;
-        }
-        if (strt_s->pll != ACPU_PLL_TCXO)
-                plls_enabled |= 1 << strt_s->pll;
-        if (!for_power_collapse) {
-                mutex_lock(&drv_state.lock);
-                if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) {
-                        rc = pc_pll_request(tgt_s->pll, 1);
-                        if (rc < 0) {
-                                pr_err("PLL%d enable failed (%d)\n",
-                                        tgt_s->pll, rc);
-                                goto out;
-                        }
-                        plls_enabled |= 1 << tgt_s->pll;
-                }
-                /* Increase VDD if needed. */
-                if (tgt_s->vdd > cur_s->vdd) {
-                        if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) {
-                                printk(KERN_ERR "Unable to switch ACPU vdd\n");
-                                goto out;
-                        }
-                }
-        }
-        /* Set wait states for CPU between frequency changes */
-        reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-        reg_clkctl |= (100 << 16); /* set WT_ST_CNT */
-        writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-#if PERF_SWITCH_DEBUG
-        printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n",
-               strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000);
-#endif
-        while (cur_s != tgt_s) {
-                /*
-                 * Always jump to target freq if within 256mhz, regulardless of
-                 * PLL. If differnece is greater, use the predefinied
-                 * steppings in the table.
-                 */
-                int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz));
-                if (d > drv_state.max_speed_delta_khz) {
-                        /* Step up or down depending on target vs current. */
-                        int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ?
-                                cur_s->up : cur_s->down;
-                        if (clk_index < 0) { /* This should not happen. */
-                                printk(KERN_ERR "cur:%u target: %u\n",
-                                        cur_s->a11clk_khz, tgt_s->a11clk_khz);
-                                rc = -EINVAL;
-                                goto out;
-                        }
-                        cur_s = &acpu_freq_tbl[clk_index];
-                } else {
-                        cur_s = tgt_s;
-                }
-#if PERF_SWITCH_STEP_DEBUG
-                printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n",
-                        __FUNCTION__, cur_s->a11clk_khz, cur_s->pll);
-#endif
-                if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO
-                    && !(plls_enabled & (1 << cur_s->pll))) {
-                        rc = pc_pll_request(cur_s->pll, 1);
-                        if (rc < 0) {
-                                pr_err("PLL%d enable failed (%d)\n",
-                                        cur_s->pll, rc);
-                                goto out;
-                        }
-                        plls_enabled |= 1 << cur_s->pll;
-                }
-                acpuclk_set_div(cur_s);
-                drv_state.current_speed = cur_s;
-                /* Re-adjust lpj for the new clock speed. */
-                loops_per_jiffy = cur_s->lpj;
-                udelay(drv_state.acpu_switch_time_us);
-        }
-        /* Nothing else to do for power collapse. */
-        if (for_power_collapse)
-                return 0;
-        /* Disable PLLs we are not using anymore. */
-        plls_enabled &= ~(1 << tgt_s->pll);
-        for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++)
-                if (plls_enabled & (1 << pll)) {
-                        rc = pc_pll_request(pll, 0);
-                        if (rc < 0) {
-                                pr_err("PLL%d disable failed (%d)\n", pll, rc);
-                                goto out;
-                        }
-                }
-        /* Change the AXI bus frequency if we can. */
-        if (strt_s->axiclk_khz != tgt_s->axiclk_khz) {
-                rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000);
-                if (rc < 0)
-                        pr_err("Setting AXI min rate failed!\n");
-        }
-        /* Drop VDD level if we can. */
-        if (tgt_s->vdd < strt_s->vdd) {
-                if (acpuclk_set_vdd_level(tgt_s->vdd) < 0)
-                        printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n");
-        }
-#if PERF_SWITCH_DEBUG
-        printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__);
-#endif
-out:
-        if (!for_power_collapse)
-                mutex_unlock(&drv_state.lock);
-        return rc;
-}
-static void __init acpuclk_init(void)
-{
-        struct clkctl_acpu_speed *speed;
-        uint32_t div, sel;
-        int rc;
-        /*
-         * Determine the rate of ACPU clock
-         */
-        if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */
-                /* CLK_SRC0_SEL */
-                sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7;
-                /* CLK_SRC0_DIV */
-                div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f;
-        } else {
-                /* CLK_SRC1_SEL */
-                sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07;
-                /* CLK_SRC1_DIV */
-                div = readl(A11S_CLK_CNTL_ADDR) & 0x0f;
-        }
-        for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) {
-                if (speed->a11clk_src_sel == sel
-                 && (speed->a11clk_src_div == div))
-                        break;
-        }
-        if (speed->a11clk_khz == 0) {
-                printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n");
-                return;
-        }
-        drv_state.current_speed = speed;
-        rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000);
-        if (rc < 0)
-                pr_err("Setting AXI min rate failed!\n");
-        printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz);
-}
-unsigned long acpuclk_get_rate(void)
-{
-        WARN_ONCE(drv_state.current_speed == NULL,
-                  "acpuclk_get_rate: not initialized\n");
-        if (drv_state.current_speed)
-                return drv_state.current_speed->a11clk_khz;
-        else
-                return 0;
-}
-uint32_t acpuclk_get_switch_time(void)
-{
-        return drv_state.acpu_switch_time_us;
-}
-/*----------------------------------------------------------------------------
- * Clock driver initialization
- *---------------------------------------------------------------------------*/
-/* Initialize the lpj field in the acpu_freq_tbl. */
-static void __init lpj_init(void)
-{
-        int i;
-        const struct clkctl_acpu_speed *base_clk = drv_state.current_speed;
-        for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) {
-                acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy,
-                                                base_clk->a11clk_khz,
-                                                acpu_freq_tbl[i].a11clk_khz);
-        }
-}
-void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
-{
-        pr_info("acpu_clock_init()\n");
-        ebi1_clk = clk_get(NULL, "ebi1_clk");
-        mutex_init(&drv_state.lock);
-        drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us;
-        drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz;
-        drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
-        drv_state.power_collapse_khz = clkdata->power_collapse_khz;
-        drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz;
-        acpuclk_init();
-        lpj_init();
-#ifdef CONFIG_CPU_FREQ_TABLE
-        cpufreq_frequency_table_get_attr(freq_table, smp_processor_id());
-#endif
-}
diff --git a/arch/arm/mach-msm/acpuclock.h b/arch/arm/mach-msm/acpuclock.h
deleted file mode 100644
index 415de2eb9a5e..000000000000
--- a/arch/arm/mach-msm/acpuclock.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* arch/arm/mach-msm/acpuclock.h
- *
- * MSM architecture clock driver header
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007 QUALCOMM Incorporated
- * Author: San Mehat <san@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
-#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
-int acpuclk_set_rate(unsigned long rate, int for_power_collapse);
-unsigned long acpuclk_get_rate(void);
-uint32_t acpuclk_get_switch_time(void);
-unsigned long acpuclk_wait_for_irq(void);
-unsigned long acpuclk_power_collapse(void);
-unsigned long acpuclk_get_wfi_rate(void);
-#endif
diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c
new file mode 100644
index 000000000000..b5b4de2cdf9e
--- /dev/null
+++ b/arch/arm/mach-msm/board-dt-8660.c
@@ -0,0 +1,64 @@
+/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+#include <mach/board.h>
+#include "common.h"
+static const struct of_device_id msm_dt_gic_match[] __initconst = {
+        { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
+        {}
+};
+static void __init msm8x60_init_irq(void)
+{
+        of_irq_init(msm_dt_gic_match);
+}
+static void __init msm8x60_init_late(void)
+{
+        smd_debugfs_init();
+}
+static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
+        {}
+};
+static void __init msm8x60_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        msm_auxdata_lookup, NULL);
+}
+static const char *msm8x60_fluid_match[] __initdata = {
+        "qcom,msm8660-fluid",
+        "qcom,msm8660-surf",
+        NULL
+};
+DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
+        .smp = smp_ops(msm_smp_ops),
+        .map_io = msm_map_msm8x60_io,
+        .init_irq = msm8x60_init_irq,
+        .handle_irq = gic_handle_irq,
+        .init_machine = msm8x60_dt_init,
+        .init_late = msm8x60_init_late,
+        .timer = &msm_dt_timer,
+        .dt_compat = msm8x60_fluid_match,
+MACHINE_END
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c
new file mode 100644
index 000000000000..4490edb71c17
--- /dev/null
+++ b/arch/arm/mach-msm/board-dt-8960.c
@@ -0,0 +1,50 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+#include "common.h"
+static const struct of_device_id msm_dt_gic_match[] __initconst = {
+        { .compatible = "qcom,msm-qgic2", .data = gic_of_init },
+        { }
+};
+static void __init msm_dt_init_irq(void)
+{
+        of_irq_init(msm_dt_gic_match);
+}
+static void __init msm_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static const char * const msm8960_dt_match[] __initconst = {
+        "qcom,msm8960-cdp",
+        NULL
+};
+DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
+        .smp = smp_ops(msm_smp_ops),
+        .map_io = msm_map_msm8960_io,
+        .init_irq = msm_dt_init_irq,
+        .timer = &msm_dt_timer,
+        .init_machine = msm_dt_init,
+        .dt_compat = msm8960_dt_match,
+        .handle_irq = gic_handle_irq,
+MACHINE_END
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 4fa3e99d9a62..6ce542e2e21c 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -36,6 +36,7 @@
 #include <linux/mtd/partitions.h>
 #include "devices.h"
+#include "common.h"
 static struct resource smc91x_resources[] = {
        [0] = {
@@ -66,8 +67,6 @@ static struct platform_device *devices[] __initdata = {
        &smc91x_device,
 };
-extern struct sys_timer msm_timer;
 static void __init halibut_init_early(void)
 {
        arch_ioremap_caller = __msm_ioremap_caller;
@@ -107,5 +106,5 @@ MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
        .init_irq       = halibut_init_irq,
        .init_machine   = halibut_init,
        .init_late      = halibut_init_late,
-        .timer          = &msm_timer,
+        .timer          = &msm7x01_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index cf1f89a5dc62..df00bc03ce74 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -30,7 +30,6 @@
 #include <mach/board.h>
 #include <mach/hardware.h>
-#include <mach/system.h>
 #include "board-mahimahi.h"
 #include "devices.h"
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
deleted file mode 100644
index 451ab1d43c92..000000000000
--- a/arch/arm/mach-msm/board-msm7x27.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/power_supply.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/setup.h>
-#ifdef CONFIG_CACHE_L2X0
-#include <asm/hardware/cache-l2x0.h>
-#endif
-#include <mach/vreg.h>
-#include <mach/mpp.h>
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-#include "devices.h"
-#include "socinfo.h"
-#include "clock.h"
-static struct resource smc91x_resources[] = {
-        [0] = {
-                .start  = 0x9C004300,
-                .end    = 0x9C0043ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = MSM_GPIO_TO_INT(132),
-                .end    = MSM_GPIO_TO_INT(132),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device smc91x_device = {
-        .name           = "smc91x",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(smc91x_resources),
-        .resource       = smc91x_resources,
-};
-static struct platform_device *devices[] __initdata = {
-        &msm_device_uart3,
-        &msm_device_smd,
-        &msm_device_dmov,
-        &msm_device_nand,
-        &smc91x_device,
-};
-extern struct sys_timer msm_timer;
-static void __init msm7x2x_init_irq(void)
-{
-        msm_init_irq();
-}
-static void __init msm7x2x_init(void)
-{
-        if (socinfo_init() < 0)
-                BUG();
-        if (machine_is_msm7x25_ffa() || machine_is_msm7x27_ffa()) {
-                smc91x_resources[0].start = 0x98000300;
-                smc91x_resources[0].end = 0x980003ff;
-                smc91x_resources[1].start = MSM_GPIO_TO_INT(85);
-                smc91x_resources[1].end = MSM_GPIO_TO_INT(85);
-                if (gpio_tlmm_config(GPIO_CFG(85, 0,
-                                              GPIO_INPUT,
-                                              GPIO_PULL_DOWN,
-                                              GPIO_2MA),
-                                     GPIO_ENABLE)) {
-                        printk(KERN_ERR
-                               "%s: Err: Config GPIO-85 INT\n",
-                                __func__);
-                }
-        }
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-static void __init msm7x2x_map_io(void)
-{
-        msm_map_common_io();
-        /* Technically dependent on the SoC but using machine_is
-         * macros since socinfo is not available this early and there
-         * are plans to restructure the code which will eliminate the
-         * need for socinfo.
-         */
-        if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa())
-                msm_clock_init(msm_clocks_7x27, msm_num_clocks_7x27);
-        if (machine_is_msm7x25_surf() || machine_is_msm7x25_ffa())
-                msm_clock_init(msm_clocks_7x25, msm_num_clocks_7x25);
-#ifdef CONFIG_CACHE_L2X0
-        if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) {
-                /* 7x27 has 256KB L2 cache:
-                        64Kb/Way and 4-Way Associativity;
-                        R/W latency: 3 cycles;
-                        evmon/parity/share disabled. */
-                l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000);
-        }
-#endif
-}
-static void __init msm7x2x_init_late(void)
-{
-        smd_debugfs_init();
-}
-MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
-        .atag_offset    = 0x100,
-        .map_io         = msm7x2x_map_io,
-        .init_irq       = msm7x2x_init_irq,
-        .init_machine   = msm7x2x_init,
-        .init_late      = msm7x2x_init_late,
-        .timer          = &msm_timer,
-MACHINE_END
-MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
-        .atag_offset    = 0x100,
-        .map_io         = msm7x2x_map_io,
-        .init_irq       = msm7x2x_init_irq,
-        .init_machine   = msm7x2x_init,
-        .init_late      = msm7x2x_init_late,
-        .timer          = &msm_timer,
-MACHINE_END
-MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
-        .atag_offset    = 0x100,
-        .map_io         = msm7x2x_map_io,
-        .init_irq       = msm7x2x_init_irq,
-        .init_machine   = msm7x2x_init,
-        .init_late      = msm7x2x_init_late,
-        .timer          = &msm_timer,
-MACHINE_END
-MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
-        .atag_offset    = 0x100,
-        .map_io         = msm7x2x_map_io,
-        .init_irq       = msm7x2x_init_irq,
-        .init_machine   = msm7x2x_init,
-        .init_late      = msm7x2x_init_late,
-        .timer          = &msm_timer,
-MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index a5001378135d..effa6f4336c7 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -38,8 +38,7 @@
 #include "devices.h"
 #include "gpiomux.h"
 #include "proc_comm.h"
+#include "common.h"
-extern struct sys_timer msm_timer;
 static void __init msm7x30_fixup(struct tag *tag, char **cmdline,
                struct meminfo *mi)
@@ -132,7 +131,7 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
        .init_irq = msm7x30_init_irq,
        .init_machine = msm7x30_init,
        .init_late = msm7x30_init_late,
-        .timer = &msm_timer,
+        .timer = &msm7x30_timer,
 MACHINE_END
 MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
@@ -143,7 +142,7 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
        .init_irq = msm7x30_init_irq,
        .init_machine = msm7x30_init,
        .init_late = msm7x30_init_late,
-        .timer = &msm_timer,
+        .timer = &msm7x30_timer,
 MACHINE_END
 MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
@@ -154,5 +153,5 @@ MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
        .init_irq = msm7x30_init_irq,
        .init_machine = msm7x30_init,
        .init_late = msm7x30_init_late,
-        .timer = &msm_timer,
+        .timer = &msm7x30_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
deleted file mode 100644
index 65f4a1daa2e5..000000000000
--- a/arch/arm/mach-msm/board-msm8960.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- *
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/clkdev.h>
-#include <linux/memblock.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
-#include <asm/setup.h>
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-#include "devices.h"
-static void __init msm8960_fixup(struct tag *tag, char **cmdline,
-                struct meminfo *mi)
-{
-        for (; tag->hdr.size; tag = tag_next(tag))
-                if (tag->hdr.tag == ATAG_MEM &&
-                                tag->u.mem.start == 0x40200000) {
-                        tag->u.mem.start = 0x40000000;
-                        tag->u.mem.size += SZ_2M;
-                }
-}
-static void __init msm8960_reserve(void)
-{
-        memblock_remove(0x40000000, SZ_2M);
-}
-static void __init msm8960_map_io(void)
-{
-        msm_map_msm8960_io();
-}
-static void __init msm8960_init_irq(void)
-{
-        unsigned int i;
-        gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
-                 (void *)MSM_QGIC_CPU_BASE);
-        /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
-        writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
-        if (machine_is_msm8960_rumi3())
-                writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
-        /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
-         * as they are configured as level, which does not play nice with
-         * handle_percpu_irq.
-         */
-        for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
-                if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
-                        irq_set_handler(i, handle_percpu_irq);
-        }
-}
-static struct platform_device *sim_devices[] __initdata = {
-        &msm8960_device_uart_gsbi2,
-};
-static struct platform_device *rumi3_devices[] __initdata = {
-        &msm8960_device_uart_gsbi5,
-};
-static void __init msm8960_sim_init(void)
-{
-        platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices));
-}
-static void __init msm8960_rumi3_init(void)
-{
-        platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices));
-}
-static void __init msm8960_init_late(void)
-{
-        smd_debugfs_init();
-}
-MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
-        .fixup = msm8960_fixup,
-        .reserve = msm8960_reserve,
-        .map_io = msm8960_map_io,
-        .init_irq = msm8960_init_irq,
-        .timer = &msm_timer,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8960_sim_init,
-        .init_late = msm8960_init_late,
-MACHINE_END
-MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
-        .fixup = msm8960_fixup,
-        .reserve = msm8960_reserve,
-        .map_io = msm8960_map_io,
-        .init_irq = msm8960_init_irq,
-        .timer = &msm_timer,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8960_rumi3_init,
-        .init_late = msm8960_init_late,
-MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
deleted file mode 100644
index e37a724cd1eb..000000000000
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/* Copyright (c) 2010, 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/memblock.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
-#include <asm/setup.h>
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-static void __init msm8x60_fixup(struct tag *tag, char **cmdline,
-                struct meminfo *mi)
-{
-        for (; tag->hdr.size; tag = tag_next(tag))
-                if (tag->hdr.tag == ATAG_MEM &&
-                                tag->u.mem.start == 0x40200000) {
-                        tag->u.mem.start = 0x40000000;
-                        tag->u.mem.size += SZ_2M;
-                }
-}
-static void __init msm8x60_reserve(void)
-{
-        memblock_remove(0x40000000, SZ_2M);
-}
-static void __init msm8x60_map_io(void)
-{
-        msm_map_msm8x60_io();
-}
-#ifdef CONFIG_OF
-static struct of_device_id msm_dt_gic_match[] __initdata = {
-        { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
-        {}
-};
-#endif
-static void __init msm8x60_init_irq(void)
-{
-        if (!of_have_populated_dt())
-                gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
-                         (void *)MSM_QGIC_CPU_BASE);
-#ifdef CONFIG_OF
-        else
-                of_irq_init(msm_dt_gic_match);
-#endif
-        /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
-        writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
-        /* RUMI does not adhere to GIC spec by enabling STIs by default.
-         * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
-         */
-        if (!machine_is_msm8x60_sim())
-                writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
-}
-static void __init msm8x60_init(void)
-{
-}
-static void __init msm8x60_init_late(void)
-{
-        smd_debugfs_init();
-}
-#ifdef CONFIG_OF
-static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
-        {}
-};
-static void __init msm8x60_dt_init(void)
-{
-        if (of_machine_is_compatible("qcom,msm8660-surf")) {
-                printk(KERN_INFO "Init surf UART registers\n");
-                msm8x60_init_uart12dm();
-        }
-        of_platform_populate(NULL, of_default_bus_match_table,
-                        msm_auxdata_lookup, NULL);
-}
-static const char *msm8x60_fluid_match[] __initdata = {
-        "qcom,msm8660-fluid",
-        "qcom,msm8660-surf",
-        NULL
-};
-#endif /* CONFIG_OF */
-MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
-        .fixup = msm8x60_fixup,
-        .reserve = msm8x60_reserve,
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8x60_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-MACHINE_END
-MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
-        .fixup = msm8x60_fixup,
-        .reserve = msm8x60_reserve,
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8x60_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-MACHINE_END
-MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
-        .fixup = msm8x60_fixup,
-        .reserve = msm8x60_reserve,
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8x60_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-MACHINE_END
-MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
-        .fixup = msm8x60_fixup,
-        .reserve = msm8x60_reserve,
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8x60_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-MACHINE_END
-#ifdef CONFIG_OF
-/* TODO: General device tree support for all MSM. */
-DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .init_machine = msm8x60_dt_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-        .dt_compat = msm8x60_fluid_match,
-MACHINE_END
-#endif /* CONFIG_OF */
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index c8fe0edb9761..2448fcf09eb1 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -32,14 +32,13 @@
 #include <mach/irqs.h>
 #include <mach/sirc.h>
 #include <mach/vreg.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-msm_sdcc.h>
 #include "devices.h"
+#include "common.h"
-extern struct sys_timer msm_timer;
+static const resource_size_t qsd8x50_surf_smc91x_base __initconst = 0x70000300;
+static const unsigned        qsd8x50_surf_smc91x_gpio __initconst = 156;
-static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
-static const unsigned        qsd8x50_surf_smc91x_gpio __initdata = 156;
 /* Leave smc91x resources empty here, as we'll fill them in
 * at run-time: they vary from board to board, and the true
@@ -201,7 +200,7 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
        .init_irq = qsd8x50_init_irq,
        .init_machine = qsd8x50_init,
        .init_late = qsd8x50_init_late,
-        .timer = &msm_timer,
+        .timer = &qsd8x50_timer,
 MACHINE_END
 MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
@@ -210,5 +209,5 @@ MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
        .init_irq = qsd8x50_init_irq,
        .init_machine = qsd8x50_init,
        .init_late = qsd8x50_init_late,
-        .timer = &msm_timer,
+        .timer = &qsd8x50_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 2e569ab10eef..b7b0fc7e3278 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -27,7 +27,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
-#include <mach/system.h>
 #include <mach/vreg.h>
 #include <mach/board.h>
diff --git a/arch/arm/mach-msm/board-trout-mmc.c b/arch/arm/mach-msm/board-trout-mmc.c
index 8650342b7493..3723e55819d6 100644
--- a/arch/arm/mach-msm/board-trout-mmc.c
+++ b/arch/arm/mach-msm/board-trout-mmc.c
@@ -15,7 +15,7 @@
 #include <mach/vreg.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-msm_sdcc.h>
 #include "devices.h"
diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c
index 89bf6b426699..f9a5db6d2ced 100644
--- a/arch/arm/mach-msm/board-trout-panel.c
+++ b/arch/arm/mach-msm/board-trout-panel.c
@@ -14,7 +14,7 @@
 #include <asm/mach-types.h>
 #include <asm/system_info.h>
-#include <mach/msm_fb.h>
+#include <linux/platform_data/video-msm_fb.h>
 #include <mach/vreg.h>
 #include "board-trout.h"
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index bbe13f12fa01..4ba0800e243e 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -31,6 +31,7 @@
 #include "devices.h"
 #include "board-trout.h"
+#include "common.h"
 extern int trout_init_mmc(unsigned int);
@@ -42,8 +43,6 @@ static struct platform_device *devices[] __initdata = {
        &msm_device_i2c,
 };
-extern struct sys_timer msm_timer;
 static void __init trout_init_early(void)
 {
        arch_ioremap_caller = __msm_ioremap_caller;
@@ -111,5 +110,5 @@ MACHINE_START(TROUT, "HTC Dream")
        .init_irq       = trout_init_irq,
        .init_machine   = trout_init,
        .init_late      = trout_init_late,
-        .timer          = &msm_timer,
+        .timer          = &msm7x01_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index 63b711311086..a52c970df157 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -25,7 +25,7 @@
 /*
 * glue for the proc_comm interface
 */
-int pc_clk_enable(unsigned id)
+static int pc_clk_enable(unsigned id)
 {
        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
        if (rc < 0)
@@ -34,7 +34,7 @@ int pc_clk_enable(unsigned id)
                return (int)id < 0 ? -EINVAL : 0;
 }
-void pc_clk_disable(unsigned id)
+static void pc_clk_disable(unsigned id)
 {
        msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
 }
@@ -54,7 +54,7 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action)
                return (int)id < 0 ? -EINVAL : 0;
 }
-int pc_clk_set_rate(unsigned id, unsigned rate)
+static int pc_clk_set_rate(unsigned id, unsigned rate)
 {
        /* The rate _might_ be rounded off to the nearest KHz value by the
         * remote function. So a return value of 0 doesn't necessarily mean
@@ -67,7 +67,7 @@ int pc_clk_set_rate(unsigned id, unsigned rate)
                return (int)id < 0 ? -EINVAL : 0;
 }
-int pc_clk_set_min_rate(unsigned id, unsigned rate)
+static int pc_clk_set_min_rate(unsigned id, unsigned rate)
 {
        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
        if (rc < 0)
@@ -76,7 +76,7 @@ int pc_clk_set_min_rate(unsigned id, unsigned rate)
                return (int)id < 0 ? -EINVAL : 0;
 }
-int pc_clk_set_max_rate(unsigned id, unsigned rate)
+static int pc_clk_set_max_rate(unsigned id, unsigned rate)
 {
        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
        if (rc < 0)
@@ -85,7 +85,7 @@ int pc_clk_set_max_rate(unsigned id, unsigned rate)
                return (int)id < 0 ? -EINVAL : 0;
 }
-int pc_clk_set_flags(unsigned id, unsigned flags)
+static int pc_clk_set_flags(unsigned id, unsigned flags)
 {
        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
        if (rc < 0)
@@ -94,7 +94,7 @@ int pc_clk_set_flags(unsigned id, unsigned flags)
                return (int)id < 0 ? -EINVAL : 0;
 }
-unsigned pc_clk_get_rate(unsigned id)
+static unsigned pc_clk_get_rate(unsigned id)
 {
        if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
                return 0;
@@ -102,7 +102,7 @@ unsigned pc_clk_get_rate(unsigned id)
                return id;
 }
-unsigned pc_clk_is_enabled(unsigned id)
+static unsigned pc_clk_is_enabled(unsigned id)
 {
        if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
                return 0;
@@ -110,7 +110,7 @@ unsigned pc_clk_is_enabled(unsigned id)
                return id;
 }
-long pc_clk_round_rate(unsigned id, unsigned rate)
+static long pc_clk_round_rate(unsigned id, unsigned rate)
 {
        /* Not really supported; pc_clk_set_rate() does rounding on it's own. */
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
new file mode 100644
index 000000000000..633a7159d5ff
--- /dev/null
+++ b/arch/arm/mach-msm/common.h
@@ -0,0 +1,32 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MACH_COMMON_H
+#define __MACH_COMMON_H
+extern struct sys_timer msm7x01_timer;
+extern struct sys_timer msm7x30_timer;
+extern struct sys_timer msm_dt_timer;
+extern struct sys_timer qsd8x50_timer;
+extern void msm_map_common_io(void);
+extern void msm_map_msm7x30_io(void);
+extern void msm_map_msm8x60_io(void);
+extern void msm_map_msm8960_io(void);
+extern void msm_map_qsd8x50_io(void);
+extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+                                          unsigned int mtype, void *caller);
+extern struct smp_operations msm_smp_ops;
+extern void msm_cpu_die(unsigned int cpu);
+#endif
diff --git a/arch/arm/mach-msm/core.h b/arch/arm/mach-msm/core.h
new file mode 100644
index 000000000000..a9bab53dddf4
--- /dev/null
+++ b/arch/arm/mach-msm/core.h
@@ -0,0 +1,2 @@
+extern struct smp_operations msm_smp_ops;
+extern void msm_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index 993780f490ad..f66ee6ea8720 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -27,7 +27,7 @@
 #include "clock.h"
 #include "clock-pcom.h"
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-msm_sdcc.h>
 static struct resource resources_uart1[] = {
        {
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 09b4f1403824..e90ab5938c5f 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -31,7 +31,7 @@
 #include "clock-pcom.h"
 #include "clock-7x30.h"
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-msm_sdcc.h>
 static struct resource resources_uart2[] = {
        {
diff --git a/arch/arm/mach-msm/devices-msm8960.c b/arch/arm/mach-msm/devices-msm8960.c
deleted file mode 100644
index d9e1f26475de..000000000000
--- a/arch/arm/mach-msm/devices-msm8960.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <mach/irqs-8960.h>
-#include <mach/board.h>
-#include "devices.h"
-#define MSM_GSBI2_PHYS          0x16100000
-#define MSM_UART2DM_PHYS        (MSM_GSBI2_PHYS + 0x40000)
-#define MSM_GSBI5_PHYS          0x16400000
-#define MSM_UART5DM_PHYS        (MSM_GSBI5_PHYS + 0x40000)
-static struct resource resources_uart_gsbi2[] = {
-        {
-                .start  = GSBI2_UARTDM_IRQ,
-                .end    = GSBI2_UARTDM_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = MSM_UART2DM_PHYS,
-                .end    = MSM_UART2DM_PHYS + PAGE_SIZE - 1,
-                .name   = "uart_resource",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MSM_GSBI2_PHYS,
-                .end    = MSM_GSBI2_PHYS + PAGE_SIZE - 1,
-                .name   = "gsbi_resource",
-                .flags  = IORESOURCE_MEM,
-        },
-};
-struct platform_device msm8960_device_uart_gsbi2 = {
-        .name   = "msm_serial",
-        .id     = 0,
-        .num_resources  = ARRAY_SIZE(resources_uart_gsbi2),
-        .resource       = resources_uart_gsbi2,
-};
-static struct resource resources_uart_gsbi5[] = {
-        {
-                .start  = GSBI5_UARTDM_IRQ,
-                .end    = GSBI5_UARTDM_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = MSM_UART5DM_PHYS,
-                .end    = MSM_UART5DM_PHYS + PAGE_SIZE - 1,
-                .name   = "uart_resource",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MSM_GSBI5_PHYS,
-                .end    = MSM_GSBI5_PHYS + PAGE_SIZE - 1,
-                .name   = "gsbi_resource",
-                .flags  = IORESOURCE_MEM,
-        },
-};
-struct platform_device msm8960_device_uart_gsbi5 = {
-        .name   = "msm_serial",
-        .id     = 0,
-        .num_resources  = ARRAY_SIZE(resources_uart_gsbi5),
-        .resource       = resources_uart_gsbi5,
-};
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 131633b12a34..4db61d5fe317 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -27,7 +27,7 @@
 #include <asm/mach/flash.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-msm_sdcc.h>
 #include "clock-pcom.h"
 static struct resource resources_uart3[] = {
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index 02cae5e2951c..354b91d4c3ac 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -223,8 +223,7 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id)
                        PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
                        if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) {
                                cmd = list_entry(ready_commands[id].next, typeof(*cmd), list);
-                                list_del(&cmd->list);
+                                list_move_tail(&cmd->list, &active_commands[id]);
-                                list_add_tail(&cmd->list, &active_commands[id]);
                                if (cmd->execute_func)
                                        cmd->execute_func(cmd);
                                PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id);
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
index a446fc14221f..750446feb444 100644
--- a/arch/arm/mach-msm/hotplug.c
+++ b/arch/arm/mach-msm/hotplug.c
@@ -13,7 +13,7 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
-extern volatile int pen_release;
+#include "common.h"
 static inline void cpu_enter_lowpower(void)
 {
@@ -57,17 +57,12 @@ static inline void platform_do_lowpower(unsigned int cpu)
        }
 }
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
 /*
 * platform-specific code to shutdown a CPU
 *
 * Called with IRQs disabled
 */
-void platform_cpu_die(unsigned int cpu)
+void __ref msm_cpu_die(unsigned int cpu)
 {
        /*
         * we're ready for shutdown now, so do it
@@ -81,12 +76,3 @@ void platform_cpu_die(unsigned int cpu)
         */
        cpu_leave_lowpower();
 }
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-msm/idle.c b/arch/arm/mach-msm/idle.c
deleted file mode 100644
index 0c9e13c65743..000000000000
--- a/arch/arm/mach-msm/idle.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/* arch/arm/mach-msm/idle.c
- *
- * Idle processing for MSM7K - work around bugs with SWFI.
- *
- * Copyright (c) 2007 QUALCOMM Incorporated.
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/init.h>
-#include <asm/system.h>
-static void msm_idle(void)
-{
-#ifdef CONFIG_MSM7X00A_IDLE
-        asm volatile (
-        "mrc     p15, 0, r1, c1, c0, 0    /* read current CR    */ \n\t"
-        "bic     r0, r1, #(1 << 2)        /* clear dcache bit   */ \n\t"
-        "bic     r0, r0, #(1 << 12)       /* clear icache bit   */ \n\t"
-        "mcr     p15, 0, r0, c1, c0, 0    /* disable d/i cache  */ \n\t"
-        "mov     r0, #0                   /* prepare wfi value  */ \n\t"
-        "mcr     p15, 0, r0, c7, c10, 0   /* flush the cache    */ \n\t"
-        "mcr     p15, 0, r0, c7, c10, 4   /* memory barrier     */ \n\t"
-        "mcr     p15, 0, r0, c7, c0, 4    /* wait for interrupt */ \n\t"
-        "mcr     p15, 0, r1, c1, c0, 0    /* restore d/i cache  */ \n\t"
-        : : : "r0","r1" );
-#endif
-}
-static int __init msm_idle_init(void)
-{
-        arm_pm_idle = msm_idle;
-        return 0;
-}
-arch_initcall(msm_idle_init);
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 435f8edfafd1..8cebedb11233 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -18,31 +18,18 @@
 #define __ASM_ARCH_MSM_BOARD_H
 #include <linux/types.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-msm_sdcc.h>
 /* platform device data structures */
-struct msm_acpu_clock_platform_data
-{
-        uint32_t acpu_switch_time_us;
-        uint32_t max_speed_delta_khz;
-        uint32_t vdd_switch_time_us;
-        unsigned long power_collapse_khz;
-        unsigned long wait_for_irq_khz;
-};
 struct clk_lookup;
-extern struct sys_timer msm_timer;
 /* common init routines for use by arch/arm/mach-msm/board-*.c */
 void __init msm_add_devices(void);
-void __init msm_map_common_io(void);
 void __init msm_init_irq(void);
 void __init msm_init_gpio(void);
 void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
-void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *);
 int __init msm_add_sdcc(unsigned int controller,
                        struct msm_mmc_platform_data *plat,
                        unsigned int stat_irq, unsigned long stat_irq_flags);
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-msm/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-msm/include/mach/mmc.h b/arch/arm/mach-msm/include/mach/mmc.h
deleted file mode 100644
index ffcd9e3a6a7e..000000000000
--- a/arch/arm/mach-msm/include/mach/mmc.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- *  arch/arm/include/asm/mach/mmc.h
- */
-#ifndef ASMARM_MACH_MMC_H
-#define ASMARM_MACH_MMC_H
-#include <linux/mmc/host.h>
-#include <linux/mmc/card.h>
-#include <linux/mmc/sdio_func.h>
-struct msm_mmc_gpio {
-        unsigned no;
-        const char *name;
-};
-struct msm_mmc_gpio_data {
-        struct msm_mmc_gpio *gpio;
-        u8 size;
-};
-struct msm_mmc_platform_data {
-        unsigned int ocr_mask;                  /* available voltages */
-        u32 (*translate_vdd)(struct device *, unsigned int);
-        unsigned int (*status)(struct device *);
-        int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
-        struct msm_mmc_gpio_data *gpio_data;
-        void (*init_card)(struct mmc_card *card);
-};
-#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_fb.h b/arch/arm/mach-msm/include/mach/msm_fb.h
deleted file mode 100644
index 1f4fc81b3d8f..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_fb.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* arch/arm/mach-msm/include/mach/msm_fb.h
- *
- * Internal shared definitions for various MSM framebuffer parts.
- *
- * Copyright (C) 2007 Google Incorporated
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef _MSM_FB_H_
-#define _MSM_FB_H_
-#include <linux/device.h>
-struct mddi_info;
-struct msm_fb_data {
-        int xres;       /* x resolution in pixels */
-        int yres;       /* y resolution in pixels */
-        int width;      /* disply width in mm */
-        int height;     /* display height in mm */
-        unsigned output_format;
-};
-struct msmfb_callback {
-        void (*func)(struct msmfb_callback *);
-};
-enum {
-        MSM_MDDI_PMDH_INTERFACE,
-        MSM_MDDI_EMDH_INTERFACE,
-        MSM_EBI2_INTERFACE,
-};
-#define MSMFB_CAP_PARTIAL_UPDATES       (1 << 0)
-struct msm_panel_data {
-        /* turns off the fb memory */
-        int (*suspend)(struct msm_panel_data *);
-        /* turns on the fb memory */
-        int (*resume)(struct msm_panel_data *);
-        /* turns off the panel */
-        int (*blank)(struct msm_panel_data *);
-        /* turns on the panel */
-        int (*unblank)(struct msm_panel_data *);
-        void (*wait_vsync)(struct msm_panel_data *);
-        void (*request_vsync)(struct msm_panel_data *, struct msmfb_callback *);
-        void (*clear_vsync)(struct msm_panel_data *);
-        /* from the enum above */
-        unsigned interface_type;
-        /* data to be passed to the fb driver */
-        struct msm_fb_data *fb_data;
-        /* capabilities supported by the panel */
-        uint32_t caps;
-};
-struct msm_mddi_client_data {
-        void (*suspend)(struct msm_mddi_client_data *);
-        void (*resume)(struct msm_mddi_client_data *);
-        void (*activate_link)(struct msm_mddi_client_data *);
-        void (*remote_write)(struct msm_mddi_client_data *, uint32_t val,
-                             uint32_t reg);
-        uint32_t (*remote_read)(struct msm_mddi_client_data *, uint32_t reg);
-        void (*auto_hibernate)(struct msm_mddi_client_data *, int);
-        /* custom data that needs to be passed from the board file to a 
-         * particular client */
-        void *private_client_data;
-        struct resource *fb_resource;
-        /* from the list above */
-        unsigned interface_type;
-};
-struct msm_mddi_platform_data {
-        unsigned int clk_rate;
-        void (*power_client)(struct msm_mddi_client_data *, int on);
-        /* fixup the mfr name, product id */
-        void (*fixup)(uint16_t *mfr_name, uint16_t *product_id);
-        struct resource *fb_resource; /*optional*/
-        /* number of clients in the list that follows */
-        int num_clients;
-        /* array of client information of clients */
-        struct {
-                unsigned product_id; /* mfr id in top 16 bits, product id
-                                      * in lower 16 bits
-                                      */
-                char *name;     /* the device name will be the platform
-                                 * device name registered for the client,
-                                 * it should match the name of the associated
-                                 * driver
-                                 */
-                unsigned id;    /* id for mddi client device node, will also
-                                 * be used as device id of panel devices, if
-                                 * the client device will have multiple panels
-                                 * space must be left here for them
-                                 */
-                void *client_data;      /* required private client data */
-                unsigned int clk_rate;  /* optional: if the client requires a
-                                        * different mddi clk rate
-                                        */
-        } client_platform_data[];
-};
-struct mdp_blit_req;
-struct fb_info;
-struct mdp_device {
-        struct device dev;
-        void (*dma)(struct mdp_device *mpd, uint32_t addr,
-                    uint32_t stride, uint32_t w, uint32_t h, uint32_t x,
-                    uint32_t y, struct msmfb_callback *callback, int interface);
-        void (*dma_wait)(struct mdp_device *mdp);
-        int (*blit)(struct mdp_device *mdp, struct fb_info *fb,
-                    struct mdp_blit_req *req);
-        void (*set_grp_disp)(struct mdp_device *mdp, uint32_t disp_id);
-};
-struct class_interface;
-int register_mdp_client(struct class_interface *class_intf);
-/**** private client data structs go below this line ***/
-struct msm_mddi_bridge_platform_data {
-        /* from board file */
-        int (*init)(struct msm_mddi_bridge_platform_data *,
-                    struct msm_mddi_client_data *);
-        int (*uninit)(struct msm_mddi_bridge_platform_data *,
-                      struct msm_mddi_client_data *);
-        /* passed to panel for use by the fb driver */
-        int (*blank)(struct msm_mddi_bridge_platform_data *,
-                     struct msm_mddi_client_data *);
-        int (*unblank)(struct msm_mddi_bridge_platform_data *,
-                       struct msm_mddi_client_data *);
-        struct msm_fb_data fb_data;
-};
-#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 6c4046c21296..67dc0e98b958 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -105,11 +105,4 @@
 #define MSM_AD5_PHYS          0xAC000000
 #define MSM_AD5_SIZE          (SZ_1M*13)
-#ifndef __ASSEMBLY__
-extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
-                                          unsigned int mtype, void *caller);
-#endif
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index f944fe65a657..198202c267c8 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -100,8 +100,4 @@
 #define MSM_HSUSB_PHYS        0xA3600000
 #define MSM_HSUSB_SIZE        SZ_1K
-#ifndef __ASSEMBLY__
-extern void msm_map_msm7x30_io(void);
-#endif
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index a1752c0284fc..9819a556acae 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -46,12 +46,8 @@
 #define MSM8960_TMR0_SIZE       SZ_4K
 #ifdef CONFIG_DEBUG_MSM8960_UART
-#define MSM_DEBUG_UART_BASE     0xE1040000
+#define MSM_DEBUG_UART_BASE     0xF0040000
 #define MSM_DEBUG_UART_PHYS     0x16440000
 #endif
-#ifndef __ASSEMBLY__
-extern void msm_map_msm8960_io(void);
-#endif
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index da77cc1d545d..0faa894729b7 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -122,8 +122,4 @@
 #define MSM_SDC4_PHYS          0xA0600000
 #define MSM_SDC4_SIZE          SZ_4K
-#ifndef __ASSEMBLY__
-extern void msm_map_qsd8x50_io(void);
-#endif
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 5aed57dc808c..199372e62def 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -41,21 +41,10 @@
 #define MSM8X60_QGIC_CPU_PHYS   0x02081000
 #define MSM8X60_QGIC_CPU_SIZE   SZ_4K
-#define MSM_ACC_BASE            IOMEM(0xF0002000)
-#define MSM_ACC_PHYS            0x02001000
-#define MSM_ACC_SIZE            SZ_4K
-#define MSM_GCC_BASE            IOMEM(0xF0003000)
-#define MSM_GCC_PHYS            0x02082000
-#define MSM_GCC_SIZE            SZ_4K
 #define MSM_TLMM_BASE           IOMEM(0xF0004000)
 #define MSM_TLMM_PHYS           0x00800000
 #define MSM_TLMM_SIZE           SZ_16K
-#define MSM_SHARED_RAM_BASE     IOMEM(0xF0100000)
-#define MSM_SHARED_RAM_SIZE     SZ_1M
 #define MSM8X60_TMR_PHYS        0x02000000
 #define MSM8X60_TMR_SIZE        SZ_4K
@@ -63,12 +52,8 @@
 #define MSM8X60_TMR0_SIZE       SZ_4K
 #ifdef CONFIG_DEBUG_MSM8660_UART
-#define MSM_DEBUG_UART_BASE     0xE1040000
+#define MSM_DEBUG_UART_BASE     0xF0040000
 #define MSM_DEBUG_UART_PHYS     0x19C40000
 #endif
-#ifndef __ASSEMBLY__
-extern void msm_map_msm8x60_io(void);
-#endif
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 00afdfb8c38f..2ab7cf0919b3 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -41,12 +41,11 @@
 #include "msm_iomap-7x30.h"
 #elif defined(CONFIG_ARCH_QSD8X50)
 #include "msm_iomap-8x50.h"
-#elif defined(CONFIG_ARCH_MSM8X60)
-#include "msm_iomap-8x60.h"
 #else
 #include "msm_iomap-7x00.h"
 #endif
+#include "msm_iomap-8x60.h"
 #include "msm_iomap-8960.h"
 #define MSM_DEBUG_UART_SIZE     SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
deleted file mode 100644
index f5fb2ec87ffe..000000000000
--- a/arch/arm/mach-msm/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* arch/arm/mach-msm/include/mach/system.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-/* low level hardware reset hook -- for example, hitting the
- * PSHOLD line on the PMIC to hard reset the system
- */
-extern void (*msm_hw_reset_hook)(void);
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index a1e7b1168850..123ef9cbce1b 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -29,30 +29,32 @@
 #include <mach/board.h>
-#define MSM_CHIP_DEVICE(name, chip) {                         \
+#include "common.h"
+#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) {                          \
                .virtual = (unsigned long) MSM_##name##_BASE, \
                .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
                .length = chip##_##name##_SIZE, \
-                .type = MT_DEVICE_NONSHARED, \
+                .type = mem_type, \
         }
+#define MSM_DEVICE_TYPE(name, mem_type) \
+                MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type)
+#define MSM_CHIP_DEVICE(name, chip) \
+                MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE)
 #define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
-#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
+#if defined(CONFIG_ARCH_MSM7X00A)
-        || defined(CONFIG_ARCH_MSM7X25)
 static struct map_desc msm_io_desc[] __initdata = {
-        MSM_DEVICE(VIC),
+        MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED),
-        MSM_CHIP_DEVICE(CSR, MSM7X00),
+        MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED),
-        MSM_DEVICE(DMOV),
+        MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED),
-        MSM_CHIP_DEVICE(GPIO1, MSM7X00),
+        MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
-        MSM_CHIP_DEVICE(GPIO2, MSM7X00),
+        MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
-        MSM_DEVICE(CLK_CTL),
+        MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
 #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
        defined(CONFIG_DEBUG_MSM_UART3)
-        MSM_DEVICE(DEBUG_UART),
+        MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED),
-#endif
-#ifdef CONFIG_ARCH_MSM7X30
-        MSM_DEVICE(GCC),
 #endif
        {
                .virtual =  (unsigned long) MSM_SHARED_RAM_BASE,
@@ -109,8 +111,6 @@ static struct map_desc msm8x60_io_desc[] __initdata = {
        MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60),
        MSM_CHIP_DEVICE(TMR, MSM8X60),
        MSM_CHIP_DEVICE(TMR0, MSM8X60),
-        MSM_DEVICE(ACC),
-        MSM_DEVICE(GCC),
 #ifdef CONFIG_DEBUG_MSM8660_UART
        MSM_DEVICE(DEBUG_UART),
 #endif
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index e012dc8391cf..7ed69b69c87c 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -22,23 +22,14 @@
 #include <asm/mach-types.h>
 #include <asm/smp_plat.h>
-#include <mach/msm_iomap.h>
 #include "scm-boot.h"
+#include "common.h"
 #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
 #define SCSS_CPU1CORE_RESET 0xD80
 #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
-/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
-#define GIC_PPI_EDGE_MASK 0xFFFFD7FF
 extern void msm_secondary_startup(void);
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen".
- */
-volatile int pen_release = -1;
 static DEFINE_SPINLOCK(boot_lock);
@@ -48,11 +39,8 @@ static inline int get_core_count(void)
        return ((read_cpuid_id() >> 4) & 3) + 1;
 }
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit msm_secondary_init(unsigned int cpu)
 {
-        /* Configure edge-triggered PPIs */
-        writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
        /*
         * if any interrupts are already enabled for the primary
         * core (e.g. timer irq), then they will not have been enabled
@@ -93,7 +81,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu)
                                  "address\n");
 }
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        unsigned long timeout;
        static int cold_boot_done;
@@ -153,7 +141,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 * does not support the ARM SCU, so just set the possible cpu mask to
 * NR_CPUS.
 */
-void __init smp_init_cpus(void)
+static void __init msm_smp_init_cpus(void)
 {
        unsigned int i, ncores = get_core_count();
@@ -169,6 +157,16 @@ void __init smp_init_cpus(void)
        set_smp_cross_call(gic_raise_softirq);
 }
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
 {
 }
+struct smp_operations msm_smp_ops __initdata = {
+        .smp_init_cpus          = msm_smp_init_cpus,
+        .smp_prepare_cpus       = msm_smp_prepare_cpus,
+        .smp_secondary_init     = msm_secondary_init,
+        .smp_boot_secondary     = msm_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = msm_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c
index 9980dc736e7b..8f1eecd88186 100644
--- a/arch/arm/mach-msm/proc_comm.c
+++ b/arch/arm/mach-msm/proc_comm.c
@@ -19,7 +19,6 @@
 #include <linux/io.h>
 #include <linux/spinlock.h>
 #include <mach/msm_iomap.h>
-#include <mach/system.h>
 #include "proc_comm.h"
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index 657be73297db..c5a2eddc6cdc 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -30,7 +30,6 @@
 #include <linux/delay.h>
 #include <mach/msm_smd.h>
-#include <mach/system.h>
 #include "smd_private.h"
 #include "proc_comm.h"
@@ -39,8 +38,6 @@
 #define CONFIG_QDSP6 1
 #endif
-void (*msm_hw_reset_hook)(void);
 #define MODULE_NAME "msm_smd"
 enum {
@@ -52,13 +49,14 @@ static int msm_smd_debug_mask;
 struct shared_info {
        int ready;
-        unsigned state;
+        void __iomem *state;
 };
 static unsigned dummy_state[SMSM_STATE_COUNT];
 static struct shared_info smd_info = {
-        .state = (unsigned) &dummy_state,
+        /* FIXME: not a real __iomem pointer */
+        .state = &dummy_state,
 };
 module_param_named(debug_mask, msm_smd_debug_mask,
@@ -101,10 +99,6 @@ static void handle_modem_crash(void)
        pr_err("ARM9 has CRASHED\n");
        smd_diag();
-        /* hard reboot if possible */
-        if (msm_hw_reset_hook)
-                msm_hw_reset_hook();
        /* in this case the modem or watchdog should reboot us */
        for (;;)
                ;
@@ -796,22 +790,22 @@ void *smem_alloc(unsigned id, unsigned size)
        return smem_find(id, size);
 }
-void *smem_item(unsigned id, unsigned *size)
+void __iomem *smem_item(unsigned id, unsigned *size)
 {
        struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
        struct smem_heap_entry *toc = shared->heap_toc;
        if (id >= SMEM_NUM_ITEMS)
-                return 0;
+                return NULL;
        if (toc[id].allocated) {
                *size = toc[id].size;
-                return (void *) (MSM_SHARED_RAM_BASE + toc[id].offset);
+                return (MSM_SHARED_RAM_BASE + toc[id].offset);
        } else {
                *size = 0;
        }
-        return 0;
+        return NULL;
 }
 void *smem_find(unsigned id, unsigned size_in)
@@ -857,7 +851,7 @@ static irqreturn_t smsm_irq_handler(int irq, void *data)
 int smsm_change_state(enum smsm_state_item item,
                      uint32_t clear_mask, uint32_t set_mask)
 {
-        unsigned long addr = smd_info.state + item * 4;
+        void __iomem *addr = smd_info.state + item * 4;
        unsigned long flags;
        unsigned state;
@@ -943,10 +937,10 @@ int smd_core_init(void)
        /* wait for essential items to be initialized */
        for (;;) {
                unsigned size;
-                void *state;
+                void __iomem *state;
                state = smem_item(SMEM_SMSM_SHARED_STATE, &size);
                if (size == SMSM_V1_SIZE || size == SMSM_V2_SIZE) {
-                        smd_info.state = (unsigned)state;
+                        smd_info.state = state;
                        break;
                }
        }
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 812808254936..476549a8a709 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -1,7 +1,7 @@
 /*
 *
 * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -20,15 +20,16 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/gic.h>
 #include <asm/localtimer.h>
 #include <asm/sched_clock.h>
-#include <mach/msm_iomap.h>
+#include "common.h"
-#include <mach/cpu.h>
-#include <mach/board.h>
 #define TIMER_MATCH_VAL         0x0000
 #define TIMER_COUNT_VAL         0x0004
@@ -36,7 +37,6 @@
 #define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
 #define TIMER_ENABLE_EN                 BIT(0)
 #define TIMER_CLEAR             0x000C
-#define DGT_CLK_CTL             0x0034
 #define DGT_CLK_CTL_DIV_4       0x3
 #define GPT_HZ 32768
@@ -101,7 +101,7 @@ static struct clock_event_device msm_clockevent = {
 static union {
        struct clock_event_device *evt;
-        struct clock_event_device __percpu **percpu_evt;
+        struct clock_event_device * __percpu *percpu_evt;
 } msm_evt;
 static void __iomem *source_base;
@@ -151,7 +151,7 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
        *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
        clockevents_register_device(evt);
-        enable_percpu_irq(evt->irq, 0);
+        enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
        return 0;
 }
@@ -172,44 +172,21 @@ static notrace u32 msm_sched_clock_read(void)
        return msm_clocksource.read(&msm_clocksource);
 }
-static void __init msm_timer_init(void)
+static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
+                                  bool percpu)
 {
        struct clock_event_device *ce = &msm_clockevent;
        struct clocksource *cs = &msm_clocksource;
        int res;
-        u32 dgt_hz;
-        if (cpu_is_msm7x01()) {
-                event_base = MSM_CSR_BASE;
-                source_base = MSM_CSR_BASE + 0x10;
-                dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */
-                cs->read = msm_read_timer_count_shift;
-                cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
-        } else if (cpu_is_msm7x30()) {
-                event_base = MSM_CSR_BASE + 0x04;
-                source_base = MSM_CSR_BASE + 0x24;
-                dgt_hz = 24576000 / 4;
-        } else if (cpu_is_qsd8x50()) {
-                event_base = MSM_CSR_BASE;
-                source_base = MSM_CSR_BASE + 0x10;
-                dgt_hz = 19200000 / 4;
-        } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
-                event_base = MSM_TMR_BASE + 0x04;
-                /* Use CPU0's timer as the global clock source. */
-                source_base = MSM_TMR0_BASE + 0x24;
-                dgt_hz = 27000000 / 4;
-                writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
-        } else
-                BUG();
        writel_relaxed(0, event_base + TIMER_ENABLE);
        writel_relaxed(0, event_base + TIMER_CLEAR);
        writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
        ce->cpumask = cpumask_of(0);
+        ce->irq = irq;
-        ce->irq = INT_GP_TIMER_EXP;
        clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
-        if (cpu_is_msm8x60() || cpu_is_msm8960()) {
+        if (percpu) {
                msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
                if (!msm_evt.percpu_evt) {
                        pr_err("memory allocation failed for %s\n", ce->name);
@@ -219,7 +196,7 @@ static void __init msm_timer_init(void)
                res = request_percpu_irq(ce->irq, msm_timer_interrupt,
                                         ce->name, msm_evt.percpu_evt);
                if (!res) {
-                        enable_percpu_irq(ce->irq, 0);
+                        enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
 #ifdef CONFIG_LOCAL_TIMERS
                        local_timer_register(&msm_local_timer_ops);
 #endif
@@ -238,10 +215,143 @@ err:
        res = clocksource_register_hz(cs, dgt_hz);
        if (res)
                pr_err("clocksource_register failed\n");
-        setup_sched_clock(msm_sched_clock_read,
+        setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
-                        cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz);
 }
-struct sys_timer msm_timer = {
+#ifdef CONFIG_OF
-        .init = msm_timer_init
+static const struct of_device_id msm_dgt_match[] __initconst = {
+        { .compatible = "qcom,msm-dgt" },
+        { },
+};
+static const struct of_device_id msm_gpt_match[] __initconst = {
+        { .compatible = "qcom,msm-gpt" },
+        { },
+};
+static void __init msm_dt_timer_init(void)
+{
+        struct device_node *np;
+        u32 freq;
+        int irq;
+        struct resource res;
+        u32 percpu_offset;
+        void __iomem *dgt_clk_ctl;
+        np = of_find_matching_node(NULL, msm_gpt_match);
+        if (!np) {
+                pr_err("Can't find GPT DT node\n");
+                return;
+        }
+        event_base = of_iomap(np, 0);
+        if (!event_base) {
+                pr_err("Failed to map event base\n");
+                return;
+        }
+        irq = irq_of_parse_and_map(np, 0);
+        if (irq <= 0) {
+                pr_err("Can't get irq\n");
+                return;
+        }
+        of_node_put(np);
+        np = of_find_matching_node(NULL, msm_dgt_match);
+        if (!np) {
+                pr_err("Can't find DGT DT node\n");
+                return;
+        }
+        if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
+                percpu_offset = 0;
+        if (of_address_to_resource(np, 0, &res)) {
+                pr_err("Failed to parse DGT resource\n");
+                return;
+        }
+        source_base = ioremap(res.start + percpu_offset, resource_size(&res));
+        if (!source_base) {
+                pr_err("Failed to map source base\n");
+                return;
+        }
+        if (!of_address_to_resource(np, 1, &res)) {
+                dgt_clk_ctl = ioremap(res.start + percpu_offset,
+                                      resource_size(&res));
+                if (!dgt_clk_ctl) {
+                        pr_err("Failed to map DGT control base\n");
+                        return;
+                }
+                writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
+                iounmap(dgt_clk_ctl);
+        }
+        if (of_property_read_u32(np, "clock-frequency", &freq)) {
+                pr_err("Unknown frequency\n");
+                return;
+        }
+        of_node_put(np);
+        msm_timer_init(freq, 32, irq, !!percpu_offset);
+}
+struct sys_timer msm_dt_timer = {
+        .init = msm_dt_timer_init
+};
+#endif
+static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
+{
+        event_base = ioremap(event, SZ_64);
+        if (!event_base) {
+                pr_err("Failed to map event base\n");
+                return 1;
+        }
+        source_base = ioremap(source, SZ_64);
+        if (!source_base) {
+                pr_err("Failed to map source base\n");
+                return 1;
+        }
+        return 0;
+}
+static void __init msm7x01_timer_init(void)
+{
+        struct clocksource *cs = &msm_clocksource;
+        if (msm_timer_map(0xc0100000, 0xc0100010))
+                return;
+        cs->read = msm_read_timer_count_shift;
+        cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
+        /* 600 KHz */
+        msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
+                        false);
+}
+struct sys_timer msm7x01_timer = {
+        .init = msm7x01_timer_init
+};
+static void __init msm7x30_timer_init(void)
+{
+        if (msm_timer_map(0xc0100004, 0xc0100024))
+                return;
+        msm_timer_init(24576000 / 4, 32, 1, false);
+}
+struct sys_timer msm7x30_timer = {
+        .init = msm7x30_timer_init
+};
+static void __init qsd8x50_timer_init(void)
+{
+        if (msm_timer_map(0xAC100000, 0xAC100010))
+                return;
+        msm_timer_init(19200000 / 4, 32, 7, false);
+}
+struct sys_timer qsd8x50_timer = {
+        .init = qsd8x50_timer_init
 };
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index a9bc84180d21..26e9876b50e9 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -13,6 +13,7 @@
 #include <linux/mbus.h>
 #include <linux/io.h>
 #include <plat/addr-map.h>
+#include <mach/mv78xx0.h>
 #include "common.h"
 /*
@@ -47,13 +48,13 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i
         * so we don't need to take that into account here.
         */
-        return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
+        return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
 }
 /*
 * Description of the windows needed by the platform code
 */
-static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+static struct orion_addr_map_cfg addr_map_cfg __initdata = {
        .num_wins = 14,
        .remappable_wins = 8,
        .win_cfg_base = win_cfg_base,
@@ -71,17 +72,17 @@ void __init mv78xx0_setup_cpu_mbus(void)
         */
        if (mv78xx0_core_index() == 0)
                orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                            DDR_WINDOW_CPU0_BASE);
+                                            (void __iomem *) DDR_WINDOW_CPU0_BASE);
        else
                orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                            DDR_WINDOW_CPU1_BASE);
+                                            (void __iomem *) DDR_WINDOW_CPU1_BASE);
 }
 void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
                                      int maj, int min)
 {
        orion_setup_cpu_win(&addr_map_cfg, window, base, size,
-                            TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1);
+                            TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0);
 }
 void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 3057f7d4329a..d0cb4857b4b3 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -20,8 +20,8 @@
 #include <mach/mv78xx0.h>
 #include <mach/bridge-regs.h>
 #include <plat/cache-feroceon-l2.h>
-#include <plat/ehci-orion.h>
+#include <linux/platform_data/usb-ehci-orion.h>
-#include <plat/orion_nand.h>
+#include <linux/platform_data/mtd-orion_nand.h>
 #include <plat/time.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
@@ -130,17 +130,12 @@ static int get_tclk(void)
 ****************************************************************************/
 static struct map_desc mv78xx0_io_desc[] __initdata = {
        {
-                .virtual        = MV78XX0_CORE_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
                .pfn            = 0,
                .length         = MV78XX0_CORE_REGS_SIZE,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = MV78XX0_PCIE_IO_VIRT_BASE(0),
+                .virtual        = (unsigned long) MV78XX0_REGS_VIRT_BASE,
-                .pfn            = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
-                .length         = MV78XX0_PCIE_IO_SIZE * 8,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = MV78XX0_REGS_VIRT_BASE,
                .pfn            = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
                .length         = MV78XX0_REGS_SIZE,
                .type           = MT_DEVICE,
@@ -341,7 +336,7 @@ void __init mv78xx0_init_early(void)
        orion_time_set_base(TIMER_VIRT_BASE);
 }
-static void mv78xx0_timer_init(void)
+static void __init_refok mv78xx0_timer_init(void)
 {
        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
                        IRQ_MV78XX0_TIMER_1, get_tclk());
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
index eb187e0e059b..5f03484584d4 100644
--- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -11,18 +11,18 @@
 #include <mach/mv78xx0.h>
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
 #define L2_WRITETHROUGH         0x00020000
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
 #define SOFT_RESET_OUT_EN       0x00000004
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET              0x00000001
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_ERR_OFF       0x0000
 #define IRQ_CAUSE_LOW_OFF       0x0004
 #define IRQ_CAUSE_HIGH_OFF      0x0008
@@ -30,7 +30,7 @@
 #define IRQ_MASK_LOW_OFF        0x0010
 #define IRQ_MASK_HIGH_OFF       0x0014
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
 #endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h
deleted file mode 100644
index c7d9d00d8fc1..000000000000
--- a/arch/arm/mach-mv78xx0/include/mach/io.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/mach-mv78xx0/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-#include "mv78xx0.h"
-#define IO_SPACE_LIMIT          0xffffffff
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
-                                        + MV78XX0_PCIE_IO_VIRT_BASE(0));
-}
-#define __io(a)                 __io(a)
-#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index e807c4c52a0b..46200a183cf2 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -29,28 +29,27 @@
 *
 * virt         phys            size
 * fe400000     f102x000        16K     core-specific peripheral registers
- * fe700000     f0800000        1M      PCIe #0 I/O space
+ * fee00000     f0800000        64K     PCIe #0 I/O space
- * fe800000     f0900000        1M      PCIe #1 I/O space
+ * fee10000     f0900000        64K     PCIe #1 I/O space
- * fe900000     f0a00000        1M      PCIe #2 I/O space
+ * fee20000     f0a00000        64K     PCIe #2 I/O space
- * fea00000     f0b00000        1M      PCIe #3 I/O space
+ * fee30000     f0b00000        64K     PCIe #3 I/O space
- * feb00000     f0c00000        1M      PCIe #4 I/O space
+ * fee40000     f0c00000        64K     PCIe #4 I/O space
- * fec00000     f0d00000        1M      PCIe #5 I/O space
+ * fee50000     f0d00000        64K     PCIe #5 I/O space
- * fed00000     f0e00000        1M      PCIe #6 I/O space
+ * fee60000     f0e00000        64K     PCIe #6 I/O space
- * fee00000     f0f00000        1M      PCIe #7 I/O space
+ * fee70000     f0f00000        64K     PCIe #7 I/O space
- * fef00000     f1000000        1M      on-chip peripheral registers
+ * fd000000     f1000000        1M      on-chip peripheral registers
 */
 #define MV78XX0_CORE0_REGS_PHYS_BASE    0xf1020000
 #define MV78XX0_CORE1_REGS_PHYS_BASE    0xf1024000
-#define MV78XX0_CORE_REGS_VIRT_BASE     0xfe400000
+#define MV78XX0_CORE_REGS_VIRT_BASE     IOMEM(0xfe400000)
 #define MV78XX0_CORE_REGS_PHYS_BASE     0xfe400000
 #define MV78XX0_CORE_REGS_SIZE          SZ_16K
 #define MV78XX0_PCIE_IO_PHYS_BASE(i)    (0xf0800000 + ((i) << 20))
-#define MV78XX0_PCIE_IO_VIRT_BASE(i)    (0xfe700000 + ((i) << 20))
 #define MV78XX0_PCIE_IO_SIZE            SZ_1M
 #define MV78XX0_REGS_PHYS_BASE          0xf1000000
-#define MV78XX0_REGS_VIRT_BASE          0xfef00000
+#define MV78XX0_REGS_VIRT_BASE          IOMEM(0xfd000000)
 #define MV78XX0_REGS_SIZE               SZ_1M
 #define MV78XX0_PCIE_MEM_PHYS_BASE      0xc0000000
@@ -65,47 +64,47 @@
 /*
 * Register Map
 */
-#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE | 0x00000)
+#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE + 0x00000)
-#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE | 0x1500)
+#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE + 0x1500)
-#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE | 0x1570)
+#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE + 0x1570)
-#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE + 0x10000)
-#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x10000)
-#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE | 0x0030)
+#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE + 0x0030)
-#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE | 0x0034)
+#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE + 0x0034)
-#define  GPIO_VIRT_BASE         (DEV_BUS_VIRT_BASE | 0x0100)
+#define  GPIO_VIRT_BASE         (DEV_BUS_VIRT_BASE + 0x0100)
-#define  I2C_0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1000)
+#define  I2C_0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x1000)
-#define  I2C_1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1100)
+#define  I2C_1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x1100)
-#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2000)
-#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2000)
-#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2100)
-#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2100)
-#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2200)
+#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2200)
-#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2200)
+#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2200)
-#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2300)
+#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2300)
-#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2300)
+#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2300)
-#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x30000)
+#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x30000)
-#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x34000)
+#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x34000)
-#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x40000)
+#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x40000)
-#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x44000)
+#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x44000)
-#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x48000)
+#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x48000)
-#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x4c000)
+#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x4c000)
-#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x50000)
+#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x50000)
-#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x51000)
+#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x51000)
-#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x52000)
+#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x52000)
-#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x70000)
+#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x70000)
-#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x74000)
+#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x74000)
-#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x80000)
+#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x80000)
-#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x84000)
+#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x84000)
-#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x88000)
+#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x88000)
-#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x8c000)
+#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x8c000)
-#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0xa0000)
+#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0xa0000)
 /*
 * Supported devices and revisions.
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index eff9a750bbe2..32073444024b 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -10,7 +10,9 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
+#include <plat/orion-gpio.h>
 #include <plat/irq.h>
 #include "common.h"
@@ -23,16 +25,16 @@ static int __initdata gpio0_irqs[4] = {
 void __init mv78xx0_init_irq(void)
 {
-        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
+        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
-        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
-        orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
+        orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
        /*
         * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask
         * registers for core #1 are at an offset of 0x18 from those of
         * core #0.)
         */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE,
+        orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE,
                        mv78xx0_core_index() ? 0x18 : 0,
                        IRQ_MV78XX0_GPIO_START, gpio0_irqs);
 }
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 2e56e86b6d68..a9a154a646dd 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -15,6 +15,7 @@
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
 #include <plat/addr-map.h>
+#include <mach/mv78xx0.h>
 #include "common.h"
 struct pcie_port {
@@ -23,119 +24,73 @@ struct pcie_port {
        u8                      root_bus_nr;
        void __iomem            *base;
        spinlock_t              conf_lock;
-        char                    io_space_name[16];
        char                    mem_space_name[16];
-        struct resource         res[2];
+        struct resource         res;
 };
 static struct pcie_port pcie_port[8];
 static int num_pcie_ports;
 static struct resource pcie_io_space;
-static struct resource pcie_mem_space;
 void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
 {
-        *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE);
+        *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
-        *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE);
+        *rev = orion_pcie_rev(PCIE00_VIRT_BASE);
 }
+u32 pcie_port_size[8] = {
+        0,
+        0x30000000,
+        0x10000000,
+        0x10000000,
+        0x08000000,
+        0x08000000,
+        0x08000000,
+        0x04000000,
+};
 static void __init mv78xx0_pcie_preinit(void)
 {
        int i;
        u32 size_each;
        u32 start;
-        int win;
+        int win = 0;
        pcie_io_space.name = "PCIe I/O Space";
        pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
        pcie_io_space.end =
                MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
-        pcie_io_space.flags = IORESOURCE_IO;
+        pcie_io_space.flags = IORESOURCE_MEM;
        if (request_resource(&iomem_resource, &pcie_io_space))
                panic("can't allocate PCIe I/O space");
-        pcie_mem_space.name = "PCIe MEM Space";
+        if (num_pcie_ports > 7)
-        pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE;
+                panic("invalid number of PCIe ports");
-        pcie_mem_space.end =
-                MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1;
+        size_each = pcie_port_size[num_pcie_ports];
-        pcie_mem_space.flags = IORESOURCE_MEM;
-        if (request_resource(&iomem_resource, &pcie_mem_space))
-                panic("can't allocate PCIe MEM space");
+        start = MV78XX0_PCIE_MEM_PHYS_BASE;
        for (i = 0; i < num_pcie_ports; i++) {
                struct pcie_port *pp = pcie_port + i;
-                snprintf(pp->io_space_name, sizeof(pp->io_space_name),
-                        "PCIe %d.%d I/O", pp->maj, pp->min);
-                pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
-                pp->res[0].name = pp->io_space_name;
-                pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i);
-                pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1;
-                pp->res[0].flags = IORESOURCE_IO;
                snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
                        "PCIe %d.%d MEM", pp->maj, pp->min);
                pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
-                pp->res[1].name = pp->mem_space_name;
+                pp->res.name = pp->mem_space_name;
-                pp->res[1].flags = IORESOURCE_MEM;
+                pp->res.flags = IORESOURCE_MEM;
-        }
+                pp->res.start = start;
+                pp->res.end = start + size_each - 1;
-        switch (num_pcie_ports) {
-        case 0:
-                size_each = 0;
-                break;
-        case 1:
-                size_each = 0x30000000;
-                break;
-        case 2 ... 3:
-                size_each = 0x10000000;
-                break;
-        case 4 ... 6:
-                size_each = 0x08000000;
-                break;
-        case 7:
-                size_each = 0x04000000;
-                break;
-        default:
-                panic("invalid number of PCIe ports");
-        }
-        start = MV78XX0_PCIE_MEM_PHYS_BASE;
-        for (i = 0; i < num_pcie_ports; i++) {
-                struct pcie_port *pp = pcie_port + i;
-                pp->res[1].start = start;
-                pp->res[1].end = start + size_each - 1;
                start += size_each;
-        }
-        for (i = 0; i < num_pcie_ports; i++) {
-                struct pcie_port *pp = pcie_port + i;
-                if (request_resource(&pcie_io_space, &pp->res[0]))
+                if (request_resource(&iomem_resource, &pp->res))
-                        panic("can't allocate PCIe I/O sub-space");
-                if (request_resource(&pcie_mem_space, &pp->res[1]))
                        panic("can't allocate PCIe MEM sub-space");
-        }
-        win = 0;
+                mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start,
-        for (i = 0; i < num_pcie_ports; i++) {
+                                           resource_size(&pp->res),
-                struct pcie_port *pp = pcie_port + i;
+                                           pp->maj, pp->min);
-                mv78xx0_setup_pcie_io_win(win++, pp->res[0].start,
+                mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K,
-                                          resource_size(&pp->res[0]),
                                          pp->maj, pp->min);
-                mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
-                                           resource_size(&pp->res[1]),
-                                           pp->maj, pp->min);
        }
 }
@@ -156,8 +111,9 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
        orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
        orion_pcie_setup(pp->base);
-        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
+        pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr));
-        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
        return 1;
 }
@@ -267,11 +223,11 @@ static struct hw_pci mv78xx0_pci __initdata = {
        .map_irq        = mv78xx0_pcie_map_irq,
 };
-static void __init add_pcie_port(int maj, int min, unsigned long base)
+static void __init add_pcie_port(int maj, int min, void __iomem *base)
 {
        printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
-        if (orion_pcie_link_up((void __iomem *)base)) {
+        if (orion_pcie_link_up(base)) {
                struct pcie_port *pp = &pcie_port[num_pcie_ports++];
                printk("link up\n");
@@ -279,9 +235,9 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
                pp->maj = maj;
                pp->min = min;
                pp->root_bus_nr = -1;
-                pp->base = (void __iomem *)base;
+                pp->base = base;
                spin_lock_init(&pp->conf_lock);
-                memset(pp->res, 0, sizeof(pp->res));
+                memset(&pp->res, 0, sizeof(pp->res));
        } else {
                printk("link down, ignoring\n");
        }
@@ -293,7 +249,7 @@ void __init mv78xx0_pcie_init(int init_port0, int init_port1)
        if (init_port0) {
                add_pcie_port(0, 0, PCIE00_VIRT_BASE);
-                if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
+                if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
                        add_pcie_port(0, 1, PCIE01_VIRT_BASE);
                        add_pcie_port(0, 2, PCIE02_VIRT_BASE);
                        add_pcie_port(0, 3, PCIE03_VIRT_BASE);
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index caa2c5e734fe..416d46ef7ebd 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,15 +1,39 @@
+config ARCH_MVEBU
+        bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
+        select CLKSRC_MMIO
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_CHIP
+        select IRQ_DOMAIN
+        select MULTI_IRQ_HANDLER
+        select PINCTRL
+        select PLAT_ORION
+        select SPARSE_IRQ
 if ARCH_MVEBU
 menu "Marvell SOC with device tree"
 config MACH_ARMADA_370_XP
-        bool "Marvell Armada 370 and Aramada XP boards"
+        bool
        select ARMADA_370_XP_TIMER
        select CPU_V7
+config MACH_ARMADA_370
+        bool "Marvell Armada 370 boards"
+        select MACH_ARMADA_370_XP
+        select PINCTRL_ARMADA_370
        help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Armada 370 SoC with device tree.
-          Say 'Y' here if you want your kernel to support boards based on
+config MACH_ARMADA_XP
-          Marvell Armada 370 or Armada XP with device tree.
+        bool "Marvell Armada XP boards"
+        select MACH_ARMADA_370_XP
+        select PINCTRL_ARMADA_XP
+        help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Armada XP SoC with device tree.
 endmenu
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index e61d2b8fdf50..57f996b6aa0e 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,2 +1,5 @@
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+        -I$(srctree)/arch/arm/plat-orion/include
 obj-y += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o
diff --git a/arch/arm/mach-mvebu/Makefile.boot b/arch/arm/mach-mvebu/Makefile.boot
deleted file mode 100644
index 2579a2fc2334..000000000000
--- a/arch/arm/mach-mvebu/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-zreladdr-y := 0x00008000
-dtb-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-db.dtb
-dtb-$(CONFIG_MACH_ARMADA_370_XP) += armada-xp-db.dtb
diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c
new file mode 100644
index 000000000000..fe454a4430be
--- /dev/null
+++ b/arch/arm/mach-mvebu/addr-map.c
@@ -0,0 +1,134 @@
+/*
+ * Address map functions for Marvell 370 / XP SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <plat/addr-map.h>
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define ARMADA_XP_TARGET_DEV_BUS        1
+#define   ARMADA_XP_ATTR_DEV_BOOTROM    0x1D
+#define ARMADA_XP_TARGET_ETH1           3
+#define ARMADA_XP_TARGET_PCIE_0_2       4
+#define ARMADA_XP_TARGET_ETH0           7
+#define ARMADA_XP_TARGET_PCIE_1_3       8
+#define ARMADA_370_TARGET_DEV_BUS       1
+#define   ARMADA_370_ATTR_DEV_BOOTROM   0x1D
+#define ARMADA_370_TARGET_PCIE_0        4
+#define ARMADA_370_TARGET_PCIE_1        8
+#define ARMADA_WINDOW_8_PLUS_OFFSET       0x90
+#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
+static const struct __initdata orion_addr_map_info
+armada_xp_addr_map_info[] = {
+        /*
+         * Window for the BootROM, needed for SMP on Armada XP
+         */
+        { 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS,
+          ARMADA_XP_ATTR_DEV_BOOTROM, -1 },
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 },
+};
+static const struct __initdata orion_addr_map_info
+armada_370_addr_map_info[] = {
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 },
+};
+static struct of_device_id of_addr_decoding_controller_table[] = {
+        { .compatible = "marvell,armada-addr-decoding-controller" },
+        { /* end of list */ },
+};
+static void __iomem *
+armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
+{
+        unsigned int offset;
+        /* The register layout is a bit annoying and the below code
+         * tries to cope with it.
+         * - At offset 0x0, there are the registers for the first 8
+         *   windows, with 4 registers of 32 bits per window (ctrl,
+         *   base, remap low, remap high)
+         * - Then at offset 0x80, there is a hole of 0x10 bytes for
+         *   the internal registers base address and internal units
+         *   sync barrier register.
+         * - Then at offset 0x90, there the registers for 12
+         *   windows, with only 2 registers of 32 bits per window
+         *   (ctrl, base).
+         */
+        if (win < 8)
+                offset = (win << 4);
+        else
+                offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3);
+        return cfg->bridge_virt_base + offset;
+}
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+        .num_wins = 20,
+        .remappable_wins = 8,
+        .win_cfg_base = armada_cfg_base,
+};
+static int __init armada_setup_cpu_mbus(void)
+{
+        struct device_node *np;
+        void __iomem *mbus_unit_addr_decoding_base;
+        void __iomem *sdram_addr_decoding_base;
+        np = of_find_matching_node(NULL, of_addr_decoding_controller_table);
+        if (!np)
+                return -ENODEV;
+        mbus_unit_addr_decoding_base = of_iomap(np, 0);
+        BUG_ON(!mbus_unit_addr_decoding_base);
+        sdram_addr_decoding_base =
+                mbus_unit_addr_decoding_base +
+                ARMADA_SDRAM_ADDR_DECODING_OFFSET;
+        addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base;
+        /*
+         * Disable, clear and configure windows.
+         */
+        if (of_machine_is_compatible("marvell,armadaxp"))
+                orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info);
+        else if (of_machine_is_compatible("marvell,armada370"))
+                orion_config_wins(&addr_map_cfg, armada_370_addr_map_info);
+        else {
+                pr_err("Unsupported SoC\n");
+                return -EINVAL;
+        }
+        /*
+         * Setup MBUS dram target info.
+         */
+        orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                    sdram_addr_decoding_base);
+        return 0;
+}
+/* Using a early_initcall is needed so that this initialization gets
+ * done before the SMP initialization, which requires the BootROM to
+ * be remapped. */
+early_initcall(armada_setup_cpu_mbus);
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 4ef923b032ec..49d791548ad6 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -20,12 +20,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <mach/armada-370-xp.h>
+#include "armada-370-xp.h"
 #include "common.h"
 static struct map_desc armada_370_xp_io_desc[] __initdata = {
        {
-                .virtual        = ARMADA_370_XP_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
                .pfn            = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
                .length         = ARMADA_370_XP_REGS_SIZE,
                .type           = MT_DEVICE,
diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 25f0ca8d7820..aac9bebc6b03 100644
--- a/arch/arm/mach-mvebu/include/mach/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -16,7 +16,7 @@
 #define __MACH_ARMADA_370_XP_H
 #define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE    0xfeb00000
+#define ARMADA_370_XP_REGS_VIRT_BASE    IOMEM(0xfeb00000)
 #define ARMADA_370_XP_REGS_SIZE         SZ_1M
 #endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/gpio.h b/arch/arm/mach-mvebu/include/mach/gpio.h
index 40a8c178f10d..40a8c178f10d 100644
--- a/arch/arm/mach-ep93xx/include/mach/gpio.h
+++ b/arch/arm/mach-mvebu/include/mach/gpio.h
diff --git a/arch/arm/mach-mvebu/include/mach/timex.h b/arch/arm/mach-mvebu/include/mach/timex.h
deleted file mode 100644
index ab324a3748f2..000000000000
--- a/arch/arm/mach-mvebu/include/mach/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Marvell Armada SoC time definitions
- *
- * Copyright (C) 2012 Marvell
- *
- * Lior Amsalem <alior@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-mvebu/include/mach/uncompress.h b/arch/arm/mach-mvebu/include/mach/uncompress.h
deleted file mode 100644
index d6a100ccf302..000000000000
--- a/arch/arm/mach-mvebu/include/mach/uncompress.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Marvell Armada SoC kernel uncompression UART routines
- *
- * Copyright (C) 2012 Marvell
- *
- * Lior Amsalem <alior@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/armada-370-xp.h>
-#define UART_THR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
-                                                                + 0x12000))
-#define UART_LSR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
-                                                                + 0x12014))
-#define LSR_THRE        0x20
-static void putc(const char c)
-{
-        int i;
-        for (i = 0; i < 0x1000; i++) {
-                /* Transmit fifo not full? */
-                if (*UART_LSR & LSR_THRE)
-                        break;
-        }
-        *UART_THR = c;
-}
-static void flush(void)
-{
-}
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 9a8bbda195b2..ecc431909d6f 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -1,7 +1,5 @@
 if ARCH_MXS
-source "arch/arm/mach-mxs/devices/Kconfig"
 config SOC_IMX23
        bool
        select ARM_AMBA
@@ -27,91 +25,4 @@ config MACH_MXS_DT
          Include support for Freescale MXS platforms(i.MX23 and i.MX28)
          using the device tree for discovery
-config MACH_STMP378X_DEVB
-        bool "Support STMP378x_devb Platform"
-        select SOC_IMX23
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-        help
-          Include support for STMP378x-devb platform. This includes specific
-          configurations for the board and its peripherals.
-config MACH_MX23EVK
-        bool "Support MX23EVK Platform"
-        select SOC_IMX23
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXSFB
-        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-        help
-          Include support for MX23EVK platform. This includes specific
-          configurations for the board and its peripherals.
-config MACH_MX28EVK
-        bool "Support MX28EVK Platform"
-        select SOC_IMX28
-        select LEDS_GPIO_REGISTER
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_FEC
-        select MXS_HAVE_PLATFORM_FLEXCAN
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXSFB
-        select MXS_HAVE_PLATFORM_MXS_SAIF
-        select MXS_HAVE_PLATFORM_MXS_I2C
-        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-        help
-          Include support for MX28EVK platform. This includes specific
-          configurations for the board and its peripherals.
-config MODULE_TX28
-        bool
-        select SOC_IMX28
-        select LEDS_GPIO_REGISTER
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_FEC
-        select MXS_HAVE_PLATFORM_MXS_I2C
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXS_PWM
-        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-config MODULE_M28
-        bool
-        select SOC_IMX28
-        select LEDS_GPIO_REGISTER
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_FEC
-        select MXS_HAVE_PLATFORM_FLEXCAN
-        select MXS_HAVE_PLATFORM_MXS_I2C
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXSFB
-config MODULE_APX4
-        bool
-        select SOC_IMX28
-        select LEDS_GPIO_REGISTER
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_FEC
-        select MXS_HAVE_PLATFORM_MXS_I2C
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXS_SAIF
-config MACH_TX28
-        bool "Ka-Ro TX28 module"
-        select MODULE_TX28
-config MACH_M28EVK
-        bool "Support DENX M28EVK Platform"
-        select MODULE_M28
-config MACH_APX4DEVKIT
-        bool "Support Bluegiga APX4 Development Kit"
-        select MODULE_APX4
 endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index fed3695a1339..3d3c8a973062 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,15 +1,6 @@
 # Common support
-obj-y := devices.o icoll.o iomux.o ocotp.o system.o timer.o mm.o
+obj-y := icoll.o ocotp.o system.o timer.o mm.o
 obj-$(CONFIG_PM) += pm.o
 obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
-obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
-obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
-obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
-obj-$(CONFIG_MACH_M28EVK)    += mach-m28evk.o
-obj-$(CONFIG_MACH_APX4DEVKIT) += mach-apx4devkit.o
-obj-$(CONFIG_MODULE_TX28) += module-tx28.o
-obj-$(CONFIG_MACH_TX28)    += mach-tx28.o
-obj-y += devices/
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot
index 4582999cf080..07b11fe6453f 100644
--- a/arch/arm/mach-mxs/Makefile.boot
+++ b/arch/arm/mach-mxs/Makefile.boot
@@ -1,10 +1 @@
 zreladdr-y += 0x40008000
-dtb-y += imx23-evk.dtb \
-         imx23-olinuxino.dtb \
-         imx23-stmp378x_devb.dtb \
-         imx28-apx4devkit.dtb \
-         imx28-cfa10036.dtb \
-         imx28-evk.dtb \
-         imx28-m28evk.dtb \
-         imx28-tx28.dtb \
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
deleted file mode 100644
index 9ee5cede3d42..000000000000
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx23.h>
-#include <mach/devices-common.h>
-#include <linux/mxsfb.h>
-#include <linux/amba/bus.h>
-static inline int mx23_add_duart(void)
-{
-        struct amba_device *d;
-        d = amba_ahb_device_add(NULL, "duart", MX23_DUART_BASE_ADDR, SZ_8K,
-                                MX23_INT_DUART, 0, 0, 0);
-        return IS_ERR(d) ? PTR_ERR(d) : 0;
-}
-extern const struct mxs_auart_data mx23_auart_data[] __initconst;
-#define mx23_add_auart(id)      mxs_add_auart(&mx23_auart_data[id])
-#define mx23_add_auart0()               mx23_add_auart(0)
-#define mx23_add_auart1()               mx23_add_auart(1)
-extern const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst;
-#define mx23_add_gpmi_nand(pdata)       \
-        mxs_add_gpmi_nand(pdata, &mx23_gpmi_nand_data)
-extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst;
-#define mx23_add_mxs_mmc(id, pdata) \
-        mxs_add_mxs_mmc(&mx23_mxs_mmc_data[id], pdata)
-#define mx23_add_mxs_pwm(id)            mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id)
-struct platform_device *__init mx23_add_mxsfb(
-                const struct mxsfb_platform_data *pdata);
-struct platform_device *__init mx23_add_rtc_stmp3xxx(void);
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
deleted file mode 100644
index fcab431060f4..000000000000
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#include <linux/mxsfb.h>
-#include <linux/amba/bus.h>
-static inline int mx28_add_duart(void)
-{
-        struct amba_device *d;
-        d = amba_ahb_device_add(NULL, "duart", MX28_DUART_BASE_ADDR, SZ_8K,
-                                MX28_INT_DUART, 0, 0, 0);
-        return IS_ERR(d) ? PTR_ERR(d) : 0;
-}
-extern const struct mxs_auart_data mx28_auart_data[] __initconst;
-#define mx28_add_auart(id)      mxs_add_auart(&mx28_auart_data[id])
-#define mx28_add_auart0()               mx28_add_auart(0)
-#define mx28_add_auart1()               mx28_add_auart(1)
-#define mx28_add_auart2()               mx28_add_auart(2)
-#define mx28_add_auart3()               mx28_add_auart(3)
-#define mx28_add_auart4()               mx28_add_auart(4)
-extern const struct mxs_fec_data mx28_fec_data[] __initconst;
-#define mx28_add_fec(id, pdata) \
-        mxs_add_fec(&mx28_fec_data[id], pdata)
-extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
-#define mx28_add_flexcan(id, pdata)     \
-        mxs_add_flexcan(&mx28_flexcan_data[id], pdata)
-#define mx28_add_flexcan0(pdata)        mx28_add_flexcan(0, pdata)
-#define mx28_add_flexcan1(pdata)        mx28_add_flexcan(1, pdata)
-extern const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst;
-#define mx28_add_gpmi_nand(pdata)       \
-        mxs_add_gpmi_nand(pdata, &mx28_gpmi_nand_data)
-extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
-#define mx28_add_mxs_i2c(id)            mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
-extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst;
-#define mx28_add_mxs_mmc(id, pdata) \
-        mxs_add_mxs_mmc(&mx28_mxs_mmc_data[id], pdata)
-#define mx28_add_mxs_pwm(id)            mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id)
-struct platform_device *__init mx28_add_mxsfb(
-                const struct mxsfb_platform_data *pdata);
-extern const struct mxs_saif_data mx28_saif_data[] __initconst;
-#define mx28_add_saif(id, pdata) \
-        mxs_add_saif(&mx28_saif_data[id], pdata)
-struct platform_device *__init mx28_add_rtc_stmp3xxx(void);
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
deleted file mode 100644
index cf50b5a66dda..000000000000
--- a/arch/arm/mach-mxs/devices.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-struct platform_device *__init mxs_add_platform_device_dmamask(
-                const char *name, int id,
-                const struct resource *res, unsigned int num_resources,
-                const void *data, size_t size_data, u64 dmamask)
-{
-        int ret = -ENOMEM;
-        struct platform_device *pdev;
-        pdev = platform_device_alloc(name, id);
-        if (!pdev)
-                goto err;
-        if (dmamask) {
-                /*
-                 * This memory isn't freed when the device is put,
-                 * I don't have a nice idea for that though.  Conceptually
-                 * dma_mask in struct device should not be a pointer.
-                 * See http://thread.gmane.org/gmane.linux.kernel.pci/9081
-                 */
-                pdev->dev.dma_mask =
-                        kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
-                if (!pdev->dev.dma_mask)
-                        /* ret is still -ENOMEM; */
-                        goto err;
-                *pdev->dev.dma_mask = dmamask;
-                pdev->dev.coherent_dma_mask = dmamask;
-        }
-        if (res) {
-                ret = platform_device_add_resources(pdev, res, num_resources);
-                if (ret)
-                        goto err;
-        }
-        if (data) {
-                ret = platform_device_add_data(pdev, data, size_data);
-                if (ret)
-                        goto err;
-        }
-        ret = platform_device_add(pdev);
-        if (ret) {
-err:
-                if (dmamask)
-                        kfree(pdev->dev.dma_mask);
-                platform_device_put(pdev);
-                return ERR_PTR(ret);
-        }
-        return pdev;
-}
-struct device mxs_apbh_bus = {
-        .init_name      = "mxs_apbh",
-        .parent         = &platform_bus,
-};
-static int __init mxs_device_init(void)
-{
-        return device_register(&mxs_apbh_bus);
-}
-core_initcall(mxs_device_init);
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
deleted file mode 100644
index 19659de1c4e8..000000000000
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-config MXS_HAVE_AMBA_DUART
-        bool
-config MXS_HAVE_PLATFORM_AUART
-        bool
-config MXS_HAVE_PLATFORM_FEC
-        bool
-config MXS_HAVE_PLATFORM_FLEXCAN
-        select HAVE_CAN_FLEXCAN if CAN
-        bool
-config MXS_HAVE_PLATFORM_GPMI_NAND
-        bool
-config MXS_HAVE_PLATFORM_MXS_I2C
-        bool
-config MXS_HAVE_PLATFORM_MXS_MMC
-        bool
-config MXS_HAVE_PLATFORM_MXS_PWM
-        bool
-config MXS_HAVE_PLATFORM_MXSFB
-        bool
-config MXS_HAVE_PLATFORM_MXS_SAIF
-        bool
-config MXS_HAVE_PLATFORM_RTC_STMP3XXX
-        bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
deleted file mode 100644
index 5f72d9787444..000000000000
--- a/arch/arm/mach-mxs/devices/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
-obj-y += platform-dma.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_GPMI_NAND) += platform-gpmi-nand.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
-obj-y += platform-gpio-mxs.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_SAIF) += platform-mxs-saif.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_RTC_STMP3XXX) += platform-rtc-stmp3xxx.o
diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c
deleted file mode 100644
index 27608f5d2ac8..000000000000
--- a/arch/arm/mach-mxs/devices/platform-auart.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#define mxs_auart_data_entry_single(soc, _id, hwid)                     \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _AUART ## hwid ## _BASE_ADDR,          \
-                .irq = soc ## _INT_AUART ## hwid,                       \
-        }
-#define mxs_auart_data_entry(soc, _id, hwid)                            \
-        [_id] = mxs_auart_data_entry_single(soc, _id, hwid)
-#ifdef CONFIG_SOC_IMX23
-const struct mxs_auart_data mx23_auart_data[] __initconst = {
-#define mx23_auart_data_entry(_id, hwid)                                \
-        mxs_auart_data_entry(MX23, _id, hwid)
-        mx23_auart_data_entry(0, 1),
-        mx23_auart_data_entry(1, 2),
-};
-#endif
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_auart_data mx28_auart_data[] __initconst = {
-#define mx28_auart_data_entry(_id)                                      \
-        mxs_auart_data_entry(MX28, _id, _id)
-        mx28_auart_data_entry(0),
-        mx28_auart_data_entry(1),
-        mx28_auart_data_entry(2),
-        mx28_auart_data_entry(3),
-        mx28_auart_data_entry(4),
-};
-#endif
-struct platform_device *__init mxs_add_auart(
-                const struct mxs_auart_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return mxs_add_platform_device_dmamask("mxs-auart", data->id,
-                                        res, ARRAY_SIZE(res), NULL, 0,
-                                        DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c
deleted file mode 100644
index 46824501de00..000000000000
--- a/arch/arm/mach-mxs/devices/platform-dma.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/compiler.h>
-#include <linux/dma-mapping.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-struct platform_device *__init mxs_add_dma(const char *devid,
-                                                resource_size_t base)
-{
-        struct resource res[] = {
-                {
-                        .start = base,
-                        .end = base + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }
-        };
-        return mxs_add_platform_device_dmamask(devid, -1,
-                                res, ARRAY_SIZE(res), NULL, 0,
-                                DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c
deleted file mode 100644
index ae96a4fd8f14..000000000000
--- a/arch/arm/mach-mxs/devices/platform-fec.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#define mxs_fec_data_entry_single(soc, _id)                             \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _ENET_MAC ## _id ## _BASE_ADDR,        \
-                .irq = soc ## _INT_ENET_MAC ## _id,                     \
-        }
-#define mxs_fec_data_entry(soc, _id)                                    \
-        [_id] = mxs_fec_data_entry_single(soc, _id)
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_fec_data mx28_fec_data[] __initconst = {
-#define mx28_fec_data_entry(_id)                                        \
-        mxs_fec_data_entry(MX28, _id)
-        mx28_fec_data_entry(0),
-        mx28_fec_data_entry(1),
-};
-#endif
-struct platform_device *__init mxs_add_fec(
-                const struct mxs_fec_data *data,
-                const struct fec_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_16K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return mxs_add_platform_device_dmamask("imx28-fec", data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
-                        DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-flexcan.c b/arch/arm/mach-mxs/devices/platform-flexcan.c
deleted file mode 100644
index 43a6b4bae6fe..000000000000
--- a/arch/arm/mach-mxs/devices/platform-flexcan.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2010, 2011 Pengutronix,
- *                          Marc Kleine-Budde <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#define mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)           \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR,           \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_CAN ## _hwid,                        \
-        }
-#define mxs_flexcan_data_entry(soc, _id, _hwid, _size)                  \
-        [_id] = mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_flexcan_data mx28_flexcan_data[] __initconst = {
-#define mx28_flexcan_data_entry(_id, _hwid)                             \
-        mxs_flexcan_data_entry_single(MX28, _id, _hwid, SZ_8K)
-        mx28_flexcan_data_entry(0, 0),
-        mx28_flexcan_data_entry(1, 1),
-};
-#endif /* ifdef CONFIG_SOC_IMX28 */
-struct platform_device *__init mxs_add_flexcan(
-                const struct mxs_flexcan_data *data,
-                const struct flexcan_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return mxs_add_platform_device("flexcan", data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c b/arch/arm/mach-mxs/devices/platform-gpio-mxs.c
deleted file mode 100644
index cd99f19ec637..000000000000
--- a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/compiler.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-struct platform_device *__init mxs_add_gpio(
-        char *name, int id, resource_size_t iobase, int irq)
-{
-        struct resource res[] = {
-                {
-                        .start = iobase,
-                        .end = iobase + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = irq,
-                        .end = irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return platform_device_register_resndata(&mxs_apbh_bus,
-                        name, id, res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c b/arch/arm/mach-mxs/devices/platform-gpmi-nand.c
deleted file mode 100644
index 3e22df5944a8..000000000000
--- a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#include <linux/dma-mapping.h>
-#ifdef CONFIG_SOC_IMX23
-const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst = {
-        .devid = "imx23-gpmi-nand",
-        .res = {
-                /* GPMI */
-                DEFINE_RES_MEM_NAMED(MX23_GPMI_BASE_ADDR, SZ_8K,
-                                        GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
-                DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_ATTENTION,
-                                        GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
-                /* BCH */
-                DEFINE_RES_MEM_NAMED(MX23_BCH_BASE_ADDR, SZ_8K,
-                                        GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
-                DEFINE_RES_IRQ_NAMED(MX23_INT_BCH,
-                                        GPMI_NAND_BCH_INTERRUPT_RES_NAME),
-                /* DMA */
-                DEFINE_RES_NAMED(MX23_DMA_GPMI0,
-                                        MX23_DMA_GPMI3 - MX23_DMA_GPMI0 + 1,
-                                        GPMI_NAND_DMA_CHANNELS_RES_NAME,
-                                        IORESOURCE_DMA),
-                DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_DMA,
-                                        GPMI_NAND_DMA_INTERRUPT_RES_NAME),
-        },
-};
-#endif
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst = {
-        .devid = "imx28-gpmi-nand",
-        .res = {
-                /* GPMI */
-                DEFINE_RES_MEM_NAMED(MX28_GPMI_BASE_ADDR, SZ_8K,
-                                        GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
-                DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI,
-                                        GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
-                /* BCH */
-                DEFINE_RES_MEM_NAMED(MX28_BCH_BASE_ADDR, SZ_8K,
-                                        GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
-                DEFINE_RES_IRQ_NAMED(MX28_INT_BCH,
-                                        GPMI_NAND_BCH_INTERRUPT_RES_NAME),
-                /* DMA */
-                DEFINE_RES_NAMED(MX28_DMA_GPMI0,
-                                        MX28_DMA_GPMI7 - MX28_DMA_GPMI0 + 1,
-                                        GPMI_NAND_DMA_CHANNELS_RES_NAME,
-                                        IORESOURCE_DMA),
-                DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI_DMA,
-                                        GPMI_NAND_DMA_INTERRUPT_RES_NAME),
-        },
-};
-#endif
-struct platform_device *__init
-mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata,
-                const struct mxs_gpmi_nand_data *data)
-{
-        return mxs_add_platform_device_dmamask(data->devid, -1,
-                                data->res, GPMI_NAND_RES_SIZE,
-                                pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
deleted file mode 100644
index 79222ec8ede1..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2011 Pengutronix
- * Wolfram Sang <w.sang@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#define mxs_i2c_data_entry_single(soc, _id)                             \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _I2C ## _id ## _BASE_ADDR,             \
-                .errirq = soc ## _INT_I2C ## _id ## _ERROR,             \
-                .dmairq = soc ## _INT_I2C ## _id ## _DMA,               \
-        }
-#define mxs_i2c_data_entry(soc, _id)                                    \
-        [_id] = mxs_i2c_data_entry_single(soc, _id)
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
-        mxs_i2c_data_entry(MX28, 0),
-        mxs_i2c_data_entry(MX28, 1),
-};
-#endif
-struct platform_device *__init mxs_add_mxs_i2c(
-                const struct mxs_mxs_i2c_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->errirq,
-                        .end = data->errirq,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->dmairq,
-                        .end = data->dmairq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return mxs_add_platform_device("mxs-i2c", data->id, res,
-                                        ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
deleted file mode 100644
index b33c9d05c552..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/compiler.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#define mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid)           \
-        {                                                               \
-                .devid = _devid,                                        \
-                .id = _id,                                              \
-                .iobase = soc ## _SSP ## hwid ## _BASE_ADDR,            \
-                .dma = soc ## _DMA_SSP ## hwid,                         \
-                .irq_err = soc ## _INT_SSP ## hwid ## _ERROR,           \
-                .irq_dma = soc ## _INT_SSP ## hwid ## _DMA,             \
-        }
-#define mxs_mxs_mmc_data_entry(soc, _devid, _id, hwid)                  \
-        [_id] = mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid)
-#ifdef CONFIG_SOC_IMX23
-const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = {
-        mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 0, 1),
-        mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 1, 2),
-};
-#endif
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = {
-        mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 0, 0),
-        mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 1, 1),
-        mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 2, 2),
-        mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 3, 3),
-};
-#endif
-struct platform_device *__init mxs_add_mxs_mmc(
-                const struct mxs_mxs_mmc_data *data,
-                const struct mxs_mmc_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start  = data->iobase,
-                        .end    = data->iobase + SZ_8K - 1,
-                        .flags  = IORESOURCE_MEM,
-                }, {
-                        .start  = data->dma,
-                        .end    = data->dma,
-                        .flags  = IORESOURCE_DMA,
-                }, {
-                        .start  = data->irq_err,
-                        .end    = data->irq_err,
-                        .flags  = IORESOURCE_IRQ,
-                }, {
-                        .start  = data->irq_dma,
-                        .end    = data->irq_dma,
-                        .flags  = IORESOURCE_IRQ,
-                },
-        };
-        return mxs_add_platform_device(data->devid, data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
deleted file mode 100644
index 680f5a902936..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/devices-common.h>
-struct platform_device *__init mxs_add_mxs_pwm(resource_size_t iobase, int id)
-{
-        struct resource res = {
-                .flags = IORESOURCE_MEM,
-        };
-        res.start = iobase + 0x10 + 0x20 * id;
-        res.end = res.start + 0x1f;
-        return mxs_add_platform_device("mxs-pwm", id, &res, 1, NULL, 0);
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-saif.c b/arch/arm/mach-mxs/devices/platform-mxs-saif.c
deleted file mode 100644
index f6e3a60b4201..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-saif.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/compiler.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#define mxs_saif_data_entry_single(soc, _id)                            \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _SAIF ## _id ## _BASE_ADDR,            \
-                .irq = soc ## _INT_SAIF ## _id,                         \
-                .dma = soc ## _DMA_SAIF ## _id,                         \
-                .dmairq = soc ## _INT_SAIF ## _id ##_DMA,               \
-        }
-#define mxs_saif_data_entry(soc, _id)                                   \
-        [_id] = mxs_saif_data_entry_single(soc, _id)
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_saif_data mx28_saif_data[] __initconst = {
-        mxs_saif_data_entry(MX28, 0),
-        mxs_saif_data_entry(MX28, 1),
-};
-#endif
-struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data,
-                                const struct mxs_saif_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->dma,
-                        .end = data->dma,
-                        .flags = IORESOURCE_DMA,
-                }, {
-                        .start = data->dmairq,
-                        .end = data->dmairq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return mxs_add_platform_device("mxs-saif", data->id, res,
-                                ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c
deleted file mode 100644
index 76b53f73418e..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxsfb.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#include <linux/mxsfb.h>
-#ifdef CONFIG_SOC_IMX23
-struct platform_device *__init mx23_add_mxsfb(
-                const struct mxsfb_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = MX23_LCDIF_BASE_ADDR,
-                        .end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-        };
-        return mxs_add_platform_device_dmamask("imx23-fb", -1,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
-#endif /* ifdef CONFIG_SOC_IMX23 */
-#ifdef CONFIG_SOC_IMX28
-struct platform_device *__init mx28_add_mxsfb(
-                const struct mxsfb_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = MX28_LCDIF_BASE_ADDR,
-                        .end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-        };
-        return mxs_add_platform_device_dmamask("imx28-fb", -1,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
-#endif /* ifdef CONFIG_SOC_IMX28 */
diff --git a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c b/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c
deleted file mode 100644
index 639eaee15553..000000000000
--- a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2011 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#ifdef CONFIG_SOC_IMX23
-struct platform_device *__init mx23_add_rtc_stmp3xxx(void)
-{
-        struct resource res[] = {
-                {
-                        .start = MX23_RTC_BASE_ADDR,
-                        .end = MX23_RTC_BASE_ADDR + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = MX23_INT_RTC_ALARM,
-                        .end = MX23_INT_RTC_ALARM,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res),
-                                        NULL, 0);
-}
-#endif /* CONFIG_SOC_IMX23 */
-#ifdef CONFIG_SOC_IMX28
-struct platform_device *__init mx28_add_rtc_stmp3xxx(void)
-{
-        struct resource res[] = {
-                {
-                        .start = MX28_RTC_BASE_ADDR,
-                        .end = MX28_RTC_BASE_ADDR + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = MX28_INT_RTC_ALARM,
-                        .end = MX28_INT_RTC_ALARM,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res),
-                                        NULL, 0);
-}
-#endif /* CONFIG_SOC_IMX28 */
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c
index 23ca9d083b2c..8fb23af154b3 100644
--- a/arch/arm/mach-mxs/icoll.c
+++ b/arch/arm/mach-mxs/icoll.c
@@ -19,20 +19,27 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <asm/exception.h>
 #include <mach/mxs.h>
 #include <mach/common.h>
 #define HW_ICOLL_VECTOR                         0x0000
 #define HW_ICOLL_LEVELACK                       0x0010
 #define HW_ICOLL_CTRL                           0x0020
+#define HW_ICOLL_STAT_OFFSET                    0x0070
 #define HW_ICOLL_INTERRUPTn_SET(n)              (0x0124 + (n) * 0x10)
 #define HW_ICOLL_INTERRUPTn_CLR(n)              (0x0128 + (n) * 0x10)
 #define BM_ICOLL_INTERRUPTn_ENABLE              0x00000004
 #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
+#define ICOLL_NUM_IRQS          128
 static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR);
+static struct irq_domain *icoll_domain;
 static void icoll_ack_irq(struct irq_data *d)
 {
@@ -48,13 +55,13 @@ static void icoll_ack_irq(struct irq_data *d)
 static void icoll_mask_irq(struct irq_data *d)
 {
        __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
-                        icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->irq));
+                        icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->hwirq));
 }
 static void icoll_unmask_irq(struct irq_data *d)
 {
        __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
-                        icoll_base + HW_ICOLL_INTERRUPTn_SET(d->irq));
+                        icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq));
 }
 static struct irq_chip mxs_icoll_chip = {
@@ -63,18 +70,56 @@ static struct irq_chip mxs_icoll_chip = {
        .irq_unmask = icoll_unmask_irq,
 };
-void __init icoll_init_irq(void)
+asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
 {
-        int i;
+        u32 irqnr;
+        do {
+                irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
+                if (irqnr != 0x7f) {
+                        __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
+                        irqnr = irq_find_mapping(icoll_domain, irqnr);
+                        handle_IRQ(irqnr, regs);
+                        continue;
+                }
+                break;
+        } while (1);
+}
+static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
+                                irq_hw_number_t hw)
+{
+        irq_set_chip_and_handler(virq, &mxs_icoll_chip, handle_level_irq);
+        set_irq_flags(virq, IRQF_VALID);
+        return 0;
+}
+static struct irq_domain_ops icoll_irq_domain_ops = {
+        .map = icoll_irq_domain_map,
+        .xlate = irq_domain_xlate_onecell,
+};
+void __init icoll_of_init(struct device_node *np,
+                          struct device_node *interrupt_parent)
+{
        /*
         * Interrupt Collector reset, which initializes the priority
         * for each irq to level 0.
         */
        mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
-        for (i = 0; i < MXS_INTERNAL_IRQS; i++) {
+        icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS,
-                irq_set_chip_and_handler(i, &mxs_icoll_chip, handle_level_irq);
+                                             &icoll_irq_domain_ops, NULL);
-                set_irq_flags(i, IRQF_VALID);
+        WARN_ON(!icoll_domain);
-        }
+}
+static const struct of_device_id icoll_of_match[] __initconst = {
+        {.compatible = "fsl,icoll", .data = icoll_of_init},
+        { /* sentinel */ }
+};
+void __init icoll_init_irq(void)
+{
+        of_irq_init(icoll_of_match);
 }
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index de6c7ba42544..be5a9c93cb2a 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -13,25 +13,17 @@
 extern const u32 *mxs_get_ocotp(void);
 extern int mxs_reset_block(void __iomem *);
-extern void mxs_timer_init(int);
+extern void mxs_timer_init(void);
 extern void mxs_restart(char, const char *);
 extern int mxs_saif_clkmux_select(unsigned int clkmux);
-extern void mx23_soc_init(void);
 extern int mx23_clocks_init(void);
 extern void mx23_map_io(void);
-extern void mx23_init_irq(void);
-extern void mx28_soc_init(void);
 extern int mx28_clocks_init(void);
 extern void mx28_map_io(void);
-extern void mx28_init_irq(void);
 extern void icoll_init_irq(void);
+extern void icoll_handle_irq(struct pt_regs *);
-extern struct platform_device *mxs_add_dma(const char *devid,
-                                                resource_size_t base);
-extern struct platform_device *mxs_add_gpio(char *name, int id,
-                                            resource_size_t iobase, int irq);
 #endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
deleted file mode 100644
index e8b1d958240b..000000000000
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/init.h>
-#include <linux/amba/bus.h>
-extern struct device mxs_apbh_bus;
-struct platform_device *mxs_add_platform_device_dmamask(
-                const char *name, int id,
-                const struct resource *res, unsigned int num_resources,
-                const void *data, size_t size_data, u64 dmamask);
-static inline struct platform_device *mxs_add_platform_device(
-                const char *name, int id,
-                const struct resource *res, unsigned int num_resources,
-                const void *data, size_t size_data)
-{
-        return mxs_add_platform_device_dmamask(
-                        name, id, res, num_resources, data, size_data, 0);
-}
-/* auart */
-struct mxs_auart_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init mxs_add_auart(
-                const struct mxs_auart_data *data);
-/* fec */
-#include <linux/fec.h>
-struct mxs_fec_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init mxs_add_fec(
-                const struct mxs_fec_data *data,
-                const struct fec_platform_data *pdata);
-/* flexcan */
-#include <linux/can/platform/flexcan.h>
-struct mxs_flexcan_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init mxs_add_flexcan(
-                const struct mxs_flexcan_data *data,
-                const struct flexcan_platform_data *pdata);
-/* gpmi-nand */
-#include <linux/mtd/gpmi-nand.h>
-struct mxs_gpmi_nand_data {
-        const char *devid;
-        const struct resource res[GPMI_NAND_RES_SIZE];
-};
-struct platform_device *__init
-mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata,
-                const struct mxs_gpmi_nand_data *data);
-/* i2c */
-struct mxs_mxs_i2c_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t errirq;
-        resource_size_t dmairq;
-};
-struct platform_device * __init mxs_add_mxs_i2c(
-                const struct mxs_mxs_i2c_data *data);
-/* mmc */
-#include <linux/mmc/mxs-mmc.h>
-struct mxs_mxs_mmc_data {
-        const char *devid;
-        int id;
-        resource_size_t iobase;
-        resource_size_t dma;
-        resource_size_t irq_err;
-        resource_size_t irq_dma;
-};
-struct platform_device *__init mxs_add_mxs_mmc(
-                const struct mxs_mxs_mmc_data *data,
-                const struct mxs_mmc_platform_data *pdata);
-/* pwm */
-struct platform_device *__init mxs_add_mxs_pwm(
-                resource_size_t iobase, int id);
-/* saif */
-#include <sound/saif.h>
-struct mxs_saif_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t irq;
-        resource_size_t dma;
-        resource_size_t dmairq;
-};
-struct platform_device *__init mxs_add_saif(
-                const struct mxs_saif_data *data,
-                const struct mxs_saif_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-mxs/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
deleted file mode 100644
index b0190a4822f2..000000000000
--- a/arch/arm/mach-mxs/include/mach/iomux-mx23.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __MACH_IOMUX_MX23_H__
-#define __MACH_IOMUX_MX23_H__
-#include <mach/iomux.h>
-/*
- * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
- * See also iomux.h
- *
- *                                                                      BANK    PIN     MUX
- */
-/* MUXSEL_0 */
-#define MX23_PAD_GPMI_D00__GPMI_D00             MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D01__GPMI_D01             MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D02__GPMI_D02             MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D03__GPMI_D03             MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D04__GPMI_D04             MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D05__GPMI_D05             MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D06__GPMI_D06             MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D07__GPMI_D07             MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D08__GPMI_D08             MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D09__GPMI_D09             MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D10__GPMI_D10             MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D11__GPMI_D11             MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D12__GPMI_D12             MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D13__GPMI_D13             MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D14__GPMI_D14             MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D15__GPMI_D15             MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CLE__GPMI_CLE             MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_ALE__GPMI_ALE             MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CE2N__GPMI_CE2N           MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY0__GPMI_RDY0           MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY1__GPMI_RDY1           MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY2__GPMI_RDY2           MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY3__GPMI_RDY3           MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_WPN__GPMI_WPN             MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_WRN__GPMI_WRN             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDN__GPMI_RDN             MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_CTS__AUART1_CTS         MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_RTS__AUART1_RTS         MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_RX__AUART1_RX           MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_TX__AUART1_TX           MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0)
-#define MX23_PAD_I2C_SCL__I2C_SCL               MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0)
-#define MX23_PAD_I2C_SDA__I2C_SDA               MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D00__LCD_D00               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D01__LCD_D01               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D02__LCD_D02               MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D03__LCD_D03               MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D04__LCD_D04               MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D05__LCD_D05               MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D06__LCD_D06               MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D07__LCD_D07               MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D08__LCD_D08               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D09__LCD_D09               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D10__LCD_D10               MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D11__LCD_D11               MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D12__LCD_D12               MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D13__LCD_D13               MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D14__LCD_D14               MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D15__LCD_D15               MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D16__LCD_D16               MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D17__LCD_D17               MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_RESET__LCD_RESET           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_RS__LCD_RS                 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_WR__LCD_WR                 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_CS__LCD_CS                 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_DOTCK__LCD_DOTCK           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_ENABLE__LCD_ENABLE         MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_HSYNC__LCD_HSYNC           MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_VSYNC__LCD_VSYNC           MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
-#define MX23_PAD_PWM0__PWM0                     MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
-#define MX23_PAD_PWM1__PWM1                     MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
-#define MX23_PAD_PWM2__PWM2                     MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
-#define MX23_PAD_PWM3__PWM3                     MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
-#define MX23_PAD_PWM4__PWM4                     MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_CMD__SSP1_CMD             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DETECT__SSP1_DETECT       MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA0__SSP1_DATA0         MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA1__SSP1_DATA1         MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA2__SSP1_DATA2         MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA3__SSP1_DATA3         MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_SCK__SSP1_SCK             MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
-#define MX23_PAD_ROTARYA__ROTARYA               MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
-#define MX23_PAD_ROTARYB__ROTARYB               MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A00__EMI_A00               MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A01__EMI_A01               MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A02__EMI_A02               MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A03__EMI_A03               MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A04__EMI_A04               MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A05__EMI_A05               MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A06__EMI_A06               MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A07__EMI_A07               MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A08__EMI_A08               MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A09__EMI_A09               MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A10__EMI_A10               MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A11__EMI_A11               MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A12__EMI_A12               MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_BA0__EMI_BA0               MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_BA1__EMI_BA1               MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CASN__EMI_CASN             MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CE0N__EMI_CE0N             MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CE1N__EMI_CE1N             MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CE1N__GPMI_CE1N           MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CE0N__GPMI_CE0N           MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CKE__EMI_CKE               MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_RASN__EMI_RASN             MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_WEN__EMI_WEN               MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D00__EMI_D00               MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D01__EMI_D01               MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D02__EMI_D02               MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D03__EMI_D03               MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D04__EMI_D04               MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D05__EMI_D05               MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D06__EMI_D06               MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D07__EMI_D07               MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D08__EMI_D08               MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D09__EMI_D09               MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D10__EMI_D10               MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D11__EMI_D11               MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D12__EMI_D12               MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D13__EMI_D13               MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D14__EMI_D14               MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D15__EMI_D15               MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQM0__EMI_DQM0             MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQM1__EMI_DQM1             MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQS0__EMI_DQS0             MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQS1__EMI_DQS1             MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CLK__EMI_CLK               MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CLKN__EMI_CLKN             MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
-/* MUXSEL_1 */
-#define MX23_PAD_GPMI_D00__LCD_D8               MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D01__LCD_D9               MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D02__LCD_D10              MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D03__LCD_D11              MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D04__LCD_D12              MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D05__LCD_D13              MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D06__LCD_D14              MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D07__LCD_D15              MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D08__LCD_D18              MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D09__LCD_D19              MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D10__LCD_D20              MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D11__LCD_D21              MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D12__LCD_D22              MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D13__LCD_D23              MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D14__AUART2_RX            MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D15__AUART2_TX            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_CLE__LCD_D16              MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_ALE__LCD_D17              MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_CE2N__ATA_A2              MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
-#define MX23_PAD_AUART1_RTS__IR_CLK             MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
-#define MX23_PAD_AUART1_RX__IR_RX               MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
-#define MX23_PAD_AUART1_TX__IR_TX               MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1)
-#define MX23_PAD_I2C_SCL__GPMI_RDY2             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1)
-#define MX23_PAD_I2C_SDA__GPMI_CE2N             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D00__ETM_DA8               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D01__ETM_DA9               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D02__ETM_DA10              MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D03__ETM_DA11              MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D04__ETM_DA12              MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D05__ETM_DA13              MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D06__ETM_DA14              MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D07__ETM_DA15              MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D08__ETM_DA0               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D09__ETM_DA1               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D10__ETM_DA2               MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D11__ETM_DA3               MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D12__ETM_DA4               MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D13__ETM_DA5               MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D14__ETM_DA6               MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D15__ETM_DA7               MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_RESET__ETM_TCTL            MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_RS__ETM_TCLK               MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_DOTCK__GPMI_RDY3           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_ENABLE__I2C_SCL            MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_HSYNC__I2C_SDA             MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_VSYNC__LCD_BUSY            MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
-#define MX23_PAD_PWM0__ROTARYA                  MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
-#define MX23_PAD_PWM1__ROTARYB                  MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
-#define MX23_PAD_PWM2__GPMI_RDY3                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
-#define MX23_PAD_PWM3__ETM_TCTL                 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
-#define MX23_PAD_PWM4__ETM_TCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
-#define MX23_PAD_SSP1_DETECT__GPMI_CE3N         MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_1)
-#define MX23_PAD_SSP1_DATA1__I2C_SCL            MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_1)
-#define MX23_PAD_SSP1_DATA2__I2C_SDA            MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
-#define MX23_PAD_ROTARYA__AUART2_RTS            MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
-#define MX23_PAD_ROTARYB__AUART2_CTS            MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_1)
-/* MUXSEL_2 */
-#define MX23_PAD_GPMI_D00__SSP2_DATA0           MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D01__SSP2_DATA1           MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D02__SSP2_DATA2           MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D03__SSP2_DATA3           MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D04__SSP2_DATA4           MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D05__SSP2_DATA5           MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D06__SSP2_DATA6           MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D07__SSP2_DATA7           MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D08__SSP1_DATA4           MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D09__SSP1_DATA5           MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D10__SSP1_DATA6           MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D11__SSP1_DATA7           MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D15__GPMI_CE3N            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_RDY0__SSP2_DETECT         MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_RDY1__SSP2_CMD            MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_WRN__SSP2_SCK             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_CTS__SSP1_DATA4         MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_RTS__SSP1_DATA5         MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_RX__SSP1_DATA6          MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_TX__SSP1_DATA7          MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2)
-#define MX23_PAD_I2C_SCL__AUART1_TX             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2)
-#define MX23_PAD_I2C_SDA__AUART1_RX             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D08__SAIF2_SDATA0          MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D09__SAIF1_SDATA0          MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK      MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D11__SAIF_LRCLK            MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D12__SAIF2_SDATA1          MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D13__SAIF2_SDATA2          MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D14__SAIF1_SDATA2          MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D15__SAIF1_SDATA1          MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_RESET__GPMI_CE3N           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
-#define MX23_PAD_PWM0__DUART_RX                 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2)
-#define MX23_PAD_PWM1__DUART_TX                 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2)
-#define MX23_PAD_PWM3__AUART1_CTS               MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
-#define MX23_PAD_PWM4__AUART1_RTS               MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_CMD__JTAG_TDO             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DETECT__USB_OTG_ID        MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA0__JTAG_TDI           MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA1__JTAG_TCLK          MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA2__JTAG_RTCK          MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA3__JTAG_TMS           MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_SCK__JTAG_TRST            MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_2)
-#define MX23_PAD_ROTARYA__SPDIF                 MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_2)
-#define MX23_PAD_ROTARYB__GPMI_CE3N             MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_2)
-/* MUXSEL_GPIO */
-#define MX23_PAD_GPMI_D00__GPIO_0_0             MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D01__GPIO_0_1             MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D02__GPIO_0_2             MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D03__GPIO_0_3             MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D04__GPIO_0_4             MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D05__GPIO_0_5             MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D06__GPIO_0_6             MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D07__GPIO_0_7             MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D08__GPIO_0_8             MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D09__GPIO_0_9             MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D10__GPIO_0_10            MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D11__GPIO_0_11            MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D12__GPIO_0_12            MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D13__GPIO_0_13            MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D14__GPIO_0_14            MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D15__GPIO_0_15            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CLE__GPIO_0_16            MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_ALE__GPIO_0_17            MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE2N__GPIO_0_18           MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY0__GPIO_0_19           MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY1__GPIO_0_20           MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY2__GPIO_0_21           MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY3__GPIO_0_22           MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_WPN__GPIO_0_23            MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_WRN__GPIO_0_24            MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDN__GPIO_0_25            MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_CTS__GPIO_0_26          MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_RTS__GPIO_0_27          MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_RX__GPIO_0_28           MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_TX__GPIO_0_29           MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_I2C_SCL__GPIO_0_30             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_I2C_SDA__GPIO_0_31             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D00__GPIO_1_0              MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D01__GPIO_1_1              MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D02__GPIO_1_2              MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D03__GPIO_1_3              MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D04__GPIO_1_4              MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D05__GPIO_1_5              MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D06__GPIO_1_6              MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D07__GPIO_1_7              MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D08__GPIO_1_8              MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D09__GPIO_1_9              MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D10__GPIO_1_10             MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D11__GPIO_1_11             MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D12__GPIO_1_12             MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D13__GPIO_1_13             MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D14__GPIO_1_14             MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D15__GPIO_1_15             MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D16__GPIO_1_16             MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D17__GPIO_1_17             MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_RESET__GPIO_1_18           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_RS__GPIO_1_19              MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_WR__GPIO_1_20              MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_CS__GPIO_1_21              MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_DOTCK__GPIO_1_22           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_ENABLE__GPIO_1_23          MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_HSYNC__GPIO_1_24           MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_VSYNC__GPIO_1_25           MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM0__GPIO_1_26                MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM1__GPIO_1_27                MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM2__GPIO_1_28                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM3__GPIO_1_29                MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM4__GPIO_1_30                MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_CMD__GPIO_2_0             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DETECT__GPIO_2_1          MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA0__GPIO_2_2           MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA1__GPIO_2_3           MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA2__GPIO_2_4           MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA3__GPIO_2_5           MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_SCK__GPIO_2_6             MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_ROTARYA__GPIO_2_7              MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_ROTARYB__GPIO_2_8              MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A00__GPIO_2_9              MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A01__GPIO_2_10             MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A02__GPIO_2_11             MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A03__GPIO_2_12             MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A04__GPIO_2_13             MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A05__GPIO_2_14             MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A06__GPIO_2_15             MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A07__GPIO_2_16             MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A08__GPIO_2_17             MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A09__GPIO_2_18             MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A10__GPIO_2_19             MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A11__GPIO_2_20             MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A12__GPIO_2_21             MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_BA0__GPIO_2_22             MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_BA1__GPIO_2_23             MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CASN__GPIO_2_24            MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CE0N__GPIO_2_25            MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CE1N__GPIO_2_26            MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE1N__GPIO_2_27           MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE0N__GPIO_2_28           MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CKE__GPIO_2_29             MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_RASN__GPIO_2_30            MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_WEN__GPIO_2_31             MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
-#endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx28.h b/arch/arm/mach-mxs/include/mach/iomux-mx28.h
deleted file mode 100644
index f50fefd10520..000000000000
--- a/arch/arm/mach-mxs/include/mach/iomux-mx28.h
+++ /dev/null
@@ -1,537 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __MACH_IOMUX_MX28_H__
-#define __MACH_IOMUX_MX28_H__
-#include <mach/iomux.h>
-/*
- * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
- * See also iomux.h
- *
- *                                                                      BANK    PIN     MUX
- */
-/* MUXSEL_0 */
-#define MX28_PAD_GPMI_D00__GPMI_D0                      MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D01__GPMI_D1                      MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D02__GPMI_D2                      MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D03__GPMI_D3                      MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D04__GPMI_D4                      MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D05__GPMI_D5                      MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D06__GPMI_D6                      MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D07__GPMI_D7                      MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE0N__GPMI_CE0N                   MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE1N__GPMI_CE1N                   MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE2N__GPMI_CE2N                   MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE3N__GPMI_CE3N                   MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY0__GPMI_READY0                 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY1__GPMI_READY1                 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY2__GPMI_READY2                 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY3__GPMI_READY3                 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDN__GPMI_RDN                     MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_WRN__GPMI_WRN                     MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_ALE__GPMI_ALE                     MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CLE__GPMI_CLE                     MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RESETN__GPMI_RESETN               MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D00__LCD_D0                        MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D01__LCD_D1                        MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D02__LCD_D2                        MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D03__LCD_D3                        MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D04__LCD_D4                        MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D05__LCD_D5                        MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D06__LCD_D6                        MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D07__LCD_D7                        MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D08__LCD_D8                        MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D09__LCD_D9                        MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D10__LCD_D10                       MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D11__LCD_D11                       MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D12__LCD_D12                       MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D13__LCD_D13                       MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D14__LCD_D14                       MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D15__LCD_D15                       MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D16__LCD_D16                       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D17__LCD_D17                       MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D18__LCD_D18                       MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D19__LCD_D19                       MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D20__LCD_D20                       MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D21__LCD_D21                       MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D22__LCD_D22                       MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D23__LCD_D23                       MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_RD_E__LCD_RD_E                     MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN                 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_RS__LCD_RS                         MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_CS__LCD_CS                         MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_VSYNC__LCD_VSYNC                   MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_HSYNC__LCD_HSYNC                   MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_ENABLE__LCD_ENABLE                 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA0__SSP0_D0                    MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA1__SSP0_D1                    MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA2__SSP0_D2                    MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA3__SSP0_D3                    MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA4__SSP0_D4                    MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA5__SSP0_D5                    MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA6__SSP0_D6                    MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA7__SSP0_D7                    MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_CMD__SSP0_CMD                     MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT          MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_SCK__SSP0_SCK                     MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_SCK__SSP1_SCK                     MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_CMD__SSP1_CMD                     MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_DATA0__SSP1_D0                    MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_DATA3__SSP1_D3                    MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SCK__SSP2_SCK                     MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_MOSI__SSP2_CMD                    MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_MISO__SSP2_D0                     MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SS0__SSP2_D3                      MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SS1__SSP2_D4                      MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SS2__SSP2_D5                      MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_SCK__SSP3_SCK                     MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_MOSI__SSP3_CMD                    MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_MISO__SSP3_D0                     MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_SS0__SSP3_D3                      MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
-#define MX28_PAD_AUART0_RX__AUART0_RX                   MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
-#define MX28_PAD_AUART0_TX__AUART0_TX                   MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
-#define MX28_PAD_AUART0_CTS__AUART0_CTS                 MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
-#define MX28_PAD_AUART0_RTS__AUART0_RTS                 MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_RX__AUART1_RX                   MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_TX__AUART1_TX                   MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_CTS__AUART1_CTS                 MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_RTS__AUART1_RTS                 MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_RX__AUART2_RX                   MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_TX__AUART2_TX                   MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_CTS__AUART2_CTS                 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_RTS__AUART2_RTS                 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_RX__AUART3_RX                   MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_TX__AUART3_TX                   MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_CTS__AUART3_CTS                 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_RTS__AUART3_RTS                 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
-#define MX28_PAD_PWM0__PWM_0                            MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
-#define MX28_PAD_PWM1__PWM_1                            MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
-#define MX28_PAD_PWM2__PWM_2                            MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK                 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK               MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK             MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0             MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0)
-#define MX28_PAD_I2C0_SCL__I2C0_SCL                     MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0)
-#define MX28_PAD_I2C0_SDA__I2C0_SDA                     MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0             MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0)
-#define MX28_PAD_SPDIF__SPDIF_TX                        MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0)
-#define MX28_PAD_PWM3__PWM_3                            MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0)
-#define MX28_PAD_PWM4__PWM_4                            MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_RESET__LCD_RESET                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_MDC__ENET0_MDC                   MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_MDIO__ENET0_MDIO                 MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN               MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD0__ENET0_RXD0                 MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD1__ENET0_RXD1                 MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK             MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN               MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD0__ENET0_TXD0                 MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD1__ENET0_TXD1                 MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD2__ENET0_RXD2                 MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD3__ENET0_RXD3                 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD2__ENET0_TXD2                 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD3__ENET0_TXD3                 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK             MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_COL__ENET0_COL                   MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_CRS__ENET0_CRS                   MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0)
-#define MX28_PAD_ENET_CLK__CLKCTRL_ENET                 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0)
-#define MX28_PAD_JTAG_RTCK__JTAG_RTCK                   MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D00__EMI_DATA0                     MXS_IOMUX_PAD_NAKED(5,  0, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D01__EMI_DATA1                     MXS_IOMUX_PAD_NAKED(5,  1, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D02__EMI_DATA2                     MXS_IOMUX_PAD_NAKED(5,  2, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D03__EMI_DATA3                     MXS_IOMUX_PAD_NAKED(5,  3, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D04__EMI_DATA4                     MXS_IOMUX_PAD_NAKED(5,  4, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D05__EMI_DATA5                     MXS_IOMUX_PAD_NAKED(5,  5, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D06__EMI_DATA6                     MXS_IOMUX_PAD_NAKED(5,  6, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D07__EMI_DATA7                     MXS_IOMUX_PAD_NAKED(5,  7, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D08__EMI_DATA8                     MXS_IOMUX_PAD_NAKED(5,  8, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D09__EMI_DATA9                     MXS_IOMUX_PAD_NAKED(5,  9, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D10__EMI_DATA10                    MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D11__EMI_DATA11                    MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D12__EMI_DATA12                    MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D13__EMI_DATA13                    MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D14__EMI_DATA14                    MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D15__EMI_DATA15                    MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_ODT0__EMI_ODT0                     MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQM0__EMI_DQM0                     MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_ODT1__EMI_ODT1                     MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQM1__EMI_DQM1                     MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CLK__EMI_CLK                       MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQS0__EMI_DQS0                     MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQS1__EMI_DQS1                     MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN             MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A00__EMI_ADDR0                     MXS_IOMUX_PAD_NAKED(6,  0, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A01__EMI_ADDR1                     MXS_IOMUX_PAD_NAKED(6,  1, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A02__EMI_ADDR2                     MXS_IOMUX_PAD_NAKED(6,  2, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A03__EMI_ADDR3                     MXS_IOMUX_PAD_NAKED(6,  3, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A04__EMI_ADDR4                     MXS_IOMUX_PAD_NAKED(6,  4, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A05__EMI_ADDR5                     MXS_IOMUX_PAD_NAKED(6,  5, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A06__EMI_ADDR6                     MXS_IOMUX_PAD_NAKED(6,  6, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A07__EMI_ADDR7                     MXS_IOMUX_PAD_NAKED(6,  7, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A08__EMI_ADDR8                     MXS_IOMUX_PAD_NAKED(6,  8, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A09__EMI_ADDR9                     MXS_IOMUX_PAD_NAKED(6,  9, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A10__EMI_ADDR10                    MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A11__EMI_ADDR11                    MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A12__EMI_ADDR12                    MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A13__EMI_ADDR13                    MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A14__EMI_ADDR14                    MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_BA0__EMI_BA0                       MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_BA1__EMI_BA1                       MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_BA2__EMI_BA2                       MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CASN__EMI_CASN                     MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_RASN__EMI_RASN                     MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_WEN__EMI_WEN                       MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CE0N__EMI_CE0N                     MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CE1N__EMI_CE1N                     MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CKE__EMI_CKE                       MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0)
-/* MUXSEL_1 */
-#define MX28_PAD_GPMI_D00__SSP1_D0                      MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D01__SSP1_D1                      MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D02__SSP1_D2                      MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D03__SSP1_D3                      MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D04__SSP1_D4                      MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D05__SSP1_D5                      MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D06__SSP1_D6                      MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D07__SSP1_D7                      MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE0N__SSP3_D0                     MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE1N__SSP3_D3                     MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE2N__CAN1_TX                     MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE3N__CAN1_RX                     MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT            MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY1__SSP1_CMD                    MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY2__CAN0_TX                     MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY3__CAN0_RX                     MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDN__SSP3_SCK                     MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_WRN__SSP1_SCK                     MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_ALE__SSP3_D1                      MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CLE__SSP3_D2                      MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RESETN__SSP3_CMD                  MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D03__ETM_DA8                       MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D04__ETM_DA9                       MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D08__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D09__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT         MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN          MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT         MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN          MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_RD_E__LCD_VSYNC                    MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC                  MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_RS__LCD_DOTCLK                     MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_CS__LCD_ENABLE                     MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1                MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
-#define MX28_PAD_SSP0_DATA4__SSP2_D0                    MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
-#define MX28_PAD_SSP0_DATA5__SSP2_D3                    MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_1)
-#define MX28_PAD_SSP0_DATA6__SSP2_CMD                   MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_1)
-#define MX28_PAD_SSP0_DATA7__SSP2_SCK                   MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_SCK__SSP2_D1                      MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_CMD__SSP2_D2                      MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_DATA0__SSP2_D6                    MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_DATA3__SSP2_D7                    MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SCK__AUART2_RX                    MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_MOSI__AUART2_TX                   MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_MISO__AUART3_RX                   MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SS0__AUART3_TX                    MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SS1__SSP2_D1                      MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SS2__SSP2_D2                      MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_SCK__AUART4_TX                    MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_MOSI__AUART4_RX                   MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_MISO__AUART4_RTS                  MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_SS0__AUART4_CTS                   MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1)
-#define MX28_PAD_AUART0_RX__I2C0_SCL                    MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_1)
-#define MX28_PAD_AUART0_TX__I2C0_SDA                    MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_1)
-#define MX28_PAD_AUART0_CTS__AUART4_RX                  MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_1)
-#define MX28_PAD_AUART0_RTS__AUART4_TX                  MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT            MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT            MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT           MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_RTS__USB0_ID                    MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_RX__SSP3_D1                     MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_TX__SSP3_D2                     MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_CTS__I2C1_SCL                   MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_RTS__I2C1_SDA                   MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_RX__CAN0_TX                     MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_TX__CAN0_RX                     MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_CTS__CAN1_TX                    MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_RTS__CAN1_RX                    MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1)
-#define MX28_PAD_PWM0__I2C1_SCL                         MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1)
-#define MX28_PAD_PWM1__I2C1_SDA                         MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1)
-#define MX28_PAD_PWM2__USB0_ID                          MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_MCLK__PWM_3                      MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_LRCLK__PWM_4                     MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_BITCLK__PWM_5                    MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_SDATA0__PWM_6                    MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1)
-#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA               MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1)
-#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB               MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF1_SDATA0__PWM_7                    MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_RESET__LCD_VSYNC                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_MDC__GPMI_CE4N                   MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_MDIO__GPMI_CE5N                  MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N                 MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD0__GPMI_CE7N                  MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD1__GPMI_READY4                MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER            MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TX_EN__GPMI_READY5               MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD0__GPMI_READY6                MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD1__GPMI_READY7                MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD2__ENET1_RXD0                 MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD3__ENET1_RXD1                 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD2__ENET1_TXD0                 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD3__ENET1_TXD1                 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER              MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_COL__ENET1_TX_EN                 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_CRS__ENET1_RX_EN                 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1)
-/* MUXSEL_2 */
-#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER                 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK                  MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_RDY0__USB0_ID                     MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER                 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER               MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_ALE__SSP3_D4                      MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_CLE__SSP3_D5                      MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D00__ETM_DA0                       MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D01__ETM_DA1                       MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D02__ETM_DA2                       MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D03__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D04__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D05__ETM_DA5                       MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D06__ETM_DA6                       MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D07__ETM_DA7                       MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D08__ETM_DA8                       MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D09__ETM_DA9                       MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D10__ETM_DA10                      MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D11__ETM_DA11                      MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D12__ETM_DA12                      MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D13__ETM_DA13                      MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D14__ETM_DA14                      MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D15__ETM_DA15                      MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D16__ETM_DA7                       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D17__ETM_DA6                       MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D18__ETM_DA5                       MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D19__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D20__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D21__ETM_DA2                       MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D22__ETM_DA1                       MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D23__ETM_DA0                       MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_RD_E__ETM_TCTL                     MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_WR_RWN__ETM_TCLK                   MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_HSYNC__ETM_TCTL                    MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_DOTCLK__ETM_TCLK                   MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
-#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT        MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2)
-#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN         MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2)
-#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT      MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2)
-#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN       MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1                 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2                MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1                MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2                 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT             MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT             MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT        MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN        MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT       MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN         MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2)
-#define MX28_PAD_AUART0_RX__DUART_CTS                   MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_2)
-#define MX28_PAD_AUART0_TX__DUART_RTS                   MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_2)
-#define MX28_PAD_AUART0_CTS__DUART_RX                   MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_2)
-#define MX28_PAD_AUART0_RTS__DUART_TX                   MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_RX__PWM_0                       MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_TX__PWM_1                       MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA             MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB             MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_RX__SSP3_D4                     MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_TX__SSP3_D5                     MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK               MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK                MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT       MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN        MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT      MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN       MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2)
-#define MX28_PAD_PWM0__DUART_RX                         MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2)
-#define MX28_PAD_PWM1__DUART_TX                         MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2)
-#define MX28_PAD_PWM2__USB1_OVERCURRENT                 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_MCLK__AUART4_CTS                 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS                MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_BITCLK__AUART4_RX                MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_SDATA0__AUART4_TX                MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2)
-#define MX28_PAD_I2C0_SCL__DUART_RX                     MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2)
-#define MX28_PAD_I2C0_SDA__DUART_TX                     MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1             MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2)
-#define MX28_PAD_SPDIF__ENET1_RX_ER                     MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1                MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2               MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1              MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2               MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT    MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT      MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN       MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT      MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN       MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN     MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT       MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN        MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2)
-/* MUXSEL_GPIO */
-#define MX28_PAD_GPMI_D00__GPIO_0_0                     MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D01__GPIO_0_1                     MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D02__GPIO_0_2                     MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D03__GPIO_0_3                     MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D04__GPIO_0_4                     MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D05__GPIO_0_5                     MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D06__GPIO_0_6                     MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D07__GPIO_0_7                     MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE0N__GPIO_0_16                   MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE1N__GPIO_0_17                   MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE2N__GPIO_0_18                   MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE3N__GPIO_0_19                   MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY0__GPIO_0_20                   MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY1__GPIO_0_21                   MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY2__GPIO_0_22                   MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY3__GPIO_0_23                   MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDN__GPIO_0_24                    MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_WRN__GPIO_0_25                    MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_ALE__GPIO_0_26                    MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CLE__GPIO_0_27                    MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RESETN__GPIO_0_28                 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D00__GPIO_1_0                      MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D01__GPIO_1_1                      MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D02__GPIO_1_2                      MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D03__GPIO_1_3                      MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D04__GPIO_1_4                      MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D05__GPIO_1_5                      MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D06__GPIO_1_6                      MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D07__GPIO_1_7                      MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D08__GPIO_1_8                      MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D09__GPIO_1_9                      MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D10__GPIO_1_10                     MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D11__GPIO_1_11                     MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D12__GPIO_1_12                     MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D13__GPIO_1_13                     MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D14__GPIO_1_14                     MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D15__GPIO_1_15                     MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D16__GPIO_1_16                     MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D17__GPIO_1_17                     MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D18__GPIO_1_18                     MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D19__GPIO_1_19                     MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D20__GPIO_1_20                     MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D21__GPIO_1_21                     MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D22__GPIO_1_22                     MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D23__GPIO_1_23                     MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_RD_E__GPIO_1_24                    MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_WR_RWN__GPIO_1_25                  MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_RS__GPIO_1_26                      MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_CS__GPIO_1_27                      MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_VSYNC__GPIO_1_28                   MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_HSYNC__GPIO_1_29                   MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_DOTCLK__GPIO_1_30                  MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_ENABLE__GPIO_1_31                  MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA0__GPIO_2_0                   MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA1__GPIO_2_1                   MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA2__GPIO_2_2                   MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA3__GPIO_2_3                   MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA4__GPIO_2_4                   MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA5__GPIO_2_5                   MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA6__GPIO_2_6                   MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA7__GPIO_2_7                   MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_CMD__GPIO_2_8                     MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DETECT__GPIO_2_9                  MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_SCK__GPIO_2_10                    MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_SCK__GPIO_2_12                    MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_CMD__GPIO_2_13                    MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_DATA0__GPIO_2_14                  MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_DATA3__GPIO_2_15                  MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SCK__GPIO_2_16                    MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_MOSI__GPIO_2_17                   MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_MISO__GPIO_2_18                   MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SS0__GPIO_2_19                    MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SS1__GPIO_2_20                    MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SS2__GPIO_2_21                    MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_SCK__GPIO_2_24                    MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_MOSI__GPIO_2_25                   MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_MISO__GPIO_2_26                   MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_SS0__GPIO_2_27                    MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART0_RX__GPIO_3_0                    MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART0_TX__GPIO_3_1                    MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART0_CTS__GPIO_3_2                   MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART0_RTS__GPIO_3_3                   MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_RX__GPIO_3_4                    MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_TX__GPIO_3_5                    MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_CTS__GPIO_3_6                   MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_RTS__GPIO_3_7                   MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_RX__GPIO_3_8                    MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_TX__GPIO_3_9                    MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_CTS__GPIO_3_10                  MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_RTS__GPIO_3_11                  MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_RX__GPIO_3_12                   MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_TX__GPIO_3_13                   MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_CTS__GPIO_3_14                  MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_RTS__GPIO_3_15                  MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM0__GPIO_3_16                        MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM1__GPIO_3_17                        MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM2__GPIO_3_18                        MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_MCLK__GPIO_3_20                  MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21                 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22                MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23                MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO)
-#define MX28_PAD_I2C0_SCL__GPIO_3_24                    MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_I2C0_SDA__GPIO_3_25                    MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26                MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SPDIF__GPIO_3_27                       MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM3__GPIO_3_28                        MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM4__GPIO_3_29                        MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_RESET__GPIO_3_30                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_MDC__GPIO_4_0                    MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_MDIO__GPIO_4_1                   MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RX_EN__GPIO_4_2                  MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD0__GPIO_4_3                   MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD1__GPIO_4_4                   MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5                 MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TX_EN__GPIO_4_6                  MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD0__GPIO_4_7                   MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD1__GPIO_4_8                   MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD2__GPIO_4_9                   MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD3__GPIO_4_10                  MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD2__GPIO_4_11                  MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD3__GPIO_4_12                  MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13                MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_COL__GPIO_4_14                   MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_CRS__GPIO_4_15                   MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET_CLK__GPIO_4_16                    MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_JTAG_RTCK__GPIO_4_20                   MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO)
-#endif /* __MACH_IOMUX_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h
deleted file mode 100644
index 7abdf58b8bb7..000000000000
--- a/arch/arm/mach-mxs/include/mach/iomux.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- *                      <armlinux@phytec.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#ifndef __MACH_MXS_IOMUX_H__
-#define __MACH_MXS_IOMUX_H__
-/*
- * IOMUX/PAD Bit field definitions
- *
- * PAD_BANK:             0..2   (3)
- * PAD_PIN:              3..7   (5)
- * PAD_MUXSEL:           8..9   (2)
- * PAD_MA:              10..11  (2)
- * PAD_MA_VALID:        12      (1)
- * PAD_VOL:             13      (1)
- * PAD_VOL_VALID:       14      (1)
- * PAD_PULL:            15      (1)
- * PAD_PULL_VALID:      16      (1)
- * RESERVED:            17..31  (15)
- */
-typedef u32 iomux_cfg_t;
-#define MXS_PAD_BANK_SHIFT      0
-#define MXS_PAD_BANK_MASK       ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT)
-#define MXS_PAD_PIN_SHIFT       3
-#define MXS_PAD_PIN_MASK        ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT)
-#define MXS_PAD_MUXSEL_SHIFT    8
-#define MXS_PAD_MUXSEL_MASK     ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT)
-#define MXS_PAD_MA_SHIFT        10
-#define MXS_PAD_MA_MASK         ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT)
-#define MXS_PAD_MA_VALID_SHIFT  12
-#define MXS_PAD_MA_VALID_MASK   ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT)
-#define MXS_PAD_VOL_SHIFT       13
-#define MXS_PAD_VOL_MASK        ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT)
-#define MXS_PAD_VOL_VALID_SHIFT 14
-#define MXS_PAD_VOL_VALID_MASK  ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT)
-#define MXS_PAD_PULL_SHIFT      15
-#define MXS_PAD_PULL_MASK       ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT)
-#define MXS_PAD_PULL_VALID_SHIFT 16
-#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT)
-#define PAD_MUXSEL_0            0
-#define PAD_MUXSEL_1            1
-#define PAD_MUXSEL_2            2
-#define PAD_MUXSEL_GPIO         3
-#define PAD_4MA                 0
-#define PAD_8MA                 1
-#define PAD_12MA                2
-#define PAD_16MA                3
-#define PAD_1V8                 0
-#define PAD_3V3                 1
-#define PAD_NOPULL              0
-#define PAD_PULLUP              1
-#define MXS_PAD_4MA     ((PAD_4MA << MXS_PAD_MA_SHIFT) | \
-                                        MXS_PAD_MA_VALID_MASK)
-#define MXS_PAD_8MA     ((PAD_8MA << MXS_PAD_MA_SHIFT) | \
-                                        MXS_PAD_MA_VALID_MASK)
-#define MXS_PAD_12MA    ((PAD_12MA << MXS_PAD_MA_SHIFT) | \
-                                        MXS_PAD_MA_VALID_MASK)
-#define MXS_PAD_16MA    ((PAD_16MA << MXS_PAD_MA_SHIFT) | \
-                                        MXS_PAD_MA_VALID_MASK)
-#define MXS_PAD_1V8     ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \
-                                        MXS_PAD_VOL_VALID_MASK)
-#define MXS_PAD_3V3     ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \
-                                        MXS_PAD_VOL_VALID_MASK)
-#define MXS_PAD_NOPULL  ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \
-                                        MXS_PAD_PULL_VALID_MASK)
-#define MXS_PAD_PULLUP  ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
-                                        MXS_PAD_PULL_VALID_MASK)
-/* generic pad control used in most cases */
-#define MXS_PAD_CTRL    (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)
-#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull)           \
-                (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) |         \
-                ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) |            \
-                ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) |      \
-                ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) |              \
-                ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) |            \
-                ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT))
-/*
- * A pad becomes naked, when none of mA, vol or pull
- * validity bits is set.
- */
-#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \
-                MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0)
-static inline unsigned int PAD_BANK(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT;
-}
-static inline unsigned int PAD_PIN(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT;
-}
-static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT;
-}
-static inline unsigned int PAD_MA(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT;
-}
-static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT;
-}
-static inline unsigned int PAD_VOL(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT;
-}
-static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT;
-}
-static inline unsigned int PAD_PULL(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT;
-}
-static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT;
-}
-/*
- * configures a single pad in the iomuxer
- */
-int mxs_iomux_setup_pad(iomux_cfg_t pad);
-/*
- * configures multiple pads
- * convenient way to call the above function with tables
- */
-int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
-#endif /* __MACH_MXS_IOMUX_H__*/
diff --git a/arch/arm/mach-mxs/include/mach/irqs.h b/arch/arm/mach-mxs/include/mach/irqs.h
deleted file mode 100644
index f771039b814a..000000000000
--- a/arch/arm/mach-mxs/include/mach/irqs.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __MACH_MXS_IRQS_H__
-#define __MACH_MXS_IRQS_H__
-#define MXS_INTERNAL_IRQS       128
-#define MXS_GPIO_IRQ_START      MXS_INTERNAL_IRQS
-/* the maximum for MXS-based */
-#define MXS_GPIO_IRQS           (32 * 5)
-/*
- * The next 16 interrupts are for board specific purposes.  Since
- * the kernel can only run on one machine at a time, we can re-use
- * these.  If you need more, increase MXS_BOARD_IRQS, but keep it
- * within sensible limits.
- */
-#define MXS_BOARD_IRQ_START     (MXS_GPIO_IRQ_START + MXS_GPIO_IRQS)
-#define MXS_BOARD_IRQS          16
-#define NR_IRQS                 (MXS_BOARD_IRQ_START + MXS_BOARD_IRQS)
-#endif /* __MACH_MXS_IRQS_H__ */
diff --git a/arch/arm/mach-mxs/iomux.c b/arch/arm/mach-mxs/iomux.c
deleted file mode 100644
index 0e804e2f11f4..000000000000
--- a/arch/arm/mach-mxs/iomux.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- *                       <armlinux@phytec.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/gpio.h>
-#include <asm/mach/map.h>
-#include <mach/mxs.h>
-#include <mach/iomux.h>
-/*
- * configures a single pad in the iomuxer
- */
-int mxs_iomux_setup_pad(iomux_cfg_t pad)
-{
-        u32 reg, ofs, bp, bm;
-        void __iomem *iomux_base = MXS_IO_ADDRESS(MXS_PINCTRL_BASE_ADDR);
-        /* muxsel */
-        ofs = 0x100;
-        ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10;
-        bp = PAD_PIN(pad) % 16 * 2;
-        bm = 0x3 << bp;
-        reg = __raw_readl(iomux_base + ofs);
-        reg &= ~bm;
-        reg |= PAD_MUXSEL(pad) << bp;
-        __raw_writel(reg, iomux_base + ofs);
-        /* drive */
-        ofs = cpu_is_mx23() ? 0x200 : 0x300;
-        ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10;
-        /* mA */
-        if (PAD_MA_VALID(pad)) {
-                bp = PAD_PIN(pad) % 8 * 4;
-                bm = 0x3 << bp;
-                reg = __raw_readl(iomux_base + ofs);
-                reg &= ~bm;
-                reg |= PAD_MA(pad) << bp;
-                __raw_writel(reg, iomux_base + ofs);
-        }
-        /* vol */
-        if (PAD_VOL_VALID(pad)) {
-                bp = PAD_PIN(pad) % 8 * 4 + 2;
-                if (PAD_VOL(pad))
-                        __mxs_setl(1 << bp, iomux_base + ofs);
-                else
-                        __mxs_clrl(1 << bp, iomux_base + ofs);
-        }
-        /* pull */
-        if (PAD_PULL_VALID(pad)) {
-                ofs = cpu_is_mx23() ? 0x400 : 0x600;
-                ofs += PAD_BANK(pad) * 0x10;
-                bp = PAD_PIN(pad);
-                if (PAD_PULL(pad))
-                        __mxs_setl(1 << bp, iomux_base + ofs);
-                else
-                        __mxs_clrl(1 << bp, iomux_base + ofs);
-        }
-        return 0;
-}
-int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count)
-{
-        const iomux_cfg_t *p = pad_list;
-        int i;
-        int ret;
-        for (i = 0; i < count; i++) {
-                ret = mxs_iomux_setup_pad(*p);
-                if (ret)
-                        return ret;
-                p++;
-        }
-        return 0;
-}
diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c
deleted file mode 100644
index f5f061757deb..000000000000
--- a/arch/arm/mach-mxs/mach-apx4devkit.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * Copyright (C) 2011-2012
- * Lauri Hintsala, Bluegiga, <lauri.hintsala@bluegiga.com>
- * Veli-Pekka Peltola, Bluegiga, <veli-pekka.peltola@bluegiga.com>
- *
- * based on: mach-mx28evk.c
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/micrel_phy.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <mach/common.h>
-#include <mach/digctl.h>
-#include <mach/iomux-mx28.h>
-#include "devices-mx28.h"
-#define APX4DEVKIT_GPIO_USERLED MXS_GPIO_NR(3, 28)
-static const iomux_cfg_t apx4devkit_pads[] __initconst = {
-        /* duart */
-        MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
-        MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
-        /* auart0 */
-        MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
-        /* auart1 */
-        MX28_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
-        /* auart2 */
-        MX28_PAD_SSP2_SCK__AUART2_RX | MXS_PAD_CTRL,
-        MX28_PAD_SSP2_MOSI__AUART2_TX | MXS_PAD_CTRL,
-        /* auart3 */
-        MX28_PAD_SSP2_MISO__AUART3_RX | MXS_PAD_CTRL,
-        MX28_PAD_SSP2_SS0__AUART3_TX | MXS_PAD_CTRL,
-#define MXS_PAD_FEC     (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
-        /* fec0 */
-        MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
-        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
-        /* i2c */
-        MX28_PAD_I2C0_SCL__I2C0_SCL,
-        MX28_PAD_I2C0_SDA__I2C0_SDA,
-        /* mmc0 */
-        MX28_PAD_SSP0_DATA0__SSP0_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA1__SSP0_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA2__SSP0_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA3__SSP0_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA4__SSP0_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA5__SSP0_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA6__SSP0_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA7__SSP0_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_CMD__SSP0_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_SSP0_SCK__SSP0_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* led */
-        MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL,
-        /* saif0 & saif1 */
-        MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-};
-/* led */
-static const struct gpio_led apx4devkit_leds[] __initconst = {
-        {
-                .name = "user-led",
-                .default_trigger = "heartbeat",
-                .gpio = APX4DEVKIT_GPIO_USERLED,
-        },
-};
-static const struct gpio_led_platform_data apx4devkit_led_data __initconst = {
-        .leds = apx4devkit_leds,
-        .num_leds = ARRAY_SIZE(apx4devkit_leds),
-};
-static const struct fec_platform_data mx28_fec_pdata __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-static const struct mxs_mmc_platform_data apx4devkit_mmc_pdata __initconst = {
-        .wp_gpio = -EINVAL,
-        .flags = SLOTF_4_BIT_CAPABLE,
-};
-static const struct i2c_board_info apx4devkit_i2c_boardinfo[] __initconst = {
-        { I2C_BOARD_INFO("sgtl5000", 0x0a) }, /* ASoC */
-        { I2C_BOARD_INFO("pcf8563", 0x51) }, /* RTC */
-};
-#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || \
-                defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
-static struct regulator_consumer_supply apx4devkit_audio_consumer_supplies[] = {
-        REGULATOR_SUPPLY("VDDA", "0-000a"),
-        REGULATOR_SUPPLY("VDDIO", "0-000a"),
-};
-static struct regulator_init_data apx4devkit_vdd_reg_init_data = {
-        .constraints    = {
-                .name   = "3V3",
-                .always_on = 1,
-        },
-        .consumer_supplies = apx4devkit_audio_consumer_supplies,
-        .num_consumer_supplies = ARRAY_SIZE(apx4devkit_audio_consumer_supplies),
-};
-static struct fixed_voltage_config apx4devkit_vdd_pdata = {
-        .supply_name    = "board-3V3",
-        .microvolts     = 3300000,
-        .gpio           = -EINVAL,
-        .enabled_at_boot = 1,
-        .init_data      = &apx4devkit_vdd_reg_init_data,
-};
-static struct platform_device apx4devkit_voltage_regulator = {
-        .name           = "reg-fixed-voltage",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &apx4devkit_vdd_pdata,
-        },
-};
-static void __init apx4devkit_add_regulators(void)
-{
-        platform_device_register(&apx4devkit_voltage_regulator);
-}
-#else
-static void __init apx4devkit_add_regulators(void) {}
-#endif
-static const struct mxs_saif_platform_data
-                        apx4devkit_mxs_saif_pdata[] __initconst = {
-        /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */
-        {
-                .master_mode = 1,
-                .master_id = 0,
-        }, {
-                .master_mode = 0,
-                .master_id = 0,
-        },
-};
-static int apx4devkit_phy_fixup(struct phy_device *phy)
-{
-        phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
-        return 0;
-}
-static void __init apx4devkit_fec_phy_clk_enable(void)
-{
-        struct clk *clk;
-        /* Enable fec phy clock */
-        clk = clk_get_sys("enet_out", NULL);
-        if (!IS_ERR(clk))
-                clk_prepare_enable(clk);
-}
-static void __init apx4devkit_init(void)
-{
-        mx28_soc_init();
-        mxs_iomux_setup_multiple_pads(apx4devkit_pads,
-                        ARRAY_SIZE(apx4devkit_pads));
-        mx28_add_duart();
-        mx28_add_auart0();
-        mx28_add_auart1();
-        mx28_add_auart2();
-        mx28_add_auart3();
-        /*
-         * Register fixup for the Micrel KS8031 PHY clock
-         * (shares same ID with KS8051)
-         */
-        phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK,
-                        apx4devkit_phy_fixup);
-        apx4devkit_fec_phy_clk_enable();
-        mx28_add_fec(0, &mx28_fec_pdata);
-        mx28_add_mxs_mmc(0, &apx4devkit_mmc_pdata);
-        gpio_led_register_device(0, &apx4devkit_led_data);
-        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
-        mx28_add_saif(0, &apx4devkit_mxs_saif_pdata[0]);
-        mx28_add_saif(1, &apx4devkit_mxs_saif_pdata[1]);
-        apx4devkit_add_regulators();
-        mx28_add_mxs_i2c(0);
-        i2c_register_board_info(0, apx4devkit_i2c_boardinfo,
-                        ARRAY_SIZE(apx4devkit_i2c_boardinfo));
-        mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, NULL, 0);
-}
-static void __init apx4devkit_timer_init(void)
-{
-        mx28_clocks_init();
-}
-static struct sys_timer apx4devkit_timer = {
-        .init   = apx4devkit_timer_init,
-};
-MACHINE_START(APX4DEVKIT, "Bluegiga APX4 Development Kit")
-        .map_io         = mx28_map_io,
-        .init_irq       = mx28_init_irq,
-        .timer          = &apx4devkit_timer,
-        .init_machine   = apx4devkit_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
deleted file mode 100644
index 4c00c879b893..000000000000
--- a/arch/arm/mach-mxs/mach-m28evk.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
- *
- * based on: mach-mx28_evk.c
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <mach/common.h>
-#include <mach/iomux-mx28.h>
-#include "devices-mx28.h"
-#define M28EVK_GPIO_USERLED1    MXS_GPIO_NR(3, 16)
-#define M28EVK_GPIO_USERLED2    MXS_GPIO_NR(3, 17)
-#define MX28EVK_BL_ENABLE       MXS_GPIO_NR(3, 18)
-#define M28EVK_LCD_ENABLE       MXS_GPIO_NR(3, 28)
-#define MX28EVK_MMC0_WRITE_PROTECT      MXS_GPIO_NR(2, 12)
-#define MX28EVK_MMC1_WRITE_PROTECT      MXS_GPIO_NR(0, 28)
-static const iomux_cfg_t m28evk_pads[] __initconst = {
-        /* duart */
-        MX28_PAD_AUART0_CTS__DUART_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_RTS__DUART_TX | MXS_PAD_CTRL,
-        /* auart0 */
-        MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
-        /* auart3 */
-        MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
-#define MXS_PAD_FEC     (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
-        /* fec0 */
-        MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
-        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
-        /* fec1 */
-        MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
-        /* flexcan0 */
-        MX28_PAD_GPMI_RDY2__CAN0_TX,
-        MX28_PAD_GPMI_RDY3__CAN0_RX,
-        /* flexcan1 */
-        MX28_PAD_GPMI_CE2N__CAN1_TX,
-        MX28_PAD_GPMI_CE3N__CAN1_RX,
-        /* I2C */
-        MX28_PAD_I2C0_SCL__I2C0_SCL,
-        MX28_PAD_I2C0_SDA__I2C0_SDA,
-        /* mxsfb (lcdif) */
-        MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
-        MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
-        /* mmc0 */
-        MX28_PAD_SSP0_DATA0__SSP0_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA1__SSP0_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA2__SSP0_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA3__SSP0_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA4__SSP0_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA5__SSP0_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA6__SSP0_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA7__SSP0_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_CMD__SSP0_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_SSP0_SCK__SSP0_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* mmc1 */
-        MX28_PAD_GPMI_D00__SSP1_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D01__SSP1_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D02__SSP1_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D03__SSP1_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D04__SSP1_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D05__SSP1_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D06__SSP1_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D07__SSP1_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RDY1__SSP1_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_WRN__SSP1_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* write protect */
-        MX28_PAD_GPMI_RESETN__GPIO_0_28 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* slot power enable */
-        MX28_PAD_PWM4__GPIO_3_29 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* led */
-        MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
-        MX28_PAD_PWM1__GPIO_3_17 | MXS_PAD_CTRL,
-        /* nand */
-        MX28_PAD_GPMI_D00__GPMI_D0 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D01__GPMI_D1 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D02__GPMI_D2 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D03__GPMI_D3 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D04__GPMI_D4 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D05__GPMI_D5 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D06__GPMI_D6 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D07__GPMI_D7 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_CE0N__GPMI_CE0N |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_RDY0__GPMI_READY0 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_RDN__GPMI_RDN |
-                (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_WRN__GPMI_WRN |
-                (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_ALE__GPMI_ALE |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_CLE__GPMI_CLE |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RESETN__GPMI_RESETN |
-                (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-        /* Backlight */
-        MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL,
-};
-/* led */
-static const struct gpio_led m28evk_leds[] __initconst = {
-        {
-                .name = "user-led1",
-                .default_trigger = "heartbeat",
-                .gpio = M28EVK_GPIO_USERLED1,
-        },
-        {
-                .name = "user-led2",
-                .default_trigger = "heartbeat",
-                .gpio = M28EVK_GPIO_USERLED2,
-        },
-};
-static const struct gpio_led_platform_data m28evk_led_data __initconst = {
-        .leds = m28evk_leds,
-        .num_leds = ARRAY_SIZE(m28evk_leds),
-};
-static struct fec_platform_data mx28_fec_pdata[] __initdata = {
-        {
-                /* fec0 */
-                .phy = PHY_INTERFACE_MODE_RMII,
-        }, {
-                /* fec1 */
-                .phy = PHY_INTERFACE_MODE_RMII,
-        },
-};
-static int __init m28evk_fec_get_mac(void)
-{
-        int i;
-        u32 val;
-        const u32 *ocotp = mxs_get_ocotp();
-        if (!ocotp)
-                return -ETIMEDOUT;
-        /*
-         * OCOTP only stores the last 4 octets for each mac address,
-         * so hard-code DENX OUI (C0:E5:4E) here.
-         */
-        for (i = 0; i < 2; i++) {
-                val = ocotp[i];
-                mx28_fec_pdata[i].mac[0] = 0xC0;
-                mx28_fec_pdata[i].mac[1] = 0xE5;
-                mx28_fec_pdata[i].mac[2] = 0x4E;
-                mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
-                mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
-                mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
-        }
-        return 0;
-}
-/* mxsfb (lcdif) */
-static struct fb_videomode m28evk_video_modes[] = {
-        {
-                .name           = "Ampire AM-800480R2TMQW-T01H",
-                .refresh        = 60,
-                .xres           = 800,
-                .yres           = 480,
-                .pixclock       = 30066, /* picosecond (33.26 MHz) */
-                .left_margin    = 0,
-                .right_margin   = 256,
-                .upper_margin   = 0,
-                .lower_margin   = 45,
-                .hsync_len      = 1,
-                .vsync_len      = 1,
-                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT,
-        },
-};
-static const struct mxsfb_platform_data m28evk_mxsfb_pdata __initconst = {
-        .mode_list      = m28evk_video_modes,
-        .mode_count     = ARRAY_SIZE(m28evk_video_modes),
-        .default_bpp    = 16,
-        .ld_intf_width  = STMLCDIF_18BIT,
-};
-static struct at24_platform_data m28evk_eeprom = {
-        .byte_len = 16384,
-        .page_size = 32,
-        .flags = AT24_FLAG_ADDR16,
-};
-static struct i2c_board_info m28_stk5v3_i2c_boardinfo[] __initdata = {
-        {
-                I2C_BOARD_INFO("at24", 0x51),   /* E0=1, E1=0, E2=0 */
-                .platform_data = &m28evk_eeprom,
-        },
-};
-static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
-        {
-                /* mmc0 */
-                .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT,
-                .flags = SLOTF_8_BIT_CAPABLE,
-        }, {
-                /* mmc1 */
-                .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT,
-                .flags = SLOTF_8_BIT_CAPABLE,
-        },
-};
-static void __init m28evk_init(void)
-{
-        mx28_soc_init();
-        mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
-        mx28_add_duart();
-        mx28_add_auart0();
-        mx28_add_auart3();
-        if (!m28evk_fec_get_mac()) {
-                mx28_add_fec(0, &mx28_fec_pdata[0]);
-                mx28_add_fec(1, &mx28_fec_pdata[1]);
-        }
-        mx28_add_flexcan(0, NULL);
-        mx28_add_flexcan(1, NULL);
-        mx28_add_mxsfb(&m28evk_mxsfb_pdata);
-        mx28_add_mxs_mmc(0, &m28evk_mmc_pdata[0]);
-        mx28_add_mxs_mmc(1, &m28evk_mmc_pdata[1]);
-        gpio_led_register_device(0, &m28evk_led_data);
-        /* I2C */
-        mx28_add_mxs_i2c(0);
-        i2c_register_board_info(0, m28_stk5v3_i2c_boardinfo,
-                        ARRAY_SIZE(m28_stk5v3_i2c_boardinfo));
-}
-static void __init m28evk_timer_init(void)
-{
-        mx28_clocks_init();
-}
-static struct sys_timer m28evk_timer = {
-        .init   = m28evk_timer_init,
-};
-MACHINE_START(M28EVK, "DENX M28 EVK")
-        .map_io         = mx28_map_io,
-        .init_irq       = mx28_init_irq,
-        .timer          = &m28evk_timer,
-        .init_machine   = m28evk_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
deleted file mode 100644
index e7272a41939d..000000000000
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <mach/common.h>
-#include <mach/iomux-mx23.h>
-#include "devices-mx23.h"
-#define MX23EVK_LCD_ENABLE      MXS_GPIO_NR(1, 18)
-#define MX23EVK_BL_ENABLE       MXS_GPIO_NR(1, 28)
-#define MX23EVK_MMC0_WRITE_PROTECT      MXS_GPIO_NR(1, 30)
-#define MX23EVK_MMC0_SLOT_POWER         MXS_GPIO_NR(1, 29)
-static const iomux_cfg_t mx23evk_pads[] __initconst = {
-        /* duart */
-        MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
-        MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
-        /* auart */
-        MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
-        MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
-        MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL,
-        MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL,
-        /* mxsfb (lcdif) */
-        MX23_PAD_LCD_D00__LCD_D00 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D01__LCD_D01 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D02__LCD_D02 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D03__LCD_D03 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D04__LCD_D04 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D05__LCD_D05 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D06__LCD_D06 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D07__LCD_D07 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D08__LCD_D08 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D09__LCD_D09 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D08__LCD_D18 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D09__LCD_D19 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D10__LCD_D20 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D11__LCD_D21 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D12__LCD_D22 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D13__LCD_D23 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
-        MX23_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
-        MX23_PAD_LCD_DOTCK__LCD_DOTCK | MXS_PAD_CTRL,
-        MX23_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
-        /* LCD panel enable */
-        MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL,
-        /* backlight control */
-        MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL,
-        /* mmc */
-        MX23_PAD_SSP1_DATA0__SSP1_DATA0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA1__SSP1_DATA1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA2__SSP1_DATA2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA3__SSP1_DATA3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_GPMI_D08__SSP1_DATA4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_GPMI_D09__SSP1_DATA5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_GPMI_D10__SSP1_DATA6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_GPMI_D11__SSP1_DATA7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_CMD__SSP1_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DETECT__SSP1_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX23_PAD_SSP1_SCK__SSP1_SCK |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* write protect */
-        MX23_PAD_PWM4__GPIO_1_30 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* slot power enable */
-        MX23_PAD_PWM3__GPIO_1_29 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-};
-/* mxsfb (lcdif) */
-static struct fb_videomode mx23evk_video_modes[] = {
-        {
-                .name           = "Samsung-LMS430HF02",
-                .refresh        = 60,
-                .xres           = 480,
-                .yres           = 272,
-                .pixclock       = 108096, /* picosecond (9.2 MHz) */
-                .left_margin    = 15,
-                .right_margin   = 8,
-                .upper_margin   = 12,
-                .lower_margin   = 4,
-                .hsync_len      = 1,
-                .vsync_len      = 1,
-                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
-                                  FB_SYNC_DOTCLK_FAILING_ACT,
-        },
-};
-static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = {
-        .mode_list      = mx23evk_video_modes,
-        .mode_count     = ARRAY_SIZE(mx23evk_video_modes),
-        .default_bpp    = 32,
-        .ld_intf_width  = STMLCDIF_24BIT,
-};
-static struct mxs_mmc_platform_data mx23evk_mmc_pdata __initdata = {
-        .wp_gpio = MX23EVK_MMC0_WRITE_PROTECT,
-        .flags = SLOTF_8_BIT_CAPABLE,
-};
-static void __init mx23evk_init(void)
-{
-        int ret;
-        mx23_soc_init();
-        mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
-        mx23_add_duart();
-        mx23_add_auart0();
-        /* power on mmc slot by writing 0 to the gpio */
-        ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
-                               "mmc0-slot-power");
-        if (ret)
-                pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);
-        mx23_add_mxs_mmc(0, &mx23evk_mmc_pdata);
-        ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
-        if (ret)
-                pr_warn("failed to request gpio lcd-enable: %d\n", ret);
-        else
-                gpio_set_value(MX23EVK_LCD_ENABLE, 1);
-        ret = gpio_request_one(MX23EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
-        if (ret)
-                pr_warn("failed to request gpio bl-enable: %d\n", ret);
-        else
-                gpio_set_value(MX23EVK_BL_ENABLE, 1);
-        mx23_add_mxsfb(&mx23evk_mxsfb_pdata);
-        mx23_add_rtc_stmp3xxx();
-}
-static void __init mx23evk_timer_init(void)
-{
-        mx23_clocks_init();
-}
-static struct sys_timer mx23evk_timer = {
-        .init   = mx23evk_timer_init,
-};
-MACHINE_START(MX23EVK, "Freescale MX23 EVK")
-        /* Maintainer: Freescale Semiconductor, Inc. */
-        .map_io         = mx23_map_io,
-        .init_irq       = mx23_init_irq,
-        .timer          = &mx23evk_timer,
-        .init_machine   = mx23evk_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
deleted file mode 100644
index dafd48e86c8c..000000000000
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <mach/common.h>
-#include <mach/iomux-mx28.h>
-#include <mach/digctl.h>
-#include "devices-mx28.h"
-#define MX28EVK_FLEXCAN_SWITCH  MXS_GPIO_NR(2, 13)
-#define MX28EVK_FEC_PHY_POWER   MXS_GPIO_NR(2, 15)
-#define MX28EVK_GPIO_LED        MXS_GPIO_NR(3, 5)
-#define MX28EVK_BL_ENABLE       MXS_GPIO_NR(3, 18)
-#define MX28EVK_LCD_ENABLE      MXS_GPIO_NR(3, 30)
-#define MX28EVK_FEC_PHY_RESET   MXS_GPIO_NR(4, 13)
-#define MX28EVK_MMC0_WRITE_PROTECT      MXS_GPIO_NR(2, 12)
-#define MX28EVK_MMC1_WRITE_PROTECT      MXS_GPIO_NR(0, 28)
-#define MX28EVK_MMC0_SLOT_POWER         MXS_GPIO_NR(3, 28)
-#define MX28EVK_MMC1_SLOT_POWER         MXS_GPIO_NR(3, 29)
-static const iomux_cfg_t mx28evk_pads[] __initconst = {
-        /* duart */
-        MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
-        MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
-        /* auart0 */
-        MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
-        /* auart3 */
-        MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
-#define MXS_PAD_FEC     (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
-        /* fec0 */
-        MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
-        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
-        /* fec1 */
-        MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
-        /* phy power line */
-        MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL,
-        /* phy reset line */
-        MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL,
-        /* flexcan0 */
-        MX28_PAD_GPMI_RDY2__CAN0_TX,
-        MX28_PAD_GPMI_RDY3__CAN0_RX,
-        /* flexcan1 */
-        MX28_PAD_GPMI_CE2N__CAN1_TX,
-        MX28_PAD_GPMI_CE3N__CAN1_RX,
-        /* transceiver power control */
-        MX28_PAD_SSP1_CMD__GPIO_2_13,
-        /* mxsfb (lcdif) */
-        MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
-        MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
-        MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
-        MX28_PAD_LCD_CS__LCD_ENABLE | MXS_PAD_CTRL,
-        /* LCD panel enable */
-        MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
-        /* backlight control */
-        MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL,
-        /* mmc0 */
-        MX28_PAD_SSP0_DATA0__SSP0_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA1__SSP0_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA2__SSP0_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA3__SSP0_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA4__SSP0_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA5__SSP0_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA6__SSP0_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA7__SSP0_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_CMD__SSP0_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_SSP0_SCK__SSP0_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* write protect */
-        MX28_PAD_SSP1_SCK__GPIO_2_12 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* slot power enable */
-        MX28_PAD_PWM3__GPIO_3_28 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* mmc1 */
-        MX28_PAD_GPMI_D00__SSP1_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D01__SSP1_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D02__SSP1_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D03__SSP1_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D04__SSP1_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D05__SSP1_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D06__SSP1_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D07__SSP1_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RDY1__SSP1_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_WRN__SSP1_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* write protect */
-        MX28_PAD_GPMI_RESETN__GPIO_0_28 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* slot power enable */
-        MX28_PAD_PWM4__GPIO_3_29 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* led */
-        MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL,
-        /* I2C */
-        MX28_PAD_I2C0_SCL__I2C0_SCL |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_I2C0_SDA__I2C0_SDA |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        /* saif0 & saif1 */
-        MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-};
-/* led */
-static const struct gpio_led mx28evk_leds[] __initconst = {
-        {
-                .name = "GPIO-LED",
-                .default_trigger = "heartbeat",
-                .gpio = MX28EVK_GPIO_LED,
-        },
-};
-static const struct gpio_led_platform_data mx28evk_led_data __initconst = {
-        .leds = mx28evk_leds,
-        .num_leds = ARRAY_SIZE(mx28evk_leds),
-};
-/* fec */
-static void __init mx28evk_fec_reset(void)
-{
-        struct clk *clk;
-        /* Enable fec phy clock */
-        clk = clk_get_sys("enet_out", NULL);
-        if (!IS_ERR(clk))
-                clk_prepare_enable(clk);
-        gpio_set_value(MX28EVK_FEC_PHY_RESET, 0);
-        mdelay(1);
-        gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
-}
-static struct fec_platform_data mx28_fec_pdata[] __initdata = {
-        {
-                /* fec0 */
-                .phy = PHY_INTERFACE_MODE_RMII,
-        }, {
-                /* fec1 */
-                .phy = PHY_INTERFACE_MODE_RMII,
-        },
-};
-static int __init mx28evk_fec_get_mac(void)
-{
-        int i;
-        u32 val;
-        const u32 *ocotp = mxs_get_ocotp();
-        if (!ocotp)
-                return -ETIMEDOUT;
-        /*
-         * OCOTP only stores the last 4 octets for each mac address,
-         * so hard-code Freescale OUI (00:04:9f) here.
-         */
-        for (i = 0; i < 2; i++) {
-                val = ocotp[i];
-                mx28_fec_pdata[i].mac[0] = 0x00;
-                mx28_fec_pdata[i].mac[1] = 0x04;
-                mx28_fec_pdata[i].mac[2] = 0x9f;
-                mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
-                mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
-                mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
-        }
-        return 0;
-}
-/*
- * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
- */
-static int flexcan0_en, flexcan1_en;
-static void mx28evk_flexcan_switch(void)
-{
-        if (flexcan0_en || flexcan1_en)
-                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
-        else
-                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
-}
-static void mx28evk_flexcan0_switch(int enable)
-{
-        flexcan0_en = enable;
-        mx28evk_flexcan_switch();
-}
-static void mx28evk_flexcan1_switch(int enable)
-{
-        flexcan1_en = enable;
-        mx28evk_flexcan_switch();
-}
-static const struct flexcan_platform_data
-                mx28evk_flexcan_pdata[] __initconst = {
-        {
-                .transceiver_switch = mx28evk_flexcan0_switch,
-        }, {
-                .transceiver_switch = mx28evk_flexcan1_switch,
-        }
-};
-/* mxsfb (lcdif) */
-static struct fb_videomode mx28evk_video_modes[] = {
-        {
-                .name           = "Seiko-43WVF1G",
-                .refresh        = 60,
-                .xres           = 800,
-                .yres           = 480,
-                .pixclock       = 29851, /* picosecond (33.5 MHz) */
-                .left_margin    = 89,
-                .right_margin   = 164,
-                .upper_margin   = 23,
-                .lower_margin   = 10,
-                .hsync_len      = 10,
-                .vsync_len      = 10,
-                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
-                                  FB_SYNC_DOTCLK_FAILING_ACT,
-        },
-};
-static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = {
-        .mode_list      = mx28evk_video_modes,
-        .mode_count     = ARRAY_SIZE(mx28evk_video_modes),
-        .default_bpp    = 32,
-        .ld_intf_width  = STMLCDIF_24BIT,
-};
-static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = {
-        {
-                /* mmc0 */
-                .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT,
-                .flags = SLOTF_8_BIT_CAPABLE,
-        }, {
-                /* mmc1 */
-                .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT,
-                .flags = SLOTF_8_BIT_CAPABLE,
-        },
-};
-static struct i2c_board_info mxs_i2c0_board_info[] __initdata = {
-        {
-                I2C_BOARD_INFO("sgtl5000", 0x0a),
-        },
-};
-#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
-static struct regulator_consumer_supply mx28evk_audio_consumer_supplies[] = {
-        REGULATOR_SUPPLY("VDDA", "0-000a"),
-        REGULATOR_SUPPLY("VDDIO", "0-000a"),
-};
-static struct regulator_init_data mx28evk_vdd_reg_init_data = {
-        .constraints    = {
-                .name   = "3V3",
-                .always_on = 1,
-        },
-        .consumer_supplies = mx28evk_audio_consumer_supplies,
-        .num_consumer_supplies = ARRAY_SIZE(mx28evk_audio_consumer_supplies),
-};
-static struct fixed_voltage_config mx28evk_vdd_pdata = {
-        .supply_name    = "board-3V3",
-        .microvolts     = 3300000,
-        .gpio           = -EINVAL,
-        .enabled_at_boot = 1,
-        .init_data      = &mx28evk_vdd_reg_init_data,
-};
-static struct platform_device mx28evk_voltage_regulator = {
-        .name           = "reg-fixed-voltage",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &mx28evk_vdd_pdata,
-        },
-};
-static void __init mx28evk_add_regulators(void)
-{
-        platform_device_register(&mx28evk_voltage_regulator);
-}
-#else
-static void __init mx28evk_add_regulators(void) {}
-#endif
-static const struct gpio mx28evk_gpios[] __initconst = {
-        { MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" },
-        { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" },
-        { MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, "flexcan-switch" },
-        { MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc0-slot-power" },
-        { MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc1-slot-power" },
-        { MX28EVK_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
-        { MX28EVK_FEC_PHY_RESET, GPIOF_DIR_OUT, "fec-phy-reset" },
-};
-static const struct mxs_saif_platform_data
-                        mx28evk_mxs_saif_pdata[] __initconst = {
-        /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */
-        {
-                .master_mode = 1,
-                .master_id = 0,
-        }, {
-                .master_mode = 0,
-                .master_id = 0,
-        },
-};
-static void __init mx28evk_init(void)
-{
-        int ret;
-        mx28_soc_init();
-        mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
-        mx28_add_duart();
-        mx28_add_auart0();
-        mx28_add_auart3();
-        if (mx28evk_fec_get_mac())
-                pr_warn("%s: failed on fec mac setup\n", __func__);
-        ret = gpio_request_array(mx28evk_gpios, ARRAY_SIZE(mx28evk_gpios));
-        if (ret)
-                pr_err("One or more GPIOs failed to be requested: %d\n", ret);
-        mx28evk_fec_reset();
-        mx28_add_fec(0, &mx28_fec_pdata[0]);
-        mx28_add_fec(1, &mx28_fec_pdata[1]);
-        mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]);
-        mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
-        mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
-        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
-        mx28_add_saif(0, &mx28evk_mxs_saif_pdata[0]);
-        mx28_add_saif(1, &mx28evk_mxs_saif_pdata[1]);
-        mx28_add_mxs_i2c(0);
-        i2c_register_board_info(0, mxs_i2c0_board_info,
-                                ARRAY_SIZE(mxs_i2c0_board_info));
-        mx28evk_add_regulators();
-        mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0,
-                        NULL, 0);
-        mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]);
-        mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
-        mx28_add_rtc_stmp3xxx();
-        gpio_led_register_device(0, &mx28evk_led_data);
-}
-static void __init mx28evk_timer_init(void)
-{
-        mx28_clocks_init();
-}
-static struct sys_timer mx28evk_timer = {
-        .init   = mx28evk_timer_init,
-};
-MACHINE_START(MX28EVK, "Freescale MX28 EVK")
-        /* Maintainer: Freescale Semiconductor, Inc. */
-        .map_io         = mx28_map_io,
-        .init_irq       = mx28_init_irq,
-        .timer          = &mx28evk_timer,
-        .init_machine   = mx28evk_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index ff886e01a0b0..4748ec551a68 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -12,18 +12,21 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/can/platform/flexcan.h>
+#include <linux/delay.h>
 #include <linux/err.h>
+#include <linux/gpio.h>
 #include <linux/init.h>
-#include <linux/init.h>
-#include <linux/irqdomain.h>
 #include <linux/micrel_phy.h>
 #include <linux/mxsfb.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
+#include <linux/pinctrl/consumer.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
+#include <mach/digctl.h>
+#include <mach/mxs.h>
 static struct fb_videomode mx23evk_video_modes[] = {
        {
@@ -99,43 +102,43 @@ static struct fb_videomode apx4devkit_video_modes[] = {
 static struct mxsfb_platform_data mxsfb_pdata __initdata;
-static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
+/*
-        OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata),
+ * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
-        OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata),
+ */
-        { /* sentinel */ }
+#define MX28EVK_FLEXCAN_SWITCH  MXS_GPIO_NR(2, 13)
-};
-static int __init mxs_icoll_add_irq_domain(struct device_node *np,
+static int flexcan0_en, flexcan1_en;
-                                struct device_node *interrupt_parent)
-{
-        irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
-        return 0;
+static void mx28evk_flexcan_switch(void)
+{
+        if (flexcan0_en || flexcan1_en)
+                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
+        else
+                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
 }
-static int __init mxs_gpio_add_irq_domain(struct device_node *np,
+static void mx28evk_flexcan0_switch(int enable)
-                                struct device_node *interrupt_parent)
 {
-        static int gpio_irq_base = MXS_GPIO_IRQ_START;
+        flexcan0_en = enable;
+        mx28evk_flexcan_switch();
-        irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
+}
-        gpio_irq_base += 32;
-        return 0;
+static void mx28evk_flexcan1_switch(int enable)
+{
+        flexcan1_en = enable;
+        mx28evk_flexcan_switch();
 }
-static const struct of_device_id mxs_irq_match[] __initconst = {
+static struct flexcan_platform_data flexcan_pdata[2];
-        { .compatible = "fsl,mxs-icoll", .data = mxs_icoll_add_irq_domain, },
-        { .compatible = "fsl,mxs-gpio", .data = mxs_gpio_add_irq_domain, },
+static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata),
+        OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata),
+        OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]),
+        OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]),
        { /* sentinel */ }
 };
-static void __init mxs_dt_init_irq(void)
-{
-        icoll_init_irq();
-        of_irq_init(mxs_irq_match);
-}
 static void __init imx23_timer_init(void)
 {
        mx23_clocks_init();
@@ -237,13 +240,21 @@ static void __init imx28_evk_init(void)
        mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes);
        mxsfb_pdata.default_bpp = 32;
        mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
+        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
 }
-static void __init m28evk_init(void)
+static void __init imx28_evk_post_init(void)
 {
-        enable_clk_enet_out();
+        if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
-        update_fec_mac_prop(OUI_DENX);
+                              "flexcan-switch")) {
+                flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch;
+                flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch;
+        }
+}
+static void __init m28evk_init(void)
+{
        mxsfb_pdata.mode_list = m28evk_video_modes;
        mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes);
        mxsfb_pdata.default_bpp = 16;
@@ -270,6 +281,80 @@ static void __init apx4devkit_init(void)
        mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
 }
+#define ENET0_MDC__GPIO_4_0     MXS_GPIO_NR(4, 0)
+#define ENET0_MDIO__GPIO_4_1    MXS_GPIO_NR(4, 1)
+#define ENET0_RX_EN__GPIO_4_2   MXS_GPIO_NR(4, 2)
+#define ENET0_RXD0__GPIO_4_3    MXS_GPIO_NR(4, 3)
+#define ENET0_RXD1__GPIO_4_4    MXS_GPIO_NR(4, 4)
+#define ENET0_TX_EN__GPIO_4_6   MXS_GPIO_NR(4, 6)
+#define ENET0_TXD0__GPIO_4_7    MXS_GPIO_NR(4, 7)
+#define ENET0_TXD1__GPIO_4_8    MXS_GPIO_NR(4, 8)
+#define ENET_CLK__GPIO_4_16     MXS_GPIO_NR(4, 16)
+#define TX28_FEC_PHY_POWER      MXS_GPIO_NR(3, 29)
+#define TX28_FEC_PHY_RESET      MXS_GPIO_NR(4, 13)
+#define TX28_FEC_nINT           MXS_GPIO_NR(4, 5)
+static const struct gpio tx28_gpios[] __initconst = {
+        { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" },
+        { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" },
+        { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" },
+        { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" },
+        { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" },
+        { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" },
+        { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" },
+        { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" },
+        { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" },
+        { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
+        { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" },
+        { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" },
+};
+static void __init tx28_post_init(void)
+{
+        struct device_node *np;
+        struct platform_device *pdev;
+        struct pinctrl *pctl;
+        int ret;
+        enable_clk_enet_out();
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec");
+        pdev = of_find_device_by_node(np);
+        if (!pdev) {
+                pr_err("%s: failed to find fec device\n", __func__);
+                return;
+        }
+        pctl = pinctrl_get_select(&pdev->dev, "gpio_mode");
+        if (IS_ERR(pctl)) {
+                pr_err("%s: failed to get pinctrl state\n", __func__);
+                return;
+        }
+        ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
+        if (ret) {
+                pr_err("%s: failed to request gpios: %d\n", __func__, ret);
+                return;
+        }
+        /* Power up fec phy */
+        gpio_set_value(TX28_FEC_PHY_POWER, 1);
+        msleep(26); /* 25ms according to data sheet */
+        /* Mode strap pins */
+        gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1);
+        gpio_set_value(ENET0_RXD0__GPIO_4_3, 1);
+        gpio_set_value(ENET0_RXD1__GPIO_4_4, 1);
+        udelay(100); /* minimum assertion time for nRST */
+        /* Deasserting FEC PHY RESET */
+        gpio_set_value(TX28_FEC_PHY_RESET, 1);
+        pinctrl_put(pctl);
+}
 static void __init mxs_machine_init(void)
 {
        if (of_machine_is_compatible("fsl,imx28-evk"))
@@ -283,29 +368,28 @@ static void __init mxs_machine_init(void)
        of_platform_populate(NULL, of_default_bus_match_table,
                             mxs_auxdata_lookup, NULL);
+        if (of_machine_is_compatible("karo,tx28"))
+                tx28_post_init();
+        if (of_machine_is_compatible("fsl,imx28-evk"))
+                imx28_evk_post_init();
 }
 static const char *imx23_dt_compat[] __initdata = {
-        "fsl,imx23-evk",
-        "fsl,stmp378x_devb"
-        "olimex,imx23-olinuxino",
        "fsl,imx23",
        NULL,
 };
 static const char *imx28_dt_compat[] __initdata = {
-        "bluegiga,apx4devkit",
-        "crystalfontz,cfa10036",
-        "denx,m28evk",
-        "fsl,imx28-evk",
-        "karo,tx28",
        "fsl,imx28",
        NULL,
 };
 DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)")
        .map_io         = mx23_map_io,
-        .init_irq       = mxs_dt_init_irq,
+        .init_irq       = icoll_init_irq,
+        .handle_irq     = icoll_handle_irq,
        .timer          = &imx23_timer,
        .init_machine   = mxs_machine_init,
        .dt_compat      = imx23_dt_compat,
@@ -314,7 +398,8 @@ MACHINE_END
 DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
        .map_io         = mx28_map_io,
-        .init_irq       = mxs_dt_init_irq,
+        .init_irq       = icoll_init_irq,
+        .handle_irq     = icoll_handle_irq,
        .timer          = &imx28_timer,
        .init_machine   = mxs_machine_init,
        .dt_compat      = imx28_dt_compat,
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
deleted file mode 100644
index 6548965e4a76..000000000000
--- a/arch/arm/mach-mxs/mach-stmp378x_devb.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * board setup for STMP378x-Development-Board
- *
- * based on mx23evk board setup and information gained form the original
- * plat-stmp based board setup, now converted to mach-mxs.
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/spi/spi.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <mach/common.h>
-#include <mach/iomux-mx23.h>
-#include "devices-mx23.h"
-#define STMP378X_DEVB_MMC0_WRITE_PROTECT        MXS_GPIO_NR(1, 30)
-#define STMP378X_DEVB_MMC0_SLOT_POWER           MXS_GPIO_NR(1, 29)
-#define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL)
-static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = {
-        /* duart (extended setup missing in old boardcode, too */
-        MX23_PAD_PWM0__DUART_RX,
-        MX23_PAD_PWM1__DUART_TX,
-        /* auart */
-        MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART,
-        MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART,
-        MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART,
-        MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART,
-        /* mmc */
-        MX23_PAD_SSP1_DATA0__SSP1_DATA0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA1__SSP1_DATA1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA2__SSP1_DATA2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA3__SSP1_DATA3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_CMD__SSP1_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DETECT__SSP1_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX23_PAD_SSP1_SCK__SSP1_SCK |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */
-        MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */
-};
-static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = {
-        .wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT,
-};
-static struct spi_board_info spi_board_info[] __initdata = {
-#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
-        {
-                .modalias       = "enc28j60",
-                .max_speed_hz   = 6 * 1000 * 1000,
-                .bus_num        = 1,
-                .chip_select    = 0,
-                .platform_data  = NULL,
-        },
-#endif
-};
-static void __init stmp378x_dvb_init(void)
-{
-        int ret;
-        mx23_soc_init();
-        mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
-                        ARRAY_SIZE(stmp378x_dvb_pads));
-        mx23_add_duart();
-        mx23_add_auart0();
-        mx23_add_rtc_stmp3xxx();
-        /* power on mmc slot */
-        ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER,
-                GPIOF_OUT_INIT_LOW, "mmc0-slot-power");
-        if (ret)
-                pr_warn("could not power mmc (%d)\n", ret);
-        mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata);
-        spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-}
-static void __init stmp378x_dvb_timer_init(void)
-{
-        mx23_clocks_init();
-}
-static struct sys_timer stmp378x_dvb_timer = {
-        .init   = stmp378x_dvb_timer_init,
-};
-MACHINE_START(STMP378X, "STMP378X")
-        .map_io         = mx23_map_io,
-        .init_irq       = mx23_init_irq,
-        .timer          = &stmp378x_dvb_timer,
-        .init_machine   = stmp378x_dvb_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
deleted file mode 100644
index 8837029de1a4..000000000000
--- a/arch/arm/mach-mxs/mach-tx28.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (C) 2010 <LW@KARO-electronics.de>
- *
- * based on: mach-mx28_evk.c
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation
- */
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/spi_gpio.h>
-#include <linux/i2c.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <mach/common.h>
-#include <mach/iomux-mx28.h>
-#include "devices-mx28.h"
-#include "module-tx28.h"
-#define TX28_STK5_GPIO_LED              MXS_GPIO_NR(4, 10)
-static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = {
-        /* LED */
-        MX28_PAD_ENET0_RXD3__GPIO_4_10 |
-                MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL,
-        /* framebuffer */
-#define LCD_MODE (MXS_PAD_3V3 | MXS_PAD_4MA)
-        MX28_PAD_LCD_D00__LCD_D0 | LCD_MODE,
-        MX28_PAD_LCD_D01__LCD_D1 | LCD_MODE,
-        MX28_PAD_LCD_D02__LCD_D2 | LCD_MODE,
-        MX28_PAD_LCD_D03__LCD_D3 | LCD_MODE,
-        MX28_PAD_LCD_D04__LCD_D4 | LCD_MODE,
-        MX28_PAD_LCD_D05__LCD_D5 | LCD_MODE,
-        MX28_PAD_LCD_D06__LCD_D6 | LCD_MODE,
-        MX28_PAD_LCD_D07__LCD_D7 | LCD_MODE,
-        MX28_PAD_LCD_D08__LCD_D8 | LCD_MODE,
-        MX28_PAD_LCD_D09__LCD_D9 | LCD_MODE,
-        MX28_PAD_LCD_D10__LCD_D10 | LCD_MODE,
-        MX28_PAD_LCD_D11__LCD_D11 | LCD_MODE,
-        MX28_PAD_LCD_D12__LCD_D12 | LCD_MODE,
-        MX28_PAD_LCD_D13__LCD_D13 | LCD_MODE,
-        MX28_PAD_LCD_D14__LCD_D14 | LCD_MODE,
-        MX28_PAD_LCD_D15__LCD_D15 | LCD_MODE,
-        MX28_PAD_LCD_D16__LCD_D16 | LCD_MODE,
-        MX28_PAD_LCD_D17__LCD_D17 | LCD_MODE,
-        MX28_PAD_LCD_D18__LCD_D18 | LCD_MODE,
-        MX28_PAD_LCD_D19__LCD_D19 | LCD_MODE,
-        MX28_PAD_LCD_D20__LCD_D20 | LCD_MODE,
-        MX28_PAD_LCD_D21__LCD_D21 | LCD_MODE,
-        MX28_PAD_LCD_D22__LCD_D22 | LCD_MODE,
-        MX28_PAD_LCD_D23__LCD_D23 | LCD_MODE,
-        MX28_PAD_LCD_RD_E__LCD_VSYNC | LCD_MODE,
-        MX28_PAD_LCD_WR_RWN__LCD_HSYNC | LCD_MODE,
-        MX28_PAD_LCD_RS__LCD_DOTCLK | LCD_MODE,
-        MX28_PAD_LCD_CS__LCD_CS | LCD_MODE,
-        MX28_PAD_LCD_VSYNC__LCD_VSYNC | LCD_MODE,
-        MX28_PAD_LCD_HSYNC__LCD_HSYNC | LCD_MODE,
-        MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | LCD_MODE,
-        MX28_PAD_LCD_ENABLE__GPIO_1_31 | LCD_MODE,
-        MX28_PAD_LCD_RESET__GPIO_3_30 | LCD_MODE,
-        MX28_PAD_PWM0__PWM_0 | LCD_MODE,
-        /* UART1 */
-        MX28_PAD_AUART0_CTS__DUART_RX,
-        MX28_PAD_AUART0_RTS__DUART_TX,
-        MX28_PAD_AUART0_TX__DUART_RTS,
-        MX28_PAD_AUART0_RX__DUART_CTS,
-        /* UART2 */
-        MX28_PAD_AUART1_RX__AUART1_RX,
-        MX28_PAD_AUART1_TX__AUART1_TX,
-        MX28_PAD_AUART1_RTS__AUART1_RTS,
-        MX28_PAD_AUART1_CTS__AUART1_CTS,
-        /* CAN */
-        MX28_PAD_GPMI_RDY2__CAN0_TX,
-        MX28_PAD_GPMI_RDY3__CAN0_RX,
-        /* I2C */
-        MX28_PAD_I2C0_SCL__I2C0_SCL,
-        MX28_PAD_I2C0_SDA__I2C0_SDA,
-        /* TSC2007 */
-        MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP,
-        /* MMC0 */
-        MX28_PAD_SSP0_DATA0__SSP0_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA1__SSP0_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA2__SSP0_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA3__SSP0_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_CMD__SSP0_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_SSP0_SCK__SSP0_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-};
-static const struct gpio_led tx28_stk5v3_leds[] __initconst = {
-        {
-                .name = "GPIO-LED",
-                .default_trigger = "heartbeat",
-                .gpio = TX28_STK5_GPIO_LED,
-        },
-};
-static const struct gpio_led_platform_data tx28_stk5v3_led_data __initconst = {
-        .leds = tx28_stk5v3_leds,
-        .num_leds = ARRAY_SIZE(tx28_stk5v3_leds),
-};
-static struct spi_board_info tx28_spi_board_info[] = {
-        {
-                .modalias = "spidev",
-                .max_speed_hz = 20000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .controller_data = (void *)SPI_GPIO_NO_CHIPSELECT,
-                .mode = SPI_MODE_0,
-        },
-};
-static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = {
-        {
-                I2C_BOARD_INFO("ds1339", 0x68),
-        },
-};
-static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
-       .wp_gpio = -EINVAL,
-       .flags = SLOTF_4_BIT_CAPABLE,
-};
-static void __init tx28_stk5v3_init(void)
-{
-        mx28_soc_init();
-        mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
-                        ARRAY_SIZE(tx28_stk5v3_pads));
-        mx28_add_duart(); /* UART1 */
-        mx28_add_auart(1); /* UART2 */
-        tx28_add_fec0();
-        /* spi via ssp will be added when available */
-        spi_register_board_info(tx28_spi_board_info,
-                        ARRAY_SIZE(tx28_spi_board_info));
-        gpio_led_register_device(0, &tx28_stk5v3_led_data);
-        mx28_add_mxs_i2c(0);
-        i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo,
-                        ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo));
-        mx28_add_mxs_mmc(0, &tx28_mmc0_pdata);
-        mx28_add_rtc_stmp3xxx();
-}
-static void __init tx28_timer_init(void)
-{
-        mx28_clocks_init();
-}
-static struct sys_timer tx28_timer = {
-        .init = tx28_timer_init,
-};
-MACHINE_START(TX28, "Ka-Ro electronics TX28 module")
-        .map_io = mx28_map_io,
-        .init_irq = mx28_init_irq,
-        .timer = &tx28_timer,
-        .init_machine = tx28_stk5v3_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c
index dccb67a9e7c4..a4294aa9f301 100644
--- a/arch/arm/mach-mxs/mm.c
+++ b/arch/arm/mach-mxs/mm.c
@@ -13,14 +13,11 @@
 #include <linux/mm.h>
 #include <linux/init.h>
-#include <linux/pinctrl/machine.h>
 #include <asm/mach/map.h>
 #include <mach/mx23.h>
 #include <mach/mx28.h>
-#include <mach/common.h>
-#include <mach/iomux.h>
 /*
 * Define the MX23 memory map.
@@ -48,43 +45,7 @@ void __init mx23_map_io(void)
        iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
 }
-void __init mx23_init_irq(void)
-{
-        icoll_init_irq();
-}
 void __init mx28_map_io(void)
 {
        iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
 }
-void __init mx28_init_irq(void)
-{
-        icoll_init_irq();
-}
-void __init mx23_soc_init(void)
-{
-        pinctrl_provide_dummies();
-        mxs_add_dma("imx23-dma-apbh", MX23_APBH_DMA_BASE_ADDR);
-        mxs_add_dma("imx23-dma-apbx", MX23_APBX_DMA_BASE_ADDR);
-        mxs_add_gpio("imx23-gpio", 0, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO0);
-        mxs_add_gpio("imx23-gpio", 1, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO1);
-        mxs_add_gpio("imx23-gpio", 2, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO2);
-}
-void __init mx28_soc_init(void)
-{
-        pinctrl_provide_dummies();
-        mxs_add_dma("imx28-dma-apbh", MX23_APBH_DMA_BASE_ADDR);
-        mxs_add_dma("imx28-dma-apbx", MX23_APBX_DMA_BASE_ADDR);
-        mxs_add_gpio("imx28-gpio", 0, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO0);
-        mxs_add_gpio("imx28-gpio", 1, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO1);
-        mxs_add_gpio("imx28-gpio", 2, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO2);
-        mxs_add_gpio("imx28-gpio", 3, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO3);
-        mxs_add_gpio("imx28-gpio", 4, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO4);
-}
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c
deleted file mode 100644
index 0f71f82101cc..000000000000
--- a/arch/arm/mach-mxs/module-tx28.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright (C) 2010 <LW@KARO-electronics.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/delay.h>
-#include <linux/fec.h>
-#include <linux/gpio.h>
-#include <mach/iomux-mx28.h>
-#include "devices-mx28.h"
-#include "module-tx28.h"
-#define TX28_FEC_PHY_POWER      MXS_GPIO_NR(3, 29)
-#define TX28_FEC_PHY_RESET      MXS_GPIO_NR(4, 13)
-static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = {
-        /* PHY POWER */
-        MX28_PAD_PWM4__GPIO_3_29 |
-                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
-        /* PHY RESET */
-        MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
-                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
-        /* Mode strap pins 0-2 */
-        MX28_PAD_ENET0_RXD0__GPIO_4_3 |
-                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
-        MX28_PAD_ENET0_RXD1__GPIO_4_4 |
-                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
-        MX28_PAD_ENET0_RX_EN__GPIO_4_2 |
-                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
-        /* nINT */
-        MX28_PAD_ENET0_TX_CLK__GPIO_4_5 |
-                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
-        MX28_PAD_ENET0_MDC__GPIO_4_0,
-        MX28_PAD_ENET0_MDIO__GPIO_4_1,
-        MX28_PAD_ENET0_TX_EN__GPIO_4_6,
-        MX28_PAD_ENET0_TXD0__GPIO_4_7,
-        MX28_PAD_ENET0_TXD1__GPIO_4_8,
-        MX28_PAD_ENET_CLK__GPIO_4_16,
-};
-#define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3)
-static const iomux_cfg_t tx28_fec0_pads[] __initconst = {
-        MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE,
-        MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE,
-        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE,
-        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | FEC_MODE,
-        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | FEC_MODE,
-        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | FEC_MODE,
-        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | FEC_MODE,
-        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | FEC_MODE,
-        MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE,
-};
-static const iomux_cfg_t tx28_fec1_pads[] __initconst = {
-        MX28_PAD_ENET0_RXD2__ENET1_RXD0,
-        MX28_PAD_ENET0_RXD3__ENET1_RXD1,
-        MX28_PAD_ENET0_TXD2__ENET1_TXD0,
-        MX28_PAD_ENET0_TXD3__ENET1_TXD1,
-        MX28_PAD_ENET0_COL__ENET1_TX_EN,
-        MX28_PAD_ENET0_CRS__ENET1_RX_EN,
-};
-static const struct fec_platform_data tx28_fec0_data __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-static const struct fec_platform_data tx28_fec1_data __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-int __init tx28_add_fec0(void)
-{
-        int i, ret;
-        pr_debug("%s: Switching FEC PHY power off\n", __func__);
-        ret = mxs_iomux_setup_multiple_pads(tx28_fec_gpio_pads,
-                        ARRAY_SIZE(tx28_fec_gpio_pads));
-        for (i = 0; i < ARRAY_SIZE(tx28_fec_gpio_pads); i++) {
-                unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
-                        PAD_PIN(tx28_fec_gpio_pads[i]));
-                ret = gpio_request(gpio, "FEC");
-                if (ret) {
-                        pr_err("Failed to request GPIO_%d_%d: %d\n",
-                                PAD_BANK(tx28_fec_gpio_pads[i]),
-                                PAD_PIN(tx28_fec_gpio_pads[i]), ret);
-                        goto free_gpios;
-                }
-                ret = gpio_direction_output(gpio, 0);
-                if (ret) {
-                        pr_err("Failed to set direction of GPIO_%d_%d to output: %d\n",
-                                        gpio / 32 + 1, gpio % 32, ret);
-                        goto free_gpios;
-                }
-        }
-        /* Power up fec phy */
-        pr_debug("%s: Switching FEC PHY power on\n", __func__);
-        ret = gpio_direction_output(TX28_FEC_PHY_POWER, 1);
-        if (ret) {
-                pr_err("Failed to power on PHY: %d\n", ret);
-                goto free_gpios;
-        }
-        mdelay(26); /* 25ms according to data sheet */
-        /* nINT */
-        gpio_direction_input(MXS_GPIO_NR(4, 5));
-        /* Mode strap pins */
-        gpio_direction_output(MXS_GPIO_NR(4, 2), 1);
-        gpio_direction_output(MXS_GPIO_NR(4, 3), 1);
-        gpio_direction_output(MXS_GPIO_NR(4, 4), 1);
-        udelay(100); /* minimum assertion time for nRST */
-        pr_debug("%s: Deasserting FEC PHY RESET\n", __func__);
-        gpio_set_value(TX28_FEC_PHY_RESET, 1);
-        ret = mxs_iomux_setup_multiple_pads(tx28_fec0_pads,
-                        ARRAY_SIZE(tx28_fec0_pads));
-        if (ret) {
-                pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
-                                __func__, ret);
-                goto free_gpios;
-        }
-        pr_debug("%s: Registering FEC0 device\n", __func__);
-        mx28_add_fec(0, &tx28_fec0_data);
-        return 0;
-free_gpios:
-        while (--i >= 0) {
-                unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
-                        PAD_PIN(tx28_fec_gpio_pads[i]));
-                gpio_free(gpio);
-        }
-        return ret;
-}
-int __init tx28_add_fec1(void)
-{
-        int ret;
-        ret = mxs_iomux_setup_multiple_pads(tx28_fec1_pads,
-                        ARRAY_SIZE(tx28_fec1_pads));
-        if (ret) {
-                pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
-                                __func__, ret);
-                return ret;
-        }
-        pr_debug("%s: Registering FEC1 device\n", __func__);
-        mx28_add_fec(1, &tx28_fec1_data);
-        return 0;
-}
diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h
deleted file mode 100644
index 8ed425457d30..000000000000
--- a/arch/arm/mach-mxs/module-tx28.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- *   Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-int __init tx28_add_fec0(void);
-int __init tx28_add_fec1(void);
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
index 02d36de9c4e8..7c3792613392 100644
--- a/arch/arm/mach-mxs/timer.c
+++ b/arch/arm/mach-mxs/timer.c
@@ -25,6 +25,8 @@
 #include <linux/irq.h>
 #include <linux/clockchips.h>
 #include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
 #include <asm/mach/time.h>
 #include <mach/mxs.h>
@@ -244,9 +246,17 @@ static int __init mxs_clocksource_init(struct clk *timer_clk)
        return 0;
 }
-void __init mxs_timer_init(int irq)
+void __init mxs_timer_init(void)
 {
+        struct device_node *np;
        struct clk *timer_clk;
+        int irq;
+        np = of_find_compatible_node(NULL, NULL, "fsl,timrot");
+        if (!np) {
+                pr_err("%s: failed find timrot node\n", __func__);
+                return;
+        }
        timer_clk = clk_get_sys("timrot", NULL);
        if (IS_ERR(timer_clk)) {
@@ -295,5 +305,6 @@ void __init mxs_timer_init(int irq)
        mxs_clockevent_init(timer_clk);
        /* Make irqs happen */
+        irq = irq_of_parse_and_map(np, 0);
        setup_irq(irq, &mxs_timer_irq);
 }
diff --git a/arch/arm/mach-netx/include/mach/eth.h b/arch/arm/mach-netx/include/mach/eth.h
deleted file mode 100644
index 88af1ac28ead..000000000000
--- a/arch/arm/mach-netx/include/mach/eth.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * arch/arm/mach-netx/include/mach/eth.h
- *
- * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef ASMARM_ARCH_ETH_H
-#define ASMARM_ARCH_ETH_H
-struct netxeth_platform_data {
-        unsigned int xcno;      /* number of xmac/xpec engine this eth uses */
-};
-#endif
diff --git a/arch/arm/mach-netx/nxdb500.c b/arch/arm/mach-netx/nxdb500.c
index 180ea899a48a..8b781ff7c9e9 100644
--- a/arch/arm/mach-netx/nxdb500.c
+++ b/arch/arm/mach-netx/nxdb500.c
@@ -30,7 +30,7 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
-#include <mach/eth.h>
+#include <linux/platform_data/eth-netx.h>
 #include "generic.h"
 #include "fb.h"
diff --git a/arch/arm/mach-netx/nxdkn.c b/arch/arm/mach-netx/nxdkn.c
index 58009e29b20e..b26dbce334f2 100644
--- a/arch/arm/mach-netx/nxdkn.c
+++ b/arch/arm/mach-netx/nxdkn.c
@@ -30,7 +30,7 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
-#include <mach/eth.h>
+#include <linux/platform_data/eth-netx.h>
 #include "generic.h"
diff --git a/arch/arm/mach-netx/nxeb500hmi.c b/arch/arm/mach-netx/nxeb500hmi.c
index 122e99826ef6..257382efafa0 100644
--- a/arch/arm/mach-netx/nxeb500hmi.c
+++ b/arch/arm/mach-netx/nxeb500hmi.c
@@ -30,7 +30,7 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
-#include <mach/eth.h>
+#include <linux/platform_data/eth-netx.h>
 #include "generic.h"
 #include "fb.h"
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index f4535a7dadf5..bfa1eab91f41 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -23,6 +23,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/i2c.h>
 #include <linux/io.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/hardware/vic.h>
 #include <asm/sizes.h>
 #include <asm/mach-types.h>
@@ -33,8 +34,9 @@
 #include <plat/gpio-nomadik.h>
 #include <plat/mtu.h>
+#include <plat/pincfg.h>
-#include <mach/nand.h>
+#include <linux/platform_data/mtd-nomadik-nand.h>
 #include <mach/fsmc.h>
 #include "cpu-8815.h"
@@ -112,8 +114,7 @@ static struct mtd_partition nhk8815_partitions[] = {
 static struct nomadik_nand_platform_data nhk8815_nand_data = {
        .parts          = nhk8815_partitions,
        .nparts         = ARRAY_SIZE(nhk8815_partitions),
-        .options        = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING \
+        .options        = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING,
-                        | NAND_NO_READRDY,
        .init           = nhk8815_nand_init,
 };
@@ -291,8 +292,42 @@ static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = {
        },
 };
+static unsigned long out_low[] = { PIN_OUTPUT_LOW };
+static unsigned long out_high[] = { PIN_OUTPUT_HIGH };
+static unsigned long in_nopull[] = { PIN_INPUT_NOPULL };
+static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
+static struct pinctrl_map __initdata nhk8815_pinmap[] = {
+        PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
+        /* Hog in MMC/SD card mux */
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
+        /* MCCLK */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
+        /* MCCMD */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
+        /* MCCMDDIR */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
+        /* MCDAT3-0 */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
+        /* MCDAT0DIR */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
+        /* MCDAT31DIR */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
+        /* MCMSFBCLK */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
+        /* CD input GPIO */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
+        /* CD bias drive */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
+};
 static void __init nhk8815_platform_init(void)
 {
+        pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
        cpu8815_platform_init();
        nhk8815_onenand_init();
        platform_add_devices(nhk8815_platform_devices,
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 6fd8e46567a4..b617eaed0ce5 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -83,6 +83,18 @@ void cpu8815_add_gpios(resource_size_t *base, int num, int irq,
        }
 }
+static inline void
+cpu8815_add_pinctrl(struct device *parent, const char *name)
+{
+        struct platform_device_info pdevinfo = {
+                .parent = parent,
+                .name = name,
+                .id = -1,
+        };
+        platform_device_register_full(&pdevinfo);
+}
 static int __init cpu8815_init(void)
 {
        struct nmk_gpio_platform_data pdata = {
@@ -91,6 +103,7 @@ static int __init cpu8815_init(void)
        cpu8815_add_gpios(cpu8815_gpio_base, ARRAY_SIZE(cpu8815_gpio_base),
                          IRQ_GPIO0, &pdata);
+        cpu8815_add_pinctrl(NULL, "pinctrl-stn8815");
        amba_apb_device_add(NULL, "rng", NOMADIK_RNG_BASE, SZ_4K, 0, 0, NULL, 0);
        amba_apb_device_add(NULL, "rtc-pl031", NOMADIK_RTC_BASE, SZ_4K, IRQ_RTC_RTT, 0, NULL, 0);
        return 0;
diff --git a/arch/arm/mach-nomadik/include/mach/gpio.h b/arch/arm/mach-nomadik/include/mach/gpio.h
deleted file mode 100644
index efdde0ae0a4f..000000000000
--- a/arch/arm/mach-nomadik/include/mach/gpio.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-nomadik/include/mach/hardware.h b/arch/arm/mach-nomadik/include/mach/hardware.h
index 6316dba3bfc8..02035e459f50 100644
--- a/arch/arm/mach-nomadik/include/mach/hardware.h
+++ b/arch/arm/mach-nomadik/include/mach/hardware.h
@@ -30,7 +30,7 @@
                        - NOMADIK_IO_VIRTUAL + NOMADIK_IO_PHYSICAL)
 /* used in asm code, so no casts */
-#define IO_ADDRESS(x) ((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
+#define IO_ADDRESS(x) IOMEM((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
 /*
 *   Base address defination for Nomadik Onchip Logic Block
diff --git a/arch/arm/mach-nomadik/include/mach/nand.h b/arch/arm/mach-nomadik/include/mach/nand.h
deleted file mode 100644
index c3c8254c22a5..000000000000
--- a/arch/arm/mach-nomadik/include/mach/nand.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __ASM_ARCH_NAND_H
-#define __ASM_ARCH_NAND_H
-struct nomadik_nand_platform_data {
-        struct mtd_partition *parts;
-        int nparts;
-        int options;
-        int (*init) (void);
-        int (*exit) (void);
-};
-#define NAND_IO_DATA    0x40000000
-#define NAND_IO_CMD     0x40800000
-#define NAND_IO_ADDR    0x41000000
-#endif                          /* __ASM_ARCH_NAND_H */
diff --git a/arch/arm/mach-nomadik/include/mach/uncompress.h b/arch/arm/mach-nomadik/include/mach/uncompress.h
index 071003bc8456..7d4687e9cbdf 100644
--- a/arch/arm/mach-nomadik/include/mach/uncompress.h
+++ b/arch/arm/mach-nomadik/include/mach/uncompress.h
@@ -27,10 +27,10 @@
 struct amba_device;
 #include <linux/amba/serial.h>
-#define NOMADIK_UART_DR         0x101FB000
+#define NOMADIK_UART_DR         (void __iomem *)0x101FB000
-#define NOMADIK_UART_LCRH       0x101FB02c
+#define NOMADIK_UART_LCRH       (void __iomem *)0x101FB02c
-#define NOMADIK_UART_CR         0x101FB030
+#define NOMADIK_UART_CR         (void __iomem *)0x101FB030
-#define NOMADIK_UART_FR         0x101FB018
+#define NOMADIK_UART_FR         (void __iomem *)0x101FB018
 static void putc(const char c)
 {
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 398e9e53e189..cd169c386161 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -61,14 +61,6 @@ obj-$(CONFIG_ARCH_OMAP850)		+= gpio7xx.o
 obj-$(CONFIG_ARCH_OMAP15XX)             += gpio15xx.o
 obj-$(CONFIG_ARCH_OMAP16XX)             += gpio16xx.o
-# LEDs support
-led-$(CONFIG_MACH_OMAP_H2)              += leds-h2p2-debug.o
-led-$(CONFIG_MACH_OMAP_H3)              += leds-h2p2-debug.o
-led-$(CONFIG_MACH_OMAP_INNOVATOR)       += leds-innovator.o
-led-$(CONFIG_MACH_OMAP_PERSEUS2)        += leds-h2p2-debug.o
-led-$(CONFIG_MACH_OMAP_OSK)             += leds-osk.o
-obj-$(CONFIG_LEDS)                      += $(led-y)
 ifneq ($(CONFIG_FB_OMAP),)
 obj-y += lcd_dma.o
 endif
diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
index a051cb8ae57f..3d1e1c250a1a 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S
+++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
@@ -16,8 +16,9 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
+#include <mach/irqs.h>
 #include <mach/ams-delta-fiq.h>
 #include "iomap.h"
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c
index 68e8e5654c0a..f12a12af3523 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq.c
+++ b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -19,7 +19,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 #include <asm/fiq.h>
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index c53469802c03..9518bf5996dc 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -26,6 +26,7 @@
 #include <linux/export.h>
 #include <linux/omapfb.h>
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <media/soc_camera.h>
@@ -34,10 +35,9 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
-#include <plat/keypad.h>
+#include <linux/platform_data/keypad-omap.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
-#include <plat/board.h>
 #include <mach/hardware.h>
 #include <mach/ams-delta-fiq.h>
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 6872f3fd400f..4b6de70c47a6 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -28,11 +28,10 @@
 #include <asm/mach/map.h>
 #include <plat/tc.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
 #include <plat/fpga.h>
-#include <plat/keypad.h>
+#include <linux/platform_data/keypad-omap.h>
-#include <plat/board.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 6ec385e2b98e..4ec579fdd366 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -22,8 +22,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
-#include <plat/board.h>
 #include <mach/usb.h>
@@ -52,9 +51,6 @@ static struct omap_usb_config generic1610_usb_config __initdata = {
 };
 #endif
-static struct omap_board_config_kernel generic_config[] __initdata = {
-};
 static void __init omap_generic_init(void)
 {
 #ifdef CONFIG_ARCH_OMAP15XX
@@ -76,8 +72,6 @@ static void __init omap_generic_init(void)
        }
 #endif
-        omap_board_config = generic_config;
-        omap_board_config_size = ARRAY_SIZE(generic_config);
        omap_serial_init();
        omap_register_i2c_bus(1, 100, NULL, 0);
 }
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 44a4ab195fbc..376f7f29ef77 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -31,17 +31,19 @@
 #include <linux/i2c/tps65010.h>
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/irda.h>
+#include <mach/irda.h>
-#include <plat/keypad.h>
+#include <linux/platform_data/keypad-omap.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
@@ -306,12 +308,39 @@ static struct platform_device h2_irda_device = {
        .resource       = h2_irda_resources,
 };
+static struct gpio_led h2_gpio_led_pins[] = {
+        {
+                .name           = "h2:red",
+                .default_trigger = "heartbeat",
+                .gpio           = 3,
+        },
+        {
+                .name           = "h2:green",
+                .default_trigger = "cpu0",
+                .gpio           = OMAP_MPUIO(4),
+        },
+};
+static struct gpio_led_platform_data h2_gpio_led_data = {
+        .leds           = h2_gpio_led_pins,
+        .num_leds       = ARRAY_SIZE(h2_gpio_led_pins),
+};
+static struct platform_device h2_gpio_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &h2_gpio_led_data,
+        },
+};
 static struct platform_device *h2_devices[] __initdata = {
        &h2_nor_device,
        &h2_nand_device,
        &h2_smc91x_device,
        &h2_irda_device,
        &h2_kp_device,
+        &h2_gpio_leds,
 };
 static void __init h2_init_smc91x(void)
@@ -406,6 +435,10 @@ static void __init h2_init(void)
        omap_cfg_reg(E19_1610_KBR4);
        omap_cfg_reg(N19_1610_KBR5);
+        /* GPIO based LEDs */
+        omap_cfg_reg(P18_1610_GPIO3);
+        omap_cfg_reg(MPUIO4);
        h2_smc91x_resources[1].start = gpio_to_irq(0);
        h2_smc91x_resources[1].end = gpio_to_irq(0);
        platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 86cb5a04a404..ededdb7ef28c 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -31,6 +31,8 @@
 #include <linux/i2c/tps65010.h>
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/leds.h>
 #include <asm/setup.h>
 #include <asm/page.h>
@@ -38,11 +40,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
-#include <plat/keypad.h>
+#include <linux/platform_data/keypad-omap.h>
 #include <plat/dma.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -324,6 +326,32 @@ static struct spi_board_info h3_spi_board_info[] __initdata = {
        },
 };
+static struct gpio_led h3_gpio_led_pins[] = {
+        {
+                .name           = "h3:red",
+                .default_trigger = "heartbeat",
+                .gpio           = 3,
+        },
+        {
+                .name           = "h3:green",
+                .default_trigger = "cpu0",
+                .gpio           = OMAP_MPUIO(4),
+        },
+};
+static struct gpio_led_platform_data h3_gpio_led_data = {
+        .leds           = h3_gpio_led_pins,
+        .num_leds       = ARRAY_SIZE(h3_gpio_led_pins),
+};
+static struct platform_device h3_gpio_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &h3_gpio_led_data,
+        },
+};
 static struct platform_device *devices[] __initdata = {
        &nor_device,
        &nand_device,
@@ -331,6 +359,7 @@ static struct platform_device *devices[] __initdata = {
        &intlat_device,
        &h3_kp_device,
        &h3_lcd_device,
+        &h3_gpio_leds,
 };
 static struct omap_usb_config h3_usb_config __initdata = {
@@ -398,6 +427,10 @@ static void __init h3_init(void)
        omap_cfg_reg(E19_1610_KBR4);
        omap_cfg_reg(N19_1610_KBR5);
+        /* GPIO based LEDs */
+        omap_cfg_reg(P18_1610_GPIO3);
+        omap_cfg_reg(MPUIO4);
        smc91x_resources[1].start = gpio_to_irq(40);
        smc91x_resources[1].end = gpio_to_irq(40);
        platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index b3f6e943e661..87ab2086ef96 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -37,13 +37,12 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/keypad-omap.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <plat/omap7xx.h>
+#include <mach/omap7xx.h>
-#include <plat/board.h>
-#include <plat/keypad.h>
 #include <plat/mmc.h>
 #include <mach/irqs.h>
@@ -476,8 +475,7 @@ static void __init htcherald_lcd_init(void)
                                break;
                }
                if (!tries)
-                        printk(KERN_WARNING "Timeout waiting for end of frame "
+                        pr_err("Timeout waiting for end of frame -- LCD may not be available\n");
-                               "-- LCD may not be available\n");
                /* turn off DMA */
                reg = omap_readw(OMAP_DMA_LCD_CCR);
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index f21c2966daad..db5f7d2976e7 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -31,11 +31,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
 #include <plat/fpga.h>
 #include <plat/tc.h>
-#include <plat/keypad.h>
+#include <linux/platform_data/keypad-omap.h>
 #include <plat/mmc.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 2c0ca8fc3380..7d5c06d6a52a 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -21,14 +21,14 @@
 #include <linux/workqueue.h>
 #include <linux/delay.h>
+#include <linux/platform_data/keypad-omap.h>
+#include <linux/platform_data/lcd-mipid.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
-#include <plat/board.h>
-#include <plat/keypad.h>
-#include <plat/lcd_mipid.h>
 #include <plat/mmc.h>
 #include <plat/clock.h>
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 8784705edb60..5973945a8741 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -39,13 +39,15 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/i2c/tps65010.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/omap1_bl.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
 #include <mach/hardware.h>
@@ -302,7 +304,7 @@ static struct omap_lcd_config osk_lcd_config __initdata = {
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
-#include <plat/keypad.h>
+#include <linux/platform_data/keypad-omap.h>
 static struct at24_platform_data at24c04 = {
        .byte_len       = SZ_4K / 8,
@@ -380,10 +382,37 @@ static struct platform_device osk5912_lcd_device = {
        .id             = -1,
 };
+static struct gpio_led mistral_gpio_led_pins[] = {
+        {
+                .name           = "mistral:red",
+                .default_trigger = "heartbeat",
+                .gpio           = 3,
+        },
+        {
+                .name           = "mistral:green",
+                .default_trigger = "cpu0",
+                .gpio           = OMAP_MPUIO(4),
+        },
+};
+static struct gpio_led_platform_data mistral_gpio_led_data = {
+        .leds           = mistral_gpio_led_pins,
+        .num_leds       = ARRAY_SIZE(mistral_gpio_led_pins),
+};
+static struct platform_device mistral_gpio_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &mistral_gpio_led_data,
+        },
+};
 static struct platform_device *mistral_devices[] __initdata = {
        &osk5912_kp_device,
        &mistral_bl_device,
        &osk5912_lcd_device,
+        &mistral_gpio_leds,
 };
 static int mistral_get_pendown_state(void)
@@ -508,6 +537,12 @@ static void __init osk_mistral_init(void)
        if (gpio_request(2, "lcd_pwr") == 0)
                gpio_direction_output(2, 1);
+        /*
+         * GPIO based LEDs
+         */
+        omap_cfg_reg(P18_1610_GPIO3);
+        omap_cfg_reg(MPUIO4);
        i2c_register_board_info(1, mistral_i2c_board_info,
                        ARRAY_SIZE(mistral_i2c_board_info));
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 26bcb9defcdc..1c578d58923a 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -28,18 +28,18 @@
 #include <linux/interrupt.h>
 #include <linux/apm-emulation.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/omap1_bl.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
 #include <plat/dma.h>
-#include <plat/board.h>
+#include <mach/irda.h>
-#include <plat/irda.h>
+#include <linux/platform_data/keypad-omap.h>
-#include <plat/keypad.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 4d099446dfa8..97158095083c 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -27,19 +27,19 @@
 #include <linux/omapfb.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/platform_data/omap1_bl.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <plat/led.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/board.h>
+#include <mach/irda.h>
-#include <plat/irda.h>
+#include <linux/platform_data/keypad-omap.h>
-#include <plat/keypad.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 355980321c2d..e311032e7eeb 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -30,18 +30,18 @@
 #include <linux/omapfb.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/platform_data/omap1_bl.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/board.h>
+#include <mach/irda.h>
-#include <plat/irda.h>
+#include <linux/platform_data/keypad-omap.h>
-#include <plat/keypad.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 703d55ecffe2..198b05417bfc 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -22,17 +22,16 @@
 #include <linux/input.h>
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/keypad-omap.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <plat/tc.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/fpga.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
-#include <plat/keypad.h>
-#include <plat/board.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c
index b59f78850e69..5932d56e17bf 100644
--- a/arch/arm/mach-omap1/board-sx1-mmc.c
+++ b/arch/arm/mach-omap1/board-sx1-mmc.c
@@ -17,7 +17,7 @@
 #include <mach/hardware.h>
 #include <plat/mmc.h>
-#include <plat/board-sx1.h>
+#include <mach/board-sx1.h>
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 8c665bd16ac2..13bf2cc56814 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -28,19 +28,18 @@
 #include <linux/errno.h>
 #include <linux/export.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/keypad-omap.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
-#include <plat/irda.h>
+#include <mach/irda.h>
 #include <plat/tc.h>
-#include <plat/board.h>
+#include <mach/board-sx1.h>
-#include <plat/keypad.h>
-#include <plat/board-sx1.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 3497769eb353..ad75e3411d46 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -31,11 +31,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/board-voiceblue.h>
+#include <mach/board-voiceblue.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
-#include <plat/board.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
@@ -155,9 +154,6 @@ static struct omap_usb_config voiceblue_usb_config __initdata = {
        .pins[2]        = 6,
 };
-static struct omap_board_config_kernel voiceblue_config[] = {
-};
 #define MACHINE_PANICED         1
 #define MACHINE_REBOOTING       2
 #define MACHINE_REBOOT          4
@@ -275,8 +271,6 @@ static void __init voiceblue_init(void)
        voiceblue_smc91x_resources[1].start = gpio_to_irq(8);
        voiceblue_smc91x_resources[1].end = gpio_to_irq(8);
        platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
-        omap_board_config = voiceblue_config;
-        omap_board_config_size = ARRAY_SIZE(voiceblue_config);
        omap_serial_init();
        omap1_usb_init(&voiceblue_usb_config);
        omap_register_i2c_bus(1, 100, NULL, 0);
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index a9ee06b6cb42..638f4070fc70 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -587,8 +587,8 @@ void omap1_clk_disable_unused(struct clk *clk)
        /* Clocks in the DSP domain need api_ck. Just assume bootloader
         * has not enabled any DSP clocks */
        if (clk->enable_reg == DSP_IDLECT2) {
-                printk(KERN_INFO "Skipping reset check for DSP domain "
+                pr_info("Skipping reset check for DSP domain clock \"%s\"\n",
-                       "clock \"%s\"\n", clk->name);
+                        clk->name);
                return;
        }
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index c007d80dfb62..9b45f4b0ee22 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -25,7 +25,6 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/clkdev_omap.h>
-#include <plat/board.h>
 #include <plat/sram.h>  /* for omap_sram_reprogram_clock() */
 #include <mach/hardware.h>
@@ -776,11 +775,10 @@ static struct clk_functions omap1_clk_functions = {
 static void __init omap1_show_rates(void)
 {
-        pr_notice("Clocking rate (xtal/DPLL1/MPU): "
+        pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
-                        "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
+                  ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
-                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
+                  ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
-                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
+                  arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
-                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 }
 u32 cpu_mask;
@@ -788,7 +786,6 @@ u32 cpu_mask;
 int __init omap1_clk_init(void)
 {
        struct omap_clk *c;
-        const struct omap_clock_config *info;
        int crystal_type = 0; /* Default 12 MHz */
        u32 reg;
@@ -837,19 +834,13 @@ int __init omap1_clk_init(void)
        ck_dpll1_p = clk_get(NULL, "ck_dpll1");
        ck_ref_p = clk_get(NULL, "ck_ref");
-        info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
-        if (info != NULL) {
-                if (!cpu_is_omap15xx())
-                        crystal_type = info->system_clock_type;
-        }
        if (cpu_is_omap7xx())
                ck_ref.rate = 13000000;
        if (cpu_is_omap16xx() && crystal_type == 2)
                ck_ref.rate = 19200000;
-        pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
+        pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
-                "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
+                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
                omap_readw(ARM_CKCTL));
        /* We want to be in syncronous scalable mode */
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index fa1fa4deb6aa..d3fec92c54cb 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -20,12 +20,11 @@
 #include <asm/mach/map.h>
 #include <plat/tc.h>
-#include <plat/board.h>
+#include <mach/mux.h>
-#include <plat/mux.h>
 #include <plat/dma.h>
 #include <plat/mmc.h>
-#include <plat/omap7xx.h>
+#include <mach/omap7xx.h>
 #include <mach/camera.h>
 #include <mach/hardware.h>
@@ -232,7 +231,7 @@ void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
                omap_mmc_add("mmci-omap", i, base, size, irq,
                                rx_req, tx_req, mmc_data[i]);
-        };
+        }
 }
 #endif
@@ -358,6 +357,33 @@ static inline void omap_init_uwire(void) {}
 #endif
+#define OMAP1_RNG_BASE          0xfffe5000
+static struct resource omap1_rng_resources[] = {
+        {
+                .start          = OMAP1_RNG_BASE,
+                .end            = OMAP1_RNG_BASE + 0x4f,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+static struct platform_device omap1_rng_device = {
+        .name           = "omap_rng",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(omap1_rng_resources),
+        .resource       = omap1_rng_resources,
+};
+static void omap1_init_rng(void)
+{
+        if (!cpu_is_omap16xx())
+                return;
+        (void) platform_device_register(&omap1_rng_device);
+}
+/*-------------------------------------------------------------------------*/
 /*
 * This gets called after board-specific INIT_MACHINE, and initializes most
 * on-chip peripherals accessible on this board (except for few like USB):
@@ -396,6 +422,7 @@ static int __init omap1_init_devices(void)
        omap_init_spi100k();
        omap_init_sti();
        omap_init_uwire();
+        omap1_init_rng();
        return 0;
 }
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 3ef7d52316b4..29007fef84cd 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -27,7 +27,8 @@
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/irqs.h>
+#include <mach/irqs.h>
 #define OMAP1_DMA_BASE                  (0xfffed800)
 #define OMAP1_LOGICAL_DMA_CH_COUNT      17
@@ -330,8 +331,9 @@ static int __init omap1_system_dma_init(void)
        d->chan = kzalloc(sizeof(struct omap_dma_lch) *
                                        (d->lch_count), GFP_KERNEL);
        if (!d->chan) {
-                dev_err(&pdev->dev, "%s: Memory allocation failed"
+                dev_err(&pdev->dev,
-                                        "for d->chan!!!\n", __func__);
+                        "%s: Memory allocation failed for d->chan!\n",
+                        __func__);
                goto exit_release_d;
        }
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c
index 401eb3c080c2..73ae6169aa4a 100644
--- a/arch/arm/mach-omap1/flash.c
+++ b/arch/arm/mach-omap1/flash.c
@@ -11,7 +11,7 @@
 #include <linux/mtd/map.h>
 #include <plat/tc.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index ebef15e5e7b7..98e6f39224a4 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -17,6 +17,7 @@
 */
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 #define OMAP1_MPUIO_VBASE               OMAP1_MPUIO_BASE
 #define OMAP1510_GPIO_BASE              0xFFFCE000
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 2a48cd2e1754..33f419236b17 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -17,6 +17,7 @@
 */
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 #define OMAP1610_GPIO1_BASE             0xfffbe400
 #define OMAP1610_GPIO2_BASE             0xfffbec00
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index acf12b73eace..958ce9acee95 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -17,6 +17,7 @@
 */
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 #define OMAP7XX_GPIO1_BASE              0xfffbc000
 #define OMAP7XX_GPIO2_BASE              0xfffbc800
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c
index 5446c9912641..a0551a6d7451 100644
--- a/arch/arm/mach-omap1/i2c.c
+++ b/arch/arm/mach-omap1/i2c.c
@@ -20,7 +20,7 @@
 */
 #include <plat/i2c.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/cpu.h>
 void __init omap1_i2c_mux_pins(int bus_id)
diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
index 23eed0035ed8..adb5e7649659 100644
--- a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
+++ b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
@@ -14,8 +14,6 @@
 #ifndef __AMS_DELTA_FIQ_H
 #define __AMS_DELTA_FIQ_H
-#include <plat/irqs.h>
 /*
 * Interrupt number used for passing control from FIQ to IRQ.
 * IRQ12, described as reserved, has been selected.
diff --git a/arch/arm/plat-omap/include/plat/board-ams-delta.h b/arch/arm/mach-omap1/include/mach/board-ams-delta.h
index ad6f865d1f16..ad6f865d1f16 100644
--- a/arch/arm/plat-omap/include/plat/board-ams-delta.h
+++ b/arch/arm/mach-omap1/include/mach/board-ams-delta.h
diff --git a/arch/arm/plat-omap/include/plat/board-sx1.h b/arch/arm/mach-omap1/include/mach/board-sx1.h
index 355adbdaae33..355adbdaae33 100644
--- a/arch/arm/plat-omap/include/plat/board-sx1.h
+++ b/arch/arm/mach-omap1/include/mach/board-sx1.h
diff --git a/arch/arm/plat-omap/include/plat/board-voiceblue.h b/arch/arm/mach-omap1/include/mach/board-voiceblue.h
index 27916b210f57..27916b210f57 100644
--- a/arch/arm/plat-omap/include/plat/board-voiceblue.h
+++ b/arch/arm/mach-omap1/include/mach/board-voiceblue.h
diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/mach-omap1/include/mach/flash.h
index 0d88499b79e9..0d88499b79e9 100644
--- a/arch/arm/plat-omap/include/plat/flash.h
+++ b/arch/arm/mach-omap1/include/mach/flash.h
diff --git a/arch/arm/mach-omap1/include/mach/gpio.h b/arch/arm/mach-omap1/include/mach/gpio.h
index e737706a8fe1..ebf86c0f4f46 100644
--- a/arch/arm/mach-omap1/include/mach/gpio.h
+++ b/arch/arm/mach-omap1/include/mach/gpio.h
@@ -1,5 +1,3 @@
 /*
 * arch/arm/mach-omap1/include/mach/gpio.h
 */
-#include <plat/gpio.h>
diff --git a/arch/arm/mach-omap1/include/mach/hardware.h b/arch/arm/mach-omap1/include/mach/hardware.h
index 01e35fa106b8..84248d250adb 100644
--- a/arch/arm/mach-omap1/include/mach/hardware.h
+++ b/arch/arm/mach-omap1/include/mach/hardware.h
@@ -1,11 +1,46 @@
 /*
 * arch/arm/mach-omap1/include/mach/hardware.h
+ *
+ * Hardware definitions for TI OMAP processors and boards
+ *
+ * NOTE: Please put device driver specific defines into a separate header
+ *       file for each driver.
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
+ *                          and Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
 */
-#ifndef __MACH_HARDWARE_H
+#ifndef __ASM_ARCH_OMAP_HARDWARE_H
-#define __MACH_HARDWARE_H
+#define __ASM_ARCH_OMAP_HARDWARE_H
+#include <asm/sizes.h>
 #ifndef __ASSEMBLER__
+#include <asm/types.h>
+#include <plat/cpu.h>
 /*
 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
 */
@@ -35,7 +70,249 @@ static inline u32 omap_cs3_phys(void)
                        ? 0 : OMAP_CS3_PHYS;
 }
+#endif  /* ifndef __ASSEMBLER__ */
+#include <plat/serial.h>
+/*
+ * ---------------------------------------------------------------------------
+ * Common definitions for all OMAP processors
+ * NOTE: Put all processor or board specific parts to the special header
+ *       files.
+ * ---------------------------------------------------------------------------
+ */
+/*
+ * ----------------------------------------------------------------------------
+ * Timers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_MPU_TIMER1_BASE    (0xfffec500)
+#define OMAP_MPU_TIMER2_BASE    (0xfffec600)
+#define OMAP_MPU_TIMER3_BASE    (0xfffec700)
+#define MPU_TIMER_FREE          (1 << 6)
+#define MPU_TIMER_CLOCK_ENABLE  (1 << 5)
+#define MPU_TIMER_AR            (1 << 1)
+#define MPU_TIMER_ST            (1 << 0)
+/*
+ * ----------------------------------------------------------------------------
+ * Clocks
+ * ----------------------------------------------------------------------------
+ */
+#define CLKGEN_REG_BASE         (0xfffece00)
+#define ARM_CKCTL               (CLKGEN_REG_BASE + 0x0)
+#define ARM_IDLECT1             (CLKGEN_REG_BASE + 0x4)
+#define ARM_IDLECT2             (CLKGEN_REG_BASE + 0x8)
+#define ARM_EWUPCT              (CLKGEN_REG_BASE + 0xC)
+#define ARM_RSTCT1              (CLKGEN_REG_BASE + 0x10)
+#define ARM_RSTCT2              (CLKGEN_REG_BASE + 0x14)
+#define ARM_SYSST               (CLKGEN_REG_BASE + 0x18)
+#define ARM_IDLECT3             (CLKGEN_REG_BASE + 0x24)
+#define CK_RATEF                1
+#define CK_IDLEF                2
+#define CK_ENABLEF              4
+#define CK_SELECTF              8
+#define SETARM_IDLE_SHIFT
+/* DPLL control registers */
+#define DPLL_CTL                (0xfffecf00)
+/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
+#define DSP_CONFIG_REG_BASE     IOMEM(0xe1008000)
+#define DSP_CKCTL               (DSP_CONFIG_REG_BASE + 0x0)
+#define DSP_IDLECT1             (DSP_CONFIG_REG_BASE + 0x4)
+#define DSP_IDLECT2             (DSP_CONFIG_REG_BASE + 0x8)
+#define DSP_RSTCT2              (DSP_CONFIG_REG_BASE + 0x14)
+/*
+ * ---------------------------------------------------------------------------
+ * UPLD
+ * ---------------------------------------------------------------------------
+ */
+#define ULPD_REG_BASE           (0xfffe0800)
+#define ULPD_IT_STATUS          (ULPD_REG_BASE + 0x14)
+#define ULPD_SETUP_ANALOG_CELL_3        (ULPD_REG_BASE + 0x24)
+#define ULPD_CLOCK_CTRL         (ULPD_REG_BASE + 0x30)
+#       define DIS_USB_PVCI_CLK         (1 << 5)        /* no USB/FAC synch */
+#       define USB_MCLK_EN              (1 << 4)        /* enable W4_USB_CLKO */
+#define ULPD_SOFT_REQ           (ULPD_REG_BASE + 0x34)
+#       define SOFT_UDC_REQ             (1 << 4)
+#       define SOFT_USB_CLK_REQ         (1 << 3)
+#       define SOFT_DPLL_REQ            (1 << 0)
+#define ULPD_DPLL_CTRL          (ULPD_REG_BASE + 0x3c)
+#define ULPD_STATUS_REQ         (ULPD_REG_BASE + 0x40)
+#define ULPD_APLL_CTRL          (ULPD_REG_BASE + 0x4c)
+#define ULPD_POWER_CTRL         (ULPD_REG_BASE + 0x50)
+#define ULPD_SOFT_DISABLE_REQ_REG       (ULPD_REG_BASE + 0x68)
+#       define DIS_MMC2_DPLL_REQ        (1 << 11)
+#       define DIS_MMC1_DPLL_REQ        (1 << 10)
+#       define DIS_UART3_DPLL_REQ       (1 << 9)
+#       define DIS_UART2_DPLL_REQ       (1 << 8)
+#       define DIS_UART1_DPLL_REQ       (1 << 7)
+#       define DIS_USB_HOST_DPLL_REQ    (1 << 6)
+#define ULPD_SDW_CLK_DIV_CTRL_SEL       (ULPD_REG_BASE + 0x74)
+#define ULPD_CAM_CLK_CTRL       (ULPD_REG_BASE + 0x7c)
+/*
+ * ---------------------------------------------------------------------------
+ * Watchdog timer
+ * ---------------------------------------------------------------------------
+ */
+/* Watchdog timer within the OMAP3.2 gigacell */
+#define OMAP_MPU_WATCHDOG_BASE  (0xfffec800)
+#define OMAP_WDT_TIMER          (OMAP_MPU_WATCHDOG_BASE + 0x0)
+#define OMAP_WDT_LOAD_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
+#define OMAP_WDT_READ_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
+#define OMAP_WDT_TIMER_MODE     (OMAP_MPU_WATCHDOG_BASE + 0x8)
+/*
+ * ---------------------------------------------------------------------------
+ * Interrupts
+ * ---------------------------------------------------------------------------
+ */
+#ifdef CONFIG_ARCH_OMAP1
+/*
+ * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
+ * or something similar.. -- PFM.
+ */
+#define OMAP_IH1_BASE           0xfffecb00
+#define OMAP_IH2_BASE           0xfffe0000
+#define OMAP_IH1_ITR            (OMAP_IH1_BASE + 0x00)
+#define OMAP_IH1_MIR            (OMAP_IH1_BASE + 0x04)
+#define OMAP_IH1_SIR_IRQ        (OMAP_IH1_BASE + 0x10)
+#define OMAP_IH1_SIR_FIQ        (OMAP_IH1_BASE + 0x14)
+#define OMAP_IH1_CONTROL        (OMAP_IH1_BASE + 0x18)
+#define OMAP_IH1_ILR0           (OMAP_IH1_BASE + 0x1c)
+#define OMAP_IH1_ISR            (OMAP_IH1_BASE + 0x9c)
+#define OMAP_IH2_ITR            (OMAP_IH2_BASE + 0x00)
+#define OMAP_IH2_MIR            (OMAP_IH2_BASE + 0x04)
+#define OMAP_IH2_SIR_IRQ        (OMAP_IH2_BASE + 0x10)
+#define OMAP_IH2_SIR_FIQ        (OMAP_IH2_BASE + 0x14)
+#define OMAP_IH2_CONTROL        (OMAP_IH2_BASE + 0x18)
+#define OMAP_IH2_ILR0           (OMAP_IH2_BASE + 0x1c)
+#define OMAP_IH2_ISR            (OMAP_IH2_BASE + 0x9c)
+#define IRQ_ITR_REG_OFFSET      0x00
+#define IRQ_MIR_REG_OFFSET      0x04
+#define IRQ_SIR_IRQ_REG_OFFSET  0x10
+#define IRQ_SIR_FIQ_REG_OFFSET  0x14
+#define IRQ_CONTROL_REG_OFFSET  0x18
+#define IRQ_ISR_REG_OFFSET      0x9c
+#define IRQ_ILR0_REG_OFFSET     0x1c
+#define IRQ_GMR_REG_OFFSET      0xa0
 #endif
-#endif
-#include <plat/hardware.h>
+/*
+ * ----------------------------------------------------------------------------
+ * System control registers
+ * ----------------------------------------------------------------------------
+ */
+#define MOD_CONF_CTRL_0         0xfffe1080
+#define MOD_CONF_CTRL_1         0xfffe1110
+/*
+ * ----------------------------------------------------------------------------
+ * Pin multiplexing registers
+ * ----------------------------------------------------------------------------
+ */
+#define FUNC_MUX_CTRL_0         0xfffe1000
+#define FUNC_MUX_CTRL_1         0xfffe1004
+#define FUNC_MUX_CTRL_2         0xfffe1008
+#define COMP_MODE_CTRL_0        0xfffe100c
+#define FUNC_MUX_CTRL_3         0xfffe1010
+#define FUNC_MUX_CTRL_4         0xfffe1014
+#define FUNC_MUX_CTRL_5         0xfffe1018
+#define FUNC_MUX_CTRL_6         0xfffe101C
+#define FUNC_MUX_CTRL_7         0xfffe1020
+#define FUNC_MUX_CTRL_8         0xfffe1024
+#define FUNC_MUX_CTRL_9         0xfffe1028
+#define FUNC_MUX_CTRL_A         0xfffe102C
+#define FUNC_MUX_CTRL_B         0xfffe1030
+#define FUNC_MUX_CTRL_C         0xfffe1034
+#define FUNC_MUX_CTRL_D         0xfffe1038
+#define PULL_DWN_CTRL_0         0xfffe1040
+#define PULL_DWN_CTRL_1         0xfffe1044
+#define PULL_DWN_CTRL_2         0xfffe1048
+#define PULL_DWN_CTRL_3         0xfffe104c
+#define PULL_DWN_CTRL_4         0xfffe10ac
+/* OMAP-1610 specific multiplexing registers */
+#define FUNC_MUX_CTRL_E         0xfffe1090
+#define FUNC_MUX_CTRL_F         0xfffe1094
+#define FUNC_MUX_CTRL_10        0xfffe1098
+#define FUNC_MUX_CTRL_11        0xfffe109c
+#define FUNC_MUX_CTRL_12        0xfffe10a0
+#define PU_PD_SEL_0             0xfffe10b4
+#define PU_PD_SEL_1             0xfffe10b8
+#define PU_PD_SEL_2             0xfffe10bc
+#define PU_PD_SEL_3             0xfffe10c0
+#define PU_PD_SEL_4             0xfffe10c4
+/* Timer32K for 1610 and 1710*/
+#define OMAP_TIMER32K_BASE      0xFFFBC400
+/*
+ * ---------------------------------------------------------------------------
+ * TIPB bus interface
+ * ---------------------------------------------------------------------------
+ */
+#define TIPB_PUBLIC_CNTL_BASE           0xfffed300
+#define MPU_PUBLIC_TIPB_CNTL            (TIPB_PUBLIC_CNTL_BASE + 0x8)
+#define TIPB_PRIVATE_CNTL_BASE          0xfffeca00
+#define MPU_PRIVATE_TIPB_CNTL           (TIPB_PRIVATE_CNTL_BASE + 0x8)
+/*
+ * ----------------------------------------------------------------------------
+ * MPUI interface
+ * ----------------------------------------------------------------------------
+ */
+#define MPUI_BASE                       (0xfffec900)
+#define MPUI_CTRL                       (MPUI_BASE + 0x0)
+#define MPUI_DEBUG_ADDR                 (MPUI_BASE + 0x4)
+#define MPUI_DEBUG_DATA                 (MPUI_BASE + 0x8)
+#define MPUI_DEBUG_FLAG                 (MPUI_BASE + 0xc)
+#define MPUI_STATUS_REG                 (MPUI_BASE + 0x10)
+#define MPUI_DSP_STATUS                 (MPUI_BASE + 0x14)
+#define MPUI_DSP_BOOT_CONFIG            (MPUI_BASE + 0x18)
+#define MPUI_DSP_API_CONFIG             (MPUI_BASE + 0x1c)
+/*
+ * ----------------------------------------------------------------------------
+ * LED Pulse Generator
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_LPG1_BASE                  0xfffbd000
+#define OMAP_LPG2_BASE                  0xfffbd800
+#define OMAP_LPG1_LCR                   (OMAP_LPG1_BASE + 0x00)
+#define OMAP_LPG1_PMR                   (OMAP_LPG1_BASE + 0x04)
+#define OMAP_LPG2_LCR                   (OMAP_LPG2_BASE + 0x00)
+#define OMAP_LPG2_PMR                   (OMAP_LPG2_BASE + 0x04)
+/*
+ * ----------------------------------------------------------------------------
+ * Pulse-Width Light
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_PWL_BASE                   0xfffb5800
+#define OMAP_PWL_ENABLE                 (OMAP_PWL_BASE + 0x00)
+#define OMAP_PWL_CLK_ENABLE             (OMAP_PWL_BASE + 0x04)
+/*
+ * ---------------------------------------------------------------------------
+ * Processor specific defines
+ * ---------------------------------------------------------------------------
+ */
+#include "omap7xx.h"
+#include "omap1510.h"
+#include "omap16xx.h"
+#endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/irda.h b/arch/arm/mach-omap1/include/mach/irda.h
index 40f60339d1c6..40f60339d1c6 100644
--- a/arch/arm/plat-omap/include/plat/irda.h
+++ b/arch/arm/mach-omap1/include/mach/irda.h
diff --git a/arch/arm/mach-omap1/include/mach/irqs.h b/arch/arm/mach-omap1/include/mach/irqs.h
index 9292fdc1cb0b..729992d7d26a 100644
--- a/arch/arm/mach-omap1/include/mach/irqs.h
+++ b/arch/arm/mach-omap1/include/mach/irqs.h
@@ -1,5 +1,268 @@
 /*
- * arch/arm/mach-omap1/include/mach/irqs.h
+ *  arch/arm/plat-omap/include/mach/irqs.h
+ *
+ *  Copyright (C) Greg Lonnon 2001
+ *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
+ *       are different.
 */
-#include <plat/irqs.h>
+#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
+#define __ASM_ARCH_OMAP15XX_IRQS_H
+/*
+ * IRQ numbers for interrupt handler 1
+ *
+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ *
+ */
+#define INT_CAMERA              1
+#define INT_FIQ                 3
+#define INT_RTDX                6
+#define INT_DSP_MMU_ABORT       7
+#define INT_HOST                8
+#define INT_ABORT               9
+#define INT_BRIDGE_PRIV         13
+#define INT_GPIO_BANK1          14
+#define INT_UART3               15
+#define INT_TIMER3              16
+#define INT_DMA_CH0_6           19
+#define INT_DMA_CH1_7           20
+#define INT_DMA_CH2_8           21
+#define INT_DMA_CH3             22
+#define INT_DMA_CH4             23
+#define INT_DMA_CH5             24
+#define INT_TIMER1              26
+#define INT_WD_TIMER            27
+#define INT_BRIDGE_PUB          28
+#define INT_TIMER2              30
+#define INT_LCD_CTRL            31
+/*
+ * OMAP-1510 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_1510_IH2_IRQ        0
+#define INT_1510_RES2           2
+#define INT_1510_SPI_TX         4
+#define INT_1510_SPI_RX         5
+#define INT_1510_DSP_MAILBOX1   10
+#define INT_1510_DSP_MAILBOX2   11
+#define INT_1510_RES12          12
+#define INT_1510_LB_MMU         17
+#define INT_1510_RES18          18
+#define INT_1510_LOCAL_BUS      29
+/*
+ * OMAP-1610 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_1610_IH2_IRQ        INT_1510_IH2_IRQ
+#define INT_1610_IH2_FIQ        2
+#define INT_1610_McBSP2_TX      4
+#define INT_1610_McBSP2_RX      5
+#define INT_1610_DSP_MAILBOX1   10
+#define INT_1610_DSP_MAILBOX2   11
+#define INT_1610_LCD_LINE       12
+#define INT_1610_GPTIMER1       17
+#define INT_1610_GPTIMER2       18
+#define INT_1610_SSR_FIFO_0     29
+/*
+ * OMAP-7xx specific IRQ numbers for interrupt handler 1
+ */
+#define INT_7XX_IH2_FIQ         0
+#define INT_7XX_IH2_IRQ         1
+#define INT_7XX_USB_NON_ISO     2
+#define INT_7XX_USB_ISO         3
+#define INT_7XX_ICR             4
+#define INT_7XX_EAC             5
+#define INT_7XX_GPIO_BANK1      6
+#define INT_7XX_GPIO_BANK2      7
+#define INT_7XX_GPIO_BANK3      8
+#define INT_7XX_McBSP2TX        10
+#define INT_7XX_McBSP2RX        11
+#define INT_7XX_McBSP2RX_OVF    12
+#define INT_7XX_LCD_LINE        14
+#define INT_7XX_GSM_PROTECT     15
+#define INT_7XX_TIMER3          16
+#define INT_7XX_GPIO_BANK5      17
+#define INT_7XX_GPIO_BANK6      18
+#define INT_7XX_SPGIO_WR        29
+/*
+ * IRQ numbers for interrupt handler 2
+ *
+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ */
+#define IH2_BASE                32
+#define INT_KEYBOARD            (1 + IH2_BASE)
+#define INT_uWireTX             (2 + IH2_BASE)
+#define INT_uWireRX             (3 + IH2_BASE)
+#define INT_I2C                 (4 + IH2_BASE)
+#define INT_MPUIO               (5 + IH2_BASE)
+#define INT_USB_HHC_1           (6 + IH2_BASE)
+#define INT_McBSP3TX            (10 + IH2_BASE)
+#define INT_McBSP3RX            (11 + IH2_BASE)
+#define INT_McBSP1TX            (12 + IH2_BASE)
+#define INT_McBSP1RX            (13 + IH2_BASE)
+#define INT_UART1               (14 + IH2_BASE)
+#define INT_UART2               (15 + IH2_BASE)
+#define INT_BT_MCSI1TX          (16 + IH2_BASE)
+#define INT_BT_MCSI1RX          (17 + IH2_BASE)
+#define INT_SOSSI_MATCH         (19 + IH2_BASE)
+#define INT_USB_W2FC            (20 + IH2_BASE)
+#define INT_1WIRE               (21 + IH2_BASE)
+#define INT_OS_TIMER            (22 + IH2_BASE)
+#define INT_MMC                 (23 + IH2_BASE)
+#define INT_GAUGE_32K           (24 + IH2_BASE)
+#define INT_RTC_TIMER           (25 + IH2_BASE)
+#define INT_RTC_ALARM           (26 + IH2_BASE)
+#define INT_MEM_STICK           (27 + IH2_BASE)
+/*
+ * OMAP-1510 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_1510_DSP_MMU        (28 + IH2_BASE)
+#define INT_1510_COM_SPI_RO     (31 + IH2_BASE)
+/*
+ * OMAP-1610 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_1610_FAC            (0 + IH2_BASE)
+#define INT_1610_USB_HHC_2      (7 + IH2_BASE)
+#define INT_1610_USB_OTG        (8 + IH2_BASE)
+#define INT_1610_SoSSI          (9 + IH2_BASE)
+#define INT_1610_SoSSI_MATCH    (19 + IH2_BASE)
+#define INT_1610_DSP_MMU        (28 + IH2_BASE)
+#define INT_1610_McBSP2RX_OF    (31 + IH2_BASE)
+#define INT_1610_STI            (32 + IH2_BASE)
+#define INT_1610_STI_WAKEUP     (33 + IH2_BASE)
+#define INT_1610_GPTIMER3       (34 + IH2_BASE)
+#define INT_1610_GPTIMER4       (35 + IH2_BASE)
+#define INT_1610_GPTIMER5       (36 + IH2_BASE)
+#define INT_1610_GPTIMER6       (37 + IH2_BASE)
+#define INT_1610_GPTIMER7       (38 + IH2_BASE)
+#define INT_1610_GPTIMER8       (39 + IH2_BASE)
+#define INT_1610_GPIO_BANK2     (40 + IH2_BASE)
+#define INT_1610_GPIO_BANK3     (41 + IH2_BASE)
+#define INT_1610_MMC2           (42 + IH2_BASE)
+#define INT_1610_CF             (43 + IH2_BASE)
+#define INT_1610_WAKE_UP_REQ    (46 + IH2_BASE)
+#define INT_1610_GPIO_BANK4     (48 + IH2_BASE)
+#define INT_1610_SPI            (49 + IH2_BASE)
+#define INT_1610_DMA_CH6        (53 + IH2_BASE)
+#define INT_1610_DMA_CH7        (54 + IH2_BASE)
+#define INT_1610_DMA_CH8        (55 + IH2_BASE)
+#define INT_1610_DMA_CH9        (56 + IH2_BASE)
+#define INT_1610_DMA_CH10       (57 + IH2_BASE)
+#define INT_1610_DMA_CH11       (58 + IH2_BASE)
+#define INT_1610_DMA_CH12       (59 + IH2_BASE)
+#define INT_1610_DMA_CH13       (60 + IH2_BASE)
+#define INT_1610_DMA_CH14       (61 + IH2_BASE)
+#define INT_1610_DMA_CH15       (62 + IH2_BASE)
+#define INT_1610_NAND           (63 + IH2_BASE)
+#define INT_1610_SHA1MD5        (91 + IH2_BASE)
+/*
+ * OMAP-7xx specific IRQ numbers for interrupt handler 2
+ */
+#define INT_7XX_HW_ERRORS       (0 + IH2_BASE)
+#define INT_7XX_NFIQ_PWR_FAIL   (1 + IH2_BASE)
+#define INT_7XX_CFCD            (2 + IH2_BASE)
+#define INT_7XX_CFIREQ          (3 + IH2_BASE)
+#define INT_7XX_I2C             (4 + IH2_BASE)
+#define INT_7XX_PCC             (5 + IH2_BASE)
+#define INT_7XX_MPU_EXT_NIRQ    (6 + IH2_BASE)
+#define INT_7XX_SPI_100K_1      (7 + IH2_BASE)
+#define INT_7XX_SYREN_SPI       (8 + IH2_BASE)
+#define INT_7XX_VLYNQ           (9 + IH2_BASE)
+#define INT_7XX_GPIO_BANK4      (10 + IH2_BASE)
+#define INT_7XX_McBSP1TX        (11 + IH2_BASE)
+#define INT_7XX_McBSP1RX        (12 + IH2_BASE)
+#define INT_7XX_McBSP1RX_OF     (13 + IH2_BASE)
+#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
+#define INT_7XX_UART_MODEM_1    (15 + IH2_BASE)
+#define INT_7XX_MCSI            (16 + IH2_BASE)
+#define INT_7XX_uWireTX         (17 + IH2_BASE)
+#define INT_7XX_uWireRX         (18 + IH2_BASE)
+#define INT_7XX_SMC_CD          (19 + IH2_BASE)
+#define INT_7XX_SMC_IREQ        (20 + IH2_BASE)
+#define INT_7XX_HDQ_1WIRE       (21 + IH2_BASE)
+#define INT_7XX_TIMER32K        (22 + IH2_BASE)
+#define INT_7XX_MMC_SDIO        (23 + IH2_BASE)
+#define INT_7XX_UPLD            (24 + IH2_BASE)
+#define INT_7XX_USB_HHC_1       (27 + IH2_BASE)
+#define INT_7XX_USB_HHC_2       (28 + IH2_BASE)
+#define INT_7XX_USB_GENI        (29 + IH2_BASE)
+#define INT_7XX_USB_OTG         (30 + IH2_BASE)
+#define INT_7XX_CAMERA_IF       (31 + IH2_BASE)
+#define INT_7XX_RNG             (32 + IH2_BASE)
+#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
+#define INT_7XX_DBB_RF_EN       (34 + IH2_BASE)
+#define INT_7XX_MPUIO_KEYPAD    (35 + IH2_BASE)
+#define INT_7XX_SHA1_MD5        (36 + IH2_BASE)
+#define INT_7XX_SPI_100K_2      (37 + IH2_BASE)
+#define INT_7XX_RNG_IDLE        (38 + IH2_BASE)
+#define INT_7XX_MPUIO           (39 + IH2_BASE)
+#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
+#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
+#define INT_7XX_LLPC_OE_RISING  (42 + IH2_BASE)
+#define INT_7XX_LLPC_VSYNC      (43 + IH2_BASE)
+#define INT_7XX_WAKE_UP_REQ     (46 + IH2_BASE)
+#define INT_7XX_DMA_CH6         (53 + IH2_BASE)
+#define INT_7XX_DMA_CH7         (54 + IH2_BASE)
+#define INT_7XX_DMA_CH8         (55 + IH2_BASE)
+#define INT_7XX_DMA_CH9         (56 + IH2_BASE)
+#define INT_7XX_DMA_CH10        (57 + IH2_BASE)
+#define INT_7XX_DMA_CH11        (58 + IH2_BASE)
+#define INT_7XX_DMA_CH12        (59 + IH2_BASE)
+#define INT_7XX_DMA_CH13        (60 + IH2_BASE)
+#define INT_7XX_DMA_CH14        (61 + IH2_BASE)
+#define INT_7XX_DMA_CH15        (62 + IH2_BASE)
+#define INT_7XX_NAND            (63 + IH2_BASE)
+/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
+ * 16 MPUIO lines */
+#define OMAP_MAX_GPIO_LINES     192
+#define IH_GPIO_BASE            (128 + IH2_BASE)
+#define IH_MPUIO_BASE           (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
+#define OMAP_IRQ_END            (IH_MPUIO_BASE + 16)
+/* External FPGA handles interrupts on Innovator boards */
+#define OMAP_FPGA_IRQ_BASE      (OMAP_IRQ_END)
+#ifdef  CONFIG_MACH_OMAP_INNOVATOR
+#define OMAP_FPGA_NR_IRQS       24
+#else
+#define OMAP_FPGA_NR_IRQS       0
+#endif
+#define OMAP_FPGA_IRQ_END       (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
+#define NR_IRQS                 OMAP_FPGA_IRQ_END
+#define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
+#include <mach/hardware.h>
+#ifdef CONFIG_FIQ
+#define FIQ_START               1024
+#endif
+#endif
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/mach-omap1/include/mach/mux.h
index 323948959200..323948959200 100644
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ b/arch/arm/mach-omap1/include/mach/mux.h
diff --git a/arch/arm/plat-omap/include/plat/omap1510.h b/arch/arm/mach-omap1/include/mach/omap1510.h
index d24004668138..8fe05d6137c0 100644
--- a/arch/arm/plat-omap/include/plat/omap1510.h
+++ b/arch/arm/mach-omap1/include/mach/omap1510.h
@@ -1,5 +1,4 @@
-/* arch/arm/plat-omap/include/mach/omap1510.h
+/*
- *
 * Hardware definitions for TI OMAP1510 processor.
 *
 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
diff --git a/arch/arm/plat-omap/include/plat/omap16xx.h b/arch/arm/mach-omap1/include/mach/omap16xx.h
index e69e1d857b45..cd1c724869c7 100644
--- a/arch/arm/plat-omap/include/plat/omap16xx.h
+++ b/arch/arm/mach-omap1/include/mach/omap16xx.h
@@ -1,5 +1,4 @@
-/* arch/arm/plat-omap/include/mach/omap16xx.h
+/*
- *
 * Hardware definitions for TI OMAP1610/5912/1710 processors.
 *
 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/mach-omap1/include/mach/omap7xx.h
index 48e4757e1e30..63da994bc609 100644
--- a/arch/arm/plat-omap/include/plat/omap7xx.h
+++ b/arch/arm/mach-omap1/include/mach/omap7xx.h
@@ -1,5 +1,4 @@
-/* arch/arm/plat-omap/include/mach/omap7xx.h
+/*
- *
 * Hardware definitions for TI OMAP7XX processor.
 *
 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
diff --git a/arch/arm/mach-omap1/include/mach/smp.h b/arch/arm/mach-omap1/include/mach/smp.h
deleted file mode 100644
index 80a371c06e59..000000000000
--- a/arch/arm/mach-omap1/include/mach/smp.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap1/include/mach/smp.h
- */
-#include <plat/smp.h>
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 6c95a59f0f16..6a5baab1f4cb 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -16,7 +16,7 @@
 #include <asm/tlb.h>
 #include <asm/mach/map.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
 #include <plat/dma.h>
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
index 5769c71815b2..ed42628611bc 100644
--- a/arch/arm/mach-omap1/lcd_dma.c
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -113,8 +113,7 @@ EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
 {
        if (cpu_is_omap15xx()) {
-                printk(KERN_ERR "DMA virtual resolution is not supported "
+                pr_err("DMA virtual resolution is not supported in 1510 mode\n");
-                                "in 1510 mode\n");
                BUG();
        }
        lcd_dma.vxres = vxres;
@@ -437,8 +436,7 @@ static int __init omap_init_lcd_dma(void)
        r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
                        "LCD DMA", NULL);
        if (r != 0)
-                printk(KERN_ERR "unable to request IRQ for LCD DMA "
+                pr_err("unable to request IRQ for LCD DMA (error %d)\n", r);
-                               "(error %d)\n", r);
        return r;
 }
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
deleted file mode 100644
index f6b14a14a957..000000000000
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds-h2p2-debug.c
- *
- * Copyright 2003 by Texas Instruments Incorporated
- *
- * There are 16 LEDs on the debug board (all green); four may be used
- * for logical 'green', 'amber', 'red', and 'blue' (after "claiming").
- *
- * The "surfer" expansion board and H2 sample board also have two-color
- * green+red LEDs (in parallel), used here for timer and idle indicators.
- */
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/sched.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-#include <plat/fpga.h>
-#include "leds.h"
-#define GPIO_LED_RED            3
-#define GPIO_LED_GREEN          OMAP_MPUIO(4)
-#define LED_STATE_ENABLED       0x01
-#define LED_STATE_CLAIMED       0x02
-#define LED_TIMER_ON            0x04
-#define GPIO_IDLE               GPIO_LED_GREEN
-#define GPIO_TIMER              GPIO_LED_RED
-void h2p2_dbg_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        static struct h2p2_dbg_fpga __iomem *fpga;
-        static u16 led_state, hw_led_state;
-        local_irq_save(flags);
-        if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
-                goto done;
-        switch (evt) {
-        case led_start:
-                if (!fpga)
-                        fpga = ioremap(H2P2_DBG_FPGA_START,
-                                                H2P2_DBG_FPGA_SIZE);
-                if (fpga) {
-                        led_state |= LED_STATE_ENABLED;
-                        __raw_writew(~0, &fpga->leds);
-                }
-                break;
-        case led_stop:
-        case led_halted:
-                /* all leds off during suspend or shutdown */
-                if (! machine_is_omap_perseus2()) {
-                        gpio_set_value(GPIO_TIMER, 0);
-                        gpio_set_value(GPIO_IDLE, 0);
-                }
-                __raw_writew(~0, &fpga->leds);
-                led_state &= ~LED_STATE_ENABLED;
-                if (evt == led_halted) {
-                        iounmap(fpga);
-                        fpga = NULL;
-                }
-                goto done;
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                led_state ^= LED_TIMER_ON;
-                if (machine_is_omap_perseus2())
-                        hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER;
-                else {
-                        gpio_set_value(GPIO_TIMER, led_state & LED_TIMER_ON);
-                        goto done;
-                }
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (machine_is_omap_perseus2())
-                        hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE;
-                else {
-                        gpio_set_value(GPIO_IDLE, 1);
-                        goto done;
-                }
-                break;
-        case led_idle_end:
-                if (machine_is_omap_perseus2())
-                        hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE;
-                else {
-                        gpio_set_value(GPIO_IDLE, 0);
-                        goto done;
-                }
-                break;
-#endif
-        case led_green_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_GREEN;
-                break;
-        case led_green_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_GREEN;
-                break;
-        case led_amber_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_AMBER;
-                break;
-        case led_amber_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_AMBER;
-                break;
-        case led_red_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_RED;
-                break;
-        case led_red_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_RED;
-                break;
-        case led_blue_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_BLUE;
-                break;
-        case led_blue_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_BLUE;
-                break;
-        default:
-                break;
-        }
-        /*
-         *  Actually burn the LEDs
-         */
-        if (led_state & LED_STATE_ENABLED)
-                __raw_writew(~hw_led_state, &fpga->leds);
-done:
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-omap1/leds-innovator.c b/arch/arm/mach-omap1/leds-innovator.c
deleted file mode 100644
index 3a066ee8d02c..000000000000
--- a/arch/arm/mach-omap1/leds-innovator.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds-innovator.c
- */
-#include <linux/init.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include "leds.h"
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-static unsigned int led_state;
-static unsigned int hw_led_state;
-void innovator_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        switch (evt) {
-        case led_start:
-                hw_led_state = 0;
-                led_state = LED_STATE_ENABLED;
-                break;
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                hw_led_state = 0;
-                break;
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= 0;
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= 0;
-                break;
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~0;
-                break;
-#endif
-        case led_halted:
-                break;
-        case led_green_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~0;
-                break;
-        case led_green_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= 0;
-                break;
-        case led_amber_on:
-                break;
-        case led_amber_off:
-                break;
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~0;
-                break;
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= 0;
-                break;
-        default:
-                break;
-        }
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c
deleted file mode 100644
index 936ed426b84f..000000000000
--- a/arch/arm/mach-omap1/leds-osk.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds-osk.c
- *
- * LED driver for OSK with optional Mistral QVGA board
- */
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include "leds.h"
-#define LED_STATE_ENABLED       (1 << 0)
-#define LED_STATE_CLAIMED       (1 << 1)
-static u8 led_state;
-#define TIMER_LED               (1 << 3)        /* Mistral board */
-#define IDLE_LED                (1 << 4)        /* Mistral board */
-static u8 hw_led_state;
-#ifdef  CONFIG_OMAP_OSK_MISTRAL
-/* For now, all system indicators require the Mistral board, since that
- * LED can be manipulated without a task context.  This LED is either red,
- * or green, but not both; it can't give the full "disco led" effect.
- */
-#define GPIO_LED_RED            3
-#define GPIO_LED_GREEN          OMAP_MPUIO(4)
-static void mistral_setled(void)
-{
-        int     red = 0;
-        int     green = 0;
-        if (hw_led_state & TIMER_LED)
-                red = 1;
-        else if (hw_led_state & IDLE_LED)
-                green = 1;
-        /* else both sides are disabled */
-        gpio_set_value(GPIO_LED_GREEN, green);
-        gpio_set_value(GPIO_LED_RED, red);
-}
-#endif
-void osk_leds_event(led_event_t evt)
-{
-        unsigned long   flags;
-        u16             leds;
-        local_irq_save(flags);
-        if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
-                goto done;
-        leds = hw_led_state;
-        switch (evt) {
-        case led_start:
-                led_state |= LED_STATE_ENABLED;
-                hw_led_state = 0;
-                leds = ~0;
-                break;
-        case led_halted:
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                hw_led_state = 0;
-                break;
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                leds = ~0;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-#ifdef  CONFIG_OMAP_OSK_MISTRAL
-        case led_timer:
-                hw_led_state ^= TIMER_LED;
-                mistral_setled();
-                break;
-        case led_idle_start:    /* idle == off */
-                hw_led_state &= ~IDLE_LED;
-                mistral_setled();
-                break;
-        case led_idle_end:
-                hw_led_state |= IDLE_LED;
-                mistral_setled();
-                break;
-#endif  /* CONFIG_OMAP_OSK_MISTRAL */
-        default:
-                break;
-        }
-        leds ^= hw_led_state;
-done:
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c
deleted file mode 100644
index ae6dd93b8ddc..000000000000
--- a/arch/arm/mach-omap1/leds.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds.c
- *
- * OMAP LEDs dispatcher
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-#include <plat/mux.h>
-#include "leds.h"
-static int __init
-omap_leds_init(void)
-{
-        if (!cpu_class_is_omap1())
-                return -ENODEV;
-        if (machine_is_omap_innovator())
-                leds_event = innovator_leds_event;
-        else if (machine_is_omap_h2()
-                        || machine_is_omap_h3()
-                        || machine_is_omap_perseus2())
-                leds_event = h2p2_dbg_leds_event;
-        else if (machine_is_omap_osk())
-                leds_event = osk_leds_event;
-        else
-                return -1;
-        if (machine_is_omap_h2()
-                        || machine_is_omap_h3()
-#ifdef  CONFIG_OMAP_OSK_MISTRAL
-                        || machine_is_omap_osk()
-#endif
-                        ) {
-                /* LED1/LED2 pins can be used as GPIO (as done here), or by
-                 * the LPG (works even in deep sleep!), to drive a bicolor
-                 * LED on the H2 sample board, and another on the H2/P2
-                 * "surfer" expansion board.
-                 *
-                 * The same pins drive a LED on the OSK Mistral board, but
-                 * that's a different kind of LED (just one color at a time).
-                 */
-                omap_cfg_reg(P18_1610_GPIO3);
-                if (gpio_request(3, "LED red") == 0)
-                        gpio_direction_output(3, 1);
-                else
-                        printk(KERN_WARNING "LED: can't get GPIO3/red?\n");
-                omap_cfg_reg(MPUIO4);
-                if (gpio_request(OMAP_MPUIO(4), "LED green") == 0)
-                        gpio_direction_output(OMAP_MPUIO(4), 1);
-                else
-                        printk(KERN_WARNING "LED: can't get MPUIO4/green?\n");
-        }
-        leds_event(led_start);
-        return 0;
-}
-__initcall(omap_leds_init);
diff --git a/arch/arm/mach-omap1/leds.h b/arch/arm/mach-omap1/leds.h
deleted file mode 100644
index a1e9fedc376c..000000000000
--- a/arch/arm/mach-omap1/leds.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern void innovator_leds_event(led_event_t evt);
-extern void h2p2_dbg_leds_event(led_event_t evt);
-extern void osk_leds_event(led_event_t evt);
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index adf00975b9bb..bdc2e7541adb 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -20,9 +20,9 @@
 #include <linux/slab.h>
 #include <plat/dma.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/cpu.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index e9cc52d4cb28..667ce5027f63 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -29,7 +29,7 @@
 #include <mach/hardware.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #ifdef CONFIG_OMAP_MUX
@@ -451,6 +451,56 @@ static int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
 #endif
 }
+static struct omap_mux_cfg *mux_cfg;
+int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
+{
+        if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
+                        || !arch_mux_cfg->cfg_reg) {
+                printk(KERN_ERR "Invalid pin table\n");
+                return -EINVAL;
+        }
+        mux_cfg = arch_mux_cfg;
+        return 0;
+}
+/*
+ * Sets the Omap MUX and PULL_DWN registers based on the table
+ */
+int __init_or_module omap_cfg_reg(const unsigned long index)
+{
+        struct pin_config *reg;
+        if (!cpu_class_is_omap1()) {
+                printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
+                                index);
+                WARN_ON(1);
+                return -EINVAL;
+        }
+        if (mux_cfg == NULL) {
+                printk(KERN_ERR "Pin mux table not initialized\n");
+                return -ENODEV;
+        }
+        if (index >= mux_cfg->size) {
+                printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
+                       index, mux_cfg->size);
+                dump_stack();
+                return -ENODEV;
+        }
+        reg = &mux_cfg->pins[index];
+        if (!mux_cfg->cfg_reg)
+                return -ENODEV;
+        return mux_cfg->cfg_reg(reg);
+}
+EXPORT_SYMBOL(omap_cfg_reg);
 int __init omap1_mux_init(void)
 {
        if (cpu_is_omap7xx()) {
@@ -468,4 +518,8 @@ int __init omap1_mux_init(void)
        return omap_mux_register(&arch_mux_cfg);
 }
-#endif
+#else
+#define omap_mux_init() do {} while(0)
+#define omap_cfg_reg(x) do {} while(0)
+#endif  /* CONFIG_OMAP_MUX */
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index b2560d32b3a0..47ec16155483 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -53,7 +53,7 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/tc.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
 #include <plat/dmtimer.h>
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index 6809c9e56c93..b9d6834af835 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -22,8 +22,7 @@
 #include <asm/mach-types.h>
-#include <plat/board.h>
+#include <mach/mux.h>
-#include <plat/mux.h>
 #include <plat/fpga.h>
 #include "pm.h"
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 4062480bfec7..4d4816fd6fc9 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -44,7 +44,6 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
-#include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/sched_clock.h>
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index aa81593db1af..cdeb9d3ef640 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -141,7 +141,7 @@ static int __init omap1_dm_timer_init(void)
                pdata->set_timer_src = omap1_dm_timer_set_src;
                pdata->timer_capability = OMAP_TIMER_ALWON |
-                                OMAP_TIMER_NEEDS_RESET;
+                                OMAP_TIMER_NEEDS_RESET | OMAP_TIMER_HAS_DSP_IRQ;
                ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
                if (ret) {
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index eae49c3980c9..74529549130c 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -46,7 +46,6 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
-#include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index 65f88176fba8..84267edd9421 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -26,7 +26,7 @@
 #include <asm/irq.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <mach/usb.h>
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 346fd26f3aa6..a6219eaf1f68 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -18,12 +18,16 @@ config ARCH_OMAP2PLUS_TYPICAL
        select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
        select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
        select HIGHMEM
+        select PINCTRL
        help
          Compile a kernel suitable for booting most boards
 config SOC_HAS_OMAP2_SDRC
        bool "OMAP2 SDRAM Controller support"
+config SOC_HAS_REALTIME_COUNTER
+        bool "Real time free running counter"
 config ARCH_OMAP2
        bool "TI OMAP2"
        depends on ARCH_OMAP2PLUS
@@ -44,6 +48,7 @@ config ARCH_OMAP3
        select ARM_CPU_SUSPEND if PM
        select MULTI_IRQ_HANDLER
        select SOC_HAS_OMAP2_SDRC
+        select OMAP_INTERCONNECT
 config ARCH_OMAP4
        bool "TI OMAP4"
@@ -63,6 +68,7 @@ config ARCH_OMAP4
        select USB_ARCH_HAS_EHCI if USB_SUPPORT
        select ARM_CPU_SUSPEND if PM
        select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
+        select OMAP_INTERCONNECT
 config SOC_OMAP5
        bool "TI OMAP5"
@@ -70,6 +76,8 @@ config SOC_OMAP5
        select ARM_GIC
        select HAVE_SMP
        select ARM_CPU_SUSPEND if PM
+        select SOC_HAS_REALTIME_COUNTER
+        select ARM_ARCH_TIMER
 comment "OMAP Core Type"
        depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 34c2c7f59f0a..fe40d9e488c9 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,36 +4,30 @@
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
+         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o
-omap-2-3-common                         = irq.o
+# INTCPS IP block support - XXX should be moved to drivers/
-hwmod-common                            = omap_hwmod.o \
+obj-$(CONFIG_ARCH_OMAP2)                += irq.o
-                                          omap_hwmod_common_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += irq.o
-clock-common                            = clock.o clock_common_data.o \
+obj-$(CONFIG_SOC_AM33XX)                += irq.o
-                                          clkt_dpll.o clkt_clksel.o
-secure-common                           = omap-smc.o omap-secure.o
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
+# Secure monitor API support
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
+obj-$(CONFIG_ARCH_OMAP3)                += omap-smc.o omap-secure.o
-obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_ARCH_OMAP4)                += omap-smc.o omap-secure.o
-obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
+obj-$(CONFIG_SOC_OMAP5)                 += omap-smc.o omap-secure.o
-obj-$(CONFIG_SOC_OMAP5)  += prm44xx.o $(hwmod-common) $(secure-common)
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o
 endif
-obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
+obj-$(CONFIG_TWL4030_CORE)              += omap_twl.o
-obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)        += sdrc.o
 # SMP support ONLY available for OMAP4
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
-omap-4-5-common                         =  omap4-common.o omap-wakeupgen.o \
+obj-$(CONFIG_ARCH_OMAP4)                += omap4-common.o omap-wakeupgen.o
-                                           sleep44xx.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap4-common.o omap-wakeupgen.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-common)
-obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-common)
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
@@ -58,6 +52,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= mux44xx.o
 # SMS/SDRC
 obj-$(CONFIG_ARCH_OMAP2)                += sdrc2xxx.o
 # obj-$(CONFIG_ARCH_OMAP3)              += sdrc3xxx.o
+obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)        += sdrc.o
 # OPP table initialization
 ifeq ($(CONFIG_PM_OPP),y)
@@ -68,15 +63,15 @@ endif
 # Power Management
 ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
+obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o sleep24xx.o
-obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o
-obj-$(CONFIG_SOC_OMAP5)                 += omap-mpuss-lowpower.o
+obj-$(CONFIG_ARCH_OMAP4)                += sleep44xx.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap-mpuss-lowpower.o sleep44xx.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 obj-$(CONFIG_POWER_AVS_OMAP)            += sr_device.o
-obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)    += smartreflex-class3.o
+obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)     += smartreflex-class3.o
 AFLAGS_sleep24xx.o                      :=-Wa,-march=armv6
 AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a$(plus_sec)
@@ -88,92 +83,76 @@ endif
 endif
 ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
 endif
 # PRCM
-omap-prcm-4-5-common                    =  prcm.o cminst44xx.o cm44xx.o \
+obj-y                                   += prcm.o prm_common.o
-                                           prcm_mpu44xx.o prminst44xx.o \
+obj-$(CONFIG_ARCH_OMAP2)                += cm2xxx_3xxx.o prm2xxx_3xxx.o
-                                           vc44xx_data.o vp44xx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += cm2xxx_3xxx.o prm2xxx_3xxx.o
-obj-y                                   += prm_common.o
-obj-$(CONFIG_ARCH_OMAP2)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
-obj-$(CONFIG_ARCH_OMAP3)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += vc3xxx_data.o vp3xxx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += prcm.o prm33xx.o cm33xx.o
+obj-$(CONFIG_SOC_AM33XX)                += prm33xx.o cm33xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(omap-prcm-4-5-common) prm44xx.o
+omap-prcm-4-5-common                    =  cminst44xx.o cm44xx.o prm44xx.o \
+                                           prcm_mpu44xx.o prminst44xx.o \
+                                           vc44xx_data.o vp44xx_data.o \
+                                           prm44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(omap-prcm-4-5-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(omap-prcm-4-5-common)
 # OMAP voltage domains
-voltagedomain-common                    := voltage.o vc.o vp.o
+obj-y                                   += voltage.o vc.o vp.o
-obj-$(CONFIG_ARCH_OMAP2)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP2)                += voltagedomains2xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += voltagedomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += voltagedomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += $(voltagedomain-common)
+obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += $(voltagedomain-common)
 # OMAP powerdomain framework
-powerdomain-common                      += powerdomain.o powerdomain-common.o
+obj-y                                   += powerdomain.o powerdomain-common.o
-obj-$(CONFIG_ARCH_OMAP2)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP2)                += powerdomains2xxx_data.o
 obj-$(CONFIG_ARCH_OMAP2)                += powerdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP2)                += powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += powerdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += powerdomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomain44xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += $(powerdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += powerdomain33xx.o
 obj-$(CONFIG_SOC_AM33XX)                += powerdomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += $(powerdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += powerdomain44xx.o
 # PRCM clockdomain control
-clockdomain-common                      += clockdomain.o
+obj-y                                   += clockdomain.o
-obj-$(CONFIG_ARCH_OMAP2)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += clockdomains2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += clockdomains2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomain44xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += $(clockdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += clockdomain33xx.o
 obj-$(CONFIG_SOC_AM33XX)                += clockdomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += $(clockdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += clockdomain44xx.o
 # Clock framework
-obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o
+obj-y                                   += clock.o clock_common_data.o \
-obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_sys.o
+                                           clkt_dpll.o clkt_clksel.o
-obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpllcore.o
+obj-$(CONFIG_ARCH_OMAP2)                += clock2xxx.o
+obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpllcore.o clkt2xxx_sys.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_virt_prcm_set.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_apll.o clkt2xxx_osc.o
 obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpll.o clkt_iclk.o
 obj-$(CONFIG_SOC_OMAP2420)              += clock2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += clock2430.o clock2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(clock-common) clock3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o clkt34xx_dpll3m2.o
-obj-$(CONFIG_ARCH_OMAP3)                += clock3517.o clock36xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock3517.o clock36xx.o clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP3)                += dpll3xxx.o clock3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += clkt_iclk.o
+obj-$(CONFIG_ARCH_OMAP4)                += clock44xx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common) clock44xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += dpll3xxx.o dpll44xx.o
-obj-$(CONFIG_SOC_AM33XX)                += $(clock-common) dpll3xxx.o
+obj-$(CONFIG_SOC_AM33XX)                += dpll3xxx.o clock33xx_data.o
-obj-$(CONFIG_SOC_AM33XX)                += clock33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                 += $(clock-common)
 obj-$(CONFIG_SOC_OMAP5)                 += dpll3xxx.o dpll44xx.o
 # OMAP2 clock rate set data (old "OPP" data)
@@ -181,6 +160,7 @@ obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += opp2430_data.o
 # hwmod data
+obj-y                                   += omap_hwmod_common_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_3xxx_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_interconnect_data.o
@@ -194,15 +174,12 @@ obj-$(CONFIG_SOC_OMAP2430)		+= omap_hwmod_2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_2xxx_3xxx_ipblock_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_2xxx_3xxx_interconnect_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_3xxx_data.o
+obj-$(CONFIG_SOC_AM33XX)                += omap_hwmod_33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap_hwmod_44xx_data.o
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)                 += emu.o
+obj-$(CONFIG_HW_PERF_EVENTS)            += pmu.o
-# L3 interconnect
-obj-$(CONFIG_ARCH_OMAP3)                += omap_l3_smx.o
-obj-$(CONFIG_ARCH_OMAP4)                += omap_l3_noc.o
-obj-$(CONFIG_SOC_OMAP5)                 += omap_l3_noc.o
 obj-$(CONFIG_OMAP_MBOX_FWK)             += mailbox_mach.o
 mailbox_mach-objs                       := mailbox.o
@@ -229,10 +206,10 @@ obj-$(CONFIG_MACH_OMAP_H4)		+= board-h4.o
 obj-$(CONFIG_MACH_OMAP_2430SDP)         += board-2430sdp.o
 obj-$(CONFIG_MACH_OMAP_APOLLON)         += board-apollon.o
 obj-$(CONFIG_MACH_OMAP3_BEAGLE)         += board-omap3beagle.o
-obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
+obj-$(CONFIG_MACH_DEVKIT8000)           += board-devkit8000.o
 obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o
-obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
-obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
 obj-$(CONFIG_MACH_ENCORE)               += board-omap3encore.o
 obj-$(CONFIG_MACH_OVERO)                += board-overo.o
 obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o
diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/mach-omap2/am33xx.h
index 06c19bb7bca6..06c19bb7bca6 100644
--- a/arch/arm/plat-omap/include/plat/am33xx.h
+++ b/arch/arm/mach-omap2/am33xx.h
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index 2c90ac686686..d0c54c573d34 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -19,7 +19,7 @@
 #include <linux/davinci_emac.h>
 #include <asm/system.h>
 #include <plat/omap_device.h>
-#include <mach/am35xx.h>
+#include "am35xx.h"
 #include "control.h"
 #include "am35xx-emac.h"
diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/am35xx.h
index 95594495fcf6..95594495fcf6 100644
--- a/arch/arm/mach-omap2/include/mach/am35xx.h
+++ b/arch/arm/mach-omap2/am35xx.h
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 9511584fdc4f..95b384d54f8a 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -33,11 +33,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
@@ -212,9 +211,6 @@ static struct regulator_init_data sdp2430_vmmc1 = {
 };
 static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
 };
 static struct twl4030_platform_data sdp2430_twldata = {
@@ -235,7 +231,7 @@ static int __init omap2430_i2c_init(void)
        sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78);
        omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
                        ARRAY_SIZE(sdp2430_i2c1_boardinfo));
-        omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ,
+        omap_pmic_init(2, 100, "twl4030", 7 + OMAP_INTC_START,
                        &sdp2430_twldata);
        return 0;
 }
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index a98c688058a9..96cd3693e1ae 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -24,14 +24,12 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/mcspi.h>
-#include <plat/board.h>
 #include <plat/usb.h>
 #include "common.h"
 #include <plat/dma.h>
@@ -39,7 +37,7 @@
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
 #include "board-flash.h"
 #include "mux.h"
@@ -191,9 +189,6 @@ static struct omap_dss_board_info sdp3430_dss_data = {
        .default_device = &sdp3430_lcd_device,
 };
-static struct omap_board_config_kernel sdp3430_config[] __initdata = {
-};
 static struct omap2_hsmmc_info mmc[] = {
        {
                .mmc            = 1,
@@ -233,9 +228,6 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
 }
 static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
        .pulldowns      = BIT(2) | BIT(6) | BIT(8) | BIT(13)
                                | BIT(16) | BIT(17),
        .setup          = sdp3430_twl_gpio_setup,
@@ -576,8 +568,6 @@ static void __init omap_3430sdp_init(void)
        int gpio_pendown;
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-        omap_board_config = sdp3430_config;
-        omap_board_config_size = ARRAY_SIZE(sdp3430_config);
        omap_hsmmc_init(mmc);
        omap3430_i2c_init();
        omap_display_init(&sdp3430_dss_data);
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 2dc9ba523c7a..fc224ad86747 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -17,8 +17,7 @@
 #include <asm/mach/arch.h>
 #include "common.h"
-#include <plat/board.h>
+#include "gpmc-smc91x.h"
-#include <plat/gpmc-smc91x.h>
 #include <plat/usb.h>
 #include <mach/board-zoom.h>
@@ -67,9 +66,6 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
        .reset_gpio_port[2]  = -EINVAL
 };
-static struct omap_board_config_kernel sdp_config[] __initdata = {
-};
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -197,8 +193,6 @@ static struct flash_partitions sdp_flash_partitions[] = {
 static void __init omap_sdp_init(void)
 {
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
-        omap_board_config = sdp_config;
-        omap_board_config_size = ARRAY_SIZE(sdp_config);
        zoom_peripherals_init();
        omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
                                  h8mbx00u0mer0em_sdrc_params);
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index ad8a7d94afcd..3669c120c7e8 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -28,23 +28,22 @@
 #include <linux/leds_pwm.h>
 #include <linux/platform_data/omap4-keypad.h>
-#include <mach/hardware.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
-#include <plat/omap4-keypad.h>
+#include "omap4-keypad.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-nokia-dsi.h>
 #include <video/omap-panel-picodlp.h>
 #include <linux/wl12xx.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
+#include "soc.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "control.h"
@@ -544,7 +543,14 @@ static struct twl6040_platform_data twl6040_data = {
        .codec          = &twl6040_codec,
        .vibra          = &twl6040_vibra,
        .audpwron_gpio  = 127,
-        .irq_base       = TWL6040_CODEC_IRQ_BASE,
+};
+static struct i2c_board_info __initdata sdp4430_i2c_1_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl6040", 0x4b),
+                .irq = 119 + OMAP44XX_IRQ_GIC_START,
+                .platform_data = &twl6040_data,
+        },
 };
 static struct twl4030_platform_data sdp4430_twldata = {
@@ -580,8 +586,8 @@ static int __init omap4_i2c_init(void)
                        TWL_COMMON_REGULATOR_CLK32KG |
                        TWL_COMMON_REGULATOR_V1V8 |
                        TWL_COMMON_REGULATOR_V2V1);
-        omap4_pmic_init("twl6030", &sdp4430_twldata,
+        omap4_pmic_init("twl6030", &sdp4430_twldata, sdp4430_i2c_1_boardinfo,
-                        &twl6040_data, OMAP44XX_IRQ_SYS_2N);
+                        ARRAY_SIZE(sdp4430_i2c_1_boardinfo));
        omap_register_i2c_bus(2, 400, NULL, 0);
        omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
                                ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
@@ -601,29 +607,6 @@ static void __init omap_sfh7741prox_init(void)
                        __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
 }
-static struct gpio sdp4430_hdmi_gpios[] = {
-        { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" },
-        { HDMI_GPIO_LS_OE,      GPIOF_OUT_INIT_HIGH,    "hdmi_gpio_ls_oe" },
-        { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" },
-};
-static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev)
-{
-        int status;
-        status = gpio_request_array(sdp4430_hdmi_gpios,
-                                    ARRAY_SIZE(sdp4430_hdmi_gpios));
-        if (status)
-                pr_err("%s: Cannot request HDMI GPIOs\n", __func__);
-        return status;
-}
-static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev)
-{
-        gpio_free_array(sdp4430_hdmi_gpios, ARRAY_SIZE(sdp4430_hdmi_gpios));
-}
 static struct nokia_dsi_panel_data dsi1_panel = {
                .name           = "taal",
                .reset_gpio     = 102,
@@ -644,29 +627,6 @@ static struct omap_dss_device sdp4430_lcd_device = {
        .phy.dsi                = {
                .module         = 0,
        },
-        .clocks = {
-                .dispc = {
-                        .channel = {
-                                /* Logic Clock = 172.8 MHz */
-                                .lck_div        = 1,
-                                /* Pixel Clock = 34.56 MHz */
-                                .pck_div        = 5,
-                                .lcd_clk_src    = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
-                        },
-                        .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
-                },
-                .dsi = {
-                        .regn           = 16,   /* Fint = 2.4 MHz */
-                        .regm           = 180,  /* DDR Clock = 216 MHz */
-                        .regm_dispc     = 5,    /* PLL1_CLK1 = 172.8 MHz */
-                        .regm_dsi       = 5,    /* PLL1_CLK2 = 172.8 MHz */
-                        .lp_clk_div     = 10,   /* LP Clock = 8.64 MHz */
-                        .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
-                },
-        },
        .channel                = OMAP_DSS_CHANNEL_LCD,
 };
@@ -691,33 +651,12 @@ static struct omap_dss_device sdp4430_lcd2_device = {
                .module         = 1,
        },
-        .clocks = {
-                .dispc = {
-                        .channel = {
-                                /* Logic Clock = 172.8 MHz */
-                                .lck_div        = 1,
-                                /* Pixel Clock = 34.56 MHz */
-                                .pck_div        = 5,
-                                .lcd_clk_src    = OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC,
-                        },
-                        .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
-                },
-                .dsi = {
-                        .regn           = 16,   /* Fint = 2.4 MHz */
-                        .regm           = 180,  /* DDR Clock = 216 MHz */
-                        .regm_dispc     = 5,    /* PLL1_CLK1 = 172.8 MHz */
-                        .regm_dsi       = 5,    /* PLL1_CLK2 = 172.8 MHz */
-                        .lp_clk_div     = 10,   /* LP Clock = 8.64 MHz */
-                        .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI,
-                },
-        },
        .channel                = OMAP_DSS_CHANNEL_LCD2,
 };
 static struct omap_dss_hdmi_data sdp4430_hdmi_data = {
+        .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD,
+        .ls_oe_gpio = HDMI_GPIO_LS_OE,
        .hpd_gpio = HDMI_GPIO_HPD,
 };
@@ -725,8 +664,6 @@ static struct omap_dss_device sdp4430_hdmi_device = {
        .name = "hdmi",
        .driver_name = "hdmi_panel",
        .type = OMAP_DISPLAY_TYPE_HDMI,
-        .platform_enable = sdp4430_panel_enable_hdmi,
-        .platform_disable = sdp4430_panel_disable_hdmi,
        .channel = OMAP_DSS_CHANNEL_DIGIT,
        .data = &sdp4430_hdmi_data,
 };
@@ -824,6 +761,32 @@ static struct omap_board_mux board_mux[] __initdata = {
        /* NIRQ2 for twl6040 */
        OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
                  OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
+        /* GPIO_127 for twl6040 */
+        OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
+        /* McPDM */
+        OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        /* DMIC */
+        OMAP4_MUX(ABE_DMIC_CLK1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP4_MUX(ABE_DMIC_DIN1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP4_MUX(ABE_DMIC_DIN2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP4_MUX(ABE_DMIC_DIN3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        /* McBSP1 */
+        OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
+                  OMAP_PULL_ENA),
+        OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        /* McBSP2 */
+        OMAP4_MUX(ABE_MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP4_MUX(ABE_MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
+                  OMAP_PULL_ENA),
+        OMAP4_MUX(ABE_MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
@@ -909,6 +872,7 @@ static void __init omap_4430sdp_init(void)
 MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
        /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
        .atag_offset    = 0x100,
+        .smp            = smp_ops(omap4_smp_ops),
        .reserve        = omap_reserve,
        .map_io         = omap4_map_io,
        .init_early     = omap4430_init_early,
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 92432c28673d..318feadb1d6e 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -21,12 +21,10 @@
 #include <linux/init.h>
 #include <linux/gpio.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
@@ -37,11 +35,6 @@
 #define GPIO_USB_POWER          35
 #define GPIO_USB_NRESET         38
-/* Board initialization */
-static struct omap_board_config_kernel am3517_crane_config[] __initdata = {
-};
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -67,9 +60,6 @@ static void __init am3517_crane_init(void)
        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
-        omap_board_config = am3517_crane_config;
-        omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
        /* Configure GPIO for EHCI port */
        if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {
                pr_err("Can not configure mux for GPIO_USB_NRESET %d\n",
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 18f601096ce1..e16289755f2e 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -25,14 +25,13 @@
 #include <linux/can/platform/ti_hecc.h>
 #include <linux/davinci_emac.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/gpio-omap.h>
-#include <mach/hardware.h>
+#include "am35xx.h"
-#include <mach/am35xx.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 #include <video/omapdss.h>
@@ -264,6 +263,16 @@ static __init void am3517_evm_musb_init(void)
        usb_musb_init(&musb_board_data);
 }
+static __init void am3517_evm_mcbsp1_init(void)
+{
+        u32 devconf0;
+        /* McBSP1 CLKR/FSR signal to be connected to CLKX/FSX pin */
+        devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        devconf0 |=  OMAP2_MCBSP1_CLKR_MASK | OMAP2_MCBSP1_FSR_MASK;
+        omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
+}
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
@@ -296,8 +305,7 @@ static struct resource am3517_hecc_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        {
-                .start  = INT_35XX_HECC0_IRQ,
+                .start  = 24 + OMAP_INTC_START,
-                .end    = INT_35XX_HECC0_IRQ,
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -324,9 +332,6 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
        platform_device_register(&am3517_hecc_device);
 }
-static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
-};
 static struct omap2_hsmmc_info mmc[] = {
        {
                .mmc            = 1,
@@ -346,8 +351,6 @@ static struct omap2_hsmmc_info mmc[] = {
 static void __init am3517_evm_init(void)
 {
-        omap_board_config = am3517_evm_config;
-        omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        am3517_evm_i2c_init();
@@ -373,6 +376,9 @@ static void __init am3517_evm_init(void)
        /* MUSB */
        am3517_evm_musb_init();
+        /* McBSP1 */
+        am3517_evm_mcbsp1_init();
        /* MMC init function */
        omap_hsmmc_init(mmc);
 }
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index e5fa46bfde2f..cea3abace815 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -29,13 +29,11 @@
 #include <linux/smc91x.h>
 #include <linux/gpio.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <plat/led.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
@@ -204,7 +202,7 @@ static inline void __init apollon_init_smc91x(void)
                return;
        }
-        clk_enable(gpmc_fck);
+        clk_prepare_enable(gpmc_fck);
        rate = clk_get_rate(gpmc_fck);
        eth_cs = APOLLON_ETH_CS;
@@ -248,7 +246,7 @@ static inline void __init apollon_init_smc91x(void)
                gpmc_cs_free(APOLLON_ETH_CS);
        }
 out:
-        clk_disable(gpmc_fck);
+        clk_disable_unprepare(gpmc_fck);
        clk_put(gpmc_fck);
 }
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 97d719047af3..376d26eb601c 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -23,6 +23,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <linux/i2c/at24.h>
 #include <linux/i2c/twl.h>
@@ -37,15 +38,14 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/board.h>
 #include "common.h"
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <mach/hardware.h>
@@ -64,7 +64,7 @@
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 #include <linux/smsc911x.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = {
        .id             = 0,
@@ -470,9 +470,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
 }
 static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
        .setup          = cm_t35_twl_gpio_setup,
 };
@@ -714,13 +711,8 @@ static inline void cm_t35_init_mux(void) {}
 static inline void cm_t3730_init_mux(void) {}
 #endif
-static struct omap_board_config_kernel cm_t35_config[] __initdata = {
-};
 static void __init cm_t3x_common_init(void)
 {
-        omap_board_config = cm_t35_config;
-        omap_board_config_size = ARRAY_SIZE(cm_t35_config);
        omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
        omap_serial_init();
        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
@@ -731,6 +723,7 @@ static void __init cm_t3x_common_init(void)
        cm_t35_init_ethernet();
        cm_t35_init_led();
        cm_t35_init_display();
+        omap_twl4030_audio_init("cm-t3x");
        usb_musb_init(NULL);
        cm_t35_init_usbh();
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index a33ad4641d9a..59c0a45f75b0 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -38,13 +38,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/gpmc.h>
-#include <mach/am35xx.h>
+#include "am35xx.h"
 #include "mux.h"
 #include "control.h"
@@ -90,8 +89,7 @@ static struct resource cm_t3517_hecc_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        {
-                .start  = INT_35XX_HECC0_IRQ,
+                .start  = 24 + OMAP_INTC_START,
-                .end    = INT_35XX_HECC0_IRQ,
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -249,9 +247,6 @@ static void __init cm_t3517_init_nand(void)
 static inline void cm_t3517_init_nand(void) {}
 #endif
-static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
-};
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        /* GPIO186 - Green LED */
@@ -285,8 +280,6 @@ static void __init cm_t3517_init(void)
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
-        omap_board_config = cm_t3517_config;
-        omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
        cm_t3517_init_leds();
        cm_t3517_init_nand();
        cm_t3517_init_rtc();
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 6567c1cd5572..1fd161e934c7 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -32,31 +32,27 @@
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
+#include "id.h"
-#include <mach/hardware.h>
-#include <mach/id.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
 #include <linux/dm9000.h>
 #include <linux/interrupt.h>
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
@@ -236,9 +232,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
 }
 static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .pulldowns      = BIT(1) | BIT(2) | BIT(6) | BIT(8) | BIT(13)
                                | BIT(15) | BIT(16) | BIT(17),
@@ -630,6 +623,7 @@ static void __init devkit8000_init(void)
        usbhs_init(&usbhs_bdata);
        omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions,
                             ARRAY_SIZE(devkit8000_nand_partitions));
+        omap_twl4030_audio_init("omap3beagle");
        /* Ensure SDRC pins are mux'd for self-refresh */
        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 53c39d239d6e..e642acf9cad0 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -16,13 +16,14 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
-#include <plat/irqs.h>
+#include <plat/cpu.h>
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
-#include <plat/onenand.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <plat/tc.h>
+#include "common.h"
 #include "board-flash.h"
 #define REG_FPGA_REV                    0x10
@@ -140,7 +141,6 @@ __init board_nand_init(struct mtd_partition *nand_parts,
        board_nand_data.devsize         = nand_type;
        board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
-        board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
        gpmc_nand_init(&board_nand_data);
 }
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
@@ -218,7 +218,7 @@ void __init board_flash_init(struct flash_partitions partition_info[],
                        if (onenandcs > GPMC_CS_NUM)
                                onenandcs = cs;
                        break;
-                };
+                }
                cs++;
        }
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 6f93a20536ea..601ecdfb1cf9 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -16,11 +16,9 @@
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
-#include <mach/hardware.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
-#include <plat/board.h>
 #include "common.h"
 #include "common-board-devices.h"
@@ -127,6 +125,7 @@ static const char *omap4_boards_compat[] __initdata = {
 DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
        .reserve        = omap_reserve,
+        .smp            = smp_ops(omap4_smp_ops),
        .map_io         = omap4_map_io,
        .init_early     = omap4430_init_early,
        .init_irq       = omap_gic_of_init,
@@ -147,6 +146,7 @@ static const char *omap5_boards_compat[] __initdata = {
 DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
        .reserve        = omap_reserve,
+        .smp            = smp_ops(omap4_smp_ops),
        .map_io         = omap5_map_io,
        .init_early     = omap5_init_early,
        .init_irq       = omap_gic_of_init,
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index ace20482e3e1..8d04bf851af4 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -27,20 +27,19 @@
 #include <linux/io.h>
 #include <linux/input/matrix_keypad.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/board.h>
-#include "common.h"
 #include <plat/menelaus.h>
 #include <plat/dma.h>
 #include <plat/gpmc.h>
+#include "debug-devices.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
+#include "common.h"
 #include "mux.h"
 #include "control.h"
@@ -266,9 +265,9 @@ static inline void __init h4_init_debug(void)
                return;
        }
-        clk_enable(gpmc_fck);
+        clk_prepare_enable(gpmc_fck);
        rate = clk_get_rate(gpmc_fck);
-        clk_disable(gpmc_fck);
+        clk_disable_unprepare(gpmc_fck);
        clk_put(gpmc_fck);
        if (is_gpmc_muxed())
@@ -312,7 +311,7 @@ static inline void __init h4_init_debug(void)
                gpmc_cs_free(eth_cs);
 out:
-        clk_disable(gpmc_fck);
+        clk_disable_unprepare(gpmc_fck);
        clk_put(gpmc_fck);
 }
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 28214483aaba..48d5e41dfbfa 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -29,13 +29,13 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/onenand.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 #include "mux.h"
 #include "hsmmc.h"
@@ -192,7 +192,7 @@ static void __init igep_flash_init(void) {}
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 #include <linux/smsc911x.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 static struct omap_smsc911x_platform_data smsc911x_cfg = {
        .cs             = IGEP2_SMSC911X_CS,
@@ -425,9 +425,6 @@ static int igep_twl_gpio_setup(struct device *dev,
 };
 static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .setup          = igep_twl_gpio_setup,
 };
@@ -628,6 +625,7 @@ static void __init igep_init(void)
        igep_flash_init();
        igep_leds_init();
+        omap_twl4030_audio_init("igep2");
        /*
         * WLAN-BT combo module from MuRata which has a Marvell WLAN
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index ef9e82977499..ee8c3cfb95b3 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -28,21 +28,17 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/mcspi.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <mach/board-zoom.h>
-#include <asm/delay.h>
 #include <plat/usb.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
@@ -275,9 +271,6 @@ static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio)
 }
 static struct twl4030_gpio_platform_data ldp_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
        .setup          = ldp_twl_gpio_setup,
 };
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 677357ff61ac..d95f727ca39a 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -20,19 +20,16 @@
 #include <linux/i2c.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/musb.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <sound/tlv320aic3x.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/menelaus.h>
-#include <mach/irqs.h>
-#include <plat/mcspi.h>
-#include <plat/onenand.h>
 #include <plat/mmc.h>
-#include <plat/serial.h>
 #include "mux.h"
@@ -553,8 +550,8 @@ static int n8x0_auto_sleep_regulators(void)
        ret = menelaus_set_regulator_sleep(1, val);
        if (ret < 0) {
-                printk(KERN_ERR "Could not set regulators to sleep on "
+                pr_err("Could not set regulators to sleep on menelaus: %u\n",
-                        "menelaus: %u\n", ret);
+                       ret);
                return ret;
        }
        return 0;
@@ -566,8 +563,7 @@ static int n8x0_auto_voltage_scale(void)
        ret = menelaus_set_vcore_hw(1400, 1050);
        if (ret < 0) {
-                printk(KERN_ERR "Could not set VCORE voltage on "
+                pr_err("Could not set VCORE voltage on menelaus: %u\n", ret);
-                        "menelaus: %u\n", ret);
                return ret;
        }
        return 0;
@@ -600,7 +596,7 @@ static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = {
 static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = {
        {
                I2C_BOARD_INFO("menelaus", 0x72),
-                .irq = INT_24XX_SYS_NIRQ,
+                .irq = 7 + OMAP_INTC_START,
                .platform_data = &n8x0_menelaus_platform_data,
        },
 };
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 6202fc76e490..388c431c745a 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -33,18 +33,16 @@
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
-#include <plat/board.h>
 #include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
@@ -297,9 +295,6 @@ static int beagle_twl_gpio_setup(struct device *dev,
 }
 static struct twl4030_gpio_platform_data beagle_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .pullups        = BIT(1),
        .pulldowns      = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
@@ -466,7 +461,7 @@ static void __init beagle_opp_init(void)
                mpu_dev = omap_device_get_by_hwmod_name("mpu");
                iva_dev = omap_device_get_by_hwmod_name("iva");
-                if (!mpu_dev || !iva_dev) {
+                if (IS_ERR(mpu_dev) || IS_ERR(iva_dev)) {
                        pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
                                __func__, mpu_dev, iva_dev);
                        return;
@@ -519,6 +514,7 @@ static void __init omap3_beagle_init(void)
        usbhs_init(&usbhs_bdata);
        omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
                             ARRAY_SIZE(omap3beagle_nand_partitions));
+        omap_twl4030_audio_init("omap3beagle");
        /* Ensure msecure is mux'd to be able to set the RTC. */
        omap_mux_init_signal("sys_drm_msecure", OMAP_PIN_OFF_OUTPUT_HIGH);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 0d362e9f9cb9..b9b776b6c954 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -32,6 +32,7 @@
 #include <linux/spi/ads7846.h>
 #include <linux/i2c/twl.h>
 #include <linux/usb/otg.h>
+#include <linux/usb/nop-usb-xceiv.h>
 #include <linux/smsc911x.h>
 #include <linux/wl12xx.h>
@@ -40,16 +41,14 @@
 #include <linux/mmc/host.h>
 #include <linux/export.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/board.h>
 #include <plat/usb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include "common.h"
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
@@ -75,13 +74,24 @@
 #define OMAP3EVM_GEN1_ETHR_GPIO_RST     64
 #define OMAP3EVM_GEN2_ETHR_GPIO_RST     7
+/*
+ * OMAP35x EVM revision
+ * Run time detection of EVM revision is done by reading Ethernet
+ * PHY ID -
+ *      GEN_1   = 0x01150000
+ *      GEN_2   = 0x92200000
+ */
+enum {
+        OMAP3EVM_BOARD_GEN_1 = 0,       /* EVM Rev between  A - D */
+        OMAP3EVM_BOARD_GEN_2,           /* EVM Rev >= Rev E */
+};
 static u8 omap3_evm_version;
-u8 get_omap3_evm_rev(void)
+static u8 get_omap3_evm_rev(void)
 {
        return omap3_evm_version;
 }
-EXPORT_SYMBOL(get_omap3_evm_rev);
 static void __init omap3_evm_get_revision(void)
 {
@@ -108,7 +118,7 @@ static void __init omap3_evm_get_revision(void)
 }
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 static struct omap_smsc911x_platform_data smsc911x_cfg = {
        .cs             = OMAP3EVM_SMSC911X_CS,
@@ -377,9 +387,6 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
 }
 static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .setup          = omap3evm_twl_gpio_setup,
 };
@@ -526,9 +533,6 @@ static int __init omap3_evm_i2c_init(void)
        return 0;
 }
-static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
-};
 static struct usbhs_omap_board_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -688,9 +692,6 @@ static void __init omap3_evm_init(void)
        obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
        omap3_mux_init(obm, OMAP_PACKAGE_CBB);
-        omap_board_config = omap3_evm_config;
-        omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
        omap_mux_init_gpio(63, OMAP_PIN_INPUT);
        omap_hsmmc_init(mmc);
@@ -737,6 +738,7 @@ static void __init omap3_evm_init(void)
        omap3evm_init_smsc911x();
        omap3_evm_display_init();
        omap3_evm_wl12xx_init();
+        omap_twl4030_audio_init("omap3evm");
 }
 MACHINE_START(OMAP3EVM, "OMAP3 EVM")
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index fca93d1afd43..7bd8253b5d1d 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -30,24 +30,21 @@
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include "gpmc-smsc911x.h"
+#include <plat/gpmc.h>
+#include <plat/sdrc.h>
+#include <plat/usb.h>
+#include "common.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "control.h"
 #include "common-board-devices.h"
-#include <plat/mux.h>
-#include <plat/board.h>
-#include "common.h"
-#include <plat/gpmc-smsc911x.h>
-#include <plat/gpmc.h>
-#include <plat/sdrc.h>
-#include <plat/usb.h>
 #define OMAP3LOGIC_SMSC911X_CS                  1
 #define OMAP3530_LV_SOM_MMC_GPIO_CD             110
@@ -78,9 +75,6 @@ static struct regulator_init_data omap3logic_vmmc1 = {
 };
 static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .pullups        = BIT(1),
        .pulldowns      = BIT(2)  | BIT(6)  | BIT(7)  | BIT(8)
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 57aebee44fd0..00a1f4ae6e44 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -35,18 +35,16 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
 #include <linux/regulator/fixed.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/board.h>
 #include "common.h"
-#include <mach/hardware.h>
-#include <plat/mcspi.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
@@ -321,9 +319,6 @@ static int omap3pandora_twl_gpio_setup(struct device *dev,
 }
 static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
        .setup          = omap3pandora_twl_gpio_setup,
 };
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index b318f5602e36..731235eb319e 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -28,28 +28,26 @@
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
+#include <linux/interrupt.h>
+#include <linux/smsc911x.h>
+#include <linux/i2c/at24.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/spi/spi.h>
-#include <linux/interrupt.h>
-#include <linux/smsc911x.h>
-#include <linux/i2c/at24.h>
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mux.h"
@@ -57,7 +55,7 @@
 #include "common-board-devices.h"
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 #define OMAP3STALKER_ETHR_START 0x2c000000
 #define OMAP3STALKER_ETHR_SIZE  1024
@@ -279,9 +277,6 @@ omap3stalker_twl_gpio_setup(struct device *dev,
 }
 static struct twl4030_gpio_platform_data omap3stalker_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .setup          = omap3stalker_twl_gpio_setup,
 };
@@ -362,9 +357,6 @@ static int __init omap3_stalker_i2c_init(void)
 #define OMAP3_STALKER_TS_GPIO   175
-static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
-};
 static struct platform_device *omap3_stalker_devices[] __initdata = {
        &keys_gpio,
 };
@@ -399,8 +391,6 @@ static void __init omap3_stalker_init(void)
 {
        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
        omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
-        omap_board_config = omap3_stalker_config;
-        omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
        omap_mux_init_gpio(23, OMAP_PIN_INPUT);
        omap_hsmmc_init(mmc);
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 485d14d6a8cd..944ffc436577 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -29,7 +29,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
@@ -37,17 +37,15 @@
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 #include <asm/system_info.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 #include "mux.h"
@@ -139,9 +137,6 @@ static int touchbook_twl_gpio_setup(struct device *dev,
 }
 static struct twl4030_gpio_platform_data touchbook_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .pullups        = BIT(1),
        .pulldowns      = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 70f6d1d25463..bfcd397e233c 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -32,19 +32,18 @@
 #include <linux/wl12xx.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
-#include <mach/hardware.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <video/omapdss.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
 #include <video/omap-panel-tfp410.h>
+#include "soc.h"
 #include "hsmmc.h"
 #include "control.h"
 #include "mux.h"
@@ -172,7 +171,7 @@ static void __init omap4_ehci_init(void)
                return;
        }
        clk_set_rate(phy_ref_clk, 19200000);
-        clk_enable(phy_ref_clk);
+        clk_prepare_enable(phy_ref_clk);
        /* disable the power to the usb hub prior to init and reset phy+hub */
        ret = gpio_request_array(panda_ehci_gpios,
@@ -248,8 +247,7 @@ static struct platform_device omap_vwlan_device = {
 };
 static struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
-        /* PANDA ref clock is 38.4 MHz */
+        .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
-        .board_ref_clock = 2,
 };
 static struct twl6040_codec_data twl6040_codec = {
@@ -263,7 +261,14 @@ static struct twl6040_codec_data twl6040_codec = {
 static struct twl6040_platform_data twl6040_data = {
        .codec          = &twl6040_codec,
        .audpwron_gpio  = 127,
-        .irq_base       = TWL6040_CODEC_IRQ_BASE,
+};
+static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl6040", 0x4b),
+                .irq = 119 + OMAP44XX_IRQ_GIC_START,
+                .platform_data = &twl6040_data,
+        },
 };
 /* Panda board uses the common PMIC configuration */
@@ -293,8 +298,8 @@ static int __init omap4_panda_i2c_init(void)
                        TWL_COMMON_REGULATOR_CLK32KG |
                        TWL_COMMON_REGULATOR_V1V8 |
                        TWL_COMMON_REGULATOR_V2V1);
-        omap4_pmic_init("twl6030", &omap4_panda_twldata,
+        omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo,
-                        &twl6040_data, OMAP44XX_IRQ_SYS_2N);
+                        ARRAY_SIZE(panda_i2c_1_boardinfo));
        omap_register_i2c_bus(2, 400, NULL, 0);
        /*
         * Bus 3 is attached to the DVI port where devices like the pico DLP
@@ -382,6 +387,21 @@ static struct omap_board_mux board_mux[] __initdata = {
        /* NIRQ2 for twl6040 */
        OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
                  OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
+        /* GPIO_127 for twl6040 */
+        OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
+        /* McPDM */
+        OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        /* McBSP1 */
+        OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
+                  OMAP_PULL_ENA),
+        OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
@@ -408,30 +428,9 @@ static struct omap_dss_device omap4_panda_dvi_device = {
        .channel                = OMAP_DSS_CHANNEL_LCD2,
 };
-static struct gpio panda_hdmi_gpios[] = {
-        { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" },
-        { HDMI_GPIO_LS_OE,      GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
-        { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" },
-};
-static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev)
-{
-        int status;
-        status = gpio_request_array(panda_hdmi_gpios,
-                                    ARRAY_SIZE(panda_hdmi_gpios));
-        if (status)
-                pr_err("Cannot request HDMI GPIOs\n");
-        return status;
-}
-static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev)
-{
-        gpio_free_array(panda_hdmi_gpios, ARRAY_SIZE(panda_hdmi_gpios));
-}
 static struct omap_dss_hdmi_data omap4_panda_hdmi_data = {
+        .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD,
+        .ls_oe_gpio = HDMI_GPIO_LS_OE,
        .hpd_gpio = HDMI_GPIO_HPD,
 };
@@ -439,8 +438,6 @@ static struct omap_dss_device  omap4_panda_hdmi_device = {
        .name = "hdmi",
        .driver_name = "hdmi_panel",
        .type = OMAP_DISPLAY_TYPE_HDMI,
-        .platform_enable = omap4_panda_panel_enable_hdmi,
-        .platform_disable = omap4_panda_panel_disable_hdmi,
        .channel = OMAP_DSS_CHANNEL_DIGIT,
        .data = &omap4_panda_hdmi_data,
 };
@@ -518,6 +515,7 @@ static void __init omap4_panda_init(void)
 MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
        /* Maintainer: David Anders - Texas Instruments Inc */
        .atag_offset    = 0x100,
+        .smp            = smp_ops(omap4_smp_ops),
        .reserve        = omap_reserve,
        .map_io         = omap4_map_io,
        .init_early     = omap4430_init_early,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 779734d8ba37..b700685762b5 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -37,21 +37,19 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
-#include <plat/board.h>
 #include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 #include <plat/gpmc.h>
-#include <mach/hardware.h>
-#include <plat/nand.h>
-#include <plat/mcspi.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 #include "mux.h"
@@ -116,7 +114,7 @@ static inline void __init overo_ads7846_init(void) { return; }
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 #include <linux/smsc911x.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 static struct omap_smsc911x_platform_data smsc911x_cfg = {
        .id             = 0,
@@ -399,9 +397,6 @@ static int overo_twl_gpio_setup(struct device *dev,
 }
 static struct twl4030_gpio_platform_data overo_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .setup          = overo_twl_gpio_setup,
 };
@@ -509,6 +504,7 @@ static void __init overo_init(void)
        overo_display_init();
        overo_init_led();
        overo_init_keys();
+        omap_twl4030_audio_init("overo");
        /* Ensure SDRC pins are mux'd for self-refresh */
        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
@@ -522,8 +518,7 @@ static void __init overo_init(void)
                udelay(10);
                gpio_set_value(OVERO_GPIO_W2W_NRESET, 1);
        } else {
-                printk(KERN_ERR "could not obtain gpio for "
+                pr_err("could not obtain gpio for OVERO_GPIO_W2W_NRESET\n");
-                                        "OVERO_GPIO_W2W_NRESET\n");
        }
        ret = gpio_request_array(overo_bt_gpios, ARRAY_SIZE(overo_bt_gpios));
@@ -542,8 +537,7 @@ static void __init overo_init(void)
        if (ret == 0)
                gpio_export(OVERO_GPIO_USBH_CPEN, 0);
        else
-                printk(KERN_ERR "could not obtain gpio for "
+                pr_err("could not obtain gpio for OVERO_GPIO_USBH_CPEN\n");
-                                        "OVERO_GPIO_USBH_CPEN\n");
 }
 MACHINE_START(OVERO, "Gumstix Overo")
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 0ad1bb3bdb98..45997bfbcbd2 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -17,6 +17,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/consumer.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -26,7 +27,7 @@
 #include <plat/usb.h>
 #include <plat/gpmc.h>
 #include "common.h"
-#include <plat/onenand.h>
+#include <plat/serial.h>
 #include "mux.h"
 #include "hsmmc.h"
@@ -72,9 +73,6 @@ static struct platform_device *rm680_peripherals_devices[] __initdata = {
 /* TWL */
 static struct twl4030_gpio_platform_data rm680_gpio_data = {
-        .gpio_base              = OMAP_MAX_GPIO_LINES,
-        .irq_base               = TWL4030_GPIO_IRQ_BASE,
-        .irq_end                = TWL4030_GPIO_IRQ_END,
        .pullups                = BIT(0),
        .pulldowns              = BIT(1) | BIT(2) | BIT(8) | BIT(15),
 };
@@ -87,7 +85,7 @@ static struct twl4030_platform_data rm680_twl_data = {
 static void __init rm680_i2c_init(void)
 {
        omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0);
-        omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data);
+        omap_pmic_init(1, 2900, "twl5031", 7 + OMAP_INTC_START, &rm680_twl_data);
        omap_register_i2c_bus(2, 400, NULL, 0);
        omap_register_i2c_bus(3, 400, NULL, 0);
 }
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index df2534de3361..020e03c95bfe 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -25,17 +25,18 @@
 #include <linux/gpio_keys.h>
 #include <linux/mmc/host.h>
 #include <linux/power/isp1704_charger.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <asm/system_info.h>
-#include <plat/mcspi.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
-#include <plat/onenand.h>
+#include <plat/omap-pm.h>
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
-#include <mach/board-rx51.h>
+#include "board-rx51.h"
 #include <sound/tlv320aic3x.h>
 #include <sound/tpa6130a2-plat.h>
@@ -46,6 +47,10 @@
 #include <../drivers/staging/iio/light/tsl2563.h>
 #include <linux/lis3lv02d.h>
+#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
+#include <media/ir-rx51.h>
+#endif
 #include "mux.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
@@ -743,7 +748,7 @@ static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module =
        .subdev_board_info = &rx51_si4713_board_info,
 };
-static struct platform_device rx51_si4713_dev = {
+static struct platform_device rx51_si4713_dev __initdata_or_module = {
        .name   = "radio-si4713",
        .id     = -1,
        .dev    = {
@@ -774,9 +779,6 @@ static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
 }
 static struct twl4030_gpio_platform_data rx51_gpio_data = {
-        .gpio_base              = OMAP_MAX_GPIO_LINES,
-        .irq_base               = TWL4030_GPIO_IRQ_BASE,
-        .irq_end                = TWL4030_GPIO_IRQ_END,
        .pulldowns              = BIT(0) | BIT(1) | BIT(2) | BIT(3)
                                | BIT(4) | BIT(5)
                                | BIT(8) | BIT(9) | BIT(10) | BIT(11)
@@ -1051,7 +1053,7 @@ static int __init rx51_i2c_init(void)
        rx51_twldata.vdac->constraints.apply_uV = true;
        rx51_twldata.vdac->constraints.name = "VDAC";
-        omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
+        omap_pmic_init(1, 2200, "twl5030", 7 + OMAP_INTC_START, &rx51_twldata);
        omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
                              ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
 #if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
@@ -1220,6 +1222,30 @@ static void __init rx51_init_tsc2005(void)
                                gpio_to_irq(RX51_TSC2005_IRQ_GPIO);
 }
+#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
+static struct lirc_rx51_platform_data rx51_lirc_data = {
+        .set_max_mpu_wakeup_lat = omap_pm_set_max_mpu_wakeup_lat,
+        .pwm_timer = 9, /* Use GPT 9 for CIR */
+};
+static struct platform_device rx51_lirc_device = {
+        .name           = "lirc_rx51",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &rx51_lirc_data,
+        },
+};
+static void __init rx51_init_lirc(void)
+{
+        platform_device_register(&rx51_lirc_device);
+}
+#else
+static void __init rx51_init_lirc(void)
+{
+}
+#endif
 void __init rx51_peripherals_init(void)
 {
        rx51_i2c_init();
@@ -1230,6 +1256,7 @@ void __init rx51_peripherals_init(void)
        rx51_init_wl1251();
        rx51_init_tsc2005();
        rx51_init_si4713();
+        rx51_init_lirc();
        spi_register_board_info(rx51_peripherals_spi_board_info,
                                ARRAY_SIZE(rx51_peripherals_spi_board_info));
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index 2c1289bd5e6a..c22e111bcd00 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -17,9 +17,9 @@
 #include <asm/mach-types.h>
 #include <video/omapdss.h>
 #include <plat/vram.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <mach/board-rx51.h>
+#include "board-rx51.h"
 #include "mux.h"
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 345dd931f76f..7bbb05d9689b 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -17,14 +17,12 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/mcspi.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
diff --git a/arch/arm/mach-omap2/include/mach/board-rx51.h b/arch/arm/mach-omap2/board-rx51.h
index b76f49e7eed5..b76f49e7eed5 100644
--- a/arch/arm/mach-omap2/include/mach/board-rx51.h
+++ b/arch/arm/mach-omap2/board-rx51.h
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index d4c8392cadb6..c4f8833b4c3c 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -15,13 +15,10 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/irqs.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
@@ -32,15 +29,10 @@ static struct omap_musb_board_data musb_board_data = {
        .power          = 500,
 };
-static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = {
-};
 static void __init ti81xx_evm_init(void)
 {
        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
-        omap_board_config = ti81xx_evm_config;
-        omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config);
        usb_musb_init(&musb_board_data);
 }
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index f64f44173061..afb2278a29f6 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -18,10 +18,13 @@
 #include <linux/regulator/machine.h>
 #include <plat/gpmc.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 #include <mach/board-zoom.h>
+#include "soc.h"
+#include "common.h"
 #define ZOOM_SMSC911X_CS        7
 #define ZOOM_SMSC911X_GPIO      158
 #define ZOOM_QUADUART_CS        3
@@ -81,8 +84,7 @@ static inline void __init zoom_init_quaduart(void)
        quart_cs = ZOOM_QUADUART_CS;
        if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) {
-                printk(KERN_ERR "Failed to request GPMC mem"
+                pr_err("Failed to request GPMC mem for Quad UART(TL16CP754C)\n");
-                                "for Quad UART(TL16CP754C)\n");
                return;
        }
@@ -104,8 +106,8 @@ static inline int omap_zoom_debugboard_detect(void)
        if (gpio_request_one(debug_board_detect, GPIOF_IN,
                             "Zoom debug board detect") < 0) {
-                printk(KERN_ERR "Failed to request GPIO%d for Zoom debug"
+                pr_err("Failed to request GPIO%d for Zoom debug board detect\n",
-                "board detect\n", debug_board_detect);
+                       debug_board_detect);
                return 0;
        }
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 28187f134fff..b940ab2259fb 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -14,10 +14,12 @@
 #include <linux/gpio.h>
 #include <linux/i2c/twl.h>
 #include <linux/spi/spi.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
 #include <mach/board-zoom.h>
+#include "common.h"
 #define LCD_PANEL_RESET_GPIO_PROD       96
 #define LCD_PANEL_RESET_GPIO_PILOT      55
 #define LCD_PANEL_QVGA_GPIO             56
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index b797cb279618..c166fe1fdff9 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -19,6 +19,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/wl12xx.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -34,6 +35,7 @@
 #include "common-board-devices.h"
 #define OMAP_ZOOM_WLAN_PMENA_GPIO       (101)
+#define ZOOM2_HEADSET_EXTMUTE_GPIO      (153)
 #define OMAP_ZOOM_WLAN_IRQ_GPIO         (162)
 #define LCD_PANEL_ENABLE_GPIO           (7 + OMAP_MAX_GPIO_LINES)
@@ -193,8 +195,7 @@ static struct platform_device omap_vwlan_device = {
 };
 static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = {
-        /* ZOOM ref clock is 26 MHz */
+        .board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */
-        .board_ref_clock = 1,
 };
 static struct omap2_hsmmc_info mmc[] = {
@@ -244,16 +245,7 @@ static int zoom_twl_gpio_setup(struct device *dev,
        return ret;
 }
-/* EXTMUTE callback function */
-static void zoom2_set_hs_extmute(int mute)
-{
-        gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute);
-}
 static struct twl4030_gpio_platform_data zoom_gpio_data = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
        .setup          = zoom_twl_gpio_setup,
 };
@@ -279,9 +271,9 @@ static int __init omap_i2c_init(void)
                codec_data->ramp_delay_value = 3;       /* 161 ms */
                codec_data->hs_extmute = 1;
-                codec_data->set_hs_extmute = zoom2_set_hs_extmute;
+                codec_data->hs_extmute_gpio = ZOOM2_HEADSET_EXTMUTE_GPIO;
        }
-        omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
+        omap_pmic_init(1, 2400, "twl5030", 7 + OMAP_INTC_START, &zoom_twldata);
        omap_register_i2c_bus(2, 400, NULL, 0);
        omap_register_i2c_bus(3, 400, NULL, 0);
        return 0;
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 4e7e56142e6f..4994438e1f46 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -22,7 +22,6 @@
 #include <asm/mach/arch.h>
 #include "common.h"
-#include <plat/board.h>
 #include <plat/usb.h>
 #include <mach/board-zoom.h>
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index b19a1f7234ae..c2d15212d64d 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
        omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
        omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
-                             OMAP24XX_CM_IDLEST_VAL, clk->name);
+                             OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
        /*
         * REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 3d9d746b221a..3524f0e7b6d5 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -33,11 +33,11 @@
 #include <linux/cpufreq.h>
 #include <linux/slab.h>
-#include <plat/cpu.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/sdrc.h>
+#include "soc.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
@@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
 long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 {
        const struct prcm_config *ptr;
-        long highest_rate;
+        long highest_rate, sys_clk_rate;
        highest_rate = -EINVAL;
+        sys_clk_rate = __clk_get_rate(sclk);
        for (ptr = rate_table; ptr->mpu_speed; ptr++) {
                if (!(ptr->flags & cpu_mask))
                        continue;
-                if (ptr->xtal_speed != sclk->rate)
+                if (ptr->xtal_speed != sys_clk_rate)
                        continue;
                highest_rate = ptr->mpu_speed;
@@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
        const struct prcm_config *prcm;
        unsigned long found_speed = 0;
        unsigned long flags;
+        long sys_clk_rate;
+        sys_clk_rate = __clk_get_rate(sclk);
        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
                if (!(prcm->flags & cpu_mask))
                        continue;
-                if (prcm->xtal_speed != sclk->rate)
+                if (prcm->xtal_speed != sys_clk_rate)
                        continue;
                if (prcm->mpu_speed <= rate) {
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index d6e34dd9e7e7..7c6da2f731dc 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
        struct omap_sdrc_params *sdrc_cs0;
        struct omap_sdrc_params *sdrc_cs1;
        int ret;
+        unsigned long clkrate;
        if (!clk || !rate)
                return -EINVAL;
@@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
        if (validrate != rate)
                return -EINVAL;
-        sdrcrate = sdrc_ick_p->rate;
+        sdrcrate = __clk_get_rate(sdrc_ick_p);
-        if (rate > clk->rate)
+        clkrate = __clk_get_rate(clk);
-                sdrcrate <<= ((rate / clk->rate) >> 1);
+        if (rate > clkrate)
+                sdrcrate <<= ((rate / clkrate) >> 1);
        else
-                sdrcrate >>= ((clk->rate / rate) >> 1);
+                sdrcrate >>= ((clkrate / rate) >> 1);
        ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
        if (ret)
@@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
        /*
         * XXX This only needs to be done when the CPU frequency changes
         */
-        _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+        _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
        c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
        c += 1;  /* for safety */
        c *= SDRC_MPURATE_LOOPS;
@@ -90,28 +92,26 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
        if (c == 0)
                c = 1;
-        pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
+        pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
-                 validrate);
+                 clkrate, validrate);
-        pr_debug("clock: SDRC CS0 timing params used:"
+        pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
-                 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
                 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
        if (sdrc_cs1)
-                pr_debug("clock: SDRC CS1 timing params used: "
+                pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
-                 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+                         sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
-                 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+                         sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
-                 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
        if (sdrc_cs1)
                omap3_configure_core_dpll(
-                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  new_div, unlock_dll, c, rate > clkrate,
                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                                  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
                                  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
        else
                omap3_configure_core_dpll(
-                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  new_div, unlock_dll, c, rate > clkrate,
                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                                  0, 0, 0, 0);
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 04d551b1f7f7..3ff22114d702 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -71,8 +71,8 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
        if (!clks->parent) {
                /* This indicates a data problem */
-                WARN(1, "clock: Could not find parent clock %s in clksel array "
+                WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
-                     "of clock %s\n", src_clk->name, clk->name);
+                     __clk_get_name(clk), __clk_get_name(src_clk));
                return NULL;
        }
@@ -126,8 +126,9 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
        if (max_div == 0) {
                /* This indicates an error in the clksel data */
-                WARN(1, "clock: Could not find divisor for clock %s parent %s"
+                WARN(1, "clock: %s: could not find divisor for parent %s\n",
-                     "\n", clk->name, src_clk->parent->name);
+                     __clk_get_name(clk),
+                     __clk_get_name(__clk_get_parent(src_clk)));
                return 0;
        }
@@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 {
        const struct clksel *clks;
        const struct clksel_rate *clkr;
+        struct clk *parent;
-        clks = _get_clksel_by_parent(clk, clk->parent);
+        parent = __clk_get_parent(clk);
+        clks = _get_clksel_by_parent(clk, parent);
        if (!clks)
                return 0;
@@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
        if (!clkr->div) {
                /* This indicates a data error */
-                WARN(1, "clock: Could not find fieldval %d for clock %s parent "
+                WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
-                     "%s\n", field_val, clk->name, clk->parent->name);
+                     __clk_get_name(clk), field_val, __clk_get_name(parent));
                return 0;
        }
@@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
 {
        const struct clksel *clks;
        const struct clksel_rate *clkr;
+        struct clk *parent;
        /* should never happen */
        WARN_ON(div == 0);
-        clks = _get_clksel_by_parent(clk, clk->parent);
+        parent = __clk_get_parent(clk);
+        clks = _get_clksel_by_parent(clk, parent);
        if (!clks)
                return ~0;
@@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
        }
        if (!clkr->div) {
-                pr_err("clock: Could not find divisor %d for clock %s parent "
+                pr_err("clock: %s: could not find divisor %d for parent %s\n",
-                       "%s\n", div, clk->name, clk->parent->name);
+                       __clk_get_name(clk), div, __clk_get_name(parent));
                return ~0;
        }
@@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
        const struct clksel *clks;
        const struct clksel_rate *clkr;
        u32 last_div = 0;
+        struct clk *parent;
+        unsigned long parent_rate;
+        const char *clk_name;
+        parent = __clk_get_parent(clk);
+        parent_rate = __clk_get_rate(parent);
+        clk_name = __clk_get_name(clk);
        if (!clk->clksel || !clk->clksel_mask)
                return ~0;
        pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
-                 clk->name, target_rate);
+                 clk_name, target_rate);
        *new_div = 1;
-        clks = _get_clksel_by_parent(clk, clk->parent);
+        clks = _get_clksel_by_parent(clk, parent);
        if (!clks)
                return ~0;
@@ -300,30 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
                /* Sanity check */
                if (clkr->div <= last_div)
-                        pr_err("clock: clksel_rate table not sorted "
+                        pr_err("clock: %s: clksel_rate table not sorted\n",
-                               "for clock %s", clk->name);
+                               clk_name);
                last_div = clkr->div;
-                test_rate = clk->parent->rate / clkr->div;
+                test_rate = parent_rate / clkr->div;
                if (test_rate <= target_rate)
                        break; /* found it */
        }
        if (!clkr->div) {
-                pr_err("clock: Could not find divisor for target "
+                pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
-                       "rate %ld for clock %s parent %s\n", target_rate,
+                       clk_name, target_rate, __clk_get_name(parent));
-                       clk->name, clk->parent->name);
                return ~0;
        }
        *new_div = clkr->div;
        pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
-                 (clk->parent->rate / clkr->div));
+                 (parent_rate / clkr->div));
-        return clk->parent->rate / clkr->div;
+        return parent_rate / clkr->div;
 }
 /*
@@ -345,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk)
        const struct clksel *clks;
        const struct clksel_rate *clkr;
        u32 r, found = 0;
+        struct clk *parent;
+        const char *clk_name;
        if (!clk->clksel || !clk->clksel_mask)
                return;
+        parent = __clk_get_parent(clk);
+        clk_name = __clk_get_name(clk);
        r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
        r >>= __ffs(clk->clksel_mask);
@@ -358,14 +374,15 @@ void omap2_init_clksel_parent(struct clk *clk)
                                continue;
                        if (clkr->val == r) {
-                                if (clk->parent != clks->parent) {
+                                if (parent != clks->parent) {
-                                        pr_debug("clock: inited %s parent "
+                                        pr_debug("clock: %s: inited parent to %s (was %s)\n",
-                                                 "to %s (was %s)\n",
+                                                 clk_name,
-                                                 clk->name, clks->parent->name,
+                                                 __clk_get_name(clks->parent),
-                                                 ((clk->parent) ?
+                                                 ((parent) ?
-                                                  clk->parent->name : "NULL"));
+                                                  __clk_get_name(parent) :
+                                                 "NULL"));
                                        clk_reparent(clk, clks->parent);
-                                };
+                                }
                                found = 1;
                        }
                }
@@ -373,7 +390,7 @@ void omap2_init_clksel_parent(struct clk *clk)
        /* This indicates a data error */
        WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
-             clk->name, r);
+             clk_name, r);
        return;
 }
@@ -391,15 +408,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
 {
        unsigned long rate;
        u32 div = 0;
+        struct clk *parent;
        div = _read_divisor(clk);
        if (div == 0)
-                return clk->rate;
+                return __clk_get_rate(clk);
-        rate = clk->parent->rate / div;
+        parent = __clk_get_parent(clk);
+        rate = __clk_get_rate(parent) / div;
-        pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
+        pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
-                 rate, div);
+                 __clk_get_name(clk), rate, div);
        return rate;
 }
@@ -454,9 +473,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
        _write_clksel_reg(clk, field_val);
-        clk->rate = clk->parent->rate / new_div;
+        clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
-        pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
+        pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
+                 __clk_get_rate(clk));
        return 0;
 }
@@ -498,13 +518,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
        clk_reparent(clk, new_parent);
        /* CLKSEL clocks follow their parents' rates, divided by a divisor */
-        clk->rate = new_parent->rate;
+        clk->rate = __clk_get_rate(new_parent);
        if (parent_div > 0)
-                clk->rate /= parent_div;
+                __clk_get_rate(clk) /= parent_div;
        pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
-                 clk->name, clk->parent->name, clk->rate);
+                 __clk_get_name(clk),
+                 __clk_get_name(__clk_get_parent(clk)),
+                 __clk_get_rate(clk));
        return 0;
 }
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index cd7fd0f91149..80411142f482 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -22,8 +22,8 @@
 #include <asm/div64.h>
 #include <plat/clock.h>
-#include <plat/cpu.h>
+#include "soc.h"
 #include "clock.h"
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
@@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
        dd = clk->dpll_data;
        /* DPLL divider must result in a valid jitter correction val */
-        fint = clk->parent->rate / n;
+        fint = __clk_get_rate(__clk_get_parent(clk)) / n;
        if (cpu_is_omap24xx()) {
                /* Should not be called for OMAP2, so warn if it is called */
@@ -105,13 +105,13 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
        }
        if (fint < fint_min) {
-                pr_debug("rejecting n=%d due to Fint failure, "
+                pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
-                         "lowering max_divider\n", n);
+                         n);
                dd->max_divider = n;
                ret = DPLL_FINT_UNDERFLOW;
        } else if (fint > fint_max) {
-                pr_debug("rejecting n=%d due to Fint failure, "
+                pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
-                         "boosting min_divider\n", n);
+                         n);
                dd->min_divider = n;
                ret = DPLL_FINT_INVALID;
        } else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
@@ -211,7 +211,7 @@ void omap2_init_dpll_parent(struct clk *clk)
                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
                        clk_reparent(clk, dd->clk_bypass);
-        } else if (cpu_is_omap44xx()) {
+        } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
@@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
        if (cpu_is_omap24xx()) {
                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
-                        return dd->clk_bypass->rate;
+                        return __clk_get_rate(dd->clk_bypass);
        } else if (cpu_is_omap34xx()) {
                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
-                        return dd->clk_bypass->rate;
+                        return __clk_get_rate(dd->clk_bypass);
-        } else if (cpu_is_omap44xx()) {
+        } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
-                        return dd->clk_bypass->rate;
+                        return __clk_get_rate(dd->clk_bypass);
        }
        v = __raw_readl(dd->mult_div1_reg);
@@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
        dpll_div = v & dd->div1_mask;
        dpll_div >>= __ffs(dd->div1_mask);
-        dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
+        dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
        do_div(dpll_clk, dpll_div + 1);
        return dpll_clk;
@@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
        unsigned long scaled_rt_rp;
        unsigned long new_rate = 0;
        struct dpll_data *dd;
+        unsigned long ref_rate;
+        const char *clk_name;
        if (!clk || !clk->dpll_data)
                return ~0;
        dd = clk->dpll_data;
+        ref_rate = __clk_get_rate(dd->clk_ref);
+        clk_name = __clk_get_name(clk);
        pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
-                 clk->name, target_rate);
+                 clk_name, target_rate);
-        scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
+        scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
        scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
        dd->last_rounded_rate = 0;
@@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
                        break;
                r = _dpll_test_mult(&m, n, &new_rate, target_rate,
-                                    dd->clk_ref->rate);
+                                    ref_rate);
                /* m can't be set low enough for this n - try with a larger n */
                if (r == DPLL_MULT_UNDERFLOW)
                        continue;
                pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
-                         clk->name, m, n, new_rate);
+                         clk_name, m, n, new_rate);
                if (target_rate == new_rate) {
                        dd->last_rounded_m = m;
@@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
        }
        if (target_rate != new_rate) {
-                pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
+                pr_debug("clock: %s: cannot round to rate %ld\n",
-                         target_rate);
+                         clk_name, target_rate);
                return ~0;
        }
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ea3f565ba1a4..961ac8f7e13d 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -22,14 +22,16 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
-#include <trace/events/power.h>
 #include <asm/cpu.h>
 #include <plat/clock.h>
-#include "clockdomain.h"
-#include <plat/cpu.h>
 #include <plat/prcm.h>
+#include <trace/events/power.h>
+#include "soc.h"
+#include "clockdomain.h"
 #include "clock.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
@@ -76,7 +78,7 @@ static void _omap2_module_wait_ready(struct clk *clk)
        clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
        omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
-                             clk->name);
+                             __clk_get_name(clk));
 }
 /* Public functions */
@@ -92,18 +94,21 @@ static void _omap2_module_wait_ready(struct clk *clk)
 void omap2_init_clk_clkdm(struct clk *clk)
 {
        struct clockdomain *clkdm;
+        const char *clk_name;
        if (!clk->clkdm_name)
                return;
+        clk_name = __clk_get_name(clk);
        clkdm = clkdm_lookup(clk->clkdm_name);
        if (clkdm) {
                pr_debug("clock: associated clk %s to clkdm %s\n",
-                         clk->name, clk->clkdm_name);
+                         clk_name, clk->clkdm_name);
                clk->clkdm = clkdm;
        } else {
-                pr_debug("clock: could not associate clk %s to "
+                pr_debug("clock: could not associate clk %s to clkdm %s\n",
-                         "clkdm %s\n", clk->name, clk->clkdm_name);
+                         clk_name, clk->clkdm_name);
        }
 }
@@ -226,8 +231,7 @@ void omap2_dflt_clk_disable(struct clk *clk)
                 * 'Independent' here refers to a clock which is not
                 * controlled by its parent.
                 */
-                printk(KERN_ERR "clock: clk_disable called on independent "
+                pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name);
-                       "clock %s which has no enable_reg\n", clk->name);
                return;
        }
@@ -270,8 +274,7 @@ const struct clkops clkops_omap2_dflt = {
 void omap2_clk_disable(struct clk *clk)
 {
        if (clk->usecount == 0) {
-                WARN(1, "clock: %s: omap2_clk_disable() called, but usecount "
+                WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name);
-                     "already 0?", clk->name);
                return;
        }
@@ -332,8 +335,8 @@ int omap2_clk_enable(struct clk *clk)
        if (clkdm_control && clk->clkdm) {
                ret = clkdm_clk_enable(clk->clkdm, clk);
                if (ret) {
-                        WARN(1, "clock: %s: could not enable clockdomain %s: "
+                        WARN(1, "clock: %s: could not enable clockdomain %s: %d\n",
-                             "%d\n", clk->name, clk->clkdm->name, ret);
+                             clk->name, clk->clkdm->name, ret);
                        goto oce_err2;
                }
        }
@@ -501,10 +504,8 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
        hfclkin_rate = clk_get_rate(hfclkin_ck);
-        pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
+        pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
-                "%ld.%01ld/%ld/%ld MHz\n",
+                (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
-                (hfclkin_rate / 1000000),
-                ((hfclkin_rate / 100000) % 10),
                (clk_get_rate(core_ck) / 1000000),
                (clk_get_rate(mpu_ck) / 1000000));
 }
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 002745181ad6..c3cde1a2b6de 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -18,9 +18,9 @@
 #include <linux/clk.h>
 #include <linux/list.h>
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
@@ -1804,6 +1804,7 @@ static struct omap_clk omap2420_clks[] = {
        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
        /* DSS domain clocks */
        CLK("omapdss_dss",      "ick",          &dss_ick,       CK_242X),
+        CLK(NULL,       "dss_ick",              &dss_ick,       CK_242X),
        CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_242X),
        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_242X),
        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_242X),
@@ -1843,12 +1844,16 @@ static struct omap_clk omap2420_clks[] = {
        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_242X),
        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_242X),
        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_242X),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_242X),
        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_242X),
        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_242X),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_242X),
        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_242X),
        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_242X),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_242X),
        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_242X),
        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_242X),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_242X),
        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_242X),
        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_242X),
        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_242X),
@@ -1859,12 +1864,15 @@ static struct omap_clk omap2420_clks[] = {
        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_242X),
        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_242X),
        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_242X),
+        CLK(NULL,       "mpu_wdt_ick",          &mpu_wdt_ick,   CK_242X),
        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_242X),
        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_242X),
        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_242X),
        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_242X),
        CLK("omap24xxcam", "fck",       &cam_fck,       CK_242X),
+        CLK(NULL,       "cam_fck",      &cam_fck,       CK_242X),
        CLK("omap24xxcam", "ick",       &cam_ick,       CK_242X),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_242X),
        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_242X),
        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_242X),
        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_242X),
@@ -1873,16 +1881,22 @@ static struct omap_clk omap2420_clks[] = {
        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_242X),
        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_242X),
        CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
+        CLK(NULL,       "mmc_ick",      &mmc_ick,       CK_242X),
        CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
+        CLK(NULL,       "mmc_fck",      &mmc_fck,       CK_242X),
        CLK(NULL,       "fac_ick",      &fac_ick,       CK_242X),
        CLK(NULL,       "fac_fck",      &fac_fck,       CK_242X),
        CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
        CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_242X),
        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_242X),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_242X),
        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_242X),
        CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_242X),
        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_242X),
        CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_242X),
        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
@@ -1892,14 +1906,18 @@ static struct omap_clk omap2420_clks[] = {
        CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
        CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
        CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
+        CLK(NULL,       "sha_ick",      &sha_ick,       CK_242X),
        CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
+        CLK(NULL,       "rng_ick",              &rng_ick,       CK_242X),
        CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
+        CLK(NULL,       "aes_ick",      &aes_ick,       CK_242X),
        CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
        CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
        CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
-        CLK(NULL,       "timer_32k_ck", &func_32k_ck,   CK_243X),
+        CLK(NULL,       "timer_32k_ck", &func_32k_ck,   CK_242X),
-        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
+        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_242X),
-        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
+        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_242X),
+        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_242X),
 };
 /*
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c
index dfda9a3f2cb2..a8e326177466 100644
--- a/arch/arm/mach-omap2/clock2430.c
+++ b/arch/arm/mach-omap2/clock2430.c
@@ -21,9 +21,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/hardware.h>
 #include <plat/clock.h>
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index cacabb070e22..22404fe435e7 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -17,9 +17,9 @@
 #include <linux/clk.h>
 #include <linux/list.h>
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
@@ -1856,6 +1856,7 @@ static struct omap_clk omap2430_clks[] = {
        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X),
        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X),
        CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
+        CLK("twl",      "fck",          &osc_ck,        CK_243X),
        CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
        CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
@@ -1887,6 +1888,7 @@ static struct omap_clk omap2430_clks[] = {
        CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
        /* DSS domain clocks */
        CLK("omapdss_dss",      "ick",          &dss_ick,       CK_243X),
+        CLK(NULL,       "dss_ick",              &dss_ick,       CK_243X),
        CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_243X),
        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X),
        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X),
@@ -1926,20 +1928,28 @@ static struct omap_clk omap2430_clks[] = {
        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X),
        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X),
        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_243X),
        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_243X),
        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_243X),
        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_243X),
        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
+        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_243X),
        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_243X),
        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
+        CLK(NULL,       "mcbsp4_ick",   &mcbsp4_ick,    CK_243X),
        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_243X),
        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
+        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_243X),
        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_243X),
        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_243X),
        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_243X),
        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_243X),
        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_243X),
        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
+        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_243X),
        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_243X),
        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X),
        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X),
@@ -1950,13 +1960,16 @@ static struct omap_clk omap2430_clks[] = {
        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X),
        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X),
        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X),
+        CLK(NULL,       "mpu_wdt_ick",  &mpu_wdt_ick,   CK_243X),
        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_243X),
        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X),
        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X),
        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X),
        CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
        CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X),
+        CLK(NULL,       "cam_fck",      &cam_fck,       CK_243X),
        CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_243X),
        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X),
        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X),
        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X),
@@ -1965,10 +1978,14 @@ static struct omap_clk omap2430_clks[] = {
        CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X),
        CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X),
        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_243X),
        CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_243X),
        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_243X),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_243X),
        CLK(NULL,       "i2chs1_fck",   &i2chs1_fck,    CK_243X),
        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_243X),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_243X),
        CLK(NULL,       "i2chs2_fck",   &i2chs2_fck,    CK_243X),
        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X),
        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X),
@@ -1977,22 +1994,29 @@ static struct omap_clk omap2430_clks[] = {
        CLK(NULL,       "des_ick",      &des_ick,       CK_243X),
        CLK("omap-sham",        "ick",  &sha_ick,       CK_243X),
        CLK("omap_rng", "ick",          &rng_ick,       CK_243X),
+        CLK(NULL,       "rng_ick",      &rng_ick,       CK_243X),
        CLK("omap-aes", "ick",  &aes_ick,       CK_243X),
        CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
        CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
        CLK("musb-omap2430",    "ick",  &usbhs_ick,     CK_243X),
+        CLK(NULL,       "usbhs_ick",    &usbhs_ick,     CK_243X),
        CLK("omap_hsmmc.0", "ick",      &mmchs1_ick,    CK_243X),
+        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_243X),
        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_243X),
        CLK("omap_hsmmc.1", "ick",      &mmchs2_ick,    CK_243X),
+        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_243X),
        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_243X),
        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
        CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
        CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
+        CLK(NULL,       "mmchsdb1_fck",         &mmchsdb1_fck,  CK_243X),
        CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
+        CLK(NULL,       "mmchsdb2_fck",         &mmchsdb2_fck,  CK_243X),
        CLK(NULL,       "timer_32k_ck",  &func_32k_ck,   CK_243X),
        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
+        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_243X),
 };
 /*
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index 12500097378d..e92be1fc1a00 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -22,9 +22,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/cpu.h>
 #include <plat/clock.h>
+#include "soc.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "cm.h"
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index ae27de8899a6..114ab4b8e0e3 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -18,8 +18,8 @@
 #include <linux/list.h>
 #include <linux/clk.h>
 #include <plat/clkdev_omap.h>
-#include <plat/am33xx.h>
+#include "am33xx.h"
 #include "iomap.h"
 #include "control.h"
 #include "clock.h"
@@ -1013,6 +1013,7 @@ static struct omap_clk am33xx_clks[] = {
        CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck,       CK_AM33XX),
        CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck,       CK_AM33XX),
        CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck,   CK_AM33XX),
+        CLK("cpu0",     NULL,                   &dpll_mpu_ck,           CK_AM33XX),
        CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck,        CK_AM33XX),
        CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck,   CK_AM33XX),
        CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck,        CK_AM33XX),
@@ -1027,11 +1028,15 @@ static struct omap_clk am33xx_clks[] = {
        CLK(NULL,       "cefuse_fck",           &cefuse_fck,    CK_AM33XX),
        CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick, CK_AM33XX),
        CLK(NULL,       "dcan0_fck",            &dcan0_fck,     CK_AM33XX),
+        CLK("481cc000.d_can",   NULL,           &dcan0_fck,     CK_AM33XX),
        CLK(NULL,       "dcan1_fck",            &dcan1_fck,     CK_AM33XX),
+        CLK("481d0000.d_can",   NULL,           &dcan1_fck,     CK_AM33XX),
        CLK(NULL,       "debugss_ick",          &debugss_ick,   CK_AM33XX),
        CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk,        CK_AM33XX),
        CLK("davinci-mcasp.0",  NULL,           &mcasp0_fck,    CK_AM33XX),
        CLK("davinci-mcasp.1",  NULL,           &mcasp1_fck,    CK_AM33XX),
+        CLK(NULL,       "mcasp0_fck",           &mcasp0_fck,    CK_AM33XX),
+        CLK(NULL,       "mcasp1_fck",           &mcasp1_fck,    CK_AM33XX),
        CLK("NULL",     "mmc2_fck",             &mmc2_fck,      CK_AM33XX),
        CLK(NULL,       "mmu_fck",              &mmu_fck,       CK_AM33XX),
        CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck,      CK_AM33XX),
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 794d82702c85..83bb01427d40 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -21,9 +21,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/hardware.h>
 #include <plat/clock.h>
+#include "soc.h"
 #include "clock.h"
 #include "clock3xxx.h"
 #include "prm2xxx_3xxx.h"
@@ -49,8 +49,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
         * on DPLL4.
         */
        if (omap_rev() == OMAP3430_REV_ES1_0) {
-                pr_err("clock: DPLL4 cannot change rate due to "
+                pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
-                       "silicon 'Limitation 2.5' on 3430ES1.\n");
                return -EINVAL;
        }
@@ -64,15 +63,15 @@ void __init omap3_clk_lock_dpll5(void)
        dpll5_clk = clk_get(NULL, "dpll5_ck");
        clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
-        clk_enable(dpll5_clk);
+        clk_prepare_enable(dpll5_clk);
        /* Program dpll5_m2_clk divider for no division */
        dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
-        clk_enable(dpll5_m2_clk);
+        clk_prepare_enable(dpll5_m2_clk);
        clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
-        clk_disable(dpll5_m2_clk);
+        clk_disable_unprepare(dpll5_m2_clk);
-        clk_disable(dpll5_clk);
+        clk_disable_unprepare(dpll5_clk);
        return;
 }
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 83bed9ad3017..1f42c9d5ecf3 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -21,9 +21,9 @@
 #include <linux/list.h>
 #include <linux/io.h>
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock3xxx.h"
@@ -3215,7 +3215,6 @@ static struct clk dummy_apb_pclk = {
 * clkdev
 */
-/* XXX At some point we should rename this file to clock3xxx_data.c */
 static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
        CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
@@ -3226,6 +3225,7 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck,      CK_3XXX),
        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
+        CLK("twl",      "fck",          &osc_sys_ck,    CK_3XXX),
        CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
        CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
@@ -3242,11 +3242,13 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
+        CLK(NULL,       "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
        CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
        CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
+        CLK(NULL,       "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX),
        CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
        CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
@@ -3262,6 +3264,7 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
+        CLK(NULL,       "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
@@ -3271,6 +3274,7 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
        CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
+        CLK(NULL,       "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
@@ -3294,6 +3298,7 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
        CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
@@ -3314,6 +3319,7 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
        CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
        CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_3XXX),
        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
@@ -3321,6 +3327,8 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1,  CK_3430ES1),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
@@ -3328,28 +3336,42 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "mmchs3_ick",   &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
        CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
        CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
        CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
        CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
        CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
+        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_3XXX),
+        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_3XXX),
        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_3XXX),
        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi4_ick",   &mcspi4_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_3XXX),
        CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
+        CLK(NULL,       "i2c3_ick",     &i2c3_ick,      CK_3XXX),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_3XXX),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_3XXX),
        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_3XXX),
        CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
@@ -3368,7 +3390,9 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
        CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
        CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
+        CLK(NULL,       "dss_ick",              &dss_ick_3430es1,       CK_3430ES1),
        CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "dss_ick",              &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
        CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
@@ -3384,6 +3408,8 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
        CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
        CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
        CLK(NULL,       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
@@ -3393,6 +3419,7 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
        CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
+        CLK(NULL,       "wdt2_ick",     &wdt2_ick,      CK_3XXX),
        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
        CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
@@ -3438,9 +3465,13 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick,    CK_3XXX),
        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
+        CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_3XXX),
        CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
        CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
@@ -3456,8 +3487,12 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
        CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
        CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
+        CLK(NULL,       "emac_ick",     &emac_ick,      CK_AM35XX),
+        CLK(NULL,       "emac_fck",     &emac_fck,      CK_AM35XX),
        CLK("davinci_emac.0",   NULL,   &emac_ick,      CK_AM35XX),
        CLK("davinci_mdio.0",   NULL,   &emac_fck,      CK_AM35XX),
+        CLK(NULL,       "vpfe_ick",     &emac_ick,      CK_AM35XX),
+        CLK(NULL,       "vpfe_fck",     &emac_fck,      CK_AM35XX),
        CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
        CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
        CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx,   CK_AM35XX),
@@ -3466,6 +3501,7 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
        CLK(NULL,       "timer_32k_ck", &omap_32k_fck,  CK_3XXX),
        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_3XXX),
+        CLK(NULL,       "cpufreq_ck",   &dpll1_ck,      CK_3XXX),
 };
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index d7f55e43b761..d661d138f270 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -28,9 +28,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock44xx.h"
@@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
+        CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
        CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
        CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
        CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
@@ -3212,6 +3213,7 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
        CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
        CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
+        CLK(NULL,       "rng_ick",                      &rng_ick,       CK_443X),
        CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
        CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
        CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
@@ -3243,6 +3245,7 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
        CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
        CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
+        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
        CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
@@ -3253,15 +3256,19 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
+        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
        CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
+        CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick,        CK_443X),
        CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
        CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
        CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
+        CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
        CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
        CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
@@ -3312,8 +3319,10 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
        CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
        CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
+        CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck,      CK_443X),
        CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
        CLK(NULL,       "timer_32k_ck", &sys_32k_ck,    CK_443X),
+        /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
        CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
        CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
        CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
@@ -3325,6 +3334,18 @@ static struct omap_clk omap44xx_clks[] = {
        CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
        CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
        CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("49038000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903a000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903c000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903e000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
 };
 int __init omap4xxx_clk_init(void)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 8664f5a8bfb6..cbb879139c51 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -174,9 +174,8 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm)
                if (IS_ERR(autodep->clkdm.ptr))
                        continue;
-                pr_debug("clockdomain: adding %s sleepdep/wkdep for "
+                pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n",
-                         "clkdm %s\n", autodep->clkdm.ptr->name,
+                         clkdm->name, autodep->clkdm.ptr->name);
-                         clkdm->name);
                clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
                clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
@@ -205,9 +204,8 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
                if (IS_ERR(autodep->clkdm.ptr))
                        continue;
-                pr_debug("clockdomain: removing %s sleepdep/wkdep for "
+                pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n",
-                         "clkdm %s\n", autodep->clkdm.ptr->name,
+                         clkdm->name, autodep->clkdm.ptr->name);
-                         clkdm->name);
                clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
                clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
@@ -469,14 +467,14 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                ret = -EINVAL;
        if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear wake up of "
+                pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
-                         "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+                         clkdm1->name, clkdm2->name);
                return ret;
        }
        if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
-                pr_debug("clockdomain: hardware will wake up %s when %s wakes "
+                pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n",
-                         "up\n", clkdm1->name, clkdm2->name);
+                         clkdm1->name, clkdm2->name);
                ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
        }
@@ -510,14 +508,14 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                ret = -EINVAL;
        if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear wake up of "
+                pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
-                         "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+                         clkdm1->name, clkdm2->name);
                return ret;
        }
        if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
-                pr_debug("clockdomain: hardware will no longer wake up %s "
+                pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n",
-                         "after %s wakes up\n", clkdm1->name, clkdm2->name);
+                         clkdm1->name, clkdm2->name);
                ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
        }
@@ -555,8 +553,8 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                ret = -EINVAL;
        if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear wake up of "
+                pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
-                         "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+                         clkdm1->name, clkdm2->name);
                return ret;
        }
@@ -613,15 +611,14 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                ret = -EINVAL;
        if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear sleep "
+                pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
-                         "dependency affecting %s from %s\n", clkdm1->name,
+                         clkdm1->name, clkdm2->name);
-                         clkdm2->name);
                return ret;
        }
        if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
-                pr_debug("clockdomain: will prevent %s from sleeping if %s "
+                pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n",
-                         "is active\n", clkdm1->name, clkdm2->name);
+                         clkdm1->name, clkdm2->name);
                ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
        }
@@ -657,16 +654,14 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                ret = -EINVAL;
        if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear sleep "
+                pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
-                         "dependency affecting %s from %s\n", clkdm1->name,
+                         clkdm1->name, clkdm2->name);
-                         clkdm2->name);
                return ret;
        }
        if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
-                pr_debug("clockdomain: will no longer prevent %s from "
+                pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n",
-                         "sleeping if %s is active\n", clkdm1->name,
+                         clkdm1->name, clkdm2->name);
-                         clkdm2->name);
                ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
        }
@@ -706,9 +701,8 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                ret = -EINVAL;
        if (ret) {
-                pr_debug("clockdomain: hardware cannot set/clear sleep "
+                pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
-                         "dependency affecting %s from %s\n", clkdm1->name,
+                         clkdm1->name, clkdm2->name);
-                         clkdm2->name);
                return ret;
        }
@@ -755,8 +749,8 @@ int clkdm_sleep(struct clockdomain *clkdm)
                return -EINVAL;
        if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
-                pr_debug("clockdomain: %s does not support forcing "
+                pr_debug("clockdomain: %s does not support forcing sleep via software\n",
-                         "sleep via software\n", clkdm->name);
+                         clkdm->name);
                return -EINVAL;
        }
@@ -790,8 +784,8 @@ int clkdm_wakeup(struct clockdomain *clkdm)
                return -EINVAL;
        if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
-                pr_debug("clockdomain: %s does not support forcing "
+                pr_debug("clockdomain: %s does not support forcing wakeup via software\n",
-                         "wakeup via software\n", clkdm->name);
+                         clkdm->name);
                return -EINVAL;
        }
@@ -826,8 +820,8 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
                return;
        if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
-                pr_debug("clock: automatic idle transitions cannot be enabled "
+                pr_debug("clock: %s: automatic idle transitions cannot be enabled\n",
-                         "on clockdomain %s\n", clkdm->name);
+                         clkdm->name);
                return;
        }
@@ -861,8 +855,8 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
                return;
        if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
-                pr_debug("clockdomain: automatic idle transitions cannot be "
+                pr_debug("clockdomain: %s: automatic idle transitions cannot be disabled\n",
-                         "disabled on %s\n", clkdm->name);
+                         clkdm->name);
                return;
        }
@@ -905,6 +899,23 @@ bool clkdm_in_hwsup(struct clockdomain *clkdm)
        return ret;
 }
+/**
+ * clkdm_missing_idle_reporting - can @clkdm enter autoidle even if in use?
+ * @clkdm: struct clockdomain *
+ *
+ * Returns true if clockdomain @clkdm has the
+ * CLKDM_MISSING_IDLE_REPORTING flag set, or false if not or @clkdm is
+ * null.  More information is available in the documentation for the
+ * CLKDM_MISSING_IDLE_REPORTING macro.
+ */
+bool clkdm_missing_idle_reporting(struct clockdomain *clkdm)
+{
+        if (!clkdm)
+                return false;
+        return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false;
+}
 /* Clockdomain-to-clock/hwmod framework interface code */
 static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
@@ -927,7 +938,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
        pwrdm_state_switch(clkdm->pwrdm.ptr);
        spin_unlock_irqrestore(&clkdm->lock, flags);
-        pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
+        pr_debug("clockdomain: %s: enabled\n", clkdm->name);
        return 0;
 }
@@ -952,7 +963,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
        pwrdm_state_switch(clkdm->pwrdm.ptr);
        spin_unlock_irqrestore(&clkdm->lock, flags);
-        pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
+        pr_debug("clockdomain: %s: disabled\n", clkdm->name);
        return 0;
 }
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 5601dc13785e..629576be7444 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -1,9 +1,7 @@
 /*
- * arch/arm/plat-omap/include/mach/clockdomain.h
- *
 * OMAP2/3 clockdomain framework functions
 *
- * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008, 2012 Texas Instruments, Inc.
 * Copyright (C) 2008-2011 Nokia Corporation
 *
 * Paul Walmsley
@@ -34,6 +32,20 @@
 * CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is
 *     active whenever the MPU is active.  True for interconnects and
 *     the WKUP clockdomains.
+ * CLKDM_MISSING_IDLE_REPORTING: The idle status of the IP blocks and
+ *     clocks inside this clockdomain are not taken into account by
+ *     the PRCM when determining whether the clockdomain is idle.
+ *     Without this flag, if the clockdomain is set to
+ *     hardware-supervised idle mode, the PRCM may transition the
+ *     enclosing powerdomain to a low power state, even when devices
+ *     inside the clockdomain and powerdomain are in use.  (An example
+ *     of such a clockdomain is the EMU clockdomain on OMAP3/4.)  If
+ *     this flag is set, and the clockdomain does not support the
+ *     force-sleep mode, then the HW_AUTO mode will be used to put the
+ *     clockdomain to sleep.  Similarly, if the clockdomain supports
+ *     the force-wakeup mode, then it will be used whenever a clock or
+ *     IP block inside the clockdomain is active, rather than the
+ *     HW_AUTO mode.
 */
 #define CLKDM_CAN_FORCE_SLEEP                   (1 << 0)
 #define CLKDM_CAN_FORCE_WAKEUP                  (1 << 1)
@@ -41,6 +53,7 @@
 #define CLKDM_CAN_DISABLE_AUTO                  (1 << 3)
 #define CLKDM_NO_AUTODEPS                       (1 << 4)
 #define CLKDM_ACTIVE_WITH_MPU                   (1 << 5)
+#define CLKDM_MISSING_IDLE_REPORTING            (1 << 6)
 #define CLKDM_CAN_HWSUP         (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
 #define CLKDM_CAN_SWSUP         (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
@@ -187,6 +200,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
 void clkdm_allow_idle(struct clockdomain *clkdm);
 void clkdm_deny_idle(struct clockdomain *clkdm);
 bool clkdm_in_hwsup(struct clockdomain *clkdm);
+bool clkdm_missing_idle_reporting(struct clockdomain *clkdm);
 int clkdm_wakeup(struct clockdomain *clkdm);
 int clkdm_sleep(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
index f99e65cfb862..70294f54e35a 100644
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -162,6 +162,19 @@ static void _disable_hwsup(struct clockdomain *clkdm)
                                                clkdm->clktrctrl_mask);
 }
+static int omap3_clkdm_sleep(struct clockdomain *clkdm)
+{
+        omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        return 0;
+}
+static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        return 0;
+}
 static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
 {
@@ -209,20 +222,6 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
        return 0;
 }
-static int omap3_clkdm_sleep(struct clockdomain *clkdm)
-{
-        omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        return 0;
-}
-static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
-{
-        omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        return 0;
-}
 static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
 {
        if (atomic_read(&clkdm->usecount) > 0)
@@ -248,6 +247,17 @@ static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
        if (!clkdm->clktrctrl_mask)
                return 0;
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
+            (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
+                omap3_clkdm_wakeup(clkdm);
+                return 0;
+        }
        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                clkdm->clktrctrl_mask);
@@ -271,6 +281,17 @@ static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
        if (!clkdm->clktrctrl_mask)
                return 0;
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
+            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+                _enable_hwsup(clkdm);
+                return 0;
+        }
        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                clkdm->clktrctrl_mask);
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index 762f2cc542ce..6fc6155625bc 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -113,6 +113,17 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
        if (!clkdm->prcm_partition)
                return 0;
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
+            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+                omap4_clkdm_allow_idle(clkdm);
+                return 0;
+        }
        hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
                                        clkdm->cm_inst, clkdm->clkdm_offs);
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index 56089c49142a..933a35cd124a 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -387,14 +387,11 @@ static struct clockdomain per_am35x_clkdm = {
        .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
 };
-/*
- * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
- * switched of even if sdti is in use
- */
 static struct clockdomain emu_clkdm = {
        .name           = "emu_clkdm",
        .pwrdm          = { .name = "emu_pwrdm" },
-        .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
+        .flags          = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP |
+                           CLKDM_MISSING_IDLE_REPORTING),
        .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
 };
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 63d60a773d3b..b56d06b48782 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -390,7 +390,8 @@ static struct clockdomain emu_sys_44xx_clkdm = {
        .prcm_partition   = OMAP4430_PRM_PARTITION,
        .cm_inst          = OMAP4430_PRM_EMU_CM_INST,
        .clkdm_offs       = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
-        .flags            = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP,
+        .flags            = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP |
+                             CLKDM_MISSING_IDLE_REPORTING),
 };
 static struct clockdomain l3_dma_44xx_clkdm = {
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
index 532027ee3d8d..adf7bb79b18f 100644
--- a/arch/arm/mach-omap2/cm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -25,263 +25,328 @@
 * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
 */
 #define AM33XX_AUTO_DPLL_MODE_SHIFT                     0
+#define AM33XX_AUTO_DPLL_MODE_WIDTH                     3
 #define AM33XX_AUTO_DPLL_MODE_MASK                      (0x7 << 0)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT               14
+#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK                (1 << 16)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT                11
+#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH                1
 #define AM33XX_CLKACTIVITY_CAN_CLK_MASK                 (1 << 11)
 /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT         4
+#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK          (1 << 4)
 /* Used by CM_PER_CPSW_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK        (1 << 4)
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK        (1 << 4)
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT        5
+#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH        1
 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK         (1 << 5)
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT         6
+#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK          (1 << 6)
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT          6
+#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK           (1 << 6)
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT     9
+#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH     1
 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK      (1 << 9)
 /* Used by CM_L3_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT              2
+#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK               (1 << 2)
 /* Used by CM_L3_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT             4
+#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH             1
 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK              (1 << 4)
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT              2
+#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK               (1 << 2)
 /* Used by CM_GFX_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT               9
+#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK                (1 << 9)
 /* Used by CM_GFX_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT            8
+#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK             (1 << 8)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT           8
+#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH           1
 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK            (1 << 8)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT          19
+#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK           (1 << 19)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT          20
+#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK           (1 << 20)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT          21
+#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK           (1 << 21)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT          22
+#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK           (1 << 22)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT          26
+#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK           (1 << 26)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT          18
+#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK           (1 << 18)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT             11
+#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK              (1 << 11)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT               24
+#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK                (1 << 24)
 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT         5
+#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK          (1 << 5)
 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT         4
+#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK          (1 << 4)
 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT        6
+#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH        1
 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK         (1 << 6)
 /* Used by CM_PER_L3S_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT               3
+#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK                (1 << 3)
 /* Used by CM_L3_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT            3
+#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK             (1 << 3)
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT                4
+#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH                1
 #define AM33XX_CLKACTIVITY_L3_GCLK_MASK                 (1 << 4)
 /* Used by CM_PER_L4FW_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT              8
+#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK               (1 << 8)
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT              3
+#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK               (1 << 3)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT              8
+#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK               (1 << 8)
 /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT          8
+#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK           (1 << 8)
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT        8
+#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH        1
 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK         (1 << 8)
 /* Used by CM_RTC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT            8
+#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK             (1 << 8)
 /* Used by CM_L4_WKUP_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT       2
+#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK        (1 << 2)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT           2
+#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH           1
 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK            (1 << 2)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT              17
+#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK               (1 << 17)
 /* Used by CM_PER_LCDC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK        (1 << 4)
 /* Used by CM_PER_LCDC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT       5
+#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK        (1 << 5)
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT             7
+#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK              (1 << 7)
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT               3
+#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK                (1 << 3)
 /* Used by CM_MPU_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT                2
+#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH                1
 #define AM33XX_CLKACTIVITY_MPU_CLK_MASK                 (1 << 2)
 /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT          4
+#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK           (1 << 4)
 /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT          5
+#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK           (1 << 5)
 /* Used by CM_RTC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT             9
+#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK              (1 << 9)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT               25
+#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK                (1 << 25)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT              3
+#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK               (1 << 3)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT            10
+#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK             (1 << 10)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT            13
+#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK             (1 << 13)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT            14
+#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK             (1 << 14)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT            15
+#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK             (1 << 15)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT            16
+#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK             (1 << 16)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT            27
+#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK             (1 << 27)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT            28
+#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK             (1 << 28)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT            13
+#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK             (1 << 13)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT            12
+#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK             (1 << 12)
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT             10
+#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK              (1 << 10)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT              9
+#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK               (1 << 9)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT              4
+#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK               (1 << 4)
 /* Used by CLKSEL_GFX_FCLK */
 #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT                0
+#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH                1
 #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK                 (1 << 0)
 /* Used by CM_CLKOUT_CTRL */
 #define AM33XX_CLKOUT2DIV_SHIFT                         3
-#define AM33XX_CLKOUT2DIV_MASK                          (0x05 << 3)
+#define AM33XX_CLKOUT2DIV_WIDTH                         3
+#define AM33XX_CLKOUT2DIV_MASK                          (0x7 << 3)
 /* Used by CM_CLKOUT_CTRL */
 #define AM33XX_CLKOUT2EN_SHIFT                          7
+#define AM33XX_CLKOUT2EN_WIDTH                          1
 #define AM33XX_CLKOUT2EN_MASK                           (1 << 7)
 /* Used by CM_CLKOUT_CTRL */
 #define AM33XX_CLKOUT2SOURCE_SHIFT                      0
-#define AM33XX_CLKOUT2SOURCE_MASK                       (0x02 << 0)
+#define AM33XX_CLKOUT2SOURCE_WIDTH                      3
+#define AM33XX_CLKOUT2SOURCE_MASK                       (0x7 << 0)
 /*
 * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
@@ -289,6 +354,7 @@
 * CLKSEL_TIMER7_CLK
 */
 #define AM33XX_CLKSEL_SHIFT                             0
+#define AM33XX_CLKSEL_WIDTH                             1
 #define AM33XX_CLKSEL_MASK                              (0x01 << 0)
 /*
@@ -296,17 +362,21 @@
 * CM_CPTS_RFT_CLKSEL
 */
 #define AM33XX_CLKSEL_0_0_SHIFT                         0
+#define AM33XX_CLKSEL_0_0_WIDTH                         1
 #define AM33XX_CLKSEL_0_0_MASK                          (1 << 0)
 #define AM33XX_CLKSEL_0_1_SHIFT                         0
+#define AM33XX_CLKSEL_0_1_WIDTH                         2
 #define AM33XX_CLKSEL_0_1_MASK                          (3 << 0)
 /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
 #define AM33XX_CLKSEL_0_2_SHIFT                         0
+#define AM33XX_CLKSEL_0_2_WIDTH                         3
 #define AM33XX_CLKSEL_0_2_MASK                          (7 << 0)
 /* Used by CLKSEL_GFX_FCLK */
 #define AM33XX_CLKSEL_GFX_FCLK_SHIFT                    1
+#define AM33XX_CLKSEL_GFX_FCLK_WIDTH                    1
 #define AM33XX_CLKSEL_GFX_FCLK_MASK                     (1 << 1)
 /*
@@ -318,6 +388,7 @@
 * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
 */
 #define AM33XX_CLKTRCTRL_SHIFT                          0
+#define AM33XX_CLKTRCTRL_WIDTH                          2
 #define AM33XX_CLKTRCTRL_MASK                           (0x3 << 0)
 /*
@@ -326,34 +397,42 @@
 * CM_SSC_DELTAMSTEP_DPLL_PER
 */
 #define AM33XX_DELTAMSTEP_SHIFT                         0
-#define AM33XX_DELTAMSTEP_MASK                          (0x19 << 0)
+#define AM33XX_DELTAMSTEP_WIDTH                         20
+#define AM33XX_DELTAMSTEP_MASK                          (0xfffff << 0)
 /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
 #define AM33XX_DPLL_BYP_CLKSEL_SHIFT                    23
+#define AM33XX_DPLL_BYP_CLKSEL_WIDTH                    1
 #define AM33XX_DPLL_BYP_CLKSEL_MASK                     (1 << 23)
 /* Used by CM_CLKDCOLDO_DPLL_PER */
 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT           8
+#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH           1
 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK            (1 << 8)
 /* Used by CM_CLKDCOLDO_DPLL_PER */
 #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT                12
+#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH                1
 #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK                 (1 << 12)
 /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
 #define AM33XX_DPLL_CLKOUT_DIV_SHIFT                    0
+#define AM33XX_DPLL_CLKOUT_DIV_WIDTH                    5
 #define AM33XX_DPLL_CLKOUT_DIV_MASK                     (0x1f << 0)
 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
 #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT                0
-#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK                 (0x06 << 0)
+#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH                7
+#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK                 (0x7f << 0)
 /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT               5
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH               1
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK                (1 << 5)
 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT        7
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH        1
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK         (1 << 7)
 /*
@@ -361,6 +440,7 @@
 * CM_DIV_M2_DPLL_PER
 */
 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT              8
+#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH              1
 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK               (1 << 8)
 /*
@@ -368,19 +448,22 @@
 * CM_CLKSEL_DPLL_MPU
 */
 #define AM33XX_DPLL_DIV_SHIFT                           0
+#define AM33XX_DPLL_DIV_WIDTH                           7
 #define AM33XX_DPLL_DIV_MASK                            (0x7f << 0)
 #define AM33XX_DPLL_PER_DIV_MASK                        (0xff << 0)
 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
 #define AM33XX_DPLL_DIV_0_7_SHIFT                       0
-#define AM33XX_DPLL_DIV_0_7_MASK                        (0x07 << 0)
+#define AM33XX_DPLL_DIV_0_7_WIDTH                       8
+#define AM33XX_DPLL_DIV_0_7_MASK                        (0xff << 0)
 /*
 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 * CM_CLKMODE_DPLL_MPU
 */
 #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT                 8
+#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH                 1
 #define AM33XX_DPLL_DRIFTGUARD_EN_MASK                  (1 << 8)
 /*
@@ -388,6 +471,7 @@
 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 */
 #define AM33XX_DPLL_EN_SHIFT                            0
+#define AM33XX_DPLL_EN_WIDTH                            3
 #define AM33XX_DPLL_EN_MASK                             (0x7 << 0)
 /*
@@ -395,6 +479,7 @@
 * CM_CLKMODE_DPLL_MPU
 */
 #define AM33XX_DPLL_LPMODE_EN_SHIFT                     10
+#define AM33XX_DPLL_LPMODE_EN_WIDTH                     1
 #define AM33XX_DPLL_LPMODE_EN_MASK                      (1 << 10)
 /*
@@ -402,10 +487,12 @@
 * CM_CLKSEL_DPLL_MPU
 */
 #define AM33XX_DPLL_MULT_SHIFT                          8
+#define AM33XX_DPLL_MULT_WIDTH                          11
 #define AM33XX_DPLL_MULT_MASK                           (0x7ff << 8)
 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
 #define AM33XX_DPLL_MULT_PERIPH_SHIFT                   8
+#define AM33XX_DPLL_MULT_PERIPH_WIDTH                   12
 #define AM33XX_DPLL_MULT_PERIPH_MASK                    (0xfff << 8)
 /*
@@ -413,17 +500,20 @@
 * CM_CLKMODE_DPLL_MPU
 */
 #define AM33XX_DPLL_REGM4XEN_SHIFT                      11
+#define AM33XX_DPLL_REGM4XEN_WIDTH                      1
 #define AM33XX_DPLL_REGM4XEN_MASK                       (1 << 11)
 /* Used by CM_CLKSEL_DPLL_PERIPH */
 #define AM33XX_DPLL_SD_DIV_SHIFT                        24
-#define AM33XX_DPLL_SD_DIV_MASK                         (24, 31)
+#define AM33XX_DPLL_SD_DIV_WIDTH                        8
+#define AM33XX_DPLL_SD_DIV_MASK                         (0xff << 24)
 /*
 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 */
 #define AM33XX_DPLL_SSC_ACK_SHIFT                       13
+#define AM33XX_DPLL_SSC_ACK_WIDTH                       1
 #define AM33XX_DPLL_SSC_ACK_MASK                        (1 << 13)
 /*
@@ -431,6 +521,7 @@
 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 */
 #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT                14
+#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH                1
 #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK                 (1 << 14)
 /*
@@ -438,54 +529,67 @@
 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 */
 #define AM33XX_DPLL_SSC_EN_SHIFT                        12
+#define AM33XX_DPLL_SSC_EN_WIDTH                        1
 #define AM33XX_DPLL_SSC_EN_MASK                         (1 << 12)
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT              0
+#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH              5
 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK               (0x1f << 0)
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH         1
 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK          (1 << 5)
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH        1
 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK         (1 << 8)
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH             1
 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK              (1 << 12)
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT              0
+#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH              5
 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK               (0x1f << 0)
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH         1
 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK          (1 << 5)
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH        1
 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK         (1 << 8)
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH             1
 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK              (1 << 12)
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT              0
-#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK               (0x04 << 0)
+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH              5
+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK               (0x1f << 0)
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH         1
 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK          (1 << 5)
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH        1
 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK         (1 << 8)
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH             1
 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK              (1 << 12)
 /*
@@ -522,11 +626,12 @@
 * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
 */
 #define AM33XX_IDLEST_SHIFT                             16
+#define AM33XX_IDLEST_WIDTH                             2
 #define AM33XX_IDLEST_MASK                              (0x3 << 16)
-#define AM33XX_IDLEST_VAL                               0x3
 /* Used by CM_MAC_CLKSEL */
 #define AM33XX_MII_CLK_SEL_SHIFT                        2
+#define AM33XX_MII_CLK_SEL_WIDTH                        1
 #define AM33XX_MII_CLK_SEL_MASK                         (1 << 2)
 /*
@@ -535,7 +640,8 @@
 * CM_SSC_MODFREQDIV_DPLL_PER
 */
 #define AM33XX_MODFREQDIV_EXPONENT_SHIFT                8
-#define AM33XX_MODFREQDIV_EXPONENT_MASK                 (0x10 << 8)
+#define AM33XX_MODFREQDIV_EXPONENT_WIDTH                3
+#define AM33XX_MODFREQDIV_EXPONENT_MASK                 (0x7 << 8)
 /*
 * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
@@ -543,7 +649,8 @@
 * CM_SSC_MODFREQDIV_DPLL_PER
 */
 #define AM33XX_MODFREQDIV_MANTISSA_SHIFT                0
-#define AM33XX_MODFREQDIV_MANTISSA_MASK                 (0x06 << 0)
+#define AM33XX_MODFREQDIV_MANTISSA_WIDTH                7
+#define AM33XX_MODFREQDIV_MANTISSA_MASK                 (0x7f << 0)
 /*
 * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
@@ -580,42 +687,52 @@
 * CM_CEFUSE_CEFUSE_CLKCTRL
 */
 #define AM33XX_MODULEMODE_SHIFT                         0
+#define AM33XX_MODULEMODE_WIDTH                         2
 #define AM33XX_MODULEMODE_MASK                          (0x3 << 0)
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT                  30
+#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH                  1
 #define AM33XX_OPTCLK_DEBUG_CLKA_MASK                   (1 << 30)
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT                19
+#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH                1
 #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK                 (1 << 19)
 /* Used by CM_WKUP_GPIO0_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT             18
+#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH             1
 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK              (1 << 18)
 /* Used by CM_PER_GPIO1_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK             (1 << 18)
 /* Used by CM_PER_GPIO2_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK             (1 << 18)
 /* Used by CM_PER_GPIO3_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK             (1 << 18)
 /* Used by CM_PER_GPIO4_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK             (1 << 18)
 /* Used by CM_PER_GPIO5_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK             (1 << 18)
 /* Used by CM_PER_GPIO6_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK             (1 << 18)
 /*
@@ -627,25 +744,30 @@
 * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
 */
 #define AM33XX_STBYST_SHIFT                             18
+#define AM33XX_STBYST_WIDTH                             1
 #define AM33XX_STBYST_MASK                              (1 << 18)
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT                  27
-#define AM33XX_STM_PMD_CLKDIVSEL_MASK                   (0x29 << 27)
+#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH                  3
+#define AM33XX_STM_PMD_CLKDIVSEL_MASK                   (0x7 << 27)
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_STM_PMD_CLKSEL_SHIFT                     22
-#define AM33XX_STM_PMD_CLKSEL_MASK                      (0x23 << 22)
+#define AM33XX_STM_PMD_CLKSEL_WIDTH                     2
+#define AM33XX_STM_PMD_CLKSEL_MASK                      (0x3 << 22)
 /*
 * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
 */
 #define AM33XX_ST_DPLL_CLK_SHIFT                        0
+#define AM33XX_ST_DPLL_CLK_WIDTH                        1
 #define AM33XX_ST_DPLL_CLK_MASK                         (1 << 0)
 /* Used by CM_CLKDCOLDO_DPLL_PER */
 #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT                  8
+#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH                  1
 #define AM33XX_ST_DPLL_CLKDCOLDO_MASK                   (1 << 8)
 /*
@@ -653,18 +775,22 @@
 * CM_DIV_M2_DPLL_PER
 */
 #define AM33XX_ST_DPLL_CLKOUT_SHIFT                     9
+#define AM33XX_ST_DPLL_CLKOUT_WIDTH                     1
 #define AM33XX_ST_DPLL_CLKOUT_MASK                      (1 << 9)
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH               1
 #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK                (1 << 9)
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH               1
 #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK                (1 << 9)
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH               1
 #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK                (1 << 9)
 /*
@@ -672,16 +798,20 @@
 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
 */
 #define AM33XX_ST_MN_BYPASS_SHIFT                       8
+#define AM33XX_ST_MN_BYPASS_WIDTH                       1
 #define AM33XX_ST_MN_BYPASS_MASK                        (1 << 8)
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT                  24
-#define AM33XX_TRC_PMD_CLKDIVSEL_MASK                   (0x26 << 24)
+#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH                  3
+#define AM33XX_TRC_PMD_CLKDIVSEL_MASK                   (0x7 << 24)
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_TRC_PMD_CLKSEL_SHIFT                     20
-#define AM33XX_TRC_PMD_CLKSEL_MASK                      (0x21 << 20)
+#define AM33XX_TRC_PMD_CLKSEL_WIDTH                     2
+#define AM33XX_TRC_PMD_CLKSEL_MASK                      (0x3 << 20)
 /* Used by CONTROL_SEC_CLK_CTRL */
+#define AM33XX_TIMER0_CLKSEL_WIDTH                      2
 #define AM33XX_TIMER0_CLKSEL_MASK                       (0x3 << 4)
 #endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 975f6bda0e0b..59598ffd8783 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -218,6 +218,8 @@
 #define OMAP3430_ST_MAILBOXES_MASK                      (1 << 7)
 #define OMAP3430_ST_OMAPCTRL_SHIFT                      6
 #define OMAP3430_ST_OMAPCTRL_MASK                       (1 << 6)
+#define OMAP3430_ST_SAD2D_SHIFT                         3
+#define OMAP3430_ST_SAD2D_MASK                          (1 << 3)
 #define OMAP3430_ST_SDMA_SHIFT                          2
 #define OMAP3430_ST_SDMA_MASK                           (1 << 2)
 #define OMAP3430_ST_SDRC_SHIFT                          1
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 65597a745638..4c6c2f7de65b 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -1,7 +1,7 @@
 /*
 * OMAP44xx Clock Management register bits
 *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley (paul@pwsan.com)
@@ -24,6 +24,7 @@
 /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
 #define OMAP4430_ABE_DYNDEP_SHIFT                               3
+#define OMAP4430_ABE_DYNDEP_WIDTH                               0x1
 #define OMAP4430_ABE_DYNDEP_MASK                                (1 << 3)
 /*
@@ -31,14 +32,17 @@
 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
 #define OMAP4430_ABE_STATDEP_SHIFT                              3
+#define OMAP4430_ABE_STATDEP_WIDTH                              0x1
 #define OMAP4430_ABE_STATDEP_MASK                               (1 << 3)
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         16
+#define OMAP4430_ALWONCORE_DYNDEP_WIDTH                         0x1
 #define OMAP4430_ALWONCORE_DYNDEP_MASK                          (1 << 16)
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
 #define OMAP4430_ALWONCORE_STATDEP_SHIFT                        16
+#define OMAP4430_ALWONCORE_STATDEP_WIDTH                        0x1
 #define OMAP4430_ALWONCORE_STATDEP_MASK                         (1 << 16)
 /*
@@ -47,294 +51,367 @@
 * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
 */
 #define OMAP4430_AUTO_DPLL_MODE_SHIFT                           0
+#define OMAP4430_AUTO_DPLL_MODE_WIDTH                           0x3
 #define OMAP4430_AUTO_DPLL_MODE_MASK                            (0x7 << 0)
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_CEFUSE_DYNDEP_SHIFT                            17
+#define OMAP4430_CEFUSE_DYNDEP_WIDTH                            0x1
 #define OMAP4430_CEFUSE_DYNDEP_MASK                             (1 << 17)
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
 #define OMAP4430_CEFUSE_STATDEP_SHIFT                           17
+#define OMAP4430_CEFUSE_STATDEP_WIDTH                           0x1
 #define OMAP4430_CEFUSE_STATDEP_MASK                            (1 << 17)
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                13
+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 (1 << 13)
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            12
+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             (1 << 12)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   9
+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    (1 << 9)
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   11
+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    (1 << 11)
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    (1 << 8)
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                11
+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 (1 << 11)
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               12
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                (1 << 12)
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               13
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                (1 << 13)
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            9
+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             (1 << 9)
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT         12
+#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH         0x1
 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK          (1 << 12)
 /* Used by CM_EMU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            9
+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             (1 << 9)
 /* Used by CM_L4CFG_CLKSTCTRL */
 #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT                9
+#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH                0x1
 #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK                 (1 << 9)
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           9
+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH           0x1
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            (1 << 9)
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      9
+#define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH                      0x1
 #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       (1 << 9)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  9
+#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   (1 << 9)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  10
+#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   (1 << 10)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   11
+#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    (1 << 11)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   12
+#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    (1 << 12)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   13
+#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    (1 << 13)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   14
+#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    (1 << 14)
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            10
+#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             (1 << 10)
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     9
+#define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH                     0x1
 #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      (1 << 9)
 /* Used by CM_DUCATI_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  8
+#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   (1 << 8)
 /* Used by CM_EMU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  8
+#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   (1 << 8)
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   10
+#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    (1 << 10)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               15
+#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                (1 << 15)
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               10
+#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                (1 << 10)
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         11
+#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH         0x1
 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          (1 << 11)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           20
+#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH           0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            (1 << 20)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                26
+#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 (1 << 26)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           21
+#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH           0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            (1 << 21)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                27
+#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 (1 << 27)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              13
+#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               (1 << 13)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               12
+#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                (1 << 12)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            28
+#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             (1 << 28)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            29
+#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             (1 << 29)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               11
+#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                (1 << 11)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               16
+#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                (1 << 16)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            17
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             (1 << 17)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            18
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             (1 << 18)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            19
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             (1 << 19)
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     8
+#define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH                     0x1
 #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      (1 << 8)
 /* Used by CM_IVAHD_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               8
+#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                (1 << 8)
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT               10
+#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK                (1 << 10)
 /* Used by CM_L3_1_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    (1 << 8)
 /* Used by CM_L3_2_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    (1 << 8)
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  (1 << 8)
 /* Used by CM_SDMA_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  (1 << 8)
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  (1 << 8)
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                8
+#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 (1 << 8)
 /* Used by CM_GFX_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  (1 << 8)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                8
+#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 (1 << 8)
 /* Used by CM_L3INSTR_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               8
+#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                (1 << 8)
 /* Used by CM_L4SEC_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              8
+#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               (1 << 8)
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    (1 << 8)
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              8
+#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               (1 << 8)
 /* Used by CM_L4CFG_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  (1 << 8)
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 9
+#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  (1 << 9)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                9
+#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 (1 << 9)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  (1 << 8)
 /* Used by CM_L4SEC_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              9
+#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               (1 << 9)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                12
+#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 (1 << 12)
 /* Used by CM_MPU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  (1 << 8)
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                9
+#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 (1 << 9)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               16
+#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                (1 << 16)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                17
+#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 (1 << 17)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                18
+#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 (1 << 18)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                19
+#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 (1 << 19)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            25
+#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             (1 << 25)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             20
+#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH             0x1
 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              (1 << 20)
 /* Used by CM_L4PER_CLKSTCTRL */
@@ -343,94 +420,114 @@
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             22
+#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH             0x1
 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              (1 << 22)
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                24
+#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 (1 << 24)
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 10
+#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  (1 << 10)
 /* Used by CM_GFX_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    9
+#define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH                    0x1
 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     (1 << 9)
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               11
+#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                (1 << 11)
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                10
+#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 (1 << 10)
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                9
+#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 (1 << 9)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      8
+#define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH                      0x1
 #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       (1 << 8)
 /* Used by CM_TESLA_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               8
+#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                (1 << 8)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                22
+#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 (1 << 22)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                23
+#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 (1 << 23)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                24
+#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 (1 << 24)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT              10
+#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK               (1 << 10)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT                 14
+#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK                  (1 << 14)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              15
+#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               (1 << 15)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   10
+#define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    (1 << 10)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                30
+#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 (1 << 30)
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              25
+#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               (1 << 25)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               11
+#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                (1 << 11)
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT                13
+#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH                0x1
 #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK                 (1 << 13)
 /*
 * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
 * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
- * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
 * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
 * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
- * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
+ * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL
- * CM_WKUP_TIMER1_CLKCTRL
 */
 #define OMAP4430_CLKSEL_SHIFT                                   24
+#define OMAP4430_CLKSEL_WIDTH                                   0x1
 #define OMAP4430_CLKSEL_MASK                                    (1 << 24)
 /*
@@ -438,50 +535,62 @@
 * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
 */
 #define OMAP4430_CLKSEL_0_0_SHIFT                               0
+#define OMAP4430_CLKSEL_0_0_WIDTH                               0x1
 #define OMAP4430_CLKSEL_0_0_MASK                                (1 << 0)
 /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
 #define OMAP4430_CLKSEL_0_1_SHIFT                               0
+#define OMAP4430_CLKSEL_0_1_WIDTH                               0x2
 #define OMAP4430_CLKSEL_0_1_MASK                                (0x3 << 0)
 /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
 #define OMAP4430_CLKSEL_24_25_SHIFT                             24
+#define OMAP4430_CLKSEL_24_25_WIDTH                             0x2
 #define OMAP4430_CLKSEL_24_25_MASK                              (0x3 << 24)
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_CLKSEL_60M_SHIFT                               24
+#define OMAP4430_CLKSEL_60M_WIDTH                               0x1
 #define OMAP4430_CLKSEL_60M_MASK                                (1 << 24)
 /* Used by CM_MPU_MPU_CLKCTRL */
 #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT                      25
+#define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH                      0x1
 #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK                       (1 << 25)
 /* Used by CM1_ABE_AESS_CLKCTRL */
 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         24
+#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH                         0x1
 #define OMAP4430_CLKSEL_AESS_FCLK_MASK                          (1 << 24)
 /* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_CORE_SHIFT                              0
+#define OMAP4430_CLKSEL_CORE_WIDTH                              0x1
 #define OMAP4430_CLKSEL_CORE_MASK                               (1 << 0)
 /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          1
+#define OMAP4430_CLKSEL_CORE_1_1_WIDTH                          0x1
 #define OMAP4430_CLKSEL_CORE_1_1_MASK                           (1 << 1)
 /* Used by CM_WKUP_USIM_CLKCTRL */
 #define OMAP4430_CLKSEL_DIV_SHIFT                               24
+#define OMAP4430_CLKSEL_DIV_WIDTH                               0x1
 #define OMAP4430_CLKSEL_DIV_MASK                                (1 << 24)
 /* Used by CM_MPU_MPU_CLKCTRL */
 #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT                     24
+#define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH                     0x1
 #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK                      (1 << 24)
 /* Used by CM_CAM_FDIF_CLKCTRL */
 #define OMAP4430_CLKSEL_FCLK_SHIFT                              24
+#define OMAP4430_CLKSEL_FCLK_WIDTH                              0x2
 #define OMAP4430_CLKSEL_FCLK_MASK                               (0x3 << 24)
 /* Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   25
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH                   0x1
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    (1 << 25)
 /*
@@ -490,34 +599,42 @@
 * CM1_ABE_MCBSP3_CLKCTRL
 */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      26
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH      0x2
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       (0x3 << 26)
 /* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_L3_SHIFT                                4
+#define OMAP4430_CLKSEL_L3_WIDTH                                0x1
 #define OMAP4430_CLKSEL_L3_MASK                                 (1 << 4)
 /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         2
+#define OMAP4430_CLKSEL_L3_SHADOW_WIDTH                         0x1
 #define OMAP4430_CLKSEL_L3_SHADOW_MASK                          (1 << 2)
 /* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_L4_SHIFT                                8
+#define OMAP4430_CLKSEL_L4_WIDTH                                0x1
 #define OMAP4430_CLKSEL_L4_MASK                                 (1 << 8)
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_CLKSEL_OPP_SHIFT                               0
+#define OMAP4430_CLKSEL_OPP_WIDTH                               0x2
 #define OMAP4430_CLKSEL_OPP_MASK                                (0x3 << 0)
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       27
+#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH                       0x3
 #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        (0x7 << 27)
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     24
+#define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH                     0x3
 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      (0x7 << 24)
 /* Used by CM_GFX_GFX_CLKCTRL */
 #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          24
+#define OMAP4430_CLKSEL_SGX_FCLK_WIDTH                          0x1
 #define OMAP4430_CLKSEL_SGX_FCLK_MASK                           (1 << 24)
 /*
@@ -525,18 +642,22 @@
 * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
 */
 #define OMAP4430_CLKSEL_SOURCE_SHIFT                            24
+#define OMAP4430_CLKSEL_SOURCE_WIDTH                            0x2
 #define OMAP4430_CLKSEL_SOURCE_MASK                             (0x3 << 24)
 /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      24
+#define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH                      0x1
 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       (1 << 24)
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           24
+#define OMAP4430_CLKSEL_UTMI_P1_WIDTH                           0x1
 #define OMAP4430_CLKSEL_UTMI_P1_MASK                            (1 << 24)
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           25
+#define OMAP4430_CLKSEL_UTMI_P2_WIDTH                           0x1
 #define OMAP4430_CLKSEL_UTMI_P2_MASK                            (1 << 25)
 /*
@@ -549,30 +670,37 @@
 * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
 */
 #define OMAP4430_CLKTRCTRL_SHIFT                                0
+#define OMAP4430_CLKTRCTRL_WIDTH                                0x2
 #define OMAP4430_CLKTRCTRL_MASK                                 (0x3 << 0)
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        0
+#define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH                        0x7
 #define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         (0x7f << 0)
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       8
+#define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH                       0xb
 #define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        (0x7ff << 8)
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_CUSTOM_SHIFT                                   6
+#define OMAP4430_CUSTOM_WIDTH                                   0x2
 #define OMAP4430_CUSTOM_MASK                                    (0x3 << 6)
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_D2D_DYNDEP_SHIFT                               18
+#define OMAP4430_D2D_DYNDEP_WIDTH                               0x1
 #define OMAP4430_D2D_DYNDEP_MASK                                (1 << 18)
 /* Used by CM_MPU_STATICDEP */
 #define OMAP4430_D2D_STATDEP_SHIFT                              18
+#define OMAP4430_D2D_STATDEP_WIDTH                              0x1
 #define OMAP4430_D2D_STATDEP_MASK                               (1 << 18)
 /* Used by CM_CLKSEL_DPLL_MPU */
 #define OMAP4460_DCC_COUNT_MAX_SHIFT                            24
+#define OMAP4460_DCC_COUNT_MAX_WIDTH                            0x8
 #define OMAP4460_DCC_COUNT_MAX_MASK                             (0xff << 24)
 /* Used by CM_CLKSEL_DPLL_MPU */
@@ -586,22 +714,27 @@
 * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
 */
 #define OMAP4430_DELTAMSTEP_SHIFT                               0
+#define OMAP4430_DELTAMSTEP_WIDTH                               0x14
 #define OMAP4430_DELTAMSTEP_MASK                                (0xfffff << 0)
 /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
 #define OMAP4460_DELTAMSTEP_0_20_SHIFT                          0
+#define OMAP4460_DELTAMSTEP_0_20_WIDTH                          0x15
 #define OMAP4460_DELTAMSTEP_0_20_MASK                           (0x1fffff << 0)
 /* Used by CM_DLL_CTRL */
 #define OMAP4430_DLL_OVERRIDE_SHIFT                             0
+#define OMAP4430_DLL_OVERRIDE_WIDTH                             0x1
 #define OMAP4430_DLL_OVERRIDE_MASK                              (1 << 0)
 /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT                         2
+#define OMAP4430_DLL_OVERRIDE_2_2_WIDTH                         0x1
 #define OMAP4430_DLL_OVERRIDE_2_2_MASK                          (1 << 2)
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DLL_RESET_SHIFT                                3
+#define OMAP4430_DLL_RESET_WIDTH                                0x1
 #define OMAP4430_DLL_RESET_MASK                                 (1 << 3)
 /*
@@ -610,30 +743,37 @@
 * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
 */
 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          23
+#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH                          0x1
 #define OMAP4430_DPLL_BYP_CLKSEL_MASK                           (1 << 23)
 /* Used by CM_CLKDCOLDO_DPLL_USB */
 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 8
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH                 0x1
 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  (1 << 8)
 /* Used by CM_CLKSEL_DPLL_CORE */
 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    20
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH                    0x1
 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     (1 << 20)
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       0
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH                       0x5
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        (0x1f << 0)
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  5
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH                  0x1
 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   (1 << 5)
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 8
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH                 0x1
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  (1 << 8)
 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  10
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH                  0x1
 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   (1 << 10)
 /*
@@ -641,10 +781,12 @@
 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
 */
 #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          0
+#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH                          0x5
 #define OMAP4430_DPLL_CLKOUT_DIV_MASK                           (0x1f << 0)
 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      0
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH                      0x7
 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       (0x7f << 0)
 /*
@@ -652,10 +794,12 @@
 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
 */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     5
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH                     0x1
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      (1 << 5)
 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              7
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH              0x1
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               (1 << 7)
 /*
@@ -663,18 +807,22 @@
 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
 */
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    8
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH                    0x1
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     (1 << 8)
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        8
+#define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH                        0x3
 #define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         (0x7 << 8)
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         11
+#define OMAP4430_DPLL_CORE_M2_DIV_WIDTH                         0x5
 #define OMAP4430_DPLL_CORE_M2_DIV_MASK                          (0x1f << 11)
 /* Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         3
+#define OMAP4430_DPLL_CORE_M5_DIV_WIDTH                         0x5
 #define OMAP4430_DPLL_CORE_M5_DIV_MASK                          (0x1f << 3)
 /*
@@ -683,10 +831,12 @@
 * CM_CLKSEL_DPLL_UNIPRO
 */
 #define OMAP4430_DPLL_DIV_SHIFT                                 0
+#define OMAP4430_DPLL_DIV_WIDTH                                 0x7
 #define OMAP4430_DPLL_DIV_MASK                                  (0x7f << 0)
 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_DIV_0_7_SHIFT                             0
+#define OMAP4430_DPLL_DIV_0_7_WIDTH                             0x8
 #define OMAP4430_DPLL_DIV_0_7_MASK                              (0xff << 0)
 /*
@@ -694,10 +844,12 @@
 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       8
+#define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH                       0x1
 #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        (1 << 8)
 /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   3
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH                   0x1
 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    (1 << 3)
 /*
@@ -706,6 +858,7 @@
 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
 */
 #define OMAP4430_DPLL_EN_SHIFT                                  0
+#define OMAP4430_DPLL_EN_WIDTH                                  0x3
 #define OMAP4430_DPLL_EN_MASK                                   (0x7 << 0)
 /*
@@ -714,6 +867,7 @@
 * CM_CLKMODE_DPLL_UNIPRO
 */
 #define OMAP4430_DPLL_LPMODE_EN_SHIFT                           10
+#define OMAP4430_DPLL_LPMODE_EN_WIDTH                           0x1
 #define OMAP4430_DPLL_LPMODE_EN_MASK                            (1 << 10)
 /*
@@ -722,10 +876,12 @@
 * CM_CLKSEL_DPLL_UNIPRO
 */
 #define OMAP4430_DPLL_MULT_SHIFT                                8
+#define OMAP4430_DPLL_MULT_WIDTH                                0xb
 #define OMAP4430_DPLL_MULT_MASK                                 (0x7ff << 8)
 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_MULT_USB_SHIFT                            8
+#define OMAP4430_DPLL_MULT_USB_WIDTH                            0xc
 #define OMAP4430_DPLL_MULT_USB_MASK                             (0xfff << 8)
 /*
@@ -734,10 +890,12 @@
 * CM_CLKMODE_DPLL_UNIPRO
 */
 #define OMAP4430_DPLL_REGM4XEN_SHIFT                            11
+#define OMAP4430_DPLL_REGM4XEN_WIDTH                            0x1
 #define OMAP4430_DPLL_REGM4XEN_MASK                             (1 << 11)
 /* Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_SD_DIV_SHIFT                              24
+#define OMAP4430_DPLL_SD_DIV_WIDTH                              0x8
 #define OMAP4430_DPLL_SD_DIV_MASK                               (0xff << 24)
 /*
@@ -746,6 +904,7 @@
 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
 */
 #define OMAP4430_DPLL_SSC_ACK_SHIFT                             13
+#define OMAP4430_DPLL_SSC_ACK_WIDTH                             0x1
 #define OMAP4430_DPLL_SSC_ACK_MASK                              (1 << 13)
 /*
@@ -754,6 +913,7 @@
 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
 */
 #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      14
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH                      0x1
 #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       (1 << 14)
 /*
@@ -762,42 +922,52 @@
 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
 */
 #define OMAP4430_DPLL_SSC_EN_SHIFT                              12
+#define OMAP4430_DPLL_SSC_EN_WIDTH                              0x1
 #define OMAP4430_DPLL_SSC_EN_MASK                               (1 << 12)
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_DSS_DYNDEP_SHIFT                               8
+#define OMAP4430_DSS_DYNDEP_WIDTH                               0x1
 #define OMAP4430_DSS_DYNDEP_MASK                                (1 << 8)
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
 #define OMAP4430_DSS_STATDEP_SHIFT                              8
+#define OMAP4430_DSS_STATDEP_WIDTH                              0x1
 #define OMAP4430_DSS_STATDEP_MASK                               (1 << 8)
 /* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_DUCATI_DYNDEP_SHIFT                            0
+#define OMAP4430_DUCATI_DYNDEP_WIDTH                            0x1
 #define OMAP4430_DUCATI_DYNDEP_MASK                             (1 << 0)
 /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
 #define OMAP4430_DUCATI_STATDEP_SHIFT                           0
+#define OMAP4430_DUCATI_STATDEP_WIDTH                           0x1
 #define OMAP4430_DUCATI_STATDEP_MASK                            (1 << 0)
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_FREQ_UPDATE_SHIFT                              0
+#define OMAP4430_FREQ_UPDATE_WIDTH                              0x1
 #define OMAP4430_FREQ_UPDATE_MASK                               (1 << 0)
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_FUNC_SHIFT                                     16
+#define OMAP4430_FUNC_WIDTH                                     0xc
 #define OMAP4430_FUNC_MASK                                      (0xfff << 16)
 /* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_GFX_DYNDEP_SHIFT                               10
+#define OMAP4430_GFX_DYNDEP_WIDTH                               0x1
 #define OMAP4430_GFX_DYNDEP_MASK                                (1 << 10)
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_GFX_STATDEP_SHIFT                              10
+#define OMAP4430_GFX_STATDEP_WIDTH                              0x1
 #define OMAP4430_GFX_STATDEP_MASK                               (1 << 10)
 /* Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         0
+#define OMAP4430_GPMC_FREQ_UPDATE_WIDTH                         0x1
 #define OMAP4430_GPMC_FREQ_UPDATE_MASK                          (1 << 0)
 /*
@@ -805,6 +975,7 @@
 * CM_DIV_M4_DPLL_PER
 */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     (0x1f << 0)
 /*
@@ -812,6 +983,7 @@
 * CM_DIV_M4_DPLL_PER
 */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                (1 << 5)
 /*
@@ -819,6 +991,7 @@
 * CM_DIV_M4_DPLL_PER
 */
 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               (1 << 8)
 /*
@@ -826,6 +999,7 @@
 * CM_DIV_M4_DPLL_PER
 */
 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    (1 << 12)
 /*
@@ -833,6 +1007,7 @@
 * CM_DIV_M5_DPLL_PER
 */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     (0x1f << 0)
 /*
@@ -840,6 +1015,7 @@
 * CM_DIV_M5_DPLL_PER
 */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                (1 << 5)
 /*
@@ -847,6 +1023,7 @@
 * CM_DIV_M5_DPLL_PER
 */
 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               (1 << 8)
 /*
@@ -854,38 +1031,47 @@
 * CM_DIV_M5_DPLL_PER
 */
 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    (1 << 12)
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     (0x1f << 0)
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                (1 << 5)
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               (1 << 8)
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    (1 << 12)
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     (0x1f << 0)
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                (1 << 5)
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               (1 << 8)
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    (1 << 12)
 /*
@@ -893,53 +1079,48 @@
 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
 * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
- * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
+ * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
- * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
- * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
+ * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
- * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
+ * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
- * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
- * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
- * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
- * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
- * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
+ * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
- * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
- * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
- * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
- * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
- * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
+ * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
- * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
+ * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
- * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
+ * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
- * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
- * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
+ * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
- * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
+ * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
- * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
- * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
+ * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
- * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
- * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
 * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
- * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
 * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
- * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
- * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
+ * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
- * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
+ * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
 */
 #define OMAP4430_IDLEST_SHIFT                                   16
+#define OMAP4430_IDLEST_WIDTH                                   0x2
 #define OMAP4430_IDLEST_MASK                                    (0x3 << 16)
 /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_ISS_DYNDEP_SHIFT                               9
+#define OMAP4430_ISS_DYNDEP_WIDTH                               0x1
 #define OMAP4430_ISS_DYNDEP_MASK                                (1 << 9)
 /*
@@ -947,10 +1128,12 @@
 * CM_TESLA_STATICDEP
 */
 #define OMAP4430_ISS_STATDEP_SHIFT                              9
+#define OMAP4430_ISS_STATDEP_WIDTH                              0x1
 #define OMAP4430_ISS_STATDEP_MASK                               (1 << 9)
 /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
 #define OMAP4430_IVAHD_DYNDEP_SHIFT                             2
+#define OMAP4430_IVAHD_DYNDEP_WIDTH                             0x1
 #define OMAP4430_IVAHD_DYNDEP_MASK                              (1 << 2)
 /*
@@ -959,10 +1142,12 @@
 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
 #define OMAP4430_IVAHD_STATDEP_SHIFT                            2
+#define OMAP4430_IVAHD_STATDEP_WIDTH                            0x1
 #define OMAP4430_IVAHD_STATDEP_MASK                             (1 << 2)
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_L3INIT_DYNDEP_SHIFT                            7
+#define OMAP4430_L3INIT_DYNDEP_WIDTH                            0x1
 #define OMAP4430_L3INIT_DYNDEP_MASK                             (1 << 7)
 /*
@@ -970,6 +1155,7 @@
 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
 #define OMAP4430_L3INIT_STATDEP_SHIFT                           7
+#define OMAP4430_L3INIT_STATDEP_WIDTH                           0x1
 #define OMAP4430_L3INIT_STATDEP_MASK                            (1 << 7)
 /*
@@ -977,6 +1163,7 @@
 * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
 */
 #define OMAP4430_L3_1_DYNDEP_SHIFT                              5
+#define OMAP4430_L3_1_DYNDEP_WIDTH                              0x1
 #define OMAP4430_L3_1_DYNDEP_MASK                               (1 << 5)
 /*
@@ -986,6 +1173,7 @@
 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
 #define OMAP4430_L3_1_STATDEP_SHIFT                             5
+#define OMAP4430_L3_1_STATDEP_WIDTH                             0x1
 #define OMAP4430_L3_1_STATDEP_MASK                              (1 << 5)
 /*
@@ -995,6 +1183,7 @@
 * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
 */
 #define OMAP4430_L3_2_DYNDEP_SHIFT                              6
+#define OMAP4430_L3_2_DYNDEP_WIDTH                              0x1
 #define OMAP4430_L3_2_DYNDEP_MASK                               (1 << 6)
 /*
@@ -1004,10 +1193,12 @@
 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
 #define OMAP4430_L3_2_STATDEP_SHIFT                             6
+#define OMAP4430_L3_2_STATDEP_WIDTH                             0x1
 #define OMAP4430_L3_2_STATDEP_MASK                              (1 << 6)
 /* Used by CM_L3_1_DYNAMICDEP */
 #define OMAP4430_L4CFG_DYNDEP_SHIFT                             12
+#define OMAP4430_L4CFG_DYNDEP_WIDTH                             0x1
 #define OMAP4430_L4CFG_DYNDEP_MASK                              (1 << 12)
 /*
@@ -1015,10 +1206,12 @@
 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
 #define OMAP4430_L4CFG_STATDEP_SHIFT                            12
+#define OMAP4430_L4CFG_STATDEP_WIDTH                            0x1
 #define OMAP4430_L4CFG_STATDEP_MASK                             (1 << 12)
 /* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_L4PER_DYNDEP_SHIFT                             13
+#define OMAP4430_L4PER_DYNDEP_WIDTH                             0x1
 #define OMAP4430_L4PER_DYNDEP_MASK                              (1 << 13)
 /*
@@ -1026,10 +1219,12 @@
 * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
 #define OMAP4430_L4PER_STATDEP_SHIFT                            13
+#define OMAP4430_L4PER_STATDEP_WIDTH                            0x1
 #define OMAP4430_L4PER_STATDEP_MASK                             (1 << 13)
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_L4SEC_DYNDEP_SHIFT                             14
+#define OMAP4430_L4SEC_DYNDEP_WIDTH                             0x1
 #define OMAP4430_L4SEC_DYNDEP_MASK                              (1 << 14)
 /*
@@ -1037,10 +1232,12 @@
 * CM_SDMA_STATICDEP
 */
 #define OMAP4430_L4SEC_STATDEP_SHIFT                            14
+#define OMAP4430_L4SEC_STATDEP_WIDTH                            0x1
 #define OMAP4430_L4SEC_STATDEP_MASK                             (1 << 14)
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_L4WKUP_DYNDEP_SHIFT                            15
+#define OMAP4430_L4WKUP_DYNDEP_WIDTH                            0x1
 #define OMAP4430_L4WKUP_DYNDEP_MASK                             (1 << 15)
 /*
@@ -1048,6 +1245,7 @@
 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
 #define OMAP4430_L4WKUP_STATDEP_SHIFT                           15
+#define OMAP4430_L4WKUP_STATDEP_WIDTH                           0x1
 #define OMAP4430_L4WKUP_STATDEP_MASK                            (1 << 15)
 /*
@@ -1055,6 +1253,7 @@
 * CM_MPU_DYNAMICDEP
 */
 #define OMAP4430_MEMIF_DYNDEP_SHIFT                             4
+#define OMAP4430_MEMIF_DYNDEP_WIDTH                             0x1
 #define OMAP4430_MEMIF_DYNDEP_MASK                              (1 << 4)
 /*
@@ -1064,6 +1263,7 @@
 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
 #define OMAP4430_MEMIF_STATDEP_SHIFT                            4
+#define OMAP4430_MEMIF_STATDEP_WIDTH                            0x1
 #define OMAP4430_MEMIF_STATDEP_MASK                             (1 << 4)
 /*
@@ -1073,6 +1273,7 @@
 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
 */
 #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      8
+#define OMAP4430_MODFREQDIV_EXPONENT_WIDTH                      0x3
 #define OMAP4430_MODFREQDIV_EXPONENT_MASK                       (0x7 << 8)
 /*
@@ -1082,6 +1283,7 @@
 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
 */
 #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      0
+#define OMAP4430_MODFREQDIV_MANTISSA_WIDTH                      0x7
 #define OMAP4430_MODFREQDIV_MANTISSA_MASK                       (0x7f << 0)
 /*
@@ -1089,69 +1291,68 @@
 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
 * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
- * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
+ * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
- * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
- * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
+ * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
- * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
+ * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
- * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
- * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
- * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
- * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
- * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
+ * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
- * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
- * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
- * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
- * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
- * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
+ * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
- * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
+ * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
- * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
+ * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
- * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
- * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
+ * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
- * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
+ * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
- * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
- * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
+ * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
- * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
- * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
 * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
- * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
 * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
- * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
- * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
+ * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
- * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
+ * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
 */
 #define OMAP4430_MODULEMODE_SHIFT                               0
+#define OMAP4430_MODULEMODE_WIDTH                               0x2
 #define OMAP4430_MODULEMODE_MASK                                (0x3 << 0)
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4460_MPU_DYNDEP_SHIFT                               19
+#define OMAP4460_MPU_DYNDEP_WIDTH                               0x1
 #define OMAP4460_MPU_DYNDEP_MASK                                (1 << 19)
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      9
+#define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH                      0x1
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       (1 << 9)
 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       8
+#define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH                       0x1
 #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        (1 << 8)
 /* Used by CM_ALWON_USBPHY_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         8
+#define OMAP4430_OPTFCLKEN_CLK32K_WIDTH                         0x1
 #define OMAP4430_OPTFCLKEN_CLK32K_MASK                          (1 << 8)
 /* Used by CM_CAM_ISS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        8
+#define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         (1 << 8)
 /*
@@ -1160,126 +1361,157 @@
 * CM_WKUP_GPIO1_CLKCTRL
 */
 #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          8
+#define OMAP4430_OPTFCLKEN_DBCLK_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_DBCLK_MASK                           (1 << 8)
 /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        8
+#define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         (1 << 8)
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         8
+#define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH                         0x1
 #define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          (1 << 8)
 /* Used by CM_WKUP_USIM_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK_SHIFT                           8
+#define OMAP4430_OPTFCLKEN_FCLK_WIDTH                           0x1
 #define OMAP4430_OPTFCLKEN_FCLK_MASK                            (1 << 8)
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          8
+#define OMAP4430_OPTFCLKEN_FCLK0_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_FCLK0_MASK                           (1 << 8)
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          9
+#define OMAP4430_OPTFCLKEN_FCLK1_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_FCLK1_MASK                           (1 << 9)
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          10
+#define OMAP4430_OPTFCLKEN_FCLK2_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_FCLK2_MASK                           (1 << 10)
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     15
+#define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH                     0x1
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      (1 << 15)
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                13
+#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH                0x1
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 (1 << 13)
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                14
+#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH                0x1
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 (1 << 14)
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 11
+#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH                 0x1
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  (1 << 11)
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 12
+#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH                 0x1
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  (1 << 12)
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  8
+#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH                  0x1
 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   (1 << 8)
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                9
+#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH                0x1
 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 (1 << 9)
 /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        8
+#define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         (1 << 8)
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    10
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     (1 << 10)
 /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              11
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH              0x1
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               (1 << 11)
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        10
+#define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         (1 << 10)
 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
 #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT                        8
+#define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH                        0x1
 #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK                         (1 << 8)
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         11
+#define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH                         0x1
 #define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          (1 << 11)
 /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       8
+#define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH                       0x1
 #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        (1 << 8)
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    8
+#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     (1 << 8)
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    9
+#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     (1 << 9)
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    10
+#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     (1 << 10)
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    8
+#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     (1 << 8)
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    9
+#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     (1 << 9)
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    10
+#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     (1 << 10)
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           8
+#define OMAP4430_OPTFCLKEN_XCLK_WIDTH                           0x1
 #define OMAP4430_OPTFCLKEN_XCLK_MASK                            (1 << 8)
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_OVERRIDE_ENABLE_SHIFT                          19
+#define OMAP4430_OVERRIDE_ENABLE_WIDTH                          0x1
 #define OMAP4430_OVERRIDE_ENABLE_MASK                           (1 << 19)
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_PAD_CLKS_GATE_SHIFT                            8
+#define OMAP4430_PAD_CLKS_GATE_WIDTH                            0x1
 #define OMAP4430_PAD_CLKS_GATE_MASK                             (1 << 8)
 /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
 #define OMAP4430_PERF_CURRENT_SHIFT                             0
+#define OMAP4430_PERF_CURRENT_WIDTH                             0x8
 #define OMAP4430_PERF_CURRENT_MASK                              (0xff << 0)
 /*
@@ -1288,74 +1520,85 @@
 * CM_IVA_DVFS_PERF_TESLA
 */
 #define OMAP4430_PERF_REQ_SHIFT                                 0
+#define OMAP4430_PERF_REQ_WIDTH                                 0x8
 #define OMAP4430_PERF_REQ_MASK                                  (0xff << 0)
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE1_COMPLETED_SHIFT                         0
+#define OMAP4430_PHASE1_COMPLETED_WIDTH                         0x1
 #define OMAP4430_PHASE1_COMPLETED_MASK                          (1 << 0)
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE2A_COMPLETED_SHIFT                        1
+#define OMAP4430_PHASE2A_COMPLETED_WIDTH                        0x1
 #define OMAP4430_PHASE2A_COMPLETED_MASK                         (1 << 1)
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE2B_COMPLETED_SHIFT                        2
+#define OMAP4430_PHASE2B_COMPLETED_WIDTH                        0x1
 #define OMAP4430_PHASE2B_COMPLETED_MASK                         (1 << 2)
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         20
+#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH                         0x2
 #define OMAP4430_PMD_STM_MUX_CTRL_MASK                          (0x3 << 20)
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       22
+#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH                       0x2
 #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        (0x3 << 22)
 /* Used by CM_DYN_DEP_PRESCAL */
 #define OMAP4430_PRESCAL_SHIFT                                  0
+#define OMAP4430_PRESCAL_WIDTH                                  0x6
 #define OMAP4430_PRESCAL_MASK                                   (0x3f << 0)
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_R_RTL_SHIFT                                    11
+#define OMAP4430_R_RTL_WIDTH                                    0x5
 #define OMAP4430_R_RTL_MASK                                     (0x1f << 11)
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_SAR_MODE_SHIFT                                 4
+#define OMAP4430_SAR_MODE_WIDTH                                 0x1
 #define OMAP4430_SAR_MODE_MASK                                  (1 << 4)
 /* Used by CM_SCALE_FCLK */
 #define OMAP4430_SCALE_FCLK_SHIFT                               0
+#define OMAP4430_SCALE_FCLK_WIDTH                               0x1
 #define OMAP4430_SCALE_FCLK_MASK                                (1 << 0)
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_SCHEME_SHIFT                                   30
+#define OMAP4430_SCHEME_WIDTH                                   0x2
 #define OMAP4430_SCHEME_MASK                                    (0x3 << 30)
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_SDMA_DYNDEP_SHIFT                              11
+#define OMAP4430_SDMA_DYNDEP_WIDTH                              0x1
 #define OMAP4430_SDMA_DYNDEP_MASK                               (1 << 11)
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_SDMA_STATDEP_SHIFT                             11
+#define OMAP4430_SDMA_STATDEP_WIDTH                             0x1
 #define OMAP4430_SDMA_STATDEP_MASK                              (1 << 11)
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         10
+#define OMAP4430_SLIMBUS_CLK_GATE_WIDTH                         0x1
 #define OMAP4430_SLIMBUS_CLK_GATE_MASK                          (1 << 10)
 /*
 * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
- * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
+ * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
- * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
- * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
- * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
- * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
- * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
- * CM_TESLA_TESLA_CLKCTRL
 */
 #define OMAP4430_STBYST_SHIFT                                   18
+#define OMAP4430_STBYST_WIDTH                                   0x1
 #define OMAP4430_STBYST_MASK                                    (1 << 18)
 /*
@@ -1364,10 +1607,12 @@
 * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
 */
 #define OMAP4430_ST_DPLL_CLK_SHIFT                              0
+#define OMAP4430_ST_DPLL_CLK_WIDTH                              0x1
 #define OMAP4430_ST_DPLL_CLK_MASK                               (1 << 0)
 /* Used by CM_CLKDCOLDO_DPLL_USB */
 #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        9
+#define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH                        0x1
 #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         (1 << 9)
 /*
@@ -1375,14 +1620,17 @@
 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
 */
 #define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           9
+#define OMAP4430_ST_DPLL_CLKOUT_WIDTH                           0x1
 #define OMAP4430_ST_DPLL_CLKOUT_MASK                            (1 << 9)
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        9
+#define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH                        0x1
 #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         (1 << 9)
 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         11
+#define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH                         0x1
 #define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          (1 << 11)
 /*
@@ -1390,6 +1638,7 @@
 * CM_DIV_M4_DPLL_PER
 */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      (1 << 9)
 /*
@@ -1397,14 +1646,17 @@
 * CM_DIV_M5_DPLL_PER
 */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      (1 << 9)
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      (1 << 9)
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      (1 << 9)
 /*
@@ -1413,18 +1665,22 @@
 * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
 */
 #define OMAP4430_ST_MN_BYPASS_SHIFT                             8
+#define OMAP4430_ST_MN_BYPASS_WIDTH                             0x1
 #define OMAP4430_ST_MN_BYPASS_MASK                              (1 << 8)
 /* Used by CM_SYS_CLKSEL */
 #define OMAP4430_SYS_CLKSEL_SHIFT                               0
+#define OMAP4430_SYS_CLKSEL_WIDTH                               0x3
 #define OMAP4430_SYS_CLKSEL_MASK                                (0x7 << 0)
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_TESLA_DYNDEP_SHIFT                             1
+#define OMAP4430_TESLA_DYNDEP_WIDTH                             0x1
 #define OMAP4430_TESLA_DYNDEP_MASK                              (1 << 1)
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_TESLA_STATDEP_SHIFT                            1
+#define OMAP4430_TESLA_STATDEP_WIDTH                            0x1
 #define OMAP4430_TESLA_STATDEP_MASK                             (1 << 1)
 /*
@@ -1433,13 +1689,16 @@
 * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
 */
 #define OMAP4430_WINDOWSIZE_SHIFT                               24
+#define OMAP4430_WINDOWSIZE_WIDTH                               0x4
 #define OMAP4430_WINDOWSIZE_MASK                                (0xf << 24)
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_X_MAJOR_SHIFT                                  8
+#define OMAP4430_X_MAJOR_WIDTH                                  0x3
 #define OMAP4430_X_MAJOR_MASK                                   (0x7 << 8)
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_Y_MINOR_SHIFT                                  0
+#define OMAP4430_Y_MINOR_WIDTH                                  0x6
 #define OMAP4430_Y_MINOR_MASK                                   (0x3f << 0)
 #endif
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 389f9f8b570c..7f07ab02a5b3 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -18,8 +18,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/hardware.h>
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "cm.h"
@@ -36,7 +35,7 @@
 #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP           0x3
 static const u8 cm_idlest_offs[] = {
-        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
+        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
 };
 u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index 088bbad73db5..57b2f3c2fbf3 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -71,6 +71,7 @@
 #define OMAP24XX_CM_FCLKEN2                             0x0004
 #define OMAP24XX_CM_ICLKEN4                             0x001c
 #define OMAP24XX_CM_AUTOIDLE4                           0x003c
+#define OMAP24XX_CM_IDLEST4                             0x002c
 #define OMAP2430_CM_IDLEST3                             0x0028
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index c1875862679f..48daac2581b4 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -24,9 +24,10 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
+#include "common.h"
 #include "common-board-devices.h"
 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
@@ -119,8 +120,7 @@ void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
        }
        if (nandcs > GPMC_CS_NUM) {
-                printk(KERN_INFO "NAND: Unable to find configuration "
+                pr_info("NAND: Unable to find configuration in GPMC\n");
-                                 "in GPMC\n ");
                return;
        }
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 069f9725b1c3..17950c6e130b 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -17,11 +17,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/hardware.h>
-#include <plat/board.h>
-#include <plat/mux.h>
 #include <plat/clock.h>
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 1f65b1871c23..7045e4d61ac3 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -26,11 +26,18 @@
 #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
 #ifndef __ASSEMBLER__
+#include <linux/irq.h>
 #include <linux/delay.h>
 #include <linux/i2c/twl.h>
-#include <plat/common.h>
 #include <asm/proc-fns.h>
+#include <plat/cpu.h>
+#include <plat/serial.h>
+#include <plat/common.h>
+#define OMAP_INTC_START         NR_IRQS
 #ifdef CONFIG_SOC_OMAP2420
 extern void omap242x_map_common_io(void);
 #else
@@ -278,6 +285,11 @@ extern void omap_secondary_startup(void);
 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
 extern void omap_auxcoreboot_addr(u32 cpu_addr);
 extern u32 omap_read_auxcoreboot0(void);
+extern void omap4_cpu_die(unsigned int cpu);
+extern struct smp_operations omap4_smp_ops;
 extern void omap5_secondary_startup(void);
 #endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 3223b81e7532..d1ff8399a222 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -15,9 +15,9 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <plat/hardware.h>
 #include <plat/sdrc.h>
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b8cdc8531b60..a89e8256fd0e 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -16,12 +16,12 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
-#include <mach/ctrl_module_core_44xx.h>
+#include "ctrl_module_core_44xx.h"
-#include <mach/ctrl_module_wkup_44xx.h>
+#include "ctrl_module_wkup_44xx.h"
-#include <mach/ctrl_module_pad_core_44xx.h>
+#include "ctrl_module_pad_core_44xx.h"
-#include <mach/ctrl_module_pad_wkup_44xx.h>
+#include "ctrl_module_pad_wkup_44xx.h"
-#include <plat/am33xx.h>
+#include "am33xx.h"
 #ifndef __ASSEMBLY__
 #define OMAP242X_CTRL_REGADDR(reg)                                      \
@@ -354,6 +354,7 @@
 /* AM33XX CONTROL_STATUS bitfields (partial) */
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT            22
+#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH            0x2
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK             (0x3 << 22)
 /* CONTROL OMAP STATUS register to identify OMAP3 features */
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index f2a49a48ef59..bc2756959be5 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -28,7 +28,6 @@
 #include <linux/cpu_pm.h>
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_core_44xx.h
index 01970824e0e5..01970824e0e5 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
+++ b/arch/arm/mach-omap2/ctrl_module_core_44xx.h
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h
index c88420de1151..c88420de1151 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
+++ b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h
index 17c9b37042c0..17c9b37042c0 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
+++ b/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/ctrl_module_wkup_44xx.h
index a0af9baec3f7..a0af9baec3f7 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
+++ b/arch/arm/mach-omap2/ctrl_module_wkup_44xx.h
diff --git a/arch/arm/mach-omap2/debug-devices.h b/arch/arm/mach-omap2/debug-devices.h
new file mode 100644
index 000000000000..a4edbd2f7484
--- /dev/null
+++ b/arch/arm/mach-omap2/debug-devices.h
@@ -0,0 +1,9 @@
+#ifndef _OMAP_DEBUG_DEVICES_H
+#define _OMAP_DEBUG_DEVICES_H
+#include <linux/types.h>
+/* for TI reference platforms sharing the same debug card */
+extern int debug_card_init(u32 addr, unsigned gpio);
+#endif
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index c00c68961bb8..c8c211731d26 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -17,21 +17,20 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/of.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_data/omap4-keypad.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
-#include <asm/pmu.h>
 #include "iomap.h"
-#include <plat/board.h>
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
-#include <plat/omap4-keypad.h>
+#include "omap4-keypad.h"
+#include "soc.h"
+#include "common.h"
 #include "mux.h"
 #include "control.h"
 #include "devices.h"
@@ -112,7 +111,7 @@ static struct resource omap2cam_resources[] = {
                .flags          = IORESOURCE_MEM,
        },
        {
-                .start          = INT_24XX_CAM_IRQ,
+                .start          = 24 + OMAP_INTC_START,
                .flags          = IORESOURCE_IRQ,
        }
 };
@@ -201,7 +200,7 @@ static struct resource omap3isp_resources[] = {
                .flags          = IORESOURCE_MEM,
        },
        {
-                .start          = INT_34XX_CAM_IRQ,
+                .start          = 24 + OMAP_INTC_START,
                .flags          = IORESOURCE_IRQ,
        }
 };
@@ -385,7 +384,7 @@ static inline void omap_init_hdmi_audio(void) {}
 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused)
 {
@@ -434,37 +433,24 @@ static void omap_init_mcspi(void)
 static inline void omap_init_mcspi(void) {}
 #endif
-static struct resource omap2_pmu_resource = {
+/**
-        .start  = 3,
+ * omap_init_rng - bind the RNG hwmod to the RNG omap_device
-        .end    = 3,
+ *
-        .flags  = IORESOURCE_IRQ,
+ * Bind the RNG hwmod to the RNG omap_device.  No return value.
-};
+ */
+static void omap_init_rng(void)
-static struct resource omap3_pmu_resource = {
-        .start  = INT_34XX_BENCH_MPU_EMUL,
-        .end    = INT_34XX_BENCH_MPU_EMUL,
-        .flags  = IORESOURCE_IRQ,
-};
-static struct platform_device omap_pmu_device = {
-        .name           = "arm-pmu",
-        .id             = ARM_PMU_DEVICE_CPU,
-        .num_resources  = 1,
-};
-static void omap_init_pmu(void)
 {
-        if (cpu_is_omap24xx())
+        struct omap_hwmod *oh;
-                omap_pmu_device.resource = &omap2_pmu_resource;
+        struct platform_device *pdev;
-        else if (cpu_is_omap34xx())
-                omap_pmu_device.resource = &omap3_pmu_resource;
+        oh = omap_hwmod_lookup("rng");
-        else
+        if (!oh)
                return;
-        platform_device_register(&omap_pmu_device);
+        pdev = omap_device_build("omap_rng", -1, oh, NULL, 0, NULL, 0, 0);
+        WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
 }
 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
 #ifdef CONFIG_ARCH_OMAP2
@@ -475,7 +461,7 @@ static struct resource omap2_sham_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        {
-                .start  = INT_24XX_SHA1MD5,
+                .start  = 51 + OMAP_INTC_START,
                .flags  = IORESOURCE_IRQ,
        }
 };
@@ -493,7 +479,7 @@ static struct resource omap3_sham_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        {
-                .start  = INT_34XX_SHA1MD52_IRQ,
+                .start  = 49 + OMAP_INTC_START,
                .flags  = IORESOURCE_IRQ,
        },
        {
@@ -631,6 +617,10 @@ static inline void omap_init_vout(void) {}
 static int __init omap2_init_devices(void)
 {
+        /* Enable dummy states for those platforms without pinctrl support */
+        if (!of_have_populated_dt())
+                pinctrl_provide_dummies();
        /*
         * please keep these calls, and their implementations above,
         * in alphabetical order so they're easier to sort through.
@@ -645,8 +635,8 @@ static int __init omap2_init_devices(void)
                omap_init_mcpdm();
                omap_init_mcspi();
        }
-        omap_init_pmu();
        omap_init_sti();
+        omap_init_rng();
        omap_init_sham();
        omap_init_aes();
        omap_init_vout();
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index af1ed7d24a1f..1011995f150a 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -76,14 +76,14 @@ struct omap_dss_hwmod_data {
        const int id;
 };
-static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
        { "dss_core", "omapdss_dss", -1 },
        { "dss_dispc", "omapdss_dispc", -1 },
        { "dss_rfbi", "omapdss_rfbi", -1 },
        { "dss_venc", "omapdss_venc", -1 },
 };
-static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
        { "dss_core", "omapdss_dss", -1 },
        { "dss_dispc", "omapdss_dispc", -1 },
        { "dss_rfbi", "omapdss_rfbi", -1 },
@@ -91,11 +91,10 @@ static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
        { "dss_dsi1", "omapdss_dsi", 0 },
 };
-static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
        { "dss_core", "omapdss_dss", -1 },
        { "dss_dispc", "omapdss_dispc", -1 },
        { "dss_rfbi", "omapdss_rfbi", -1 },
-        { "dss_venc", "omapdss_venc", -1 },
        { "dss_dsi1", "omapdss_dsi", 0 },
        { "dss_dsi2", "omapdss_dsi", 1 },
        { "dss_hdmi", "omapdss_hdmi", -1 },
@@ -221,7 +220,7 @@ static struct platform_device *create_dss_pdev(const char *pdev_name,
        ohs[0] = oh;
        od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
-        if (!od) {
+        if (IS_ERR(od)) {
                pr_err("Could not alloc omap_device for %s\n", pdev_name);
                r = -ENOMEM;
                goto err;
@@ -488,7 +487,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
        for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                if (oc->_clk)
-                        clk_enable(oc->_clk);
+                        clk_prepare_enable(oc->_clk);
        dispc_disable_outputs();
@@ -515,7 +514,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
        for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                if (oc->_clk)
-                        clk_disable(oc->_clk);
+                        clk_disable_unprepare(oc->_clk);
        r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index b9c8d2f6a81f..814e1808e158 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -28,9 +28,9 @@
 #include <linux/bitops.h>
 #include <linux/clkdev.h>
-#include <plat/cpu.h>
 #include <plat/clock.h>
+#include "soc.h"
 #include "clock.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
@@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
        const struct dpll_data *dd;
        int i = 0;
        int ret = -EINVAL;
+        const char *clk_name;
        dd = clk->dpll_data;
+        clk_name = __clk_get_name(clk);
        state <<= __ffs(dd->idlest_mask);
@@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
        if (i == MAX_DPLL_WAIT_TRIES) {
                printk(KERN_ERR "clock: %s failed transition to '%s'\n",
-                       clk->name, (state) ? "locked" : "bypassed");
+                       clk_name, (state) ? "locked" : "bypassed");
        } else {
                pr_debug("clock: %s transition to '%s' in %d loops\n",
-                         clk->name, (state) ? "locked" : "bypassed", i);
+                         clk_name, (state) ? "locked" : "bypassed", i);
                ret = 0;
        }
@@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
        unsigned long fint;
        u16 f = 0;
-        fint = clk->dpll_data->clk_ref->rate / n;
+        fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
        pr_debug("clock: fint is %lu\n", fint);
@@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
        u8 state = 1;
        int r = 0;
-        pr_debug("clock: locking DPLL %s\n", clk->name);
+        pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
        dd = clk->dpll_data;
        state <<= __ffs(dd->idlest_mask);
@@ -187,7 +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
                return -EINVAL;
        pr_debug("clock: configuring DPLL %s for low-power bypass\n",
-                 clk->name);
+                 __clk_get_name(clk));
        ai = omap3_dpll_autoidle_read(clk);
@@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
                return -EINVAL;
-        pr_debug("clock: stopping DPLL %s\n", clk->name);
+        pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
        ai = omap3_dpll_autoidle_read(clk);
@@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
 {
        unsigned long fint, clkinp; /* watch out for overflow */
-        clkinp = clk->parent->rate;
+        clkinp = __clk_get_rate(__clk_get_parent(clk));
        fint = (clkinp / n) * m;
        if (fint < 1000000000)
@@ -271,7 +273,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
        unsigned long clkinp, sd; /* watch out for overflow */
        int mod1, mod2;
-        clkinp = clk->parent->rate;
+        clkinp = __clk_get_rate(__clk_get_parent(clk));
        /*
         * target sigma-delta to near 250MHz
@@ -311,7 +313,7 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
         * Set jitter correction. No jitter correction for OMAP4 and 3630
         * since freqsel field is no longer present
         */
-        if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
+        if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
                v = __raw_readl(dd->control_reg);
                v &= ~dd->freqsel_mask;
                v |= freqsel << __ffs(dd->freqsel_mask);
@@ -380,16 +382,19 @@ int omap3_noncore_dpll_enable(struct clk *clk)
 {
        int r;
        struct dpll_data *dd;
+        struct clk *parent;
        dd = clk->dpll_data;
        if (!dd)
                return -EINVAL;
-        if (clk->rate == dd->clk_bypass->rate) {
+        parent = __clk_get_parent(clk);
-                WARN_ON(clk->parent != dd->clk_bypass);
+        if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
+                WARN_ON(parent != dd->clk_bypass);
                r = _omap3_noncore_dpll_bypass(clk);
        } else {
-                WARN_ON(clk->parent != dd->clk_ref);
+                WARN_ON(parent != dd->clk_ref);
                r = _omap3_noncore_dpll_lock(clk);
        }
        /*
@@ -432,7 +437,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 {
        struct clk *new_parent = NULL;
-        unsigned long hw_rate;
+        unsigned long hw_rate, bypass_rate;
        u16 freqsel = 0;
        struct dpll_data *dd;
        int ret;
@@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
        omap2_clk_enable(dd->clk_bypass);
        omap2_clk_enable(dd->clk_ref);
-        if (dd->clk_bypass->rate == rate &&
+        bypass_rate = __clk_get_rate(dd->clk_bypass);
+        if (bypass_rate == rate &&
            (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
                pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
@@ -471,7 +477,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
                        return -EINVAL;
                /* No freqsel on OMAP4 and OMAP3630 */
-                if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
+                if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
                        freqsel = _omap3_dpll_compute_freqsel(clk,
                                                dd->last_rounded_n);
                        if (!freqsel)
@@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
                }
                pr_debug("clock: %s: set rate: locking rate to %lu.\n",
-                         clk->name, rate);
+                         __clk_get_name(clk), rate);
                ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
                                                 dd->last_rounded_n, freqsel);
@@ -557,7 +563,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
        if (!dd->autoidle_reg) {
                pr_debug("clock: DPLL %s: autoidle not supported\n",
-                        clk->name);
+                        __clk_get_name(clk));
                return;
        }
@@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk)
        if (!dd->autoidle_reg) {
                pr_debug("clock: DPLL %s: autoidle not supported\n",
-                        clk->name);
+                        __clk_get_name(clk));
                return;
        }
@@ -617,25 +623,30 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
        unsigned long rate;
        u32 v;
        struct clk *pclk;
+        unsigned long parent_rate;
        /* Walk up the parents of clk, looking for a DPLL */
-        pclk = clk->parent;
+        pclk = __clk_get_parent(clk);
        while (pclk && !pclk->dpll_data)
-                pclk = pclk->parent;
+                pclk = __clk_get_parent(pclk);
-        /* clk does not have a DPLL as a parent? */
+        /* clk does not have a DPLL as a parent?  error in the clock data */
-        WARN_ON(!pclk);
+        if (!pclk) {
+                WARN_ON(1);
+                return 0;
+        }
        dd = pclk->dpll_data;
        WARN_ON(!dd->enable_mask);
+        parent_rate = __clk_get_rate(__clk_get_parent(clk));
        v = __raw_readl(dd->control_reg) & dd->enable_mask;
        v >>= __ffs(dd->enable_mask);
        if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
-                rate = clk->parent->rate;
+                rate = parent_rate;
        else
-                rate = clk->parent->rate * 2;
+                rate = parent_rate * 2;
        return rate;
 }
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 9c6a296b3dc3..09d0ccccb861 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -15,9 +15,9 @@
 #include <linux/io.h>
 #include <linux/bitops.h>
-#include <plat/cpu.h>
 #include <plat/clock.h>
+#include "soc.h"
 #include "clock.h"
 #include "clock44xx.h"
 #include "cm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index a636ebc16b39..98388109f22a 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -30,7 +30,7 @@
 #include <plat/omap-pm.h>
 #endif
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 static struct platform_device *omap_dsp_pdev;
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
index e28e761b7ab9..b3566f68a559 100644
--- a/arch/arm/mach-omap2/emu.c
+++ b/arch/arm/mach-omap2/emu.c
@@ -21,8 +21,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
-#include <mach/hardware.h>
+#include "soc.h"
 #include "iomap.h"
 MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 9ad7d489b0de..d1058f16fb40 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -21,6 +21,7 @@
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/of.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
@@ -60,6 +61,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
        pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
        if (!pdata->regs) {
                pr_err("gpio%d: Memory allocation failed\n", id);
+                kfree(pdata);
                return -ENOMEM;
        }
@@ -121,6 +123,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                break;
        default:
                WARN(1, "Invalid gpio bank_type\n");
+                kfree(pdata->regs);
                kfree(pdata);
                return -EINVAL;
        }
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 386dec8d2351..4acf497faeb3 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -13,23 +13,31 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/mtd/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <asm/mach/flash.h>
-#include <plat/cpu.h>
-#include <plat/nand.h>
-#include <plat/board.h>
 #include <plat/gpmc.h>
-static struct resource gpmc_nand_resource = {
+#include "soc.h"
-        .flags          = IORESOURCE_MEM,
+static struct resource gpmc_nand_resource[] = {
+        {
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .flags          = IORESOURCE_IRQ,
+        },
 };
 static struct platform_device gpmc_nand_device = {
        .name           = "omap2-nand",
        .id             = 0,
-        .num_resources  = 1,
+        .num_resources  = ARRAY_SIZE(gpmc_nand_resource),
-        .resource       = &gpmc_nand_resource,
+        .resource       = gpmc_nand_resource,
 };
 static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data)
@@ -75,6 +83,7 @@ static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data
                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
        gpmc_cs_configure(gpmc_nand_data->cs,
                        GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
+        gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0);
        err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
        if (err)
                return err;
@@ -90,12 +99,19 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
        gpmc_nand_device.dev.platform_data = gpmc_nand_data;
        err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
-                                &gpmc_nand_data->phys_base);
+                                (unsigned long *)&gpmc_nand_resource[0].start);
        if (err < 0) {
                dev_err(dev, "Cannot request GPMC CS\n");
                return err;
        }
+        gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
+                                                        NAND_IO_SIZE - 1;
+        gpmc_nand_resource[1].start =
+                                gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
+        gpmc_nand_resource[2].start =
+                                gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
         /* Set timings in GPMC */
        err = omap2_nand_gpmc_retime(gpmc_nand_data);
        if (err < 0) {
@@ -108,6 +124,8 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
        }
+        gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
        err = platform_device_register(&gpmc_nand_device);
        if (err < 0) {
                dev_err(dev, "Unable to register NAND device\n");
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index a0fa9bb2bda5..916716e1da3b 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -15,19 +15,27 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/onenand_regs.h>
 #include <linux/io.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <asm/mach/flash.h>
-#include <plat/cpu.h>
-#include <plat/onenand.h>
-#include <plat/board.h>
 #include <plat/gpmc.h>
+#include "soc.h"
+#define ONENAND_IO_SIZE SZ_128K
 static struct omap_onenand_platform_data *gpmc_onenand_data;
+static struct resource gpmc_onenand_resource = {
+        .flags          = IORESOURCE_MEM,
+};
 static struct platform_device gpmc_onenand_device = {
        .name           = "omap2-onenand",
        .id             = -1,
+        .num_resources  = 1,
+        .resource       = &gpmc_onenand_resource,
 };
 static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
@@ -390,6 +398,8 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 {
+        int err;
        gpmc_onenand_data = _onenand_data;
        gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
        gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
@@ -401,8 +411,19 @@ void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
                gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
        }
+        err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
+                                (unsigned long *)&gpmc_onenand_resource.start);
+        if (err < 0) {
+                pr_err("%s: Cannot request GPMC CS\n", __func__);
+                return;
+        }
+        gpmc_onenand_resource.end = gpmc_onenand_resource.start +
+                                                        ONENAND_IO_SIZE - 1;
        if (platform_device_register(&gpmc_onenand_device) < 0) {
-                printk(KERN_ERR "Unable to register OneNAND device\n");
+                pr_err("%s: Unable to register OneNAND device\n", __func__);
+                gpmc_cs_free(gpmc_onenand_data->cs);
                return;
        }
 }
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index ba10c24f3d8d..565475310374 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -17,9 +17,10 @@
 #include <linux/io.h>
 #include <linux/smc91x.h>
-#include <plat/board.h>
 #include <plat/gpmc.h>
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
+#include "soc.h"
 static struct omap_smc91x_platform_data *gpmc_cfg;
diff --git a/arch/arm/plat-omap/include/plat/gpmc-smc91x.h b/arch/arm/mach-omap2/gpmc-smc91x.h
index b64fbee4d567..b64fbee4d567 100644
--- a/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
+++ b/arch/arm/mach-omap2/gpmc-smc91x.h
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index b6c77be3e8f7..249a0b440cd6 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -20,9 +20,8 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
-#include <plat/board.h>
 #include <plat/gpmc.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 static struct resource gpmc_smsc911x_resources[] = {
        [0] = {
diff --git a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h b/arch/arm/mach-omap2/gpmc-smsc911x.h
index ea6c9c88c725..ea6c9c88c725 100644
--- a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.h
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index b2b5759ab0fe..5ac5cf30406a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -24,11 +24,20 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
+#include <linux/platform_device.h>
 #include <asm/mach-types.h>
 #include <plat/gpmc.h>
+#include <plat/cpu.h>
+#include <plat/gpmc.h>
 #include <plat/sdrc.h>
+#include <plat/omap_device.h>
+#include "soc.h"
+#include "common.h"
+#define DEVICE_NAME             "omap-gpmc"
 /* GPMC register offsets */
 #define GPMC_REVISION           0x00
@@ -78,6 +87,21 @@
 #define ENABLE_PREFETCH         (0x1 << 7)
 #define DMA_MPU_MODE            2
+#define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
+#define GPMC_REVISION_MINOR(l)          (l & 0xf)
+#define GPMC_HAS_WR_ACCESS              0x1
+#define GPMC_HAS_WR_DATA_MUX_BUS        0x2
+/* XXX: Only NAND irq has been considered,currently these are the only ones used
+ */
+#define GPMC_NR_IRQ             2
+struct gpmc_client_irq  {
+        unsigned                irq;
+        u32                     bitmask;
+};
 /* Structure to save gpmc cs context */
 struct gpmc_cs_config {
        u32 config1;
@@ -105,12 +129,19 @@ struct omap3_gpmc_regs {
        struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 };
+static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
+static struct irq_chip gpmc_irq_chip;
+static unsigned gpmc_irq_start;
 static struct resource  gpmc_mem_root;
 static struct resource  gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 static unsigned int gpmc_cs_map;        /* flag for cs which are initialized */
 static int gpmc_ecc_used = -EINVAL;     /* cs using ecc engine */
+static struct device *gpmc_dev;
+static int gpmc_irq;
+static resource_size_t phys_base, mem_size;
+static unsigned gpmc_capability;
 static void __iomem *gpmc_base;
 static struct clk *gpmc_l3_clk;
@@ -279,7 +310,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
        div = gpmc_cs_calc_divider(cs, t->sync_clk);
        if (div < 0)
-                return -1;
+                return div;
        GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
        GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
@@ -300,10 +331,10 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
        GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
-        if (cpu_is_omap34xx()) {
+        if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
                GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
+        if (gpmc_capability & GPMC_HAS_WR_ACCESS)
                GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
-        }
        /* caller is expected to have initialized CONFIG1 to cover
         * at least sync vs async
@@ -413,6 +444,20 @@ static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
        return r;
 }
+static int gpmc_cs_delete_mem(int cs)
+{
+        struct resource *res = &gpmc_cs_mem[cs];
+        int r;
+        spin_lock(&gpmc_mem_lock);
+        r = release_resource(&gpmc_cs_mem[cs]);
+        res->start = 0;
+        res->end = 0;
+        spin_unlock(&gpmc_mem_lock);
+        return r;
+}
 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 {
        struct resource *res = &gpmc_cs_mem[cs];
@@ -682,7 +727,148 @@ int gpmc_prefetch_reset(int cs)
 }
 EXPORT_SYMBOL(gpmc_prefetch_reset);
-static void __init gpmc_mem_init(void)
+void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
+{
+        reg->gpmc_status = gpmc_base + GPMC_STATUS;
+        reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
+                                GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
+        reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
+                                GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
+        reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
+                                GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
+        reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
+        reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
+        reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
+        reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
+        reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
+        reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
+        reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
+        reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
+        reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0;
+}
+int gpmc_get_client_irq(unsigned irq_config)
+{
+        int i;
+        if (hweight32(irq_config) > 1)
+                return 0;
+        for (i = 0; i < GPMC_NR_IRQ; i++)
+                if (gpmc_client_irq[i].bitmask & irq_config)
+                        return gpmc_client_irq[i].irq;
+        return 0;
+}
+static int gpmc_irq_endis(unsigned irq, bool endis)
+{
+        int i;
+        u32 regval;
+        for (i = 0; i < GPMC_NR_IRQ; i++)
+                if (irq == gpmc_client_irq[i].irq) {
+                        regval = gpmc_read_reg(GPMC_IRQENABLE);
+                        if (endis)
+                                regval |= gpmc_client_irq[i].bitmask;
+                        else
+                                regval &= ~gpmc_client_irq[i].bitmask;
+                        gpmc_write_reg(GPMC_IRQENABLE, regval);
+                        break;
+                }
+        return 0;
+}
+static void gpmc_irq_disable(struct irq_data *p)
+{
+        gpmc_irq_endis(p->irq, false);
+}
+static void gpmc_irq_enable(struct irq_data *p)
+{
+        gpmc_irq_endis(p->irq, true);
+}
+static void gpmc_irq_noop(struct irq_data *data) { }
+static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
+static int gpmc_setup_irq(void)
+{
+        int i;
+        u32 regval;
+        if (!gpmc_irq)
+                return -EINVAL;
+        gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
+        if (IS_ERR_VALUE(gpmc_irq_start)) {
+                pr_err("irq_alloc_descs failed\n");
+                return gpmc_irq_start;
+        }
+        gpmc_irq_chip.name = "gpmc";
+        gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
+        gpmc_irq_chip.irq_enable = gpmc_irq_enable;
+        gpmc_irq_chip.irq_disable = gpmc_irq_disable;
+        gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
+        gpmc_irq_chip.irq_ack = gpmc_irq_noop;
+        gpmc_irq_chip.irq_mask = gpmc_irq_noop;
+        gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
+        gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
+        gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
+        for (i = 0; i < GPMC_NR_IRQ; i++) {
+                gpmc_client_irq[i].irq = gpmc_irq_start + i;
+                irq_set_chip_and_handler(gpmc_client_irq[i].irq,
+                                        &gpmc_irq_chip, handle_simple_irq);
+                set_irq_flags(gpmc_client_irq[i].irq,
+                                IRQF_VALID | IRQF_NOAUTOEN);
+        }
+        /* Disable interrupts */
+        gpmc_write_reg(GPMC_IRQENABLE, 0);
+        /* clear interrupts */
+        regval = gpmc_read_reg(GPMC_IRQSTATUS);
+        gpmc_write_reg(GPMC_IRQSTATUS, regval);
+        return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
+}
+static __devexit int gpmc_free_irq(void)
+{
+        int i;
+        if (gpmc_irq)
+                free_irq(gpmc_irq, NULL);
+        for (i = 0; i < GPMC_NR_IRQ; i++) {
+                irq_set_handler(gpmc_client_irq[i].irq, NULL);
+                irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
+                irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
+        }
+        irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
+        return 0;
+}
+static void __devexit gpmc_mem_exit(void)
+{
+        int cs;
+        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+                if (!gpmc_cs_mem_enabled(cs))
+                        continue;
+                gpmc_cs_delete_mem(cs);
+        }
+}
+static void __devinit gpmc_mem_init(void)
 {
        int cs;
        unsigned long boot_rom_space = 0;
@@ -709,83 +895,120 @@ static void __init gpmc_mem_init(void)
        }
 }
-static int __init gpmc_init(void)
+static __devinit int gpmc_probe(struct platform_device *pdev)
 {
-        u32 l, irq;
+        u32 l;
-        int cs, ret = -EINVAL;
+        struct resource *res;
-        int gpmc_irq;
-        char *ck = NULL;
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res == NULL)
-        if (cpu_is_omap24xx()) {
+                return -ENOENT;
-                ck = "core_l3_ck";
-                if (cpu_is_omap2420())
+        phys_base = res->start;
-                        l = OMAP2420_GPMC_BASE;
+        mem_size = resource_size(res);
-                else
-                        l = OMAP34XX_GPMC_BASE;
+        gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
-                gpmc_irq = INT_34XX_GPMC_IRQ;
+        if (!gpmc_base) {
-        } else if (cpu_is_omap34xx()) {
+                dev_err(&pdev->dev, "error: request memory / ioremap\n");
-                ck = "gpmc_fck";
+                return -EADDRNOTAVAIL;
-                l = OMAP34XX_GPMC_BASE;
-                gpmc_irq = INT_34XX_GPMC_IRQ;
-        } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
-                /* Base address and irq number are same for OMAP4/5 */
-                ck = "gpmc_ck";
-                l = OMAP44XX_GPMC_BASE;
-                gpmc_irq = OMAP44XX_IRQ_GPMC;
        }
-        if (WARN_ON(!ck))
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-                return ret;
+        if (res == NULL)
+                dev_warn(&pdev->dev, "Failed to get resource: irq\n");
+        else
+                gpmc_irq = res->start;
-        gpmc_l3_clk = clk_get(NULL, ck);
+        gpmc_l3_clk = clk_get(&pdev->dev, "fck");
        if (IS_ERR(gpmc_l3_clk)) {
-                printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
+                dev_err(&pdev->dev, "error: clk_get\n");
-                BUG();
+                gpmc_irq = 0;
+                return PTR_ERR(gpmc_l3_clk);
        }
-        gpmc_base = ioremap(l, SZ_4K);
+        clk_prepare_enable(gpmc_l3_clk);
-        if (!gpmc_base) {
-                clk_put(gpmc_l3_clk);
-                printk(KERN_ERR "Could not get GPMC register memory\n");
-                BUG();
-        }
-        clk_enable(gpmc_l3_clk);
+        gpmc_dev = &pdev->dev;
        l = gpmc_read_reg(GPMC_REVISION);
-        printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
+        if (GPMC_REVISION_MAJOR(l) > 0x4)
-        /* Set smart idle mode and automatic L3 clock gating */
+                gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
-        l = gpmc_read_reg(GPMC_SYSCONFIG);
+        dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
-        l &= 0x03 << 3;
+                 GPMC_REVISION_MINOR(l));
-        l |= (0x02 << 3) | (1 << 0);
-        gpmc_write_reg(GPMC_SYSCONFIG, l);
        gpmc_mem_init();
-        /* initalize the irq_chained */
+        if (IS_ERR_VALUE(gpmc_setup_irq()))
-        irq = OMAP_GPMC_IRQ_BASE;
+                dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
-        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-                irq_set_chip_and_handler(irq, &dummy_irq_chip,
+        return 0;
-                                                handle_simple_irq);
+}
-                set_irq_flags(irq, IRQF_VALID);
-                irq++;
+static __devexit int gpmc_remove(struct platform_device *pdev)
-        }
+{
+        gpmc_free_irq();
+        gpmc_mem_exit();
+        gpmc_dev = NULL;
+        return 0;
+}
+static struct platform_driver gpmc_driver = {
+        .probe          = gpmc_probe,
+        .remove         = __devexit_p(gpmc_remove),
+        .driver         = {
+                .name   = DEVICE_NAME,
+                .owner  = THIS_MODULE,
+        },
+};
-        ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL);
+static __init int gpmc_init(void)
-        if (ret)
+{
-                pr_err("gpmc: irq-%d could not claim: err %d\n",
+        return platform_driver_register(&gpmc_driver);
-                                                gpmc_irq, ret);
-        return ret;
 }
+static __exit void gpmc_exit(void)
+{
+        platform_driver_unregister(&gpmc_driver);
+}
 postcore_initcall(gpmc_init);
+module_exit(gpmc_exit);
+static int __init omap_gpmc_init(void)
+{
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+        char *oh_name = "gpmc";
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up %s\n", oh_name);
+                return -ENODEV;
+        }
+        pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
+        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
+        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+}
+postcore_initcall(omap_gpmc_init);
 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
 {
-        u8 cs;
+        int i;
+        u32 regval;
+        regval = gpmc_read_reg(GPMC_IRQSTATUS);
+        if (!regval)
+                return IRQ_NONE;
+        for (i = 0; i < GPMC_NR_IRQ; i++)
+                if (regval & gpmc_client_irq[i].bitmask)
+                        generic_handle_irq(gpmc_client_irq[i].irq);
-        /* check cs to invoke the irq */
+        gpmc_write_reg(GPMC_IRQSTATUS, regval);
-        cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
-        if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
-                generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
        return IRQ_HANDLED;
 }
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index cdd6dda03828..e003f2bba30c 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -29,7 +29,7 @@
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
-#include <plat/hdq1w.h>
+#include "hdq1w.h"
 #include "common.h"
diff --git a/arch/arm/plat-omap/include/plat/hdq1w.h b/arch/arm/mach-omap2/hdq1w.h
index 0c1efc846d8d..0c1efc846d8d 100644
--- a/arch/arm/plat-omap/include/plat/hdq1w.h
+++ b/arch/arm/mach-omap2/hdq1w.h
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index a9675d8d1822..4d3a6324155f 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -15,9 +15,10 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 #include <mach/hardware.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <plat/mmc.h>
 #include <plat/omap-pm.h>
-#include <plat/mux.h>
 #include <plat/omap_device.h>
 #include "mux.h"
@@ -522,7 +523,7 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
        dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
        od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
-        if (!od) {
+        if (IS_ERR(od)) {
                pr_err("Could not allocate od for %s\n", name);
                goto put_pdev;
        }
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index a12e224eb97d..fc57e67b321f 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -19,7 +19,6 @@
 *
 */
-#include <plat/cpu.h>
 #include <plat/i2c.h>
 #include "common.h"
 #include <plat/omap_hwmod.h>
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 40373db649aa..cf2362ccb234 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -22,10 +22,10 @@
 #include <asm/cputype.h>
 #include "common.h"
-#include <plat/cpu.h>
-#include <mach/id.h>
+#include "id.h"
+#include "soc.h"
 #include "control.h"
 static unsigned int omap_revision;
@@ -161,9 +161,8 @@ void __init omap2xxx_check_revision(void)
        }
        if (j == ARRAY_SIZE(omap_ids)) {
-                printk(KERN_ERR "Unknown OMAP device type. "
+                pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
-                                "Handling it as OMAP%04x\n",
+                       omap_ids[i].type >> 16);
-                                omap_ids[i].type >> 16);
                j = i;
        }
diff --git a/arch/arm/mach-omap2/include/mach/id.h b/arch/arm/mach-omap2/id.h
index 02ed3aa56f1e..02ed3aa56f1e 100644
--- a/arch/arm/mach-omap2/include/mach/id.h
+++ b/arch/arm/mach-omap2/id.h
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h
index 775fdc3b000b..2e9486940ead 100644
--- a/arch/arm/mach-omap2/include/mach/board-zoom.h
+++ b/arch/arm/mach-omap2/include/mach/board-zoom.h
@@ -8,5 +8,3 @@
 extern int __init zoom_debugboard_init(void);
 extern void __init zoom_peripherals_init(void);
 extern void __init zoom_display_init(void);
-#define ZOOM2_HEADSET_EXTMUTE_GPIO      153
diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h
index be4d290d57ee..5621cc59c9f4 100644
--- a/arch/arm/mach-omap2/include/mach/gpio.h
+++ b/arch/arm/mach-omap2/include/mach/gpio.h
@@ -1,5 +1,3 @@
 /*
 * arch/arm/mach-omap2/include/mach/gpio.h
 */
-#include <plat/gpio.h>
diff --git a/arch/arm/mach-omap2/include/mach/hardware.h b/arch/arm/mach-omap2/include/mach/hardware.h
index 78edf9d33f71..54492dbf6973 100644
--- a/arch/arm/mach-omap2/include/mach/hardware.h
+++ b/arch/arm/mach-omap2/include/mach/hardware.h
@@ -1,5 +1,3 @@
 /*
 * arch/arm/mach-omap2/include/mach/hardware.h
 */
-#include <plat/hardware.h>
diff --git a/arch/arm/mach-omap2/include/mach/irqs.h b/arch/arm/mach-omap2/include/mach/irqs.h
index 44dab7725696..ba5282cafa42 100644
--- a/arch/arm/mach-omap2/include/mach/irqs.h
+++ b/arch/arm/mach-omap2/include/mach/irqs.h
@@ -1,5 +1,3 @@
 /*
 * arch/arm/mach-omap2/include/mach/irqs.h
 */
-#include <plat/irqs.h>
diff --git a/arch/arm/mach-omap2/include/mach/smp.h b/arch/arm/mach-omap2/include/mach/smp.h
deleted file mode 100644
index 323675f21b69..000000000000
--- a/arch/arm/mach-omap2/include/mach/smp.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap2/include/mach/smp.h
- */
-#include <plat/smp.h>
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4d2d981ff5c5..4234d28dc171 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -33,6 +33,7 @@
 #include <plat/multi.h>
 #include <plat/dma.h>
+#include "soc.h"
 #include "iomap.h"
 #include "voltage.h"
 #include "powerdomain.h"
@@ -523,6 +524,8 @@ void __init am33xx_init_early(void)
        am33xx_voltagedomains_init();
        am33xx_powerdomains_init();
        am33xx_clockdomains_init();
+        am33xx_hwmod_init();
+        omap_hwmod_init_postsetup();
        am33xx_clk_init();
 }
 #endif
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index bcd83db41bbc..3926f370448f 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -23,8 +23,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
-#include <mach/hardware.h>
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
@@ -49,6 +48,8 @@
 #define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
 #define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
 #define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
+#define INTCPS_NR_MIR_REGS      3
+#define INTCPS_NR_IRQS          96
 /*
 * OMAP2 has a number of different interrupt controllers, each interrupt
@@ -107,9 +108,8 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
        unsigned long tmp;
        tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
-        printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
+        pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
-                         "(revision %ld.%ld) with %d interrupts\n",
+                bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
-                         bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
        tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
        tmp |= 1 << 1;  /* soft reset */
diff --git a/arch/arm/plat-omap/include/plat/l3_2xxx.h b/arch/arm/mach-omap2/l3_2xxx.h
index b8b5641379b0..b8b5641379b0 100644
--- a/arch/arm/plat-omap/include/plat/l3_2xxx.h
+++ b/arch/arm/mach-omap2/l3_2xxx.h
diff --git a/arch/arm/plat-omap/include/plat/l3_3xxx.h b/arch/arm/mach-omap2/l3_3xxx.h
index cde1938c5f82..cde1938c5f82 100644
--- a/arch/arm/plat-omap/include/plat/l3_3xxx.h
+++ b/arch/arm/mach-omap2/l3_3xxx.h
diff --git a/arch/arm/plat-omap/include/plat/l4_2xxx.h b/arch/arm/mach-omap2/l4_2xxx.h
index 3f39cf8a35c6..3f39cf8a35c6 100644
--- a/arch/arm/plat-omap/include/plat/l4_2xxx.h
+++ b/arch/arm/mach-omap2/l4_2xxx.h
diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/mach-omap2/l4_3xxx.h
index 881a858b1ffc..881a858b1ffc 100644
--- a/arch/arm/plat-omap/include/plat/l4_3xxx.h
+++ b/arch/arm/mach-omap2/l4_3xxx.h
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 6875be837d9f..0d974565f8ca 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -16,8 +16,10 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/pm_runtime.h>
 #include <plat/mailbox.h>
-#include <mach/irqs.h>
+#include "soc.h"
 #define MAILBOX_REVISION                0x000
 #define MAILBOX_MESSAGE(m)              (0x040 + 4 * (m))
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 577cb77db26c..37f8f948047b 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -15,18 +15,15 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <mach/irqs.h>
 #include <plat/dma.h>
-#include <plat/cpu.h>
-#include <plat/mcbsp.h>
 #include <plat/omap_device.h>
 #include <linux/pm_runtime.h>
-#include "control.h"
 /*
 * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
 * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
@@ -34,112 +31,6 @@
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
-/* McBSP1 internal signal muxing function for OMAP2/3 */
-static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
-                                   const char *src)
-{
-        u32 v;
-        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-        if (!strcmp(signal, "clkr")) {
-                if (!strcmp(src, "clkr"))
-                        v &= ~OMAP2_MCBSP1_CLKR_MASK;
-                else if (!strcmp(src, "clkx"))
-                        v |= OMAP2_MCBSP1_CLKR_MASK;
-                else
-                        return -EINVAL;
-        } else if (!strcmp(signal, "fsr")) {
-                if (!strcmp(src, "fsr"))
-                        v &= ~OMAP2_MCBSP1_FSR_MASK;
-                else if (!strcmp(src, "fsx"))
-                        v |= OMAP2_MCBSP1_FSR_MASK;
-                else
-                        return -EINVAL;
-        } else {
-                return -EINVAL;
-        }
-        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
-        return 0;
-}
-/* McBSP4 internal signal muxing function for OMAP4 */
-#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX     (1 << 31)
-#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX    (1 << 30)
-static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
-                                   const char *src)
-{
-        u32 v;
-        /*
-         * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
-         * mux) is used */
-        v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
-        if (!strcmp(signal, "clkr")) {
-                if (!strcmp(src, "clkr"))
-                        v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
-                else if (!strcmp(src, "clkx"))
-                        v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
-                else
-                        return -EINVAL;
-        } else if (!strcmp(signal, "fsr")) {
-                if (!strcmp(src, "fsr"))
-                        v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
-                else if (!strcmp(src, "fsx"))
-                        v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
-                else
-                        return -EINVAL;
-        } else {
-                return -EINVAL;
-        }
-        omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
-        return 0;
-}
-/* McBSP CLKS source switching function */
-static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
-                                   const char *src)
-{
-        struct clk *fck_src;
-        char *fck_src_name;
-        int r;
-        if (!strcmp(src, "clks_ext"))
-                fck_src_name = "pad_fck";
-        else if (!strcmp(src, "clks_fclk"))
-                fck_src_name = "prcm_fck";
-        else
-                return -EINVAL;
-        fck_src = clk_get(dev, fck_src_name);
-        if (IS_ERR_OR_NULL(fck_src)) {
-                pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
-                       fck_src_name);
-                return -EINVAL;
-        }
-        pm_runtime_put_sync(dev);
-        r = clk_set_parent(clk, fck_src);
-        if (IS_ERR_VALUE(r)) {
-                pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
-                       "clks", fck_src_name);
-                clk_put(fck_src);
-                return -EINVAL;
-        }
-        pm_runtime_get_sync(dev);
-        clk_put(fck_src);
-        return 0;
-}
 static int omap3_enable_st_clock(unsigned int id, bool enable)
 {
        unsigned int w;
@@ -181,17 +72,11 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
                pdata->reg_size = 4;
                pdata->has_ccr = true;
        }
-        pdata->set_clk_src = omap2_mcbsp_set_clk_src;
-        /* On OMAP2/3 the McBSP1 port has 6 pin configuration */
-        if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
-                pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
-        /* On OMAP4 the McBSP4 port has 6 pin configuration */
+        if (oh->class->rev == MCBSP_CONFIG_TYPE2) {
-        if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
+                /* The FIFO has 128 locations */
-                pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
+                pdata->buffer_size = 0x80;
+        } else if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
-        if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
                if (id == 2)
                        /* The FIFO has 1024 + 256 locations */
                        pdata->buffer_size = 0x500;
@@ -227,7 +112,8 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 static int __init omap2_mcbsp_init(void)
 {
-        omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
+        if (!of_have_populated_dt())
+                omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
        return 0;
 }
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index fb5bc6cf3773..9e57b4aadb06 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -23,6 +23,7 @@
 #include <linux/kernel.h>
 #include <linux/err.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 9fe6829f4c16..701e17cba468 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -486,7 +486,7 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
                default:
                        /* Nothing to be done */
                        break;
-                };
+                }
                if (val >= 0) {
                        omap_mux_write(pad->partition, val,
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 414083b427df..e712d1725a8b 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -20,22 +20,17 @@
 #include <linux/io.h>
 #include <asm/cacheflush.h>
-#include <mach/omap-wakeupgen.h>
+#include "omap-wakeupgen.h"
 #include "common.h"
 #include "powerdomain.h"
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
 /*
 * platform-specific code to shutdown a CPU
 * Called with IRQs disabled
 */
-void __ref platform_cpu_die(unsigned int cpu)
+void __ref omap4_cpu_die(unsigned int cpu)
 {
        unsigned int boot_cpu = 0;
        void __iomem *base = omap_get_wakeupgen_base();
@@ -75,12 +70,3 @@ void __ref platform_cpu_die(unsigned int cpu)
                pr_debug("CPU%u: spurious wakeup call\n", cpu);
        }
 }
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 1be8bcb52e93..df298d46707c 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -14,7 +14,9 @@
 #include <linux/platform_device.h>
 #include <plat/iommu.h>
-#include <plat/irqs.h>
+#include "soc.h"
+#include "common.h"
 struct iommu_device {
        resource_size_t base;
@@ -29,7 +31,7 @@ static int num_iommu_devices;
 static struct iommu_device omap3_devices[] = {
        {
                .base = 0x480bd400,
-                .irq = 24,
+                .irq = 24 + OMAP_INTC_START,
                .pdata = {
                        .name = "isp",
                        .nr_tlb_entries = 8,
@@ -41,7 +43,7 @@ static struct iommu_device omap3_devices[] = {
 #if defined(CONFIG_OMAP_IOMMU_IVA2)
        {
                .base = 0x5d000000,
-                .irq = 28,
+                .irq = 28 + OMAP_INTC_START,
                .pdata = {
                        .name = "iva2",
                        .nr_tlb_entries = 32,
@@ -64,7 +66,7 @@ static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES];
 static struct iommu_device omap4_devices[] = {
        {
                .base = OMAP4_MMU1_BASE,
-                .irq = OMAP44XX_IRQ_DUCATI_MMU,
+                .irq = 100 + OMAP44XX_IRQ_GIC_START,
                .pdata = {
                        .name = "ducati",
                        .nr_tlb_entries = 32,
@@ -75,7 +77,7 @@ static struct iommu_device omap4_devices[] = {
        },
        {
                .base = OMAP4_MMU2_BASE,
-                .irq = OMAP44XX_IRQ_TESLA_MMU,
+                .irq = 28 + OMAP44XX_IRQ_GIC_START,
                .pdata = {
                        .name = "tesla",
                        .nr_tlb_entries = 32,
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 637a1bdf2ac4..ff4e6a0e9c7c 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -50,9 +50,8 @@
 #include <asm/suspend.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <plat/omap44xx.h>
 #include "common.h"
+#include "omap44xx.h"
 #include "omap4-sar-layout.h"
 #include "pm.h"
 #include "prcm_mpu44xx.h"
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index d9ae4a53d818..e089e4d1ae38 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -19,7 +19,7 @@
 #include <asm/memblock.h>
 #include <plat/omap-secure.h>
-#include <mach/omap-secure.h>
+#include "omap-secure.h"
 static phys_addr_t omap_secure_memblock_base;
@@ -61,8 +61,8 @@ int __init omap_secure_ram_reserve_memblock(void)
 {
        u32 size = OMAP_SECURE_RAM_STORAGE;
-        size = ALIGN(size, SZ_1M);
+        size = ALIGN(size, SECTION_SIZE);
-        omap_secure_memblock_base = arm_memblock_steal(size, SZ_1M);
+        omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE);
        return 0;
 }
diff --git a/arch/arm/mach-omap2/include/mach/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index c90a43589abe..c90a43589abe 100644
--- a/arch/arm/mach-omap2/include/mach/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 9a35adf91232..4d05fa8a4e48 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -24,11 +24,11 @@
 #include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
-#include <mach/hardware.h>
+#include "omap-secure.h"
-#include <mach/omap-secure.h>
+#include "omap-wakeupgen.h"
-#include <mach/omap-wakeupgen.h>
 #include <asm/cputype.h>
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "clockdomain.h"
@@ -49,7 +49,7 @@ void __iomem *omap4_get_scu_base(void)
        return scu_base;
 }
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit omap4_secondary_init(unsigned int cpu)
 {
        /*
         * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
@@ -77,7 +77,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
        spin_unlock(&boot_lock);
 }
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        static struct clockdomain *cpu1_clkdm;
        static bool booted;
@@ -165,7 +165,7 @@ static void __init wakeup_secondary(void)
 * Initialise the CPU possible map early - this describes the CPUs
 * which may be present or become present in the system.
 */
-void __init smp_init_cpus(void)
+static void __init omap4_smp_init_cpus(void)
 {
        unsigned int i = 0, ncores = 1, cpu_id;
@@ -196,7 +196,7 @@ void __init smp_init_cpus(void)
        set_smp_cross_call(gic_raise_softirq);
 }
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
 {
        /*
@@ -207,3 +207,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
                scu_enable(scu_base);
        wakeup_secondary();
 }
+struct smp_operations omap4_smp_ops __initdata = {
+        .smp_init_cpus          = omap4_smp_init_cpus,
+        .smp_prepare_cpus       = omap4_smp_prepare_cpus,
+        .smp_secondary_init     = omap4_secondary_init,
+        .smp_boot_secondary     = omap4_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = omap4_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 330d4c6e746b..5d3b4f4f81ae 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -27,9 +27,10 @@
 #include <asm/hardware/gic.h>
-#include <mach/omap-wakeupgen.h>
+#include "omap-wakeupgen.h"
-#include <mach/omap-secure.h>
+#include "omap-secure.h"
+#include "soc.h"
 #include "omap4-sar-layout.h"
 #include "common.h"
@@ -229,13 +230,7 @@ static inline void omap4_irq_save_context(void)
        /* Save AuxBoot* registers */
        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
        __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
-        __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
-        /* Save SyncReq generation logic */
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-        __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
        __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
        /* Save SyncReq generation logic */
diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/omap-wakeupgen.h
index b0fd16f5c391..b0fd16f5c391 100644
--- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/omap-wakeupgen.h
diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/mach-omap2/omap24xx.h
index 92df9e27cc5c..641a2c8d2eee 100644
--- a/arch/arm/plat-omap/include/plat/omap24xx.h
+++ b/arch/arm/mach-omap2/omap24xx.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/plat-omap/include/mach/omap24xx.h
- *
 * This file contains the processor specific definitions
 * of the TI OMAP24XX.
 *
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/mach-omap2/omap34xx.h
index 0d818acf3917..c0d1b4b1653f 100644
--- a/arch/arm/plat-omap/include/plat/omap34xx.h
+++ b/arch/arm/mach-omap2/omap34xx.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/plat-omap/include/mach/omap34xx.h
- *
 * This file contains the processor specific definitions of the TI OMAP34XX.
 *
 * Copyright (C) 2007 Texas Instruments.
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index c29dee998a79..e1f289748c5d 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -16,26 +16,25 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/memblock.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/export.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <plat/irqs.h>
 #include <plat/sram.h>
 #include <plat/omap-secure.h>
 #include <plat/mmc.h>
-#include <mach/hardware.h>
+#include "omap-wakeupgen.h"
-#include <mach/omap-wakeupgen.h>
+#include "soc.h"
 #include "common.h"
 #include "hsmmc.h"
 #include "omap4-sar-layout.h"
-#include <linux/export.h>
 #ifdef CONFIG_CACHE_L2X0
 static void __iomem *l2cache_base;
@@ -171,7 +170,10 @@ static int __init omap_l2_cache_init(void)
        /* Enable PL310 L2 Cache controller */
        omap_smc1(0x102, 0x1);
-        l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
+        if (of_have_populated_dt())
+                l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
+        else
+                l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
        /*
         * Override default outer_cache.disable with a OMAP4
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/mach-omap2/omap4-keypad.h
index 8ad0a377a54b..20de0d5a7e77 100644
--- a/arch/arm/plat-omap/include/plat/omap4-keypad.h
+++ b/arch/arm/mach-omap2/omap4-keypad.h
@@ -1,6 +1,8 @@
 #ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
 #define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
+struct omap_board_data;
 extern int omap4_keyboard_init(struct omap4_keypad_platform_data *,
                                struct omap_board_data *);
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/mach-omap2/omap44xx.h
index c0d478e55c84..43b927b2e2e8 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/mach-omap2/omap44xx.h
@@ -39,12 +39,12 @@
 #define IRQ_SIR_IRQ                     0x0040
 #define OMAP44XX_GIC_DIST_BASE          0x48241000
 #define OMAP44XX_GIC_CPU_BASE           0x48240100
+#define OMAP44XX_IRQ_GIC_START          32
 #define OMAP44XX_SCU_BASE               0x48240000
 #define OMAP44XX_LOCAL_TWD_BASE         0x48240600
 #define OMAP44XX_L2CACHE_BASE           0x48242000
 #define OMAP44XX_WKUPGEN_BASE           0x48281000
 #define OMAP44XX_MCPDM_BASE             0x40132000
-#define OMAP44XX_MCPDM_L3_BASE          0x49032000
 #define OMAP44XX_SAR_RAM_BASE           0x4a326000
 #define OMAP44XX_MAILBOX_BASE           (L4_44XX_BASE + 0xF4000)
diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h
index a2582bb3cab3..a2582bb3cab3 100644
--- a/arch/arm/plat-omap/include/plat/omap54xx.h
+++ b/arch/arm/mach-omap2/omap54xx.h
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 37afbd173c2c..b969ab1d258b 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -139,18 +139,20 @@
 #include <linux/slab.h>
 #include <linux/bootmem.h>
-#include "common.h"
-#include <plat/cpu.h>
-#include "clockdomain.h"
-#include "powerdomain.h"
 #include <plat/clock.h>
 #include <plat/omap_hwmod.h>
 #include <plat/prcm.h>
+#include "soc.h"
+#include "common.h"
+#include "clockdomain.h"
+#include "powerdomain.h"
 #include "cm2xxx_3xxx.h"
 #include "cminst44xx.h"
+#include "cm33xx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
+#include "prm33xx.h"
 #include "prminst44xx.h"
 #include "mux.h"
 #include "pm.h"
@@ -677,16 +679,25 @@ static int _init_main_clk(struct omap_hwmod *oh)
        if (!oh->main_clk)
                return 0;
-        oh->_clk = omap_clk_get_by_name(oh->main_clk);
+        oh->_clk = clk_get(NULL, oh->main_clk);
-        if (!oh->_clk) {
+        if (IS_ERR(oh->_clk)) {
                pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
                           oh->name, oh->main_clk);
                return -EINVAL;
        }
+        /*
+         * HACK: This needs a re-visit once clk_prepare() is implemented
+         * to do something meaningful. Today its just a no-op.
+         * If clk_prepare() is used at some point to do things like
+         * voltage scaling etc, then this would have to be moved to
+         * some point where subsystems like i2c and pmic become
+         * available.
+         */
+        clk_prepare(oh->_clk);
        if (!oh->_clk->clkdm)
-                pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
+                pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n",
-                           oh->main_clk, oh->_clk->name);
+                           oh->name, oh->main_clk);
        return ret;
 }
@@ -713,13 +724,22 @@ static int _init_interface_clks(struct omap_hwmod *oh)
                if (!os->clk)
                        continue;
-                c = omap_clk_get_by_name(os->clk);
+                c = clk_get(NULL, os->clk);
-                if (!c) {
+                if (IS_ERR(c)) {
                        pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
                                   oh->name, os->clk);
                        ret = -EINVAL;
                }
                os->_clk = c;
+                /*
+                 * HACK: This needs a re-visit once clk_prepare() is implemented
+                 * to do something meaningful. Today its just a no-op.
+                 * If clk_prepare() is used at some point to do things like
+                 * voltage scaling etc, then this would have to be moved to
+                 * some point where subsystems like i2c and pmic become
+                 * available.
+                 */
+                clk_prepare(os->_clk);
        }
        return ret;
@@ -740,13 +760,22 @@ static int _init_opt_clks(struct omap_hwmod *oh)
        int ret = 0;
        for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
-                c = omap_clk_get_by_name(oc->clk);
+                c = clk_get(NULL, oc->clk);
-                if (!c) {
+                if (IS_ERR(c)) {
                        pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
                                   oh->name, oc->clk);
                        ret = -EINVAL;
                }
                oc->_clk = c;
+                /*
+                 * HACK: This needs a re-visit once clk_prepare() is implemented
+                 * to do something meaningful. Today its just a no-op.
+                 * If clk_prepare() is used at some point to do things like
+                 * voltage scaling etc, then this would have to be moved to
+                 * some point where subsystems like i2c and pmic become
+                 * available.
+                 */
+                clk_prepare(oc->_clk);
        }
        return ret;
@@ -825,7 +854,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh)
        for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                if (oc->_clk) {
                        pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
-                                 oc->_clk->name);
+                                 __clk_get_name(oc->_clk));
                        clk_enable(oc->_clk);
                }
 }
@@ -840,7 +869,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
        for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                if (oc->_clk) {
                        pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
-                                 oc->_clk->name);
+                                 __clk_get_name(oc->_clk));
                        clk_disable(oc->_clk);
                }
 }
@@ -868,6 +897,26 @@ static void _omap4_enable_module(struct omap_hwmod *oh)
 }
 /**
+ * _am33xx_enable_module - enable CLKCTRL modulemode on AM33XX
+ * @oh: struct omap_hwmod *
+ *
+ * Enables the PRCM module mode related to the hwmod @oh.
+ * No return value.
+ */
+static void _am33xx_enable_module(struct omap_hwmod *oh)
+{
+        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+                return;
+        pr_debug("omap_hwmod: %s: %s: %d\n",
+                 oh->name, __func__, oh->prcm.omap4.modulemode);
+        am33xx_cm_module_enable(oh->prcm.omap4.modulemode, oh->clkdm->cm_inst,
+                                oh->clkdm->clkdm_offs,
+                                oh->prcm.omap4.clkctrl_offs);
+}
+/**
 * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4
 * @oh: struct omap_hwmod *
 *
@@ -878,10 +927,10 @@ static void _omap4_enable_module(struct omap_hwmod *oh)
 */
 static int _omap4_wait_target_disable(struct omap_hwmod *oh)
 {
-        if (!oh || !oh->clkdm)
+        if (!oh)
                return -EINVAL;
-        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm)
                return 0;
        if (oh->flags & HWMOD_NO_IDLEST)
@@ -894,6 +943,31 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh)
 }
 /**
+ * _am33xx_wait_target_disable - wait for a module to be disabled on AM33XX
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to enter slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully enters
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_idle() function.
+ */
+static int _am33xx_wait_target_disable(struct omap_hwmod *oh)
+{
+        if (!oh)
+                return -EINVAL;
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+                return 0;
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+        return am33xx_cm_wait_module_idle(oh->clkdm->cm_inst,
+                                             oh->clkdm->clkdm_offs,
+                                             oh->prcm.omap4.clkctrl_offs);
+}
+/**
 * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
 * @oh: struct omap_hwmod *oh
 *
@@ -1380,8 +1454,10 @@ static struct omap_hwmod *_lookup(const char *name)
 */
 static int _init_clkdm(struct omap_hwmod *oh)
 {
-        if (!oh->clkdm_name)
+        if (!oh->clkdm_name) {
+                pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name);
                return 0;
+        }
        oh->clkdm = clkdm_lookup(oh->clkdm_name);
        if (!oh->clkdm) {
@@ -1438,8 +1514,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
 * Return the bit position of the reset line that match the
 * input name. Return -ENOENT if not found.
 */
-static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
+static int _lookup_hardreset(struct omap_hwmod *oh, const char *name,
-                            struct omap_hwmod_rst_info *ohri)
+                             struct omap_hwmod_rst_info *ohri)
 {
        int i;
@@ -1475,7 +1551,7 @@ static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
 static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
 {
        struct omap_hwmod_rst_info ohri;
-        u8 ret = -EINVAL;
+        int ret = -EINVAL;
        if (!oh)
                return -EINVAL;
@@ -1484,7 +1560,7 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
                return -ENOSYS;
        ret = _lookup_hardreset(oh, name, &ohri);
-        if (IS_ERR_VALUE(ret))
+        if (ret < 0)
                return ret;
        ret = soc_ops.assert_hardreset(oh, &ohri);
@@ -1509,6 +1585,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
 {
        struct omap_hwmod_rst_info ohri;
        int ret = -EINVAL;
+        int hwsup = 0;
        if (!oh)
                return -EINVAL;
@@ -1520,10 +1597,46 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
        if (IS_ERR_VALUE(ret))
                return ret;
+        if (oh->clkdm) {
+                /*
+                 * A clockdomain must be in SW_SUP otherwise reset
+                 * might not be completed. The clockdomain can be set
+                 * in HW_AUTO only when the module become ready.
+                 */
+                hwsup = clkdm_in_hwsup(oh->clkdm);
+                ret = clkdm_hwmod_enable(oh->clkdm, oh);
+                if (ret) {
+                        WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
+                             oh->name, oh->clkdm->name, ret);
+                        return ret;
+                }
+        }
+        _enable_clocks(oh);
+        if (soc_ops.enable_module)
+                soc_ops.enable_module(oh);
        ret = soc_ops.deassert_hardreset(oh, &ohri);
+        if (soc_ops.disable_module)
+                soc_ops.disable_module(oh);
+        _disable_clocks(oh);
        if (ret == -EBUSY)
                pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
+        if (!ret) {
+                /*
+                 * Set the clockdomain to HW_AUTO, assuming that the
+                 * previous state was HW_AUTO.
+                 */
+                if (oh->clkdm && hwsup)
+                        clkdm_allow_idle(oh->clkdm);
+        } else {
+                if (oh->clkdm)
+                        clkdm_hwmod_disable(oh->clkdm, oh);
+        }
        return ret;
 }
@@ -1542,7 +1655,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
 static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 {
        struct omap_hwmod_rst_info ohri;
-        u8 ret = -EINVAL;
+        int ret = -EINVAL;
        if (!oh)
                return -EINVAL;
@@ -1551,37 +1664,63 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
                return -ENOSYS;
        ret = _lookup_hardreset(oh, name, &ohri);
-        if (IS_ERR_VALUE(ret))
+        if (ret < 0)
                return ret;
        return soc_ops.is_hardreset_asserted(oh, &ohri);
 }
 /**
- * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset
+ * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset
 * @oh: struct omap_hwmod *
 *
- * If any hardreset line associated with @oh is asserted, then return true.
+ * If all hardreset lines associated with @oh are asserted, then return true.
- * Otherwise, if @oh has no hardreset lines associated with it, or if
+ * Otherwise, if part of @oh is out hardreset or if no hardreset lines
- * no hardreset lines associated with @oh are asserted, then return false.
+ * associated with @oh are asserted, then return false.
 * This function is used to avoid executing some parts of the IP block
- * enable/disable sequence if a hardreset line is set.
+ * enable/disable sequence if its hardreset line is set.
 */
-static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
+static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh)
 {
-        int i;
+        int i, rst_cnt = 0;
        if (oh->rst_lines_cnt == 0)
                return false;
        for (i = 0; i < oh->rst_lines_cnt; i++)
                if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
-                        return true;
+                        rst_cnt++;
+        if (oh->rst_lines_cnt == rst_cnt)
+                return true;
        return false;
 }
 /**
+ * _are_any_hardreset_lines_asserted - return true if any part of @oh is
+ * hard-reset
+ * @oh: struct omap_hwmod *
+ *
+ * If any hardreset lines associated with @oh are asserted, then
+ * return true.  Otherwise, if no hardreset lines associated with @oh
+ * are asserted, or if @oh has no hardreset lines, then return false.
+ * This function is used to avoid executing some parts of the IP block
+ * enable/disable sequence if any hardreset line is set.
+ */
+static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
+{
+        int rst_cnt = 0;
+        int i;
+        for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++)
+                if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
+                        rst_cnt++;
+        return (rst_cnt) ? true : false;
+}
+/**
 * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
 * @oh: struct omap_hwmod *
 *
@@ -1595,6 +1734,13 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
                return -EINVAL;
+        /*
+         * Since integration code might still be doing something, only
+         * disable if all lines are under hardreset.
+         */
+        if (_are_any_hardreset_lines_asserted(oh))
+                return 0;
        pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
        omap4_cminst_module_disable(oh->clkdm->prcm_partition,
@@ -1602,10 +1748,37 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
                                    oh->clkdm->clkdm_offs,
                                    oh->prcm.omap4.clkctrl_offs);
+        v = _omap4_wait_target_disable(oh);
+        if (v)
+                pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+                        oh->name);
+        return 0;
+}
+/**
+ * _am33xx_disable_module - enable CLKCTRL modulemode on AM33XX
+ * @oh: struct omap_hwmod *
+ *
+ * Disable the PRCM module mode related to the hwmod @oh.
+ * Return EINVAL if the modulemode is not supported and 0 in case of success.
+ */
+static int _am33xx_disable_module(struct omap_hwmod *oh)
+{
+        int v;
+        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+                return -EINVAL;
+        pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
        if (_are_any_hardreset_lines_asserted(oh))
                return 0;
-        v = _omap4_wait_target_disable(oh);
+        am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs,
+                                 oh->prcm.omap4.clkctrl_offs);
+        v = _am33xx_wait_target_disable(oh);
        if (v)
                pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
                        oh->name);
@@ -1641,8 +1814,8 @@ static int _ocp_softreset(struct omap_hwmod *oh)
        /* clocks must be on for this operation */
        if (oh->_state != _HWMOD_STATE_ENABLED) {
-                pr_warning("omap_hwmod: %s: reset can only be entered from "
+                pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n",
-                           "enabled state\n", oh->name);
+                        oh->name);
                return -EINVAL;
        }
@@ -1830,7 +2003,7 @@ static int _enable(struct omap_hwmod *oh)
        }
        /*
-         * If an IP block contains HW reset lines and any of them are
+         * If an IP block contains HW reset lines and all of them are
         * asserted, we let integration code associated with that
         * block handle the enable.  We've received very little
         * information on what those driver authors need, and until
@@ -1838,7 +2011,7 @@ static int _enable(struct omap_hwmod *oh)
         * posted to the public lists, this is probably the best we
         * can do.
         */
-        if (_are_any_hardreset_lines_asserted(oh))
+        if (_are_all_hardreset_lines_asserted(oh))
                return 0;
        /* Mux pins for device runtime if populated */
@@ -1857,7 +2030,8 @@ static int _enable(struct omap_hwmod *oh)
                 * completely the module. The clockdomain can be set
                 * in HW_AUTO only when the module become ready.
                 */
-                hwsup = clkdm_in_hwsup(oh->clkdm);
+                hwsup = clkdm_in_hwsup(oh->clkdm) &&
+                        !clkdm_missing_idle_reporting(oh->clkdm);
                r = clkdm_hwmod_enable(oh->clkdm, oh);
                if (r) {
                        WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
@@ -1919,7 +2093,7 @@ static int _idle(struct omap_hwmod *oh)
                return -EINVAL;
        }
-        if (_are_any_hardreset_lines_asserted(oh))
+        if (_are_all_hardreset_lines_asserted(oh))
                return 0;
        if (oh->class->sysc)
@@ -2007,7 +2181,7 @@ static int _shutdown(struct omap_hwmod *oh)
                return -EINVAL;
        }
-        if (_are_any_hardreset_lines_asserted(oh))
+        if (_are_all_hardreset_lines_asserted(oh))
                return 0;
        pr_debug("omap_hwmod: %s: disabling\n", oh->name);
@@ -2531,10 +2705,10 @@ static int _omap2_wait_target_ready(struct omap_hwmod *oh)
 */
 static int _omap4_wait_target_ready(struct omap_hwmod *oh)
 {
-        if (!oh || !oh->clkdm)
+        if (!oh)
                return -EINVAL;
-        if (oh->flags & HWMOD_NO_IDLEST)
+        if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm)
                return 0;
        if (!_find_mpu_rt_port(oh))
@@ -2549,6 +2723,33 @@ static int _omap4_wait_target_ready(struct omap_hwmod *oh)
 }
 /**
+ * _am33xx_wait_target_ready - wait for a module to leave slave idle
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to leave slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully leaves
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_ready() function.
+ */
+static int _am33xx_wait_target_ready(struct omap_hwmod *oh)
+{
+        if (!oh || !oh->clkdm)
+                return -EINVAL;
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+        if (!_find_mpu_rt_port(oh))
+                return 0;
+        /* XXX check module SIDLEMODE, hardreset status */
+        return am33xx_cm_wait_module_ready(oh->clkdm->cm_inst,
+                                              oh->clkdm->clkdm_offs,
+                                              oh->prcm.omap4.clkctrl_offs);
+}
+/**
 * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
 * @oh: struct omap_hwmod * to assert hardreset
 * @ohri: hardreset line data
@@ -2679,6 +2880,72 @@ static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
                                oh->prcm.omap4.rstctrl_offs);
 }
+/**
+ * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to assert hardreset
+ * @ohri: hardreset line data
+ *
+ * Call am33xx_prminst_assert_hardreset() with parameters extracted
+ * from the hwmod @oh and the hardreset line data @ohri.  Only
+ * intended for use as an soc_ops function pointer.  Passes along the
+ * return value from am33xx_prminst_assert_hardreset().  XXX This
+ * function is scheduled for removal when the PRM code is moved into
+ * drivers/.
+ */
+static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
+                                   struct omap_hwmod_rst_info *ohri)
+{
+        return am33xx_prm_assert_hardreset(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs);
+}
+/**
+ * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to deassert hardreset
+ * @ohri: hardreset line data
+ *
+ * Call am33xx_prminst_deassert_hardreset() with parameters extracted
+ * from the hwmod @oh and the hardreset line data @ohri.  Only
+ * intended for use as an soc_ops function pointer.  Passes along the
+ * return value from am33xx_prminst_deassert_hardreset().  XXX This
+ * function is scheduled for removal when the PRM code is moved into
+ * drivers/.
+ */
+static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
+                                     struct omap_hwmod_rst_info *ohri)
+{
+        if (ohri->st_shift)
+                pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
+                       oh->name, ohri->name);
+        return am33xx_prm_deassert_hardreset(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs,
+                                oh->prcm.omap4.rstst_offs);
+}
+/**
+ * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to test hardreset
+ * @ohri: hardreset line data
+ *
+ * Call am33xx_prminst_is_hardreset_asserted() with parameters
+ * extracted from the hwmod @oh and the hardreset line data @ohri.
+ * Only intended for use as an soc_ops function pointer.  Passes along
+ * the return value from am33xx_prminst_is_hardreset_asserted().  XXX
+ * This function is scheduled for removal when the PRM code is moved
+ * into drivers/.
+ */
+static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh,
+                                        struct omap_hwmod_rst_info *ohri)
+{
+        return am33xx_prm_is_hardreset_asserted(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs);
+}
 /* Public functions */
 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
@@ -3159,6 +3426,33 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 }
 /**
+ * omap_hwmod_fill_dma_resources - fill struct resource array with dma data
+ * @oh: struct omap_hwmod *
+ * @res: pointer to the array of struct resource to fill
+ *
+ * Fill the struct resource array @res with dma resource data from the
+ * omap_hwmod @oh.  Intended to be called by code that registers
+ * omap_devices.  See also omap_hwmod_count_resources().  Returns the
+ * number of array elements filled.
+ */
+int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res)
+{
+        int i, sdma_reqs_cnt;
+        int r = 0;
+        sdma_reqs_cnt = _count_sdma_reqs(oh);
+        for (i = 0; i < sdma_reqs_cnt; i++) {
+                (res + r)->name = (oh->sdma_reqs + i)->name;
+                (res + r)->start = (oh->sdma_reqs + i)->dma_req;
+                (res + r)->end = (oh->sdma_reqs + i)->dma_req;
+                (res + r)->flags = IORESOURCE_DMA;
+                r++;
+        }
+        return r;
+}
+/**
 * omap_hwmod_get_resource_byname - fetch IP block integration data by name
 * @oh: struct omap_hwmod * to operate on
 * @type: one of the IORESOURCE_* constants from include/linux/ioport.h
@@ -3678,6 +3972,14 @@ void __init omap_hwmod_init(void)
                soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
                soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
                soc_ops.init_clkdm = _init_clkdm;
+        } else if (soc_is_am33xx()) {
+                soc_ops.enable_module = _am33xx_enable_module;
+                soc_ops.disable_module = _am33xx_disable_module;
+                soc_ops.wait_target_ready = _am33xx_wait_target_ready;
+                soc_ops.assert_hardreset = _am33xx_assert_hardreset;
+                soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
+                soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted;
+                soc_ops.init_clkdm = _init_clkdm;
        } else {
                WARN(1, "omap_hwmod: unknown SoC type\n");
        }
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 50cfab61b0e2..b5db6007c523 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -12,17 +12,15 @@
 * XXX handle crossbar/shared link difference for L3?
 * XXX these should be marked initdata for multi-OMAP kernels
 */
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/omap_hwmod.h>
-#include <mach/irqs.h>
-#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
-#include <plat/mcspi.h>
 #include <plat/dmtimer.h>
-#include <plat/l3_2xxx.h>
+#include "l3_2xxx.h"
-#include <plat/l4_2xxx.h>
+#include "l4_2xxx.h"
 #include <plat/mmc.h>
 #include "omap_hwmod_common_data.h"
@@ -162,9 +160,9 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
 /* mailbox */
 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
-        { .name = "dsp", .irq = 26 },
+        { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
-        { .name = "iva", .irq = 34 },
+        { .name = "iva", .irq = 34 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap2420_mailbox_hwmod = {
@@ -199,9 +197,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
-        { .name = "tx", .irq = 59 },
+        { .name = "tx", .irq = 59 + OMAP_INTC_START, },
-        { .name = "rx", .irq = 60 },
+        { .name = "rx", .irq = 60 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
@@ -225,9 +223,9 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
 /* mcbsp2 */
 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
-        { .name = "tx", .irq = 62 },
+        { .name = "tx", .irq = 62 + OMAP_INTC_START, },
-        { .name = "rx", .irq = 63 },
+        { .name = "rx", .irq = 63 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
@@ -265,8 +263,8 @@ static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
 /* msdi1 */
 static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
-        { .irq = 83 },
+        { .irq = 83 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
@@ -538,6 +536,15 @@ static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
        { }
 };
+static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x6800a000,
+                .pa_end         = 0x6800afff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
        .master         = &omap2xxx_l4_wkup_hwmod,
        .slave          = &omap2xxx_counter_32k_hwmod,
@@ -546,6 +553,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
+        .master         = &omap2xxx_l3_main_hwmod,
+        .slave          = &omap2xxx_gpmc_hwmod,
+        .clk            = "core_l3_ck",
+        .addr           = omap2420_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
        &omap2xxx_l3_main__l4_core,
        &omap2xxx_mpu__l3_main,
@@ -587,8 +602,10 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
        &omap2420_l4_core__mcbsp1,
        &omap2420_l4_core__mcbsp2,
        &omap2420_l4_core__msdi1,
+        &omap2xxx_l4_core__rng,
        &omap2420_l4_core__hdq1w,
        &omap2420_l4_wkup__counter_32k,
+        &omap2420_l3__gpmc,
        NULL,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 58b5bc196d32..c455e41b0237 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -12,21 +12,19 @@
 * XXX handle crossbar/shared link difference for L3?
 * XXX these should be marked initdata for multi-OMAP kernels
 */
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/omap_hwmod.h>
-#include <mach/irqs.h>
-#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
-#include <plat/mcbsp.h>
-#include <plat/mcspi.h>
 #include <plat/dmtimer.h>
 #include <plat/mmc.h>
-#include <plat/l3_2xxx.h>
+#include "l3_2xxx.h"
+#include "soc.h"
 #include "omap_hwmod_common_data.h"
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
 #include "wd_timer.h"
@@ -133,8 +131,8 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
 /* gpio5 */
 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
-        { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
+        { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap2430_gpio5_hwmod = {
@@ -173,8 +171,8 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
 /* mailbox */
 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
-        { .irq = 26 },
+        { .irq = 26 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap2430_mailbox_hwmod = {
@@ -195,8 +193,8 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
 /* mcspi3 */
 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
-        { .irq = 91 },
+        { .irq = 91 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
@@ -250,9 +248,9 @@ static struct omap_hwmod_class usbotg_class = {
 /* usb_otg_hs */
 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
-        { .name = "mc", .irq = 92 },
+        { .name = "mc", .irq = 92 + OMAP_INTC_START, },
-        { .name = "dma", .irq = 93 },
+        { .name = "dma", .irq = 93 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
@@ -303,11 +301,11 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
-        { .name = "tx",         .irq = 59 },
+        { .name = "tx",         .irq = 59 + OMAP_INTC_START, },
-        { .name = "rx",         .irq = 60 },
+        { .name = "rx",         .irq = 60 + OMAP_INTC_START, },
-        { .name = "ovr",        .irq = 61 },
+        { .name = "ovr",        .irq = 61 + OMAP_INTC_START, },
-        { .name = "common",     .irq = 64 },
+        { .name = "common",     .irq = 64 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
@@ -331,10 +329,10 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
 /* mcbsp2 */
 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
-        { .name = "tx",         .irq = 62 },
+        { .name = "tx",         .irq = 62 + OMAP_INTC_START, },
-        { .name = "rx",         .irq = 63 },
+        { .name = "rx",         .irq = 63 + OMAP_INTC_START, },
-        { .name = "common",     .irq = 16 },
+        { .name = "common",     .irq = 16 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
@@ -358,10 +356,10 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
 /* mcbsp3 */
 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
-        { .name = "tx",         .irq = 89 },
+        { .name = "tx",         .irq = 89 + OMAP_INTC_START, },
-        { .name = "rx",         .irq = 90 },
+        { .name = "rx",         .irq = 90 + OMAP_INTC_START, },
-        { .name = "common",     .irq = 17 },
+        { .name = "common",     .irq = 17 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
@@ -385,10 +383,10 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
 /* mcbsp4 */
 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
-        { .name = "tx",         .irq = 54 },
+        { .name = "tx",         .irq = 54 + OMAP_INTC_START, },
-        { .name = "rx",         .irq = 55 },
+        { .name = "rx",         .irq = 55 + OMAP_INTC_START, },
-        { .name = "common",     .irq = 18 },
+        { .name = "common",     .irq = 18 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
@@ -418,10 +416,10 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
 /* mcbsp5 */
 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
-        { .name = "tx",         .irq = 81 },
+        { .name = "tx",         .irq = 81 + OMAP_INTC_START, },
-        { .name = "rx",         .irq = 82 },
+        { .name = "rx",         .irq = 82 + OMAP_INTC_START, },
-        { .name = "common",     .irq = 19 },
+        { .name = "common",     .irq = 19 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
@@ -468,8 +466,8 @@ static struct omap_hwmod_class omap2430_mmc_class = {
 /* MMC/SD/SDIO1 */
 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
-        { .irq = 83 },
+        { .irq = 83 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
@@ -509,8 +507,8 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
 /* MMC/SD/SDIO2 */
 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
-        { .irq = 86 },
+        { .irq = 86 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
@@ -890,6 +888,15 @@ static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
        { }
 };
+static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x6e000000,
+                .pa_end         = 0x6e000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
        .master         = &omap2xxx_l4_wkup_hwmod,
        .slave          = &omap2xxx_counter_32k_hwmod,
@@ -898,6 +905,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
+        .master         = &omap2xxx_l3_main_hwmod,
+        .slave          = &omap2xxx_gpmc_hwmod,
+        .clk            = "core_l3_ck",
+        .addr           = omap2430_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
        &omap2xxx_l3_main__l4_core,
        &omap2xxx_mpu__l3_main,
@@ -947,7 +962,9 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
        &omap2430_l4_core__mcbsp4,
        &omap2430_l4_core__mcbsp5,
        &omap2430_l4_core__hdq1w,
+        &omap2xxx_l4_core__rng,
        &omap2430_l4_wkup__counter_32k,
+        &omap2430_l3__gpmc,
        NULL,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 102d76e9e9ea..8851bbb6bb24 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -13,9 +13,7 @@
 #include <plat/serial.h>
 #include <plat/dma.h>
 #include <plat/common.h>
-#include <plat/hdq1w.h>
+#include "hdq1w.h"
-#include <mach/irqs.h>
 #include "omap_hwmod_common_data.h"
@@ -182,126 +180,126 @@ struct omap_hwmod_class iva_hwmod_class = {
 /* Common MPU IRQ line data */
 struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
-        { .irq = 37, },
+        { .irq = 37 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
-        { .irq = 38, },
+        { .irq = 38 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
-        { .irq = 39, },
+        { .irq = 39 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
-        { .irq = 40, },
+        { .irq = 40 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
-        { .irq = 41, },
+        { .irq = 41 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
-        { .irq = 42, },
+        { .irq = 42 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
-        { .irq = 43, },
+        { .irq = 43 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
-        { .irq = 44, },
+        { .irq = 44 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
-        { .irq = 45, },
+        { .irq = 45 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
-        { .irq = 46, },
+        { .irq = 46 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
-        { .irq = 47, },
+        { .irq = 47 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
-        { .irq = INT_24XX_UART1_IRQ, },
+        { .irq = 72 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
-        { .irq = INT_24XX_UART2_IRQ, },
+        { .irq = 73 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
-        { .irq = INT_24XX_UART3_IRQ, },
+        { .irq = 74 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
-        { .irq = 25 },
+        { .irq = 25 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
-        { .irq = INT_24XX_I2C1_IRQ, },
+        { .irq = 56 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
-        { .irq = INT_24XX_I2C2_IRQ, },
+        { .irq = 57 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
-        { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
+        { .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
-        { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
+        { .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
-        { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
+        { .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
-        { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
+        { .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
-        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+        { .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */
-        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+        { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
-        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+        { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
-        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+        { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
-        { .irq = 65 },
+        { .irq = 65 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
-        { .irq = 66 },
+        { .irq = 66 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
@@ -320,7 +318,7 @@ struct omap_hwmod_class omap2_hdq1w_class = {
 };
 struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
-        { .irq = 58, },
+        { .irq = 58 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 5178e40e84f9..1a1287d62648 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -15,8 +15,8 @@
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
-#include <plat/l3_2xxx.h>
+#include "l3_2xxx.h"
-#include <plat/l4_2xxx.h>
+#include "l4_2xxx.h"
 #include "omap_hwmod_common_data.h"
@@ -129,6 +129,15 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
        { }
 };
+static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
+        {
+                .pa_start       = 0x480a0000,
+                .pa_end         = 0x480a004f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
 /*
 * Common interconnect data
 */
@@ -372,3 +381,11 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+/* l4_core -> rng */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_rng_hwmod,
+        .clk            = "rng_ick",
+        .addr           = omap2_rng_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index afad69c6ba6e..bd9220ed5ab9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -10,12 +10,10 @@
 */
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
-#include <plat/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <plat/dma.h>
 #include <plat/dmtimer.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <mach/irqs.h>
 #include "omap_hwmod_common_data.h"
 #include "cm-regbits-24xx.h"
@@ -23,8 +21,8 @@
 #include "wd_timer.h"
 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
-        { .irq = 48, },
+        { .irq = 48 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
@@ -175,6 +173,26 @@ struct omap_hwmod_class omap2xxx_mcspi_class = {
 };
 /*
+ * 'gpmc' class
+ * general purpose memory controller
+ */
+static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
+        .name   = "gpmc",
+        .sysc   = &omap2xxx_gpmc_sysc,
+};
+/*
 * IP blocks
 */
@@ -200,8 +218,14 @@ struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 };
 /* MPU */
+static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = {
+        { .name = "pmu", .irq = 3 + OMAP_INTC_START },
+        { .irq = -1 }
+};
 struct omap_hwmod omap2xxx_mpu_hwmod = {
        .name           = "mpu",
+        .mpu_irqs       = omap2xxx_mpu_irqs,
        .class          = &mpu_hwmod_class,
        .main_clk       = "mpu_ck",
 };
@@ -222,6 +246,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
        .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
 /* timer1 */
 struct omap_hwmod omap2xxx_timer1_hwmod = {
@@ -310,6 +339,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
                },
        },
+        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
 };
@@ -328,6 +358,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
                },
        },
+        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
 };
@@ -346,6 +377,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
                },
        },
+        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
 };
@@ -364,6 +396,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
                },
        },
+        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
 };
@@ -726,7 +759,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = {
        .dev_attr       = &omap_mcspi2_dev_attr,
 };
 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
        .name   = "counter",
 };
@@ -745,3 +777,77 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = {
        },
        .class          = &omap2xxx_counter_hwmod_class,
 };
+/* gpmc */
+static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
+        { .irq = 20 },
+        { .irq = -1 }
+};
+struct omap_hwmod omap2xxx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &omap2xxx_gpmc_hwmod_class,
+        .mpu_irqs       = omap2xxx_gpmc_irqs,
+        .main_clk       = "gpmc_fck",
+        /*
+         * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
+         * block.  It is not being added due to any known bugs with
+         * resetting the GPMC IP block, but rather because any timings
+         * set by the bootloader are not being correctly programmed by
+         * the kernel from the board file or DT data.
+         * HWMOD_INIT_NO_RESET should be removed ASAP.
+         */
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
+                           HWMOD_NO_IDLEST),
+        .prcm           = {
+                .omap2  = {
+                        .prcm_reg_id = 3,
+                        .module_bit = OMAP24XX_EN_GPMC_MASK,
+                        .module_offs = CORE_MOD,
+                },
+        },
+};
+/* RNG */
+static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
+        .rev_offs       = 0x3c,
+        .sysc_offs      = 0x40,
+        .syss_offs      = 0x44,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap2_rng_hwmod_class = {
+        .name           = "rng",
+        .sysc           = &omap2_rng_sysc,
+};
+static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
+        { .irq = 52 },
+        { .irq = -1 }
+};
+struct omap_hwmod omap2xxx_rng_hwmod = {
+        .name           = "rng",
+        .mpu_irqs       = omap2_rng_mpu_irqs,
+        .main_clk       = "l4_ck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 4,
+                        .module_bit = OMAP24XX_EN_RNG_SHIFT,
+                        .idlest_reg_id = 4,
+                        .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
+                },
+        },
+        /*
+         * XXX The first read from the SYSSTATUS register of the RNG
+         * after the SYSCONFIG SOFTRESET bit is set triggers an
+         * imprecise external abort.  It's unclear why this happens.
+         * Until this is analyzed, skip the IP block reset.
+         */
+        .flags          = HWMOD_INIT_NO_RESET,
+        .class          = &omap2_rng_hwmod_class,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
new file mode 100644
index 000000000000..59d5c1cd316d
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -0,0 +1,3381 @@
+/*
+ * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
+ *
+ * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is automatically generated from the AM33XX hardware databases.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <plat/omap_hwmod.h>
+#include <plat/cpu.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <plat/dma.h>
+#include <plat/mmc.h>
+#include <plat/i2c.h>
+#include "omap_hwmod_common_data.h"
+#include "control.h"
+#include "cm33xx.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+/*
+ * IP blocks
+ */
+/*
+ * 'emif_fw' class
+ * instance(s): emif_fw
+ */
+static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
+        .name           = "emif_fw",
+};
+/* emif_fw */
+static struct omap_hwmod am33xx_emif_fw_hwmod = {
+        .name           = "emif_fw",
+        .class          = &am33xx_emif_fw_hwmod_class,
+        .clkdm_name     = "l4fw_clkdm",
+        .main_clk       = "l4fw_gclk",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'emif' class
+ * instance(s): emif
+ */
+static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
+        .rev_offs       = 0x0000,
+};
+static struct omap_hwmod_class am33xx_emif_hwmod_class = {
+        .name           = "emif",
+        .sysc           = &am33xx_emif_sysc,
+};
+static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
+        { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+/* emif */
+static struct omap_hwmod am33xx_emif_hwmod = {
+        .name           = "emif",
+        .class          = &am33xx_emif_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_emif_irqs,
+        .main_clk       = "dpll_ddr_m2_div2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'l3' class
+ * instance(s): l3_main, l3_s, l3_instr
+ */
+static struct omap_hwmod_class am33xx_l3_hwmod_class = {
+        .name           = "l3",
+};
+/* l3_main (l3_fast) */
+static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
+        { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
+        { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_l3_main_hwmod = {
+        .name           = "l3_main",
+        .class          = &am33xx_l3_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_l3_main_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* l3_s */
+static struct omap_hwmod am33xx_l3_s_hwmod = {
+        .name           = "l3_s",
+        .class          = &am33xx_l3_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+};
+/* l3_instr */
+static struct omap_hwmod am33xx_l3_instr_hwmod = {
+        .name           = "l3_instr",
+        .class          = &am33xx_l3_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'l4' class
+ * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
+ */
+static struct omap_hwmod_class am33xx_l4_hwmod_class = {
+        .name           = "l4",
+};
+/* l4_ls */
+static struct omap_hwmod am33xx_l4_ls_hwmod = {
+        .name           = "l4_ls",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* l4_hs */
+static struct omap_hwmod am33xx_l4_hs_hwmod = {
+        .name           = "l4_hs",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l4hs_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l4hs_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* l4_wkup */
+static struct omap_hwmod am33xx_l4_wkup_hwmod = {
+        .name           = "l4_wkup",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* l4_fw */
+static struct omap_hwmod am33xx_l4_fw_hwmod = {
+        .name           = "l4_fw",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l4fw_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'mpu' class
+ */
+static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
+        .name   = "mpu",
+};
+/* mpu */
+static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
+        { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
+        { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
+        { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
+        { .name = "bench", .irq = 3 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_mpu_hwmod = {
+        .name           = "mpu",
+        .class          = &am33xx_mpu_hwmod_class,
+        .clkdm_name     = "mpu_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_mpu_irqs,
+        .main_clk       = "dpll_mpu_m2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'wakeup m3' class
+ * Wakeup controller sub-system under wakeup domain
+ */
+static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
+        .name           = "wkup_m3",
+};
+static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
+        { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
+};
+static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
+        { .name = "txev", .irq = 78 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+/* wkup_m3  */
+static struct omap_hwmod am33xx_wkup_m3_hwmod = {
+        .name           = "wkup_m3",
+        .class          = &am33xx_wkup_m3_hwmod_class,
+        .clkdm_name     = "l4_wkup_aon_clkdm",
+        .flags          = HWMOD_INIT_NO_RESET,  /* Keep hardreset asserted */
+        .mpu_irqs       = am33xx_wkup_m3_irqs,
+        .main_clk       = "dpll_core_m4_div2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
+                        .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .rst_lines      = am33xx_wkup_m3_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
+};
+/*
+ * 'pru-icss' class
+ * Programmable Real-Time Unit and Industrial Communication Subsystem
+ */
+static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
+        .name   = "pruss",
+};
+static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
+        { .name = "pruss", .rst_shift = 1 },
+};
+static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
+        { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
+        { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
+        { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
+        { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
+        { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
+        { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
+        { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
+        { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+/* pru-icss */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod am33xx_pruss_hwmod = {
+        .name           = "pruss",
+        .class          = &am33xx_pruss_hwmod_class,
+        .clkdm_name     = "pruss_ocp_clkdm",
+        .mpu_irqs       = am33xx_pruss_irqs,
+        .main_clk       = "pruss_ocp_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
+                        .rstctrl_offs   = AM33XX_RM_PER_RSTCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .rst_lines      = am33xx_pruss_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
+};
+/* gfx */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
+        .name   = "gfx",
+};
+static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
+        { .name = "gfx", .rst_shift = 0 },
+};
+static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
+        { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_gfx_hwmod = {
+        .name           = "gfx",
+        .class          = &am33xx_gfx_hwmod_class,
+        .clkdm_name     = "gfx_l3_clkdm",
+        .mpu_irqs       = am33xx_gfx_irqs,
+        .main_clk       = "gfx_fck_div_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
+                        .rstctrl_offs   = AM33XX_RM_GFX_RSTCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .rst_lines      = am33xx_gfx_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
+};
+/*
+ * 'prcm' class
+ * power and reset manager (whole prcm infrastructure)
+ */
+static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
+        .name   = "prcm",
+};
+/* prcm */
+static struct omap_hwmod am33xx_prcm_hwmod = {
+        .name           = "prcm",
+        .class          = &am33xx_prcm_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+/*
+ * 'adc/tsc' class
+ * TouchScreen Controller (Anolog-To-Digital Converter)
+ */
+static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
+        .rev_offs       = 0x00,
+        .sysc_offs      = 0x10,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                        SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
+        .name           = "adc_tsc",
+        .sysc           = &am33xx_adc_tsc_sysc,
+};
+static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
+        { .irq = 16 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_adc_tsc_hwmod = {
+        .name           = "adc_tsc",
+        .class          = &am33xx_adc_tsc_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_adc_tsc_irqs,
+        .main_clk       = "adc_tsc_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * Modules omap_hwmod structures
+ *
+ * The following IPs are excluded for the moment because:
+ * - They do not need an explicit SW control using omap_hwmod API.
+ * - They still need to be validated with the driver
+ *   properly adapted to omap_hwmod / omap_device
+ *
+ *    - cEFUSE (doesn't fall under any ocp_if)
+ *    - clkdiv32k
+ *    - debugss
+ *    - ocmc ram
+ *    - ocp watch point
+ *    - aes0
+ *    - sha0
+ */
+#if 0
+/*
+ * 'cefuse' class
+ */
+static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
+        .name           = "cefuse",
+};
+static struct omap_hwmod am33xx_cefuse_hwmod = {
+        .name           = "cefuse",
+        .class          = &am33xx_cefuse_hwmod_class,
+        .clkdm_name     = "l4_cefuse_clkdm",
+        .main_clk       = "cefuse_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'clkdiv32k' class
+ */
+static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
+        .name           = "clkdiv32k",
+};
+static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
+        .name           = "clkdiv32k",
+        .class          = &am33xx_clkdiv32k_hwmod_class,
+        .clkdm_name     = "clk_24mhz_clkdm",
+        .main_clk       = "clkdiv32k_ick",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'debugss' class
+ * debug sub system
+ */
+static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
+        .name           = "debugss",
+};
+static struct omap_hwmod am33xx_debugss_hwmod = {
+        .name           = "debugss",
+        .class          = &am33xx_debugss_hwmod_class,
+        .clkdm_name     = "l3_aon_clkdm",
+        .main_clk       = "debugss_ick",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* ocmcram */
+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+        .name = "ocmcram",
+};
+static struct omap_hwmod am33xx_ocmcram_hwmod = {
+        .name           = "ocmcram",
+        .class          = &am33xx_ocmcram_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* ocpwp */
+static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
+        .name           = "ocpwp",
+};
+static struct omap_hwmod am33xx_ocpwp_hwmod = {
+        .name           = "ocpwp",
+        .class          = &am33xx_ocpwp_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'aes' class
+ */
+static struct omap_hwmod_class am33xx_aes_hwmod_class = {
+        .name           = "aes",
+};
+static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
+        { .irq = 102 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_aes0_hwmod = {
+        .name           = "aes0",
+        .class          = &am33xx_aes_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_aes0_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* sha0 */
+static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
+        .name           = "sha0",
+};
+static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
+        { .irq = 108 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_sha0_hwmod = {
+        .name           = "sha0",
+        .class          = &am33xx_sha0_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_sha0_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+#endif
+/* 'smartreflex' class */
+static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
+        .name           = "smartreflex",
+};
+/* smartreflex0 */
+static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
+        { .irq = 120 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_smartreflex0_hwmod = {
+        .name           = "smartreflex0",
+        .class          = &am33xx_smartreflex_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_smartreflex0_irqs,
+        .main_clk       = "smartreflex0_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* smartreflex1 */
+static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
+        { .irq = 121 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_smartreflex1_hwmod = {
+        .name           = "smartreflex1",
+        .class          = &am33xx_smartreflex_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_smartreflex1_irqs,
+        .main_clk       = "smartreflex1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'control' module class
+ */
+static struct omap_hwmod_class am33xx_control_hwmod_class = {
+        .name           = "control",
+};
+static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
+        { .irq = 8 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_control_hwmod = {
+        .name           = "control",
+        .class          = &am33xx_control_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_control_irqs,
+        .main_clk       = "dpll_core_m4_div2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'cpgmac' class
+ * cpsw/cpgmac sub system
+ */
+static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x8,
+        .syss_offs      = 0x4,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+                           MSTANDBY_NO),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
+        .name           = "cpgmac0",
+        .sysc           = &am33xx_cpgmac_sysc,
+};
+static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
+        { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
+        { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
+        { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
+        { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_cpgmac0_hwmod = {
+        .name           = "cpgmac0",
+        .class          = &am33xx_cpgmac0_hwmod_class,
+        .clkdm_name     = "cpsw_125mhz_clkdm",
+        .mpu_irqs       = am33xx_cpgmac0_irqs,
+        .main_clk       = "cpsw_125mhz_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * dcan class
+ */
+static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
+        .name = "d_can",
+};
+/* dcan0 */
+static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
+        { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
+        { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_dcan0_hwmod = {
+        .name           = "d_can0",
+        .class          = &am33xx_dcan_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_dcan0_irqs,
+        .main_clk       = "dcan0_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* dcan1 */
+static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
+        { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
+        { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_dcan1_hwmod = {
+        .name           = "d_can1",
+        .class          = &am33xx_dcan_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_dcan1_irqs,
+        .main_clk       = "dcan1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* elm */
+static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                        SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class am33xx_elm_hwmod_class = {
+        .name           = "elm",
+        .sysc           = &am33xx_elm_sysc,
+};
+static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
+        { .irq = 4 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_elm_hwmod = {
+        .name           = "elm",
+        .class          = &am33xx_elm_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_elm_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'epwmss' class: ecap0,1,2,  ehrpwm0,1,2
+ */
+static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x4,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                        SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                        MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
+        .name           = "epwmss",
+        .sysc           = &am33xx_epwmss_sysc,
+};
+/* ehrpwm0 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
+        { .name = "int", .irq = 86 + OMAP_INTC_START, },
+        { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
+        .name           = "ehrpwm0",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ehrpwm0_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* ehrpwm1 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
+        { .name = "int", .irq = 87 + OMAP_INTC_START, },
+        { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
+        .name           = "ehrpwm1",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ehrpwm1_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* ehrpwm2 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
+        { .name = "int", .irq = 39 + OMAP_INTC_START, },
+        { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
+        .name           = "ehrpwm2",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ehrpwm2_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* ecap0 */
+static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
+        { .irq = 31 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_ecap0_hwmod = {
+        .name           = "ecap0",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ecap0_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* ecap1 */
+static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
+        { .irq = 47 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_ecap1_hwmod = {
+        .name           = "ecap1",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ecap1_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* ecap2 */
+static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
+        { .irq = 61 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_ecap2_hwmod = {
+        .name           = "ecap2",
+        .mpu_irqs       = am33xx_ecap2_irqs,
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'gpio' class: for gpio 0,1,2,3
+ */
+static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0114,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                          SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                          SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
+        .name           = "gpio",
+        .sysc           = &am33xx_gpio_sysc,
+        .rev            = 2,
+};
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width     = 32,
+        .dbck_flag      = true,
+};
+/* gpio0 */
+static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio0_dbclk" },
+};
+static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
+        { .irq = 96 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_gpio0_hwmod = {
+        .name           = "gpio1",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = am33xx_gpio0_irqs,
+        .main_clk       = "dpll_core_m4_div2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio0_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+/* gpio1 */
+static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
+        { .irq = 98 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+static struct omap_hwmod am33xx_gpio1_hwmod = {
+        .name           = "gpio2",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = am33xx_gpio1_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+/* gpio2 */
+static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
+        { .irq = 32 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+static struct omap_hwmod am33xx_gpio2_hwmod = {
+        .name           = "gpio3",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = am33xx_gpio2_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+/* gpio3 */
+static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
+        { .irq = 62 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+static struct omap_hwmod am33xx_gpio3_hwmod = {
+        .name           = "gpio4",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = am33xx_gpio3_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+/* gpmc */
+static struct omap_hwmod_class_sysconfig gpmc_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
+        .name           = "gpmc",
+        .sysc           = &gpmc_sysc,
+};
+static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
+        { .irq = 100 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &am33xx_gpmc_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_gpmc_irqs,
+        .main_clk       = "l3s_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* 'i2c' class */
+static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0090,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class i2c_class = {
+        .name           = "i2c",
+        .sysc           = &am33xx_i2c_sysc,
+        .rev            = OMAP_I2C_IP_VERSION_2,
+        .reset          = &omap_i2c_reset,
+};
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+        .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
+                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
+};
+/* i2c1 */
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+        { .irq = 70 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
+        { .name = "tx", .dma_req = 0, },
+        { .name = "rx", .dma_req = 0, },
+        { .dma_req = -1 }
+};
+static struct omap_hwmod am33xx_i2c1_hwmod = {
+        .name           = "i2c1",
+        .class          = &i2c_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = i2c1_mpu_irqs,
+        .sdma_reqs      = i2c1_edma_reqs,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+/* i2c1 */
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+        { .irq = 71 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
+        { .name = "tx", .dma_req = 0, },
+        { .name = "rx", .dma_req = 0, },
+        { .dma_req = -1 }
+};
+static struct omap_hwmod am33xx_i2c2_hwmod = {
+        .name           = "i2c2",
+        .class          = &i2c_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = i2c2_mpu_irqs,
+        .sdma_reqs      = i2c2_edma_reqs,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_offs   = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+/* i2c3 */
+static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
+        { .name = "tx", .dma_req = 0, },
+        { .name = "rx", .dma_req = 0, },
+        { .dma_req = -1 }
+};
+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+        { .irq = 30 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_i2c3_hwmod = {
+        .name           = "i2c3",
+        .class          = &i2c_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = i2c3_mpu_irqs,
+        .sdma_reqs      = i2c3_edma_reqs,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+/* lcdc */
+static struct omap_hwmod_class_sysconfig lcdc_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x54,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
+        .name           = "lcdc",
+        .sysc           = &lcdc_sysc,
+};
+static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
+        { .irq = 36 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_lcdc_hwmod = {
+        .name           = "lcdc",
+        .class          = &am33xx_lcdc_hwmod_class,
+        .clkdm_name     = "lcdc_clkdm",
+        .mpu_irqs       = am33xx_lcdc_irqs,
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+        .main_clk       = "lcd_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
+        .name   = "mailbox",
+        .sysc   = &am33xx_mailbox_sysc,
+};
+static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
+        { .irq = 77 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &am33xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_mailbox_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'mcasp' class
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x4,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
+        .name           = "mcasp",
+        .sysc           = &am33xx_mcasp_sysc,
+};
+/* mcasp0 */
+static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
+        { .name = "ax", .irq = 80 + OMAP_INTC_START, },
+        { .name = "ar", .irq = 81 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
+        { .name = "tx", .dma_req = 8, },
+        { .name = "rx", .dma_req = 9, },
+        { .dma_req = -1 }
+};
+static struct omap_hwmod am33xx_mcasp0_hwmod = {
+        .name           = "mcasp0",
+        .class          = &am33xx_mcasp_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .mpu_irqs       = am33xx_mcasp0_irqs,
+        .sdma_reqs      = am33xx_mcasp0_edma_reqs,
+        .main_clk       = "mcasp0_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* mcasp1 */
+static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
+        { .name = "ax", .irq = 82 + OMAP_INTC_START, },
+        { .name = "ar", .irq = 83 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
+        { .name = "tx", .dma_req = 10, },
+        { .name = "rx", .dma_req = 11, },
+        { .dma_req = -1 }
+};
+static struct omap_hwmod am33xx_mcasp1_hwmod = {
+        .name           = "mcasp1",
+        .class          = &am33xx_mcasp_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .mpu_irqs       = am33xx_mcasp1_irqs,
+        .sdma_reqs      = am33xx_mcasp1_edma_reqs,
+        .main_clk       = "mcasp1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* 'mmc' class */
+static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
+        .rev_offs       = 0x1fc,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                          SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
+        .name           = "mmc",
+        .sysc           = &am33xx_mmc_sysc,
+};
+/* mmc0 */
+static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
+        { .irq = 64 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
+        { .name = "tx", .dma_req = 24, },
+        { .name = "rx", .dma_req = 25, },
+        { .dma_req = -1 }
+};
+static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
+        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+static struct omap_hwmod am33xx_mmc0_hwmod = {
+        .name           = "mmc1",
+        .class          = &am33xx_mmc_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_mmc0_irqs,
+        .sdma_reqs      = am33xx_mmc0_edma_reqs,
+        .main_clk       = "mmc_clk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &am33xx_mmc0_dev_attr,
+};
+/* mmc1 */
+static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
+        { .irq = 28 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
+        { .name = "tx", .dma_req = 2, },
+        { .name = "rx", .dma_req = 3, },
+        { .dma_req = -1 }
+};
+static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
+        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+static struct omap_hwmod am33xx_mmc1_hwmod = {
+        .name           = "mmc2",
+        .class          = &am33xx_mmc_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_mmc1_irqs,
+        .sdma_reqs      = am33xx_mmc1_edma_reqs,
+        .main_clk       = "mmc_clk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &am33xx_mmc1_dev_attr,
+};
+/* mmc2 */
+static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
+        { .irq = 29 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
+        { .name = "tx", .dma_req = 64, },
+        { .name = "rx", .dma_req = 65, },
+        { .dma_req = -1 }
+};
+static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
+        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+static struct omap_hwmod am33xx_mmc2_hwmod = {
+        .name           = "mmc3",
+        .class          = &am33xx_mmc_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .mpu_irqs       = am33xx_mmc2_irqs,
+        .sdma_reqs      = am33xx_mmc2_edma_reqs,
+        .main_clk       = "mmc_clk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &am33xx_mmc2_dev_attr,
+};
+/*
+ * 'rtc' class
+ * rtc subsystem
+ */
+static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
+        .rev_offs       = 0x0074,
+        .sysc_offs      = 0x0078,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
+                          SIDLE_SMART | SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
+        .name           = "rtc",
+        .sysc           = &am33xx_rtc_sysc,
+};
+static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
+        { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
+        { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_rtc_hwmod = {
+        .name           = "rtc",
+        .class          = &am33xx_rtc_hwmod_class,
+        .clkdm_name     = "l4_rtc_clkdm",
+        .mpu_irqs       = am33xx_rtc_irqs,
+        .main_clk       = "clk_32768_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* 'spi' class */
+static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0110,
+        .syss_offs      = 0x0114,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                          SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class am33xx_spi_hwmod_class = {
+        .name           = "mcspi",
+        .sysc           = &am33xx_mcspi_sysc,
+        .rev            = OMAP4_MCSPI_REV,
+};
+/* spi0 */
+static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
+        { .irq = 65 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
+        { .name = "rx0", .dma_req = 17 },
+        { .name = "tx0", .dma_req = 16 },
+        { .name = "rx1", .dma_req = 19 },
+        { .name = "tx1", .dma_req = 18 },
+        { .dma_req = -1 }
+};
+static struct omap2_mcspi_dev_attr mcspi_attrib = {
+        .num_chipselect = 2,
+};
+static struct omap_hwmod am33xx_spi0_hwmod = {
+        .name           = "spi0",
+        .class          = &am33xx_spi_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_spi0_irqs,
+        .sdma_reqs      = am33xx_mcspi0_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi_attrib,
+};
+/* spi1 */
+static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
+        { .irq = 125 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
+        { .name = "rx0", .dma_req = 43 },
+        { .name = "tx0", .dma_req = 42 },
+        { .name = "rx1", .dma_req = 45 },
+        { .name = "tx1", .dma_req = 44 },
+        { .dma_req = -1 }
+};
+static struct omap_hwmod am33xx_spi1_hwmod = {
+        .name           = "spi1",
+        .class          = &am33xx_spi_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_spi1_irqs,
+        .sdma_reqs      = am33xx_mcspi1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi_attrib,
+};
+/*
+ * 'spinlock' class
+ * spinlock provides hardware assistance for synchronizing the
+ * processes running on multiple processors
+ */
+static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
+        .name           = "spinlock",
+};
+static struct omap_hwmod am33xx_spinlock_hwmod = {
+        .name           = "spinlock",
+        .class          = &am33xx_spinlock_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* 'timer 2-7' class */
+static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class am33xx_timer_hwmod_class = {
+        .name           = "timer",
+        .sysc           = &am33xx_timer_sysc,
+};
+/* timer1 1ms */
+static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                        SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
+        .name           = "timer",
+        .sysc           = &am33xx_timer1ms_sysc,
+};
+static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
+        { .irq = 67 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_timer1_hwmod = {
+        .name           = "timer1",
+        .class          = &am33xx_timer1ms_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_timer1_irqs,
+        .main_clk       = "timer1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
+        { .irq = 68 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_timer2_hwmod = {
+        .name           = "timer2",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer2_irqs,
+        .main_clk       = "timer2_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
+        { .irq = 69 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_timer3_hwmod = {
+        .name           = "timer3",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer3_irqs,
+        .main_clk       = "timer3_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
+        { .irq = 92 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_timer4_hwmod = {
+        .name           = "timer4",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer4_irqs,
+        .main_clk       = "timer4_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
+        { .irq = 93 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_timer5_hwmod = {
+        .name           = "timer5",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer5_irqs,
+        .main_clk       = "timer5_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
+        { .irq = 94 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_timer6_hwmod = {
+        .name           = "timer6",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer6_irqs,
+        .main_clk       = "timer6_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
+        { .irq = 95 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_timer7_hwmod = {
+        .name           = "timer7",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer7_irqs,
+        .main_clk       = "timer7_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* tpcc */
+static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
+        .name           = "tpcc",
+};
+static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
+        { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
+        { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
+        { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_tpcc_hwmod = {
+        .name           = "tpcc",
+        .class          = &am33xx_tpcc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_tpcc_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                          SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+/* 'tptc' class */
+static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
+        .name           = "tptc",
+        .sysc           = &am33xx_tptc_sysc,
+};
+/* tptc0 */
+static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
+        { .irq = 112 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_tptc0_hwmod = {
+        .name           = "tptc0",
+        .class          = &am33xx_tptc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_tptc0_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* tptc1 */
+static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
+        { .irq = 113 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_tptc1_hwmod = {
+        .name           = "tptc1",
+        .class          = &am33xx_tptc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_tptc1_irqs,
+        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* tptc2 */
+static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
+        { .irq = 114 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_tptc2_hwmod = {
+        .name           = "tptc2",
+        .class          = &am33xx_tptc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_tptc2_irqs,
+        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* 'uart' class */
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+                          SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class uart_class = {
+        .name           = "uart",
+        .sysc           = &uart_sysc,
+};
+/* uart1 */
+static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
+        { .name = "tx", .dma_req = 26, },
+        { .name = "rx", .dma_req = 27, },
+        { .dma_req = -1 }
+};
+static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
+        { .irq = 72 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_uart1_hwmod = {
+        .name           = "uart1",
+        .class          = &uart_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_uart1_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
+        { .irq = 73 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_uart2_hwmod = {
+        .name           = "uart2",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart2_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* uart3 */
+static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
+        { .name = "tx", .dma_req = 30, },
+        { .name = "rx", .dma_req = 31, },
+        { .dma_req = -1 }
+};
+static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
+        { .irq = 74 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_uart3_hwmod = {
+        .name           = "uart3",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart3_irqs,
+        .sdma_reqs      = uart3_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
+        { .irq = 44 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_uart4_hwmod = {
+        .name           = "uart4",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart4_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
+        { .irq = 45 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_uart5_hwmod = {
+        .name           = "uart5",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart5_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
+        { .irq = 46 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_uart6_hwmod = {
+        .name           = "uart6",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart6_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* 'wd_timer' class */
+static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
+        .name           = "wd_timer",
+};
+/*
+ * XXX: device.c file uses hardcoded name for watchdog timer
+ * driver "wd_timer2, so we are also using same name as of now...
+ */
+static struct omap_hwmod am33xx_wd_timer1_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &am33xx_wd_timer_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .main_clk       = "wdt1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'usb_otg' class
+ * high-speed on-the-go universal serial bus (usb_otg) controller
+ */
+static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class am33xx_usbotg_class = {
+        .name           = "usbotg",
+        .sysc           = &am33xx_usbhsotg_sysc,
+};
+static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
+        { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
+        { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
+        { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
+        { .irq = -1 + OMAP_INTC_START, },
+};
+static struct omap_hwmod am33xx_usbss_hwmod = {
+        .name           = "usb_otg_hs",
+        .class          = &am33xx_usbotg_class,
+        .clkdm_name     = "l3s_clkdm",
+        .mpu_irqs       = am33xx_usbss_mpu_irqs,
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+        .main_clk       = "usbotg_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * Interfaces
+ */
+/* l4 fw -> emif fw */
+static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
+        .master         = &am33xx_l4_fw_hwmod,
+        .slave          = &am33xx_emif_fw_hwmod,
+        .clk            = "l4fw_gclk",
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
+        {
+                .pa_start       = 0x4c000000,
+                .pa_end         = 0x4c000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3 main -> emif */
+static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_emif_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .addr           = am33xx_emif_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* mpu -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
+        .master         = &am33xx_mpu_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "dpll_mpu_m2_ck",
+        .user           = OCP_USER_MPU,
+};
+/* l3 main -> l4 hs */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_l4_hs_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3 main -> l3 s */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_l3_s_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3 s -> l4 per/ls */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l4_ls_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3 s -> l4 wkup */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l4_wkup_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3 s -> l4 fw */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l4_fw_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3 main -> l3 instr */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_l3_instr_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* mpu -> prcm */
+static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
+        .master         = &am33xx_mpu_hwmod,
+        .slave          = &am33xx_prcm_hwmod,
+        .clk            = "dpll_mpu_m2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3 s -> l3 main*/
+static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* pru-icss -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
+        .master         = &am33xx_pruss_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "l3_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* wkup m3 -> l4 wkup */
+static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
+        .master         = &am33xx_wkup_m3_hwmod,
+        .slave          = &am33xx_l4_wkup_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* gfx -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
+        .master         = &am33xx_gfx_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4 wkup -> wkup m3 */
+static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
+        {
+                .name           = "umem",
+                .pa_start       = 0x44d00000,
+                .pa_end         = 0x44d00000 + SZ_16K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "dmem",
+                .pa_start       = 0x44d80000,
+                .pa_end         = 0x44d80000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_wkup_m3_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_wkup_m3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4 hs -> pru-icss */
+static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
+        {
+                .pa_start       = 0x4a300000,
+                .pa_end         = 0x4a300000 + SZ_512K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
+        .master         = &am33xx_l4_hs_hwmod,
+        .slave          = &am33xx_pruss_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .addr           = am33xx_pruss_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3 main -> gfx */
+static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
+        {
+                .pa_start       = 0x56000000,
+                .pa_end         = 0x56000000 + SZ_16M - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_gfx_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .addr           = am33xx_gfx_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4 wkup -> smartreflex0 */
+static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
+        {
+                .pa_start       = 0x44e37000,
+                .pa_end         = 0x44e37000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_smartreflex0_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_smartreflex0_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* l4 wkup -> smartreflex1 */
+static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
+        {
+                .pa_start       = 0x44e39000,
+                .pa_end         = 0x44e39000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_smartreflex1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_smartreflex1_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* l4 wkup -> control */
+static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
+        {
+                .pa_start       = 0x44e10000,
+                .pa_end         = 0x44e10000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_control_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_control_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* l4 wkup -> rtc */
+static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
+        {
+                .pa_start       = 0x44e3e000,
+                .pa_end         = 0x44e3e000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_rtc_hwmod,
+        .clk            = "clkdiv32k_ick",
+        .addr           = am33xx_rtc_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* l4 per/ls -> DCAN0 */
+static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
+        {
+                .pa_start       = 0x481CC000,
+                .pa_end         = 0x481CC000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_dcan0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_dcan0_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4 per/ls -> DCAN1 */
+static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
+        {
+                .pa_start       = 0x481D0000,
+                .pa_end         = 0x481D0000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_dcan1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_dcan1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4 per/ls -> GPIO2 */
+static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
+        {
+                .pa_start       = 0x4804C000,
+                .pa_end         = 0x4804C000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_gpio1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_gpio1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4 per/ls -> gpio3 */
+static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
+        {
+                .pa_start       = 0x481AC000,
+                .pa_end         = 0x481AC000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_gpio2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_gpio2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4 per/ls -> gpio4 */
+static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
+        {
+                .pa_start       = 0x481AE000,
+                .pa_end         = 0x481AE000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_gpio3_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_gpio3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4 WKUP -> I2C1 */
+static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
+        {
+                .pa_start       = 0x44E0B000,
+                .pa_end         = 0x44E0B000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_i2c1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_i2c1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* L4 WKUP -> GPIO1 */
+static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
+        {
+                .pa_start       = 0x44E07000,
+                .pa_end         = 0x44E07000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_gpio0_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_gpio0_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4 WKUP -> ADC_TSC */
+static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
+        {
+                .pa_start       = 0x44E0D000,
+                .pa_end         = 0x44E0D000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_adc_tsc_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_adc_tsc_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
+        /* cpsw ss */
+        {
+                .pa_start       = 0x4a100000,
+                .pa_end         = 0x4a100000 + SZ_2K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        /* cpsw wr */
+        {
+                .pa_start       = 0x4a101200,
+                .pa_end         = 0x4a101200 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
+        .master         = &am33xx_l4_hs_hwmod,
+        .slave          = &am33xx_cpgmac0_hwmod,
+        .clk            = "cpsw_125mhz_gclk",
+        .addr           = am33xx_cpgmac0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
+        {
+                .pa_start       = 0x48080000,
+                .pa_end         = 0x48080000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_elm_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_elm_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
+        {
+                .pa_start       = 0x48300000,
+                .pa_end         = 0x48300000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48300200,
+                .pa_end         = 0x48300200 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ehrpwm0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ehrpwm0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
+        {
+                .pa_start       = 0x48302000,
+                .pa_end         = 0x48302000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48302200,
+                .pa_end         = 0x48302200 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ehrpwm1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ehrpwm1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
+        {
+                .pa_start       = 0x48304000,
+                .pa_end         = 0x48304000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48304200,
+                .pa_end         = 0x48304200 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ehrpwm2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ehrpwm2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
+        {
+                .pa_start       = 0x48300000,
+                .pa_end         = 0x48300000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48300100,
+                .pa_end         = 0x48300100 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ecap0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ecap0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
+        {
+                .pa_start       = 0x48302000,
+                .pa_end         = 0x48302000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48302100,
+                .pa_end         = 0x48302100 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ecap1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ecap1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
+        {
+                .pa_start       = 0x48304000,
+                .pa_end         = 0x48304000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48304100,
+                .pa_end         = 0x48304100 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ecap2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ecap2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l3s cfg -> gpmc */
+static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
+        {
+                .pa_start       = 0x50000000,
+                .pa_end         = 0x50000000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_gpmc_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_gpmc_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* i2c2 */
+static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
+        {
+                .pa_start       = 0x4802A000,
+                .pa_end         = 0x4802A000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_i2c2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_i2c2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
+        {
+                .pa_start       = 0x4819C000,
+                .pa_end         = 0x4819C000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_i2c3_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_i2c3_addr_space,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
+        {
+                .pa_start       = 0x4830E000,
+                .pa_end         = 0x4830E000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_lcdc_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .addr           = am33xx_lcdc_addr_space,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x480C8000,
+                .pa_end         = 0x480C8000 + (SZ_4K - 1),
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4 ls -> mailbox */
+static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mailbox_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mailbox_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* l4 ls -> spinlock */
+static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
+        {
+                .pa_start       = 0x480Ca000,
+                .pa_end         = 0x480Ca000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_spinlock_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_spinlock_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* l4 ls -> mcasp0 */
+static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
+        {
+                .pa_start       = 0x48038000,
+                .pa_end         = 0x48038000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mcasp0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mcasp0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l3 s -> mcasp0 data */
+static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
+        {
+                .pa_start       = 0x46000000,
+                .pa_end         = 0x46000000 + SZ_4M - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_mcasp0_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_mcasp0_data_addr_space,
+        .user           = OCP_USER_SDMA,
+};
+/* l4 ls -> mcasp1 */
+static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
+        {
+                .pa_start       = 0x4803C000,
+                .pa_end         = 0x4803C000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mcasp1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mcasp1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l3 s -> mcasp1 data */
+static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
+        {
+                .pa_start       = 0x46400000,
+                .pa_end         = 0x46400000 + SZ_4M - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_mcasp1_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_mcasp1_data_addr_space,
+        .user           = OCP_USER_SDMA,
+};
+/* l4 ls -> mmc0 */
+static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
+        {
+                .pa_start       = 0x48060100,
+                .pa_end         = 0x48060100 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mmc0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mmc0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 ls -> mmc1 */
+static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
+        {
+                .pa_start       = 0x481d8100,
+                .pa_end         = 0x481d8100 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mmc1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mmc1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l3 s -> mmc2 */
+static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
+        {
+                .pa_start       = 0x47810100,
+                .pa_end         = 0x47810100 + SZ_64K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_mmc2_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_mmc2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 ls -> mcspi0 */
+static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
+        {
+                .pa_start       = 0x48030000,
+                .pa_end         = 0x48030000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_spi0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mcspi0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 ls -> mcspi1 */
+static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
+        {
+                .pa_start       = 0x481A0000,
+                .pa_end         = 0x481A0000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_spi1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mcspi1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 wkup -> timer1 */
+static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
+        {
+                .pa_start       = 0x44E31000,
+                .pa_end         = 0x44E31000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_timer1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_timer1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 per -> timer2 */
+static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
+        {
+                .pa_start       = 0x48040000,
+                .pa_end         = 0x48040000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 per -> timer3 */
+static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
+        {
+                .pa_start       = 0x48042000,
+                .pa_end         = 0x48042000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer3_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer3_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 per -> timer4 */
+static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
+        {
+                .pa_start       = 0x48044000,
+                .pa_end         = 0x48044000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer4_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer4_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 per -> timer5 */
+static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
+        {
+                .pa_start       = 0x48046000,
+                .pa_end         = 0x48046000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer5_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer5_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 per -> timer6 */
+static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
+        {
+                .pa_start       = 0x48048000,
+                .pa_end         = 0x48048000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer6_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer6_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 per -> timer7 */
+static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
+        {
+                .pa_start       = 0x4804A000,
+                .pa_end         = 0x4804A000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer7_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer7_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l3 main -> tpcc */
+static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
+        {
+                .pa_start       = 0x49000000,
+                .pa_end         = 0x49000000 + SZ_32K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tpcc_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tpcc_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l3 main -> tpcc0 */
+static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
+        {
+                .pa_start       = 0x49800000,
+                .pa_end         = 0x49800000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tptc0_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tptc0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l3 main -> tpcc1 */
+static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
+        {
+                .pa_start       = 0x49900000,
+                .pa_end         = 0x49900000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tptc1_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tptc1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l3 main -> tpcc2 */
+static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
+        {
+                .pa_start       = 0x49a00000,
+                .pa_end         = 0x49a00000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tptc2_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tptc2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 wkup -> uart1 */
+static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
+        {
+                .pa_start       = 0x44E09000,
+                .pa_end         = 0x44E09000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_uart1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_uart1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 ls -> uart2 */
+static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
+        {
+                .pa_start       = 0x48022000,
+                .pa_end         = 0x48022000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 ls -> uart3 */
+static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
+        {
+                .pa_start       = 0x48024000,
+                .pa_end         = 0x48024000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart3_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart3_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 ls -> uart4 */
+static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
+        {
+                .pa_start       = 0x481A6000,
+                .pa_end         = 0x481A6000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart4_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart4_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 ls -> uart5 */
+static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
+        {
+                .pa_start       = 0x481A8000,
+                .pa_end         = 0x481A8000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart5_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart5_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 ls -> uart6 */
+static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
+        {
+                .pa_start       = 0x481aa000,
+                .pa_end         = 0x481aa000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart6_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart6_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* l4 wkup -> wd_timer1 */
+static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
+        {
+                .pa_start       = 0x44e35000,
+                .pa_end         = 0x44e35000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_wd_timer1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_wd_timer1_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* usbss */
+/* l3 s -> USBSS interface */
+static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
+        {
+                .name           = "usbss",
+                .pa_start       = 0x47400000,
+                .pa_end         = 0x47400000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "musb0",
+                .pa_start       = 0x47401000,
+                .pa_end         = 0x47401000 + SZ_2K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "musb1",
+                .pa_start       = 0x47401800,
+                .pa_end         = 0x47401800 + SZ_2K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_usbss_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_usbss_addr_space,
+        .user           = OCP_USER_MPU,
+        .flags          = OCPIF_SWSUP_IDLE,
+};
+static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
+        &am33xx_l4_fw__emif_fw,
+        &am33xx_l3_main__emif,
+        &am33xx_mpu__l3_main,
+        &am33xx_mpu__prcm,
+        &am33xx_l3_s__l4_ls,
+        &am33xx_l3_s__l4_wkup,
+        &am33xx_l3_s__l4_fw,
+        &am33xx_l3_main__l4_hs,
+        &am33xx_l3_main__l3_s,
+        &am33xx_l3_main__l3_instr,
+        &am33xx_l3_main__gfx,
+        &am33xx_l3_s__l3_main,
+        &am33xx_pruss__l3_main,
+        &am33xx_wkup_m3__l4_wkup,
+        &am33xx_gfx__l3_main,
+        &am33xx_l4_wkup__wkup_m3,
+        &am33xx_l4_wkup__control,
+        &am33xx_l4_wkup__smartreflex0,
+        &am33xx_l4_wkup__smartreflex1,
+        &am33xx_l4_wkup__uart1,
+        &am33xx_l4_wkup__timer1,
+        &am33xx_l4_wkup__rtc,
+        &am33xx_l4_wkup__i2c1,
+        &am33xx_l4_wkup__gpio0,
+        &am33xx_l4_wkup__adc_tsc,
+        &am33xx_l4_wkup__wd_timer1,
+        &am33xx_l4_hs__pruss,
+        &am33xx_l4_per__dcan0,
+        &am33xx_l4_per__dcan1,
+        &am33xx_l4_per__gpio1,
+        &am33xx_l4_per__gpio2,
+        &am33xx_l4_per__gpio3,
+        &am33xx_l4_per__i2c2,
+        &am33xx_l4_per__i2c3,
+        &am33xx_l4_per__mailbox,
+        &am33xx_l4_ls__mcasp0,
+        &am33xx_l3_s__mcasp0_data,
+        &am33xx_l4_ls__mcasp1,
+        &am33xx_l3_s__mcasp1_data,
+        &am33xx_l4_ls__mmc0,
+        &am33xx_l4_ls__mmc1,
+        &am33xx_l3_s__mmc2,
+        &am33xx_l4_ls__timer2,
+        &am33xx_l4_ls__timer3,
+        &am33xx_l4_ls__timer4,
+        &am33xx_l4_ls__timer5,
+        &am33xx_l4_ls__timer6,
+        &am33xx_l4_ls__timer7,
+        &am33xx_l3_main__tpcc,
+        &am33xx_l4_ls__uart2,
+        &am33xx_l4_ls__uart3,
+        &am33xx_l4_ls__uart4,
+        &am33xx_l4_ls__uart5,
+        &am33xx_l4_ls__uart6,
+        &am33xx_l4_ls__spinlock,
+        &am33xx_l4_ls__elm,
+        &am33xx_l4_ls__ehrpwm0,
+        &am33xx_l4_ls__ehrpwm1,
+        &am33xx_l4_ls__ehrpwm2,
+        &am33xx_l4_ls__ecap0,
+        &am33xx_l4_ls__ecap1,
+        &am33xx_l4_ls__ecap2,
+        &am33xx_l3_s__gpmc,
+        &am33xx_l3_main__lcdc,
+        &am33xx_l4_ls__mcspi0,
+        &am33xx_l4_ls__mcspi1,
+        &am33xx_l3_main__tptc0,
+        &am33xx_l3_main__tptc1,
+        &am33xx_l3_main__tptc2,
+        &am33xx_l3_s__usbss,
+        &am33xx_l4_hs__cpgmac0,
+        NULL,
+};
+int __init am33xx_hwmod_init(void)
+{
+        omap_hwmod_init();
+        return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index ce7e6068768f..f67b7ee07dd4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -15,26 +15,27 @@
 * XXX these should be marked initdata for multi-OMAP kernels
 */
 #include <linux/power/smartreflex.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <plat/omap_hwmod.h>
-#include <mach/irqs.h>
-#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
-#include <plat/l3_3xxx.h>
+#include "l3_3xxx.h"
-#include <plat/l4_3xxx.h>
+#include "l4_3xxx.h"
 #include <plat/i2c.h>
-#include <plat/gpio.h>
 #include <plat/mmc.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/dmtimer.h>
+#include <plat/iommu.h>
+#include "am35xx.h"
+#include "soc.h"
 #include "omap_hwmod_common_data.h"
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
 #include "wd_timer.h"
-#include <mach/am35xx.h>
 /*
 * OMAP3xxx hardware module integration data
@@ -51,9 +52,9 @@
 /* L3 */
 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
-        { .irq = INT_34XX_L3_DBG_IRQ },
+        { .irq = 9 + OMAP_INTC_START, },
-        { .irq = INT_34XX_L3_APP_IRQ },
+        { .irq = 10 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
@@ -92,8 +93,14 @@ static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
 };
 /* MPU */
+static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
+        { .name = "pmu", .irq = 3 + OMAP_INTC_START },
+        { .irq = -1 }
+};
 static struct omap_hwmod omap3xxx_mpu_hwmod = {
        .name           = "mpu",
+        .mpu_irqs       = omap3xxx_mpu_irqs,
        .class          = &mpu_hwmod_class,
        .main_clk       = "arm_fck",
 };
@@ -123,6 +130,24 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
        },
 };
+/*
+ * 'debugss' class
+ * debug and emulation sub system
+ */
+static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
+        .name   = "debugss",
+};
+/* debugss */
+static struct omap_hwmod omap3xxx_debugss_hwmod = {
+        .name           = "debugss",
+        .class          = &omap3xxx_debugss_hwmod_class,
+        .clkdm_name     = "emu_clkdm",
+        .main_clk       = "emu_src_ck",
+        .flags          = HWMOD_NO_IDLEST,
+};
 /* timer class */
 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
        .rev_offs       = 0x0000,
@@ -170,6 +195,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
        .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+/* pwm timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+};
 /* timer1 */
 static struct omap_hwmod omap3xxx_timer1_hwmod = {
        .name           = "timer1",
@@ -253,6 +288,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
                },
        },
+        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
 };
@@ -270,6 +306,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
                },
        },
+        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
 };
@@ -287,6 +324,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
                },
        },
+        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
 };
@@ -304,7 +342,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
                },
        },
-        .dev_attr       = &capability_pwm_dev_attr,
+        .dev_attr       = &capability_dsp_pwm_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
 };
@@ -364,8 +402,8 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
 /* timer12 */
 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
-        { .irq = 95, },
+        { .irq = 95 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap3xxx_timer12_hwmod = {
@@ -499,8 +537,8 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
 /* UART4 */
 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
-        { .irq = INT_36XX_UART4_IRQ, },
+        { .irq = 80 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
@@ -527,8 +565,8 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
 };
 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
-        { .irq = INT_35XX_UART4_IRQ, },
+        { .irq = 84 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
@@ -683,8 +721,8 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 };
 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
-        { .irq = 25 },
+        { .irq = 25 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 /* dss_dsi1 */
@@ -813,8 +851,8 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = {
 };
 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
-        { .irq = INT_34XX_I2C3_IRQ, },
+        { .irq = 61 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
@@ -972,8 +1010,8 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 /* gpio5 */
 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
-        { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
+        { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
@@ -1002,8 +1040,8 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 /* gpio6 */
 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
-        { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
+        { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
@@ -1107,10 +1145,10 @@ static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
-        { .name = "common", .irq = 16 },
+        { .name = "common", .irq = 16 + OMAP_INTC_START, },
-        { .name = "tx", .irq = 59 },
+        { .name = "tx", .irq = 59 + OMAP_INTC_START, },
-        { .name = "rx", .irq = 60 },
+        { .name = "rx", .irq = 60 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
@@ -1134,10 +1172,10 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
 /* mcbsp2 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
-        { .name = "common", .irq = 17 },
+        { .name = "common", .irq = 17 + OMAP_INTC_START, },
-        { .name = "tx", .irq = 62 },
+        { .name = "tx", .irq = 62 + OMAP_INTC_START, },
-        { .name = "rx", .irq = 63 },
+        { .name = "rx", .irq = 63 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
@@ -1166,10 +1204,10 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
 /* mcbsp3 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
-        { .name = "common", .irq = 22 },
+        { .name = "common", .irq = 22 + OMAP_INTC_START, },
-        { .name = "tx", .irq = 89 },
+        { .name = "tx", .irq = 89 + OMAP_INTC_START, },
-        { .name = "rx", .irq = 90 },
+        { .name = "rx", .irq = 90 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
@@ -1198,10 +1236,10 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
 /* mcbsp4 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
-        { .name = "common", .irq = 23 },
+        { .name = "common", .irq = 23 + OMAP_INTC_START, },
-        { .name = "tx", .irq = 54 },
+        { .name = "tx", .irq = 54 + OMAP_INTC_START, },
-        { .name = "rx", .irq = 55 },
+        { .name = "rx", .irq = 55 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
@@ -1231,10 +1269,10 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
 /* mcbsp5 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
-        { .name = "common", .irq = 27 },
+        { .name = "common", .irq = 27 + OMAP_INTC_START, },
-        { .name = "tx", .irq = 81 },
+        { .name = "tx", .irq = 81 + OMAP_INTC_START, },
-        { .name = "rx", .irq = 82 },
+        { .name = "rx", .irq = 82 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
@@ -1276,8 +1314,8 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
 /* mcbsp2_sidetone */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
-        { .name = "irq", .irq = 4 },
+        { .name = "irq", .irq = 4 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
@@ -1298,8 +1336,8 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
 /* mcbsp3_sidetone */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
-        { .name = "irq", .irq = 5 },
+        { .name = "irq", .irq = 5 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
@@ -1361,8 +1399,8 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = {
 };
 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
-        { .irq = 18 },
+        { .irq = 18 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap34xx_sr1_hwmod = {
@@ -1406,8 +1444,8 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = {
 };
 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
-        { .irq = 19 },
+        { .irq = 19 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap34xx_sr2_hwmod = {
@@ -1467,8 +1505,8 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
 };
 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
-        { .irq = 26 },
+        { .irq = 26 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
@@ -1558,8 +1596,8 @@ static struct omap_hwmod omap34xx_mcspi2 = {
 /* mcspi3 */
 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
-        { .name = "irq", .irq = 91 }, /* 91 */
+        { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
@@ -1594,8 +1632,8 @@ static struct omap_hwmod omap34xx_mcspi3 = {
 /* mcspi4 */
 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
-        { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
+        { .name = "irq", .irq = 48 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
@@ -1647,9 +1685,9 @@ static struct omap_hwmod_class usbotg_class = {
 /* usb_otg_hs */
 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
-        { .name = "mc", .irq = 92 },
+        { .name = "mc", .irq = 92 + OMAP_INTC_START, },
-        { .name = "dma", .irq = 93 },
+        { .name = "dma", .irq = 93 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
@@ -1679,8 +1717,8 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
 /* usb_otg_hs */
 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
-        { .name = "mc", .irq = 71 },
+        { .name = "mc", .irq = 71 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_class am35xx_usbotg_class = {
@@ -1715,8 +1753,8 @@ static struct omap_hwmod_class omap34xx_mmc_class = {
 /* MMC/SD/SDIO1 */
 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
-        { .irq = 83, },
+        { .irq = 83 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
@@ -1782,8 +1820,8 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
 /* MMC/SD/SDIO2 */
 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
-        { .irq = INT_24XX_MMC2_IRQ, },
+        { .irq = 86 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
@@ -1843,8 +1881,8 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
 /* MMC/SD/SDIO3 */
 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
-        { .irq = 94, },
+        { .irq = 94 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
@@ -1902,9 +1940,9 @@ static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
 };
 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
-        { .name = "ohci-irq", .irq = 76 },
+        { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
-        { .name = "ehci-irq", .irq = 77 },
+        { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
@@ -1996,8 +2034,8 @@ static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
 };
 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
-        { .name = "tll-irq", .irq = 78 },
+        { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
@@ -2033,6 +2071,33 @@ static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
        .class          = &omap2_hdq1w_class,
 };
+/* SAD2D */
+static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
+        { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
+        { .name = "rst_modem_sw", .rst_shift = 1 },
+};
+static struct omap_hwmod_class omap3xxx_sad2d_class = {
+        .name                   = "sad2d",
+};
+static struct omap_hwmod omap3xxx_sad2d_hwmod = {
+        .name           = "sad2d",
+        .rst_lines      = omap3xxx_sad2d_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
+        .main_clk       = "sad2d_ick",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_SAD2D_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
+                },
+        },
+        .class          = &omap3xxx_sad2d_class,
+};
 /*
 * '32K sync counter' class
 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
@@ -2068,6 +2133,49 @@ static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
 };
 /*
+ * 'gpmc' class
+ * general purpose memory controller
+ */
+static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
+        .name   = "gpmc",
+        .sysc   = &omap3xxx_gpmc_sysc,
+};
+static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
+        { .irq = 20 },
+        { .irq = -1 }
+};
+static struct omap_hwmod omap3xxx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &omap3xxx_gpmc_hwmod_class,
+        .clkdm_name     = "core_l3_clkdm",
+        .mpu_irqs       = omap3xxx_gpmc_irqs,
+        .main_clk       = "gpmc_fck",
+        /*
+         * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
+         * block.  It is not being added due to any known bugs with
+         * resetting the GPMC IP block, but rather because any timings
+         * set by the bootloader are not being correctly programmed by
+         * the kernel from the board file or DT data.
+         * HWMOD_INIT_NO_RESET should be removed ASAP.
+         */
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
+                           HWMOD_NO_IDLEST),
+};
+/*
 * interfaces
 */
@@ -2102,6 +2210,23 @@ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
        .user   = OCP_USER_MPU,
 };
+static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
+        {
+                .pa_start       = 0x54000000,
+                .pa_end         = 0x547fffff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+/* l3 -> debugss */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
+        .master         = &omap3xxx_l3_main_hwmod,
+        .slave          = &omap3xxx_debugss_hwmod,
+        .addr           = omap3xxx_l4_emu_addrs,
+        .user           = OCP_USER_MPU,
+};
 /* DSS -> l3 */
 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
        .master         = &omap3430es1_dss_core_hwmod,
@@ -2137,6 +2262,14 @@ static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
        .user           = OCP_USER_MPU,
 };
+/* l3_core -> sad2d interface */
+static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
+        .master         = &omap3xxx_sad2d_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
        .master = &omap3xxx_l4_core_hwmod,
@@ -2823,6 +2956,122 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+/*
+ * 'mmu' class
+ * The memory management unit performs virtual to physical address translation
+ * for its requestors.
+ */
+static struct omap_hwmod_class_sysconfig mmu_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
+        .name = "mmu",
+        .sysc = &mmu_sysc,
+};
+/* mmu isp */
+static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
+        .da_start       = 0x0,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 8,
+};
+static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
+        { .irq = 24 },
+        { .irq = -1 }
+};
+static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
+        {
+                .pa_start       = 0x480bd400,
+                .pa_end         = 0x480bd47f,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+/* l4_core -> mmu isp */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mmu_isp_hwmod,
+        .addr           = omap3xxx_mmu_isp_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
+        .name           = "mmu_isp",
+        .class          = &omap3xxx_mmu_hwmod_class,
+        .mpu_irqs       = omap3xxx_mmu_isp_irqs,
+        .main_clk       = "cam_ick",
+        .dev_attr       = &mmu_isp_dev_attr,
+        .flags          = HWMOD_NO_IDLEST,
+};
+#ifdef CONFIG_OMAP_IOMMU_IVA2
+/* mmu iva */
+static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
+        .da_start       = 0x11000000,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 32,
+};
+static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
+        { .irq = 28 },
+        { .irq = -1 }
+};
+static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
+        { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
+};
+static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
+        {
+                .pa_start       = 0x5d000000,
+                .pa_end         = 0x5d00007f,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+/* l3_main -> iva mmu */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
+        .master         = &omap3xxx_l3_main_hwmod,
+        .slave          = &omap3xxx_mmu_iva_hwmod,
+        .addr           = omap3xxx_mmu_iva_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
+        .name           = "mmu_iva",
+        .class          = &omap3xxx_mmu_hwmod_class,
+        .mpu_irqs       = omap3xxx_mmu_iva_irqs,
+        .rst_lines      = omap3xxx_mmu_iva_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
+        .main_clk       = "iva2_ck",
+        .prcm = {
+                .omap2 = {
+                        .module_offs = OMAP3430_IVA2_MOD,
+                },
+        },
+        .dev_attr       = &mmu_iva_dev_attr,
+        .flags          = HWMOD_NO_IDLEST,
+};
+#endif
 /* l4_per -> gpio4 */
 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
        {
@@ -3168,6 +3417,15 @@ static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
        { }
 };
+static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x6e000000,
+                .pa_end         = 0x6e000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
        .master         = &omap3xxx_l4_wkup_hwmod,
        .slave          = &omap3xxx_counter_32k_hwmod,
@@ -3223,11 +3481,11 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
 };
 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
-        { .name = "rxthresh",   .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ },
+        { .name = "rxthresh",   .irq = 67 + OMAP_INTC_START, },
-        { .name = "rx_pulse",   .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ },
+        { .name = "rx_pulse",   .irq = 68 + OMAP_INTC_START, },
-        { .name = "tx_pulse",   .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ },
+        { .name = "tx_pulse",   .irq = 69 + OMAP_INTC_START },
-        { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ },
+        { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
-        { .irq = -1 }
+        { .irq = -1 },
 };
 static struct omap_hwmod_class am35xx_emac_class = {
@@ -3277,10 +3535,19 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
        .user           = OCP_USER_MPU,
 };
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
+        .master         = &omap3xxx_l3_main_hwmod,
+        .slave          = &omap3xxx_gpmc_hwmod,
+        .clk            = "core_l3_ick",
+        .addr           = omap3xxx_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
        &omap3xxx_l3_main__l4_core,
        &omap3xxx_l3_main__l4_per,
        &omap3xxx_mpu__l3_main,
+        &omap3xxx_l3_main__l4_debugss,
        &omap3xxx_l4_core__l4_wkup,
        &omap3xxx_l4_core__mmc3,
        &omap3_l4_core__uart1,
@@ -3322,6 +3589,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
        &omap34xx_l4_core__mcspi3,
        &omap34xx_l4_core__mcspi4,
        &omap3xxx_l4_wkup__counter_32k,
+        &omap3xxx_l3_main__gpmc,
        NULL,
 };
@@ -3371,6 +3639,11 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
        &omap34xx_l4_core__sr2,
        &omap3xxx_l4_core__mailbox,
        &omap3xxx_l4_core__hdq1w,
+        &omap3xxx_sad2d__l3,
+        &omap3xxx_l4_core__mmu_isp,
+#ifdef CONFIG_OMAP_IOMMU_IVA2
+        &omap3xxx_l3_main__mmu_iva,
+#endif
        NULL
 };
@@ -3391,6 +3664,11 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
        &omap3xxx_l4_core__es3plus_mmc1,
        &omap3xxx_l4_core__es3plus_mmc2,
        &omap3xxx_l4_core__hdq1w,
+        &omap3xxx_sad2d__l3,
+        &omap3xxx_l4_core__mmu_isp,
+#ifdef CONFIG_OMAP_IOMMU_IVA2
+        &omap3xxx_l3_main__mmu_iva,
+#endif
        NULL
 };
@@ -3405,6 +3683,7 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
        &omap3xxx_l4_core__usb_tll_hs,
        &omap3xxx_l4_core__es3plus_mmc1,
        &omap3xxx_l4_core__es3plus_mmc2,
+        &omap3xxx_l4_core__hdq1w,
        &am35xx_mdio__l3,
        &am35xx_l4_core__mdio,
        &am35xx_emac__l3,
@@ -3459,7 +3738,7 @@ int __init omap3xxx_hwmod_init(void)
        } else {
                WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
                return -EINVAL;
-        };
+        }
        r = omap_hwmod_register_links(h);
        if (r < 0)
@@ -3476,7 +3755,7 @@ int __init omap3xxx_hwmod_init(void)
                   rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
                   rev == OMAP3430_REV_ES3_1_2) {
                h = omap3430es2plus_hwmod_ocp_ifs;
-        };
+        }
        if (h) {
                r = omap_hwmod_register_links(h);
@@ -3491,7 +3770,7 @@ int __init omap3xxx_hwmod_init(void)
        } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
                   rev == OMAP3430_REV_ES3_1_2) {
                h = omap3430_es3plus_hwmod_ocp_ifs;
-        };
+        }
        if (h)
                r = omap_hwmod_register_links(h);
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index afb60917a948..652d0285bd6d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -19,18 +19,18 @@
 */
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <linux/power/smartreflex.h>
 #include <plat/omap_hwmod.h>
-#include <plat/cpu.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
 #include <plat/dma.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <plat/mmc.h>
 #include <plat/dmtimer.h>
 #include <plat/common.h>
+#include <plat/iommu.h>
 #include "omap_hwmod_common_data.h"
 #include "cm1_44xx.h"
@@ -203,6 +203,9 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
+                        .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
+                        .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
                },
        },
 };
@@ -259,6 +262,11 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
        .name           = "mpu_private",
        .class          = &omap44xx_mpu_bus_hwmod_class,
        .clkdm_name     = "mpuss_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 /*
@@ -343,6 +351,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
                        .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
+                        .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
@@ -447,6 +456,11 @@ static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
        .class          = &omap44xx_ctrl_module_hwmod_class,
        .clkdm_name     = "l4_cfg_clkdm",
        .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 /* ctrl_module_pad_core */
@@ -454,6 +468,11 @@ static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
        .name           = "ctrl_module_pad_core",
        .class          = &omap44xx_ctrl_module_hwmod_class,
        .clkdm_name     = "l4_cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 /* ctrl_module_wkup */
@@ -461,6 +480,11 @@ static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
        .name           = "ctrl_module_wkup",
        .class          = &omap44xx_ctrl_module_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 /* ctrl_module_pad_wkup */
@@ -468,6 +492,11 @@ static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
        .name           = "ctrl_module_pad_wkup",
        .class          = &omap44xx_ctrl_module_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 /*
@@ -612,7 +641,6 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
        { .name = "dsp", .rst_shift = 0 },
-        { .name = "mmu_cache", .rst_shift = 1 },
 };
 static struct omap_hwmod omap44xx_dsp_hwmod = {
@@ -1324,6 +1352,14 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
        .name           = "gpmc",
        .class          = &omap44xx_gpmc_hwmod_class,
        .clkdm_name     = "l3_2_clkdm",
+        /*
+         * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
+         * block.  It is not being added due to any known bugs with
+         * resetting the GPMC IP block, but rather because any timings
+         * set by the bootloader are not being correctly programmed by
+         * the kernel from the board file or DT data.
+         * HWMOD_INIT_NO_RESET should be removed ASAP.
+         */
        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
        .mpu_irqs       = omap44xx_gpmc_irqs,
        .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
@@ -1632,7 +1668,6 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
        { .name = "cpu0", .rst_shift = 0 },
        { .name = "cpu1", .rst_shift = 1 },
-        { .name = "mmu_cache", .rst_shift = 2 },
 };
 static struct omap_hwmod omap44xx_ipu_hwmod = {
@@ -2439,6 +2474,137 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
 };
 /*
+ * 'mmu' class
+ * The memory management unit performs virtual to physical address translation
+ * for its requestors.
+ */
+static struct omap_hwmod_class_sysconfig mmu_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
+        .name = "mmu",
+        .sysc = &mmu_sysc,
+};
+/* mmu ipu */
+static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
+        .da_start       = 0x0,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 32,
+};
+static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
+        { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
+        { .irq = -1 }
+};
+static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
+        { .name = "mmu_cache", .rst_shift = 2 },
+};
+static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
+        {
+                .pa_start       = 0x55082000,
+                .pa_end         = 0x550820ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+/* l3_main_2 -> mmu_ipu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_mmu_ipu_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_mmu_ipu_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
+        .name           = "mmu_ipu",
+        .class          = &omap44xx_mmu_hwmod_class,
+        .clkdm_name     = "ducati_clkdm",
+        .mpu_irqs       = omap44xx_mmu_ipu_irqs,
+        .rst_lines      = omap44xx_mmu_ipu_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
+        .main_clk       = "ducati_clk_mux_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
+                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .dev_attr       = &mmu_ipu_dev_attr,
+};
+/* mmu dsp */
+static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
+        .da_start       = 0x0,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 32,
+};
+static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
+        { .irq = 28 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
+        { .name = "mmu_cache", .rst_shift = 1 },
+};
+static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
+        {
+                .pa_start       = 0x4a066000,
+                .pa_end         = 0x4a0660ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+/* l4_cfg -> dsp */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_mmu_dsp_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmu_dsp_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
+        .name           = "mmu_dsp",
+        .class          = &omap44xx_mmu_hwmod_class,
+        .clkdm_name     = "tesla_clkdm",
+        .mpu_irqs       = omap44xx_mmu_dsp_irqs,
+        .rst_lines      = omap44xx_mmu_dsp_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
+        .main_clk       = "dpll_iva_m4x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
+                        .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .dev_attr       = &mmu_dsp_dev_attr,
+};
+/*
 * 'mpu' class
 * mpu sub-system
 */
@@ -2449,6 +2615,8 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 /* mpu */
 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
+        { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
+        { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
        { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
        { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
        { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
@@ -2498,19 +2666,27 @@ static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
 * protocol
 */
+static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
        .name   = "ocp2scp",
+        .sysc   = &omap44xx_ocp2scp_sysc,
 };
 /* ocp2scp_usb_phy */
-static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
-        { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
-};
 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
        .name           = "ocp2scp_usb_phy",
        .class          = &omap44xx_ocp2scp_hwmod_class,
        .clkdm_name     = "l3_init_clkdm",
+        .main_clk       = "ocp2scp_usb_phy_phy_48m",
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
@@ -2518,8 +2694,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
                        .modulemode   = MODULEMODE_HWCTRL,
                },
        },
-        .opt_clks       = ocp2scp_usb_phy_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
 };
 /*
@@ -2537,18 +2711,36 @@ static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
        .name           = "prcm_mpu",
        .class          = &omap44xx_prcm_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_NO_IDLEST,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 /* cm_core_aon */
 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
        .name           = "cm_core_aon",
        .class          = &omap44xx_prcm_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 /* cm_core */
 static struct omap_hwmod omap44xx_cm_core_hwmod = {
        .name           = "cm_core",
        .class          = &omap44xx_prcm_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 /* prm */
@@ -2584,6 +2776,11 @@ static struct omap_hwmod omap44xx_scrm_hwmod = {
        .name           = "scrm",
        .class          = &omap44xx_scrm_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 /*
@@ -2902,6 +3099,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
        .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+/* pwm timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+};
 /* timer1 */
 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
        { .irq = 37 + OMAP44XX_IRQ_GIC_START },
@@ -3006,6 +3213,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_dsp_dev_attr,
 };
 /* timer6 */
@@ -3028,6 +3236,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_dsp_dev_attr,
 };
 /* timer7 */
@@ -3049,6 +3258,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
+        .dev_attr       = &capability_dsp_dev_attr,
 };
 /* timer8 */
@@ -3070,7 +3280,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .dev_attr       = &capability_pwm_dev_attr,
+        .dev_attr       = &capability_dsp_pwm_dev_attr,
 };
 /* timer9 */
@@ -5059,6 +5269,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
        {
+                .name           = "mpu",
                .pa_start       = 0x40132000,
                .pa_end         = 0x4013207f,
                .flags          = ADDR_TYPE_RT
@@ -5077,6 +5288,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
        {
+                .name           = "dma",
                .pa_start       = 0x49032000,
                .pa_end         = 0x4903207f,
                .flags          = ADDR_TYPE_RT
@@ -5263,11 +5475,21 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
+        {
+                .pa_start       = 0x4a0ad000,
+                .pa_end         = 0x4a0ad01f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
 /* l4_cfg -> ocp2scp_usb_phy */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
        .master         = &omap44xx_l4_cfg_hwmod,
        .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
        .clk            = "l4_div_ck",
+        .addr           = omap44xx_ocp2scp_usb_phy_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
@@ -5887,7 +6109,13 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
        {
                .pa_start       = 0x4a0ab000,
-                .pa_end         = 0x4a0ab003,
+                .pa_end         = 0x4a0ab7ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                /* XXX: Remove this once control module driver is in place */
+                .pa_start       = 0x4a00233c,
+                .pa_end         = 0x4a00233f,
                .flags          = ADDR_TYPE_RT
        },
        { }
@@ -6092,6 +6320,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
        &omap44xx_l4_per__mmc3,
        &omap44xx_l4_per__mmc4,
        &omap44xx_l4_per__mmc5,
+        &omap44xx_l3_main_2__mmu_ipu,
+        &omap44xx_l4_cfg__mmu_dsp,
        &omap44xx_l3_main_2__ocmc_ram,
        &omap44xx_l4_cfg__ocp2scp_usb_phy,
        &omap44xx_mpu_private__prcm_mpu,
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index e7e8eeae95e5..2bc8f1705d4a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -2,9 +2,8 @@
 * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
 *
 * Copyright (C) 2010-2011 Nokia Corporation
+ * Copyright (C) 2010-2012 Texas Instruments, Inc.
 * Paul Walmsley
- *
- * Copyright (C) 2010-2011 Texas Instruments, Inc.
 * Benoît Cousson
 *
 * This program is free software; you can redistribute it and/or modify
@@ -16,6 +15,7 @@
 #include <plat/omap_hwmod.h>
+#include "common.h"
 #include "display.h"
 /* Common address space across OMAP2xxx */
@@ -76,6 +76,8 @@ extern struct omap_hwmod omap2xxx_gpio4_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
 extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
+extern struct omap_hwmod omap2xxx_gpmc_hwmod;
+extern struct omap_hwmod omap2xxx_rng_hwmod;
 /* Common interface data across OMAP2xxx */
 extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
@@ -102,6 +104,7 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
 /* Common IP block data */
 extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
deleted file mode 100644
index d15225ff5c49..000000000000
--- a/arch/arm/mach-omap2/omap_l3_noc.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * OMAP4XXX L3 Interconnect error handling driver
- *
- * Copyright (C) 2011 Texas Corporation
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *      Sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- * USA
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include "omap_l3_noc.h"
-/*
- * Interrupt Handler for L3 error detection.
- *      1) Identify the L3 clockdomain partition to which the error belongs to.
- *      2) Identify the slave where the error information is logged
- *      3) Print the logged information.
- *      4) Add dump stack to provide kernel trace.
- *
- * Two Types of errors :
- *      1) Custom errors in L3 :
- *              Target like DMM/FW/EMIF generates SRESP=ERR error
- *      2) Standard L3 error:
- *              - Unsupported CMD.
- *                      L3 tries to access target while it is idle
- *              - OCP disconnect.
- *              - Address hole error:
- *                      If DSS/ISS/FDIF/USBHOSTFS access a target where they
- *                      do not have connectivity, the error is logged in
- *                      their default target which is DMM2.
- *
- *      On High Secure devices, firewall errors are possible and those
- *      can be trapped as well. But the trapping is implemented as part
- *      secure software and hence need not be implemented here.
- */
-static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
-{
-        struct omap4_l3 *l3 = _l3;
-        int inttype, i, k;
-        int err_src = 0;
-        u32 std_err_main, err_reg, clear, masterid;
-        void __iomem *base, *l3_targ_base;
-        char *target_name, *master_name = "UN IDENTIFIED";
-        /* Get the Type of interrupt */
-        inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
-        for (i = 0; i < L3_MODULES; i++) {
-                /*
-                 * Read the regerr register of the clock domain
-                 * to determine the source
-                 */
-                base = l3->l3_base[i];
-                err_reg = __raw_readl(base + l3_flagmux[i] +
-                                        + L3_FLAGMUX_REGERR0 + (inttype << 3));
-                /* Get the corresponding error and analyse */
-                if (err_reg) {
-                        /* Identify the source from control status register */
-                        err_src = __ffs(err_reg);
-                        /* Read the stderrlog_main_source from clk domain */
-                        l3_targ_base = base + *(l3_targ[i] + err_src);
-                        std_err_main =  __raw_readl(l3_targ_base +
-                                        L3_TARG_STDERRLOG_MAIN);
-                        masterid = __raw_readl(l3_targ_base +
-                                        L3_TARG_STDERRLOG_MSTADDR);
-                        switch (std_err_main & CUSTOM_ERROR) {
-                        case STANDARD_ERROR:
-                                target_name =
-                                        l3_targ_inst_name[i][err_src];
-                                WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
-                                        target_name,
-                                        __raw_readl(l3_targ_base +
-                                                L3_TARG_STDERRLOG_SLVOFSLSB));
-                                /* clear the std error log*/
-                                clear = std_err_main | CLEAR_STDERR_LOG;
-                                writel(clear, l3_targ_base +
-                                        L3_TARG_STDERRLOG_MAIN);
-                                break;
-                        case CUSTOM_ERROR:
-                                target_name =
-                                        l3_targ_inst_name[i][err_src];
-                                for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
-                                        if (masterid == l3_masters[k].id)
-                                                master_name =
-                                                        l3_masters[k].name;
-                                }
-                                WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
-                                        master_name, target_name);
-                                /* clear the std error log*/
-                                clear = std_err_main | CLEAR_STDERR_LOG;
-                                writel(clear, l3_targ_base +
-                                        L3_TARG_STDERRLOG_MAIN);
-                                break;
-                        default:
-                                /* Nothing to be handled here as of now */
-                                break;
-                        }
-                /* Error found so break the for loop */
-                break;
-                }
-        }
-        return IRQ_HANDLED;
-}
-static int __devinit omap4_l3_probe(struct platform_device *pdev)
-{
-        static struct omap4_l3 *l3;
-        struct resource *res;
-        int ret;
-        l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
-        if (!l3)
-                return -ENOMEM;
-        platform_set_drvdata(pdev, l3);
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                dev_err(&pdev->dev, "couldn't find resource 0\n");
-                ret = -ENODEV;
-                goto err0;
-        }
-        l3->l3_base[0] = ioremap(res->start, resource_size(res));
-        if (!l3->l3_base[0]) {
-                dev_err(&pdev->dev, "ioremap failed\n");
-                ret = -ENOMEM;
-                goto err0;
-        }
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-        if (!res) {
-                dev_err(&pdev->dev, "couldn't find resource 1\n");
-                ret = -ENODEV;
-                goto err1;
-        }
-        l3->l3_base[1] = ioremap(res->start, resource_size(res));
-        if (!l3->l3_base[1]) {
-                dev_err(&pdev->dev, "ioremap failed\n");
-                ret = -ENOMEM;
-                goto err1;
-        }
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
-        if (!res) {
-                dev_err(&pdev->dev, "couldn't find resource 2\n");
-                ret = -ENODEV;
-                goto err2;
-        }
-        l3->l3_base[2] = ioremap(res->start, resource_size(res));
-        if (!l3->l3_base[2]) {
-                dev_err(&pdev->dev, "ioremap failed\n");
-                ret = -ENOMEM;
-                goto err2;
-        }
-        /*
-         * Setup interrupt Handlers
-         */
-        l3->debug_irq = platform_get_irq(pdev, 0);
-        ret = request_irq(l3->debug_irq,
-                        l3_interrupt_handler,
-                        IRQF_DISABLED, "l3-dbg-irq", l3);
-        if (ret) {
-                pr_crit("L3: request_irq failed to register for 0x%x\n",
-                                                OMAP44XX_IRQ_L3_DBG);
-                goto err3;
-        }
-        l3->app_irq = platform_get_irq(pdev, 1);
-        ret = request_irq(l3->app_irq,
-                        l3_interrupt_handler,
-                        IRQF_DISABLED, "l3-app-irq", l3);
-        if (ret) {
-                pr_crit("L3: request_irq failed to register for 0x%x\n",
-                                                OMAP44XX_IRQ_L3_APP);
-                goto err4;
-        }
-        return 0;
-err4:
-        free_irq(l3->debug_irq, l3);
-err3:
-        iounmap(l3->l3_base[2]);
-err2:
-        iounmap(l3->l3_base[1]);
-err1:
-        iounmap(l3->l3_base[0]);
-err0:
-        kfree(l3);
-        return ret;
-}
-static int __devexit omap4_l3_remove(struct platform_device *pdev)
-{
-        struct omap4_l3 *l3 = platform_get_drvdata(pdev);
-        free_irq(l3->app_irq, l3);
-        free_irq(l3->debug_irq, l3);
-        iounmap(l3->l3_base[0]);
-        iounmap(l3->l3_base[1]);
-        iounmap(l3->l3_base[2]);
-        kfree(l3);
-        return 0;
-}
-#if defined(CONFIG_OF)
-static const struct of_device_id l3_noc_match[] = {
-        {.compatible = "ti,omap4-l3-noc", },
-        {},
-};
-MODULE_DEVICE_TABLE(of, l3_noc_match);
-#else
-#define l3_noc_match NULL
-#endif
-static struct platform_driver omap4_l3_driver = {
-        .probe          = omap4_l3_probe,
-        .remove         = __devexit_p(omap4_l3_remove),
-        .driver         = {
-                .name           = "omap_l3_noc",
-                .owner          = THIS_MODULE,
-                .of_match_table = l3_noc_match,
-        },
-};
-static int __init omap4_l3_init(void)
-{
-        return platform_driver_register(&omap4_l3_driver);
-}
-postcore_initcall_sync(omap4_l3_init);
-static void __exit omap4_l3_exit(void)
-{
-        platform_driver_unregister(&omap4_l3_driver);
-}
-module_exit(omap4_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
deleted file mode 100644
index a6ce34dc4814..000000000000
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * OMAP4XXX L3 Interconnect  error handling driver header
- *
- * Copyright (C) 2011 Texas Corporation
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *      sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- * USA
- */
-#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
-#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
-#define L3_MODULES                      3
-#define CLEAR_STDERR_LOG                (1 << 31)
-#define CUSTOM_ERROR                    0x2
-#define STANDARD_ERROR                  0x0
-#define INBAND_ERROR                    0x0
-#define L3_APPLICATION_ERROR            0x0
-#define L3_DEBUG_ERROR                  0x1
-/* L3 TARG register offsets */
-#define L3_TARG_STDERRLOG_MAIN          0x48
-#define L3_TARG_STDERRLOG_SLVOFSLSB     0x5c
-#define L3_TARG_STDERRLOG_MSTADDR       0x68
-#define L3_FLAGMUX_REGERR0              0xc
-#define NUM_OF_L3_MASTERS       (sizeof(l3_masters)/sizeof(l3_masters[0]))
-static u32 l3_flagmux[L3_MODULES] = {
-        0x500,
-        0x1000,
-        0X0200
-};
-/* L3 Target standard Error register offsets */
-static u32 l3_targ_inst_clk1[] = {
-        0x100, /* DMM1 */
-        0x200, /* DMM2 */
-        0x300, /* ABE */
-        0x400, /* L4CFG */
-        0x600,  /* CLK2 PWR DISC */
-        0x0,    /* Host CLK1 */
-        0x900   /* L4 Wakeup */
-};
-static u32 l3_targ_inst_clk2[] = {
-        0x500, /* CORTEX M3 */
-        0x300, /* DSS */
-        0x100, /* GPMC */
-        0x400, /* ISS */
-        0x700, /* IVAHD */
-        0xD00, /* missing in TRM  corresponds to AES1*/
-        0x900, /* L4 PER0*/
-        0x200, /* OCMRAM */
-        0x100, /* missing in TRM corresponds to GPMC sERROR*/
-        0x600, /* SGX */
-        0x800, /* SL2 */
-        0x1600, /* C2C */
-        0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
-        0xF00, /* missing in TRM corrsponds to SHA1*/
-        0xE00, /* missing in TRM corresponds to AES2*/
-        0xC00, /* L4 PER3 */
-        0xA00, /* L4 PER1*/
-        0xB00, /* L4 PER2*/
-        0x0, /* HOST CLK2 */
-        0x1800, /* CAL */
-        0x1700 /* LLI */
-};
-static u32 l3_targ_inst_clk3[] = {
-        0x0100  /* EMUSS */,
-        0x0300, /* DEBUGSS_CT_TBR */
-        0x0 /* HOST CLK3 */
-};
-static struct l3_masters_data {
-        u32 id;
-        char name[10];
-} l3_masters[] = {
-        { 0x0 , "MPU"},
-        { 0x10, "CS_ADP"},
-        { 0x14, "xxx"},
-        { 0x20, "DSP"},
-        { 0x30, "IVAHD"},
-        { 0x40, "ISS"},
-        { 0x44, "DucatiM3"},
-        { 0x48, "FaceDetect"},
-        { 0x50, "SDMA_Rd"},
-        { 0x54, "SDMA_Wr"},
-        { 0x58, "xxx"},
-        { 0x5C, "xxx"},
-        { 0x60, "SGX"},
-        { 0x70, "DSS"},
-        { 0x80, "C2C"},
-        { 0x88, "xxx"},
-        { 0x8C, "xxx"},
-        { 0x90, "HSI"},
-        { 0xA0, "MMC1"},
-        { 0xA4, "MMC2"},
-        { 0xA8, "MMC6"},
-        { 0xB0, "UNIPRO1"},
-        { 0xC0, "USBHOSTHS"},
-        { 0xC4, "USBOTGHS"},
-        { 0xC8, "USBHOSTFS"}
-};
-static char *l3_targ_inst_name[L3_MODULES][21] = {
-        {
-                "DMM1",
-                "DMM2",
-                "ABE",
-                "L4CFG",
-                "CLK2 PWR DISC",
-                "HOST CLK1",
-                "L4 WAKEUP"
-        },
-        {
-                "CORTEX M3" ,
-                "DSS ",
-                "GPMC ",
-                "ISS ",
-                "IVAHD ",
-                "AES1",
-                "L4 PER0",
-                "OCMRAM ",
-                "GPMC sERROR",
-                "SGX ",
-                "SL2 ",
-                "C2C ",
-                "PWR DISC CLK1",
-                "SHA1",
-                "AES2",
-                "L4 PER3",
-                "L4 PER1",
-                "L4 PER2",
-                "HOST CLK2",
-                "CAL",
-                "LLI"
-        },
-        {
-                "EMUSS",
-                "DEBUG SOURCE",
-                "HOST CLK3"
-        },
-};
-static u32 *l3_targ[L3_MODULES] = {
-        l3_targ_inst_clk1,
-        l3_targ_inst_clk2,
-        l3_targ_inst_clk3,
-};
-struct omap4_l3 {
-        struct device *dev;
-        struct clk *ick;
-        /* memory base */
-        void __iomem *l3_base[L3_MODULES];
-        int debug_irq;
-        int app_irq;
-};
-#endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
deleted file mode 100644
index acc216491b8a..000000000000
--- a/arch/arm/mach-omap2/omap_l3_smx.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * OMAP3XXX L3 Interconnect Driver
- *
- * Copyright (C) 2011 Texas Corporation
- *      Felipe Balbi <balbi@ti.com>
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *      Sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- * USA
- */
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include "omap_l3_smx.h"
-static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
-{
-        return __raw_readll(base + reg);
-}
-static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value)
-{
-        __raw_writell(value, base + reg);
-}
-static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error)
-{
-        return (error & 0x0f000000) >> L3_ERROR_LOG_CODE;
-}
-static inline u32 omap3_l3_decode_addr(u64 error_addr)
-{
-        return error_addr & 0xffffffff;
-}
-static inline unsigned omap3_l3_decode_cmd(u64 error)
-{
-        return (error & 0x07) >> L3_ERROR_LOG_CMD;
-}
-static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error)
-{
-        return (error & 0xff00) >> L3_ERROR_LOG_INITID;
-}
-static inline unsigned omap3_l3_decode_req_info(u64 error)
-{
-        return (error >> 32) & 0xffff;
-}
-static char *omap3_l3_code_string(u8 code)
-{
-        switch (code) {
-        case OMAP_L3_CODE_NOERROR:
-                return "No Error";
-        case OMAP_L3_CODE_UNSUP_CMD:
-                return "Unsupported Command";
-        case OMAP_L3_CODE_ADDR_HOLE:
-                return "Address Hole";
-        case OMAP_L3_CODE_PROTECT_VIOLATION:
-                return "Protection Violation";
-        case OMAP_L3_CODE_IN_BAND_ERR:
-                return "In-band Error";
-        case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT:
-                return "Request Timeout Not Accepted";
-        case OMAP_L3_CODE_REQ_TOUT_NO_RESP:
-                return "Request Timeout, no response";
-        default:
-                return "UNKNOWN error";
-        }
-}
-static char *omap3_l3_initiator_string(u8 initid)
-{
-        switch (initid) {
-        case OMAP_L3_LCD:
-                return "LCD";
-        case OMAP_L3_SAD2D:
-                return "SAD2D";
-        case OMAP_L3_IA_MPU_SS_1:
-        case OMAP_L3_IA_MPU_SS_2:
-        case OMAP_L3_IA_MPU_SS_3:
-        case OMAP_L3_IA_MPU_SS_4:
-        case OMAP_L3_IA_MPU_SS_5:
-                return "MPU";
-        case OMAP_L3_IA_IVA_SS_1:
-        case OMAP_L3_IA_IVA_SS_2:
-        case OMAP_L3_IA_IVA_SS_3:
-                return "IVA_SS";
-        case OMAP_L3_IA_IVA_SS_DMA_1:
-        case OMAP_L3_IA_IVA_SS_DMA_2:
-        case OMAP_L3_IA_IVA_SS_DMA_3:
-        case OMAP_L3_IA_IVA_SS_DMA_4:
-        case OMAP_L3_IA_IVA_SS_DMA_5:
-        case OMAP_L3_IA_IVA_SS_DMA_6:
-                return "IVA_SS_DMA";
-        case OMAP_L3_IA_SGX:
-                return "SGX";
-        case OMAP_L3_IA_CAM_1:
-        case OMAP_L3_IA_CAM_2:
-        case OMAP_L3_IA_CAM_3:
-                return "CAM";
-        case OMAP_L3_IA_DAP:
-                return "DAP";
-        case OMAP_L3_SDMA_WR_1:
-        case OMAP_L3_SDMA_WR_2:
-                return "SDMA_WR";
-        case OMAP_L3_SDMA_RD_1:
-        case OMAP_L3_SDMA_RD_2:
-        case OMAP_L3_SDMA_RD_3:
-        case OMAP_L3_SDMA_RD_4:
-                return "SDMA_RD";
-        case OMAP_L3_USBOTG:
-                return "USB_OTG";
-        case OMAP_L3_USBHOST:
-                return "USB_HOST";
-        default:
-                return "UNKNOWN Initiator";
-        }
-}
-/*
- * omap3_l3_block_irq - handles a register block's irq
- * @l3: struct omap3_l3 *
- * @base: register block base address
- * @error: L3_ERROR_LOG register of our block
- *
- * Called in hard-irq context. Caller should take care of locking
- *
- * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error
- * Analysis Sequence, we are following that sequence here, please
- * refer to that Figure for more information on the subject.
- */
-static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
-                                        u64 error, int error_addr)
-{
-        u8 code = omap3_l3_decode_error_code(error);
-        u8 initid = omap3_l3_decode_initid(error);
-        u8 multi = error & L3_ERROR_LOG_MULTI;
-        u32 address = omap3_l3_decode_addr(error_addr);
-        pr_err("%s seen by %s %s at address %x\n",
-                        omap3_l3_code_string(code),
-                        omap3_l3_initiator_string(initid),
-                        multi ? "Multiple Errors" : "", address);
-        WARN_ON(1);
-        return IRQ_HANDLED;
-}
-static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
-{
-        struct omap3_l3 *l3 = _l3;
-        u64 status, clear;
-        u64 error;
-        u64 error_addr;
-        u64 err_source = 0;
-        void __iomem *base;
-        int int_type;
-        irqreturn_t ret = IRQ_NONE;
-        int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
-        if (!int_type) {
-                status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
-                /*
-                 * if we have a timeout error, there's nothing we can
-                 * do besides rebooting the board. So let's BUG on any
-                 * of such errors and handle the others. timeout error
-                 * is severe and not expected to occur.
-                 */
-                BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
-        } else {
-                status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
-                /* No timeout error for debug sources */
-        }
-        /* identify the error source */
-        err_source = __ffs(status);
-        base = l3->rt + omap3_l3_bases[int_type][err_source];
-        error = omap3_l3_readll(base, L3_ERROR_LOG);
-        if (error) {
-                error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
-                ret |= omap3_l3_block_irq(l3, error, error_addr);
-        }
-        /* Clear the status register */
-        clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) |
-                L3_AGENT_STATUS_CLEAR_TA;
-        omap3_l3_writell(base, L3_AGENT_STATUS, clear);
-        /* clear the error log register */
-        omap3_l3_writell(base, L3_ERROR_LOG, error);
-        return ret;
-}
-static int __init omap3_l3_probe(struct platform_device *pdev)
-{
-        struct omap3_l3 *l3;
-        struct resource *res;
-        int ret;
-        l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
-        if (!l3)
-                return -ENOMEM;
-        platform_set_drvdata(pdev, l3);
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                dev_err(&pdev->dev, "couldn't find resource\n");
-                ret = -ENODEV;
-                goto err0;
-        }
-        l3->rt = ioremap(res->start, resource_size(res));
-        if (!l3->rt) {
-                dev_err(&pdev->dev, "ioremap failed\n");
-                ret = -ENOMEM;
-                goto err0;
-        }
-        l3->debug_irq = platform_get_irq(pdev, 0);
-        ret = request_irq(l3->debug_irq, omap3_l3_app_irq,
-                IRQF_DISABLED | IRQF_TRIGGER_RISING,
-                "l3-debug-irq", l3);
-        if (ret) {
-                dev_err(&pdev->dev, "couldn't request debug irq\n");
-                goto err1;
-        }
-        l3->app_irq = platform_get_irq(pdev, 1);
-        ret = request_irq(l3->app_irq, omap3_l3_app_irq,
-                IRQF_DISABLED | IRQF_TRIGGER_RISING,
-                "l3-app-irq", l3);
-        if (ret) {
-                dev_err(&pdev->dev, "couldn't request app irq\n");
-                goto err2;
-        }
-        return 0;
-err2:
-        free_irq(l3->debug_irq, l3);
-err1:
-        iounmap(l3->rt);
-err0:
-        kfree(l3);
-        return ret;
-}
-static int __exit omap3_l3_remove(struct platform_device *pdev)
-{
-        struct omap3_l3         *l3 = platform_get_drvdata(pdev);
-        free_irq(l3->app_irq, l3);
-        free_irq(l3->debug_irq, l3);
-        iounmap(l3->rt);
-        kfree(l3);
-        return 0;
-}
-static struct platform_driver omap3_l3_driver = {
-        .remove         = __exit_p(omap3_l3_remove),
-        .driver         = {
-        .name   = "omap_l3_smx",
-        },
-};
-static int __init omap3_l3_init(void)
-{
-        return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
-}
-postcore_initcall_sync(omap3_l3_init);
-static void __exit omap3_l3_exit(void)
-{
-        platform_driver_unregister(&omap3_l3_driver);
-}
-module_exit(omap3_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
deleted file mode 100644
index 4f3cebca4179..000000000000
--- a/arch/arm/mach-omap2/omap_l3_smx.h
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * OMAP3XXX L3 Interconnect Driver header
- *
- * Copyright (C) 2011 Texas Corporation
- *      Felipe Balbi <balbi@ti.com>
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *      sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- * USA
- */
-#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
-#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
-/* Register definitions. All 64-bit wide */
-#define L3_COMPONENT                    0x000
-#define L3_CORE                         0x018
-#define L3_AGENT_CONTROL                0x020
-#define L3_AGENT_STATUS                 0x028
-#define L3_ERROR_LOG                    0x058
-#define L3_ERROR_LOG_MULTI              (1 << 31)
-#define L3_ERROR_LOG_SECONDARY          (1 << 30)
-#define L3_ERROR_LOG_ADDR               0x060
-/* Register definitions for Sideband Interconnect */
-#define L3_SI_CONTROL                   0x020
-#define L3_SI_FLAG_STATUS_0             0x510
-static const u64 shift = 1;
-#define L3_STATUS_0_MPUIA_BRST          (shift << 0)
-#define L3_STATUS_0_MPUIA_RSP           (shift << 1)
-#define L3_STATUS_0_MPUIA_INBAND        (shift << 2)
-#define L3_STATUS_0_IVAIA_BRST          (shift << 6)
-#define L3_STATUS_0_IVAIA_RSP           (shift << 7)
-#define L3_STATUS_0_IVAIA_INBAND        (shift << 8)
-#define L3_STATUS_0_SGXIA_BRST          (shift << 9)
-#define L3_STATUS_0_SGXIA_RSP           (shift << 10)
-#define L3_STATUS_0_SGXIA_MERROR        (shift << 11)
-#define L3_STATUS_0_CAMIA_BRST          (shift << 12)
-#define L3_STATUS_0_CAMIA_RSP           (shift << 13)
-#define L3_STATUS_0_CAMIA_INBAND        (shift << 14)
-#define L3_STATUS_0_DISPIA_BRST         (shift << 15)
-#define L3_STATUS_0_DISPIA_RSP          (shift << 16)
-#define L3_STATUS_0_DMARDIA_BRST        (shift << 18)
-#define L3_STATUS_0_DMARDIA_RSP         (shift << 19)
-#define L3_STATUS_0_DMAWRIA_BRST        (shift << 21)
-#define L3_STATUS_0_DMAWRIA_RSP         (shift << 22)
-#define L3_STATUS_0_USBOTGIA_BRST       (shift << 24)
-#define L3_STATUS_0_USBOTGIA_RSP        (shift << 25)
-#define L3_STATUS_0_USBOTGIA_INBAND     (shift << 26)
-#define L3_STATUS_0_USBHOSTIA_BRST      (shift << 27)
-#define L3_STATUS_0_USBHOSTIA_INBAND    (shift << 28)
-#define L3_STATUS_0_SMSTA_REQ           (shift << 48)
-#define L3_STATUS_0_GPMCTA_REQ          (shift << 49)
-#define L3_STATUS_0_OCMRAMTA_REQ        (shift << 50)
-#define L3_STATUS_0_OCMROMTA_REQ        (shift << 51)
-#define L3_STATUS_0_IVATA_REQ           (shift << 54)
-#define L3_STATUS_0_SGXTA_REQ           (shift << 55)
-#define L3_STATUS_0_SGXTA_SERROR        (shift << 56)
-#define L3_STATUS_0_GPMCTA_SERROR       (shift << 57)
-#define L3_STATUS_0_L4CORETA_REQ        (shift << 58)
-#define L3_STATUS_0_L4PERTA_REQ         (shift << 59)
-#define L3_STATUS_0_L4EMUTA_REQ         (shift << 60)
-#define L3_STATUS_0_MAD2DTA_REQ         (shift << 61)
-#define L3_STATUS_0_TIMEOUT_MASK        (L3_STATUS_0_MPUIA_BRST         \
-                                        | L3_STATUS_0_MPUIA_RSP         \
-                                        | L3_STATUS_0_IVAIA_BRST        \
-                                        | L3_STATUS_0_IVAIA_RSP         \
-                                        | L3_STATUS_0_SGXIA_BRST        \
-                                        | L3_STATUS_0_SGXIA_RSP         \
-                                        | L3_STATUS_0_CAMIA_BRST        \
-                                        | L3_STATUS_0_CAMIA_RSP         \
-                                        | L3_STATUS_0_DISPIA_BRST       \
-                                        | L3_STATUS_0_DISPIA_RSP        \
-                                        | L3_STATUS_0_DMARDIA_BRST      \
-                                        | L3_STATUS_0_DMARDIA_RSP       \
-                                        | L3_STATUS_0_DMAWRIA_BRST      \
-                                        | L3_STATUS_0_DMAWRIA_RSP       \
-                                        | L3_STATUS_0_USBOTGIA_BRST     \
-                                        | L3_STATUS_0_USBOTGIA_RSP      \
-                                        | L3_STATUS_0_USBHOSTIA_BRST    \
-                                        | L3_STATUS_0_SMSTA_REQ         \
-                                        | L3_STATUS_0_GPMCTA_REQ        \
-                                        | L3_STATUS_0_OCMRAMTA_REQ      \
-                                        | L3_STATUS_0_OCMROMTA_REQ      \
-                                        | L3_STATUS_0_IVATA_REQ         \
-                                        | L3_STATUS_0_SGXTA_REQ         \
-                                        | L3_STATUS_0_L4CORETA_REQ      \
-                                        | L3_STATUS_0_L4PERTA_REQ       \
-                                        | L3_STATUS_0_L4EMUTA_REQ       \
-                                        | L3_STATUS_0_MAD2DTA_REQ)
-#define L3_SI_FLAG_STATUS_1             0x530
-#define L3_STATUS_1_MPU_DATAIA          (1 << 0)
-#define L3_STATUS_1_DAPIA0              (1 << 3)
-#define L3_STATUS_1_DAPIA1              (1 << 4)
-#define L3_STATUS_1_IVAIA               (1 << 6)
-#define L3_PM_ERROR_LOG                 0x020
-#define L3_PM_CONTROL                   0x028
-#define L3_PM_ERROR_CLEAR_SINGLE        0x030
-#define L3_PM_ERROR_CLEAR_MULTI         0x038
-#define L3_PM_REQ_INFO_PERMISSION(n)    (0x048 + (0x020 * n))
-#define L3_PM_READ_PERMISSION(n)        (0x050 + (0x020 * n))
-#define L3_PM_WRITE_PERMISSION(n)       (0x058 + (0x020 * n))
-#define L3_PM_ADDR_MATCH(n)             (0x060 + (0x020 * n))
-/* L3 error log bit fields. Common for IA and TA */
-#define L3_ERROR_LOG_CODE               24
-#define L3_ERROR_LOG_INITID             8
-#define L3_ERROR_LOG_CMD                0
-/* L3 agent status bit fields. */
-#define L3_AGENT_STATUS_CLEAR_IA        0x10000000
-#define L3_AGENT_STATUS_CLEAR_TA        0x01000000
-#define OMAP34xx_IRQ_L3_APP             10
-#define L3_APPLICATION_ERROR            0x0
-#define L3_DEBUG_ERROR                  0x1
-enum omap3_l3_initiator_id {
-        /* LCD has 1 ID */
-        OMAP_L3_LCD = 29,
-        /* SAD2D has 1 ID */
-        OMAP_L3_SAD2D = 28,
-        /* MPU has 5 IDs */
-        OMAP_L3_IA_MPU_SS_1 = 27,
-        OMAP_L3_IA_MPU_SS_2 = 26,
-        OMAP_L3_IA_MPU_SS_3 = 25,
-        OMAP_L3_IA_MPU_SS_4 = 24,
-        OMAP_L3_IA_MPU_SS_5 = 23,
-        /* IVA2.2 SS has 3 IDs*/
-        OMAP_L3_IA_IVA_SS_1 = 22,
-        OMAP_L3_IA_IVA_SS_2 = 21,
-        OMAP_L3_IA_IVA_SS_3 = 20,
-        /* IVA 2.2 SS DMA has 6 IDS */
-        OMAP_L3_IA_IVA_SS_DMA_1 = 19,
-        OMAP_L3_IA_IVA_SS_DMA_2 = 18,
-        OMAP_L3_IA_IVA_SS_DMA_3 = 17,
-        OMAP_L3_IA_IVA_SS_DMA_4 = 16,
-        OMAP_L3_IA_IVA_SS_DMA_5 = 15,
-        OMAP_L3_IA_IVA_SS_DMA_6 = 14,
-        /* SGX has 1 ID */
-        OMAP_L3_IA_SGX = 13,
-        /* CAM has 3 ID */
-        OMAP_L3_IA_CAM_1 = 12,
-        OMAP_L3_IA_CAM_2 = 11,
-        OMAP_L3_IA_CAM_3 = 10,
-        /* DAP has 1 ID */
-        OMAP_L3_IA_DAP = 9,
-        /* SDMA WR has 2 IDs */
-        OMAP_L3_SDMA_WR_1 = 8,
-        OMAP_L3_SDMA_WR_2 = 7,
-        /* SDMA RD has 4 IDs */
-        OMAP_L3_SDMA_RD_1 = 6,
-        OMAP_L3_SDMA_RD_2 = 5,
-        OMAP_L3_SDMA_RD_3 = 4,
-        OMAP_L3_SDMA_RD_4 = 3,
-        /* HSUSB OTG has 1 ID */
-        OMAP_L3_USBOTG = 2,
-        /* HSUSB HOST has 1 ID */
-        OMAP_L3_USBHOST = 1,
-};
-enum omap3_l3_code {
-        OMAP_L3_CODE_NOERROR = 0,
-        OMAP_L3_CODE_UNSUP_CMD = 1,
-        OMAP_L3_CODE_ADDR_HOLE = 2,
-        OMAP_L3_CODE_PROTECT_VIOLATION = 3,
-        OMAP_L3_CODE_IN_BAND_ERR = 4,
-        /* codes 5 and 6 are reserved */
-        OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
-        OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
-        /* codes 9 - 15 are also reserved */
-};
-struct omap3_l3 {
-        struct device *dev;
-        struct clk *ick;
-        /* memory base*/
-        void __iomem *rt;
-        int debug_irq;
-        int app_irq;
-        /* true when and inband functional error occurs */
-        unsigned inband:1;
-};
-/* offsets for l3 agents in order with the Flag status register */
-static unsigned int omap3_l3_app_bases[] = {
-        /* MPU IA */
-        0x1400,
-        0x1400,
-        0x1400,
-        /* RESERVED */
-        0,
-        0,
-        0,
-        /* IVA 2.2 IA */
-        0x1800,
-        0x1800,
-        0x1800,
-        /* SGX IA */
-        0x1c00,
-        0x1c00,
-        /* RESERVED */
-        0,
-        /* CAMERA IA */
-        0x5800,
-        0x5800,
-        0x5800,
-        /* DISPLAY IA */
-        0x5400,
-        0x5400,
-        /* RESERVED */
-        0,
-        /*SDMA RD IA */
-        0x4c00,
-        0x4c00,
-        /* RESERVED */
-        0,
-        /* SDMA WR IA */
-        0x5000,
-        0x5000,
-        /* RESERVED */
-        0,
-        /* USB OTG IA */
-        0x4400,
-        0x4400,
-        0x4400,
-        /* USB HOST IA */
-        0x4000,
-        0x4000,
-        /* RESERVED */
-        0,
-        0,
-        0,
-        0,
-        /* SAD2D IA */
-        0x3000,
-        0x3000,
-        0x3000,
-        /* RESERVED */
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        /* SMA TA */
-        0x2000,
-        /* GPMC TA */
-        0x2400,
-        /* OCM RAM TA */
-        0x2800,
-        /* OCM ROM TA */
-        0x2C00,
-        /* L4 CORE TA */
-        0x6800,
-        /* L4 PER TA */
-        0x6c00,
-        /* IVA 2.2 TA */
-        0x6000,
-        /* SGX TA */
-        0x6400,
-        /* L4 EMU TA */
-        0x7000,
-        /* GPMC TA */
-        0x2400,
-        /* L4 CORE TA */
-        0x6800,
-        /* L4 PER TA */
-        0x6c00,
-        /* L4 EMU TA */
-        0x7000,
-        /* MAD2D TA */
-        0x3400,
-        /* RESERVED */
-        0,
-        0,
-};
-static unsigned int omap3_l3_debug_bases[] = {
-        /* MPU DATA IA */
-        0x1400,
-        /* RESERVED */
-        0,
-        0,
-        /* DAP IA */
-        0x5c00,
-        0x5c00,
-        /* RESERVED */
-        0,
-        /* IVA 2.2 IA */
-        0x1800,
-        /* REST RESERVED */
-};
-static u32 *omap3_l3_bases[] = {
-        omap3_l3_app_bases,
-        omap3_l3_debug_bases,
-};
-/*
- * REVISIT define __raw_readll/__raw_writell here, but move them to
- * <asm/io.h> at some point
- */
-#define __raw_writell(v, a)     (__chk_io_ptr(a), \
-                                *(volatile u64 __force *)(a) = (v))
-#define __raw_readll(a)         (__chk_io_ptr(a), \
-                                *(volatile u64 __force *)(a))
-#endif
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index d52651a05daa..d992db8ff0b0 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -29,145 +29,9 @@
 #include <linux/usb.h>
 #include <plat/usb.h>
-#include "control.h"
-/* OMAP control module register for UTMI PHY */
-#define CONTROL_DEV_CONF                0x300
-#define PHY_PD                          0x1
-#define USBOTGHS_CONTROL                0x33c
-#define AVALID                          BIT(0)
-#define BVALID                          BIT(1)
-#define VBUSVALID                       BIT(2)
-#define SESSEND                         BIT(3)
-#define IDDIG                           BIT(4)
-static struct clk *phyclk, *clk48m, *clk32k;
-static void __iomem *ctrl_base;
-static int usbotghs_control;
-int omap4430_phy_init(struct device *dev)
-{
-        ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
-        if (!ctrl_base) {
-                pr_err("control module ioremap failed\n");
-                return -ENOMEM;
-        }
-        /* Power down the phy */
-        __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-        if (!dev) {
-                iounmap(ctrl_base);
-                return 0;
-        }
-        phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
-        if (IS_ERR(phyclk)) {
-                dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
-                iounmap(ctrl_base);
-                return PTR_ERR(phyclk);
-        }
-        clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m");
-        if (IS_ERR(clk48m)) {
-                dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
-                clk_put(phyclk);
-                iounmap(ctrl_base);
-                return PTR_ERR(clk48m);
-        }
-        clk32k = clk_get(dev, "usb_phy_cm_clk32k");
-        if (IS_ERR(clk32k)) {
-                dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n");
-                clk_put(phyclk);
-                clk_put(clk48m);
-                iounmap(ctrl_base);
-                return PTR_ERR(clk32k);
-        }
-        return 0;
-}
-int omap4430_phy_set_clk(struct device *dev, int on)
-{
-        static int state;
-        if (on && !state) {
-                /* Enable the phy clocks */
-                clk_enable(phyclk);
-                clk_enable(clk48m);
-                clk_enable(clk32k);
-                state = 1;
-        } else if (state) {
-                /* Disable the phy clocks */
-                clk_disable(phyclk);
-                clk_disable(clk48m);
-                clk_disable(clk32k);
-                state = 0;
-        }
-        return 0;
-}
-int omap4430_phy_power(struct device *dev, int ID, int on)
-{
-        if (on) {
-                if (ID)
-                        /* enable VBUS valid, IDDIG groung */
-                        __raw_writel(AVALID | VBUSVALID, ctrl_base +
-                                                        USBOTGHS_CONTROL);
-                else
-                        /*
-                         * Enable VBUS Valid, AValid and IDDIG
-                         * high impedance
-                         */
-                        __raw_writel(IDDIG | AVALID | VBUSVALID,
-                                                ctrl_base + USBOTGHS_CONTROL);
-        } else {
-                /* Enable session END and IDIG to high impedance. */
-                __raw_writel(SESSEND | IDDIG, ctrl_base +
-                                        USBOTGHS_CONTROL);
-        }
-        return 0;
-}
-int omap4430_phy_suspend(struct device *dev, int suspend)
-{
-        if (suspend) {
-                /* Disable the clocks */
-                omap4430_phy_set_clk(dev, 0);
-                /* Power down the phy */
-                __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-                /* save the context */
-                usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL);
-        } else {
-                /* Enable the internel phy clcoks */
-                omap4430_phy_set_clk(dev, 1);
-                /* power on the phy */
-                if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) {
-                        __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-                        mdelay(200);
-                }
-                /* restore the context */
-                __raw_writel(usbotghs_control, ctrl_base + USBOTGHS_CONTROL);
-        }
-        return 0;
-}
-int omap4430_phy_exit(struct device *dev)
-{
-        if (ctrl_base)
-                iounmap(ctrl_base);
-        if (phyclk)
-                clk_put(phyclk);
-        if (clk48m)
-                clk_put(clk48m);
-        if (clk32k)
-                clk_put(clk32k);
-        return 0;
+#include "soc.h"
-}
+#include "control.h"
 void am35x_musb_reset(void)
 {
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index d8f6dbf45d16..58e16aef40bb 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -18,6 +18,7 @@
 */
 #include <linux/module.h>
 #include <linux/opp.h>
+#include <linux/cpu.h>
 #include <plat/omap_device.h>
@@ -62,27 +63,34 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
                                __func__, i);
                        return -EINVAL;
                }
-                oh = omap_hwmod_lookup(opp_def->hwmod_name);
-                if (!oh || !oh->od) {
+                if (!strncmp(opp_def->hwmod_name, "mpu", 3)) {
-                        pr_debug("%s: no hwmod or odev for %s, [%d] "
+                        /* 
-                                "cannot add OPPs.\n", __func__,
+                         * All current OMAPs share voltage rail and
-                                opp_def->hwmod_name, i);
+                         * clock source, so CPU0 is used to represent
-                        continue;
+                         * the MPU-SS.
+                         */
+                        dev = get_cpu_device(0);
+                } else {
+                        oh = omap_hwmod_lookup(opp_def->hwmod_name);
+                        if (!oh || !oh->od) {
+                                pr_debug("%s: no hwmod or odev for %s, [%d] cannot add OPPs.\n",
+                                         __func__, opp_def->hwmod_name, i);
+                                continue;
+                        }
+                        dev = &oh->od->pdev->dev;
                }
-                dev = &oh->od->pdev->dev;
                r = opp_add(dev, opp_def->freq, opp_def->u_volt);
                if (r) {
-                        dev_err(dev, "%s: add OPP %ld failed for %s [%d] "
+                        dev_err(dev, "%s: add OPP %ld failed for %s [%d] result=%d\n",
-                                "result=%d\n",
+                                __func__, opp_def->freq,
-                               __func__, opp_def->freq,
+                                opp_def->hwmod_name, i, r);
-                               opp_def->hwmod_name, i, r);
                } else {
                        if (!opp_def->default_available)
                                r = opp_disable(dev, opp_def->freq);
                        if (r)
-                                dev_err(dev, "%s: disable %ld failed for %s "
+                                dev_err(dev, "%s: disable %ld failed for %s [%d] result=%d\n",
-                                        "[%d] result=%d\n",
                                        __func__, opp_def->freq,
                                        opp_def->hwmod_name, i, r);
                }
diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c
index 5037e76e4e23..a9e8cf21705d 100644
--- a/arch/arm/mach-omap2/opp2420_data.c
+++ b/arch/arm/mach-omap2/opp2420_data.c
@@ -28,7 +28,7 @@
 *     http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
 */
-#include <plat/hardware.h>
+#include <linux/kernel.h>
 #include "opp2xxx.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c
index 750805c528d8..0e75ec3e114b 100644
--- a/arch/arm/mach-omap2/opp2430_data.c
+++ b/arch/arm/mach-omap2/opp2430_data.c
@@ -26,7 +26,7 @@
 * This is technically part of the OMAP2xxx clock code.
 */
-#include <plat/hardware.h>
+#include <linux/kernel.h>
 #include "opp2xxx.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index d95f3f945d4a..75cef5f67a8a 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -19,8 +19,6 @@
 */
 #include <linux/module.h>
-#include <plat/cpu.h>
 #include "control.h"
 #include "omap_opp_data.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index c95415da23c2..a9fd6d5fe79e 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -20,8 +20,7 @@
 */
 #include <linux/module.h>
-#include <plat/cpu.h>
+#include "soc.h"
 #include "control.h"
 #include "omap_opp_data.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 814bcd901596..46092cd806fa 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -28,7 +28,6 @@
 #include <linux/slab.h>
 #include <plat/clock.h>
-#include <plat/board.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
 #include <plat/dmtimer.h>
@@ -169,7 +168,7 @@ static int pm_dbg_open(struct inode *inode, struct file *file)
        default:
                return single_open(file, pm_dbg_show_timers,
                        &inode->i_private);
-        };
+        }
 }
 static const struct file_operations debug_fops = {
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9cb5cede0f50..ea61c32957bd 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -16,6 +16,7 @@
 #include <linux/opp.h>
 #include <linux/export.h>
 #include <linux/suspend.h>
+#include <linux/cpu.h>
 #include <asm/system_misc.h>
@@ -80,7 +81,8 @@ static void __init omap2_init_processor_devices(void)
 int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
 {
-        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+        if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) &&
+            !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING))
                clkdm_allow_idle(clkdm);
        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
                 atomic_read(&clkdm->usecount) == 0)
@@ -168,7 +170,15 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
                goto exit;
        }
-        dev = omap_device_get_by_hwmod_name(oh_name);
+        if (!strncmp(oh_name, "mpu", 3))
+                /* 
+                 * All current OMAPs share voltage rail and clock
+                 * source, so CPU0 is used to represent the MPU-SS.
+                 */
+                dev = get_cpu_device(0);
+        else
+                dev = omap_device_get_by_hwmod_name(oh_name);
        if (IS_ERR(dev)) {
                pr_err("%s: Unable to get dev pointer for hwmod %s\n",
                        __func__, oh_name);
@@ -176,7 +186,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
        }
        voltdm = voltdm_lookup(vdd_name);
-        if (IS_ERR(voltdm)) {
+        if (!voltdm) {
                pr_err("%s: unable to get vdd pointer for vdd_%s\n",
                        __func__, vdd_name);
                goto exit;
@@ -188,7 +198,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
                goto exit;
        }
-        freq = clk->rate;
+        freq = clk_get_rate(clk);
        clk_put(clk);
        rcu_read_lock();
@@ -203,8 +213,8 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
        bootup_volt = opp_get_voltage(opp);
        rcu_read_unlock();
        if (!bootup_volt) {
-                pr_err("%s: unable to find voltage corresponding "
+                pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n",
-                        "to the bootup OPP for vdd_%s\n", __func__, vdd_name);
+                       __func__, vdd_name);
                goto exit;
        }
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 2edeffc923a6..8af6cd6ac331 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -29,6 +29,7 @@
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
@@ -38,9 +39,6 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/dma.h>
-#include <plat/board.h>
-#include <mach/irqs.h>
 #include "common.h"
 #include "prm2xxx_3xxx.h"
@@ -352,16 +350,6 @@ int __init omap2_pm_init(void)
        prcm_setup_regs();
-        /* Hack to prevent MPU retention when STI console is enabled. */
-        {
-                const struct omap_sti_console_config *sti;
-                sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
-                                      struct omap_sti_console_config);
-                if (sti != NULL && sti->enable)
-                        sti_console_enabled = 1;
-        }
        /*
         * We copy the assembler sleep/wakeup routines to SRAM.
         * These routines need to be in SRAM as that's the only
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 05bd8f02723f..ba670db1fd37 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -28,6 +28,8 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <trace/events/power.h>
 #include <asm/suspend.h>
@@ -389,9 +391,8 @@ restore:
        list_for_each_entry(pwrst, &pwrst_list, node) {
                state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
                if (state > pwrst->next_state) {
-                        pr_info("Powerdomain (%s) didn't enter "
+                        pr_info("Powerdomain (%s) didn't enter target state %d\n",
-                                "target state %d\n",
+                                pwrst->pwrdm->name, pwrst->next_state);
-                               pwrst->pwrdm->name, pwrst->next_state);
                        ret = -1;
                }
                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
@@ -731,8 +732,7 @@ int __init omap3_pm_init(void)
                omap3_secure_ram_storage =
                        kmalloc(0x803F, GFP_KERNEL);
                if (!omap3_secure_ram_storage)
-                        pr_err("Memory allocation failed when "
+                        pr_err("Memory allocation failed when allocating for secure sram context\n");
-                               "allocating for secure sram context\n");
                local_irq_disable();
                local_fiq_disable();
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index ea24174f5707..04922d149068 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -69,9 +69,8 @@ static int omap4_pm_suspend(void)
        list_for_each_entry(pwrst, &pwrst_list, node) {
                state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
                if (state > pwrst->next_state) {
-                        pr_info("Powerdomain (%s) didn't enter "
+                        pr_info("Powerdomain (%s) didn't enter target state %d\n",
-                               "target state %d\n",
+                                pwrst->pwrdm->name, pwrst->next_state);
-                               pwrst->pwrdm->name, pwrst->next_state);
                        ret = -1;
                }
                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
@@ -189,8 +188,7 @@ int __init omap4_pm_init(void)
        ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
        ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
        if (ret) {
-                pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
+                pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
-                                "wakeup dependency\n");
                goto err2;
        }
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
new file mode 100644
index 000000000000..2a791766283d
--- /dev/null
+++ b/arch/arm/mach-omap2/pmu.c
@@ -0,0 +1,95 @@
+/*
+ * OMAP2 ARM Performance Monitoring Unit (PMU) Support
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Contacts:
+ * Jon Hunter <jon-hunter@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/pm_runtime.h>
+#include <asm/pmu.h>
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+static char *omap2_pmu_oh_names[] = {"mpu"};
+static char *omap3_pmu_oh_names[] = {"mpu", "debugss"};
+static char *omap4430_pmu_oh_names[] = {"l3_main_3", "l3_instr", "debugss"};
+static struct platform_device *omap_pmu_dev;
+/**
+ * omap2_init_pmu - creates and registers PMU platform device
+ * @oh_num:     Number of OMAP HWMODs required to create PMU device
+ * @oh_names:   Array of OMAP HWMODS names required to create PMU device
+ *
+ * Uses OMAP HWMOD framework to create and register an ARM PMU device
+ * from a list of HWMOD names passed. Currently supports OMAP2, OMAP3
+ * and OMAP4 devices.
+ */
+static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
+{
+        int i;
+        struct omap_hwmod *oh[3];
+        char *dev_name = "arm-pmu";
+        if ((!oh_num) || (oh_num > 3))
+                return -EINVAL;
+        for (i = 0; i < oh_num; i++) {
+                oh[i] = omap_hwmod_lookup(oh_names[i]);
+                if (!oh[i]) {
+                        pr_err("Could not look up %s hwmod\n", oh_names[i]);
+                        return -ENODEV;
+                }
+        }
+        omap_pmu_dev = omap_device_build_ss(dev_name, -1, oh, oh_num, NULL, 0,
+                                            NULL, 0, 0);
+        WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n",
+             dev_name);
+        if (IS_ERR(omap_pmu_dev))
+                return PTR_ERR(omap_pmu_dev);
+        pm_runtime_enable(&omap_pmu_dev->dev);
+        return 0;
+}
+static int __init omap_init_pmu(void)
+{
+        unsigned oh_num;
+        char **oh_names;
+        /*
+         * To create an ARM-PMU device the following HWMODs
+         * are required for the various OMAP2+ devices.
+         *
+         * OMAP24xx:    mpu
+         * OMAP3xxx:    mpu, debugss
+         * OMAP4430:    l3_main_3, l3_instr, debugss
+         * OMAP4460/70: mpu, debugss
+         */
+        if (cpu_is_omap443x()) {
+                oh_num = ARRAY_SIZE(omap4430_pmu_oh_names);
+                oh_names = omap4430_pmu_oh_names;
+                /* XXX Remove the next two lines when CTI driver available */
+                pr_info("ARM PMU: not yet supported on OMAP4430 due to missing CTI driver\n");
+                return 0;
+        } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                oh_num = ARRAY_SIZE(omap3_pmu_oh_names);
+                oh_names = omap3_pmu_oh_names;
+        } else {
+                oh_num = ARRAY_SIZE(omap2_pmu_oh_names);
+                oh_names = omap2_pmu_oh_names;
+        }
+        return omap2_init_pmu(oh_num, oh_names);
+}
+subsys_initcall(omap_init_pmu);
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 69b36e185e9b..1678a3284233 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -28,11 +28,13 @@
 #include "prm44xx.h"
 #include <asm/cpu.h>
-#include <plat/cpu.h>
+#include <plat/prcm.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
-#include <plat/prcm.h>
+#include "soc.h"
 #include "pm.h"
 #define PWRDM_TRACE_STATES_FLAG (1<<31)
@@ -339,8 +341,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
        if (!pwrdm || !clkdm)
                return -EINVAL;
-        pr_debug("powerdomain: associating clockdomain %s with powerdomain "
+        pr_debug("powerdomain: %s: associating clockdomain %s\n",
-                 "%s\n", clkdm->name, pwrdm->name);
+                 pwrdm->name, clkdm->name);
        for (i = 0; i < PWRDM_MAX_CLKDMS; i++) {
                if (!pwrdm->pwrdm_clkdms[i])
@@ -354,8 +356,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
        }
        if (i == PWRDM_MAX_CLKDMS) {
-                pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for "
+                pr_debug("powerdomain: %s: increase PWRDM_MAX_CLKDMS for clkdm %s\n",
-                         "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name);
+                         pwrdm->name, clkdm->name);
                WARN_ON(1);
                ret = -ENOMEM;
                goto pac_exit;
@@ -387,16 +389,16 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
        if (!pwrdm || !clkdm)
                return -EINVAL;
-        pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
+        pr_debug("powerdomain: %s: dissociating clockdomain %s\n",
-                 "%s\n", clkdm->name, pwrdm->name);
+                 pwrdm->name, clkdm->name);
        for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
                if (pwrdm->pwrdm_clkdms[i] == clkdm)
                        break;
        if (i == PWRDM_MAX_CLKDMS) {
-                pr_debug("powerdomain: clkdm %s not associated with pwrdm "
+                pr_debug("powerdomain: %s: clkdm %s not associated?!\n",
-                         "%s ?!\n", clkdm->name, pwrdm->name);
+                         pwrdm->name, clkdm->name);
                ret = -ENOENT;
                goto pdc_exit;
        }
@@ -485,7 +487,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
        if (!(pwrdm->pwrsts & (1 << pwrst)))
                return -EINVAL;
-        pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
+        pr_debug("powerdomain: %s: setting next powerstate to %0x\n",
                 pwrdm->name, pwrst);
        if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
@@ -587,7 +589,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
        if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst)))
                return -EINVAL;
-        pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
+        pr_debug("powerdomain: %s: setting next logic powerstate to %0x\n",
                 pwrdm->name, pwrst);
        if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst)
@@ -624,8 +626,8 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
        if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst)))
                return -EINVAL;
-        pr_debug("powerdomain: setting next memory powerstate for domain %s "
+        pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-ON to %0x\n",
-                 "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
+                 pwrdm->name, bank, pwrst);
        if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst)
                ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst);
@@ -662,8 +664,8 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
        if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst)))
                return -EINVAL;
-        pr_debug("powerdomain: setting next memory powerstate for domain %s "
+        pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-RET to %0x\n",
-                 "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
+                 pwrdm->name, bank, pwrst);
        if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst)
                ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst);
@@ -841,7 +843,7 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
         * warn & fail if it is not ON.
         */
-        pr_debug("powerdomain: clearing previous power state reg for %s\n",
+        pr_debug("powerdomain: %s: clearing previous power state reg\n",
                 pwrdm->name);
        if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst)
@@ -871,8 +873,7 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
        if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
                return ret;
-        pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
+        pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", pwrdm->name);
-                 pwrdm->name);
        if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar)
                ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm);
@@ -901,8 +902,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
        if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
                return ret;
-        pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
+        pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", pwrdm->name);
-                 pwrdm->name);
        if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar)
                ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
index 0f0a9f1592fe..3950ccfe5f4a 100644
--- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -122,8 +122,8 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
                        udelay(1);
        if (c > PWRDM_TRANSITION_BAILOUT) {
-                printk(KERN_ERR "powerdomain: waited too long for "
+                pr_err("powerdomain: %s: waited too long to complete transition\n",
-                        "powerdomain %s to complete transition\n", pwrdm->name);
+                       pwrdm->name);
                return -EAGAIN;
        }
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
index 601325b852a4..aceb4f464c9b 100644
--- a/arch/arm/mach-omap2/powerdomain44xx.c
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -1,7 +1,7 @@
 /*
 * OMAP4 powerdomain control
 *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010, 2012 Texas Instruments, Inc.
 * Copyright (C) 2007-2009 Nokia Corporation
 *
 * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
@@ -151,6 +151,34 @@ static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
        return v;
 }
+/**
+ * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
+ * @pwrdm: struct powerdomain * to read the state for
+ *
+ * Reads the previous logic powerstate for a powerdomain. This
+ * function must determine the previous logic powerstate by first
+ * checking the previous powerstate for the domain. If that was OFF,
+ * then logic has been lost. If previous state was RETENTION, the
+ * function reads the setting for the next retention logic state to
+ * see the actual value.  In every other case, the logic is
+ * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
+ * depending whether the logic was retained or not.
+ */
+static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
+{
+        int state;
+        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
+        if (state == PWRDM_POWER_OFF)
+                return PWRDM_POWER_OFF;
+        if (state != PWRDM_POWER_RET)
+                return PWRDM_POWER_RET;
+        return omap4_pwrdm_read_logic_retst(pwrdm);
+}
 static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 {
        u32 m, v;
@@ -179,6 +207,35 @@ static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
        return v;
 }
+/**
+ * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
+ * @pwrdm: struct powerdomain * to read mem powerstate for
+ * @bank: memory bank index
+ *
+ * Reads the previous memory powerstate for a powerdomain. This
+ * function must determine the previous memory powerstate by first
+ * checking the previous powerstate for the domain. If that was OFF,
+ * then logic has been lost. If previous state was RETENTION, the
+ * function reads the setting for the next memory retention state to
+ * see the actual value.  In every other case, the logic is
+ * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
+ * depending whether logic was retained or not.
+ */
+static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        int state;
+        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
+        if (state == PWRDM_POWER_OFF)
+                return PWRDM_POWER_OFF;
+        if (state != PWRDM_POWER_RET)
+                return PWRDM_POWER_RET;
+        return omap4_pwrdm_read_mem_retst(pwrdm, bank);
+}
 static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
 {
        u32 c = 0;
@@ -198,8 +255,8 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
                udelay(1);
        if (c > PWRDM_TRANSITION_BAILOUT) {
-                printk(KERN_ERR "powerdomain: waited too long for "
+                pr_err("powerdomain: %s: waited too long to complete transition\n",
-                       "powerdomain %s to complete transition\n", pwrdm->name);
+                       pwrdm->name);
                return -EAGAIN;
        }
@@ -217,9 +274,11 @@ struct pwrdm_ops omap4_pwrdm_operations = {
        .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
        .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
        .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
+        .pwrdm_read_prev_logic_pwrst    = omap4_pwrdm_read_prev_logic_pwrst,
        .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
        .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
        .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
+        .pwrdm_read_prev_mem_pwrst      = omap4_pwrdm_read_prev_mem_pwrst,
        .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
        .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
        .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index bb883e463078..8b23d234fb55 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -15,11 +15,9 @@
 #include <linux/init.h>
 #include <linux/bug.h>
-#include <plat/cpu.h>
+#include "soc.h"
 #include "powerdomain.h"
 #include "powerdomains2xxx_3xxx_data.h"
 #include "prcm-common.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index e5f0503a68b0..72df97482cc0 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -109,6 +109,8 @@
 #define OMAP2430_EN_MDM_INTC_MASK                       (1 << 11)
 #define OMAP2430_EN_USBHS_SHIFT                         6
 #define OMAP2430_EN_USBHS_MASK                          (1 << 6)
+#define OMAP24XX_EN_GPMC_SHIFT                          1
+#define OMAP24XX_EN_GPMC_MASK                           (1 << 1)
 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
 #define OMAP2420_ST_MMC_SHIFT                           26
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 053e24ed3c48..0f51e034e0aa 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -27,7 +27,6 @@
 #include "common.h"
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 #include "clock.h"
 #include "clock2xxx.h"
@@ -140,11 +139,11 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
                          MAX_MODULE_ENABLE_WAIT, i);
        if (i < MAX_MODULE_ENABLE_WAIT)
-                pr_debug("cm: Module associated with clock %s ready after %d "
+                pr_debug("cm: Module associated with clock %s ready after %d loops\n",
-                         "loops\n", name, i);
+                         name, i);
        else
-                pr_err("cm: Module associated with clock %s didn't enable in "
+                pr_err("cm: Module associated with clock %s didn't enable in %d tries\n",
-                       "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
+                       name, MAX_MODULE_ENABLE_WAIT);
        return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
 };
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index a0309dea6794..9529984d8d2b 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -17,11 +17,10 @@
 #include <linux/io.h>
 #include <linux/irq.h>
-#include "common.h"
-#include <plat/cpu.h>
 #include <plat/prcm.h>
-#include <plat/irqs.h>
+#include "soc.h"
+#include "common.h"
 #include "vp.h"
 #include "prm2xxx_3xxx.h"
@@ -40,7 +39,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
        .nr_regs                = 1,
        .irqs                   = omap3_prcm_irqs,
        .nr_irqs                = ARRAY_SIZE(omap3_prcm_irqs),
-        .irq                    = INT_34XX_PRCM_MPU_IRQ,
+        .irq                    = 11 + OMAP_INTC_START,
        .read_pending_irqs      = &omap3xxx_prm_read_pending_irqs,
        .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
        .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index bb727c2d9337..f0c4d5f4a174 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -17,10 +17,9 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/cpu.h>
-#include <plat/irqs.h>
 #include <plat/prcm.h>
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "vp.h"
@@ -40,7 +39,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
        .nr_regs                = 2,
        .irqs                   = omap4_prcm_irqs,
        .nr_irqs                = ARRAY_SIZE(omap4_prcm_irqs),
-        .irq                    = OMAP44XX_IRQ_PRCM,
+        .irq                    = 11 + OMAP44XX_IRQ_GIC_START,
        .read_pending_irqs      = &omap44xx_prm_read_pending_irqs,
        .ocp_barrier            = &omap44xx_prm_ocp_barrier,
        .save_and_clear_irqen   = &omap44xx_prm_save_and_clear_irqen,
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 03b126d9ad94..6b4d332be2f6 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -26,7 +26,6 @@
 #include <plat/common.h>
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 1133bb2f632b..73e55e485329 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -24,11 +24,11 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/hardware.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/sdrc.h>
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index c1b93c752d70..0405c8190803 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -29,11 +29,11 @@
 #include <plat/omap-serial.h>
 #include "common.h"
-#include <plat/board.h>
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/omap-pm.h>
+#include <plat/serial.h>
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
@@ -81,8 +81,9 @@ static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
 };
 #ifdef CONFIG_PM
-static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+static void omap_uart_enable_wakeup(struct device *dev, bool enable)
 {
+        struct platform_device *pdev = to_platform_device(dev);
        struct omap_device *od = to_omap_device(pdev);
        if (!od)
@@ -99,15 +100,17 @@ static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
 * in Smartidle Mode When Configured for DMA Operations.
 * WA: configure uart in force idle mode.
 */
-static void omap_uart_set_noidle(struct platform_device *pdev)
+static void omap_uart_set_noidle(struct device *dev)
 {
+        struct platform_device *pdev = to_platform_device(dev);
        struct omap_device *od = to_omap_device(pdev);
        omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
 }
-static void omap_uart_set_smartidle(struct platform_device *pdev)
+static void omap_uart_set_smartidle(struct device *dev)
 {
+        struct platform_device *pdev = to_platform_device(dev);
        struct omap_device *od = to_omap_device(pdev);
        u8 idlemode;
@@ -120,10 +123,10 @@ static void omap_uart_set_smartidle(struct platform_device *pdev)
 }
 #else
-static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+static void omap_uart_enable_wakeup(struct device *dev, bool enable)
 {}
-static void omap_uart_set_noidle(struct platform_device *pdev) {}
+static void omap_uart_set_noidle(struct device *dev) {}
-static void omap_uart_set_smartidle(struct platform_device *pdev) {}
+static void omap_uart_set_smartidle(struct device *dev) {}
 #endif /* CONFIG_PM */
 #ifdef CONFIG_OMAP_MUX
@@ -229,9 +232,8 @@ static int __init omap_serial_early_init(void)
                        if (console_loglevel >= 10) {
                                uart_debug = true;
-                                pr_info("%s used as console in debug mode"
+                                pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
-                                                " uart%d clocks will not be"
+                                        uart_name, uart->num);
-                                                " gated", uart_name, uart->num);
                        }
                        if (cmdline_find_option("no_console_suspend"))
@@ -304,6 +306,9 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
        omap_up.dma_rx_timeout = info->dma_rx_timeout;
        omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
        omap_up.autosuspend_timeout = info->autosuspend_timeout;
+        omap_up.DTR_gpio = info->DTR_gpio;
+        omap_up.DTR_inverted = info->DTR_inverted;
+        omap_up.DTR_present = info->DTR_present;
        pdata = &omap_up;
        pdata_size = sizeof(struct omap_uart_port_info);
@@ -313,8 +318,11 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
        pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
                                 NULL, 0, false);
-        WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
+        if (IS_ERR(pdev)) {
-             name, oh->name);
+                WARN(1, "Could not build omap_device for %s: %s.\n", name,
+                     oh->name);
+                return;
+        }
        if ((console_uart_id == bdata->id) && no_console_suspend)
                omap_device_disable_idle_on_suspend(pdev);
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S
index d4bf904d84ab..ce0ccd26efbd 100644
--- a/arch/arm/mach-omap2/sleep24xx.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -28,8 +28,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <plat/omap24xx.h>
+#include "omap24xx.h"
 #include "sdrc.h"
 /* First address of reserved address space?  apparently valid for OMAP2 & 3 */
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 1f62f23673fb..506987979c1c 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -26,9 +26,9 @@
 #include <asm/assembler.h>
-#include <plat/hardware.h>
 #include <plat/sram.h>
+#include "omap34xx.h"
 #include "iomap.h"
 #include "cm2xxx_3xxx.h"
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 91e71d8f46f0..88ff83a0942e 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -14,10 +14,10 @@
 #include <asm/memory.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <plat/omap44xx.h>
+#include "omap-secure.h"
-#include <mach/omap-secure.h>
 #include "common.h"
+#include "omap44xx.h"
 #include "omap4-sar-layout.h"
 #if defined(CONFIG_SMP) && defined(CONFIG_PM)
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
new file mode 100644
index 000000000000..fc9b96daf851
--- /dev/null
+++ b/arch/arm/mach-omap2/soc.h
@@ -0,0 +1,7 @@
+#include <plat/cpu.h>
+#include "omap24xx.h"
+#include "omap34xx.h"
+#include "omap44xx.h"
+#include "ti81xx.h"
+#include "am33xx.h"
+#include "omap54xx.h"
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index d033a65f4e4e..f8217a5a4a26 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -104,16 +104,15 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
        sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL);
        if (!sr_data) {
-                pr_err("%s: Unable to allocate memory for %s sr_data.Error!\n",
+                pr_err("%s: Unable to allocate memory for %s sr_data\n",
-                        __func__, oh->name);
+                       __func__, oh->name);
                return -ENOMEM;
        }
        sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
        if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
-                pr_err("%s: No voltage domain specified for %s."
+                pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
-                                "Cannot initialize\n", __func__,
+                       __func__, oh->name);
-                                        oh->name);
                goto exit;
        }
@@ -123,7 +122,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
        sr_data->senp_mod = 0x1;
        sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name);
-        if (IS_ERR(sr_data->voltdm)) {
+        if (!sr_data->voltdm) {
                pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
                        __func__, sr_dev_attr->sensor_voltdm_name);
                goto exit;
@@ -131,8 +130,8 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
        omap_voltage_get_volttable(sr_data->voltdm, &volt_data);
        if (!volt_data) {
-                pr_warning("%s: No Voltage table registered fo VDD%d."
+                pr_err("%s: No Voltage table registered for VDD%d\n",
-                        "Something really wrong\n\n", __func__, i + 1);
+                       __func__, i + 1);
                goto exit;
        }
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index ee0bfcc1410f..8f7326cd435b 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -32,8 +32,7 @@
 #include <asm/assembler.h>
-#include <mach/hardware.h>
+#include "soc.h"
 #include "iomap.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index d4d39ef04769..b140d6578529 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -32,8 +32,7 @@
 #include <asm/assembler.h>
-#include <mach/hardware.h>
+#include "soc.h"
 #include "iomap.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index df5a21322b0a..2d0ceaa23fb8 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -29,8 +29,7 @@
 #include <asm/assembler.h>
-#include <mach/hardware.h>
+#include "soc.h"
 #include "iomap.h"
 #include "sdrc.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/plat-omap/include/plat/ti81xx.h b/arch/arm/mach-omap2/ti81xx.h
index 8f9843f78422..8f9843f78422 100644
--- a/arch/arm/plat-omap/include/plat/ti81xx.h
+++ b/arch/arm/mach-omap2/ti81xx.h
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 2ba4f57dda86..44f9aa7ec0c0 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -36,16 +36,20 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 #include <asm/mach/time.h>
-#include <plat/dmtimer.h>
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
-#include "common.h"
+#include <asm/arch_timer.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
+#include <plat/dmtimer.h>
 #include <plat/omap-pm.h>
+#include "soc.h"
+#include "common.h"
 #include "powerdomain.h"
 /* Parent clocks, eventually these will come from the clock framework */
@@ -69,6 +73,11 @@
 #define OMAP3_SECURE_TIMER      1
 #endif
+#define REALTIME_COUNTER_BASE                           0x48243200
+#define INCREMENTER_NUMERATOR_OFFSET                    0x10
+#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
+#define NUMERATOR_DENUMERATOR_MASK                      0xfffff000
 /* Clockevent code */
 static struct omap_dm_timer clkev;
@@ -211,7 +220,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
        res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
        BUG_ON(res);
-        omap2_gp_timer_irq.dev_id = (void *)&clkev;
+        omap2_gp_timer_irq.dev_id = &clkev;
        setup_irq(clkev.irq, &omap2_gp_timer_irq);
        __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
@@ -346,6 +355,84 @@ static void __init omap2_clocksource_init(int gptimer_id,
                omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 }
+#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
+/*
+ * The realtime counter also called master counter, is a free-running
+ * counter, which is related to real time. It produces the count used
+ * by the CPU local timer peripherals in the MPU cluster. The timer counts
+ * at a rate of 6.144 MHz. Because the device operates on different clocks
+ * in different power modes, the master counter shifts operation between
+ * clocks, adjusting the increment per clock in hardware accordingly to
+ * maintain a constant count rate.
+ */
+static void __init realtime_counter_init(void)
+{
+        void __iomem *base;
+        static struct clk *sys_clk;
+        unsigned long rate;
+        unsigned int reg, num, den;
+        base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
+        if (!base) {
+                pr_err("%s: ioremap failed\n", __func__);
+                return;
+        }
+        sys_clk = clk_get(NULL, "sys_clkin_ck");
+        if (IS_ERR(sys_clk)) {
+                pr_err("%s: failed to get system clock handle\n", __func__);
+                iounmap(base);
+                return;
+        }
+        rate = clk_get_rate(sys_clk);
+        /* Numerator/denumerator values refer TRM Realtime Counter section */
+        switch (rate) {
+        case 1200000:
+                num = 64;
+                den = 125;
+                break;
+        case 1300000:
+                num = 768;
+                den = 1625;
+                break;
+        case 19200000:
+                num = 8;
+                den = 25;
+                break;
+        case 2600000:
+                num = 384;
+                den = 1625;
+                break;
+        case 2700000:
+                num = 256;
+                den = 1125;
+                break;
+        case 38400000:
+        default:
+                /* Program it for 38.4 MHz */
+                num = 4;
+                den = 25;
+                break;
+        }
+        /* Program numerator and denumerator registers */
+        reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+                        NUMERATOR_DENUMERATOR_MASK;
+        reg |= num;
+        __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
+        reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+                        NUMERATOR_DENUMERATOR_MASK;
+        reg |= den;
+        __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+        iounmap(base);
+}
+#else
+static inline void __init realtime_counter_init(void)
+{}
+#endif
 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,                  \
                                clksrc_nr, clksrc_src)                  \
 static void __init omap##name##_timer_init(void)                        \
@@ -380,8 +467,7 @@ OMAP_SYS_TIMER(3_am33xx)
 #ifdef CONFIG_ARCH_OMAP4
 #ifdef CONFIG_LOCAL_TIMERS
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
-                              OMAP44XX_LOCAL_TWD_BASE,
+                              OMAP44XX_LOCAL_TWD_BASE, 29 + OMAP_INTC_START);
-                              OMAP44XX_IRQ_LOCALTIMER);
 #endif
 static void __init omap4_timer_init(void)
@@ -393,6 +479,11 @@ static void __init omap4_timer_init(void)
        if (omap_rev() != OMAP4430_REV_ES1_0) {
                int err;
+                if (of_have_populated_dt()) {
+                        twd_local_timer_of_register();
+                        return;
+                }
                err = twd_local_timer_register(&twd_local_timer);
                if (err)
                        pr_err("twd_local_timer_register failed %d\n", err);
@@ -403,7 +494,18 @@ OMAP_SYS_TIMER(4)
 #endif
 #ifdef CONFIG_SOC_OMAP5
-OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
+static void __init omap5_timer_init(void)
+{
+        int err;
+        omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+        omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
+        realtime_counter_init();
+        err = arch_timer_of_register();
+        if (err)
+                pr_err("%s: arch_timer_register failed %d\n", __func__, err);
+}
 OMAP_SYS_TIMER(5)
 #endif
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index db5ff6642375..635e109f5ad3 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -29,6 +29,7 @@
 #include <plat/i2c.h>
 #include <plat/usb.h>
+#include "soc.h"
 #include "twl-common.h"
 #include "pm.h"
 #include "voltage.h"
@@ -39,16 +40,6 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = {
        .flags          = I2C_CLIENT_WAKE,
 };
-static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
-        {
-                .addr           = 0x48,
-                .flags          = I2C_CLIENT_WAKE,
-        },
-        {
-                I2C_BOARD_INFO("twl6040", 0x4b),
-        },
-};
 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 static int twl_set_voltage(void *data, int target_uV)
 {
@@ -78,30 +69,25 @@ void __init omap_pmic_init(int bus, u32 clkrate,
 void __init omap4_pmic_init(const char *pmic_type,
                    struct twl4030_platform_data *pmic_data,
-                    struct twl6040_platform_data *twl6040_data, int twl6040_irq)
+                    struct i2c_board_info *devices, int nr_devices)
 {
        /* PMIC part*/
        omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
-        strncpy(omap4_i2c1_board_info[0].type, pmic_type,
+        omap_pmic_init(1, 400, pmic_type, 7 + OMAP44XX_IRQ_GIC_START, pmic_data);
-                sizeof(omap4_i2c1_board_info[0].type));
-        omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N;
-        omap4_i2c1_board_info[0].platform_data = pmic_data;
-        /* TWL6040 audio IC part */
-        omap4_i2c1_board_info[1].irq = twl6040_irq;
-        omap4_i2c1_board_info[1].platform_data = twl6040_data;
-        omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2);
+        /* Register additional devices on i2c1 bus if needed */
+        if (devices)
+                i2c_register_board_info(1, devices, nr_devices);
 }
 void __init omap_pmic_late_init(void)
 {
-        /* Init the OMAP TWL parameters (if PMIC has been registered) */
+        /* Init the OMAP TWL parameters (if PMIC has been registerd) */
-        if (pmic_i2c_board_info.irq)
+        if (!pmic_i2c_board_info.irq)
-                omap3_twl_init();
+                return;
-        if (omap4_i2c1_board_info[0].irq)
-                omap4_twl_init();
+        omap3_twl_init();
+        omap4_twl_init();
 }
 #if defined(CONFIG_ARCH_OMAP3)
@@ -172,7 +158,7 @@ static struct regulator_init_data omap3_vpll2_idata = {
 };
 static struct regulator_consumer_supply omap3_vdd1_supply[] = {
-        REGULATOR_SUPPLY("vcc", "mpu.0"),
+        REGULATOR_SUPPLY("vcc", "cpu0"),
 };
 static struct regulator_consumer_supply omap3_vdd2_supply[] = {
@@ -251,11 +237,10 @@ void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
 #if defined(CONFIG_ARCH_OMAP4)
 static struct twl4030_usb_data omap4_usb_pdata = {
-        .phy_init       = omap4430_phy_init,
+};
-        .phy_exit       = omap4430_phy_exit,
-        .phy_power      = omap4430_phy_power,
+static struct regulator_consumer_supply omap4_vdda_hdmi_dac_supplies[] = {
-        .phy_set_clock  = omap4430_phy_set_clk,
+        REGULATOR_SUPPLY("vdda_hdmi_dac", "omapdss_hdmi"),
-        .phy_suspend    = omap4430_phy_suspend,
 };
 static struct regulator_init_data omap4_vdac_idata = {
@@ -267,6 +252,8 @@ static struct regulator_init_data omap4_vdac_idata = {
                .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                        | REGULATOR_CHANGE_STATUS,
        },
+        .num_consumer_supplies  = ARRAY_SIZE(omap4_vdda_hdmi_dac_supplies),
+        .consumer_supplies      = omap4_vdda_hdmi_dac_supplies,
        .supply_regulator       = "V2V1",
 };
@@ -538,3 +525,30 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
                pmic_data->v2v1 = &omap4_v2v1_idata;
 }
 #endif /* CONFIG_ARCH_OMAP4 */
+#if defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030) || \
+        defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030_MODULE)
+#include <linux/platform_data/omap-twl4030.h>
+static struct omap_tw4030_pdata omap_twl4030_audio_data;
+static struct platform_device audio_device = {
+        .name           = "omap-twl4030",
+        .id             = -1,
+        .dev = {
+                .platform_data = &omap_twl4030_audio_data,
+        },
+};
+void __init omap_twl4030_audio_init(char *card_name)
+{
+        omap_twl4030_audio_data.card_name = card_name;
+        platform_device_register(&audio_device);
+}
+#else /* SOC_OMAP_TWL4030 */
+void __init omap_twl4030_audio_init(char *card_name)
+{
+        return;
+}
+#endif /* SOC_OMAP_TWL4030 */
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index 8fe71cfd002c..dcfbad5ac471 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -1,7 +1,7 @@
 #ifndef __OMAP_PMIC_COMMON__
 #define __OMAP_PMIC_COMMON__
-#include <plat/irqs.h>
+#include "common.h"
 #define TWL_COMMON_PDATA_USB            (1 << 0)
 #define TWL_COMMON_PDATA_BCI            (1 << 1)
@@ -32,6 +32,7 @@
 struct twl4030_platform_data;
 struct twl6040_platform_data;
+struct i2c_board_info;
 void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
                    struct twl4030_platform_data *pmic_data);
@@ -40,18 +41,18 @@ void omap_pmic_late_init(void);
 static inline void omap2_pmic_init(const char *pmic_type,
                                   struct twl4030_platform_data *pmic_data)
 {
-        omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
+        omap_pmic_init(2, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data);
 }
 static inline void omap3_pmic_init(const char *pmic_type,
                                   struct twl4030_platform_data *pmic_data)
 {
-        omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
+        omap_pmic_init(1, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data);
 }
 void omap4_pmic_init(const char *pmic_type,
                    struct twl4030_platform_data *pmic_data,
-                    struct twl6040_platform_data *audio_data, int twl6040_irq);
+                    struct i2c_board_info *devices, int nr_devices);
 void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
                           u32 pdata_flags, u32 regulators_flags);
@@ -59,4 +60,6 @@ void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
 void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
                           u32 pdata_flags, u32 regulators_flags);
+void omap_twl4030_audio_init(char *card_name);
 #endif /* __OMAP_PMIC_COMMON__ */
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index dde8a11f47d5..3c434498e12e 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -25,8 +25,6 @@
 #include <asm/io.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
@@ -35,10 +33,12 @@
 #ifdef CONFIG_MFD_OMAP_USB_HOST
 #define OMAP_USBHS_DEVICE       "usbhs_omap"
+#define OMAP_USBTLL_DEVICE      "usbhs_tll"
 #define USBHS_UHH_HWMODNAME     "usb_host_hs"
 #define USBHS_TLL_HWMODNAME     "usb_tll_hs"
 static struct usbhs_omap_platform_data          usbhs_data;
+static struct usbtll_omap_platform_data         usbtll_data;
 static struct ehci_hcd_omap_platform_data       ehci_data;
 static struct ohci_hcd_omap_platform_data       ohci_data;
@@ -487,13 +487,14 @@ void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
 {
-        struct omap_hwmod       *oh[2];
+        struct omap_hwmod       *uhh_hwm, *tll_hwm;
        struct platform_device  *pdev;
        int                     bus_id = -1;
        int                     i;
        for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
                usbhs_data.port_mode[i] = pdata->port_mode[i];
+                usbtll_data.port_mode[i] = pdata->port_mode[i];
                ohci_data.port_mode[i] = pdata->port_mode[i];
                ehci_data.port_mode[i] = pdata->port_mode[i];
                ehci_data.reset_gpio_port[i] = pdata->reset_gpio_port[i];
@@ -512,25 +513,35 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
                setup_4430ohci_io_mux(pdata->port_mode);
        }
-        oh[0] = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
+        uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
-        if (!oh[0]) {
+        if (!uhh_hwm) {
                pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
                return;
        }
-        oh[1] = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
+        tll_hwm = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
-        if (!oh[1]) {
+        if (!tll_hwm) {
                pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
                return;
        }
-        pdev = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
+        pdev = omap_device_build(OMAP_USBTLL_DEVICE, bus_id, tll_hwm,
-                                (void *)&usbhs_data, sizeof(usbhs_data),
+                                &usbtll_data, sizeof(usbtll_data),
                                omap_uhhtll_latency,
                                ARRAY_SIZE(omap_uhhtll_latency), false);
        if (IS_ERR(pdev)) {
-                pr_err("Could not build hwmod devices %s,%s\n",
+                pr_err("Could not build hwmod device %s\n",
-                        USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME);
+                       USBHS_TLL_HWMODNAME);
+                return;
+        }
+        pdev = omap_device_build(OMAP_USBHS_DEVICE, bus_id, uhh_hwm,
+                                &usbhs_data, sizeof(usbhs_data),
+                                omap_uhhtll_latency,
+                                ARRAY_SIZE(omap_uhhtll_latency), false);
+        if (IS_ERR(pdev)) {
+                pr_err("Could not build hwmod devices %s\n",
+                       USBHS_UHH_HWMODNAME);
                return;
        }
 }
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index c4a576856661..51da21cb78f1 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -23,14 +23,13 @@
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
 #include <linux/usb/musb.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <mach/am35xx.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
+#include "am35xx.h"
 #include "mux.h"
 static struct musb_hdrc_config musb_config = {
@@ -117,7 +116,4 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
        dev->dma_mask = &musb_dmamask;
        dev->coherent_dma_mask = musb_dmamask;
        put_device(dev);
-        if (cpu_is_omap44xx())
-                omap4430_phy_init(dev);
 }
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 84da34f9a7cf..880249b17012 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -12,8 +12,7 @@
 #include <linux/init.h>
 #include <linux/bug.h>
-#include <plat/cpu.h>
+#include "soc.h"
 #include "voltage.h"
 #include "vc.h"
 #include "prm-regbits-34xx.h"
@@ -116,9 +115,8 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
        }
        if (!voltdm->pmic->uv_to_vsel) {
-                pr_err("%s: PMIC function to convert voltage in uV to"
+                pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
-                        "vsel not registered. Hence unable to scale voltage"
+                       __func__, voltdm->name);
-                        "for vdd_%s\n", __func__, voltdm->name);
                return -ENODATA;
        }
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 4dc60e83e00d..3ac8fe1d8213 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -195,8 +195,8 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
                        return &voltdm->volt_data[i];
        }
-        pr_notice("%s: Unable to match the current voltage with the voltage"
+        pr_notice("%s: Unable to match the current voltage with the voltage table for vdd_%s\n",
-                "table for vdd_%s\n", __func__, voltdm->name);
+                  __func__, voltdm->name);
        return ERR_PTR(-ENODATA);
 }
@@ -249,8 +249,8 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm,
                voltdm->scale = omap_vc_bypass_scale;
                return;
        default:
-                pr_warning("%s: Trying to change the method of voltage scaling"
+                pr_warn("%s: Trying to change the method of voltage scaling to an unsupported one!\n",
-                        "to an unsupported one!\n", __func__);
+                        __func__);
        }
 }
@@ -331,8 +331,8 @@ int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm)
        if (!voltdm || !pwrdm)
                return -EINVAL;
-        pr_debug("voltagedomain: associating powerdomain %s with voltagedomain "
+        pr_debug("voltagedomain: %s: associating powerdomain %s\n",
-                 "%s\n", pwrdm->name, voltdm->name);
+                 voltdm->name, pwrdm->name);
        list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list);
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 0ac2caf15941..7283b7ed7de8 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -16,7 +16,7 @@
 #include <linux/err.h>
-#include <plat/voltage.h>
+#include <linux/platform_data/voltage-omap.h>
 #include "vc.h"
 #include "vp.h"
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
index d0103c80d040..63afbfed3cbc 100644
--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -18,9 +18,8 @@
 #include <linux/err.h>
 #include <linux/init.h>
+#include "soc.h"
 #include "common.h"
-#include <plat/cpu.h>
 #include "prm-regbits-34xx.h"
 #include "omap_opp_data.h"
 #include "voltage.h"
diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
index f95c1bad9dc6..85241b828c02 100644
--- a/arch/arm/mach-omap2/vp.c
+++ b/arch/arm/mach-omap2/vp.c
@@ -138,8 +138,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
                udelay(1);
        }
        if (timeout >= VP_TRANXDONE_TIMEOUT) {
-                pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
+                pr_warn("%s: vdd_%s TRANXDONE timeout exceeded. Voltage change aborted",
-                        "Voltage change aborted", __func__, voltdm->name);
+                        __func__, voltdm->name);
                return -ETIMEDOUT;
        }
@@ -157,9 +157,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
        omap_test_timeout(vp->common->ops->check_txdone(vp->id),
                          VP_TRANXDONE_TIMEOUT, timeout);
        if (timeout >= VP_TRANXDONE_TIMEOUT)
-                pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
+                pr_err("%s: vdd_%s TRANXDONE timeout exceeded. TRANXDONE never got set after the voltage update\n",
-                        "TRANXDONE never got set after the voltage update\n",
+                       __func__, voltdm->name);
-                        __func__, voltdm->name);
        omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
@@ -176,8 +175,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
        }
        if (timeout >= VP_TRANXDONE_TIMEOUT)
-                pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
+                pr_warn("%s: vdd_%s TRANXDONE timeout exceeded while trying to clear the TRANXDONE status\n",
-                        "to clear the TRANXDONE status\n",
                        __func__, voltdm->name);
        /* Clear force bit */
@@ -257,8 +255,8 @@ void omap_vp_disable(struct voltagedomain *voltdm)
        /* If VP is already disabled, do nothing. Return */
        if (!vp->enabled) {
-                pr_warning("%s: Trying to disable VP for vdd_%s when"
+                pr_warn("%s: Trying to disable VP for vdd_%s when it is already disabled\n",
-                        "it is already disabled\n", __func__, voltdm->name);
+                        __func__, voltdm->name);
                return;
        }
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index eaac83d1df6f..b5efc0fd31cb 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -113,7 +113,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
        /*
         * Setup MBUS dram target info.
         */
-        orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
+        orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                    (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE);
 }
 void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index a6cd14ab1e4e..b3eb3da01160 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -30,8 +30,8 @@
 #include <mach/bridge-regs.h>
 #include <mach/hardware.h>
 #include <mach/orion5x.h>
-#include <plat/orion_nand.h>
+#include <linux/platform_data/mtd-orion_nand.h>
-#include <plat/ehci-orion.h>
+#include <linux/platform_data/usb-ehci-orion.h>
 #include <plat/time.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
@@ -42,22 +42,12 @@
 ****************************************************************************/
 static struct map_desc orion5x_io_desc[] __initdata = {
        {
-                .virtual        = ORION5X_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) ORION5X_REGS_VIRT_BASE,
                .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
                .length         = ORION5X_REGS_SIZE,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = ORION5X_PCIE_IO_VIRT_BASE,
+                .virtual        = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
-                .length         = ORION5X_PCIE_IO_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = ORION5X_PCI_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
-                .length         = ORION5X_PCI_IO_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
                .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
                .length         = ORION5X_PCIE_WA_SIZE,
                .type           = MT_DEVICE,
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index d75dcfa0f01c..e3629c063df2 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -27,6 +27,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
+#include <plat/orion-gpio.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 49a3fd630313..41fe2b1ff47c 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -24,7 +24,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
-#include <plat/orion_nand.h>
+#include <linux/platform_data/mtd-orion_nand.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index d470864b4e42..e533588880ff 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -34,6 +34,7 @@
 #include <asm/mach/pci.h>
 #include <asm/system_info.h>
 #include <mach/orion5x.h>
+#include <plat/orion-gpio.h>
 #include "common.h"
 #include "mpp.h"
@@ -700,7 +701,7 @@ static void __init dns323_init(void)
                 * Note: AFAIK, rev B1 needs the same treatement but I'll let
                 * somebody else test it.
                 */
-                writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c);
+                writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c);
                break;
        }
 }
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index 11a3c1e9801f..461fd69a10ae 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -13,27 +13,27 @@
 #include <mach/orion5x.h>
-#define CPU_CONF                (ORION5X_BRIDGE_VIRT_BASE | 0x100)
+#define CPU_CONF                (ORION5X_BRIDGE_VIRT_BASE + 0x100)
-#define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE | 0x104)
+#define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE + 0x104)
-#define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE | 0x108)
+#define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE + 0x108)
 #define WDT_RESET_OUT_EN        0x0002
-#define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
+#define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
-#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE | 0x110)
+#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE + 0x110)
-#define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
+#define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
 #define WDT_INT_REQ             0x0008
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
-#define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE | 0x200)
+#define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE + 0x200)
-#define MAIN_IRQ_MASK           (ORION5X_BRIDGE_VIRT_BASE | 0x204)
+#define MAIN_IRQ_MASK           (ORION5X_BRIDGE_VIRT_BASE + 0x204)
-#define TIMER_VIRT_BASE         (ORION5X_BRIDGE_VIRT_BASE | 0x300)
+#define TIMER_VIRT_BASE         (ORION5X_BRIDGE_VIRT_BASE + 0x300)
-#define TIMER_PHYS_BASE         (ORION5X_BRIDGE_PHYS_BASE | 0x300)
+#define TIMER_PHYS_BASE         (ORION5X_BRIDGE_PHYS_BASE + 0x300)
 #endif
diff --git a/arch/arm/mach-orion5x/include/mach/gpio.h b/arch/arm/mach-orion5x/include/mach/gpio.h
deleted file mode 100644
index a1d0b78decb1..000000000000
--- a/arch/arm/mach-orion5x/include/mach/gpio.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * arch/arm/mach-orion5x/include/mach/gpio.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <plat/gpio.h>
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
deleted file mode 100644
index 1aa5d0a50a0b..000000000000
--- a/arch/arm/mach-orion5x/include/mach/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-orion5x/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-#include <mach/orion5x.h>
-#include <asm/sizes.h>
-#define IO_SPACE_LIMIT          SZ_2M
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)(addr + ORION5X_PCIE_IO_VIRT_BASE);
-}
-#define __io(a)                  __io(a)
-#endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 683e085ce162..d265f5484a8e 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -31,31 +31,29 @@
 * fc000000     device bus mappings (cs0/cs1)
 *
 * virt         phys            size
- * fdd00000     f1000000        1M      on-chip peripheral registers
+ * fe000000     f1000000        1M      on-chip peripheral registers
- * fde00000     f2000000        1M      PCIe I/O space
+ * fee00000     f2000000        64K     PCIe I/O space
- * fdf00000     f2100000        1M      PCI I/O space
+ * fee10000     f2100000        64K     PCI I/O space
- * fe000000     f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
+ * fd000000     f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
 ****************************************************************************/
 #define ORION5X_REGS_PHYS_BASE          0xf1000000
-#define ORION5X_REGS_VIRT_BASE          0xfdd00000
+#define ORION5X_REGS_VIRT_BASE          IOMEM(0xfe000000)
 #define ORION5X_REGS_SIZE               SZ_1M
 #define ORION5X_PCIE_IO_PHYS_BASE       0xf2000000
-#define ORION5X_PCIE_IO_VIRT_BASE       0xfde00000
 #define ORION5X_PCIE_IO_BUS_BASE        0x00000000
-#define ORION5X_PCIE_IO_SIZE            SZ_1M
+#define ORION5X_PCIE_IO_SIZE            SZ_64K
 #define ORION5X_PCI_IO_PHYS_BASE        0xf2100000
-#define ORION5X_PCI_IO_VIRT_BASE        0xfdf00000
+#define ORION5X_PCI_IO_BUS_BASE         0x00010000
-#define ORION5X_PCI_IO_BUS_BASE         0x00100000
+#define ORION5X_PCI_IO_SIZE             SZ_64K
-#define ORION5X_PCI_IO_SIZE             SZ_1M
 #define ORION5X_SRAM_PHYS_BASE          (0xf2200000)
 #define ORION5X_SRAM_SIZE               SZ_8K
 /* Relevant only for Orion-1/Orion-NAS */
 #define ORION5X_PCIE_WA_PHYS_BASE       0xf0000000
-#define ORION5X_PCIE_WA_VIRT_BASE       0xfe000000
+#define ORION5X_PCIE_WA_VIRT_BASE       IOMEM(0xfd000000)
 #define ORION5X_PCIE_WA_SIZE            SZ_16M
 #define ORION5X_PCIE_MEM_PHYS_BASE      0xe0000000
@@ -68,42 +66,42 @@
 * Orion Registers Map
 ******************************************************************************/
-#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
+#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x00000)
-#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE | 0x1500)
+#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE + 0x1500)
-#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
+#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE + 0x10000)
-#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
+#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE + 0x10000)
-#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE + (x))
 #define  GPIO_VIRT_BASE                 ORION5X_DEV_BUS_REG(0x0100)
-#define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
+#define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE + 0x0600)
-#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
+#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE + 0x1000)
-#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE + 0x2000)
-#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE + 0x2000)
-#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE + 0x2100)
-#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
+#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE + 0x2100)
-#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE | 0x20000)
+#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE + 0x20000)
-#define ORION5X_BRIDGE_PHYS_BASE        (ORION5X_REGS_PHYS_BASE | 0x20000)
+#define ORION5X_BRIDGE_PHYS_BASE        (ORION5X_REGS_PHYS_BASE + 0x20000)
-#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x30000)
+#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x30000)
-#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x40000)
+#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x40000)
-#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x50000)
+#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0x50000)
-#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x50000)
+#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x50000)
-#define ORION5X_XOR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x60900)
+#define ORION5X_XOR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x60900)
-#define ORION5X_XOR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x60900)
+#define ORION5X_XOR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x60900)
-#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x70000)
+#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x70000)
-#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x70000)
+#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x70000)
-#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x80000)
+#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0x80000)
-#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x80000)
+#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x80000)
-#define ORION5X_CRYPTO_PHYS_BASE        (ORION5X_REGS_PHYS_BASE | 0x90000)
+#define ORION5X_CRYPTO_PHYS_BASE        (ORION5X_REGS_PHYS_BASE + 0x90000)
-#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0xa0000)
+#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0xa0000)
-#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0xa0000)
+#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0xa0000)
 /*******************************************************************************
 * Device Bus Registers
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index 17da7091d310..30a192b9c517 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -12,7 +12,9 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
+#include <plat/orion-gpio.h>
 #include <plat/irq.h>
 static int __initdata gpio0_irqs[4] = {
@@ -24,11 +26,11 @@ static int __initdata gpio0_irqs[4] = {
 void __init orion5x_init_irq(void)
 {
-        orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
+        orion_irq_init(0, MAIN_IRQ_MASK);
        /*
         * Initialize gpiolib for GPIOs 0-31.
         */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0,
                        IRQ_ORION5X_GPIO_START, gpio0_irqs);
 }
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 1e458efafb9a..f1ae10ae5bd4 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -24,7 +24,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
-#include <plat/orion_nand.h>
+#include <linux/platform_data/mtd-orion_nand.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index 0180c393c711..3506f16c0bf2 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -25,6 +25,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/orion5x.h>
+#include <plat/orion-gpio.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index cb19e1661bb3..cd50e328db2a 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -38,7 +38,7 @@
 /*****************************************************************************
 * PCIe controller
 ****************************************************************************/
-#define PCIE_BASE       ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
+#define PCIE_BASE       (ORION5X_PCIE_VIRT_BASE)
 void __init orion5x_pcie_id(u32 *dev, u32 *rev)
 {
@@ -111,7 +111,7 @@ static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
                return PCIBIOS_DEVICE_NOT_FOUND;
        }
-        ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
+        ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
                                    bus, devfn, where, size, val);
        return ret;
@@ -162,35 +162,25 @@ static int __init pcie_setup(struct pci_sys_data *sys)
                pcie_ops.read = pcie_rd_conf_wa;
        }
+        pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
        /*
         * Request resources.
         */
-        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+        res = kzalloc(sizeof(struct resource), GFP_KERNEL);
        if (!res)
                panic("pcie_setup unable to alloc resources");
        /*
-         * IORESOURCE_IO
-         */
-        sys->io_offset = 0;
-        res[0].name = "PCIe I/O Space";
-        res[0].flags = IORESOURCE_IO;
-        res[0].start = ORION5X_PCIE_IO_BUS_BASE;
-        res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
-        if (request_resource(&ioport_resource, &res[0]))
-                panic("Request PCIe IO resource failed\n");
-        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
-        /*
         * IORESOURCE_MEM
         */
-        res[1].name = "PCIe Memory Space";
+        res->name = "PCIe Memory Space";
-        res[1].flags = IORESOURCE_MEM;
+        res->flags = IORESOURCE_MEM;
-        res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
+        res->start = ORION5X_PCIE_MEM_PHYS_BASE;
-        res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
+        res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
-        if (request_resource(&iomem_resource, &res[1]))
+        if (request_resource(&iomem_resource, res))
                panic("Request PCIe Memory resource failed\n");
-        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
        return 1;
 }
@@ -198,7 +188,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
 /*****************************************************************************
 * PCI controller
 ****************************************************************************/
-#define ORION5X_PCI_REG(x)      (ORION5X_PCI_VIRT_BASE | (x))
+#define ORION5X_PCI_REG(x)      (ORION5X_PCI_VIRT_BASE + (x))
 #define PCI_MODE                ORION5X_PCI_REG(0xd00)
 #define PCI_CMD                 ORION5X_PCI_REG(0xc00)
 #define PCI_P2P_CONF            ORION5X_PCI_REG(0x1d14)
@@ -489,35 +479,25 @@ static int __init pci_setup(struct pci_sys_data *sys)
         */
        orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
+        pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
        /*
         * Request resources
         */
-        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+        res = kzalloc(sizeof(struct resource), GFP_KERNEL);
        if (!res)
                panic("pci_setup unable to alloc resources");
        /*
-         * IORESOURCE_IO
-         */
-        sys->io_offset = 0;
-        res[0].name = "PCI I/O Space";
-        res[0].flags = IORESOURCE_IO;
-        res[0].start = ORION5X_PCI_IO_BUS_BASE;
-        res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
-        if (request_resource(&ioport_resource, &res[0]))
-                panic("Request PCI IO resource failed\n");
-        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
-        /*
         * IORESOURCE_MEM
         */
-        res[1].name = "PCI Memory Space";
+        res->name = "PCI Memory Space";
-        res[1].flags = IORESOURCE_MEM;
+        res->flags = IORESOURCE_MEM;
-        res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
+        res->start = ORION5X_PCI_MEM_PHYS_BASE;
-        res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
+        res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
-        if (request_resource(&iomem_resource, &res[1]))
+        if (request_resource(&iomem_resource, res))
                panic("Request PCI Memory resource failed\n");
-        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
        return 1;
 }
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 78a6a11d8216..9b1c95310291 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -18,7 +18,6 @@
 #include <linux/ethtool.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index 2f5dc54cd4cd..51ba2b81a10b 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -19,7 +19,6 @@
 #include <linux/i2c.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 399130fac0b6..0a56b9444f1b 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -19,8 +19,8 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/ata_platform.h>
 #include <linux/i2c.h>
+#include <linux/leds.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
@@ -53,12 +53,6 @@
 #define RD88F5182_PCI_SLOT0_IRQ_A_PIN   7
 #define RD88F5182_PCI_SLOT0_IRQ_B_PIN   6
-/*
- * GPIO Debug LED
- */
-#define RD88F5182_GPIO_DBG_LED          0
 /*****************************************************************************
 * 16M NOR Flash on Device bus CS1
 ****************************************************************************/
@@ -83,55 +77,32 @@ static struct platform_device rd88f5182_nor_flash = {
        .resource               = &rd88f5182_nor_flash_resource,
 };
-#ifdef CONFIG_LEDS
 /*****************************************************************************
- * Use GPIO debug led as CPU active indication
+ * Use GPIO LED as CPU active indication
 ****************************************************************************/
-static void rd88f5182_dbgled_event(led_event_t evt)
+#define RD88F5182_GPIO_LED              0
-{
-        int val;
-        if (evt == led_idle_end)
-                val = 1;
-        else if (evt == led_idle_start)
-                val = 0;
-        else
-                return;
-        gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
-}
-static int __init rd88f5182_dbgled_init(void)
-{
-        int pin;
-        if (machine_is_rd88f5182()) {
-                pin = RD88F5182_GPIO_DBG_LED;
-                if (gpio_request(pin, "DBGLED") == 0) {
+static struct gpio_led rd88f5182_gpio_led_pins[] = {
-                        if (gpio_direction_output(pin, 0) != 0) {
+        {
-                                printk(KERN_ERR "rd88f5182_dbgled_init failed "
+                .name           = "rd88f5182:cpu",
-                                                "to set output pin %d\n", pin);
+                .default_trigger = "cpu0",
-                                gpio_free(pin);
+                .gpio           = RD88F5182_GPIO_LED,
-                                return 0;
+        },
-                        }
+};
-                } else {
-                        printk(KERN_ERR "rd88f5182_dbgled_init failed "
-                                        "to request gpio %d\n", pin);
-                        return 0;
-                }
-                leds_event = rd88f5182_dbgled_event;
-        }
-        return 0;
-}
-__initcall(rd88f5182_dbgled_init);
+static struct gpio_led_platform_data rd88f5182_gpio_led_data = {
+        .leds           = rd88f5182_gpio_led_pins,
+        .num_leds       = ARRAY_SIZE(rd88f5182_gpio_led_pins),
+};
-#endif
+static struct platform_device rd88f5182_gpio_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &rd88f5182_gpio_led_data,
+        },
+};
 /*****************************************************************************
 * PCI
@@ -298,6 +269,7 @@ static void __init rd88f5182_init(void)
        orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
        platform_device_register(&rd88f5182_nor_flash);
+        platform_device_register(&rd88f5182_gpio_leds);
        i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
 }
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 92df49c1b62a..ed50910b08a4 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -20,7 +20,6 @@
 #include <linux/ethtool.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index b4203277f3cd..b0727dcd1ef9 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -36,7 +36,7 @@
 * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
 */
 #define TS78XX_FPGA_REGS_PHYS_BASE      0xe8000000
-#define TS78XX_FPGA_REGS_VIRT_BASE      0xff900000
+#define TS78XX_FPGA_REGS_VIRT_BASE      IOMEM(0xff900000)
 #define TS78XX_FPGA_REGS_SIZE           SZ_1M
 static struct ts78xx_fpga_data ts78xx_fpga = {
@@ -50,7 +50,7 @@ static struct ts78xx_fpga_data ts78xx_fpga = {
 ****************************************************************************/
 static struct map_desc ts78xx_io_desc[] __initdata = {
        {
-                .virtual        = TS78XX_FPGA_REGS_VIRT_BASE,
+                .virtual        = (unsigned long)TS78XX_FPGA_REGS_VIRT_BASE,
                .pfn            = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
                .length         = TS78XX_FPGA_REGS_SIZE,
                .type           = MT_DEVICE,
@@ -80,8 +80,8 @@ static struct mv_sata_platform_data ts78xx_sata_data = {
 /*****************************************************************************
 * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
 ****************************************************************************/
-#define TS_RTC_CTRL     (TS78XX_FPGA_REGS_VIRT_BASE | 0x808)
+#define TS_RTC_CTRL     (TS78XX_FPGA_REGS_VIRT_BASE + 0x808)
-#define TS_RTC_DATA     (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c)
+#define TS_RTC_DATA     (TS78XX_FPGA_REGS_VIRT_BASE + 0x80c)
 static unsigned char ts78xx_ts_rtc_readbyte(unsigned long addr)
 {
@@ -162,8 +162,8 @@ static void ts78xx_ts_rtc_unload(void)
 /*****************************************************************************
 * NAND Flash
 ****************************************************************************/
-#define TS_NAND_CTRL    (TS78XX_FPGA_REGS_VIRT_BASE | 0x800)    /* VIRT */
+#define TS_NAND_CTRL    (TS78XX_FPGA_REGS_VIRT_BASE + 0x800)    /* VIRT */
-#define TS_NAND_DATA    (TS78XX_FPGA_REGS_PHYS_BASE | 0x804)    /* PHYS */
+#define TS_NAND_DATA    (TS78XX_FPGA_REGS_PHYS_BASE + 0x804)    /* PHYS */
 /*
 * hardware specific access to control-lines
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
new file mode 100644
index 000000000000..868796f8085c
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -0,0 +1,14 @@
+config ARCH_PICOXCELL
+        bool "Picochip PicoXcell" if ARCH_MULTI_V6
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_PATCH_PHYS_VIRT
+        select ARM_VIC
+        select CPU_V6K
+        select DW_APB_TIMER
+        select DW_APB_TIMER_OF
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
+        select HAVE_TCM
+        select NO_IOPORT
+        select SPARSE_IRQ
+        select USE_OF
diff --git a/arch/arm/mach-picoxcell/Makefile.boot b/arch/arm/mach-picoxcell/Makefile.boot
deleted file mode 100644
index b3271754e9fd..000000000000
--- a/arch/arm/mach-picoxcell/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
-zreladdr-y := 0x00008000
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 8f9a0b47a7fa..f6c0849af5e9 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -20,14 +20,15 @@
 #include <asm/hardware/vic.h>
 #include <asm/mach/map.h>
-#include <mach/map.h>
-#include <mach/picoxcell_soc.h>
 #include "common.h"
-#define WDT_CTRL_REG_EN_MASK    (1 << 0)
+#define PHYS_TO_IO(x)                   (((x) & 0x00ffffff) | 0xfe000000)
-#define WDT_CTRL_REG_OFFS       (0x00)
+#define PICOXCELL_PERIPH_BASE           0x80000000
-#define WDT_TIMEOUT_REG_OFFS    (0x04)
+#define PICOXCELL_PERIPH_LENGTH         SZ_4M
+#define WDT_CTRL_REG_EN_MASK            (1 << 0)
+#define WDT_CTRL_REG_OFFS               (0x00)
+#define WDT_TIMEOUT_REG_OFFS            (0x04)
 static void __iomem *wdt_regs;
 /*
diff --git a/arch/arm/mach-picoxcell/include/mach/gpio.h b/arch/arm/mach-picoxcell/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-picoxcell/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-picoxcell/include/mach/map.h b/arch/arm/mach-picoxcell/include/mach/map.h
deleted file mode 100644
index c06afad218bb..000000000000
--- a/arch/arm/mach-picoxcell/include/mach/map.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __PICOXCELL_MAP_H__
-#define __PICOXCELL_MAP_H__
-#define PHYS_TO_IO(x)           (((x) & 0x00ffffff) | 0xfe000000)
-#ifdef __ASSEMBLY__
-#define IO_ADDRESS(x)           PHYS_TO_IO((x))
-#else
-#define IO_ADDRESS(x)           (void __iomem __force *)(PHYS_TO_IO((x)))
-#endif
-#endif /* __PICOXCELL_MAP_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h b/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
deleted file mode 100644
index 5566fc88ddbc..000000000000
--- a/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This file contains the hardware definitions of the picoXcell SoC devices.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __PICOXCELL_SOC_H__
-#define __PICOXCELL_SOC_H__
-#define PICOXCELL_UART1_BASE            0x80230000
-#define PICOXCELL_PERIPH_BASE           0x80000000
-#define PICOXCELL_PERIPH_LENGTH         SZ_4M
-#define PICOXCELL_VIC0_BASE             0x80060000
-#define PICOXCELL_VIC1_BASE             0x80064000
-#endif /* __PICOXCELL_SOC_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/timex.h b/arch/arm/mach-picoxcell/include/mach/timex.h
deleted file mode 100644
index 6c540a69f405..000000000000
--- a/arch/arm/mach-picoxcell/include/mach/timex.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __TIMEX_H__
-#define __TIMEX_H__
-/* Bogus value to allow the kernel to compile. */
-#define CLOCK_TICK_RATE         1000000
-#endif /* __TIMEX_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/uncompress.h b/arch/arm/mach-picoxcell/include/mach/uncompress.h
deleted file mode 100644
index b60b19d1d739..000000000000
--- a/arch/arm/mach-picoxcell/include/mach/uncompress.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define putc(c)
-#define flush()
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-pnx4008/Makefile b/arch/arm/mach-pnx4008/Makefile
deleted file mode 100644
index 777564c90a12..000000000000
--- a/arch/arm/mach-pnx4008/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-obj-y                   := core.o irq.o time.o clock.o gpio.o serial.o dma.o i2c.o
-obj-m                   :=
-obj-n                   :=
-obj-                    :=
-# Power Management
-obj-$(CONFIG_PM) += pm.o sleep.o
diff --git a/arch/arm/mach-pnx4008/Makefile.boot b/arch/arm/mach-pnx4008/Makefile.boot
deleted file mode 100644
index 9fa19baa7f2e..000000000000
--- a/arch/arm/mach-pnx4008/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-   zreladdr-y           += 0x80008000
-params_phys-y           := 0x80000100
-initrd_phys-y           := 0x80800000
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c
deleted file mode 100644
index a4a3819c96cb..000000000000
--- a/arch/arm/mach-pnx4008/clock.c
+++ /dev/null
@@ -1,1001 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/clock.c
- *
- * Clock control driver for PNX4008
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- * Generic clock management functions are partially based on:
- *  linux/arch/arm/mach-omap/clock.c
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <mach/hardware.h>
-#include <mach/clock.h>
-#include "clock.h"
-/*forward declaration*/
-static struct clk per_ck;
-static struct clk hclk_ck;
-static struct clk ck_1MHz;
-static struct clk ck_13MHz;
-static struct clk ck_pll1;
-static int local_set_rate(struct clk *clk, u32 rate);
-static inline void clock_lock(void)
-{
-        local_irq_disable();
-}
-static inline void clock_unlock(void)
-{
-        local_irq_enable();
-}
-static void propagate_rate(struct clk *clk)
-{
-        struct clk *tmp_clk;
-        tmp_clk = clk;
-        while (tmp_clk->propagate_next) {
-                tmp_clk = tmp_clk->propagate_next;
-                local_set_rate(tmp_clk, tmp_clk->user_rate);
-        }
-}
-static void clk_reg_disable(struct clk *clk)
-{
-        if (clk->enable_reg)
-                __raw_writel(__raw_readl(clk->enable_reg) &
-                             ~(1 << clk->enable_shift), clk->enable_reg);
-}
-static int clk_reg_enable(struct clk *clk)
-{
-        if (clk->enable_reg)
-                __raw_writel(__raw_readl(clk->enable_reg) |
-                             (1 << clk->enable_shift), clk->enable_reg);
-        return 0;
-}
-static inline void clk_reg_disable1(struct clk *clk)
-{
-        if (clk->enable_reg1)
-                __raw_writel(__raw_readl(clk->enable_reg1) &
-                             ~(1 << clk->enable_shift1), clk->enable_reg1);
-}
-static inline void clk_reg_enable1(struct clk *clk)
-{
-        if (clk->enable_reg1)
-                __raw_writel(__raw_readl(clk->enable_reg1) |
-                             (1 << clk->enable_shift1), clk->enable_reg1);
-}
-static int clk_wait_for_pll_lock(struct clk *clk)
-{
-        int i;
-        i = 0;
-        while (i++ < 0xFFF && !(__raw_readl(clk->scale_reg) & 1)) ;     /*wait for PLL to lock */
-        if (!(__raw_readl(clk->scale_reg) & 1)) {
-                printk(KERN_ERR
-                       "%s ERROR: failed to lock, scale reg data: %x\n",
-                       clk->name, __raw_readl(clk->scale_reg));
-                return -1;
-        }
-        return 0;
-}
-static int switch_to_dirty_13mhz(struct clk *clk)
-{
-        int i;
-        int ret;
-        u32 tmp_reg;
-        ret = 0;
-        if (!clk->rate)
-                clk_reg_enable1(clk);
-        tmp_reg = __raw_readl(clk->parent_switch_reg);
-        /*if 13Mhz clock selected, select 13'MHz (dirty) source from OSC */
-        if (!(tmp_reg & 1)) {
-                tmp_reg |= (1 << 1);    /* Trigger switch to 13'MHz (dirty) clock */
-                __raw_writel(tmp_reg, clk->parent_switch_reg);
-                i = 0;
-                while (i++ < 0xFFF && !(__raw_readl(clk->parent_switch_reg) & 1)) ;     /*wait for 13'MHz selection status */
-                if (!(__raw_readl(clk->parent_switch_reg) & 1)) {
-                        printk(KERN_ERR
-                               "%s ERROR: failed to select 13'MHz, parent sw reg data: %x\n",
-                               clk->name, __raw_readl(clk->parent_switch_reg));
-                        ret = -1;
-                }
-        }
-        if (!clk->rate)
-                clk_reg_disable1(clk);
-        return ret;
-}
-static int switch_to_clean_13mhz(struct clk *clk)
-{
-        int i;
-        int ret;
-        u32 tmp_reg;
-        ret = 0;
-        if (!clk->rate)
-                clk_reg_enable1(clk);
-        tmp_reg = __raw_readl(clk->parent_switch_reg);
-        /*if 13'Mhz clock selected, select 13MHz (clean) source from OSC */
-        if (tmp_reg & 1) {
-                tmp_reg &= ~(1 << 1);   /* Trigger switch to 13MHz (clean) clock */
-                __raw_writel(tmp_reg, clk->parent_switch_reg);
-                i = 0;
-                while (i++ < 0xFFF && (__raw_readl(clk->parent_switch_reg) & 1)) ;      /*wait for 13MHz selection status */
-                if (__raw_readl(clk->parent_switch_reg) & 1) {
-                        printk(KERN_ERR
-                               "%s ERROR: failed to select 13MHz, parent sw reg data: %x\n",
-                               clk->name, __raw_readl(clk->parent_switch_reg));
-                        ret = -1;
-                }
-        }
-        if (!clk->rate)
-                clk_reg_disable1(clk);
-        return ret;
-}
-static int set_13MHz_parent(struct clk *clk, struct clk *parent)
-{
-        int ret = -EINVAL;
-        if (parent == &ck_13MHz)
-                ret = switch_to_clean_13mhz(clk);
-        else if (parent == &ck_pll1)
-                ret = switch_to_dirty_13mhz(clk);
-        return ret;
-}
-#define PLL160_MIN_FCCO 156000
-#define PLL160_MAX_FCCO 320000
-/*
- * Calculate pll160 settings.
- * Possible input: up to 320MHz with step of clk->parent->rate.
- * In PNX4008 parent rate for pll160s may be either 1 or 13MHz.
- * Ignored paths: "feedback" (bit 13 set), "div-by-N".
- * Setting ARM PLL4 rate to 0 will put CPU into direct run mode.
- * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
- * Please refer to PNX4008 IC manual for details.
- */
-static int pll160_set_rate(struct clk *clk, u32 rate)
-{
-        u32 tmp_reg, tmp_m, tmp_2p, i;
-        u32 parent_rate;
-        int ret = -EINVAL;
-        parent_rate = clk->parent->rate;
-        if (!parent_rate)
-                goto out;
-        /* set direct run for ARM or disable output for others  */
-        clk_reg_disable(clk);
-        /* disable source input as well (ignored for ARM) */
-        clk_reg_disable1(clk);
-        tmp_reg = __raw_readl(clk->scale_reg);
-        tmp_reg &= ~0x1ffff;    /*clear all settings, power down */
-        __raw_writel(tmp_reg, clk->scale_reg);
-        rate -= rate % parent_rate;     /*round down the input */
-        if (rate > PLL160_MAX_FCCO)
-                rate = PLL160_MAX_FCCO;
-        if (!rate) {
-                clk->rate = 0;
-                ret = 0;
-                goto out;
-        }
-        clk_reg_enable1(clk);
-        tmp_reg = __raw_readl(clk->scale_reg);
-        if (rate == parent_rate) {
-                /*enter direct bypass mode */
-                tmp_reg |= ((1 << 14) | (1 << 15));
-                __raw_writel(tmp_reg, clk->scale_reg);
-                clk->rate = parent_rate;
-                clk_reg_enable(clk);
-                ret = 0;
-                goto out;
-        }
-        i = 0;
-        for (tmp_2p = 1; tmp_2p < 16; tmp_2p <<= 1) {
-                if (rate * tmp_2p >= PLL160_MIN_FCCO)
-                        break;
-                i++;
-        }
-        if (tmp_2p > 1)
-                tmp_reg |= ((i - 1) << 11);
-        else
-                tmp_reg |= (1 << 14);   /*direct mode, no divide */
-        tmp_m = rate * tmp_2p;
-        tmp_m /= parent_rate;
-        tmp_reg |= (tmp_m - 1) << 1;    /*calculate M */
-        tmp_reg |= (1 << 16);   /*power up PLL */
-        __raw_writel(tmp_reg, clk->scale_reg);
-        if (clk_wait_for_pll_lock(clk) < 0) {
-                clk_reg_disable(clk);
-                clk_reg_disable1(clk);
-                tmp_reg = __raw_readl(clk->scale_reg);
-                tmp_reg &= ~0x1ffff;    /*clear all settings, power down */
-                __raw_writel(tmp_reg, clk->scale_reg);
-                clk->rate = 0;
-                ret = -EFAULT;
-                goto out;
-        }
-        clk->rate = (tmp_m * parent_rate) / tmp_2p;
-        if (clk->flags & RATE_PROPAGATES)
-                propagate_rate(clk);
-        clk_reg_enable(clk);
-        ret = 0;
-out:
-        return ret;
-}
-/*configure PER_CLK*/
-static int per_clk_set_rate(struct clk *clk, u32 rate)
-{
-        u32 tmp;
-        tmp = __raw_readl(clk->scale_reg);
-        tmp &= ~(0x1f << 2);
-        tmp |= ((clk->parent->rate / clk->rate) - 1) << 2;
-        __raw_writel(tmp, clk->scale_reg);
-        clk->rate = rate;
-        return 0;
-}
-/*configure HCLK*/
-static int hclk_set_rate(struct clk *clk, u32 rate)
-{
-        u32 tmp;
-        tmp = __raw_readl(clk->scale_reg);
-        tmp = tmp & ~0x3;
-        switch (rate) {
-        case 1:
-                break;
-        case 2:
-                tmp |= 1;
-                break;
-        case 4:
-                tmp |= 2;
-                break;
-        }
-        __raw_writel(tmp, clk->scale_reg);
-        clk->rate = rate;
-        return 0;
-}
-static u32 hclk_round_rate(struct clk *clk, u32 rate)
-{
-        switch (rate) {
-        case 1:
-        case 4:
-                return rate;
-        }
-        return 2;
-}
-static u32 per_clk_round_rate(struct clk *clk, u32 rate)
-{
-        return CLK_RATE_13MHZ;
-}
-static int on_off_set_rate(struct clk *clk, u32 rate)
-{
-        if (rate) {
-                clk_reg_enable(clk);
-                clk->rate = 1;
-        } else {
-                clk_reg_disable(clk);
-                clk->rate = 0;
-        }
-        return 0;
-}
-static int on_off_inv_set_rate(struct clk *clk, u32 rate)
-{
-        if (rate) {
-                clk_reg_disable(clk);   /*enable bit is inverted */
-                clk->rate = 1;
-        } else {
-                clk_reg_enable(clk);
-                clk->rate = 0;
-        }
-        return 0;
-}
-static u32 on_off_round_rate(struct clk *clk, u32 rate)
-{
-        return (rate ? 1 : 0);
-}
-static u32 pll4_round_rate(struct clk *clk, u32 rate)
-{
-        if (rate > CLK_RATE_208MHZ)
-                rate = CLK_RATE_208MHZ;
-        if (rate == CLK_RATE_208MHZ && hclk_ck.user_rate == 1)
-                rate = CLK_RATE_208MHZ - CLK_RATE_13MHZ;
-        return (rate - (rate % (hclk_ck.user_rate * CLK_RATE_13MHZ)));
-}
-static u32 pll3_round_rate(struct clk *clk, u32 rate)
-{
-        if (rate > CLK_RATE_208MHZ)
-                rate = CLK_RATE_208MHZ;
-        return (rate - rate % CLK_RATE_13MHZ);
-}
-static u32 pll5_round_rate(struct clk *clk, u32 rate)
-{
-        return (rate ? CLK_RATE_48MHZ : 0);
-}
-static u32 ck_13MHz_round_rate(struct clk *clk, u32 rate)
-{
-        return (rate ? CLK_RATE_13MHZ : 0);
-}
-static int ck_13MHz_set_rate(struct clk *clk, u32 rate)
-{
-        if (rate) {
-                clk_reg_disable(clk);   /*enable bit is inverted */
-                udelay(500);
-                clk->rate = CLK_RATE_13MHZ;
-                ck_1MHz.rate = CLK_RATE_1MHZ;
-        } else {
-                clk_reg_enable(clk);
-                clk->rate = 0;
-                ck_1MHz.rate = 0;
-        }
-        return 0;
-}
-static int pll1_set_rate(struct clk *clk, u32 rate)
-{
-#if 0 /* doesn't work on some boards, probably a HW BUG */
-        if (rate) {
-                clk_reg_disable(clk);   /*enable bit is inverted */
-                if (!clk_wait_for_pll_lock(clk)) {
-                        clk->rate = CLK_RATE_13MHZ;
-                } else {
-                        clk_reg_enable(clk);
-                        clk->rate = 0;
-                }
-        } else {
-                clk_reg_enable(clk);
-                clk->rate = 0;
-        }
-#endif
-        return 0;
-}
-/* Clock sources */
-static struct clk osc_13MHz = {
-        .name = "osc_13MHz",
-        .flags = FIXED_RATE,
-        .rate = CLK_RATE_13MHZ,
-};
-static struct clk ck_13MHz = {
-        .name = "ck_13MHz",
-        .parent = &osc_13MHz,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &ck_13MHz_round_rate,
-        .set_rate = &ck_13MHz_set_rate,
-        .enable_reg = OSC13CTRL_REG,
-        .enable_shift = 0,
-        .rate = CLK_RATE_13MHZ,
-};
-static struct clk osc_32KHz = {
-        .name = "osc_32KHz",
-        .flags = FIXED_RATE,
-        .rate = CLK_RATE_32KHZ,
-};
-/*attached to PLL5*/
-static struct clk ck_1MHz = {
-        .name = "ck_1MHz",
-        .flags = FIXED_RATE | PARENT_SET_RATE,
-        .parent = &ck_13MHz,
-};
-/* PLL1 (397) - provides 13' MHz clock */
-static struct clk ck_pll1 = {
-        .name = "ck_pll1",
-        .parent = &osc_32KHz,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &ck_13MHz_round_rate,
-        .set_rate = &pll1_set_rate,
-        .enable_reg = PLLCTRL_REG,
-        .enable_shift = 1,
-        .scale_reg = PLLCTRL_REG,
-        .rate = CLK_RATE_13MHZ,
-};
-/* CPU/Bus PLL */
-static struct clk ck_pll4 = {
-        .name = "ck_pll4",
-        .parent = &ck_pll1,
-        .flags = RATE_PROPAGATES | NEEDS_INITIALIZATION,
-        .propagate_next = &per_ck,
-        .round_rate = &pll4_round_rate,
-        .set_rate = &pll160_set_rate,
-        .rate = CLK_RATE_208MHZ,
-        .scale_reg = HCLKPLLCTRL_REG,
-        .enable_reg = PWRCTRL_REG,
-        .enable_shift = 2,
-        .parent_switch_reg = SYSCLKCTRL_REG,
-        .set_parent = &set_13MHz_parent,
-};
-/* USB PLL */
-static struct clk ck_pll5 = {
-        .name = "ck_pll5",
-        .parent = &ck_1MHz,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &pll5_round_rate,
-        .set_rate = &pll160_set_rate,
-        .scale_reg = USBCTRL_REG,
-        .enable_reg = USBCTRL_REG,
-        .enable_shift = 18,
-        .enable_reg1 = USBCTRL_REG,
-        .enable_shift1 = 17,
-};
-/* XPERTTeak DSP PLL */
-static struct clk ck_pll3 = {
-        .name = "ck_pll3",
-        .parent = &ck_pll1,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &pll3_round_rate,
-        .set_rate = &pll160_set_rate,
-        .scale_reg = DSPPLLCTRL_REG,
-        .enable_reg = DSPCLKCTRL_REG,
-        .enable_shift = 3,
-        .enable_reg1 = DSPCLKCTRL_REG,
-        .enable_shift1 = 2,
-        .parent_switch_reg = DSPCLKCTRL_REG,
-        .set_parent = &set_13MHz_parent,
-};
-static struct clk hclk_ck = {
-        .name = "hclk_ck",
-        .parent = &ck_pll4,
-        .flags = PARENT_SET_RATE,
-        .set_rate = &hclk_set_rate,
-        .round_rate = &hclk_round_rate,
-        .scale_reg = HCLKDIVCTRL_REG,
-        .rate = 2,
-        .user_rate = 2,
-};
-static struct clk per_ck = {
-        .name = "per_ck",
-        .parent = &ck_pll4,
-        .flags = FIXED_RATE,
-        .propagate_next = &hclk_ck,
-        .set_rate = &per_clk_set_rate,
-        .round_rate = &per_clk_round_rate,
-        .scale_reg = HCLKDIVCTRL_REG,
-        .rate = CLK_RATE_13MHZ,
-        .user_rate = CLK_RATE_13MHZ,
-};
-static struct clk m2hclk_ck = {
-        .name = "m2hclk_ck",
-        .parent = &hclk_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_inv_set_rate,
-        .rate = 1,
-        .enable_shift = 6,
-        .enable_reg = PWRCTRL_REG,
-};
-static struct clk vfp9_ck = {
-        .name = "vfp9_ck",
-        .parent = &ck_pll4,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .rate = 1,
-        .enable_shift = 4,
-        .enable_reg = VFP9CLKCTRL_REG,
-};
-static struct clk keyscan_ck = {
-        .name = "keyscan_ck",
-        .parent = &osc_32KHz,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 0,
-        .enable_reg = KEYCLKCTRL_REG,
-};
-static struct clk touch_ck = {
-        .name = "touch_ck",
-        .parent = &osc_32KHz,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 0,
-        .enable_reg = TSCLKCTRL_REG,
-};
-static struct clk pwm1_ck = {
-        .name = "pwm1_ck",
-        .parent = &osc_32KHz,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 0,
-        .enable_reg = PWMCLKCTRL_REG,
-};
-static struct clk pwm2_ck = {
-        .name = "pwm2_ck",
-        .parent = &osc_32KHz,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 2,
-        .enable_reg = PWMCLKCTRL_REG,
-};
-static struct clk jpeg_ck = {
-        .name = "jpeg_ck",
-        .parent = &hclk_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 0,
-        .enable_reg = JPEGCLKCTRL_REG,
-};
-static struct clk ms_ck = {
-        .name = "ms_ck",
-        .parent = &ck_pll4,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 5,
-        .enable_reg = MSCTRL_REG,
-};
-static struct clk dum_ck = {
-        .name = "dum_ck",
-        .parent = &hclk_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 0,
-        .enable_reg = DUMCLKCTRL_REG,
-};
-static struct clk flash_ck = {
-        .name = "flash_ck",
-        .parent = &hclk_ck,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 1,      /* Only MLC clock supported */
-        .enable_reg = FLASHCLKCTRL_REG,
-};
-static struct clk i2c0_ck = {
-        .name = "i2c0_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION | FIXED_RATE,
-        .enable_shift = 0,
-        .enable_reg = I2CCLKCTRL_REG,
-        .rate = 13000000,
-        .enable = clk_reg_enable,
-        .disable = clk_reg_disable,
-};
-static struct clk i2c1_ck = {
-        .name = "i2c1_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION | FIXED_RATE,
-        .enable_shift = 1,
-        .enable_reg = I2CCLKCTRL_REG,
-        .rate = 13000000,
-        .enable = clk_reg_enable,
-        .disable = clk_reg_disable,
-};
-static struct clk i2c2_ck = {
-        .name = "i2c2_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION | FIXED_RATE,
-        .enable_shift = 2,
-        .enable_reg = USB_OTG_CLKCTRL_REG,
-        .rate = 13000000,
-        .enable = clk_reg_enable,
-        .disable = clk_reg_disable,
-};
-static struct clk spi0_ck = {
-        .name = "spi0_ck",
-        .parent = &hclk_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 0,
-        .enable_reg = SPICTRL_REG,
-};
-static struct clk spi1_ck = {
-        .name = "spi1_ck",
-        .parent = &hclk_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 4,
-        .enable_reg = SPICTRL_REG,
-};
-static struct clk dma_ck = {
-        .name = "dma_ck",
-        .parent = &hclk_ck,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 0,
-        .enable_reg = DMACLKCTRL_REG,
-};
-static struct clk uart3_ck = {
-        .name = "uart3_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .rate = 1,
-        .enable_shift = 0,
-        .enable_reg = UARTCLKCTRL_REG,
-};
-static struct clk uart4_ck = {
-        .name = "uart4_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 1,
-        .enable_reg = UARTCLKCTRL_REG,
-};
-static struct clk uart5_ck = {
-        .name = "uart5_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .rate = 1,
-        .enable_shift = 2,
-        .enable_reg = UARTCLKCTRL_REG,
-};
-static struct clk uart6_ck = {
-        .name = "uart6_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
-        .enable_shift = 3,
-        .enable_reg = UARTCLKCTRL_REG,
-};
-static struct clk wdt_ck = {
-        .name = "wdt_ck",
-        .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .enable_shift = 0,
-        .enable_reg = TIMCLKCTRL_REG,
-        .enable = clk_reg_enable,
-        .disable = clk_reg_disable,
-};
-/* These clocks are visible outside this module
- * and can be initialized
- */
-static struct clk *onchip_clks[] __initdata = {
-        &ck_13MHz,
-        &ck_pll1,
-        &ck_pll4,
-        &ck_pll5,
-        &ck_pll3,
-        &vfp9_ck,
-        &m2hclk_ck,
-        &hclk_ck,
-        &dma_ck,
-        &flash_ck,
-        &dum_ck,
-        &keyscan_ck,
-        &pwm1_ck,
-        &pwm2_ck,
-        &jpeg_ck,
-        &ms_ck,
-        &touch_ck,
-        &i2c0_ck,
-        &i2c1_ck,
-        &i2c2_ck,
-        &spi0_ck,
-        &spi1_ck,
-        &uart3_ck,
-        &uart4_ck,
-        &uart5_ck,
-        &uart6_ck,
-        &wdt_ck,
-};
-static struct clk_lookup onchip_clkreg[] = {
-        { .clk = &ck_13MHz,     .con_id = "ck_13MHz"    },
-        { .clk = &ck_pll1,      .con_id = "ck_pll1"     },
-        { .clk = &ck_pll4,      .con_id = "ck_pll4"     },
-        { .clk = &ck_pll5,      .con_id = "ck_pll5"     },
-        { .clk = &ck_pll3,      .con_id = "ck_pll3"     },
-        { .clk = &vfp9_ck,      .con_id = "vfp9_ck"     },
-        { .clk = &m2hclk_ck,    .con_id = "m2hclk_ck"   },
-        { .clk = &hclk_ck,      .con_id = "hclk_ck"     },
-        { .clk = &dma_ck,       .con_id = "dma_ck"      },
-        { .clk = &flash_ck,     .con_id = "flash_ck"    },
-        { .clk = &dum_ck,       .con_id = "dum_ck"      },
-        { .clk = &keyscan_ck,   .con_id = "keyscan_ck"  },
-        { .clk = &pwm1_ck,      .con_id = "pwm1_ck"     },
-        { .clk = &pwm2_ck,      .con_id = "pwm2_ck"     },
-        { .clk = &jpeg_ck,      .con_id = "jpeg_ck"     },
-        { .clk = &ms_ck,        .con_id = "ms_ck"       },
-        { .clk = &touch_ck,     .con_id = "touch_ck"    },
-        { .clk = &i2c0_ck,      .dev_id = "pnx-i2c.0"   },
-        { .clk = &i2c1_ck,      .dev_id = "pnx-i2c.1"   },
-        { .clk = &i2c2_ck,      .dev_id = "pnx-i2c.2"   },
-        { .clk = &spi0_ck,      .con_id = "spi0_ck"     },
-        { .clk = &spi1_ck,      .con_id = "spi1_ck"     },
-        { .clk = &uart3_ck,     .con_id = "uart3_ck"    },
-        { .clk = &uart4_ck,     .con_id = "uart4_ck"    },
-        { .clk = &uart5_ck,     .con_id = "uart5_ck"    },
-        { .clk = &uart6_ck,     .con_id = "uart6_ck"    },
-        { .clk = &wdt_ck,       .dev_id = "pnx4008-watchdog" },
-};
-static void local_clk_disable(struct clk *clk)
-{
-        if (WARN_ON(clk->usecount == 0))
-                return;
-        if (!(--clk->usecount)) {
-                if (clk->disable)
-                        clk->disable(clk);
-                else if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
-                        clk->set_rate(clk, 0);
-                if (clk->parent)
-                        local_clk_disable(clk->parent);
-        }
-}
-static int local_clk_enable(struct clk *clk)
-{
-        int ret = 0;
-        if (clk->usecount == 0) {
-                if (clk->parent) {
-                        ret = local_clk_enable(clk->parent);
-                        if (ret != 0)
-                                goto out;
-                }
-                if (clk->enable)
-                        ret = clk->enable(clk);
-                else if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
-                            && clk->user_rate)
-                        ret = clk->set_rate(clk, clk->user_rate);
-                if (ret != 0 && clk->parent) {
-                        local_clk_disable(clk->parent);
-                        goto out;
-                }
-                clk->usecount++;
-        }
-out:
-        return ret;
-}
-static int local_set_rate(struct clk *clk, u32 rate)
-{
-        int ret = -EINVAL;
-        if (clk->set_rate) {
-                if (clk->user_rate == clk->rate && clk->parent->rate) {
-                        /* if clock enabled or rate not set */
-                        clk->user_rate = clk->round_rate(clk, rate);
-                        ret = clk->set_rate(clk, clk->user_rate);
-                } else
-                        clk->user_rate = clk->round_rate(clk, rate);
-                ret = 0;
-        }
-        return ret;
-}
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        int ret = -EINVAL;
-        if (clk->flags & FIXED_RATE)
-                goto out;
-        clock_lock();
-        if ((clk->flags & PARENT_SET_RATE) && clk->parent) {
-                clk->user_rate = clk->round_rate(clk, rate);
-                /* parent clock needs to be refreshed
-                   for the setting to take effect */
-        } else {
-                ret = local_set_rate(clk, rate);
-        }
-        ret = 0;
-        clock_unlock();
-out:
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-unsigned long clk_get_rate(struct clk *clk)
-{
-        unsigned long ret;
-        clock_lock();
-        ret = clk->rate;
-        clock_unlock();
-        return ret;
-}
-EXPORT_SYMBOL(clk_get_rate);
-int clk_enable(struct clk *clk)
-{
-        int ret;
-        clock_lock();
-        ret = local_clk_enable(clk);
-        clock_unlock();
-        return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-void clk_disable(struct clk *clk)
-{
-        clock_lock();
-        local_clk_disable(clk);
-        clock_unlock();
-}
-EXPORT_SYMBOL(clk_disable);
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        long ret;
-        clock_lock();
-        if (clk->round_rate)
-                ret = clk->round_rate(clk, rate);
-        else
-                ret = clk->rate;
-        clock_unlock();
-        return ret;
-}
-EXPORT_SYMBOL(clk_round_rate);
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        int ret = -ENODEV;
-        if (!clk->set_parent)
-                goto out;
-        clock_lock();
-        ret = clk->set_parent(clk, parent);
-        if (!ret)
-                clk->parent = parent;
-        clock_unlock();
-out:
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-static int __init clk_init(void)
-{
-        struct clk **clkp;
-        /* Disable autoclocking, as it doesn't seem to work */
-        __raw_writel(0xff, AUTOCLK_CTRL);
-        for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
-             clkp++) {
-                struct clk *clk = *clkp;
-                if (clk->flags & NEEDS_INITIALIZATION) {
-                        if (clk->set_rate) {
-                                clk->user_rate = clk->rate;
-                                local_set_rate(clk, clk->user_rate);
-                                if (clk->set_parent)
-                                        clk->set_parent(clk, clk->parent);
-                        }
-                        if (clk->enable && clk->usecount)
-                                clk->enable(clk);
-                        if (clk->disable && !clk->usecount)
-                                clk->disable(clk);
-                }
-                pr_debug("%s: clock %s, rate %ld\n",
-                        __func__, clk->name, clk->rate);
-        }
-        local_clk_enable(&ck_pll4);
-        /* if ck_13MHz is not used, disable it. */
-        if (ck_13MHz.usecount == 0)
-                local_clk_disable(&ck_13MHz);
-        /* Disable autoclocking */
-        __raw_writeb(0xff, AUTOCLK_CTRL);
-        clkdev_add_table(onchip_clkreg, ARRAY_SIZE(onchip_clkreg));
-        return 0;
-}
-arch_initcall(clk_init);
diff --git a/arch/arm/mach-pnx4008/clock.h b/arch/arm/mach-pnx4008/clock.h
deleted file mode 100644
index 39720d6c0d01..000000000000
--- a/arch/arm/mach-pnx4008/clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/clock.h
- *
- * Clock control driver for PNX4008 - internal header file
- *
- * Author: Vitaly Wool <source@mvista.com>
- *
- * 2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ARCH_ARM_PNX4008_CLOCK_H__
-#define __ARCH_ARM_PNX4008_CLOCK_H__
-struct clk {
-        const char *name;
-        struct clk *parent;
-        struct clk *propagate_next;
-        u32 rate;
-        u32 user_rate;
-        s8 usecount;
-        u32 flags;
-        u32 scale_reg;
-        u8 enable_shift;
-        u32 enable_reg;
-        u8 enable_shift1;
-        u32 enable_reg1;
-        u32 parent_switch_reg;
-        u32(*round_rate) (struct clk *, u32);
-        int (*set_rate) (struct clk *, u32);
-        int (*set_parent) (struct clk * clk, struct clk * parent);
-        int (*enable)(struct clk *);
-        void (*disable)(struct clk *);
-};
-/* Flags */
-#define RATE_PROPAGATES      (1<<0)
-#define NEEDS_INITIALIZATION (1<<1)
-#define PARENT_SET_RATE      (1<<2)
-#define FIXED_RATE           (1<<3)
-#endif
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
deleted file mode 100644
index a00d2f1254ed..000000000000
--- a/arch/arm/mach-pnx4008/core.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/core.c
- *
- * PNX4008 core startup code
- *
- * Authors: Vitaly Wool, Dmitry Chigirev,
- * Grigory Tolstolytkin, Dmitry Pervushin <source@mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/serial_8250.h>
-#include <linux/device.h>
-#include <linux/spi/spi.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/system_misc.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include <mach/irq.h>
-#include <mach/clock.h>
-#include <mach/dma.h>
-struct resource spipnx_0_resources[] = {
-        {
-                .start = PNX4008_SPI1_BASE,
-                .end = PNX4008_SPI1_BASE + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = PER_SPI1_REC_XMIT,
-                .flags = IORESOURCE_DMA,
-        }, {
-                .start = SPI1_INT,
-                .flags = IORESOURCE_IRQ,
-        }, {
-                .flags = 0,
-        },
-};
-struct resource spipnx_1_resources[] = {
-        {
-                .start = PNX4008_SPI2_BASE,
-                .end = PNX4008_SPI2_BASE + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = PER_SPI2_REC_XMIT,
-                .flags = IORESOURCE_DMA,
-        }, {
-                .start = SPI2_INT,
-                .flags = IORESOURCE_IRQ,
-        }, {
-                .flags = 0,
-        }
-};
-static struct spi_board_info spi_board_info[] __initdata = {
-        {
-                .modalias       = "m25p80",
-                .max_speed_hz   = 1000000,
-                .bus_num        = 1,
-                .chip_select    = 0,
-        },
-};
-static struct platform_device spipnx_1 = {
-        .name = "spipnx",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(spipnx_0_resources),
-        .resource = spipnx_0_resources,
-        .dev = {
-                .coherent_dma_mask = 0xFFFFFFFF,
-                },
-};
-static struct platform_device spipnx_2 = {
-        .name = "spipnx",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(spipnx_1_resources),
-        .resource = spipnx_1_resources,
-        .dev = {
-                .coherent_dma_mask = 0xFFFFFFFF,
-                },
-};
-static struct plat_serial8250_port platform_serial_ports[] = {
-        {
-                .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART5_BASE)),
-                .mapbase = (unsigned long)PNX4008_UART5_BASE,
-                .irq = IIR5_INT,
-                .uartclk = PNX4008_UART_CLK,
-                .regshift = 2,
-                .iotype = UPIO_MEM,
-                .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
-        },
-        {
-                .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART3_BASE)),
-                .mapbase = (unsigned long)PNX4008_UART3_BASE,
-                .irq = IIR3_INT,
-                .uartclk = PNX4008_UART_CLK,
-                .regshift = 2,
-                .iotype = UPIO_MEM,
-                .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
-         },
-        {}
-};
-static struct platform_device serial_device = {
-        .name = "serial8250",
-        .id = PLAT8250_DEV_PLATFORM,
-        .dev = {
-                .platform_data = &platform_serial_ports,
-        },
-};
-static struct platform_device nand_flash_device = {
-        .name = "pnx4008-flash",
-        .id = -1,
-        .dev = {
-                .coherent_dma_mask = 0xFFFFFFFF,
-        },
-};
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = ~(u32) 0;
-static struct resource ohci_resources[] = {
-        {
-                .start = IO_ADDRESS(PNX4008_USB_CONFIG_BASE),
-                .end = IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x100),
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = USB_HOST_INT,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device ohci_device = {
-        .name = "pnx4008-usb-ohci",
-        .id = -1,
-        .dev = {
-                .dma_mask = &ohci_dmamask,
-                .coherent_dma_mask = 0xffffffff,
-                },
-        .num_resources = ARRAY_SIZE(ohci_resources),
-        .resource = ohci_resources,
-};
-static struct platform_device sdum_device = {
-        .name = "pnx4008-sdum",
-        .id = 0,
-        .dev = {
-                .coherent_dma_mask = 0xffffffff,
-        },
-};
-static struct platform_device rgbfb_device = {
-        .name = "pnx4008-rgbfb",
-        .id = 0,
-        .dev = {
-                .coherent_dma_mask = 0xffffffff,
-        }
-};
-struct resource watchdog_resources[] = {
-        {
-                .start = PNX4008_WDOG_BASE,
-                .end = PNX4008_WDOG_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-static struct platform_device watchdog_device = {
-        .name = "pnx4008-watchdog",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(watchdog_resources),
-        .resource = watchdog_resources,
-};
-static struct platform_device *devices[] __initdata = {
-        &spipnx_1,
-        &spipnx_2,
-        &serial_device,
-        &ohci_device,
-        &nand_flash_device,
-        &sdum_device,
-        &rgbfb_device,
-        &watchdog_device,
-};
-extern void pnx4008_uart_init(void);
-static void __init pnx4008_init(void)
-{
-        /*disable all START interrupt sources,
-           and clear all START interrupt flags */
-        __raw_writel(0, START_INT_ER_REG(SE_PIN_BASE_INT));
-        __raw_writel(0, START_INT_ER_REG(SE_INT_BASE_INT));
-        __raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
-        __raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-        spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-        /* Switch on the UART clocks */
-        pnx4008_uart_init();
-}
-static struct map_desc pnx4008_io_desc[] __initdata = {
-        {
-                .virtual        = IO_ADDRESS(PNX4008_IRAM_BASE),
-                .pfn            = __phys_to_pfn(PNX4008_IRAM_BASE),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IO_ADDRESS(PNX4008_NDF_FLASH_BASE),
-                .pfn            = __phys_to_pfn(PNX4008_NDF_FLASH_BASE),
-                .length         = SZ_1M - SZ_128K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IO_ADDRESS(PNX4008_JPEG_CONFIG_BASE),
-                .pfn            = __phys_to_pfn(PNX4008_JPEG_CONFIG_BASE),
-                .length         = SZ_128K * 3,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IO_ADDRESS(PNX4008_DMA_CONFIG_BASE),
-                .pfn            = __phys_to_pfn(PNX4008_DMA_CONFIG_BASE),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IO_ADDRESS(PNX4008_AHB2FAB_BASE),
-                .pfn            = __phys_to_pfn(PNX4008_AHB2FAB_BASE),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE,
-        },
-};
-void __init pnx4008_map_io(void)
-{
-        iotable_init(pnx4008_io_desc, ARRAY_SIZE(pnx4008_io_desc));
-}
-static void pnx4008_restart(char mode, const char *cmd)
-{
-        soft_restart(0);
-}
-#ifdef CONFIG_PM
-extern int pnx4008_pm_init(void);
-#else
-static inline int pnx4008_pm_init(void) { return 0; }
-#endif
-void __init pnx4008_init_late(void)
-{
-        pnx4008_pm_init();
-}
-extern struct sys_timer pnx4008_timer;
-MACHINE_START(PNX4008, "Philips PNX4008")
-        /* Maintainer: MontaVista Software Inc. */
-        .atag_offset            = 0x100,
-        .map_io                 = pnx4008_map_io,
-        .init_irq               = pnx4008_init_irq,
-        .init_machine           = pnx4008_init,
-        .init_late              = pnx4008_init_late,
-        .timer                  = &pnx4008_timer,
-        .restart                = pnx4008_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c
deleted file mode 100644
index a4739e9fb2fb..000000000000
--- a/arch/arm/mach-pnx4008/dma.c
+++ /dev/null
@@ -1,1105 +0,0 @@
-/*
- *  linux/arch/arm/mach-pnx4008/dma.c
- *
- *  PNX4008 DMA registration and IRQ dispatching
- *
- *  Author:     Vitaly Wool
- *  Copyright:  MontaVista Software Inc. (c) 2005
- *
- *  Based on the code from Nicolas Pitre
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/gfp.h>
-#include <mach/hardware.h>
-#include <mach/dma.h>
-#include <asm/dma-mapping.h>
-#include <mach/clock.h>
-static struct dma_channel {
-        char *name;
-        void (*irq_handler) (int, int, void *);
-        void *data;
-        struct pnx4008_dma_ll *ll;
-        u32 ll_dma;
-        void *target_addr;
-        int target_id;
-} dma_channels[MAX_DMA_CHANNELS];
-static struct ll_pool {
-        void *vaddr;
-        void *cur;
-        dma_addr_t dma_addr;
-        int count;
-} ll_pool;
-static DEFINE_SPINLOCK(ll_lock);
-struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t * ll_dma)
-{
-        struct pnx4008_dma_ll *ll = NULL;
-        unsigned long flags;
-        spin_lock_irqsave(&ll_lock, flags);
-        if (ll_pool.count > 4) { /* can give one more */
-                ll = *(struct pnx4008_dma_ll **) ll_pool.cur;
-                *ll_dma = ll_pool.dma_addr + ((void *)ll - ll_pool.vaddr);
-                *(void **)ll_pool.cur = **(void ***)ll_pool.cur;
-                memset(ll, 0, sizeof(*ll));
-                ll_pool.count--;
-        }
-        spin_unlock_irqrestore(&ll_lock, flags);
-        return ll;
-}
-EXPORT_SYMBOL_GPL(pnx4008_alloc_ll_entry);
-void pnx4008_free_ll_entry(struct pnx4008_dma_ll * ll, dma_addr_t ll_dma)
-{
-        unsigned long flags;
-        if (ll) {
-                if ((unsigned long)((long)ll - (long)ll_pool.vaddr) > 0x4000) {
-                        printk(KERN_ERR "Trying to free entry not allocated by DMA\n");
-                        BUG();
-                }
-                if (ll->flags & DMA_BUFFER_ALLOCATED)
-                        ll->free(ll->alloc_data);
-                spin_lock_irqsave(&ll_lock, flags);
-                *(long *)ll = *(long *)ll_pool.cur;
-                *(long *)ll_pool.cur = (long)ll;
-                ll_pool.count++;
-                spin_unlock_irqrestore(&ll_lock, flags);
-        }
-}
-EXPORT_SYMBOL_GPL(pnx4008_free_ll_entry);
-void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll * ll)
-{
-        struct pnx4008_dma_ll *ptr;
-        u32 dma;
-        while (ll) {
-                dma = ll->next_dma;
-                ptr = ll->next;
-                pnx4008_free_ll_entry(ll, ll_dma);
-                ll_dma = dma;
-                ll = ptr;
-        }
-}
-EXPORT_SYMBOL_GPL(pnx4008_free_ll);
-static int dma_channels_requested = 0;
-static inline void dma_increment_usage(void)
-{
-        if (!dma_channels_requested++) {
-                struct clk *clk = clk_get(0, "dma_ck");
-                if (!IS_ERR(clk)) {
-                        clk_set_rate(clk, 1);
-                        clk_put(clk);
-                }
-                pnx4008_config_dma(-1, -1, 1);
-        }
-}
-static inline void dma_decrement_usage(void)
-{
-        if (!--dma_channels_requested) {
-                struct clk *clk = clk_get(0, "dma_ck");
-                if (!IS_ERR(clk)) {
-                        clk_set_rate(clk, 0);
-                        clk_put(clk);
-                }
-                pnx4008_config_dma(-1, -1, 0);
-        }
-}
-static DEFINE_SPINLOCK(dma_lock);
-static inline void pnx4008_dma_lock(void)
-{
-        spin_lock_irq(&dma_lock);
-}
-static inline void pnx4008_dma_unlock(void)
-{
-        spin_unlock_irq(&dma_lock);
-}
-#define VALID_CHANNEL(c)        (((c) >= 0) && ((c) < MAX_DMA_CHANNELS))
-int pnx4008_request_channel(char *name, int ch,
-                            void (*irq_handler) (int, int, void *), void *data)
-{
-        int i, found = 0;
-        /* basic sanity checks */
-        if (!name || (ch != -1 && !VALID_CHANNEL(ch)))
-                return -EINVAL;
-        pnx4008_dma_lock();
-        /* try grabbing a DMA channel with the requested priority */
-        for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
-                if (!dma_channels[i].name && (ch == -1 || ch == i)) {
-                        found = 1;
-                        break;
-                }
-        }
-        if (found) {
-                dma_increment_usage();
-                dma_channels[i].name = name;
-                dma_channels[i].irq_handler = irq_handler;
-                dma_channels[i].data = data;
-                dma_channels[i].ll = NULL;
-                dma_channels[i].ll_dma = 0;
-        } else {
-                printk(KERN_WARNING "No more available DMA channels for %s\n",
-                       name);
-                i = -ENODEV;
-        }
-        pnx4008_dma_unlock();
-        return i;
-}
-EXPORT_SYMBOL_GPL(pnx4008_request_channel);
-void pnx4008_free_channel(int ch)
-{
-        if (!dma_channels[ch].name) {
-                printk(KERN_CRIT
-                       "%s: trying to free channel %d which is already freed\n",
-                       __func__, ch);
-                return;
-        }
-        pnx4008_dma_lock();
-        pnx4008_free_ll(dma_channels[ch].ll_dma, dma_channels[ch].ll);
-        dma_channels[ch].ll = NULL;
-        dma_decrement_usage();
-        dma_channels[ch].name = NULL;
-        pnx4008_dma_unlock();
-}
-EXPORT_SYMBOL_GPL(pnx4008_free_channel);
-int pnx4008_config_dma(int ahb_m1_be, int ahb_m2_be, int enable)
-{
-        unsigned long dma_cfg = __raw_readl(DMAC_CONFIG);
-        switch (ahb_m1_be) {
-        case 0:
-                dma_cfg &= ~(1 << 1);
-                break;
-        case 1:
-                dma_cfg |= (1 << 1);
-                break;
-        default:
-                break;
-        }
-        switch (ahb_m2_be) {
-        case 0:
-                dma_cfg &= ~(1 << 2);
-                break;
-        case 1:
-                dma_cfg |= (1 << 2);
-                break;
-        default:
-                break;
-        }
-        switch (enable) {
-        case 0:
-                dma_cfg &= ~(1 << 0);
-                break;
-        case 1:
-                dma_cfg |= (1 << 0);
-                break;
-        default:
-                break;
-        }
-        pnx4008_dma_lock();
-        __raw_writel(dma_cfg, DMAC_CONFIG);
-        pnx4008_dma_unlock();
-        return 0;
-}
-EXPORT_SYMBOL_GPL(pnx4008_config_dma);
-int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl * ch_ctrl,
-                             unsigned long *ctrl)
-{
-        int i = 0, dbsize, sbsize, err = 0;
-        if (!ctrl || !ch_ctrl) {
-                err = -EINVAL;
-                goto out;
-        }
-        *ctrl = 0;
-        switch (ch_ctrl->tc_mask) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 31);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->cacheable) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 30);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->bufferable) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 29);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->priv_mode) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 28);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->di) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 27);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->si) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 26);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->dest_ahb1) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 25);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->src_ahb1) {
-        case 0:
-                break;
-        case 1:
-                *ctrl |= (1 << 24);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->dwidth) {
-        case WIDTH_BYTE:
-                *ctrl &= ~(7 << 21);
-                break;
-        case WIDTH_HWORD:
-                *ctrl &= ~(7 << 21);
-                *ctrl |= (1 << 21);
-                break;
-        case WIDTH_WORD:
-                *ctrl &= ~(7 << 21);
-                *ctrl |= (2 << 21);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_ctrl->swidth) {
-        case WIDTH_BYTE:
-                *ctrl &= ~(7 << 18);
-                break;
-        case WIDTH_HWORD:
-                *ctrl &= ~(7 << 18);
-                *ctrl |= (1 << 18);
-                break;
-        case WIDTH_WORD:
-                *ctrl &= ~(7 << 18);
-                *ctrl |= (2 << 18);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        dbsize = ch_ctrl->dbsize;
-        while (!(dbsize & 1)) {
-                i++;
-                dbsize >>= 1;
-        }
-        if (ch_ctrl->dbsize != 1 || i > 8 || i == 1) {
-                err = -EINVAL;
-                goto out;
-        } else if (i > 1)
-                i--;
-        *ctrl &= ~(7 << 15);
-        *ctrl |= (i << 15);
-        sbsize = ch_ctrl->sbsize;
-        while (!(sbsize & 1)) {
-                i++;
-                sbsize >>= 1;
-        }
-        if (ch_ctrl->sbsize != 1 || i > 8 || i == 1) {
-                err = -EINVAL;
-                goto out;
-        } else if (i > 1)
-                i--;
-        *ctrl &= ~(7 << 12);
-        *ctrl |= (i << 12);
-        if (ch_ctrl->tr_size > 0x7ff) {
-                err = -E2BIG;
-                goto out;
-        }
-        *ctrl &= ~0x7ff;
-        *ctrl |= ch_ctrl->tr_size & 0x7ff;
-out:
-        return err;
-}
-EXPORT_SYMBOL_GPL(pnx4008_dma_pack_control);
-int pnx4008_dma_parse_control(unsigned long ctrl,
-                              struct pnx4008_dma_ch_ctrl * ch_ctrl)
-{
-        int err = 0;
-        if (!ch_ctrl) {
-                err = -EINVAL;
-                goto out;
-        }
-        ch_ctrl->tr_size = ctrl & 0x7ff;
-        ctrl >>= 12;
-        ch_ctrl->sbsize = 1 << (ctrl & 7);
-        if (ch_ctrl->sbsize > 1)
-                ch_ctrl->sbsize <<= 1;
-        ctrl >>= 3;
-        ch_ctrl->dbsize = 1 << (ctrl & 7);
-        if (ch_ctrl->dbsize > 1)
-                ch_ctrl->dbsize <<= 1;
-        ctrl >>= 3;
-        switch (ctrl & 7) {
-        case 0:
-                ch_ctrl->swidth = WIDTH_BYTE;
-                break;
-        case 1:
-                ch_ctrl->swidth = WIDTH_HWORD;
-                break;
-        case 2:
-                ch_ctrl->swidth = WIDTH_WORD;
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        ctrl >>= 3;
-        switch (ctrl & 7) {
-        case 0:
-                ch_ctrl->dwidth = WIDTH_BYTE;
-                break;
-        case 1:
-                ch_ctrl->dwidth = WIDTH_HWORD;
-                break;
-        case 2:
-                ch_ctrl->dwidth = WIDTH_WORD;
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        ctrl >>= 3;
-        ch_ctrl->src_ahb1 = ctrl & 1;
-        ctrl >>= 1;
-        ch_ctrl->dest_ahb1 = ctrl & 1;
-        ctrl >>= 1;
-        ch_ctrl->si = ctrl & 1;
-        ctrl >>= 1;
-        ch_ctrl->di = ctrl & 1;
-        ctrl >>= 1;
-        ch_ctrl->priv_mode = ctrl & 1;
-        ctrl >>= 1;
-        ch_ctrl->bufferable = ctrl & 1;
-        ctrl >>= 1;
-        ch_ctrl->cacheable = ctrl & 1;
-        ctrl >>= 1;
-        ch_ctrl->tc_mask = ctrl & 1;
-out:
-        return err;
-}
-EXPORT_SYMBOL_GPL(pnx4008_dma_parse_control);
-int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config * ch_cfg,
-                            unsigned long *cfg)
-{
-        int err = 0;
-        if (!cfg || !ch_cfg) {
-                err = -EINVAL;
-                goto out;
-        }
-        *cfg = 0;
-        switch (ch_cfg->halt) {
-        case 0:
-                break;
-        case 1:
-                *cfg |= (1 << 18);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_cfg->active) {
-        case 0:
-                break;
-        case 1:
-                *cfg |= (1 << 17);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_cfg->lock) {
-        case 0:
-                break;
-        case 1:
-                *cfg |= (1 << 16);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_cfg->itc) {
-        case 0:
-                break;
-        case 1:
-                *cfg |= (1 << 15);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_cfg->ie) {
-        case 0:
-                break;
-        case 1:
-                *cfg |= (1 << 14);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        switch (ch_cfg->flow_cntrl) {
-        case FC_MEM2MEM_DMA:
-                *cfg &= ~(7 << 11);
-                break;
-        case FC_MEM2PER_DMA:
-                *cfg &= ~(7 << 11);
-                *cfg |= (1 << 11);
-                break;
-        case FC_PER2MEM_DMA:
-                *cfg &= ~(7 << 11);
-                *cfg |= (2 << 11);
-                break;
-        case FC_PER2PER_DMA:
-                *cfg &= ~(7 << 11);
-                *cfg |= (3 << 11);
-                break;
-        case FC_PER2PER_DPER:
-                *cfg &= ~(7 << 11);
-                *cfg |= (4 << 11);
-                break;
-        case FC_MEM2PER_PER:
-                *cfg &= ~(7 << 11);
-                *cfg |= (5 << 11);
-                break;
-        case FC_PER2MEM_PER:
-                *cfg &= ~(7 << 11);
-                *cfg |= (6 << 11);
-                break;
-        case FC_PER2PER_SPER:
-                *cfg |= (7 << 11);
-                break;
-        default:
-                err = -EINVAL;
-                goto out;
-        }
-        *cfg &= ~(0x1f << 6);
-        *cfg |= ((ch_cfg->dest_per & 0x1f) << 6);
-        *cfg &= ~(0x1f << 1);
-        *cfg |= ((ch_cfg->src_per & 0x1f) << 1);
-out:
-        return err;
-}
-EXPORT_SYMBOL_GPL(pnx4008_dma_pack_config);
-int pnx4008_dma_parse_config(unsigned long cfg,
-                             struct pnx4008_dma_ch_config * ch_cfg)
-{
-        int err = 0;
-        if (!ch_cfg) {
-                err = -EINVAL;
-                goto out;
-        }
-        cfg >>= 1;
-        ch_cfg->src_per = cfg & 0x1f;
-        cfg >>= 5;
-        ch_cfg->dest_per = cfg & 0x1f;
-        cfg >>= 5;
-        switch (cfg & 7) {
-        case 0:
-                ch_cfg->flow_cntrl = FC_MEM2MEM_DMA;
-                break;
-        case 1:
-                ch_cfg->flow_cntrl = FC_MEM2PER_DMA;
-                break;
-        case 2:
-                ch_cfg->flow_cntrl = FC_PER2MEM_DMA;
-                break;
-        case 3:
-                ch_cfg->flow_cntrl = FC_PER2PER_DMA;
-                break;
-        case 4:
-                ch_cfg->flow_cntrl = FC_PER2PER_DPER;
-                break;
-        case 5:
-                ch_cfg->flow_cntrl = FC_MEM2PER_PER;
-                break;
-        case 6:
-                ch_cfg->flow_cntrl = FC_PER2MEM_PER;
-                break;
-        case 7:
-                ch_cfg->flow_cntrl = FC_PER2PER_SPER;
-        }
-        cfg >>= 3;
-        ch_cfg->ie = cfg & 1;
-        cfg >>= 1;
-        ch_cfg->itc = cfg & 1;
-        cfg >>= 1;
-        ch_cfg->lock = cfg & 1;
-        cfg >>= 1;
-        ch_cfg->active = cfg & 1;
-        cfg >>= 1;
-        ch_cfg->halt = cfg & 1;
-out:
-        return err;
-}
-EXPORT_SYMBOL_GPL(pnx4008_dma_parse_config);
-void pnx4008_dma_split_head_entry(struct pnx4008_dma_config * config,
-                                  struct pnx4008_dma_ch_ctrl * ctrl)
-{
-        int new_len = ctrl->tr_size, num_entries = 0;
-        int old_len = new_len;
-        int src_width, dest_width, count = 1;
-        switch (ctrl->swidth) {
-        case WIDTH_BYTE:
-                src_width = 1;
-                break;
-        case WIDTH_HWORD:
-                src_width = 2;
-                break;
-        case WIDTH_WORD:
-                src_width = 4;
-                break;
-        default:
-                return;
-        }
-        switch (ctrl->dwidth) {
-        case WIDTH_BYTE:
-                dest_width = 1;
-                break;
-        case WIDTH_HWORD:
-                dest_width = 2;
-                break;
-        case WIDTH_WORD:
-                dest_width = 4;
-                break;
-        default:
-                return;
-        }
-        while (new_len > 0x7FF) {
-                num_entries++;
-                new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
-        }
-        if (num_entries != 0) {
-                struct pnx4008_dma_ll *ll = NULL;
-                config->ch_ctrl &= ~0x7ff;
-                config->ch_ctrl |= new_len;
-                if (!config->is_ll) {
-                        config->is_ll = 1;
-                        while (num_entries) {
-                                if (!ll) {
-                                        config->ll =
-                                            pnx4008_alloc_ll_entry(&config->
-                                                                   ll_dma);
-                                        ll = config->ll;
-                                } else {
-                                        ll->next =
-                                            pnx4008_alloc_ll_entry(&ll->
-                                                                   next_dma);
-                                        ll = ll->next;
-                                }
-                                if (ctrl->si)
-                                        ll->src_addr =
-                                            config->src_addr +
-                                            src_width * new_len * count;
-                                else
-                                        ll->src_addr = config->src_addr;
-                                if (ctrl->di)
-                                        ll->dest_addr =
-                                            config->dest_addr +
-                                            dest_width * new_len * count;
-                                else
-                                        ll->dest_addr = config->dest_addr;
-                                ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
-                                ll->next_dma = 0;
-                                ll->next = NULL;
-                                num_entries--;
-                                count++;
-                        }
-                } else {
-                        struct pnx4008_dma_ll *ll_old = config->ll;
-                        unsigned long ll_dma_old = config->ll_dma;
-                        while (num_entries) {
-                                if (!ll) {
-                                        config->ll =
-                                            pnx4008_alloc_ll_entry(&config->
-                                                                   ll_dma);
-                                        ll = config->ll;
-                                } else {
-                                        ll->next =
-                                            pnx4008_alloc_ll_entry(&ll->
-                                                                   next_dma);
-                                        ll = ll->next;
-                                }
-                                if (ctrl->si)
-                                        ll->src_addr =
-                                            config->src_addr +
-                                            src_width * new_len * count;
-                                else
-                                        ll->src_addr = config->src_addr;
-                                if (ctrl->di)
-                                        ll->dest_addr =
-                                            config->dest_addr +
-                                            dest_width * new_len * count;
-                                else
-                                        ll->dest_addr = config->dest_addr;
-                                ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
-                                ll->next_dma = 0;
-                                ll->next = NULL;
-                                num_entries--;
-                                count++;
-                        }
-                        ll->next_dma = ll_dma_old;
-                        ll->next = ll_old;
-                }
-                /* adjust last length/tc */
-                ll->ch_ctrl = config->ch_ctrl & (~0x7ff);
-                ll->ch_ctrl |= old_len - new_len * (count - 1);
-                config->ch_ctrl &= 0x7fffffff;
-        }
-}
-EXPORT_SYMBOL_GPL(pnx4008_dma_split_head_entry);
-void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll * cur_ll,
-                                struct pnx4008_dma_ch_ctrl * ctrl)
-{
-        int new_len = ctrl->tr_size, num_entries = 0;
-        int old_len = new_len;
-        int src_width, dest_width, count = 1;
-        switch (ctrl->swidth) {
-        case WIDTH_BYTE:
-                src_width = 1;
-                break;
-        case WIDTH_HWORD:
-                src_width = 2;
-                break;
-        case WIDTH_WORD:
-                src_width = 4;
-                break;
-        default:
-                return;
-        }
-        switch (ctrl->dwidth) {
-        case WIDTH_BYTE:
-                dest_width = 1;
-                break;
-        case WIDTH_HWORD:
-                dest_width = 2;
-                break;
-        case WIDTH_WORD:
-                dest_width = 4;
-                break;
-        default:
-                return;
-        }
-        while (new_len > 0x7FF) {
-                num_entries++;
-                new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
-        }
-        if (num_entries != 0) {
-                struct pnx4008_dma_ll *ll = NULL;
-                cur_ll->ch_ctrl &= ~0x7ff;
-                cur_ll->ch_ctrl |= new_len;
-                if (!cur_ll->next) {
-                        while (num_entries) {
-                                if (!ll) {
-                                        cur_ll->next =
-                                            pnx4008_alloc_ll_entry(&cur_ll->
-                                                                   next_dma);
-                                        ll = cur_ll->next;
-                                } else {
-                                        ll->next =
-                                            pnx4008_alloc_ll_entry(&ll->
-                                                                   next_dma);
-                                        ll = ll->next;
-                                }
-                                if (ctrl->si)
-                                        ll->src_addr =
-                                            cur_ll->src_addr +
-                                            src_width * new_len * count;
-                                else
-                                        ll->src_addr = cur_ll->src_addr;
-                                if (ctrl->di)
-                                        ll->dest_addr =
-                                            cur_ll->dest_addr +
-                                            dest_width * new_len * count;
-                                else
-                                        ll->dest_addr = cur_ll->dest_addr;
-                                ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
-                                ll->next_dma = 0;
-                                ll->next = NULL;
-                                num_entries--;
-                                count++;
-                        }
-                } else {
-                        struct pnx4008_dma_ll *ll_old = cur_ll->next;
-                        unsigned long ll_dma_old = cur_ll->next_dma;
-                        while (num_entries) {
-                                if (!ll) {
-                                        cur_ll->next =
-                                            pnx4008_alloc_ll_entry(&cur_ll->
-                                                                   next_dma);
-                                        ll = cur_ll->next;
-                                } else {
-                                        ll->next =
-                                            pnx4008_alloc_ll_entry(&ll->
-                                                                   next_dma);
-                                        ll = ll->next;
-                                }
-                                if (ctrl->si)
-                                        ll->src_addr =
-                                            cur_ll->src_addr +
-                                            src_width * new_len * count;
-                                else
-                                        ll->src_addr = cur_ll->src_addr;
-                                if (ctrl->di)
-                                        ll->dest_addr =
-                                            cur_ll->dest_addr +
-                                            dest_width * new_len * count;
-                                else
-                                        ll->dest_addr = cur_ll->dest_addr;
-                                ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
-                                ll->next_dma = 0;
-                                ll->next = NULL;
-                                num_entries--;
-                                count++;
-                        }
-                        ll->next_dma = ll_dma_old;
-                        ll->next = ll_old;
-                }
-                /* adjust last length/tc */
-                ll->ch_ctrl = cur_ll->ch_ctrl & (~0x7ff);
-                ll->ch_ctrl |= old_len - new_len * (count - 1);
-                cur_ll->ch_ctrl &= 0x7fffffff;
-        }
-}
-EXPORT_SYMBOL_GPL(pnx4008_dma_split_ll_entry);
-int pnx4008_config_channel(int ch, struct pnx4008_dma_config * config)
-{
-        if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-                return -EINVAL;
-        pnx4008_dma_lock();
-        __raw_writel(config->src_addr, DMAC_Cx_SRC_ADDR(ch));
-        __raw_writel(config->dest_addr, DMAC_Cx_DEST_ADDR(ch));
-        if (config->is_ll)
-                __raw_writel(config->ll_dma, DMAC_Cx_LLI(ch));
-        else
-                __raw_writel(0, DMAC_Cx_LLI(ch));
-        __raw_writel(config->ch_ctrl, DMAC_Cx_CONTROL(ch));
-        __raw_writel(config->ch_cfg, DMAC_Cx_CONFIG(ch));
-        pnx4008_dma_unlock();
-        return 0;
-}
-EXPORT_SYMBOL_GPL(pnx4008_config_channel);
-int pnx4008_channel_get_config(int ch, struct pnx4008_dma_config * config)
-{
-        if (!VALID_CHANNEL(ch) || !dma_channels[ch].name || !config)
-                return -EINVAL;
-        pnx4008_dma_lock();
-        config->ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-        config->ch_ctrl = __raw_readl(DMAC_Cx_CONTROL(ch));
-        config->ll_dma = __raw_readl(DMAC_Cx_LLI(ch));
-        config->is_ll = config->ll_dma ? 1 : 0;
-        config->src_addr = __raw_readl(DMAC_Cx_SRC_ADDR(ch));
-        config->dest_addr = __raw_readl(DMAC_Cx_DEST_ADDR(ch));
-        pnx4008_dma_unlock();
-        return 0;
-}
-EXPORT_SYMBOL_GPL(pnx4008_channel_get_config);
-int pnx4008_dma_ch_enable(int ch)
-{
-        unsigned long ch_cfg;
-        if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-                return -EINVAL;
-        pnx4008_dma_lock();
-        ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-        ch_cfg |= 1;
-        __raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
-        pnx4008_dma_unlock();
-        return 0;
-}
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enable);
-int pnx4008_dma_ch_disable(int ch)
-{
-        unsigned long ch_cfg;
-        if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-                return -EINVAL;
-        pnx4008_dma_lock();
-        ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-        ch_cfg &= ~1;
-        __raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
-        pnx4008_dma_unlock();
-        return 0;
-}
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_disable);
-int pnx4008_dma_ch_enabled(int ch)
-{
-        unsigned long ch_cfg;
-        if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-                return -EINVAL;
-        pnx4008_dma_lock();
-        ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-        pnx4008_dma_unlock();
-        return ch_cfg & 1;
-}
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enabled);
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
-        int i;
-        unsigned long dint = __raw_readl(DMAC_INT_STAT);
-        unsigned long tcint = __raw_readl(DMAC_INT_TC_STAT);
-        unsigned long eint = __raw_readl(DMAC_INT_ERR_STAT);
-        unsigned long i_bit;
-        for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
-                i_bit = 1 << i;
-                if (dint & i_bit) {
-                        struct dma_channel *channel = &dma_channels[i];
-                        if (channel->name && channel->irq_handler) {
-                                int cause = 0;
-                                if (eint & i_bit)
-                                        cause |= DMA_ERR_INT;
-                                if (tcint & i_bit)
-                                        cause |= DMA_TC_INT;
-                                channel->irq_handler(i, cause, channel->data);
-                        } else {
-                                /*
-                                 * IRQ for an unregistered DMA channel
-                                 */
-                                printk(KERN_WARNING
-                                       "spurious IRQ for DMA channel %d\n", i);
-                        }
-                        if (tcint & i_bit)
-                                __raw_writel(i_bit, DMAC_INT_TC_CLEAR);
-                        if (eint & i_bit)
-                                __raw_writel(i_bit, DMAC_INT_ERR_CLEAR);
-                }
-        }
-        return IRQ_HANDLED;
-}
-static int __init pnx4008_dma_init(void)
-{
-        int ret, i;
-        ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
-        if (ret) {
-                printk(KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
-                goto out;
-        }
-        ll_pool.count = 0x4000 / sizeof(struct pnx4008_dma_ll);
-        ll_pool.cur = ll_pool.vaddr =
-            dma_alloc_coherent(NULL, ll_pool.count * sizeof(struct pnx4008_dma_ll),
-                               &ll_pool.dma_addr, GFP_KERNEL);
-        if (!ll_pool.vaddr) {
-                ret = -ENOMEM;
-                free_irq(DMA_INT, NULL);
-                goto out;
-        }
-        for (i = 0; i < ll_pool.count - 1; i++) {
-                void **addr = ll_pool.vaddr + i * sizeof(struct pnx4008_dma_ll);
-                *addr = (void *)addr + sizeof(struct pnx4008_dma_ll);
-        }
-        *(long *)(ll_pool.vaddr +
-                  (ll_pool.count - 1) * sizeof(struct pnx4008_dma_ll)) =
-            (long)ll_pool.vaddr;
-        __raw_writel(1, DMAC_CONFIG);
-out:
-        return ret;
-}
-arch_initcall(pnx4008_dma_init);
diff --git a/arch/arm/mach-pnx4008/gpio.c b/arch/arm/mach-pnx4008/gpio.c
deleted file mode 100644
index d3e71d3847b4..000000000000
--- a/arch/arm/mach-pnx4008/gpio.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/gpio.c
- *
- * PNX4008 GPIO driver
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <mach/gpio-pnx4008.h>
-/* register definitions */
-#define PIO_VA_BASE     IO_ADDRESS(PNX4008_PIO_BASE)
-#define PIO_INP_STATE   (0x00U)
-#define PIO_OUTP_SET    (0x04U)
-#define PIO_OUTP_CLR    (0x08U)
-#define PIO_OUTP_STATE  (0x0CU)
-#define PIO_DRV_SET     (0x10U)
-#define PIO_DRV_CLR     (0x14U)
-#define PIO_DRV_STATE   (0x18U)
-#define PIO_SDINP_STATE (0x1CU)
-#define PIO_SDOUTP_SET  (0x20U)
-#define PIO_SDOUTP_CLR  (0x24U)
-#define PIO_MUX_SET     (0x28U)
-#define PIO_MUX_CLR     (0x2CU)
-#define PIO_MUX_STATE   (0x30U)
-static inline void gpio_lock(void)
-{
-        local_irq_disable();
-}
-static inline void gpio_unlock(void)
-{
-        local_irq_enable();
-}
-/* Inline functions */
-static inline int gpio_read_bit(u32 reg, int gpio)
-{
-        u32 bit, val;
-        int ret = -EFAULT;
-        if (gpio < 0)
-                goto out;
-        bit = GPIO_BIT(gpio);
-        if (bit) {
-                val = __raw_readl(PIO_VA_BASE + reg);
-                ret = (val & bit) ? 1 : 0;
-        }
-out:
-        return ret;
-}
-static inline int gpio_set_bit(u32 reg, int gpio)
-{
-        u32 bit, val;
-        int ret = -EFAULT;
-        if (gpio < 0)
-                goto out;
-        bit = GPIO_BIT(gpio);
-        if (bit) {
-                val = __raw_readl(PIO_VA_BASE + reg);
-                val |= bit;
-                __raw_writel(val, PIO_VA_BASE + reg);
-                ret = 0;
-        }
-out:
-        return ret;
-}
-/* Very simple access control, bitmap for allocated/free */
-static unsigned long access_map[4];
-#define INP_INDEX       0
-#define OUTP_INDEX      1
-#define GPIO_INDEX      2
-#define MUX_INDEX       3
-/*GPIO to Input Mapping */
-static short gpio_to_inp_map[32] = {
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, 10, 11, 12, 13, 14, 24, -1
-};
-/*GPIO to Mux Mapping */
-static short gpio_to_mux_map[32] = {
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, -1, -1, 0, 1, 4, 5, -1
-};
-/*Output to Mux Mapping */
-static short outp_to_mux_map[32] = {
-        -1, -1, -1, 6, -1, -1, -1, -1,
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, -1, -1, -1, -1, 2, -1, -1,
-        -1, -1, -1, -1, -1, -1, -1, -1
-};
-int pnx4008_gpio_register_pin(unsigned short pin)
-{
-        unsigned long bit = GPIO_BIT(pin);
-        int ret = -EBUSY;       /* Already in use */
-        gpio_lock();
-        if (GPIO_ISBID(pin)) {
-                if (access_map[GPIO_INDEX] & bit)
-                        goto out;
-                access_map[GPIO_INDEX] |= bit;
-        } else if (GPIO_ISRAM(pin)) {
-                if (access_map[GPIO_INDEX] & bit)
-                        goto out;
-                access_map[GPIO_INDEX] |= bit;
-        } else if (GPIO_ISMUX(pin)) {
-                if (access_map[MUX_INDEX] & bit)
-                        goto out;
-                access_map[MUX_INDEX] |= bit;
-        } else if (GPIO_ISOUT(pin)) {
-                if (access_map[OUTP_INDEX] & bit)
-                        goto out;
-                access_map[OUTP_INDEX] |= bit;
-        } else if (GPIO_ISIN(pin)) {
-                if (access_map[INP_INDEX] & bit)
-                        goto out;
-                access_map[INP_INDEX] |= bit;
-        } else
-                goto out;
-        ret = 0;
-out:
-        gpio_unlock();
-        return ret;
-}
-EXPORT_SYMBOL(pnx4008_gpio_register_pin);
-int pnx4008_gpio_unregister_pin(unsigned short pin)
-{
-        unsigned long bit = GPIO_BIT(pin);
-        int ret = -EFAULT;      /* Not registered */
-        gpio_lock();
-        if (GPIO_ISBID(pin)) {
-                if (~access_map[GPIO_INDEX] & bit)
-                        goto out;
-                access_map[GPIO_INDEX] &= ~bit;
-        } else if (GPIO_ISRAM(pin)) {
-                if (~access_map[GPIO_INDEX] & bit)
-                        goto out;
-                access_map[GPIO_INDEX] &= ~bit;
-        } else if (GPIO_ISMUX(pin)) {
-                if (~access_map[MUX_INDEX] & bit)
-                        goto out;
-                access_map[MUX_INDEX] &= ~bit;
-        } else if (GPIO_ISOUT(pin)) {
-                if (~access_map[OUTP_INDEX] & bit)
-                        goto out;
-                access_map[OUTP_INDEX] &= ~bit;
-        } else if (GPIO_ISIN(pin)) {
-                if (~access_map[INP_INDEX] & bit)
-                        goto out;
-                access_map[INP_INDEX] &= ~bit;
-        } else
-                goto out;
-        ret = 0;
-out:
-        gpio_unlock();
-        return ret;
-}
-EXPORT_SYMBOL(pnx4008_gpio_unregister_pin);
-unsigned long pnx4008_gpio_read_pin(unsigned short pin)
-{
-        unsigned long ret = -EFAULT;
-        int gpio = GPIO_BIT_MASK(pin);
-        gpio_lock();
-        if (GPIO_ISOUT(pin)) {
-                ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
-        } else if (GPIO_ISRAM(pin)) {
-                if (gpio_read_bit(PIO_DRV_STATE, gpio) == 0) {
-                        ret = gpio_read_bit(PIO_SDINP_STATE, gpio);
-                }
-        } else if (GPIO_ISBID(pin)) {
-                ret = gpio_read_bit(PIO_DRV_STATE, gpio);
-                if (ret > 0)
-                        ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
-                else if (ret == 0)
-                        ret =
-                            gpio_read_bit(PIO_INP_STATE, gpio_to_inp_map[gpio]);
-        } else if (GPIO_ISIN(pin)) {
-                ret = gpio_read_bit(PIO_INP_STATE, gpio);
-        }
-        gpio_unlock();
-        return ret;
-}
-EXPORT_SYMBOL(pnx4008_gpio_read_pin);
-/* Write Value to output */
-int pnx4008_gpio_write_pin(unsigned short pin, int output)
-{
-        int gpio = GPIO_BIT_MASK(pin);
-        int ret = -EFAULT;
-        gpio_lock();
-        if (GPIO_ISOUT(pin)) {
-                printk( "writing '%x' to '%x'\n",
-                                gpio, output ? PIO_OUTP_SET : PIO_OUTP_CLR );
-                ret = gpio_set_bit(output ? PIO_OUTP_SET : PIO_OUTP_CLR, gpio);
-        } else if (GPIO_ISRAM(pin)) {
-                if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
-                        ret = gpio_set_bit(output ? PIO_SDOUTP_SET :
-                                           PIO_SDOUTP_CLR, gpio);
-        } else if (GPIO_ISBID(pin)) {
-                if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
-                        ret = gpio_set_bit(output ? PIO_OUTP_SET :
-                                           PIO_OUTP_CLR, gpio);
-        }
-        gpio_unlock();
-        return ret;
-}
-EXPORT_SYMBOL(pnx4008_gpio_write_pin);
-/* Value = 1 : Set GPIO pin as output */
-/* Value = 0 : Set GPIO pin as input */
-int pnx4008_gpio_set_pin_direction(unsigned short pin, int output)
-{
-        int gpio = GPIO_BIT_MASK(pin);
-        int ret = -EFAULT;
-        gpio_lock();
-        if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
-                ret = gpio_set_bit(output ? PIO_DRV_SET : PIO_DRV_CLR, gpio);
-        }
-        gpio_unlock();
-        return ret;
-}
-EXPORT_SYMBOL(pnx4008_gpio_set_pin_direction);
-/* Read GPIO pin direction: 0= pin used as input, 1= pin used as output*/
-int pnx4008_gpio_read_pin_direction(unsigned short pin)
-{
-        int gpio = GPIO_BIT_MASK(pin);
-        int ret = -EFAULT;
-        gpio_lock();
-        if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
-                ret = gpio_read_bit(PIO_DRV_STATE, gpio);
-        }
-        gpio_unlock();
-        return ret;
-}
-EXPORT_SYMBOL(pnx4008_gpio_read_pin_direction);
-/* Value = 1 : Set pin to muxed function  */
-/* Value = 0 : Set pin as GPIO */
-int pnx4008_gpio_set_pin_mux(unsigned short pin, int output)
-{
-        int gpio = GPIO_BIT_MASK(pin);
-        int ret = -EFAULT;
-        gpio_lock();
-        if (GPIO_ISBID(pin)) {
-                ret =
-                    gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
-                                 gpio_to_mux_map[gpio]);
-        } else if (GPIO_ISOUT(pin)) {
-                ret =
-                    gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
-                                 outp_to_mux_map[gpio]);
-        } else if (GPIO_ISMUX(pin)) {
-                ret = gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR, gpio);
-        }
-        gpio_unlock();
-        return ret;
-}
-EXPORT_SYMBOL(pnx4008_gpio_set_pin_mux);
-/* Read pin mux function: 0= pin used as GPIO, 1= pin used for muxed function*/
-int pnx4008_gpio_read_pin_mux(unsigned short pin)
-{
-        int gpio = GPIO_BIT_MASK(pin);
-        int ret = -EFAULT;
-        gpio_lock();
-        if (GPIO_ISBID(pin)) {
-                ret = gpio_read_bit(PIO_MUX_STATE, gpio_to_mux_map[gpio]);
-        } else if (GPIO_ISOUT(pin)) {
-                ret = gpio_read_bit(PIO_MUX_STATE, outp_to_mux_map[gpio]);
-        } else if (GPIO_ISMUX(pin)) {
-                ret = gpio_read_bit(PIO_MUX_STATE, gpio);
-        }
-        gpio_unlock();
-        return ret;
-}
-EXPORT_SYMBOL(pnx4008_gpio_read_pin_mux);
diff --git a/arch/arm/mach-pnx4008/i2c.c b/arch/arm/mach-pnx4008/i2c.c
deleted file mode 100644
index 550cfc2a1f2e..000000000000
--- a/arch/arm/mach-pnx4008/i2c.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * I2C initialization for PNX4008.
- *
- * Author: Vitaly Wool <vitalywool@gmail.com>
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/i2c-pnx.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <mach/platform.h>
-#include <mach/irqs.h>
-static struct resource i2c0_resources[] = {
-        {
-                .start = PNX4008_I2C1_BASE,
-                .end = PNX4008_I2C1_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = I2C_1_INT,
-                .end = I2C_1_INT,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct resource i2c1_resources[] = {
-        {
-                .start = PNX4008_I2C2_BASE,
-                .end = PNX4008_I2C2_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = I2C_2_INT,
-                .end = I2C_2_INT,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct resource i2c2_resources[] = {
-        {
-                .start = PNX4008_USB_CONFIG_BASE + 0x300,
-                .end = PNX4008_USB_CONFIG_BASE + 0x300 + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = USB_I2C_INT,
-                .end = USB_I2C_INT,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device i2c0_device = {
-        .name = "pnx-i2c.0",
-        .id = 0,
-        .resource = i2c0_resources,
-        .num_resources = ARRAY_SIZE(i2c0_resources),
-};
-static struct platform_device i2c1_device = {
-        .name = "pnx-i2c.1",
-        .id = 1,
-        .resource = i2c1_resources,
-        .num_resources = ARRAY_SIZE(i2c1_resources),
-};
-static struct platform_device i2c2_device = {
-        .name = "pnx-i2c.2",
-        .id = 2,
-        .resource = i2c2_resources,
-        .num_resources = ARRAY_SIZE(i2c2_resources),
-};
-static struct platform_device *devices[] __initdata = {
-        &i2c0_device,
-        &i2c1_device,
-        &i2c2_device,
-};
-void __init pnx4008_register_i2c_devices(void)
-{
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-}
diff --git a/arch/arm/mach-pnx4008/include/mach/clock.h b/arch/arm/mach-pnx4008/include/mach/clock.h
deleted file mode 100644
index 8d2a5ef52c90..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/clock.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/clock.h
- *
- * Clock control driver for PNX4008 - header file
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_CLOCK_H__
-#define __PNX4008_CLOCK_H__
-struct module;
-struct clk;
-#define PWRMAN_VA_BASE          IO_ADDRESS(PNX4008_PWRMAN_BASE)
-#define HCLKDIVCTRL_REG         (PWRMAN_VA_BASE + 0x40)
-#define PWRCTRL_REG             (PWRMAN_VA_BASE + 0x44)
-#define PLLCTRL_REG             (PWRMAN_VA_BASE + 0x48)
-#define OSC13CTRL_REG           (PWRMAN_VA_BASE + 0x4c)
-#define SYSCLKCTRL_REG          (PWRMAN_VA_BASE + 0x50)
-#define HCLKPLLCTRL_REG         (PWRMAN_VA_BASE + 0x58)
-#define USBCTRL_REG             (PWRMAN_VA_BASE + 0x64)
-#define SDRAMCLKCTRL_REG        (PWRMAN_VA_BASE + 0x68)
-#define MSCTRL_REG              (PWRMAN_VA_BASE + 0x80)
-#define BTCLKCTRL               (PWRMAN_VA_BASE + 0x84)
-#define DUMCLKCTRL_REG          (PWRMAN_VA_BASE + 0x90)
-#define I2CCLKCTRL_REG          (PWRMAN_VA_BASE + 0xac)
-#define KEYCLKCTRL_REG          (PWRMAN_VA_BASE + 0xb0)
-#define TSCLKCTRL_REG           (PWRMAN_VA_BASE + 0xb4)
-#define PWMCLKCTRL_REG          (PWRMAN_VA_BASE + 0xb8)
-#define TIMCLKCTRL_REG          (PWRMAN_VA_BASE + 0xbc)
-#define SPICTRL_REG             (PWRMAN_VA_BASE + 0xc4)
-#define FLASHCLKCTRL_REG        (PWRMAN_VA_BASE + 0xc8)
-#define UART3CLK_REG            (PWRMAN_VA_BASE + 0xd0)
-#define UARTCLKCTRL_REG         (PWRMAN_VA_BASE + 0xe4)
-#define DMACLKCTRL_REG          (PWRMAN_VA_BASE + 0xe8)
-#define AUTOCLK_CTRL            (PWRMAN_VA_BASE + 0xec)
-#define JPEGCLKCTRL_REG         (PWRMAN_VA_BASE + 0xfc)
-#define AUDIOCONFIG_VA_BASE     IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
-#define DSPPLLCTRL_REG          (AUDIOCONFIG_VA_BASE + 0x60)
-#define DSPCLKCTRL_REG          (AUDIOCONFIG_VA_BASE + 0x64)
-#define AUDIOCLKCTRL_REG        (AUDIOCONFIG_VA_BASE + 0x68)
-#define AUDIOPLLCTRL_REG        (AUDIOCONFIG_VA_BASE + 0x6C)
-#define USB_OTG_CLKCTRL_REG     IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
-#define VFP9CLKCTRL_REG         IO_ADDRESS(PNX4008_DEBUG_BASE)
-#define CLK_RATE_13MHZ 13000
-#define CLK_RATE_1MHZ 1000
-#define CLK_RATE_208MHZ 208000
-#define CLK_RATE_48MHZ 48000
-#define CLK_RATE_32KHZ 32
-#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/debug-macro.S b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
deleted file mode 100644
index 469d60d97f5c..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/debug-macro.S
+++ /dev/null
@@ -1,21 +0,0 @@
-/* arch/arm/mach-pnx4008/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-                .macro  addruart, rp, rv, tmp
-                mov     \rp, #0x00090000
-                add     \rv, \rp, #0xf4000000   @ virtual
-                add     \rp, \rp, #0x40000000   @ physical
-                .endm
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-pnx4008/include/mach/dma.h b/arch/arm/mach-pnx4008/include/mach/dma.h
deleted file mode 100644
index f094bf8bfb18..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/dma.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- *  arch/arm/mach-pnx4008/include/mach/dma.h
- *
- *  PNX4008 DMA header file
- *
- *  Author:     Vitaly Wool
- *  Copyright:  MontaVista Software Inc. (c) 2005
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-#include "platform.h"
-#define MAX_DMA_CHANNELS        8
-#define DMAC_BASE               IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
-#define DMAC_INT_STAT           (DMAC_BASE + 0x0000)
-#define DMAC_INT_TC_STAT        (DMAC_BASE + 0x0004)
-#define DMAC_INT_TC_CLEAR       (DMAC_BASE + 0x0008)
-#define DMAC_INT_ERR_STAT       (DMAC_BASE + 0x000c)
-#define DMAC_INT_ERR_CLEAR      (DMAC_BASE + 0x0010)
-#define DMAC_SOFT_SREQ          (DMAC_BASE + 0x0024)
-#define DMAC_CONFIG             (DMAC_BASE + 0x0030)
-#define DMAC_Cx_SRC_ADDR(c)     (DMAC_BASE + 0x0100 + (c) * 0x20)
-#define DMAC_Cx_DEST_ADDR(c)    (DMAC_BASE + 0x0104 + (c) * 0x20)
-#define DMAC_Cx_LLI(c)          (DMAC_BASE + 0x0108 + (c) * 0x20)
-#define DMAC_Cx_CONTROL(c)      (DMAC_BASE + 0x010c + (c) * 0x20)
-#define DMAC_Cx_CONFIG(c)       (DMAC_BASE + 0x0110 + (c) * 0x20)
-enum {
-        WIDTH_BYTE = 0,
-        WIDTH_HWORD,
-        WIDTH_WORD
-};
-enum {
-        FC_MEM2MEM_DMA,
-        FC_MEM2PER_DMA,
-        FC_PER2MEM_DMA,
-        FC_PER2PER_DMA,
-        FC_PER2PER_DPER,
-        FC_MEM2PER_PER,
-        FC_PER2MEM_PER,
-        FC_PER2PER_SPER
-};
-enum {
-        DMA_INT_UNKNOWN = 0,
-        DMA_ERR_INT = 1,
-        DMA_TC_INT = 2,
-};
-enum {
-        DMA_BUFFER_ALLOCATED = 1,
-        DMA_HAS_LL = 2,
-};
-enum {
-        PER_CAM_DMA_1 = 0,
-        PER_NDF_FLASH = 1,
-        PER_MBX_SLAVE_FIFO = 2,
-        PER_SPI2_REC_XMIT = 3,
-        PER_MS_SD_RX_XMIT = 4,
-        PER_HS_UART_1_XMIT = 5,
-        PER_HS_UART_1_RX = 6,
-        PER_HS_UART_2_XMIT = 7,
-        PER_HS_UART_2_RX = 8,
-        PER_HS_UART_7_XMIT = 9,
-        PER_HS_UART_7_RX = 10,
-        PER_SPI1_REC_XMIT = 11,
-        PER_MLC_NDF_SREC = 12,
-        PER_CAM_DMA_2 = 13,
-        PER_PRNG_INFIFO = 14,
-        PER_PRNG_OUTFIFO = 15,
-};
-struct pnx4008_dma_ch_ctrl {
-        int tc_mask;
-        int cacheable;
-        int bufferable;
-        int priv_mode;
-        int di;
-        int si;
-        int dest_ahb1;
-        int src_ahb1;
-        int dwidth;
-        int swidth;
-        int dbsize;
-        int sbsize;
-        int tr_size;
-};
-struct pnx4008_dma_ch_config {
-        int halt;
-        int active;
-        int lock;
-        int itc;
-        int ie;
-        int flow_cntrl;
-        int dest_per;
-        int src_per;
-};
-struct pnx4008_dma_ll {
-        unsigned long src_addr;
-        unsigned long dest_addr;
-        u32 next_dma;
-        unsigned long ch_ctrl;
-        struct pnx4008_dma_ll *next;
-        int flags;
-        void *alloc_data;
-        int (*free) (void *);
-};
-struct pnx4008_dma_config {
-        int is_ll;
-        unsigned long src_addr;
-        unsigned long dest_addr;
-        unsigned long ch_ctrl;
-        unsigned long ch_cfg;
-        struct pnx4008_dma_ll *ll;
-        u32 ll_dma;
-        int flags;
-        void *alloc_data;
-        int (*free) (void *);
-};
-extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);
-extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);
-extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
-extern int pnx4008_request_channel(char *, int,
-                                   void (*)(int, int, void *),
-                                   void *);
-extern void pnx4008_free_channel(int);
-extern int pnx4008_config_dma(int, int, int);
-extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,
-                                    unsigned long *);
-extern int pnx4008_dma_parse_control(unsigned long,
-                                     struct pnx4008_dma_ch_ctrl *);
-extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,
-                                   unsigned long *);
-extern int pnx4008_dma_parse_config(unsigned long,
-                                    struct pnx4008_dma_ch_config *);
-extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);
-extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);
-extern int pnx4008_dma_ch_enable(int);
-extern int pnx4008_dma_ch_disable(int);
-extern int pnx4008_dma_ch_enabled(int);
-extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,
-                                         struct pnx4008_dma_ch_ctrl *);
-extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,
-                                       struct pnx4008_dma_ch_ctrl *);
-#endif                          /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/entry-macro.S b/arch/arm/mach-pnx4008/include/mach/entry-macro.S
deleted file mode 100644
index 77a555846719..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/entry-macro.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for PNX4008-based platforms
- *
- * 2005-2006 (c) MontaVista Software, Inc.
- * Author: Vitaly Wool <vwool@ru.mvista.com>
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include "platform.h"
-#define IO_BASE         0xF0000000
-#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
-#define INTRC_MASK                      0x00
-#define INTRC_RAW_STAT                  0x04
-#define INTRC_STAT                      0x08
-#define INTRC_POLAR                     0x0C
-#define INTRC_ACT_TYPE                  0x10
-#define INTRC_TYPE                      0x14
-#define SIC1_BASE_INT   32
-#define SIC2_BASE_INT   64
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-/* decode the MIC interrupt numbers */
-                ldr     \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
-                ldr     \irqstat, [\base, #INTRC_STAT]
-                cmp     \irqstat,#1<<16
-                movhs   \irqnr,#16
-                movlo   \irqnr,#0
-                movhs   \irqstat,\irqstat,lsr#16
-                cmp     \irqstat,#1<<8
-                addhs   \irqnr,\irqnr,#8
-                movhs   \irqstat,\irqstat,lsr#8
-                cmp     \irqstat,#1<<4
-                addhs   \irqnr,\irqnr,#4
-                movhs   \irqstat,\irqstat,lsr#4
-                cmp     \irqstat,#1<<2
-                addhs   \irqnr,\irqnr,#2
-                movhs   \irqstat,\irqstat,lsr#2
-                cmp     \irqstat,#1<<1
-                addhs   \irqnr,\irqnr,#1
-/* was there an interrupt ? if not then drop out with EQ status */
-                teq     \irqstat,#0
-                beq     1003f
-/* and now check for extended IRQ reasons */
-                cmp     \irqnr,#1
-                bls     1003f
-                cmp     \irqnr,#30
-                blo     1002f
-/* IRQ 31,30  : High priority cascade IRQ handle */
-/* read the correct SIC */
-/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
-/* set the base IRQ number */
-                ldreq   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-                moveq  \irqnr,#SIC1_BASE_INT
-                ldrne   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-                movne   \irqnr,#SIC2_BASE_INT
-                ldr     \irqstat, [\base, #INTRC_STAT]
-                ldr     \tmp,     [\base, #INTRC_TYPE]
-/* and with inverted mask : low priority interrupts  */
-                and     \irqstat,\irqstat,\tmp
-                b       1004f
-1003:
-/* IRQ 1,0  : Low priority cascade IRQ handle */
-/* read the correct SIC */
-/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
-/* read the correct SIC */
-/* set the base IRQ number  */
-                ldrne   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-                movne   \irqnr,#SIC1_BASE_INT
-                ldreq   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-                moveq   \irqnr,#SIC2_BASE_INT
-                ldr     \irqstat, [\base, #INTRC_STAT]
-                ldr     \tmp,     [\base, #INTRC_TYPE]
-/* and with inverted mask : low priority interrupts  */
-                bic     \irqstat,\irqstat,\tmp
-1004:
-                cmp     \irqstat,#1<<16
-                addhs   \irqnr,\irqnr,#16
-                movhs   \irqstat,\irqstat,lsr#16
-                cmp     \irqstat,#1<<8
-                addhs   \irqnr,\irqnr,#8
-                movhs   \irqstat,\irqstat,lsr#8
-                cmp     \irqstat,#1<<4
-                addhs   \irqnr,\irqnr,#4
-                movhs   \irqstat,\irqstat,lsr#4
-                cmp     \irqstat,#1<<2
-                addhs   \irqnr,\irqnr,#2
-                movhs   \irqstat,\irqstat,lsr#2
-                cmp     \irqstat,#1<<1
-                addhs   \irqnr,\irqnr,#1
-/* is irqstat not zero */
-1002:
-/* we assert that irqstat is not equal to zero and return ne status if true*/
-                teq     \irqstat,#0
-1003:
-                .endm
diff --git a/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h b/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
deleted file mode 100644
index 41027dd7cf74..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
- *
- * PNX4008 GPIO driver - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef _PNX4008_GPIO_H_
-#define _PNX4008_GPIO_H_
-/* Block numbers */
-#define GPIO_IN         (0)
-#define GPIO_OUT                (0x100)
-#define GPIO_BID                (0x200)
-#define GPIO_RAM                (0x300)
-#define GPIO_MUX                (0x400)
-#define GPIO_TYPE_MASK(K) ((K) & 0x700)
-/* INPUT GPIOs */
-/* GPI */
-#define GPI_00          (GPIO_IN | 0)
-#define GPI_01          (GPIO_IN | 1)
-#define GPI_02          (GPIO_IN | 2)
-#define GPI_03          (GPIO_IN | 3)
-#define GPI_04          (GPIO_IN | 4)
-#define GPI_05          (GPIO_IN | 5)
-#define GPI_06          (GPIO_IN | 6)
-#define GPI_07          (GPIO_IN | 7)
-#define GPI_08          (GPIO_IN | 8)
-#define GPI_09          (GPIO_IN | 9)
-#define U1_RX           (GPIO_IN | 15)
-#define U2_HTCS         (GPIO_IN | 16)
-#define U2_RX           (GPIO_IN | 17)
-#define U3_RX           (GPIO_IN | 18)
-#define U4_RX           (GPIO_IN | 19)
-#define U5_RX           (GPIO_IN | 20)
-#define U6_IRRX         (GPIO_IN | 21)
-#define U7_HCTS         (GPIO_IN | 22)
-#define U7_RX           (GPIO_IN | 23)
-/* MISC IN */
-#define SPI1_DATIN      (GPIO_IN | 25)
-#define DISP_SYNC       (GPIO_IN | 26)
-#define SPI2_DATIN      (GPIO_IN | 27)
-#define GPI_11          (GPIO_IN | 28)
-#define GPIO_IN_MASK   0x1eff83ff
-/* OUTPUT GPIOs */
-/* GPO */
-#define GPO_00          (GPIO_OUT | 0)
-#define GPO_01          (GPIO_OUT | 1)
-#define GPO_02          (GPIO_OUT | 2)
-#define GPO_03          (GPIO_OUT | 3)
-#define GPO_04          (GPIO_OUT | 4)
-#define GPO_05          (GPIO_OUT | 5)
-#define GPO_06          (GPIO_OUT | 6)
-#define GPO_07          (GPIO_OUT | 7)
-#define GPO_08          (GPIO_OUT | 8)
-#define GPO_09          (GPIO_OUT | 9)
-#define GPO_10          (GPIO_OUT | 10)
-#define GPO_11          (GPIO_OUT | 11)
-#define GPO_12          (GPIO_OUT | 12)
-#define GPO_13          (GPIO_OUT | 13)
-#define GPO_14          (GPIO_OUT | 14)
-#define GPO_15          (GPIO_OUT | 15)
-#define GPO_16          (GPIO_OUT | 16)
-#define GPO_17          (GPIO_OUT | 17)
-#define GPO_18          (GPIO_OUT | 18)
-#define GPO_19          (GPIO_OUT | 19)
-#define GPO_20          (GPIO_OUT | 20)
-#define GPO_21          (GPIO_OUT | 21)
-#define GPO_22          (GPIO_OUT | 22)
-#define GPO_23          (GPIO_OUT | 23)
-#define GPIO_OUT_MASK   0xffffff
-/* BIDIRECTIONAL GPIOs */
-/* RAM pins */
-#define RAM_D19         (GPIO_RAM | 0)
-#define RAM_D20         (GPIO_RAM | 1)
-#define RAM_D21         (GPIO_RAM | 2)
-#define RAM_D22         (GPIO_RAM | 3)
-#define RAM_D23         (GPIO_RAM | 4)
-#define RAM_D24         (GPIO_RAM | 5)
-#define RAM_D25         (GPIO_RAM | 6)
-#define RAM_D26         (GPIO_RAM | 7)
-#define RAM_D27         (GPIO_RAM | 8)
-#define RAM_D28         (GPIO_RAM | 9)
-#define RAM_D29         (GPIO_RAM | 10)
-#define RAM_D30         (GPIO_RAM | 11)
-#define RAM_D31         (GPIO_RAM | 12)
-#define GPIO_RAM_MASK   0x1fff
-/* I/O pins */
-#define GPIO_00         (GPIO_BID | 25)
-#define GPIO_01         (GPIO_BID | 26)
-#define GPIO_02         (GPIO_BID | 27)
-#define GPIO_03         (GPIO_BID | 28)
-#define GPIO_04         (GPIO_BID | 29)
-#define GPIO_05         (GPIO_BID | 30)
-#define GPIO_BID_MASK   0x7e000000
-/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */
-#define GPIO_SDRAM_SEL  (GPIO_MUX | 3)
-#define GPIO_MUX_MASK   0x8
-/* Extraction/assembly macros */
-#define GPIO_BIT_MASK(K) ((K) & 0x1F)
-#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))
-#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))
-#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))
-#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))
-#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))
-#define GPIO_ISIN(K)  ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))
-/* Start Enable Pin Interrupts - table 58 page 66 */
-#define SE_PIN_BASE_INT   32
-#define SE_U7_RX_INT            63
-#define SE_U7_HCTS_INT          62
-#define SE_BT_CLKREQ_INT        61
-#define SE_U6_IRRX_INT          60
-/*59 unused*/
-#define SE_U5_RX_INT            58
-#define SE_GPI_11_INT           57
-#define SE_U3_RX_INT            56
-#define SE_U2_HCTS_INT          55
-#define SE_U2_RX_INT            54
-#define SE_U1_RX_INT            53
-#define SE_DISP_SYNC_INT        52
-/*51 unused*/
-#define SE_SDIO_INT_N           50
-#define SE_MSDIO_START_INT      49
-#define SE_GPI_06_INT           48
-#define SE_GPI_05_INT           47
-#define SE_GPI_04_INT           46
-#define SE_GPI_03_INT           45
-#define SE_GPI_02_INT           44
-#define SE_GPI_01_INT           43
-#define SE_GPI_00_INT           42
-#define SE_SYSCLKEN_PIN_INT     41
-#define SE_SPI1_DATAIN_INT      40
-#define SE_GPI_07_INT           39
-#define SE_SPI2_DATAIN_INT      38
-#define SE_GPI_10_INT           37
-#define SE_GPI_09_INT           36
-#define SE_GPI_08_INT           35
-/*34-32 unused*/
-/* Start Enable Internal Interrupts - table 57 page 65 */
-#define SE_INT_BASE_INT   0
-#define SE_TS_IRQ               31
-#define SE_TS_P_INT             30
-#define SE_TS_AUX_INT           29
-/*27-28 unused*/
-#define SE_USB_AHB_NEED_CLK_INT 26
-#define SE_MSTIMER_INT          25
-#define SE_RTC_INT              24
-#define SE_USB_NEED_CLK_INT     23
-#define SE_USB_INT              22
-#define SE_USB_I2C_INT          21
-#define SE_USB_OTG_TIMER_INT    20
-#define SE_USB_OTG_ATX_INT_N    19
-/*18 unused*/
-#define SE_DSP_GPIO4_INT        17
-#define SE_KEY_IRQ              16
-#define SE_DSP_SLAVEPORT_INT    15
-#define SE_DSP_GPIO1_INT        14
-#define SE_DSP_GPIO0_INT        13
-#define SE_DSP_AHB_INT          12
-/*11-6 unused*/
-#define SE_GPIO_05_INT          5
-#define SE_GPIO_04_INT          4
-#define SE_GPIO_03_INT          3
-#define SE_GPIO_02_INT          2
-#define SE_GPIO_01_INT          1
-#define SE_GPIO_00_INT          0
-#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
-#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
-extern int pnx4008_gpio_register_pin(unsigned short pin);
-extern int pnx4008_gpio_unregister_pin(unsigned short pin);
-extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
-extern int pnx4008_gpio_write_pin(unsigned short pin, int output);
-extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);
-extern int pnx4008_gpio_read_pin_direction(unsigned short pin);
-extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);
-extern int pnx4008_gpio_read_pin_mux(unsigned short pin);
-static inline void start_int_umask(u8 irq)
-{
-        __raw_writel(__raw_readl(START_INT_ER_REG(irq)) |
-                     START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
-}
-static inline void start_int_mask(u8 irq)
-{
-        __raw_writel(__raw_readl(START_INT_ER_REG(irq)) &
-                     ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
-}
-static inline void start_int_ack(u8 irq)
-{
-        __raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));
-}
-static inline void start_int_set_falling_edge(u8 irq)
-{
-        __raw_writel(__raw_readl(START_INT_APR_REG(irq)) &
-                     ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
-}
-static inline void start_int_set_rising_edge(u8 irq)
-{
-        __raw_writel(__raw_readl(START_INT_APR_REG(irq)) |
-                     START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
-}
-#endif                          /* _PNX4008_GPIO_H_ */
diff --git a/arch/arm/mach-pnx4008/include/mach/hardware.h b/arch/arm/mach-pnx4008/include/mach/hardware.h
deleted file mode 100644
index 7b98b828d368..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/hardware.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/hardware.h
- *
- * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-#include <asm/sizes.h>
-#include <mach/platform.h>
-/* Start of virtual addresses for IO devices */
-#define IO_BASE         0xF0000000
-/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */
-#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/irq.h b/arch/arm/mach-pnx4008/include/mach/irq.h
deleted file mode 100644
index 2a690ca33870..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/irq.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/irq.h
- *
- * PNX4008 IRQ controller driver - header file
- * this one is used in entry-arnv.S as well so it cannot contain C code
- *
- * Copyright (c) 2005 Philips Semiconductors
- * Copyright (c) 2005 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef __PNX4008_IRQ_H__
-#define __PNX4008_IRQ_H__
-#define MIC_VA_BASE             IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
-#define SIC1_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-#define SIC2_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-/* Manual: Chapter 20, page 195 */
-#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
-#define INTC_ER(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
-#define INTC_RSR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
-#define INTC_SR(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
-#define INTC_APR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
-#define INTC_ATR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
-#define INTC_ITR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
-#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
-#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
-extern void __init pnx4008_init_irq(void);
-#endif /* __PNX4008_IRQ_H__ */
diff --git a/arch/arm/mach-pnx4008/include/mach/irqs.h b/arch/arm/mach-pnx4008/include/mach/irqs.h
deleted file mode 100644
index f6b33cf23ae2..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/irqs.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/irqs.h
- *
- * PNX4008 IRQ controller driver - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_IRQS_h__
-#define __PNX4008_IRQS_h__
-#define NR_IRQS         96
-/*Manual: table 259, page 199*/
-/*SUB2 Interrupt Routing (SIC2)*/
-#define SIC2_BASE_INT   64
-#define CLK_SWITCH_ARM_INT 95   /*manual: Clkswitch ARM  */
-#define CLK_SWITCH_DSP_INT 94   /*manual: ClkSwitch DSP  */
-#define CLK_SWITCH_AUD_INT 93   /*manual: Clkswitch AUD  */
-#define GPI_06_INT         92
-#define GPI_05_INT         91
-#define GPI_04_INT         90
-#define GPI_03_INT         89
-#define GPI_02_INT         88
-#define GPI_01_INT         87
-#define GPI_00_INT         86
-#define BT_CLKREQ_INT      85
-#define SPI1_DATIN_INT     84
-#define U5_RX_INT          83
-#define SDIO_INT_N         82
-#define CAM_HS_INT         81
-#define CAM_VS_INT         80
-#define GPI_07_INT         79
-#define DISP_SYNC_INT      78
-#define DSP_INT8           77
-#define U7_HCTS_INT        76
-#define GPI_10_INT         75
-#define GPI_09_INT         74
-#define GPI_08_INT         73
-#define DSP_INT7           72
-#define U2_HCTS_INT        71
-#define SPI2_DATIN_INT     70
-#define GPIO_05_INT        69
-#define GPIO_04_INT        68
-#define GPIO_03_INT        67
-#define GPIO_02_INT        66
-#define GPIO_01_INT        65
-#define GPIO_00_INT        64
-/*Manual: table 258, page 198*/
-/*SUB1 Interrupt Routing (SIC1)*/
-#define SIC1_BASE_INT   32
-#define USB_I2C_INT        63
-#define USB_DEV_HP_INT     62
-#define USB_DEV_LP_INT     61
-#define USB_DEV_DMA_INT    60
-#define USB_HOST_INT       59
-#define USB_OTG_ATX_INT_N  58
-#define USB_OTG_TIMER_INT  57
-#define SW_INT             56
-#define SPI1_INT           55
-#define KEY_IRQ            54
-#define DSP_M_INT          53
-#define RTC_INT            52
-#define I2C_1_INT          51
-#define I2C_2_INT          50
-#define PLL1_LOCK_INT      49
-#define PLL2_LOCK_INT      48
-#define PLL3_LOCK_INT      47
-#define PLL4_LOCK_INT      46
-#define PLL5_LOCK_INT      45
-#define SPI2_INT           44
-#define DSP_INT1           43
-#define DSP_INT2           42
-#define DSP_TDM_INT2       41
-#define TS_AUX_INT         40
-#define TS_IRQ             39
-#define TS_P_INT           38
-#define UOUT1_TO_PAD_INT   37
-#define GPI_11_INT         36
-#define DSP_INT4           35
-#define JTAG_COMM_RX_INT   34
-#define JTAG_COMM_TX_INT   33
-#define DSP_INT3           32
-/*Manual: table 257, page 197*/
-/*MAIN Interrupt Routing*/
-#define MAIN_BASE_INT   0
-#define SUB2_FIQ_N         31   /*active low */
-#define SUB1_FIQ_N         30   /*active low */
-#define JPEG_INT           29
-#define DMA_INT            28
-#define MSTIMER_INT        27
-#define IIR1_INT           26
-#define IIR2_INT           25
-#define IIR7_INT           24
-#define DSP_TDM_INT0       23
-#define DSP_TDM_INT1       22
-#define DSP_P_INT          21
-#define DSP_INT0           20
-#define DUM_INT            19
-#define UOUT0_TO_PAD_INT   18
-#define MP4_ENC_INT        17
-#define MP4_DEC_INT        16
-#define SD0_INT            15
-#define MBX_INT            14
-#define SD1_INT            13
-#define MS_INT_N           12
-#define FLASH_INT          11 /*NAND*/
-#define IIR6_INT           10
-#define IIR5_INT           9
-#define IIR4_INT           8
-#define IIR3_INT           7
-#define WATCH_INT          6
-#define HSTIMER_INT        5
-#define ARCH_TIMER_IRQ     HSTIMER_INT
-#define CAM_INT            4
-#define PRNG_INT           3
-#define CRYPTO_INT         2
-#define SUB2_IRQ_N         1    /*active low */
-#define SUB1_IRQ_N         0    /*active low */
-#define PNX4008_IRQ_TYPES \
-{                                           /*IRQ #'s: */         \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /*  0, 1, 2, 3 */     \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  4, 5, 6, 7 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  8, 9,10,11 */     \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 28,29,30,31 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */  \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 48,49,50,51 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */     \
-}
-/* Start Enable Pin Interrupts - table 58 page 66 */
-#define SE_PIN_BASE_INT   32
-#define SE_U7_RX_INT            63
-#define SE_U7_HCTS_INT          62
-#define SE_BT_CLKREQ_INT        61
-#define SE_U6_IRRX_INT          60
-/*59 unused*/
-#define SE_U5_RX_INT            58
-#define SE_GPI_11_INT           57
-#define SE_U3_RX_INT            56
-#define SE_U2_HCTS_INT          55
-#define SE_U2_RX_INT            54
-#define SE_U1_RX_INT            53
-#define SE_DISP_SYNC_INT        52
-/*51 unused*/
-#define SE_SDIO_INT_N           50
-#define SE_MSDIO_START_INT      49
-#define SE_GPI_06_INT           48
-#define SE_GPI_05_INT           47
-#define SE_GPI_04_INT           46
-#define SE_GPI_03_INT           45
-#define SE_GPI_02_INT           44
-#define SE_GPI_01_INT           43
-#define SE_GPI_00_INT           42
-#define SE_SYSCLKEN_PIN_INT     41
-#define SE_SPI1_DATAIN_INT      40
-#define SE_GPI_07_INT           39
-#define SE_SPI2_DATAIN_INT      38
-#define SE_GPI_10_INT           37
-#define SE_GPI_09_INT           36
-#define SE_GPI_08_INT           35
-/*34-32 unused*/
-/* Start Enable Internal Interrupts - table 57 page 65 */
-#define SE_INT_BASE_INT   0
-#define SE_TS_IRQ               31
-#define SE_TS_P_INT             30
-#define SE_TS_AUX_INT           29
-/*27-28 unused*/
-#define SE_USB_AHB_NEED_CLK_INT 26
-#define SE_MSTIMER_INT          25
-#define SE_RTC_INT              24
-#define SE_USB_NEED_CLK_INT     23
-#define SE_USB_INT              22
-#define SE_USB_I2C_INT          21
-#define SE_USB_OTG_TIMER_INT    20
-#endif /* __PNX4008_IRQS_h__ */
diff --git a/arch/arm/mach-pnx4008/include/mach/platform.h b/arch/arm/mach-pnx4008/include/mach/platform.h
deleted file mode 100644
index 368c2c10a308..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/platform.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/platform.h
- *
- * PNX4008 Base addresses - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_PLATFORM_H__
-#define __ASM_ARCH_PLATFORM_H__
-#define PNX4008_IRAM_BASE               0x08000000
-#define PNX4008_IRAM_SIZE               0x00010000
-#define PNX4008_YUV_SLAVE_BASE          0x10000000
-#define PNX4008_DUM_SLAVE_BASE          0x18000000
-#define PNX4008_NDF_FLASH_BASE          0x20020000
-#define PNX4008_SPI1_BASE               0x20088000
-#define PNX4008_SPI2_BASE               0x20090000
-#define PNX4008_SD_CONFIG_BASE          0x20098000
-#define PNX4008_FLASH_DATA              0x200B0000
-#define PNX4008_MLC_FLASH_BASE          0x200B8000
-#define PNX4008_JPEG_CONFIG_BASE        0x300A0000
-#define PNX4008_DMA_CONFIG_BASE         0x31000000
-#define PNX4008_USB_CONFIG_BASE         0x31020000
-#define PNX4008_SDRAM_CFG_BASE          0x31080000
-#define PNX4008_AHB2FAB_BASE            0x40000000
-#define PNX4008_PWRMAN_BASE             0x40004000
-#define PNX4008_INTCTRLMIC_BASE         0x40008000
-#define PNX4008_INTCTRLSIC1_BASE        0x4000C000
-#define PNX4008_INTCTRLSIC2_BASE        0x40010000
-#define PNX4008_HSUART1_BASE            0x40014000
-#define PNX4008_HSUART2_BASE            0x40018000
-#define PNX4008_HSUART7_BASE            0x4001C000
-#define PNX4008_RTC_BASE                0x40024000
-#define PNX4008_PIO_BASE                0x40028000
-#define PNX4008_MSTIMER_BASE            0x40034000
-#define PNX4008_HSTIMER_BASE            0x40038000
-#define PNX4008_WDOG_BASE               0x4003C000
-#define PNX4008_DEBUG_BASE              0x40040000
-#define PNX4008_TOUCH1_BASE             0x40048000
-#define PNX4008_KEYSCAN_BASE            0x40050000
-#define PNX4008_UARTCTRL_BASE           0x40054000
-#define PNX4008_PWM_BASE                0x4005C000
-#define PNX4008_UART3_BASE              0x40080000
-#define PNX4008_UART4_BASE              0x40088000
-#define PNX4008_UART5_BASE              0x40090000
-#define PNX4008_UART6_BASE              0x40098000
-#define PNX4008_I2C1_BASE               0x400A0000
-#define PNX4008_I2C2_BASE               0x400A8000
-#define PNX4008_MAGICGATE_BASE          0x400B0000
-#define PNX4008_DUMCONF_BASE            0x400B8000
-#define PNX4008_DUM_MAINCFG_BASE        0x400BC000
-#define PNX4008_DSP_BASE                0x400C0000
-#define PNX4008_PROFCOUNTER_BASE        0x400C8000
-#define PNX4008_CRYPTO_BASE             0x400D0000
-#define PNX4008_CAMIFCONF_BASE          0x400D8000
-#define PNX4008_YUV2RGB_BASE            0x400E0000
-#define PNX4008_AUDIOCONFIG_BASE        0x400E8000
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/pm.h b/arch/arm/mach-pnx4008/include/mach/pm.h
deleted file mode 100644
index 2fa685bff858..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/pm.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/pm.h
- *
- * PNX4008 Power Management Routiness - header file
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_PNX4008_PM_H
-#define __ASM_ARCH_PNX4008_PM_H
-#ifndef __ASSEMBLER__
-#include "irq.h"
-#include "irqs.h"
-#include "clock.h"
-extern void pnx4008_pm_idle(void);
-extern void pnx4008_pm_suspend(void);
-extern unsigned int pnx4008_cpu_suspend_sz;
-extern void pnx4008_cpu_suspend(void);
-extern unsigned int pnx4008_cpu_standby_sz;
-extern void pnx4008_cpu_standby(void);
-extern int pnx4008_startup_pll(struct clk *);
-extern int pnx4008_shutdown_pll(struct clk *);
-#endif                          /* ASSEMBLER */
-#endif                          /* __ASM_ARCH_PNX4008_PM_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/timex.h b/arch/arm/mach-pnx4008/include/mach/timex.h
deleted file mode 100644
index b383c7de7ab4..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/timex.h
- *
- * PNX4008 timers header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_TIMEX_H
-#define __PNX4008_TIMEX_H
-#define CLOCK_TICK_RATE         1000000
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/uncompress.h b/arch/arm/mach-pnx4008/include/mach/uncompress.h
deleted file mode 100644
index bb4751ee2539..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/uncompress.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *  arch/arm/mach-pnx4008/include/mach/uncompress.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2006 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define UART5_BASE 0x40090000
-#define UART5_DR    (*(volatile unsigned char *) (UART5_BASE))
-#define UART5_FR    (*(volatile unsigned char *) (UART5_BASE + 18))
-static __inline__ void putc(char c)
-{
-        while (UART5_FR & (1 << 5))
-                barrier();
-        UART5_DR = c;
-}
-/*
- * This does not append a newline
- */
-static inline void flush(void)
-{
-}
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
deleted file mode 100644
index 41e4201972d5..000000000000
--- a/arch/arm/mach-pnx4008/irq.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/irq.c
- *
- * PNX4008 IRQ controller driver
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-#include <mach/irq.h>
-static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
-static void pnx4008_mask_irq(struct irq_data *d)
-{
-        __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq));        /* mask interrupt */
-}
-static void pnx4008_unmask_irq(struct irq_data *d)
-{
-        __raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq)); /* unmask interrupt */
-}
-static void pnx4008_mask_ack_irq(struct irq_data *d)
-{
-        __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq));        /* mask interrupt */
-        __raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq));        /* clear interrupt status */
-}
-static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
-{
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq));       /*edge sensitive */
-                __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq));       /*rising edge */
-                irq_set_handler(d->irq, handle_edge_irq);
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq));       /*edge sensitive */
-                __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq));      /*falling edge */
-                irq_set_handler(d->irq, handle_edge_irq);
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq));      /*level sensitive */
-                __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq));      /*low level */
-                irq_set_handler(d->irq, handle_level_irq);
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq));      /*level sensitive */
-                __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq));       /* high level */
-                irq_set_handler(d->irq, handle_level_irq);
-                break;
-        /* IRQ_TYPE_EDGE_BOTH is not supported */
-        default:
-                printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
-                return -1;
-        }
-        return 0;
-}
-static struct irq_chip pnx4008_irq_chip = {
-        .irq_ack = pnx4008_mask_ack_irq,
-        .irq_mask = pnx4008_mask_irq,
-        .irq_unmask = pnx4008_unmask_irq,
-        .irq_set_type = pnx4008_set_irq_type,
-};
-void __init pnx4008_init_irq(void)
-{
-        unsigned int i;
-        /* configure IRQ's */
-        for (i = 0; i < NR_IRQS; i++) {
-                set_irq_flags(i, IRQF_VALID);
-                irq_set_chip(i, &pnx4008_irq_chip);
-                pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
-        }
-        /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
-        pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N),
-                             pnx4008_irq_type[SUB1_IRQ_N]);
-        pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N),
-                             pnx4008_irq_type[SUB2_IRQ_N]);
-        pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N),
-                             pnx4008_irq_type[SUB1_FIQ_N]);
-        pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N),
-                             pnx4008_irq_type[SUB2_FIQ_N]);
-        /* mask all others */
-        __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
-                        (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
-                INTC_ER(MAIN_BASE_INT));
-        __raw_writel(0, INTC_ER(SIC1_BASE_INT));
-        __raw_writel(0, INTC_ER(SIC2_BASE_INT));
-}
diff --git a/arch/arm/mach-pnx4008/pm.c b/arch/arm/mach-pnx4008/pm.c
deleted file mode 100644
index 26f8d06b142a..000000000000
--- a/arch/arm/mach-pnx4008/pm.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/pm.c
- *
- * Power Management driver for PNX4008
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/pm.h>
-#include <linux/rtc.h>
-#include <linux/sched.h>
-#include <linux/proc_fs.h>
-#include <linux/suspend.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <asm/cacheflush.h>
-#include <mach/hardware.h>
-#include <mach/pm.h>
-#include <mach/clock.h>
-#define SRAM_VA IO_ADDRESS(PNX4008_IRAM_BASE)
-static void *saved_sram;
-static struct clk *pll4_clk;
-static inline void pnx4008_standby(void)
-{
-        void (*pnx4008_cpu_standby_ptr) (void);
-        local_irq_disable();
-        local_fiq_disable();
-        clk_disable(pll4_clk);
-        /*saving portion of SRAM to be used by suspend function. */
-        memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_standby_sz);
-        /*make sure SRAM copy gets physically written into SDRAM.
-           SDRAM will be placed into self-refresh during power down */
-        flush_cache_all();
-        /*copy suspend function into SRAM */
-        memcpy((void *)SRAM_VA, pnx4008_cpu_standby, pnx4008_cpu_standby_sz);
-        /*do suspend */
-        pnx4008_cpu_standby_ptr = (void *)SRAM_VA;
-        pnx4008_cpu_standby_ptr();
-        /*restoring portion of SRAM that was used by suspend function */
-        memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_standby_sz);
-        clk_enable(pll4_clk);
-        local_fiq_enable();
-        local_irq_enable();
-}
-static inline void pnx4008_suspend(void)
-{
-        void (*pnx4008_cpu_suspend_ptr) (void);
-        local_irq_disable();
-        local_fiq_disable();
-        clk_disable(pll4_clk);
-        __raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
-        __raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
-        /*saving portion of SRAM to be used by suspend function. */
-        memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_suspend_sz);
-        /*make sure SRAM copy gets physically written into SDRAM.
-           SDRAM will be placed into self-refresh during power down */
-        flush_cache_all();
-        /*copy suspend function into SRAM */
-        memcpy((void *)SRAM_VA, pnx4008_cpu_suspend, pnx4008_cpu_suspend_sz);
-        /*do suspend */
-        pnx4008_cpu_suspend_ptr = (void *)SRAM_VA;
-        pnx4008_cpu_suspend_ptr();
-        /*restoring portion of SRAM that was used by suspend function */
-        memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_suspend_sz);
-        clk_enable(pll4_clk);
-        local_fiq_enable();
-        local_irq_enable();
-}
-static int pnx4008_pm_enter(suspend_state_t state)
-{
-        switch (state) {
-        case PM_SUSPEND_STANDBY:
-                pnx4008_standby();
-                break;
-        case PM_SUSPEND_MEM:
-                pnx4008_suspend();
-                break;
-        }
-        return 0;
-}
-static int pnx4008_pm_valid(suspend_state_t state)
-{
-        return (state == PM_SUSPEND_STANDBY) ||
-               (state == PM_SUSPEND_MEM);
-}
-static const struct platform_suspend_ops pnx4008_pm_ops = {
-        .enter = pnx4008_pm_enter,
-        .valid = pnx4008_pm_valid,
-};
-int __init pnx4008_pm_init(void)
-{
-        u32 sram_size_to_allocate;
-        pll4_clk = clk_get(0, "ck_pll4");
-        if (IS_ERR(pll4_clk)) {
-                printk(KERN_ERR
-                       "PM Suspend cannot acquire ARM(PLL4) clock control\n");
-                return PTR_ERR(pll4_clk);
-        }
-        if (pnx4008_cpu_standby_sz > pnx4008_cpu_suspend_sz)
-                sram_size_to_allocate = pnx4008_cpu_standby_sz;
-        else
-                sram_size_to_allocate = pnx4008_cpu_suspend_sz;
-        saved_sram = kmalloc(sram_size_to_allocate, GFP_ATOMIC);
-        if (!saved_sram) {
-                printk(KERN_ERR
-                       "PM Suspend: cannot allocate memory to save portion of SRAM\n");
-                clk_put(pll4_clk);
-                return -ENOMEM;
-        }
-        suspend_set_ops(&pnx4008_pm_ops);
-        return 0;
-}
diff --git a/arch/arm/mach-pnx4008/serial.c b/arch/arm/mach-pnx4008/serial.c
deleted file mode 100644
index 374c138ac1ac..000000000000
--- a/arch/arm/mach-pnx4008/serial.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *  linux/arch/arm/mach-pnx4008/serial.c
- *
- *  PNX4008 UART initialization
- *
- *  Copyright:  MontaVista Software Inc. (c) 2005
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/io.h>
-#include <mach/platform.h>
-#include <mach/hardware.h>
-#include <linux/serial_core.h>
-#include <linux/serial_reg.h>
-#include <mach/gpio-pnx4008.h>
-#include <mach/clock.h>
-#define UART_3          0
-#define UART_4          1
-#define UART_5          2
-#define UART_6          3
-#define UART_UNKNOWN    (-1)
-#define UART3_BASE_VA   IO_ADDRESS(PNX4008_UART3_BASE)
-#define UART4_BASE_VA   IO_ADDRESS(PNX4008_UART4_BASE)
-#define UART5_BASE_VA   IO_ADDRESS(PNX4008_UART5_BASE)
-#define UART6_BASE_VA   IO_ADDRESS(PNX4008_UART6_BASE)
-#define UART_FCR_OFFSET         8
-#define UART_FIFO_SIZE          64
-void pnx4008_uart_init(void)
-{
-        u32 tmp;
-        int i = UART_FIFO_SIZE;
-        __raw_writel(0xC1, UART5_BASE_VA + UART_FCR_OFFSET);
-        __raw_writel(0xC1, UART3_BASE_VA + UART_FCR_OFFSET);
-        /* Send a NULL to fix the UART HW bug */
-        __raw_writel(0x00, UART5_BASE_VA);
-        __raw_writel(0x00, UART3_BASE_VA);
-        while (i--) {
-                tmp = __raw_readl(UART5_BASE_VA);
-                tmp = __raw_readl(UART3_BASE_VA);
-        }
-        __raw_writel(0, UART5_BASE_VA + UART_FCR_OFFSET);
-        __raw_writel(0, UART3_BASE_VA + UART_FCR_OFFSET);
-        /* setup wakeup interrupt */
-        start_int_set_rising_edge(SE_U3_RX_INT);
-        start_int_ack(SE_U3_RX_INT);
-        start_int_umask(SE_U3_RX_INT);
-        start_int_set_rising_edge(SE_U5_RX_INT);
-        start_int_ack(SE_U5_RX_INT);
-        start_int_umask(SE_U5_RX_INT);
-}
diff --git a/arch/arm/mach-pnx4008/sleep.S b/arch/arm/mach-pnx4008/sleep.S
deleted file mode 100644
index f4eed495d295..000000000000
--- a/arch/arm/mach-pnx4008/sleep.S
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * linux/arch/arm/mach-pnx4008/sleep.S
- *
- * PNX4008 support for STOP mode and SDRAM self-refresh
- *
- * Authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <mach/hardware.h>
-#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
-#define PWR_CTRL_REG_OFFS 0x44
-#define SDRAM_CFG_VA_BASE IO_ADDRESS(PNX4008_SDRAM_CFG_BASE)
-#define MPMC_STATUS_REG_OFFS 0x4
-                .text
-ENTRY(pnx4008_cpu_suspend)
-        @this function should be entered in Direct run mode.
-        @ save registers on stack
-        stmfd   sp!, {r0 - r6, lr}
-        @ setup Power Manager base address in r4
-        @ and put it's value in r5
-        mov     r4, #(PWRMAN_VA_BASE & 0xff000000)
-        orr     r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
-        orr     r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
-        orr     r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
-        ldr     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ setup SDRAM controller base address in r2
-        @ and put it's value in r3
-        mov     r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
-        orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
-        orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
-        orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
-        ldr     r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
-        @ clear SDRAM self-refresh bit latch
-        and     r5, r5, #(~(1 << 8))
-        @ clear SDRAM self-refresh bit
-        and     r5, r5, #(~(1 << 9))
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ do save current bit settings in r1
-        mov     r1, r5
-        @ set SDRAM self-refresh bit
-        orr     r5, r5, #(1 << 9)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ set SDRAM self-refresh bit latch
-        orr     r5, r5, #(1 << 8)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ clear SDRAM self-refresh bit latch
-        and     r5, r5, #(~(1 << 8))
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ clear SDRAM self-refresh bit
-        and     r5, r5, #(~(1 << 9))
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ wait for SDRAM to get into self-refresh mode
-2:      ldr     r3, [r2, #MPMC_STATUS_REG_OFFS]
-        tst     r3, #(1 << 2)
-        beq     2b
-        @ to prepare SDRAM to get out of self-refresh mode after wakeup
-        orr     r5, r5, #(1 << 7)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ do enter stop mode
-        orr     r5, r5, #(1 << 0)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        @ sleeping now...
-        @ coming out of STOP mode into Direct Run mode
-        @ clear STOP mode and SDRAM self-refresh bits
-        str     r1, [r4, #PWR_CTRL_REG_OFFS]
-        @ wait for SDRAM to get out self-refresh mode
-3:      ldr     r3, [r2, #MPMC_STATUS_REG_OFFS]
-        tst     r3, #5
-        bne     3b
-        @ restore regs and return
-        ldmfd   sp!, {r0 - r6, pc}
-ENTRY(pnx4008_cpu_suspend_sz)
-        .word   . - pnx4008_cpu_suspend
-ENTRY(pnx4008_cpu_standby)
-        @ save registers on stack
-        stmfd   sp!, {r0 - r6, lr}
-        @ setup Power Manager base address in r4
-        @ and put it's value in r5
-        mov     r4, #(PWRMAN_VA_BASE & 0xff000000)
-        orr     r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
-        orr     r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
-        orr     r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
-        ldr     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ setup SDRAM controller base address in r2
-        @ and put it's value in r3
-        mov     r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
-        orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
-        orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
-        orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
-        ldr     r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
-        @ clear SDRAM self-refresh bit latch
-        and     r5, r5, #(~(1 << 8))
-        @ clear SDRAM self-refresh bit
-        and     r5, r5, #(~(1 << 9))
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ do save current bit settings in r1
-        mov     r1, r5
-        @ set SDRAM self-refresh bit
-        orr     r5, r5, #(1 << 9)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ set SDRAM self-refresh bit latch
-        orr     r5, r5, #(1 << 8)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ clear SDRAM self-refresh bit latch
-        and     r5, r5, #(~(1 << 8))
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ clear SDRAM self-refresh bit
-        and     r5, r5, #(~(1 << 9))
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ wait for SDRAM to get into self-refresh mode
-2:      ldr     r3, [r2, #MPMC_STATUS_REG_OFFS]
-        tst     r3, #(1 << 2)
-        beq     2b
-        @ set 'get out of self-refresh mode after wakeup' bit
-        orr     r5, r5, #(1 << 7)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        mcr     p15, 0, r0, c7, c0, 4   @ kinda sleeping now...
-        @ set SDRAM self-refresh bit latch
-        orr     r5, r5, #(1 << 8)
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ clear SDRAM self-refresh bit latch
-        and     r5, r5, #(~(1 << 8))
-        str     r5, [r4, #PWR_CTRL_REG_OFFS]
-        @ wait for SDRAM to get out self-refresh mode
-3:      ldr     r3, [r2, #MPMC_STATUS_REG_OFFS]
-        tst     r3, #5
-        bne     3b
-        @ restore regs and return
-        ldmfd   sp!, {r0 - r6, pc}
-ENTRY(pnx4008_cpu_standby_sz)
-        .word   . - pnx4008_cpu_standby
-ENTRY(pnx4008_cache_clean_invalidate)
-        stmfd   sp!, {r0 - r6, lr}
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-        mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
-#else
-1:      mrc     p15, 0, r15, c7, c14, 3         @ test,clean,invalidate
-        bne     1b
-#endif
-        ldmfd   sp!, {r0 - r6, pc}
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
deleted file mode 100644
index 0cfe8af3d3be..000000000000
--- a/arch/arm/mach-pnx4008/time.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/time.c
- *
- * PNX4008 Timers
- *
- * Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-#include <linux/kallsyms.h>
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach/time.h>
-#include <asm/errno.h>
-#include "time.h"
-/*! Note: all timers are UPCOUNTING */
-/*!
- * Returns number of us since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
- */
-static unsigned long pnx4008_gettimeoffset(void)
-{
-        u32 ticks_to_match =
-            __raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER);
-        u32 elapsed = LATCH - ticks_to_match;
-        return (elapsed * (tick_nsec / 1000)) / LATCH;
-}
-/*!
- * IRQ handler for the timer
- */
-static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id)
-{
-        if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
-                do {
-                        timer_tick();
-                        /*
-                         * this algorithm takes care of possible delay
-                         * for this interrupt handling longer than a normal
-                         * timer period
-                         */
-                        __raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH,
-                                     HSTIM_MATCH0);
-                        __raw_writel(MATCH0_INT, HSTIM_INT);    /* clear interrupt */
-                        /*
-                         * The goal is to keep incrementing HSTIM_MATCH0
-                         * register until HSTIM_MATCH0 indicates time after
-                         * what HSTIM_COUNTER indicates.
-                         */
-                } while ((signed)
-                         (__raw_readl(HSTIM_MATCH0) -
-                          __raw_readl(HSTIM_COUNTER)) < 0);
-        }
-        return IRQ_HANDLED;
-}
-static struct irqaction pnx4008_timer_irq = {
-        .name = "PNX4008 Tick Timer",
-        .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler = pnx4008_timer_interrupt
-};
-/*!
- * Set up timer and timer interrupt.
- */
-static __init void pnx4008_setup_timer(void)
-{
-        __raw_writel(RESET_COUNT, MSTIM_CTRL);
-        while (__raw_readl(MSTIM_COUNTER)) ;    /* wait for reset to complete. 100% guarantee event */
-        __raw_writel(0, MSTIM_CTRL);    /* stop the timer */
-        __raw_writel(0, MSTIM_MCTRL);
-        __raw_writel(RESET_COUNT, HSTIM_CTRL);
-        while (__raw_readl(HSTIM_COUNTER)) ;    /* wait for reset to complete. 100% guarantee event */
-        __raw_writel(0, HSTIM_CTRL);
-        __raw_writel(0, HSTIM_MCTRL);
-        __raw_writel(0, HSTIM_CCR);
-        __raw_writel(12, HSTIM_PMATCH); /* scale down to 1 MHZ */
-        __raw_writel(LATCH, HSTIM_MATCH0);
-        __raw_writel(MR0_INT, HSTIM_MCTRL);
-        setup_irq(HSTIMER_INT, &pnx4008_timer_irq);
-        __raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL);        /*start timer, stop when JTAG active */
-}
-/* Timer Clock Control in PM register */
-#define TIMCLK_CTRL_REG  IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC))
-#define WATCHDOG_CLK_EN                   1
-#define TIMER_CLK_EN                      2     /* HS and MS timers? */
-static u32 timclk_ctrl_reg_save;
-void pnx4008_timer_suspend(void)
-{
-        timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG);
-        __raw_writel(0, TIMCLK_CTRL_REG);       /* disable timers */
-}
-void pnx4008_timer_resume(void)
-{
-        __raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG);    /* enable timers */
-}
-struct sys_timer pnx4008_timer = {
-        .init = pnx4008_setup_timer,
-        .offset = pnx4008_gettimeoffset,
-        .suspend = pnx4008_timer_suspend,
-        .resume = pnx4008_timer_resume,
-};
diff --git a/arch/arm/mach-pnx4008/time.h b/arch/arm/mach-pnx4008/time.h
deleted file mode 100644
index 75e88c570aa7..000000000000
--- a/arch/arm/mach-pnx4008/time.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/timex.h
- *
- * PNX4008 timers header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef PNX_TIME_H
-#define PNX_TIME_H
-#include <linux/io.h>
-#include <mach/hardware.h>
-#define TICKS2USECS(x)  (x)
-/* MilliSecond Timer - Chapter 21 Page 202 */
-#define MSTIM_INT     IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
-#define MSTIM_CTRL    IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
-#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
-#define MSTIM_MCTRL   IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
-#define MSTIM_MATCH0  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
-#define MSTIM_MATCH1  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
-/* High Speed Timer - Chpater 22, Page 205 */
-#define HSTIM_INT     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
-#define HSTIM_CTRL    IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
-#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
-#define HSTIM_PMATCH  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
-#define HSTIM_PCOUNT  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
-#define HSTIM_MCTRL   IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
-#define HSTIM_MATCH0  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
-#define HSTIM_MATCH1  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
-#define HSTIM_MATCH2  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
-#define HSTIM_CCR     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
-#define HSTIM_CR0     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
-#define HSTIM_CR1     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
-/* IMPORTANT: both timers are UPCOUNTING */
-/* xSTIM_MCTRL bit definitions */
-#define MR0_INT        1
-#define RESET_COUNT0   (1<<1)
-#define STOP_COUNT0    (1<<2)
-#define MR1_INT        (1<<3)
-#define RESET_COUNT1   (1<<4)
-#define STOP_COUNT1    (1<<5)
-#define MR2_INT        (1<<6)
-#define RESET_COUNT2   (1<<7)
-#define STOP_COUNT2    (1<<8)
-/* xSTIM_CTRL bit definitions */
-#define COUNT_ENAB     1
-#define RESET_COUNT    (1<<1)
-#define DEBUG_EN       (1<<2)
-/* xSTIM_INT bit definitions */
-#define MATCH0_INT     1
-#define MATCH1_INT     (1<<1)
-#define MATCH2_INT     (1<<2)
-#define RTC_TICK0      (1<<4)
-#define RTC_TICK1      (1<<5)
-#endif
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
new file mode 100644
index 000000000000..41fc85327673
--- /dev/null
+++ b/arch/arm/mach-prima2/Kconfig
@@ -0,0 +1,19 @@
+if ARCH_SIRF
+menu "CSR SiRF primaII/Marco/Polo Specific Features"
+config ARCH_PRIMA2
+        bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
+        default y
+        select CPU_V7
+        select ZONE_DMA
+        select SIRF_IRQ
+        help
+          Support for CSR SiRFSoC ARM Cortex A9 Platform
+endmenu
+config SIRF_IRQ
+        bool
+endif
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index 13dd1604d951..fc9ce22e2b5a 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -1,9 +1,8 @@
 obj-y := timer.o
-obj-y += irq.o
-obj-y += clock.o
 obj-y += rstc.o
-obj-y += prima2.o
+obj-y += common.o
 obj-y += rtciobrg.o
 obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_CACHE_L2X0) += l2x0.o
 obj-$(CONFIG_SUSPEND) += pm.o sleep.o
+obj-$(CONFIG_SIRF_IRQ) += irq.o
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c
deleted file mode 100644
index aebad7e565cf..000000000000
--- a/arch/arm/mach-prima2/clock.c
+++ /dev/null
@@ -1,510 +0,0 @@
-/*
- * Clock tree for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-#include <linux/module.h>
-#include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <asm/mach/map.h>
-#include <mach/map.h>
-#define SIRFSOC_CLKC_CLK_EN0    0x0000
-#define SIRFSOC_CLKC_CLK_EN1    0x0004
-#define SIRFSOC_CLKC_REF_CFG    0x0014
-#define SIRFSOC_CLKC_CPU_CFG    0x0018
-#define SIRFSOC_CLKC_MEM_CFG    0x001c
-#define SIRFSOC_CLKC_SYS_CFG    0x0020
-#define SIRFSOC_CLKC_IO_CFG     0x0024
-#define SIRFSOC_CLKC_DSP_CFG    0x0028
-#define SIRFSOC_CLKC_GFX_CFG    0x002c
-#define SIRFSOC_CLKC_MM_CFG     0x0030
-#define SIRFSOC_LKC_LCD_CFG     0x0034
-#define SIRFSOC_CLKC_MMC_CFG    0x0038
-#define SIRFSOC_CLKC_PLL1_CFG0  0x0040
-#define SIRFSOC_CLKC_PLL2_CFG0  0x0044
-#define SIRFSOC_CLKC_PLL3_CFG0  0x0048
-#define SIRFSOC_CLKC_PLL1_CFG1  0x004c
-#define SIRFSOC_CLKC_PLL2_CFG1  0x0050
-#define SIRFSOC_CLKC_PLL3_CFG1  0x0054
-#define SIRFSOC_CLKC_PLL1_CFG2  0x0058
-#define SIRFSOC_CLKC_PLL2_CFG2  0x005c
-#define SIRFSOC_CLKC_PLL3_CFG2  0x0060
-#define SIRFSOC_CLOCK_VA_BASE           SIRFSOC_VA(0x005000)
-#define KHZ     1000
-#define MHZ     (KHZ * KHZ)
-struct clk_ops {
-        unsigned long (*get_rate)(struct clk *clk);
-        long (*round_rate)(struct clk *clk, unsigned long rate);
-        int (*set_rate)(struct clk *clk, unsigned long rate);
-        int (*enable)(struct clk *clk);
-        int (*disable)(struct clk *clk);
-        struct clk *(*get_parent)(struct clk *clk);
-        int (*set_parent)(struct clk *clk, struct clk *parent);
-};
-struct clk {
-        struct clk *parent;     /* parent clk */
-        unsigned long rate;     /* clock rate in Hz */
-        signed char usage;      /* clock enable count */
-        signed char enable_bit; /* enable bit: 0 ~ 63 */
-        unsigned short regofs;  /* register offset */
-        struct clk_ops *ops;    /* clock operation */
-};
-static DEFINE_SPINLOCK(clocks_lock);
-static inline unsigned long clkc_readl(unsigned reg)
-{
-        return readl(SIRFSOC_CLOCK_VA_BASE + reg);
-}
-static inline void clkc_writel(u32 val, unsigned reg)
-{
-        writel(val, SIRFSOC_CLOCK_VA_BASE + reg);
-}
-/*
- * osc_rtc - real time oscillator - 32.768KHz
- * osc_sys - high speed oscillator - 26MHz
- */
-static struct clk clk_rtc = {
-        .rate = 32768,
-};
-static struct clk clk_osc = {
-        .rate = 26 * MHZ,
-};
-/*
- * std pll
- */
-static unsigned long std_pll_get_rate(struct clk *clk)
-{
-        unsigned long fin = clk_get_rate(clk->parent);
-        u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
-                SIRFSOC_CLKC_PLL1_CFG0;
-        if (clkc_readl(regcfg2) & BIT(2)) {
-                /* pll bypass mode */
-                clk->rate = fin;
-        } else {
-                /* fout = fin * nf / nr / od */
-                u32 cfg0 = clkc_readl(clk->regofs);
-                u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
-                u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
-                u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
-                WARN_ON(fin % MHZ);
-                clk->rate = fin / MHZ * nf / nr / od * MHZ;
-        }
-        return clk->rate;
-}
-static int std_pll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long fin, nf, nr, od, reg;
-        /*
-         * fout = fin * nf / (nr * od);
-         * set od = 1, nr = fin/MHz, so fout = nf * MHz
-         */
-        nf = rate / MHZ;
-        if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
-                return -EINVAL;
-        fin = clk_get_rate(clk->parent);
-        BUG_ON(fin < MHZ);
-        nr = fin / MHZ;
-        BUG_ON((fin % MHZ) || nr > BIT(6));
-        od = 1;
-        reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
-        clkc_writel(reg, clk->regofs);
-        reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
-        clkc_writel((nf >> 1) - 1, reg);
-        reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
-        while (!(clkc_readl(reg) & BIT(6)))
-                cpu_relax();
-        clk->rate = 0; /* set to zero will force recalculation */
-        return 0;
-}
-static struct clk_ops std_pll_ops = {
-        .get_rate = std_pll_get_rate,
-        .set_rate = std_pll_set_rate,
-};
-static struct clk clk_pll1 = {
-        .parent = &clk_osc,
-        .regofs = SIRFSOC_CLKC_PLL1_CFG0,
-        .ops = &std_pll_ops,
-};
-static struct clk clk_pll2 = {
-        .parent = &clk_osc,
-        .regofs = SIRFSOC_CLKC_PLL2_CFG0,
-        .ops = &std_pll_ops,
-};
-static struct clk clk_pll3 = {
-        .parent = &clk_osc,
-        .regofs = SIRFSOC_CLKC_PLL3_CFG0,
-        .ops = &std_pll_ops,
-};
-/*
- * clock domains - cpu, mem, sys/io
- */
-static struct clk clk_mem;
-static struct clk *dmn_get_parent(struct clk *clk)
-{
-        struct clk *clks[] = {
-                &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
-        };
-        u32 cfg = clkc_readl(clk->regofs);
-        WARN_ON((cfg & (BIT(3) - 1)) > 4);
-        return clks[cfg & (BIT(3) - 1)];
-}
-static int dmn_set_parent(struct clk *clk, struct clk *parent)
-{
-        const struct clk *clks[] = {
-                &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
-        };
-        u32 cfg = clkc_readl(clk->regofs);
-        int i;
-        for (i = 0; i < ARRAY_SIZE(clks); i++) {
-                if (clks[i] == parent) {
-                        cfg &= ~(BIT(3) - 1);
-                        clkc_writel(cfg | i, clk->regofs);
-                        /* BIT(3) - switching status: 1 - busy, 0 - done */
-                        while (clkc_readl(clk->regofs) & BIT(3))
-                                cpu_relax();
-                        return 0;
-                }
-        }
-        return -EINVAL;
-}
-static unsigned long dmn_get_rate(struct clk *clk)
-{
-        unsigned long fin = clk_get_rate(clk->parent);
-        u32 cfg = clkc_readl(clk->regofs);
-        if (cfg & BIT(24)) {
-                /* fcd bypass mode */
-                clk->rate = fin;
-        } else {
-                /*
-                 * wait count: bit[19:16], hold count: bit[23:20]
-                 */
-                u32 wait = (cfg >> 16) & (BIT(4) - 1);
-                u32 hold = (cfg >> 20) & (BIT(4) - 1);
-                clk->rate = fin / (wait + hold + 2);
-        }
-        return clk->rate;
-}
-static int dmn_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long fin;
-        unsigned ratio, wait, hold, reg;
-        unsigned bits = (clk == &clk_mem) ? 3 : 4;
-        fin = clk_get_rate(clk->parent);
-        ratio = fin / rate;
-        if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
-                return -EINVAL;
-        WARN_ON(fin % rate);
-        wait = (ratio >> 1) - 1;
-        hold = ratio - wait - 2;
-        reg = clkc_readl(clk->regofs);
-        reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
-        reg |= (wait << 16) | (hold << 20) | BIT(25);
-        clkc_writel(reg, clk->regofs);
-        /* waiting FCD been effective */
-        while (clkc_readl(clk->regofs) & BIT(25))
-                cpu_relax();
-        clk->rate = 0; /* set to zero will force recalculation */
-        return 0;
-}
-/*
- * cpu clock has no FCD register in Prima2, can only change pll
- */
-static int cpu_set_rate(struct clk *clk, unsigned long rate)
-{
-        int ret1, ret2;
-        struct clk *cur_parent, *tmp_parent;
-        cur_parent = dmn_get_parent(clk);
-        BUG_ON(cur_parent == NULL || cur_parent->usage > 1);
-        /* switch to tmp pll before setting parent clock's rate */
-        tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1;
-        ret1 = dmn_set_parent(clk, tmp_parent);
-        BUG_ON(ret1);
-        ret2 = clk_set_rate(cur_parent, rate);
-        ret1 = dmn_set_parent(clk, cur_parent);
-        clk->rate = 0; /* set to zero will force recalculation */
-        return ret2 ? ret2 : ret1;
-}
-static struct clk_ops cpu_ops = {
-        .get_parent = dmn_get_parent,
-        .set_parent = dmn_set_parent,
-        .set_rate = cpu_set_rate,
-};
-static struct clk clk_cpu = {
-        .parent = &clk_pll1,
-        .regofs = SIRFSOC_CLKC_CPU_CFG,
-        .ops = &cpu_ops,
-};
-static struct clk_ops msi_ops = {
-        .set_rate = dmn_set_rate,
-        .get_rate = dmn_get_rate,
-        .set_parent = dmn_set_parent,
-        .get_parent = dmn_get_parent,
-};
-static struct clk clk_mem = {
-        .parent = &clk_pll2,
-        .regofs = SIRFSOC_CLKC_MEM_CFG,
-        .ops = &msi_ops,
-};
-static struct clk clk_sys = {
-        .parent = &clk_pll3,
-        .regofs = SIRFSOC_CLKC_SYS_CFG,
-        .ops = &msi_ops,
-};
-static struct clk clk_io = {
-        .parent = &clk_pll3,
-        .regofs = SIRFSOC_CLKC_IO_CFG,
-        .ops = &msi_ops,
-};
-/*
- * on-chip clock sets
- */
-static struct clk_lookup onchip_clks[] = {
-        {
-                .dev_id = "rtc",
-                .clk = &clk_rtc,
-        }, {
-                .dev_id = "osc",
-                .clk = &clk_osc,
-        }, {
-                .dev_id = "pll1",
-                .clk = &clk_pll1,
-        }, {
-                .dev_id = "pll2",
-                .clk = &clk_pll2,
-        }, {
-                .dev_id = "pll3",
-                .clk = &clk_pll3,
-        }, {
-                .dev_id = "cpu",
-                .clk = &clk_cpu,
-        }, {
-                .dev_id = "mem",
-                .clk = &clk_mem,
-        }, {
-                .dev_id = "sys",
-                .clk = &clk_sys,
-        }, {
-                .dev_id = "io",
-                .clk = &clk_io,
-        },
-};
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-        if (unlikely(IS_ERR_OR_NULL(clk)))
-                return -EINVAL;
-        if (clk->parent)
-                clk_enable(clk->parent);
-        spin_lock_irqsave(&clocks_lock, flags);
-        if (!clk->usage++ && clk->ops && clk->ops->enable)
-                clk->ops->enable(clk);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-        if (unlikely(IS_ERR_OR_NULL(clk)))
-                return;
-        WARN_ON(!clk->usage);
-        spin_lock_irqsave(&clocks_lock, flags);
-        if (--clk->usage == 0 && clk->ops && clk->ops->disable)
-                clk->ops->disable(clk);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        if (clk->parent)
-                clk_disable(clk->parent);
-}
-EXPORT_SYMBOL(clk_disable);
-unsigned long clk_get_rate(struct clk *clk)
-{
-        if (unlikely(IS_ERR_OR_NULL(clk)))
-                return 0;
-        if (clk->rate)
-                return clk->rate;
-        if (clk->ops && clk->ops->get_rate)
-                return clk->ops->get_rate(clk);
-        return clk_get_rate(clk->parent);
-}
-EXPORT_SYMBOL(clk_get_rate);
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        if (unlikely(IS_ERR_OR_NULL(clk)))
-                return 0;
-        if (clk->ops && clk->ops->round_rate)
-                return clk->ops->round_rate(clk, rate);
-        return 0;
-}
-EXPORT_SYMBOL(clk_round_rate);
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        if (unlikely(IS_ERR_OR_NULL(clk)))
-                return -EINVAL;
-        if (!clk->ops || !clk->ops->set_rate)
-                return -EINVAL;
-        return clk->ops->set_rate(clk, rate);
-}
-EXPORT_SYMBOL(clk_set_rate);
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        int ret;
-        unsigned long flags;
-        if (unlikely(IS_ERR_OR_NULL(clk)))
-                return -EINVAL;
-        if (!clk->ops || !clk->ops->set_parent)
-                return -EINVAL;
-        spin_lock_irqsave(&clocks_lock, flags);
-        ret = clk->ops->set_parent(clk, parent);
-        if (!ret) {
-                parent->usage += clk->usage;
-                clk->parent->usage -= clk->usage;
-                BUG_ON(clk->parent->usage < 0);
-                clk->parent = parent;
-        }
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-struct clk *clk_get_parent(struct clk *clk)
-{
-        unsigned long flags;
-        if (unlikely(IS_ERR_OR_NULL(clk)))
-                return NULL;
-        if (!clk->ops || !clk->ops->get_parent)
-                return clk->parent;
-        spin_lock_irqsave(&clocks_lock, flags);
-        clk->parent = clk->ops->get_parent(clk);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-static void __init sirfsoc_clk_init(void)
-{
-        clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
-}
-static struct of_device_id clkc_ids[] = {
-        { .compatible = "sirf,prima2-clkc" },
-        {},
-};
-void __init sirfsoc_of_clk_init(void)
-{
-        struct device_node *np;
-        struct resource res;
-        struct map_desc sirfsoc_clkc_iodesc = {
-                .virtual = SIRFSOC_CLOCK_VA_BASE,
-                .type    = MT_DEVICE,
-        };
-        np = of_find_matching_node(NULL, clkc_ids);
-        if (!np)
-                panic("unable to find compatible clkc node in dtb\n");
-        if (of_address_to_resource(np, 0, &res))
-                panic("unable to find clkc range in dtb");
-        of_node_put(np);
-        sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start);
-        sirfsoc_clkc_iodesc.length = 1 + res.end - res.start;
-        iotable_init(&sirfsoc_clkc_iodesc, 1);
-        sirfsoc_clk_init();
-}
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/common.c
index 8f0429d4b79f..f25a54194639 100644
--- a/arch/arm/mach-prima2/prima2.c
+++ b/arch/arm/mach-prima2/common.c
@@ -30,21 +30,21 @@ void __init sirfsoc_init_late(void)
        sirfsoc_pm_init();
 }
-static const char *prima2cb_dt_match[] __initdata = {
+#ifdef CONFIG_ARCH_PRIMA2
-       "sirf,prima2-cb",
+static const char *prima2_dt_match[] __initdata = {
+       "sirf,prima2",
       NULL
 };
-MACHINE_START(PRIMA2_EVB, "prima2cb")
+DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
        /* Maintainer: Barry Song <baohua.song@csr.com> */
-        .atag_offset    = 0x100,
-        .init_early     = sirfsoc_of_clk_init,
        .map_io         = sirfsoc_map_lluart,
        .init_irq       = sirfsoc_of_irq_init,
        .timer          = &sirfsoc_timer,
        .dma_zone_size  = SZ_256M,
        .init_machine   = sirfsoc_mach_init,
        .init_late      = sirfsoc_init_late,
-        .dt_compat      = prima2cb_dt_match,
+        .dt_compat      = prima2_dt_match,
        .restart        = sirfsoc_restart,
 MACHINE_END
+#endif
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h
index 83125c6a30b3..0c898fcf909c 100644
--- a/arch/arm/mach-prima2/include/mach/uncompress.h
+++ b/arch/arm/mach-prima2/include/mach/uncompress.h
@@ -25,11 +25,11 @@ static __inline__ void putc(char c)
         * during kernel decompression, all mappings are flat:
         *  virt_addr == phys_addr
         */
-        while (__raw_readl(SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
+        while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
                & SIRFSOC_UART1_TXFIFO_FULL)
                barrier();
-        __raw_writel(c, SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
+        __raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
 }
 static inline void flush(void)
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
index a7b9415d30f8..7dee9176e77a 100644
--- a/arch/arm/mach-prima2/irq.c
+++ b/arch/arm/mach-prima2/irq.c
@@ -63,7 +63,7 @@ void __init sirfsoc_of_irq_init(void)
        np = of_find_matching_node(NULL, intc_ids);
        if (!np)
-                panic("unable to find compatible intc node in dtb\n");
+                return;
        sirfsoc_intc_base = of_iomap(np, 0);
        if (!sirfsoc_intc_base)
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
index f224107de7bc..d95bf252f694 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer.c
@@ -21,6 +21,8 @@
 #include <asm/sched_clock.h>
 #include <asm/mach/time.h>
+#include "common.h"
 #define SIRFSOC_TIMER_COUNTER_LO        0x0000
 #define SIRFSOC_TIMER_COUNTER_HI        0x0004
 #define SIRFSOC_TIMER_MATCH_0           0x0008
@@ -188,9 +190,13 @@ static void __init sirfsoc_clockevent_init(void)
 static void __init sirfsoc_timer_init(void)
 {
        unsigned long rate;
+        struct clk *clk;
+        /* initialize clocking early, we want to set the OS timer */
+        sirfsoc_of_clk_init();
        /* timer's input clock is io clock */
-        struct clk *clk = clk_get_sys("io", NULL);
+        clk = clk_get_sys("io", NULL);
        BUG_ON(IS_ERR(clk));
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index fe2d1f80ef50..8e6288de69b9 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -25,6 +25,18 @@ config PXA_V7_MACH_AUTO
 if !ARCH_PXA_V7
 comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
+config MACH_PXA3XX_DT
+        bool "Support PXA3xx platforms from device tree"
+        select PXA3xx
+        select CPU_PXA300
+        select POWER_SUPPLY
+        select HAVE_PWM
+        select USE_OF
+        help
+          Include support for Marvell PXA3xx based platforms using
+          the device tree. Needn't select any other machine while
+          MACH_PXA3XX_DT is enabled.
 config ARCH_LUBBOCK
        bool "Intel DBPXA250 Development Platform (aka Lubbock)"
        select PXA25x
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index be0f7df8685c..ee88d6eae648 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -26,6 +26,9 @@ obj-$(CONFIG_CPU_PXA930)	+= pxa930.o
 # NOTE: keep the order of boards in accordance to their order in Kconfig
+# Device Tree support
+obj-$(CONFIG_MACH_PXA3XX_DT)    += pxa-dt.o
 # Intel/Marvell Dev Platforms
 obj-$(CONFIG_ARCH_LUBBOCK)      += lubbock.o
 obj-$(CONFIG_MACH_MAINSTONE)    += mainstone.o
@@ -95,12 +98,4 @@ obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR)	+= raumfeld.o
 obj-$(CONFIG_MACH_RAUMFELD_SPEAKER)     += raumfeld.o
 obj-$(CONFIG_MACH_ZIPIT2)       += z2.o
-# Support for blinky lights
-led-y := leds.o
-led-$(CONFIG_ARCH_LUBBOCK)      += leds-lubbock.o
-led-$(CONFIG_MACH_MAINSTONE)    += leds-mainstone.o
-led-$(CONFIG_ARCH_PXA_IDP)      += leds-idp.o
-obj-$(CONFIG_LEDS)              += $(led-y)
 obj-$(CONFIG_TOSA_BT)           += tosa-bt.o
diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c
index ccdac4b6a469..ffa6d811aad8 100644
--- a/arch/arm/mach-pxa/am200epd.c
+++ b/arch/arm/mach-pxa/am200epd.c
@@ -32,7 +32,7 @@
 #include <mach/pxa25x.h>
 #include <mach/gumstix.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c
index 76c4b9494031..3dfec1ec462d 100644
--- a/arch/arm/mach-pxa/am300epd.c
+++ b/arch/arm/mach-pxa/am300epd.c
@@ -30,7 +30,7 @@
 #include <mach/gumstix.h>
 #include <mach/mfp-pxa25x.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 9244493dbcb7..208229342514 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -45,12 +45,12 @@
 #include <mach/pxa27x.h>
 #include <mach/balloon3.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/udc.h>
 #include <mach/pxa27x-udc.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c
index 2a37a9a8f621..d4e9499832dc 100644
--- a/arch/arm/mach-pxa/clock-pxa3xx.c
+++ b/arch/arm/mach-pxa/clock-pxa3xx.c
@@ -127,8 +127,10 @@ void clk_pxa3xx_cken_enable(struct clk *clk)
        if (clk->cken < 32)
                CKENA |= mask;
-        else
+        else if (clk->cken < 64)
                CKENB |= mask;
+        else
+                CKENC |= mask;
 }
 void clk_pxa3xx_cken_disable(struct clk *clk)
@@ -137,8 +139,10 @@ void clk_pxa3xx_cken_disable(struct clk *clk)
        if (clk->cken < 32)
                CKENA &= ~mask;
-        else
+        else if (clk->cken < 64)
                CKENB &= ~mask;
+        else
+                CKENC &= ~mask;
 }
 const struct clkops clk_pxa3xx_cken_ops = {
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index 431ef56700c4..2503db9e3253 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -22,8 +22,8 @@
 #include <linux/spi/libertas_spi.h>
 #include <mach/pxa27x.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index 8fa4ad27edf3..a103c8ffea9f 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -22,9 +22,10 @@
 #include <asm/mach/map.h>
 #include <mach/pxa25x.h>
+#undef GPIO24_SSP1_SFRM
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/smemc.h>
 #include <asm/hardware/it8152.h>
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index 3e4e9fe2d462..cc2b23afcaaf 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -48,12 +48,12 @@
 #include <mach/pxa300.h>
 #include <mach/pxa27x-udc.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 #include <mach/audio.h>
-#include <mach/pxa3xx-u2d.h>
+#include <linux/platform_data/usb-pxa3xx-ulpi.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-pxa/colibri-evalboard.c b/arch/arm/mach-pxa/colibri-evalboard.c
index d28e802e2448..8404b24240ea 100644
--- a/arch/arm/mach-pxa/colibri-evalboard.c
+++ b/arch/arm/mach-pxa/colibri-evalboard.c
@@ -23,8 +23,8 @@
 #include <mach/pxa27x.h>
 #include <mach/colibri.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c
index 248804bb2c9d..2d4a7b4d5d78 100644
--- a/arch/arm/mach-pxa/colibri-pxa270-income.c
+++ b/arch/arm/mach-pxa/colibri-pxa270-income.c
@@ -27,11 +27,11 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index bb6def8ec979..a9c9c163dd95 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -24,8 +24,8 @@
 #include <mach/pxa300.h>
 #include <mach/colibri.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/audio.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index d88e7b37f1da..25515cd7e68f 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -25,8 +25,8 @@
 #include <mach/pxa320.h>
 #include <mach/colibri.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/audio.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/udc.h>
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
index 68cc75fac219..8240291ab8cf 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -24,9 +24,9 @@
 #include <mach/pxa3xx-regs.h>
 #include <mach/mfp-pxa300.h>
 #include <mach/colibri.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index c1fe32db4755..7c83f52c549c 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -46,8 +46,8 @@
 #include <asm/mach/irq.h>
 #include <mach/pxa25x.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/udc.h>
 #include <mach/corgi.h>
 #include <mach/sharpsl_pm.h>
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index 67f0de37f46e..7039f44b3647 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -23,8 +23,8 @@
 #include <asm/mach/arch.h>
 #include <mach/csb726.h>
 #include <mach/pxa27x.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/audio.h>
 #include <mach/smemc.h>
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 166eee5b8a70..ddaa04de8e22 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -6,19 +6,18 @@
 #include <linux/spi/pxa2xx_spi.h>
 #include <linux/i2c/pxa-i2c.h>
-#include <asm/pmu.h>
 #include <mach/udc.h>
-#include <mach/pxa3xx-u2d.h>
+#include <linux/platform_data/usb-pxa3xx-ulpi.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
 #include <mach/irqs.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
-#include <mach/camera.h>
+#include <linux/platform_data/camera-pxa.h>
 #include <mach/audio.h>
 #include <mach/hardware.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 #include "devices.h"
 #include "generic.h"
@@ -42,7 +41,7 @@ static struct resource pxa_resource_pmu = {
 struct platform_device pxa_device_pmu = {
        .name           = "arm-pmu",
-        .id             = ARM_PMU_DEVICE_CPU,
+        .id             = -1,
        .resource       = &pxa_resource_pmu,
        .num_resources  = 1,
 };
@@ -384,9 +383,24 @@ struct platform_device pxa_device_asoc_platform = {
 static u64 pxaficp_dmamask = ~(u32)0;
+static struct resource pxa_ir_resources[] = {
+        [0] = {
+                .start  = IRQ_STUART,
+                .end    = IRQ_STUART,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [1] = {
+                .start  = IRQ_ICP,
+                .end    = IRQ_ICP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
 struct platform_device pxa_device_ficp = {
        .name           = "pxa2xx-ir",
        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa_ir_resources),
+        .resource       = pxa_ir_resources,
        .dev            = {
                .dma_mask = &pxaficp_dmamask,
                .coherent_dma_mask = 0xffffffff,
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 97f82ad341bf..1b6411439ec8 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -42,11 +42,11 @@
 #include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
-#include <mach/camera.h>
+#include <linux/platform_data/camera-pxa.h>
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 4cb2391a782e..be2ee9bf5c6e 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -32,9 +32,9 @@
 #include <mach/eseries-gpio.h>
 #include <mach/eseries-irq.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/udc.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 15ab2533667d..dc58fa0edb66 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -29,11 +29,11 @@
 #include <asm/mach/arch.h>
 #include <mach/pxa27x.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/hardware.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
-#include <mach/camera.h>
+#include <linux/platform_data/camera-pxa.h>
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index e529a35a44ce..60755a6bb1c6 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -41,7 +41,7 @@
 #include <asm/mach/flash.h>
 #include <mach/pxa25x.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/udc.h>
 #include <mach/gumstix.h>
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index e6311988add2..5ecbd17b5641 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -45,7 +45,7 @@
 #include <mach/pxa27x.h>
 #include <mach/hx4700.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
 #include <sound/ak4641.h>
 #include <video/platform_lcd.h>
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index 6ff466bd43e8..64507cdd2e8f 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -33,9 +33,9 @@
 #include <mach/pxa25x.h>
 #include <mach/idp.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/bitfield.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include "generic.h"
 #include "devices.h"
@@ -191,6 +191,87 @@ static void __init idp_map_io(void)
        iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc));
 }
+/* LEDs */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct idp_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} idp_leds[] = {
+        { "idp:green", "heartbeat", },
+        { "idp:red", "cpu0", },
+};
+static void idp_led_set(struct led_classdev *cdev,
+                enum led_brightness b)
+{
+        struct idp_led *led = container_of(cdev,
+                        struct idp_led, cdev);
+        u32 reg = IDP_CPLD_LED_CONTROL;
+        if (b != LED_OFF)
+                reg &= ~led->mask;
+        else
+                reg |= led->mask;
+        IDP_CPLD_LED_CONTROL = reg;
+}
+static enum led_brightness idp_led_get(struct led_classdev *cdev)
+{
+        struct idp_led *led = container_of(cdev,
+                        struct idp_led, cdev);
+        return (IDP_CPLD_LED_CONTROL & led->mask) ? LED_OFF : LED_FULL;
+}
+static int __init idp_leds_init(void)
+{
+        int i;
+        if (!machine_is_pxa_idp())
+                return -ENODEV;
+        for (i = 0; i < ARRAY_SIZE(idp_leds); i++) {
+                struct idp_led *led;
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+                led->cdev.name = idp_leds[i].name;
+                led->cdev.brightness_set = idp_led_set;
+                led->cdev.brightness_get = idp_led_get;
+                led->cdev.default_trigger = idp_leds[i].trigger;
+                if (i == 0)
+                        led->mask = IDP_HB_LED;
+                else
+                        led->mask = IDP_BUSY_LED;
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+        return 0;
+}
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(idp_leds_init);
+#endif
 MACHINE_START(PXA_IDP, "Vibren PXA255 IDP")
        /* Maintainer: Vibren Technologies */
diff --git a/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h b/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h
deleted file mode 100644
index d428be4db44c..000000000000
--- a/arch/arm/mach-pxa/include/mach/arcom-pcmcia.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __ARCOM_PCMCIA_H
-#define __ARCOM_PCMCIA_H
-struct arcom_pcmcia_pdata {
-        int     cd_gpio;
-        int     rdy_gpio;
-        int     pwr_gpio;
-        void    (*reset)(int state);
-};
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/camera.h b/arch/arm/mach-pxa/include/mach/camera.h
deleted file mode 100644
index 6709b1cd7c77..000000000000
--- a/arch/arm/mach-pxa/include/mach/camera.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
-    camera.h - PXA camera driver header file
-    Copyright (C) 2003, Intel Corporation
-    Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-*/
-#ifndef __ASM_ARCH_CAMERA_H_
-#define __ASM_ARCH_CAMERA_H_
-#define PXA_CAMERA_MASTER       1
-#define PXA_CAMERA_DATAWIDTH_4  2
-#define PXA_CAMERA_DATAWIDTH_5  4
-#define PXA_CAMERA_DATAWIDTH_8  8
-#define PXA_CAMERA_DATAWIDTH_9  0x10
-#define PXA_CAMERA_DATAWIDTH_10 0x20
-#define PXA_CAMERA_PCLK_EN      0x40
-#define PXA_CAMERA_MCLK_EN      0x80
-#define PXA_CAMERA_PCP          0x100
-#define PXA_CAMERA_HSP          0x200
-#define PXA_CAMERA_VSP          0x400
-struct pxacamera_platform_data {
-        unsigned long flags;
-        unsigned long mclk_10khz;
-};
-extern void pxa_set_camera_info(struct pxacamera_platform_data *);
-#endif /* __ASM_ARCH_CAMERA_H_ */
diff --git a/arch/arm/mach-pxa/include/mach/irda.h b/arch/arm/mach-pxa/include/mach/irda.h
deleted file mode 100644
index 3cd41f77dda4..000000000000
--- a/arch/arm/mach-pxa/include/mach/irda.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef ASMARM_ARCH_IRDA_H
-#define ASMARM_ARCH_IRDA_H
-/* board specific transceiver capabilities */
-#define IR_OFF          1
-#define IR_SIRMODE      2
-#define IR_FIRMODE      4
-struct pxaficp_platform_data {
-        int transceiver_cap;
-        void (*transceiver_mode)(struct device *dev, int mode);
-        int (*startup)(struct device *dev);
-        void (*shutdown)(struct device *dev);
-        int gpio_pwdown;                /* powerdown GPIO for the IrDA chip */
-        bool gpio_pwdown_inverted;      /* gpio_pwdown is inverted */
-};
-extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
-#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
-void pxa2xx_transceiver_mode(struct device *dev, int mode);
-#endif
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/mmc.h b/arch/arm/mach-pxa/include/mach/mmc.h
deleted file mode 100644
index 9eb515bb799d..000000000000
--- a/arch/arm/mach-pxa/include/mach/mmc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef ASMARM_ARCH_MMC_H
-#define ASMARM_ARCH_MMC_H
-#include <linux/mmc/host.h>
-#include <linux/interrupt.h>
-struct device;
-struct mmc_host;
-struct pxamci_platform_data {
-        unsigned int ocr_mask;                  /* available voltages */
-        unsigned long detect_delay_ms;          /* delay in millisecond before detecting cards after interrupt */
-        int (*init)(struct device *, irq_handler_t , void *);
-        int (*get_ro)(struct device *);
-        void (*setpower)(struct device *, unsigned int);
-        void (*exit)(struct device *, void *);
-        int gpio_card_detect;                   /* gpio detecting card insertion */
-        int gpio_card_ro;                       /* gpio detecting read only toggle */
-        bool gpio_card_ro_invert;               /* gpio ro is inverted */
-        int gpio_power;                         /* gpio powering up MMC bus */
-        bool gpio_power_invert;                 /* gpio power is inverted */
-};
-extern void pxa_set_mci_info(struct pxamci_platform_data *info);
-extern void pxa3xx_set_mci2_info(struct pxamci_platform_data *info);
-extern void pxa3xx_set_mci3_info(struct pxamci_platform_data *info);
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/ohci.h b/arch/arm/mach-pxa/include/mach/ohci.h
deleted file mode 100644
index 95b6e2a6e514..000000000000
--- a/arch/arm/mach-pxa/include/mach/ohci.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef ASMARM_ARCH_OHCI_H
-#define ASMARM_ARCH_OHCI_H
-struct device;
-struct pxaohci_platform_data {
-        int (*init)(struct device *);
-        void (*exit)(struct device *);
-        unsigned long flags;
-#define ENABLE_PORT1            (1 << 0)
-#define ENABLE_PORT2            (1 << 1)
-#define ENABLE_PORT3            (1 << 2)
-#define ENABLE_PORT_ALL         (ENABLE_PORT1 | ENABLE_PORT2 | ENABLE_PORT3)
-#define POWER_SENSE_LOW         (1 << 3)
-#define POWER_CONTROL_LOW       (1 << 4)
-#define NO_OC_PROTECTION        (1 << 5)
-#define OC_MODE_GLOBAL          (0 << 6)
-#define OC_MODE_PERPORT         (1 << 6)
-        int power_on_delay;     /* Power On to Power Good time - in ms
-                                 * HCD must wait for this duration before
-                                 * accessing a powered on port
-                                 */
-        int port_mode;
-#define PMM_NPS_MODE           1
-#define PMM_GLOBAL_MODE        2
-#define PMM_PERPORT_MODE       3
-        int power_budget;
-};
-extern void pxa_set_ohci_info(struct pxaohci_platform_data *info);
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/palmasoc.h b/arch/arm/mach-pxa/include/mach/palmasoc.h
deleted file mode 100644
index 58afb30d5298..000000000000
--- a/arch/arm/mach-pxa/include/mach/palmasoc.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _INCLUDE_PALMASOC_H_
-#define _INCLUDE_PALMASOC_H_
-struct palm27x_asoc_info {
-        int     jack_gpio;
-};
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/pata_pxa.h b/arch/arm/mach-pxa/include/mach/pata_pxa.h
deleted file mode 100644
index 6cf7df1d5830..000000000000
--- a/arch/arm/mach-pxa/include/mach/pata_pxa.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Generic PXA PATA driver
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2, or (at your option)
- *  any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; see the file COPYING.  If not, write to
- *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __MACH_PATA_PXA_H__
-#define __MACH_PATA_PXA_H__
-struct pata_pxa_pdata {
-        /* PXA DMA DREQ<0:2> pin */
-        uint32_t        dma_dreq;
-        /* Register shift */
-        uint32_t        reg_shift;
-        /* IRQ flags */
-        uint32_t        irq_flags;
-};
-#endif  /* __MACH_PATA_PXA_H__ */
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index 207ecb49a61b..f4d48d20754e 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -131,6 +131,7 @@
 #define AICSR           __REG(0x41340008)       /* Application Subsystem Interrupt Control/Status Register */
 #define CKENA           __REG(0x4134000C)       /* A Clock Enable Register */
 #define CKENB           __REG(0x41340010)       /* B Clock Enable Register */
+#define CKENC           __REG(0x41340024)       /* C Clock Enable Register */
 #define AC97_DIV        __REG(0x41340014)       /* AC97 clock divisor value register */
 #define ACCR_XPDIS              (1 << 31)       /* Core PLL Output Disable */
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h b/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h
deleted file mode 100644
index 9d82cb65ea56..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * PXA3xx U2D header
- *
- * Copyright (C) 2010 CompuLab Ltd.
- *
- * Igor Grinberg <grinberg@compulab.co.il>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __PXA310_U2D__
-#define __PXA310_U2D__
-#include <linux/usb/ulpi.h>
-struct pxa3xx_u2d_platform_data {
-#define ULPI_SER_6PIN   (1 << 0)
-#define ULPI_SER_3PIN   (1 << 1)
-        unsigned int ulpi_mode;
-        int (*init)(struct device *);
-        void (*exit)(struct device *);
-};
-/* Start PXA3xx U2D host */
-int pxa3xx_u2d_start_hc(struct usb_bus *host);
-/* Stop PXA3xx U2D host */
-void pxa3xx_u2d_stop_hc(struct usb_bus *host);
-extern void pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info);
-#endif /* __PXA310_U2D__ */
diff --git a/arch/arm/mach-pxa/include/mach/pxa930_rotary.h b/arch/arm/mach-pxa/include/mach/pxa930_rotary.h
deleted file mode 100644
index 053587caffdd..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxa930_rotary.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __ASM_ARCH_PXA930_ROTARY_H
-#define __ASM_ARCH_PXA930_ROTARY_H
-/* NOTE:
- *
- * rotary can be either interpreted as a ralative input event (e.g.
- * REL_WHEEL or REL_HWHEEL) or a specific key event (e.g. UP/DOWN
- * or LEFT/RIGHT), depending on if up_key & down_key are assigned
- * or rel_code is assigned a non-zero value. When all are non-zero,
- * up_key and down_key will be preferred.
- */
-struct pxa930_rotary_platform_data {
-        int     up_key;
-        int     down_key;
-        int     rel_code;
-};
-void __init pxa930_set_rotarykey_info(struct pxa930_rotary_platform_data *info);
-#endif /* __ASM_ARCH_PXA930_ROTARY_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa930_trkball.h b/arch/arm/mach-pxa/include/mach/pxa930_trkball.h
deleted file mode 100644
index 5e0789bc4729..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxa930_trkball.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __ASM_ARCH_PXA930_TRKBALL_H
-#define __ASM_ARCH_PXA930_TRKBALL_H
-struct pxa930_trkball_platform_data {
-        int x_filter;
-        int y_filter;
-};
-#endif /* __ASM_ARCH_PXA930_TRKBALL_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h
deleted file mode 100644
index 486b4c519ae2..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxafb.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- *  arch/arm/mach-pxa/include/mach/pxafb.h
- *
- *  Support for the xscale frame buffer.
- *
- *  Author:     Jean-Frederic Clere
- *  Created:    Sep 22, 2003
- *  Copyright:  jfclere@sinix.net
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#include <linux/fb.h>
-#include <mach/regs-lcd.h>
-/*
- * Supported LCD connections
- *
- * bits 0 - 3: for LCD panel type:
- *
- *   STN  - for passive matrix
- *   DSTN - for dual scan passive matrix
- *   TFT  - for active matrix
- *
- * bits 4 - 9 : for bus width
- * bits 10-17 : for AC Bias Pin Frequency
- * bit     18 : for output enable polarity
- * bit     19 : for pixel clock edge
- * bit     20 : for output pixel format when base is RGBT16
- */
-#define LCD_CONN_TYPE(_x)       ((_x) & 0x0f)
-#define LCD_CONN_WIDTH(_x)      (((_x) >> 4) & 0x1f)
-#define LCD_TYPE_MASK           0xf
-#define LCD_TYPE_UNKNOWN        0
-#define LCD_TYPE_MONO_STN       1
-#define LCD_TYPE_MONO_DSTN      2
-#define LCD_TYPE_COLOR_STN      3
-#define LCD_TYPE_COLOR_DSTN     4
-#define LCD_TYPE_COLOR_TFT      5
-#define LCD_TYPE_SMART_PANEL    6
-#define LCD_TYPE_MAX            7
-#define LCD_MONO_STN_4BPP       ((4  << 4) | LCD_TYPE_MONO_STN)
-#define LCD_MONO_STN_8BPP       ((8  << 4) | LCD_TYPE_MONO_STN)
-#define LCD_MONO_DSTN_8BPP      ((8  << 4) | LCD_TYPE_MONO_DSTN)
-#define LCD_COLOR_STN_8BPP      ((8  << 4) | LCD_TYPE_COLOR_STN)
-#define LCD_COLOR_DSTN_16BPP    ((16 << 4) | LCD_TYPE_COLOR_DSTN)
-#define LCD_COLOR_TFT_8BPP      ((8  << 4) | LCD_TYPE_COLOR_TFT)
-#define LCD_COLOR_TFT_16BPP     ((16 << 4) | LCD_TYPE_COLOR_TFT)
-#define LCD_COLOR_TFT_18BPP     ((18 << 4) | LCD_TYPE_COLOR_TFT)
-#define LCD_SMART_PANEL_8BPP    ((8  << 4) | LCD_TYPE_SMART_PANEL)
-#define LCD_SMART_PANEL_16BPP   ((16 << 4) | LCD_TYPE_SMART_PANEL)
-#define LCD_SMART_PANEL_18BPP   ((18 << 4) | LCD_TYPE_SMART_PANEL)
-#define LCD_AC_BIAS_FREQ(x)     (((x) & 0xff) << 10)
-#define LCD_BIAS_ACTIVE_HIGH    (0 << 18)
-#define LCD_BIAS_ACTIVE_LOW     (1 << 18)
-#define LCD_PCLK_EDGE_RISE      (0 << 19)
-#define LCD_PCLK_EDGE_FALL      (1 << 19)
-#define LCD_ALTERNATE_MAPPING   (1 << 20)
-/*
- * This structure describes the machine which we are running on.
- * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
- * of linux/drivers/video/pxafb.c
- */
-struct pxafb_mode_info {
-        u_long          pixclock;
-        u_short         xres;
-        u_short         yres;
-        u_char          bpp;
-        u_int           cmap_greyscale:1,
-                        depth:8,
-                        transparency:1,
-                        unused:22;
-        /* Parallel Mode Timing */
-        u_char          hsync_len;
-        u_char          left_margin;
-        u_char          right_margin;
-        u_char          vsync_len;
-        u_char          upper_margin;
-        u_char          lower_margin;
-        u_char          sync;
-        /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
-         * Note:
-         * 1. all parameters in nanosecond (ns)
-         * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
-         *    in pxa27x and pxa3xx, initialize them to the same value or
-         *    the larger one will be used
-         * 3. same to {rd,wr}_pulse_width
-         *
-         * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
-         * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
-         * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
-         */
-        unsigned        a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
-        unsigned        a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
-        unsigned        wr_pulse_width; /* L_PCLK_WR pulse width */
-        unsigned        rd_pulse_width; /* L_FCLK_RD pulse width */
-        unsigned        cmd_inh_time;   /* Command Inhibit time between two writes */
-        unsigned        op_hold_time;   /* Output Hold time from L_FCLK_RD negation */
-};
-struct pxafb_mach_info {
-        struct pxafb_mode_info *modes;
-        unsigned int num_modes;
-        unsigned int    lcd_conn;
-        unsigned long   video_mem_size;
-        u_int           fixed_modes:1,
-                        cmap_inverse:1,
-                        cmap_static:1,
-                        acceleration_enabled:1,
-                        unused:28;
-        /* The following should be defined in LCCR0
-         *      LCCR0_Act or LCCR0_Pas          Active or Passive
-         *      LCCR0_Sngl or LCCR0_Dual        Single/Dual panel
-         *      LCCR0_Mono or LCCR0_Color       Mono/Color
-         *      LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
-         *      LCCR0_DMADel(Tcpu) (optional)   DMA request delay
-         *
-         * The following should not be defined in LCCR0:
-         *      LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
-         *      LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
-         */
-        u_int           lccr0;
-        /* The following should be defined in LCCR3
-         *      LCCR3_OutEnH or LCCR3_OutEnL    Output enable polarity
-         *      LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
-         *      LCCR3_Acb(X)                    AB Bias pin frequency
-         *      LCCR3_DPC (optional)            Double Pixel Clock mode (untested)
-         *
-         * The following should not be defined in LCCR3
-         *      LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
-         */
-        u_int           lccr3;
-        /* The following should be defined in LCCR4
-         *      LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
-         *
-         * All other bits in LCCR4 should be left alone.
-         */
-        u_int           lccr4;
-        void (*pxafb_backlight_power)(int);
-        void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
-        void (*smart_update)(struct fb_info *);
-};
-void pxa_set_fb_info(struct device *, struct pxafb_mach_info *);
-unsigned long pxafb_get_hsync_time(struct device *dev);
-#ifdef CONFIG_FB_PXA_SMARTPANEL
-extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
-extern int pxafb_smart_flush(struct fb_info *info);
-#else
-static inline int pxafb_smart_queue(struct fb_info *info,
-                                    uint16_t *cmds, int n)
-{
-        return 0;
-}
-static inline int pxafb_smart_flush(struct fb_info *info)
-{
-        return 0;
-}
-#endif
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 5dae15ea6718..b6cc1816463e 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -17,6 +17,8 @@
 #include <linux/syscore_ops.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <asm/exception.h>
@@ -25,8 +27,6 @@
 #include "generic.h"
-#define IRQ_BASE                io_p2v(0x40d00000)
 #define ICIP                    (0x000)
 #define ICMR                    (0x004)
 #define ICLR                    (0x008)
@@ -48,22 +48,19 @@
 * This is for peripheral IRQs internal to the PXA chip.
 */
+static void __iomem *pxa_irq_base;
 static int pxa_internal_irq_nr;
+static bool cpu_has_ipr;
-static inline int cpu_has_ipr(void)
-{
-        return !cpu_is_pxa25x();
-}
 static inline void __iomem *irq_base(int i)
 {
-        static unsigned long phys_base[] = {
+        static unsigned long phys_base_offset[] = {
-                0x40d00000,
+                0x0,
-                0x40d0009c,
+                0x9c,
-                0x40d00130,
+                0x130,
        };
-        return io_p2v(phys_base[i]);
+        return pxa_irq_base + phys_base_offset[i];
 }
 void pxa_mask_irq(struct irq_data *d)
@@ -96,8 +93,8 @@ asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
        uint32_t icip, icmr, mask;
        do {
-                icip = __raw_readl(IRQ_BASE + ICIP);
+                icip = __raw_readl(pxa_irq_base + ICIP);
-                icmr = __raw_readl(IRQ_BASE + ICMR);
+                icmr = __raw_readl(pxa_irq_base + ICMR);
                mask = icip & icmr;
                if (mask == 0)
@@ -128,6 +125,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
        BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
        pxa_internal_irq_nr = irq_nr;
+        cpu_has_ipr = !cpu_is_pxa25x();
+        pxa_irq_base = io_p2v(0x40d00000);
        for (n = 0; n < irq_nr; n += 32) {
                void __iomem *base = irq_base(n >> 5);
@@ -136,8 +135,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
                __raw_writel(0, base + ICLR);   /* all IRQs are IRQ, not FIQ */
                for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
                        /* initialize interrupt priority */
-                        if (cpu_has_ipr())
+                        if (cpu_has_ipr)
-                                __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
+                                __raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i));
                        irq = PXA_IRQ(i);
                        irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
@@ -168,9 +167,9 @@ static int pxa_irq_suspend(void)
                __raw_writel(0, base + ICMR);
        }
-        if (cpu_has_ipr()) {
+        if (cpu_has_ipr) {
                for (i = 0; i < pxa_internal_irq_nr; i++)
-                        saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));
+                        saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i));
        }
        return 0;
@@ -187,11 +186,11 @@ static void pxa_irq_resume(void)
                __raw_writel(0, base + ICLR);
        }
-        if (cpu_has_ipr())
+        if (cpu_has_ipr)
                for (i = 0; i < pxa_internal_irq_nr; i++)
-                        __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
+                        __raw_writel(saved_ipr[i], pxa_irq_base + IPR(i));
-        __raw_writel(1, IRQ_BASE + ICCR);
+        __raw_writel(1, pxa_irq_base + ICCR);
 }
 #else
 #define pxa_irq_suspend         NULL
@@ -202,3 +201,93 @@ struct syscore_ops pxa_irq_syscore_ops = {
        .suspend        = pxa_irq_suspend,
        .resume         = pxa_irq_resume,
 };
+#ifdef CONFIG_OF
+static struct irq_domain *pxa_irq_domain;
+static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
+                       irq_hw_number_t hw)
+{
+        void __iomem *base = irq_base(hw / 32);
+        /* initialize interrupt priority */
+        if (cpu_has_ipr)
+                __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
+        irq_set_chip_and_handler(hw, &pxa_internal_irq_chip,
+                                 handle_level_irq);
+        irq_set_chip_data(hw, base);
+        set_irq_flags(hw, IRQF_VALID);
+        return 0;
+}
+static struct irq_domain_ops pxa_irq_ops = {
+        .map    = pxa_irq_map,
+        .xlate  = irq_domain_xlate_onecell,
+};
+static const struct of_device_id intc_ids[] __initconst = {
+        { .compatible = "marvell,pxa-intc", },
+        {}
+};
+void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
+{
+        struct device_node *node;
+        const struct of_device_id *of_id;
+        struct pxa_intc_conf *conf;
+        struct resource res;
+        int n, ret;
+        node = of_find_matching_node(NULL, intc_ids);
+        if (!node) {
+                pr_err("Failed to find interrupt controller in arch-pxa\n");
+                return;
+        }
+        of_id = of_match_node(intc_ids, node);
+        conf = of_id->data;
+        ret = of_property_read_u32(node, "marvell,intc-nr-irqs",
+                                   &pxa_internal_irq_nr);
+        if (ret) {
+                pr_err("Not found marvell,intc-nr-irqs property\n");
+                return;
+        }
+        ret = of_address_to_resource(node, 0, &res);
+        if (ret < 0) {
+                pr_err("No registers defined for node\n");
+                return;
+        }
+        pxa_irq_base = io_p2v(res.start);
+        if (of_find_property(node, "marvell,intc-priority", NULL))
+                cpu_has_ipr = 1;
+        ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0);
+        if (ret < 0) {
+                pr_err("Failed to allocate IRQ numbers\n");
+                return;
+        }
+        pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0,
+                                               &pxa_irq_ops, NULL);
+        if (!pxa_irq_domain)
+                panic("Unable to add PXA IRQ domain\n");
+        irq_set_default_host(pxa_irq_domain);
+        for (n = 0; n < pxa_internal_irq_nr; n += 32) {
+                void __iomem *base = irq_base(n >> 5);
+                __raw_writel(0, base + ICMR);   /* disable all IRQs */
+                __raw_writel(0, base + ICLR);   /* all IRQs are IRQ, not FIQ */
+        }
+        /* only unmasked interrupts kick us out of idle */
+        __raw_writel(1, irq_base(0) + ICCR);
+        pxa_internal_irq_chip.irq_set_wake = fn;
+}
+#endif /* CONFIG_OF */
diff --git a/arch/arm/mach-pxa/leds-idp.c b/arch/arm/mach-pxa/leds-idp.c
deleted file mode 100644
index 06b060025d11..000000000000
--- a/arch/arm/mach-pxa/leds-idp.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds-idp.c
- *
- * Copyright (C) 2000 John Dorsey <john+@cs.cmu.edu>
- *
- * Copyright (c) 2001 Jeff Sutherland <jeffs@accelent.com>
- *
- * Original (leds-footbridge.c) by Russell King
- *
- * Macros for actual LED manipulation should be in machine specific
- * files in this 'mach' directory.
- */
-#include <linux/init.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <mach/pxa25x.h>
-#include <mach/idp.h>
-#include "leds.h"
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-static unsigned int led_state;
-static unsigned int hw_led_state;
-void idp_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        switch (evt) {
-        case led_start:
-                hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
-                led_state = LED_STATE_ENABLED;
-                break;
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= IDP_HB_LED;
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~IDP_BUSY_LED;
-                break;
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= IDP_BUSY_LED;
-                break;
-#endif
-        case led_halted:
-                break;
-        case led_green_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= IDP_HB_LED;
-                break;
-        case led_green_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~IDP_HB_LED;
-                break;
-        case led_amber_on:
-                break;
-        case led_amber_off:
-                break;
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= IDP_BUSY_LED;
-                break;
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~IDP_BUSY_LED;
-                break;
-        default:
-                break;
-        }
-        if  (led_state & LED_STATE_ENABLED)
-                IDP_CPLD_LED_CONTROL = ( (IDP_CPLD_LED_CONTROL | IDP_LEDS_MASK) & ~hw_led_state);
-        else
-                IDP_CPLD_LED_CONTROL |= IDP_LEDS_MASK;
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-pxa/leds-lubbock.c b/arch/arm/mach-pxa/leds-lubbock.c
deleted file mode 100644
index 0bd85c884a7c..000000000000
--- a/arch/arm/mach-pxa/leds-lubbock.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds-lubbock.c
- *
- * Copyright (C) 2000 John Dorsey <john+@cs.cmu.edu>
- *
- * Copyright (c) 2001 Jeff Sutherland <jeffs@accelent.com>
- *
- * Original (leds-footbridge.c) by Russell King
- *
- * Major surgery on April 2004 by Nicolas Pitre for less global
- * namespace collision.  Mostly adapted the Mainstone version.
- */
-#include <linux/init.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <mach/pxa25x.h>
-#include <mach/lubbock.h>
-#include "leds.h"
-/*
- * 8 discrete leds available for general use:
- *
- * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
- * so be sure to not monkey with them here.
- */
-#define D28                     (1 << 0)
-#define D27                     (1 << 1)
-#define D26                     (1 << 2)
-#define D25                     (1 << 3)
-#define D24                     (1 << 4)
-#define D23                     (1 << 5)
-#define D22                     (1 << 6)
-#define D21                     (1 << 7)
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-static unsigned int led_state;
-static unsigned int hw_led_state;
-void lubbock_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        switch (evt) {
-        case led_start:
-                hw_led_state = 0;
-                led_state = LED_STATE_ENABLED;
-                break;
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                hw_led_state ^= D26;
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                hw_led_state &= ~D27;
-                break;
-        case led_idle_end:
-                hw_led_state |= D27;
-                break;
-#endif
-        case led_halted:
-                break;
-        case led_green_on:
-                hw_led_state |= D21;
-                break;
-        case led_green_off:
-                hw_led_state &= ~D21;
-                break;
-        case led_amber_on:
-                hw_led_state |= D22;
-                break;
-        case led_amber_off:
-                hw_led_state &= ~D22;
-                break;
-        case led_red_on:
-                hw_led_state |= D23;
-                break;
-        case led_red_off:
-                hw_led_state &= ~D23;
-                break;
-        default:
-                break;
-        }
-        if  (led_state & LED_STATE_ENABLED)
-                LUB_DISC_BLNK_LED = (LUB_DISC_BLNK_LED | 0xff) & ~hw_led_state;
-        else
-                LUB_DISC_BLNK_LED |= 0xff;
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-pxa/leds-mainstone.c b/arch/arm/mach-pxa/leds-mainstone.c
deleted file mode 100644
index 4058ab340fe6..000000000000
--- a/arch/arm/mach-pxa/leds-mainstone.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds-mainstone.c
- *
- * Author:     Nicolas Pitre
- * Created:    Nov 05, 2002
- * Copyright:  MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <mach/pxa27x.h>
-#include <mach/mainstone.h>
-#include "leds.h"
-/* 8 discrete leds available for general use: */
-#define D28                     (1 << 0)
-#define D27                     (1 << 1)
-#define D26                     (1 << 2)
-#define D25                     (1 << 3)
-#define D24                     (1 << 4)
-#define D23                     (1 << 5)
-#define D22                     (1 << 6)
-#define D21                     (1 << 7)
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-static unsigned int led_state;
-static unsigned int hw_led_state;
-void mainstone_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        switch (evt) {
-        case led_start:
-                hw_led_state = 0;
-                led_state = LED_STATE_ENABLED;
-                break;
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                hw_led_state ^= D26;
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                hw_led_state &= ~D27;
-                break;
-        case led_idle_end:
-                hw_led_state |= D27;
-                break;
-#endif
-        case led_halted:
-                break;
-        case led_green_on:
-                hw_led_state |= D21;
-                break;
-        case led_green_off:
-                hw_led_state &= ~D21;
-                break;
-        case led_amber_on:
-                hw_led_state |= D22;
-                break;
-        case led_amber_off:
-                hw_led_state &= ~D22;
-                break;
-        case led_red_on:
-                hw_led_state |= D23;
-                break;
-        case led_red_off:
-                hw_led_state &= ~D23;
-                break;
-        default:
-                break;
-        }
-        if  (led_state & LED_STATE_ENABLED)
-                MST_LEDCTRL = (MST_LEDCTRL | 0xff) & ~hw_led_state;
-        else
-                MST_LEDCTRL |= 0xff;
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-pxa/leds.c b/arch/arm/mach-pxa/leds.c
deleted file mode 100644
index bbe4d5f6afaa..000000000000
--- a/arch/arm/mach-pxa/leds.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds.c
- *
- * xscale LEDs dispatcher
- *
- * Copyright (C) 2001 Nicolas Pitre
- *
- * Copyright (c) 2001 Jeff Sutherland, Accelent Systems Inc.
- */
-#include <linux/compiler.h>
-#include <linux/init.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-#include "leds.h"
-static int __init
-pxa_leds_init(void)
-{
-        if (machine_is_lubbock())
-                leds_event = lubbock_leds_event;
-        if (machine_is_mainstone())
-                leds_event = mainstone_leds_event;
-        if (machine_is_pxa_idp())
-                leds_event = idp_leds_event;
-        leds_event(led_start);
-        return 0;
-}
-core_initcall(pxa_leds_init);
diff --git a/arch/arm/mach-pxa/leds.h b/arch/arm/mach-pxa/leds.h
deleted file mode 100644
index 7f0dfe01345a..000000000000
--- a/arch/arm/mach-pxa/leds.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-pxa/leds.h
- *
- * Copyright (c) 2001 Jeff Sutherland, Accelent Systems Inc.
- *
- * blinky lights for various PXA-based systems:
- *
- */
-extern void idp_leds_event(led_event_t evt);
-extern void lubbock_leds_event(led_event_t evt);
-extern void mainstone_leds_event(led_event_t evt);
-extern void trizeps4_leds_event(led_event_t evt);
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 1fb86edb857c..402874f9021f 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -42,11 +42,11 @@
 #include <asm/mach/irq.h>
 #include <mach/pxa300.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/littleton.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index cee9ce2fc0b5..1a63eaa89867 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -41,10 +41,10 @@
 #include <mach/pxa27x.h>
 #include <mach/lpd270.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/smemc.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 0ca0db787903..553056d9a3c5 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/syscore_ops.h>
 #include <linux/major.h>
@@ -23,6 +24,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/smc91x.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
@@ -46,9 +49,9 @@
 #include <mach/audio.h>
 #include <mach/lubbock.h>
 #include <mach/udc.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/pm.h>
 #include <mach/smemc.h>
@@ -549,6 +552,98 @@ static void __init lubbock_map_io(void)
        PCFR |= PCFR_OPDE;
 }
+/*
+ * Driver for the 8 discrete LEDs available for general use:
+ * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
+ * so be sure to not monkey with them here.
+ */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct lubbock_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} lubbock_leds[] = {
+        { "lubbock:D28", "default-on", },
+        { "lubbock:D27", "cpu0", },
+        { "lubbock:D26", "heartbeat" },
+        { "lubbock:D25", },
+        { "lubbock:D24", },
+        { "lubbock:D23", },
+        { "lubbock:D22", },
+        { "lubbock:D21", },
+};
+static void lubbock_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
+{
+        struct lubbock_led *led = container_of(cdev,
+                                         struct lubbock_led, cdev);
+        u32 reg = LUB_DISC_BLNK_LED;
+        if (b != LED_OFF)
+                reg |= led->mask;
+        else
+                reg &= ~led->mask;
+        LUB_DISC_BLNK_LED = reg;
+}
+static enum led_brightness lubbock_led_get(struct led_classdev *cdev)
+{
+        struct lubbock_led *led = container_of(cdev,
+                                         struct lubbock_led, cdev);
+        u32 reg = LUB_DISC_BLNK_LED;
+        return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
+static int __init lubbock_leds_init(void)
+{
+        int i;
+        if (!machine_is_lubbock())
+                return -ENODEV;
+        /* All ON */
+        LUB_DISC_BLNK_LED |= 0xff;
+        for (i = 0; i < ARRAY_SIZE(lubbock_leds); i++) {
+                struct lubbock_led *led;
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+                led->cdev.name = lubbock_leds[i].name;
+                led->cdev.brightness_set = lubbock_led_set;
+                led->cdev.brightness_get = lubbock_led_get;
+                led->cdev.default_trigger = lubbock_leds[i].trigger;
+                led->mask = BIT(i);
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+        return 0;
+}
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(lubbock_leds_init);
+#endif
 MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
        /* Maintainer: MontaVista Software Inc. */
        .map_io         = lubbock_map_io,
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 39561dcf65f2..f7922404d941 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -38,10 +38,10 @@
 #include <mach/pxa27x.h>
 #include <mach/magician.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 1aebaf719462..f27a61ee7ac7 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -28,6 +28,8 @@
 #include <linux/pwm_backlight.h>
 #include <linux/smc91x.h>
 #include <linux/i2c/pxa-i2c.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -45,11 +47,11 @@
 #include <mach/pxa27x.h>
 #include <mach/mainstone.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/smemc.h>
 #include "generic.h"
@@ -613,6 +615,98 @@ static void __init mainstone_map_io(void)
        PCFR = 0x66;
 }
+/*
+ * Driver for the 8 discrete LEDs available for general use:
+ * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
+ * so be sure to not monkey with them here.
+ */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct mainstone_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} mainstone_leds[] = {
+        { "mainstone:D28", "default-on", },
+        { "mainstone:D27", "cpu0", },
+        { "mainstone:D26", "heartbeat" },
+        { "mainstone:D25", },
+        { "mainstone:D24", },
+        { "mainstone:D23", },
+        { "mainstone:D22", },
+        { "mainstone:D21", },
+};
+static void mainstone_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
+{
+        struct mainstone_led *led = container_of(cdev,
+                                         struct mainstone_led, cdev);
+        u32 reg = MST_LEDCTRL;
+        if (b != LED_OFF)
+                reg |= led->mask;
+        else
+                reg &= ~led->mask;
+        MST_LEDCTRL = reg;
+}
+static enum led_brightness mainstone_led_get(struct led_classdev *cdev)
+{
+        struct mainstone_led *led = container_of(cdev,
+                                         struct mainstone_led, cdev);
+        u32 reg = MST_LEDCTRL;
+        return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
+static int __init mainstone_leds_init(void)
+{
+        int i;
+        if (!machine_is_mainstone())
+                return -ENODEV;
+        /* All ON */
+        MST_LEDCTRL |= 0xff;
+        for (i = 0; i < ARRAY_SIZE(mainstone_leds); i++) {
+                struct mainstone_led *led;
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+                led->cdev.name = mainstone_leds[i].name;
+                led->cdev.brightness_set = mainstone_led_set;
+                led->cdev.brightness_get = mainstone_led_get;
+                led->cdev.default_trigger = mainstone_leds[i].trigger;
+                led->mask = BIT(i);
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+        return 0;
+}
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(mainstone_leds_init);
+#endif
 MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
        /* Maintainer: MontaVista Software Inc. */
        .atag_offset    = 0x100,        /* BLOB boot parameter setting */
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index bf99022b021f..2831308dba68 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -46,12 +46,12 @@
 #include <mach/pxa27x.h>
 #include <mach/regs-rtc.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/udc.h>
 #include <mach/pxa27x-udc.h>
-#include <mach/camera.h>
+#include <linux/platform_data/camera-pxa.h>
 #include <mach/audio.h>
 #include <mach/smemc.h>
 #include <media/soc_camera.h>
diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c
index 83570a79e7d2..d04ed4961e60 100644
--- a/arch/arm/mach-pxa/mxm8x10.c
+++ b/arch/arm/mach-pxa/mxm8x10.c
@@ -24,11 +24,11 @@
 #include <linux/gpio.h>
 #include <linux/i2c/pxa-i2c.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pxa320.h>
 #include <mach/mxm8x10.h>
diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c
index dad71cfa34c8..17d4c53017ca 100644
--- a/arch/arm/mach-pxa/palm27x.c
+++ b/arch/arm/mach-pxa/palm27x.c
@@ -29,11 +29,11 @@
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
 #include <mach/udc.h>
-#include <mach/palmasoc.h>
+#include <linux/platform_data/asoc-palm27x.h>
 #include <mach/palm27x.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 31e0433d83ba..8bcc96e3b0db 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -35,11 +35,11 @@
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <mach/palmld.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
-#include <mach/palmasoc.h>
+#include <linux/platform_data/asoc-palm27x.h>
 #include <mach/palm27x.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 0f6bd4fcfa3b..5ca7b904a30e 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -36,12 +36,12 @@
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <mach/palmt5.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/udc.h>
-#include <mach/palmasoc.h>
+#include <linux/platform_data/asoc-palm27x.h>
 #include <mach/palm27x.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index e2d97eed07a7..ca924cfedfc0 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -34,9 +34,9 @@
 #include <mach/pxa25x.h>
 #include <mach/audio.h>
 #include <mach/palmtc.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
 #include <mach/udc.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index c054827c567f..32e0d7998355 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -34,11 +34,11 @@
 #include <mach/pxa25x.h>
 #include <mach/audio.h>
 #include <mach/palmte2.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
 #include <mach/udc.h>
-#include <mach/palmasoc.h>
+#include <linux/platform_data/asoc-palm27x.h>
 #include "generic.h"
 #include "devices.h"
@@ -105,6 +105,7 @@ static struct pxamci_platform_data palmte2_mci_platform_data = {
        .gpio_power             = GPIO_NR_PALMTE2_SD_POWER,
 };
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 /******************************************************************************
 * GPIO keys
 ******************************************************************************/
@@ -132,6 +133,7 @@ static struct platform_device palmte2_pxa_keys = {
                .platform_data = &palmte2_pxa_keys_data,
        },
 };
+#endif
 /******************************************************************************
 * Backlight
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index fbdebee39a53..3f3c48f2f7ce 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -35,15 +35,15 @@
 #include <mach/pxa27x-udc.h>
 #include <mach/audio.h>
 #include <mach/palmtreo.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/udc.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pxa2xx-regs.h>
-#include <mach/palmasoc.h>
+#include <linux/platform_data/asoc-palm27x.h>
-#include <mach/camera.h>
+#include <linux/platform_data/camera-pxa.h>
 #include <mach/palm27x.h>
 #include <sound/pxa2xx-lib.h>
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 0da35dccfd89..8b4366628a12 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -40,12 +40,12 @@
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <mach/palmtx.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/udc.h>
-#include <mach/palmasoc.h>
+#include <linux/platform_data/asoc-palm27x.h>
 #include <mach/palm27x.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index a97b59965bb9..8cdd4f58e253 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -40,16 +40,16 @@
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <mach/palmz72.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/udc.h>
-#include <mach/palmasoc.h>
+#include <linux/platform_data/asoc-palm27x.h>
 #include <mach/palm27x.h>
 #include <mach/pm.h>
-#include <mach/camera.h>
+#include <linux/platform_data/camera-pxa.h>
 #include <media/soc_camera.h>
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index cb723e84bc27..113c57a03565 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -28,14 +28,14 @@
 #include <media/soc_camera.h>
-#include <mach/camera.h>
+#include <linux/platform_data/camera-pxa.h>
 #include <asm/mach/map.h>
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pcm990_baseboard.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 89d98c832189..2910bb935c75 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -40,11 +40,11 @@
 #include <asm/mach/irq.h>
 #include <mach/pxa25x.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/udc.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
 #include <mach/poodle.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <asm/hardware/scoop.h>
 #include <asm/hardware/locomo.h>
diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c
new file mode 100644
index 000000000000..c9192cea0033
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa-dt.c
@@ -0,0 +1,63 @@
+/*
+ *  linux/arch/arm/mach-pxa/pxa-dt.c
+ *
+ *  Copyright (C) 2012 Daniel Mack
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+#include <mach/pxa3xx.h>
+#include "generic.h"
+#ifdef CONFIG_PXA3xx
+extern void __init pxa3xx_dt_init_irq(void);
+static const struct of_dev_auxdata pxa3xx_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x40100000, "pxa2xx-uart.0", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x40200000, "pxa2xx-uart.1", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x40700000, "pxa2xx-uart.2", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x41600000, "pxa2xx-uart.3", NULL),
+        OF_DEV_AUXDATA("marvell,pxa-mmc",       0x41100000, "pxa2xx-mci.0", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-gpio",         0x40e00000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("marvell,pxa-ohci",      0x4c000000, "pxa27x-ohci", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-i2c",          0x40301680, "pxa2xx-i2c.0", NULL),
+        OF_DEV_AUXDATA("mrvl,pwri2c",           0x40f500c0, "pxa3xx-i2c.1", NULL),
+        OF_DEV_AUXDATA("marvell,pxa3xx-nand",   0x43100000, "pxa3xx-nand", NULL),
+        {}
+};
+static void __init pxa3xx_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             pxa3xx_auxdata_lookup, NULL);
+}
+static const char *pxa3xx_dt_board_compat[] __initdata = {
+        "marvell,pxa300",
+        "marvell,pxa310",
+        "marvell,pxa320",
+        NULL,
+};
+#endif
+#ifdef CONFIG_PXA3xx
+DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)")
+        .map_io         = pxa3xx_map_io,
+        .init_irq       = pxa3xx_dt_init_irq,
+        .handle_irq     = pxa3xx_handle_irq,
+        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
+        .init_machine   = pxa3xx_dt_init,
+        .dt_compat      = pxa3xx_dt_board_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 4726c246dcdc..8047ee0effc5 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -30,7 +30,7 @@
 #include <mach/irqs.h>
 #include <mach/pxa27x.h>
 #include <mach/reset.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pm.h>
 #include <mach/dma.h>
 #include <mach/smemc.h>
diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c
index f8ec85450c42..447dcbb22f6f 100644
--- a/arch/arm/mach-pxa/pxa2xx.c
+++ b/arch/arm/mach-pxa/pxa2xx.c
@@ -19,7 +19,7 @@
 #include <mach/pxa2xx-regs.h>
 #include <mach/mfp-pxa25x.h>
 #include <mach/reset.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
 void pxa2xx_clear_reset_status(unsigned int mask)
 {
diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c
index 5ead6d480c6d..7dbe3ccf1993 100644
--- a/arch/arm/mach-pxa/pxa3xx-ulpi.c
+++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c
@@ -27,7 +27,7 @@
 #include <mach/hardware.h>
 #include <mach/regs-u2d.h>
-#include <mach/pxa3xx-u2d.h>
+#include <linux/platform_data/usb-pxa3xx-ulpi.h>
 struct pxa3xx_u2d_ulpi {
        struct clk              *clk;
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index dffb7e813d98..656a1bb16d14 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -19,6 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/syscore_ops.h>
 #include <linux/i2c/pxa-i2c.h>
@@ -27,7 +28,7 @@
 #include <mach/hardware.h>
 #include <mach/pxa3xx-regs.h>
 #include <mach/reset.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pm.h>
 #include <mach/dma.h>
 #include <mach/smemc.h>
@@ -40,6 +41,8 @@
 #define PECR_IE(n)      ((1 << ((n) * 2)) << 28)
 #define PECR_IS(n)      ((1 << ((n) * 2)) << 29)
+extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
@@ -382,7 +385,7 @@ static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
        pxa_ext_wakeup_chip.irq_set_wake = fn;
 }
-void __init pxa3xx_init_irq(void)
+static void __init __pxa3xx_init_irq(void)
 {
        /* enable CP6 access */
        u32 value;
@@ -390,10 +393,23 @@ void __init pxa3xx_init_irq(void)
        value |= (1 << 6);
        __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
-        pxa_init_irq(56, pxa3xx_set_wake);
        pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
 }
+void __init pxa3xx_init_irq(void)
+{
+        __pxa3xx_init_irq();
+        pxa_init_irq(56, pxa3xx_set_wake);
+}
+#ifdef CONFIG_OF
+void __init pxa3xx_dt_init_irq(void)
+{
+        __pxa3xx_init_irq();
+        pxa_dt_irq_init(pxa3xx_set_wake);
+}
+#endif  /* CONFIG_OF */
 static struct map_desc pxa3xx_io_desc[] __initdata = {
        {       /* Mem Ctl */
                .virtual        = (unsigned long)SMEMC_VIRT,
@@ -466,7 +482,8 @@ static int __init pxa3xx_init(void)
                register_syscore_ops(&pxa3xx_mfp_syscore_ops);
                register_syscore_ops(&pxa3xx_clock_syscore_ops);
-                ret = platform_add_devices(devices, ARRAY_SIZE(devices));
+                if (!of_have_populated_dt())
+                        ret = platform_add_devices(devices, ARRAY_SIZE(devices));
        }
        return ret;
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index d89d87ae144c..25b08bfa997b 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -49,10 +49,10 @@
 #include <asm/mach/arch.h>
 #include <mach/pxa300.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index 86c95a5d8533..08d87a5d2639 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -32,7 +32,7 @@
 #include <asm/mach/flash.h>
 #include <mach/pxa930.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index bdf4cb88ca0a..ec55c575ed19 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -55,7 +55,6 @@
 #ifdef CONFIG_PM
 static int sharpsl_off_charge_battery(void);
 static int sharpsl_check_battery_voltage(void);
-static int sharpsl_fatal_check(void);
 #endif
 static int sharpsl_check_battery_temp(void);
 static int sharpsl_ac_check(void);
@@ -579,8 +578,8 @@ static int sharpsl_ac_check(void)
 static int sharpsl_pm_suspend(struct platform_device *pdev, pm_message_t state)
 {
        sharpsl_pm.flags |= SHARPSL_SUSPENDED;
-        flush_delayed_work_sync(&toggle_charger);
+        flush_delayed_work(&toggle_charger);
-        flush_delayed_work_sync(&sharpsl_bat);
+        flush_delayed_work(&sharpsl_bat);
        if (sharpsl_pm.charge_mode == CHRG_ON)
                sharpsl_pm.flags |= SHARPSL_DO_OFFLINE_CHRG;
@@ -686,53 +685,6 @@ static int corgi_pxa_pm_enter(suspend_state_t state)
        return 0;
 }
-/*
- * Check for fatal battery errors
- * Fatal returns -1
- */
-static int sharpsl_fatal_check(void)
-{
-        int buff[5], temp, i, acin;
-        dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check entered\n");
-        /* Check AC-Adapter */
-        acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
-        if (acin && (sharpsl_pm.charge_mode == CHRG_ON)) {
-                sharpsl_pm.machinfo->charge(0);
-                udelay(100);
-                sharpsl_pm.machinfo->discharge(1);      /* enable discharge */
-                mdelay(SHARPSL_WAIT_DISCHARGE_ON);
-        }
-        if (sharpsl_pm.machinfo->discharge1)
-                sharpsl_pm.machinfo->discharge1(1);
-        /* Check battery : check inserting battery ? */
-        for (i = 0; i < 5; i++) {
-                buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
-                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT);
-        }
-        if (sharpsl_pm.machinfo->discharge1)
-                sharpsl_pm.machinfo->discharge1(0);
-        if (acin && (sharpsl_pm.charge_mode == CHRG_ON)) {
-                udelay(100);
-                sharpsl_pm.machinfo->charge(1);
-                sharpsl_pm.machinfo->discharge(0);
-        }
-        temp = get_select_val(buff);
-        dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %ld\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT));
-        if ((acin && (temp < sharpsl_pm.machinfo->fatal_acin_volt)) ||
-                        (!acin && (temp < sharpsl_pm.machinfo->fatal_noacin_volt)))
-                return -1;
-        return 0;
-}
 static int sharpsl_off_charge_error(void)
 {
        dev_err(sharpsl_pm.dev, "Offline Charger: Error occurred.\n");
@@ -879,7 +831,7 @@ static const struct platform_suspend_ops sharpsl_pm_ops = {
 static int __devinit sharpsl_pm_probe(struct platform_device *pdev)
 {
-        int ret;
+        int ret, irq;
        if (!pdev->dev.platform_data)
                return -EINVAL;
@@ -907,24 +859,28 @@ static int __devinit sharpsl_pm_probe(struct platform_device *pdev)
        gpio_direction_input(sharpsl_pm.machinfo->gpio_batlock);
        /* Register interrupt handlers */
-        if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) {
+        irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_acin);
-                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin));
+        if (request_irq(irq, sharpsl_ac_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) {
+                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
        }
-        if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) {
+        irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_batlock);
-                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock));
+        if (request_irq(irq, sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) {
+                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
        }
        if (sharpsl_pm.machinfo->gpio_fatal) {
-                if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) {
+                irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_fatal);
-                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal));
+                if (request_irq(irq, sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) {
+                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
                }
        }
        if (sharpsl_pm.machinfo->batfull_irq) {
                /* Register interrupt handler. */
-                if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) {
+                irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_batfull);
-                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull));
+                if (request_irq(irq, sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) {
+                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq);
                }
        }
@@ -953,14 +909,14 @@ static int sharpsl_pm_remove(struct platform_device *pdev)
        led_trigger_unregister_simple(sharpsl_charge_led_trigger);
-        free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr);
+        free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr);
-        free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr);
+        free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr);
        if (sharpsl_pm.machinfo->gpio_fatal)
-                free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr);
+                free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr);
        if (sharpsl_pm.machinfo->batfull_irq)
-                free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr);
+                free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr);
        gpio_free(sharpsl_pm.machinfo->gpio_batlock);
        gpio_free(sharpsl_pm.machinfo->gpio_batfull);
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 363d91b44ecb..2073f0e6db0d 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -41,10 +41,10 @@
 #include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/reset.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/spitz.h>
 #include <mach/sharpsl_pm.h>
 #include <mach/smemc.h>
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 30b1b0b3c7f7..456560b5aad4 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -44,7 +44,7 @@
 #include <asm/mach/flash.h>
 #include <mach/pxa27x.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/udc.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/smemc.h>
@@ -52,7 +52,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/pxa2xx_spi.h>
 #include <linux/mfd/da903x.h>
-#include <linux/sht15.h>
+#include <linux/platform_data/sht15.h>
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 736bfdc50ee6..1a25f8a7b0ce 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -24,8 +24,8 @@
 #include <asm/mach/arch.h>
 #include <mach/pxa930.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 4d4eb60bad1e..233629edf7ee 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -42,8 +42,8 @@
 #include <mach/pxa25x.h>
 #include <mach/reset.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/udc.h>
 #include <mach/tosa_bt.h>
 #include <mach/audio.h>
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 166dd32cc1d3..fbbcbed4d1d4 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -43,10 +43,10 @@
 #include <mach/pxa27x.h>
 #include <mach/trizeps4.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/irda.h>
+#include <linux/platform_data/irda-pxaficp.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/smemc.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 130379fb9d0f..c773e4dded64 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -48,9 +48,9 @@
 #include <mach/pxa25x.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/regs-uart.h>
-#include <mach/arcom-pcmcia.h>
+#include <linux/platform_data/pcmcia-pxa2xx_viper.h>
 #include <mach/viper.h>
 #include <asm/setup.h>
@@ -768,8 +768,7 @@ static unsigned long viper_tpm;
 static int __init viper_tpm_setup(char *str)
 {
-        strict_strtoul(str, 10, &viper_tpm);
+        return strict_strtoul(str, 10, &viper_tpm) >= 0;
-        return 1;
 }
 __setup("tpm=", viper_tpm_setup);
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index e1740acd15f1..491b6c9a2a9b 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -33,12 +33,12 @@
 #include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <mach/vpac270.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/udc.h>
-#include <mach/pata_pxa.h>
+#include <linux/platform_data/ata-pxa.h>
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index b9320cb8a11f..97529face7aa 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -37,9 +37,9 @@
 #include <mach/pxa27x.h>
 #include <mach/mfp-pxa27x.h>
 #include <mach/z2.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
 #include <mach/pm.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index af3d4f7646d7..abd3aa145083 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -38,14 +38,14 @@
 #include <mach/pxa27x.h>
 #include <mach/regs-uart.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/udc.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/pm.h>
 #include <mach/audio.h>
-#include <mach/arcom-pcmcia.h>
+#include <linux/platform_data/pcmcia-pxa2xx_viper.h>
 #include <mach/zeus.h>
 #include <mach/smemc.h>
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 98eec80623e3..226279fac9d4 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -26,12 +26,12 @@
 #include <asm/mach/arch.h>
 #include <mach/pxa3xx.h>
 #include <mach/audio.h>
-#include <mach/pxafb.h>
+#include <linux/platform_data/video-pxafb.h>
 #include <mach/zylonite.h>
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-pxamci.h>
-#include <mach/ohci.h>
+#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <plat/pxa27x_keypad.h>
+#include <linux/platform_data/keypad-pxa27x.h>
-#include <plat/pxa3xx_nand.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 45868bb43cbd..682467480588 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -30,12 +30,10 @@
 #include <linux/ata_platform.h>
 #include <linux/amba/mmci.h>
 #include <linux/gfp.h>
-#include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst.h>
@@ -226,115 +224,10 @@ struct mmci_platform_data realview_mmc1_plat_data = {
        .cd_invert      = true,
 };
-/*
- * Clock handling
- */
-static const struct icst_params realview_oscvco_params = {
-        .ref            = 24000000,
-        .vco_max        = ICST307_VCO_MAX,
-        .vco_min        = ICST307_VCO_MIN,
-        .vd_min         = 4 + 8,
-        .vd_max         = 511 + 8,
-        .rd_min         = 1 + 2,
-        .rd_max         = 127 + 2,
-        .s2div          = icst307_s2div,
-        .idx2s          = icst307_idx2s,
-};
-static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
-{
-        void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
-        u32 val;
-        val = readl(clk->vcoreg) & ~0x7ffff;
-        val |= vco.v | (vco.r << 9) | (vco.s << 16);
-        writel(0xa05f, sys_lock);
-        writel(val, clk->vcoreg);
-        writel(0, sys_lock);
-}
-static const struct clk_ops oscvco_clk_ops = {
-        .round  = icst_clk_round,
-        .set    = icst_clk_set,
-        .setvco = realview_oscvco_set,
-};
-static struct clk oscvco_clk = {
-        .ops    = &oscvco_clk_ops,
-        .params = &realview_oscvco_params,
-};
-/*
- * These are fixed clocks.
- */
-static struct clk ref24_clk = {
-        .rate   = 24000000,
-};
-static struct clk sp804_clk = {
-        .rate   = 1000000,
-};
-static struct clk dummy_apb_pclk;
-static struct clk_lookup lookups[] = {
-        {       /* Bus clock */
-                .con_id         = "apb_pclk",
-                .clk            = &dummy_apb_pclk,
-        }, {    /* UART0 */
-                .dev_id         = "dev:uart0",
-                .clk            = &ref24_clk,
-        }, {    /* UART1 */
-                .dev_id         = "dev:uart1",
-                .clk            = &ref24_clk,
-        }, {    /* UART2 */
-                .dev_id         = "dev:uart2",
-                .clk            = &ref24_clk,
-        }, {    /* UART3 */
-                .dev_id         = "fpga:uart3",
-                .clk            = &ref24_clk,
-        }, {    /* UART3 is on the dev chip in PB1176 */
-                .dev_id         = "dev:uart3",
-                .clk            = &ref24_clk,
-        }, {    /* UART4 only exists in PB1176 */
-                .dev_id         = "fpga:uart4",
-                .clk            = &ref24_clk,
-        }, {    /* KMI0 */
-                .dev_id         = "fpga:kmi0",
-                .clk            = &ref24_clk,
-        }, {    /* KMI1 */
-                .dev_id         = "fpga:kmi1",
-                .clk            = &ref24_clk,
-        }, {    /* MMC0 */
-                .dev_id         = "fpga:mmc0",
-                .clk            = &ref24_clk,
-        }, {    /* CLCD is in the PB1176 and EB DevChip */
-                .dev_id         = "dev:clcd",
-                .clk            = &oscvco_clk,
-        }, {    /* PB:CLCD */
-                .dev_id         = "issp:clcd",
-                .clk            = &oscvco_clk,
-        }, {    /* SSP */
-                .dev_id         = "dev:ssp0",
-                .clk            = &ref24_clk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .clk            = &sp804_clk,
-        },
-};
 void __init realview_init_early(void)
 {
        void __iomem *sys = __io_address(REALVIEW_SYS_BASE);
-        if (machine_is_realview_pb1176())
-                oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET;
-        else
-                oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET;
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
        versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000);
 }
@@ -436,44 +329,6 @@ struct clcd_board clcd_plat_data = {
        .remove         = versatile_clcd_remove_dma,
 };
-#ifdef CONFIG_LEDS
-#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
-void realview_leds_event(led_event_t ledevt)
-{
-        unsigned long flags;
-        u32 val;
-        u32 led = 1 << smp_processor_id();
-        local_irq_save(flags);
-        val = readl(VA_LEDS_BASE);
-        switch (ledevt) {
-        case led_idle_start:
-                val = val & ~led;
-                break;
-        case led_idle_end:
-                val = val | led;
-                break;
-        case led_timer:
-                val = val ^ REALVIEW_SYS_LED7;
-                break;
-        case led_halted:
-                val = 0;
-                break;
-        default:
-                break;
-        }
-        writel(val, VA_LEDS_BASE);
-        local_irq_restore(flags);
-}
-#endif  /* CONFIG_LEDS */
 /*
 * Where is the timer (VA)?
 */
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index f8f2c0ac4c01..602ca5ec52c5 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -26,7 +26,6 @@
 #include <linux/io.h>
 #include <asm/setup.h>
-#include <asm/leds.h>
 #define APB_DEVICE(name, busid, base, plat)                     \
 static AMBA_APB_DEVICE(name, busid, 0, REALVIEW_##base##_BASE, base##_IRQ, plat)
@@ -47,7 +46,6 @@ extern void __iomem *timer1_va_base;
 extern void __iomem *timer2_va_base;
 extern void __iomem *timer3_va_base;
-extern void realview_leds_event(led_event_t ledevt);
 extern void realview_timer_init(unsigned int timer_irq);
 extern int realview_flash_register(struct resource *res, u32 num);
 extern int realview_eth_register(const char *name, struct resource *res);
@@ -56,4 +54,7 @@ extern void realview_init_early(void);
 extern void realview_fixup(struct tag *tags, char **from,
                           struct meminfo *meminfo);
+extern struct smp_operations realview_smp_ops;
+extern void realview_cpu_die(unsigned int cpu);
 #endif
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
index 57d9efba2956..53818e5cd3ad 100644
--- a/arch/arm/mach-realview/hotplug.c
+++ b/arch/arm/mach-realview/hotplug.c
@@ -16,8 +16,6 @@
 #include <asm/cp15.h>
 #include <asm/smp_plat.h>
-extern volatile int pen_release;
 static inline void cpu_enter_lowpower(void)
 {
        unsigned int v;
@@ -89,17 +87,12 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
        }
 }
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
 /*
 * platform-specific code to shutdown a CPU
 *
 * Called with IRQs disabled
 */
-void platform_cpu_die(unsigned int cpu)
+void __ref realview_cpu_die(unsigned int cpu)
 {
        int spurious = 0;
@@ -118,12 +111,3 @@ void platform_cpu_die(unsigned int cpu)
        if (spurious)
                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 }
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-realview/include/mach/clkdev.h b/arch/arm/mach-realview/include/mach/clkdev.h
deleted file mode 100644
index e58d0771b64e..000000000000
--- a/arch/arm/mach-realview/include/mach/clkdev.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-#include <plat/clock.h>
-struct clk {
-        unsigned long           rate;
-        const struct clk_ops    *ops;
-        const struct icst_params *params;
-        void __iomem            *vcoreg;
-};
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-#endif
diff --git a/arch/arm/mach-realview/include/mach/gpio.h b/arch/arm/mach-realview/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-realview/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 17c878ddbc70..300f7064465d 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -22,9 +22,9 @@
 #include <mach/board-pb11mp.h>
 #include <mach/board-pbx.h>
-#include "core.h"
+#include <plat/platsmp.h>
-extern void versatile_secondary_startup(void);
+#include "core.h"
 static void __iomem *scu_base_addr(void)
 {
@@ -43,7 +43,7 @@ static void __iomem *scu_base_addr(void)
 * Initialise the CPU possible map early - this describes the CPUs
 * which may be present or become present in the system.
 */
-void __init smp_init_cpus(void)
+static void __init realview_smp_init_cpus(void)
 {
        void __iomem *scu_base = scu_base_addr();
        unsigned int i, ncores;
@@ -63,7 +63,7 @@ void __init smp_init_cpus(void)
        set_smp_cross_call(gic_raise_softirq);
 }
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init realview_smp_prepare_cpus(unsigned int max_cpus)
 {
        scu_enable(scu_base_addr());
@@ -77,3 +77,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
        __raw_writel(virt_to_phys(versatile_secondary_startup),
                     __io_address(REALVIEW_SYS_FLAGSSET));
 }
+struct smp_operations realview_smp_ops __initdata = {
+        .smp_init_cpus          = realview_smp_init_cpus,
+        .smp_prepare_cpus       = realview_smp_prepare_cpus,
+        .smp_secondary_init     = versatile_secondary_init,
+        .smp_boot_secondary     = versatile_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = realview_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index baf382c5e776..d3b3cd216d64 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -27,12 +27,11 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -297,7 +296,7 @@ static struct resource pmu_resources[] = {
 static struct platform_device pmu_device = {
        .name                   = "arm-pmu",
-        .id                     = ARM_PMU_DEVICE_CPU,
+        .id                     = -1,
        .num_resources          = ARRAY_SIZE(pmu_resources),
        .resource               = pmu_resources,
 };
@@ -414,6 +413,7 @@ static void __init realview_eb_timer_init(void)
        else
                timer_irq = IRQ_EB_TIMER0_1;
+        realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
        realview_timer_init(timer_irq);
        realview_eb_twd_init();
 }
@@ -462,10 +462,6 @@ static void __init realview_eb_init(void)
                struct amba_device *d = amba_devs[i];
                amba_device_register(d, &iomem_resource);
        }
-#ifdef CONFIG_LEDS
-        leds_event = realview_leds_event;
-#endif
 }
 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index b1d7cafa1a6d..07d6672ddae7 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -29,12 +29,11 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -280,7 +279,7 @@ static struct resource pmu_resource = {
 static struct platform_device pmu_device = {
        .name                   = "arm-pmu",
-        .id                     = ARM_PMU_DEVICE_CPU,
+        .id                     = -1,
        .num_resources          = 1,
        .resource               = &pmu_resource,
 };
@@ -326,6 +325,7 @@ static void __init realview_pb1176_timer_init(void)
        timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE);
        timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20;
+        realview_clk_init(__io_address(REALVIEW_SYS_BASE), true);
        realview_timer_init(IRQ_DC1176_TIMER0);
 }
@@ -375,10 +375,6 @@ static void __init realview_pb1176_init(void)
                struct amba_device *d = amba_devs[i];
                amba_device_register(d, &iomem_resource);
        }
-#ifdef CONFIG_LEDS
-        leds_event = realview_leds_event;
-#endif
 }
 MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index a98c536e3327..7ed53d75350f 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -27,12 +27,11 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -263,7 +262,7 @@ static struct resource pmu_resources[] = {
 static struct platform_device pmu_device = {
        .name                   = "arm-pmu",
-        .id                     = ARM_PMU_DEVICE_CPU,
+        .id                     = -1,
        .num_resources          = ARRAY_SIZE(pmu_resources),
        .resource               = pmu_resources,
 };
@@ -312,6 +311,7 @@ static void __init realview_pb11mp_timer_init(void)
        timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
        timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
+        realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
        realview_timer_init(IRQ_TC11MP_TIMER0_1);
        realview_pb11mp_twd_init();
 }
@@ -357,15 +357,12 @@ static void __init realview_pb11mp_init(void)
                struct amba_device *d = amba_devs[i];
                amba_device_register(d, &iomem_resource);
        }
-#ifdef CONFIG_LEDS
-        leds_event = realview_leds_event;
-#endif
 }
 MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
        .atag_offset    = 0x100,
+        .smp            = smp_ops(realview_smp_ops),
        .fixup          = realview_fixup,
        .map_io         = realview_pb11mp_map_io,
        .init_early     = realview_init_early,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 59650174e6ed..9992431b8a15 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -27,11 +27,10 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
@@ -241,7 +240,7 @@ static struct resource pmu_resource = {
 static struct platform_device pmu_device = {
        .name                   = "arm-pmu",
-        .id                     = ARM_PMU_DEVICE_CPU,
+        .id                     = -1,
        .num_resources          = 1,
        .resource               = &pmu_resource,
 };
@@ -261,6 +260,7 @@ static void __init realview_pba8_timer_init(void)
        timer2_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE);
        timer3_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE) + 0x20;
+        realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
        realview_timer_init(IRQ_PBA8_TIMER0_1);
 }
@@ -299,10 +299,6 @@ static void __init realview_pba8_init(void)
                struct amba_device *d = amba_devs[i];
                amba_device_register(d, &iomem_resource);
        }
-#ifdef CONFIG_LEDS
-        leds_event = realview_leds_event;
-#endif
 }
 MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 3f2f605624e9..4f486f05108a 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -26,11 +26,10 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/smp_twd.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
@@ -280,7 +279,7 @@ static struct resource pmu_resources[] = {
 static struct platform_device pmu_device = {
        .name                   = "arm-pmu",
-        .id                     = ARM_PMU_DEVICE_CPU,
+        .id                     = -1,
        .num_resources          = ARRAY_SIZE(pmu_resources),
        .resource               = pmu_resources,
 };
@@ -320,6 +319,7 @@ static void __init realview_pbx_timer_init(void)
        timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE);
        timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20;
+        realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
        realview_timer_init(IRQ_PBX_TIMER0_1);
        realview_pbx_twd_init();
 }
@@ -394,15 +394,12 @@ static void __init realview_pbx_init(void)
                struct amba_device *d = amba_devs[i];
                amba_device_register(d, &iomem_resource);
        }
-#ifdef CONFIG_LEDS
-        leds_event = realview_leds_event;
-#endif
 }
 MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
        .atag_offset    = 0x100,
+        .smp            = smp_ops(realview_smp_ops),
        .fixup          = realview_pbx_fixup,
        .map_io         = realview_pbx_map_io,
        .init_early     = realview_init_early,
diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c
index b91bc87b3dcf..fcb1d59f7aec 100644
--- a/arch/arm/mach-rpc/ecard.c
+++ b/arch/arm/mach-rpc/ecard.c
@@ -960,7 +960,9 @@ static int __init ecard_probe(int slot, unsigned irq, card_type_t type)
        *ecp = ec;
        slot_to_expcard[slot] = ec;
-        device_register(&ec->dev);
+        rc = device_register(&ec->dev);
+        if (rc)
+                goto nodev;
        return 0;
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index cb2883d553b5..749220f91a70 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
@@ -87,6 +87,19 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
        return 0;
 }
+static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);
+        if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL))
+                return parent_rate;
+        camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK;
+        return parent_rate / (camdivn + 1) / 2;
+}
 /* Extra S3C2440 clocks */
 static struct clk s3c2440_clk_cam = {
@@ -99,6 +112,7 @@ static struct clk s3c2440_clk_cam_upll = {
        .name           = "camif-upll",
        .ops            = &(struct clk_ops) {
                .set_rate       = s3c2440_camif_upll_setrate,
+                .get_rate       = s3c2440_camif_upll_getrate,
                .round_rate     = s3c2440_camif_upll_round,
        },
 };
diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c
index 87e75a250d5e..3b2cf6db3634 100644
--- a/arch/arm/mach-s3c24xx/common-smdk.c
+++ b/arch/arm/mach-s3c24xx/common-smdk.c
@@ -37,9 +37,9 @@
 #include <asm/irq.h>
 #include <mach/regs-gpio.h>
-#include <mach/leds-gpio.h>
+#include <linux/platform_data/leds-s3c24xx.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <plat/common-smdk.h>
 #include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
index a5eeb62ce1c2..57aee916bdb1 100644
--- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
@@ -138,19 +138,7 @@ static struct platform_driver h1940bt_driver = {
        .remove         = h1940bt_remove,
 };
+module_platform_driver(h1940bt_driver);
-static int __init h1940bt_init(void)
-{
-        return platform_driver_register(&h1940bt_driver);
-}
-static void __exit h1940bt_exit(void)
-{
-        platform_driver_unregister(&h1940bt_driver);
-}
-module_init(h1940bt_init);
-module_exit(h1940bt_exit);
 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
 MODULE_DESCRIPTION("Driver for the iPAQ H1940 bluetooth chip");
diff --git a/arch/arm/mach-s3c24xx/include/mach/leds-gpio.h b/arch/arm/mach-s3c24xx/include/mach/leds-gpio.h
deleted file mode 100644
index d8a7672519b6..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/leds-gpio.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/leds-gpio.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX - LEDs GPIO connector
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_LEDSGPIO_H
-#define __ASM_ARCH_LEDSGPIO_H "leds-gpio.h"
-#define S3C24XX_LEDF_ACTLOW     (1<<0)          /* LED is on when GPIO low */
-#define S3C24XX_LEDF_TRISTATE   (1<<1)          /* tristate to turn off */
-struct s3c24xx_led_platdata {
-        unsigned int             gpio;
-        unsigned int             flags;
-        char                    *name;
-        char                    *def_trigger;
-};
-#endif /* __ASM_ARCH_LEDSGPIO_H */
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2416.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c
index 23ec97370f32..ff141b0af26b 100644
--- a/arch/arm/mach-s3c24xx/irq-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2416.c
@@ -232,7 +232,7 @@ struct irq_chip s3c2416_irq_second = {
 /* IRQ initialisation code */
-static int __init s3c2416_add_sub(unsigned int base,
+static int s3c2416_add_sub(unsigned int base,
                                   void (*demux)(unsigned int,
                                                 struct irq_desc *),
                                   struct irq_chip *chip,
@@ -251,7 +251,7 @@ static int __init s3c2416_add_sub(unsigned int base,
        return 0;
 }
-static void __init s3c2416_irq_add_second(void)
+static void s3c2416_irq_add_second(void)
 {
        unsigned long pend;
        unsigned long last;
@@ -287,7 +287,7 @@ static void __init s3c2416_irq_add_second(void)
        }
 }
-static int __init s3c2416_irq_add(struct device *dev,
+static int s3c2416_irq_add(struct device *dev,
                                  struct subsys_interface *sif)
 {
        printk(KERN_INFO "S3C2416: IRQ Support\n");
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2443.c b/arch/arm/mach-s3c24xx/irq-s3c2443.c
index ac2829f56d12..5e69109c0928 100644
--- a/arch/arm/mach-s3c24xx/irq-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2443.c
@@ -222,7 +222,7 @@ static struct irq_chip s3c2443_irq_cam = {
 /* IRQ initialisation code */
-static int __init s3c2443_add_sub(unsigned int base,
+static int s3c2443_add_sub(unsigned int base,
                                   void (*demux)(unsigned int,
                                                 struct irq_desc *),
                                   struct irq_chip *chip,
@@ -241,7 +241,7 @@ static int __init s3c2443_add_sub(unsigned int base,
        return 0;
 }
-static int __init s3c2443_irq_add(struct device *dev,
+static int s3c2443_irq_add(struct device *dev,
                                  struct subsys_interface *sif)
 {
        printk("S3C2443: IRQ Support\n");
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index ea2c4b003d58..f4ad99c1e476 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -53,7 +53,7 @@
 #include <mach/regs-lcd.h>
 #include <mach/regs-gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 5a7d0c0010f7..1ee8c4638743 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -40,8 +40,8 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -53,7 +53,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/audio-simtec.h>
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
 #include "simtec.h"
 #include "common.h"
@@ -424,7 +424,8 @@ static void __init anubis_map_io(void)
                anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
        } else {
                /* ensure that the GPIO is setup */
-                s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
+                gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
+                gpio_free(S3C2410_GPA(0));
        }
 }
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index 7a05abf1270b..00381fe5de32 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -36,8 +36,8 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -47,7 +47,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/mci.h>
+#include <linux/platform_data/mmc-s3cmci.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index 1cf1720682d3..6a30ce7e4aa7 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -45,9 +45,9 @@
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
-#include <plat/hwmon.h>
+#include <linux/platform_data/hwmon-s3c.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/fb.h>
 #include <linux/mtd/mtd.h>
@@ -62,7 +62,7 @@
 #include <plat/cpu.h>
 #include <plat/cpu-freq.h>
 #include <plat/gpio-cfg.h>
-#include <plat/audio-simtec.h>
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
 #include "simtec.h"
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index 92e1f93a6bca..4a963467b7ee 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -73,21 +73,21 @@
 #include <mach/regs-gpio.h>
 #include <mach/fb.h>
-#include <plat/usb-control.h>
+#include <linux/platform_data/usb-ohci-s3c2410.h>
 #include <mach/regs-mem.h>
 #include <mach/hardware.h>
 #include <mach/gta02.h>
 #include <plat/regs-serial.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
 #include <plat/gpio-cfg.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index bb8d008d5a5c..63aaf076f611 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -56,8 +56,8 @@
 #include <mach/h1940.h>
 #include <mach/h1940-latch.h>
 #include <mach/fb.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
@@ -65,8 +65,8 @@
 #include <plat/cpu.h>
 #include <plat/pll.h>
 #include <plat/pm.h>
-#include <plat/mci.h>
+#include <linux/platform_data/mmc-s3cmci.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 #include <sound/uda1380.h>
@@ -380,7 +380,7 @@ int h1940_led_blink_set(unsigned gpio, int state,
        default:
                blink_gpio = S3C2410_GPA(3);
                check_gpio1 = S3C2410_GPA(1);
-                check_gpio1 = S3C2410_GPA(7);
+                check_gpio2 = S3C2410_GPA(7);
                break;
        }
@@ -460,7 +460,7 @@ static void h1940_set_mmc_power(unsigned char power_mode, unsigned short vdd)
                break;
        default:
                break;
-        };
+        }
 }
 static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = {
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index ae73ba34ecc6..c9954e26b492 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -32,8 +32,8 @@
 #include <asm/mach/irq.h>
 #include <plat/regs-serial.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/regs-power.h>
 #include <mach/regs-gpio.h>
@@ -54,7 +54,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
 static struct map_desc jive_iodesc[] __initdata = {
 };
@@ -512,8 +512,8 @@ static void jive_power_off(void)
 {
        printk(KERN_INFO "powering system down...\n");
-        s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
+        gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
-        s3c_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
+        gpio_free(S3C2410_GPC(5));
 }
 static void __init jive_machine_init(void)
@@ -623,11 +623,11 @@ static void __init jive_machine_init(void)
        gpio_request(S3C2410_GPB(7), "jive spi");
        gpio_direction_output(S3C2410_GPB(7), 1);
-        s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
+        gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
-        s3c_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
+        gpio_free(S3C2410_GPB(6));
-        s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
+        gpio_request_one(S3C2410_GPG(8), GPIOF_OUT_INIT_HIGH, NULL);
-        s3c_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
+        gpio_free(S3C2410_GPG(8));
        /* initialise the WM8750 spi */
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index bd6d2525debe..393c0f1ac11a 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -39,14 +39,14 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/leds-gpio.h>
+#include <linux/platform_data/leds-s3c24xx.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/irqs.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/mci.h>
+#include <linux/platform_data/mmc-s3cmci.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -638,9 +638,9 @@ static void __init mini2440_init(void)
        gpio_free(S3C2410_GPG(4));
        /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */
+        gpio_request_one(S3C2410_GPB(1), GPIOF_IN, NULL);
        s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP);
-        s3c2410_gpio_setpin(S3C2410_GPB(1), 0);
+        gpio_free(S3C2410_GPB(1));
-        s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT);
        /* mark the key as input, without pullups (there is one on the board) */
        for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) {
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 383d00ca8f60..c53a9bfe1417 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -33,7 +33,7 @@
 #include <asm/mach-types.h>
 #include <mach/fb.h>
-#include <mach/leds-gpio.h>
+#include <linux/platform_data/leds-s3c24xx.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
@@ -41,15 +41,15 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/regs-serial.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/mci.h>
+#include <linux/platform_data/mmc-s3cmci.h>
 #include <plat/s3c2410.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 5c05ba1c330f..a2b92b0898e2 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -38,7 +38,7 @@
 //#include <asm/debug-ll.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-serial.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 #include <plat/s3c2410.h>
@@ -119,17 +119,17 @@ static struct platform_device *nexcoder_devices[] __initdata = {
 static void __init nexcoder_sensorboard_init(void)
 {
-        // Initialize SCCB bus
+        /* Initialize SCCB bus */
-        s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
+        gpio_request_one(S3C2410_GPE(14), GPIOF_OUT_INIT_HIGH, NULL);
-        s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
+        gpio_free(S3C2410_GPE(14)); /* IICSCL */
-        s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
+        gpio_request_one(S3C2410_GPE(15), GPIOF_OUT_INIT_HIGH, NULL);
-        s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
+        gpio_free(S3C2410_GPE(15)); /* IICSDA */
-        // Power up the sensor board
+        /* Power up the sensor board */
-        s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
+        gpio_request_one(S3C2410_GPF(1), GPIOF_OUT_INIT_HIGH, NULL);
-        s3c_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
+        gpio_free(S3C2410_GPF(1)); /* CAM_GPIO7 => nLDO_PWRDN */
-        s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
+        gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL);
-        s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
+        gpio_free(S3C2410_GPF(2)); /* CAM_GPIO6 => CAM_PWRDN */
 }
 static void __init nexcoder_map_io(void)
diff --git a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
index ad2792dfbee1..5876c6ba7500 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
@@ -175,18 +175,7 @@ static struct platform_driver osiris_dvs_driver = {
        },
 };
-static int __init osiris_dvs_init(void)
+module_platform_driver(osiris_dvs_driver);
-{
-        return platform_driver_register(&osiris_dvs_driver);
-}
-static void __exit osiris_dvs_exit(void)
-{
-        platform_driver_unregister(&osiris_dvs_driver);
-}
-module_init(osiris_dvs_init);
-module_exit(osiris_dvs_exit);
 MODULE_DESCRIPTION("Simtec OSIRIS DVS support");
 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index 95d077255024..bb36d832bd3d 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -41,8 +41,8 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -274,8 +274,8 @@ static int osiris_pm_suspend(void)
        __raw_writeb(tmp, OSIRIS_VA_CTRL0);
        /* ensure that an nRESET is not generated on resume. */
-        s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
+        gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL);
-        s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
+        gpio_free(S3C2410_GPA(21));
        return 0;
 }
@@ -396,7 +396,8 @@ static void __init osiris_map_io(void)
                osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
        } else {
                /* write-protect line to the NAND */
-                s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
+                gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
+                gpio_free(S3C2410_GPA(0));
        }
        /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index bc4b6efb3b27..bca39f0232b3 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -35,7 +35,7 @@
 #include <plat/s3c2410.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/cpu.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 678bbca2b5e5..7b6ba13d7285 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -47,13 +47,13 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <mach/leds-gpio.h>
+#include <linux/platform_data/leds-s3c24xx.h>
 #include <mach/regs-lcd.h>
 #include <plat/regs-serial.h>
 #include <mach/fb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/common-smdk.h>
 #include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 7ee73f27f207..379fde521d37 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -49,15 +49,15 @@
 #include <plat/clock.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-iic.h>
-#include <plat/mci.h>
+#include <linux/platform_data/mmc-s3cmci.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
 #include <plat/irq.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 #include <sound/uda1380.h>
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index 56af35447598..dacbb9a2122a 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -43,7 +43,7 @@
 #include <mach/regs-lcd.h>
 #include <mach/h1940.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <mach/fb.h>
 #include <plat/clock.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index bdc27e772876..82796b97cb04 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -47,7 +47,7 @@
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index b11451b853d8..ce99fd8bbbc5 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -38,8 +38,8 @@
 #include <mach/regs-lcd.h>
 #include <mach/idle.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/fb.h>
 #include <plat/s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index c3100a044fbe..f30d7fccbfee 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -29,6 +29,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <video/samsung_fimd.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -39,20 +40,19 @@
 #include <mach/regs-s3c2443-clock.h>
 #include <mach/idle.h>
-#include <mach/leds-gpio.h>
+#include <linux/platform_data/leds-s3c24xx.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/s3c2416.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <plat/sdhci.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/s3c-hsudc.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
 #include <plat/common-smdk.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index 83a1036d7dcb..b7ff882c6ce6 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -37,7 +37,7 @@
 #include <mach/idle.h>
 #include <mach/fb.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/s3c2410.h>
 #include <plat/s3c244x.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index 209236956222..2568656f046f 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -37,7 +37,7 @@
 #include <mach/idle.h>
 #include <mach/fb.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/s3c2410.h>
 #include <plat/s3c2443.h>
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index fe990289ee7d..495bf5cf52e9 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -45,7 +45,7 @@
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index bd5f189f0424..14d5b12e388c 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -43,13 +43,13 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/leds-gpio.h>
+#include <linux/platform_data/leds-s3c24xx.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/audio-simtec.h>
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
 #include "simtec.h"
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 94bfaa1fb148..f1d44ae11833 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -39,8 +39,8 @@
 #include <mach/idle.h>
 #include <mach/fb.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <plat/s3c2410.h>
 #include <plat/s3c2412.h>
diff --git a/arch/arm/mach-s3c24xx/setup-i2c.c b/arch/arm/mach-s3c24xx/setup-i2c.c
index 9e90a7cbd1d6..7b4f33332d19 100644
--- a/arch/arm/mach-s3c24xx/setup-i2c.c
+++ b/arch/arm/mach-s3c24xx/setup-i2c.c
@@ -16,7 +16,7 @@
 struct platform_device;
 #include <plat/gpio-cfg.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
diff --git a/arch/arm/mach-s3c24xx/simtec-audio.c b/arch/arm/mach-s3c24xx/simtec-audio.c
index 11881c9a38c0..fd0ef05763a9 100644
--- a/arch/arm/mach-s3c24xx/simtec-audio.c
+++ b/arch/arm/mach-s3c24xx/simtec-audio.c
@@ -24,7 +24,7 @@
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
-#include <plat/audio-simtec.h>
+#include <linux/platform_data/asoc-s3c24xx_simtec.h>
 #include <plat/devs.h>
 #include "simtec.h"
diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c24xx/simtec-usb.c
index d91c1a725139..ddf7a3c743ac 100644
--- a/arch/arm/mach-s3c24xx/simtec-usb.c
+++ b/arch/arm/mach-s3c24xx/simtec-usb.c
@@ -34,7 +34,7 @@
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <plat/usb-control.h>
+#include <linux/platform_data/usb-ohci-s3c2410.h>
 #include <plat/devs.h>
 #include "simtec.h"
@@ -104,7 +104,7 @@ static struct s3c2410_hcd_info usb_simtec_info __initdata = {
 };
-int usb_simtec_init(void)
+int __init usb_simtec_init(void)
 {
        int ret;
diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c64xx/dev-audio.c
index 124fd5d63006..35f3e07eaccc 100644
--- a/arch/arm/mach-s3c64xx/dev-audio.c
+++ b/arch/arm/mach-s3c64xx/dev-audio.c
@@ -20,7 +20,7 @@
 #include <mach/dma.h>
 #include <plat/devs.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 #include <plat/gpio-cfg.h>
 static const char *rclksrc[] = {
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index ffa29ddfdfce..99e82ac81b69 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -29,6 +29,7 @@
 #include <linux/dm9000.h>
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -42,9 +43,8 @@
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 9e382e7c77cb..4e3fe57674c8 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -16,6 +16,7 @@
 #include <linux/mfd/wm831x/irq.h>
 #include <linux/mfd/wm831x/gpio.h>
 #include <linux/mfd/wm8994/pdata.h>
+#include <linux/mfd/arizona/pdata.h>
 #include <linux/regulator/machine.h>
@@ -24,7 +25,7 @@
 #include <sound/wm8962.h>
 #include <sound/wm9081.h>
-#include <plat/s3c64xx-spi.h>
+#include <linux/platform_data/spi-s3c64xx.h>
 #include <mach/crag6410.h>
@@ -181,9 +182,33 @@ static const struct i2c_board_info wm1277_devs[] = {
        },
 };
-static const struct i2c_board_info wm5102_devs[] = {
+static struct arizona_pdata wm5102_pdata = {
-        { I2C_BOARD_INFO("wm5102", 0x1a),
+        .ldoena = S3C64XX_GPN(7),
-          .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, },
+        .gpio_base = CODEC_GPIO_BASE,
+        .irq_active_high = true,
+        .micd_pol_gpio = CODEC_GPIO_BASE + 4,
+        .gpio_defaults = {
+                [2] = 0x10000, /* AIF3TXLRCLK */
+                [3] = 0x4,     /* OPCLK */
+        },
+};
+static struct s3c64xx_spi_csinfo wm5102_spi_csinfo = {
+        .line = S3C64XX_GPN(5),
+};
+static struct spi_board_info wm5102_spi_devs[] = {
+        [0] = {
+                .modalias       = "wm5102",
+                .max_speed_hz   = 10 * 1000 * 1000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_0,
+                .irq            = GLENFARCLAS_PMIC_IRQ_BASE +
+                                  WM831X_IRQ_GPIO_2,
+                .controller_data = &wm5102_spi_csinfo,
+                .platform_data = &wm5102_pdata,
+        },
 };
 static const struct i2c_board_info wm6230_i2c_devs[] = {
@@ -223,8 +248,9 @@ static __devinitdata const struct {
        { .id = 0x3c, .name = "1273-EV1 Longmorn" },
        { .id = 0x3d, .name = "1277-EV1 Littlemill",
          .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) },
-        { .id = 0x3e, .name = "WM5102-6271-EV1-CS127",
+        { .id = 0x3e, .name = "WM5102-6271-EV1-CS127 Amrut",
-          .i2c_devs = wm5102_devs, .num_i2c_devs = ARRAY_SIZE(wm5102_devs) },
+          .spi_devs = wm5102_spi_devs,
+          .num_spi_devs = ARRAY_SIZE(wm5102_spi_devs) },
 };
 static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 09cd81207a3f..13b7eaa45fd0 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -46,6 +46,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
+#include <video/samsung_fimd.h>
 #include <mach/hardware.h>
 #include <mach/map.h>
@@ -57,18 +58,17 @@
 #include <mach/regs-gpio-memport.h>
 #include <plat/regs-serial.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
+#include <linux/platform_data/spi-s3c64xx.h>
 #include <plat/keypad.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/adc.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pm.h>
 #include "common.h"
@@ -287,6 +287,16 @@ static struct platform_device littlemill_device = {
        .id             = -1,
 };
+static struct platform_device bells_wm5102_device = {
+        .name           = "bells",
+        .id             = 0,
+};
+static struct platform_device bells_wm5110_device = {
+        .name           = "bells",
+        .id             = 1,
+};
 static struct regulator_consumer_supply wallvdd_consumers[] = {
        REGULATOR_SUPPLY("SPKVDD", "1-001a"),
        REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
@@ -359,6 +369,8 @@ static struct platform_device *crag6410_devices[] __initdata = {
        &tobermory_device,
        &littlemill_device,
        &lowland_device,
+        &bells_wm5102_device,
+        &bells_wm5110_device,
        &wallvdd_device,
 };
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 689088162f77..2b144893ddc4 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -26,6 +26,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <video/samsung_fimd.h>
 #include <mach/hardware.h>
 #include <mach/map.h>
@@ -34,14 +35,13 @@
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/regs-fb-v4.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 5539a255a704..07c349cca333 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -38,12 +38,12 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <plat/regs-serial.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/regs-fb-v4.h>
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index cad2e05eddf7..e5f9a79b535d 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -37,13 +38,12 @@
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/regs-fb-v4.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 326b21604bc3..7476f7c722ab 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -39,12 +39,12 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <plat/regs-serial.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/regs-fb-v4.h>
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index ceeb1de40376..c6d7390939ae 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -30,13 +30,13 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
-#include <plat/hwmon.h>
+#include <linux/platform_data/hwmon-s3c.h>
 #include <plat/regs-serial.h>
-#include <plat/usb-control.h>
+#include <linux/platform_data/usb-ohci-s3c2410.h>
 #include <plat/sdhci.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 #include <video/platform_lcd.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index d6266d8b43c9..96d6da2b6b5f 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -21,6 +21,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
@@ -28,7 +29,6 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-fb-v4.h>
 #include "common.h"
 #include "mach-smartq.h"
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 0957d2a980e1..7d1167bdc921 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -21,6 +21,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
@@ -28,7 +29,6 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-fb-v4.h>
 #include "common.h"
 #include "mach-smartq.h"
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index b0f4525c66bd..a928fae5694e 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -35,7 +35,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 0fe4f1503f4f..da1a771a29e9 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -43,6 +43,7 @@
 #endif
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -60,8 +61,8 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-sys.h>
 #include <mach/regs-srom.h>
-#include <plat/ata.h>
+#include <linux/platform_data/ata-samsung_cf.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
@@ -69,10 +70,9 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/adc.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 #include <plat/keypad.h>
 #include <plat/backlight.h>
-#include <plat/regs-fb-v4.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c64xx/setup-i2c0.c b/arch/arm/mach-s3c64xx/setup-i2c0.c
index 241af94a9e70..40666ba8d607 100644
--- a/arch/arm/mach-s3c64xx/setup-i2c0.c
+++ b/arch/arm/mach-s3c64xx/setup-i2c0.c
@@ -18,7 +18,7 @@
 struct platform_device; /* don't need the contents */
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-s3c64xx/setup-i2c1.c b/arch/arm/mach-s3c64xx/setup-i2c1.c
index 3d13a961986d..3fdb24c4e62a 100644
--- a/arch/arm/mach-s3c64xx/setup-i2c1.c
+++ b/arch/arm/mach-s3c64xx/setup-i2c1.c
@@ -18,7 +18,7 @@
 struct platform_device; /* don't need the contents */
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-s3c64xx/setup-ide.c b/arch/arm/mach-s3c64xx/setup-ide.c
index 41b425602d88..648d8b85bf6b 100644
--- a/arch/arm/mach-s3c64xx/setup-ide.c
+++ b/arch/arm/mach-s3c64xx/setup-ide.c
@@ -17,7 +17,7 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <plat/gpio-cfg.h>
-#include <plat/ata.h>
+#include <linux/platform_data/ata-samsung_cf.h>
 void s3c64xx_ide_setup_gpio(void)
 {
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c
index 91113ddc51da..a0d6edfd23a0 100644
--- a/arch/arm/mach-s5p64x0/dev-audio.c
+++ b/arch/arm/mach-s5p64x0/dev-audio.c
@@ -13,7 +13,7 @@
 #include <linux/gpio.h>
 #include <plat/gpio-cfg.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 #include <mach/map.h>
 #include <mach/dma.h>
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 92fefad505cc..96ea1fe0ec94 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -27,6 +27,7 @@
 #include <linux/mmc/host.h>
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -45,14 +46,13 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pll.h>
 #include <plat/adc.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
-#include <plat/regs-fb.h>
 #include <plat/sdhci.h>
 #include "common.h"
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index e2335ecf6eae..12748b6eaa7b 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -27,6 +27,7 @@
 #include <linux/mmc/host.h>
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -45,14 +46,13 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pll.h>
 #include <plat/adc.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
-#include <plat/regs-fb.h>
 #include <plat/sdhci.h>
 #include "common.h"
diff --git a/arch/arm/mach-s5p64x0/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c
index 46b463917c54..a32edc545e6c 100644
--- a/arch/arm/mach-s5p64x0/setup-i2c0.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c0.c
@@ -19,7 +19,7 @@
 struct platform_device; /* don't need the contents */
 #include <plat/gpio-cfg.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/i2c.h>
diff --git a/arch/arm/mach-s5p64x0/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c
index 6ad3b986021c..ca2c5c7f8aa6 100644
--- a/arch/arm/mach-s5p64x0/setup-i2c1.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c1.c
@@ -19,7 +19,7 @@
 struct platform_device; /* don't need the contents */
 #include <plat/gpio-cfg.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/i2c.h>
diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c
index 9d4bde3f1110..1cc252cef268 100644
--- a/arch/arm/mach-s5pc100/dev-audio.c
+++ b/arch/arm/mach-s5pc100/dev-audio.c
@@ -13,7 +13,7 @@
 #include <linux/gpio.h>
 #include <plat/gpio-cfg.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 #include <mach/map.h>
 #include <mach/dma.h>
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 0c3ae38d27ca..dba7384a87bd 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -33,6 +33,7 @@
 #include <mach/regs-gpio.h>
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -44,14 +45,13 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/ata.h>
+#include <linux/platform_data/ata-samsung_cf.h>
 #include <plat/adc.h>
 #include <plat/keypad.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 #include <plat/backlight.h>
-#include <plat/regs-fb-v4.h>
 #include "common.h"
diff --git a/arch/arm/mach-s5pc100/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c
index eaef7a3bda49..89a6a769d622 100644
--- a/arch/arm/mach-s5pc100/setup-i2c0.c
+++ b/arch/arm/mach-s5pc100/setup-i2c0.c
@@ -18,7 +18,7 @@
 struct platform_device; /* don't need the contents */
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-s5pc100/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c
index aaff74a90dee..faa667ef02cb 100644
--- a/arch/arm/mach-s5pc100/setup-i2c1.c
+++ b/arch/arm/mach-s5pc100/setup-i2c1.c
@@ -18,7 +18,7 @@
 struct platform_device; /* don't need the contents */
 #include <linux/gpio.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
index 8367749c3eec..0a5480bbcbd5 100644
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ b/arch/arm/mach-s5pv210/dev-audio.c
@@ -13,7 +13,7 @@
 #include <linux/gpio.h>
 #include <plat/gpio-cfg.h>
-#include <plat/audio.h>
+#include <linux/platform_data/asoc-s3c.h>
 #include <mach/map.h>
 #include <mach/dma.h>
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 78028df86c5d..ee9fa5c2ef2c 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -28,6 +28,7 @@
 #include <asm/setup.h>
 #include <asm/mach-types.h>
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
@@ -39,7 +40,6 @@
 #include <plat/fimc-core.h>
 #include <plat/sdhci.h>
 #include <plat/s5p-time.h>
-#include <plat/regs-fb-v4.h>
 #include "common.h"
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 822a55950685..55e1dba4ffde 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -35,6 +35,7 @@
 #include <asm/setup.h>
 #include <asm/mach-types.h>
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
@@ -43,13 +44,12 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
 #include <plat/clock.h>
 #include <plat/s5p-time.h>
 #include <plat/mfc.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/camport.h>
 #include <media/v4l2-mediabus.h>
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index dfc29236321c..d9c99fcc1aa7 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -27,8 +27,8 @@
 #include <plat/regs-serial.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/ata.h>
+#include <linux/platform_data/ata-samsung_cf.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pm.h>
 #include <plat/s5p-time.h>
 #include <plat/mfc.h>
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 918b23d71fdf..4cdb5bb7bbcf 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -28,6 +28,7 @@
 #include <asm/mach-types.h>
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
@@ -38,15 +39,14 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/adc.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/ata.h>
+#include <linux/platform_data/ata-samsung_cf.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/keypad.h>
 #include <plat/pm.h>
 #include <plat/fb.h>
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/mfc.h>
 #include <plat/clock.h>
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 74e99bc0dc9b..18785cb5e1ef 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -26,7 +26,7 @@
 #include <plat/regs-serial.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/s5p-time.h>
 #include "common.h"
diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c
index 0f1cc3a1c1e8..4a15849766c0 100644
--- a/arch/arm/mach-s5pv210/setup-i2c0.c
+++ b/arch/arm/mach-s5pv210/setup-i2c0.c
@@ -18,7 +18,7 @@
 struct platform_device; /* don't need the contents */
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c
index f61365a34c56..4777f6b97a92 100644
--- a/arch/arm/mach-s5pv210/setup-i2c1.c
+++ b/arch/arm/mach-s5pv210/setup-i2c1.c
@@ -18,7 +18,7 @@
 struct platform_device; /* don't need the contents */
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c
index 2f91b5cefbc6..bbce6c74b915 100644
--- a/arch/arm/mach-s5pv210/setup-i2c2.c
+++ b/arch/arm/mach-s5pv210/setup-i2c2.c
@@ -18,7 +18,7 @@
 struct platform_device; /* don't need the contents */
-#include <plat/iic.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 void s3c_i2c2_cfg_gpio(struct platform_device *dev)
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index 60b97ec01676..1aed9e70465d 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -7,21 +7,17 @@ obj-y := clock.o generic.o irq.o time.o #nmi-oopser.o
 obj-m :=
 obj-n :=
 obj-  :=
-led-y := leds.o
 obj-$(CONFIG_CPU_FREQ_SA1100)           += cpu-sa1100.o
 obj-$(CONFIG_CPU_FREQ_SA1110)           += cpu-sa1110.o
 # Specific board support
 obj-$(CONFIG_SA1100_ASSABET)            += assabet.o
-led-$(CONFIG_SA1100_ASSABET)            += leds-assabet.o
 obj-$(CONFIG_ASSABET_NEPONSET)          += neponset.o
 obj-$(CONFIG_SA1100_BADGE4)             += badge4.o
-led-$(CONFIG_SA1100_BADGE4)             += leds-badge4.o
 obj-$(CONFIG_SA1100_CERF)               += cerf.o
-led-$(CONFIG_SA1100_CERF)               += leds-cerf.o
 obj-$(CONFIG_SA1100_COLLIE)             += collie.o
@@ -29,13 +25,11 @@ obj-$(CONFIG_SA1100_H3100)		+= h3100.o h3xxx.o
 obj-$(CONFIG_SA1100_H3600)              += h3600.o h3xxx.o
 obj-$(CONFIG_SA1100_HACKKIT)            += hackkit.o
-led-$(CONFIG_SA1100_HACKKIT)            += leds-hackkit.o
 obj-$(CONFIG_SA1100_JORNADA720)         += jornada720.o
 obj-$(CONFIG_SA1100_JORNADA720_SSP)     += jornada720_ssp.o
 obj-$(CONFIG_SA1100_LART)               += lart.o
-led-$(CONFIG_SA1100_LART)               += leds-lart.o
 obj-$(CONFIG_SA1100_NANOENGINE)         += nanoengine.o
 obj-$(CONFIG_PCI_NANOENGINE)            += pci-nanoengine.o
@@ -46,9 +40,6 @@ obj-$(CONFIG_SA1100_SHANNON)		+= shannon.o
 obj-$(CONFIG_SA1100_SIMPAD)             += simpad.o
-# LEDs support
-obj-$(CONFIG_LEDS) += $(led-y)
 # Miscellaneous functions
 obj-$(CONFIG_PM)                        += pm.o sleep.o
 obj-$(CONFIG_SA1100_SSP)                += ssp.o
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index d673211f121c..6a7ad3c2a3fc 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -20,6 +20,8 @@
 #include <linux/mtd/partitions.h>
 #include <linux/delay.h>
 #include <linux/mm.h>
+#include <linux/leds.h>
+#include <linux/slab.h>
 #include <video/sa1100fb.h>
@@ -37,7 +39,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
 #include <mach/assabet.h>
-#include <mach/mcp.h>
+#include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/irqs.h>
 #include "generic.h"
@@ -386,7 +388,7 @@ static void __init map_sa1100_gpio_regs( void )
 */
 static void __init get_assabet_scr(void)
 {
-        unsigned long scr, i;
+        unsigned long uninitialized_var(scr), i;
        GPDR |= 0x3fc;                  /* Configure GPIO 9:2 as outputs */
        GPSR = 0x3fc;                   /* Write 0xFF to GPIO 9:2 */
@@ -529,6 +531,89 @@ static void __init assabet_map_io(void)
        sa1100_register_uart(2, 3);
 }
+/* LEDs */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct assabet_led {
+        struct led_classdev cdev;
+        u32 mask;
+};
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} assabet_leds[] = {
+        { "assabet:red", "cpu0",},
+        { "assabet:green", "heartbeat", },
+};
+/*
+ * The LED control in Assabet is reversed:
+ *  - setting bit means turn off LED
+ *  - clearing bit means turn on LED
+ */
+static void assabet_led_set(struct led_classdev *cdev,
+                enum led_brightness b)
+{
+        struct assabet_led *led = container_of(cdev,
+                        struct assabet_led, cdev);
+        if (b != LED_OFF)
+                ASSABET_BCR_clear(led->mask);
+        else
+                ASSABET_BCR_set(led->mask);
+}
+static enum led_brightness assabet_led_get(struct led_classdev *cdev)
+{
+        struct assabet_led *led = container_of(cdev,
+                        struct assabet_led, cdev);
+        return (ASSABET_BCR & led->mask) ? LED_OFF : LED_FULL;
+}
+static int __init assabet_leds_init(void)
+{
+        int i;
+        if (!machine_is_assabet())
+                return -ENODEV;
+        for (i = 0; i < ARRAY_SIZE(assabet_leds); i++) {
+                struct assabet_led *led;
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+                led->cdev.name = assabet_leds[i].name;
+                led->cdev.brightness_set = assabet_led_set;
+                led->cdev.brightness_get = assabet_led_get;
+                led->cdev.default_trigger = assabet_leds[i].trigger;
+                if (!i)
+                        led->mask = ASSABET_BCR_LED_RED;
+                else
+                        led->mask = ASSABET_BCR_LED_GREEN;
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+        return 0;
+}
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(assabet_leds_init);
+#endif
 MACHINE_START(ASSABET, "Intel-Assabet")
        .atag_offset    = 0x100,
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index b30fb99b587c..038df4894b0f 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -22,6 +22,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/errno.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -76,8 +78,36 @@ static struct platform_device sa1111_device = {
        .resource       = sa1111_resources,
 };
+/* LEDs */
+struct gpio_led badge4_gpio_leds[] = {
+        {
+                .name                   = "badge4:red",
+                .default_trigger        = "heartbeat",
+                .gpio                   = 7,
+        },
+        {
+                .name                   = "badge4:green",
+                .default_trigger        = "cpu0",
+                .gpio                   = 9,
+        },
+};
+static struct gpio_led_platform_data badge4_gpio_led_info = {
+        .leds           = badge4_gpio_leds,
+        .num_leds       = ARRAY_SIZE(badge4_gpio_leds),
+};
+static struct platform_device badge4_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &badge4_gpio_led_info,
+        }
+};
 static struct platform_device *devices[] __initdata = {
        &sa1111_device,
+        &badge4_leds,
 };
 static int __init badge4_sa1111_init(void)
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index 09d7f4b4b354..ad0eb08ea077 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -17,6 +17,8 @@
 #include <linux/irq.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -28,7 +30,7 @@
 #include <asm/mach/serial_sa1100.h>
 #include <mach/cerf.h>
-#include <mach/mcp.h>
+#include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/irqs.h>
 #include "generic.h"
@@ -43,8 +45,48 @@ static struct platform_device cerfuart2_device = {
        .resource       = cerfuart2_resources,
 };
+/* LEDs */
+struct gpio_led cerf_gpio_leds[] = {
+        {
+                .name                   = "cerf:d0",
+                .default_trigger        = "heartbeat",
+                .gpio                   = 0,
+        },
+        {
+                .name                   = "cerf:d1",
+                .default_trigger        = "cpu0",
+                .gpio                   = 1,
+        },
+        {
+                .name                   = "cerf:d2",
+                .default_trigger        = "default-on",
+                .gpio                   = 2,
+        },
+        {
+                .name                   = "cerf:d3",
+                .default_trigger        = "default-on",
+                .gpio                   = 3,
+        },
+};
+static struct gpio_led_platform_data cerf_gpio_led_info = {
+        .leds           = cerf_gpio_leds,
+        .num_leds       = ARRAY_SIZE(cerf_gpio_leds),
+};
+static struct platform_device cerf_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &cerf_gpio_led_info,
+        }
+};
 static struct platform_device *cerf_devices[] __initdata = {
        &cerfuart2_device,
+        &cerf_leds,
 };
 #ifdef CONFIG_SA1100_CERF_FLASH_32MB
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index ea5cff38745c..170cb6107f68 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -45,7 +45,7 @@
 #include <asm/hardware/scoop.h>
 #include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/locomo.h>
-#include <mach/mcp.h>
+#include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/irqs.h>
 #include "generic.h"
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index 7f86bd911826..fc106aab7c7e 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -21,6 +21,10 @@
 #include <linux/serial_core.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/tty.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
@@ -183,9 +187,37 @@ static struct flash_platform_data hackkit_flash_data = {
 static struct resource hackkit_flash_resource =
        DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
+/* LEDs */
+struct gpio_led hackkit_gpio_leds[] = {
+        {
+                .name                   = "hackkit:red",
+                .default_trigger        = "cpu0",
+                .gpio                   = 22,
+        },
+        {
+                .name                   = "hackkit:green",
+                .default_trigger        = "heartbeat",
+                .gpio                   = 23,
+        },
+};
+static struct gpio_led_platform_data hackkit_gpio_led_info = {
+        .leds           = hackkit_gpio_leds,
+        .num_leds       = ARRAY_SIZE(hackkit_gpio_leds),
+};
+static struct platform_device hackkit_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &hackkit_gpio_led_info,
+        }
+};
 static void __init hackkit_init(void)
 {
        sa11x0_register_mtd(&hackkit_flash_data, &hackkit_flash_resource, 1);
+        platform_device_register(&hackkit_leds);
 }
 /**********************************************************************
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1111.h b/arch/arm/mach-sa1100/include/mach/SA-1111.h
deleted file mode 100644
index c38f60915cb6..000000000000
--- a/arch/arm/mach-sa1100/include/mach/SA-1111.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * Moved to new location
- */
-#warning using old SA-1111.h - update to <asm/hardware/sa1111.h>
-#include <asm/hardware/sa1111.h>
diff --git a/arch/arm/mach-sa1100/include/mach/lart.h b/arch/arm/mach-sa1100/include/mach/lart.h
deleted file mode 100644
index 8a5482d908db..000000000000
--- a/arch/arm/mach-sa1100/include/mach/lart.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _INCLUDE_LART_H
-#define _INCLUDE_LART_H
-#define LART_GPIO_ETH0                  GPIO_GPIO0
-#define LART_IRQ_ETH0                   IRQ_GPIO0
-#define LART_GPIO_IDE                   GPIO_GPIO1
-#define LART_IRQ_IDE                    IRQ_GPIO1
-#define LART_GPIO_UCB1200               GPIO_GPIO18
-#define LART_IRQ_UCB1200                IRQ_GPIO18
-#endif
diff --git a/arch/arm/mach-sa1100/include/mach/mcp.h b/arch/arm/mach-sa1100/include/mach/mcp.h
deleted file mode 100644
index 4b2860ae3828..000000000000
--- a/arch/arm/mach-sa1100/include/mach/mcp.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- *  arch/arm/mach-sa1100/include/mach/mcp.h
- *
- *  Copyright (C) 2005 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARM_ARCH_MCP_H
-#define __ASM_ARM_ARCH_MCP_H
-#include <linux/types.h>
-struct mcp_plat_data {
-        u32 mccr0;
-        u32 mccr1;
-        unsigned int sclk_rate;
-        void *codec_pdata;
-};
-#endif
diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h
index cdea671e8931..ac2ea767215d 100644
--- a/arch/arm/mach-sa1100/include/mach/simpad.h
+++ b/arch/arm/mach-sa1100/include/mach/simpad.h
@@ -87,7 +87,7 @@
 #define SIMPAD_CS3_PCMCIA_SHORT         (SIMPAD_CS3_GPIO_BASE + 22)
 #define SIMPAD_CS3_GPIO_23              (SIMPAD_CS3_GPIO_BASE + 23)
-#define CS3_BASE        0xf1000000
+#define CS3_BASE        IOMEM(0xf1000000)
 long simpad_get_cs3_ro(void);
 long simpad_get_cs3_shadow(void);
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index b775a0abec0a..3048b17e84c5 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -5,6 +5,9 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/tty.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
 #include <video/sa1100fb.h>
@@ -16,7 +19,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
-#include <mach/mcp.h>
+#include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/irqs.h>
 #include "generic.h"
@@ -126,6 +129,27 @@ static struct map_desc lart_io_desc[] __initdata = {
        }
 };
+/* LEDs */
+struct gpio_led lart_gpio_leds[] = {
+        {
+                .name                   = "lart:red",
+                .default_trigger        = "cpu0",
+                .gpio                   = 23,
+        },
+};
+static struct gpio_led_platform_data lart_gpio_led_info = {
+        .leds           = lart_gpio_leds,
+        .num_leds       = ARRAY_SIZE(lart_gpio_leds),
+};
+static struct platform_device lart_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &lart_gpio_led_info,
+        }
+};
 static void __init lart_map_io(void)
 {
        sa1100_map_io();
@@ -139,6 +163,8 @@ static void __init lart_map_io(void)
        GPDR |= GPIO_UART_TXD;
        GPDR &= ~GPIO_UART_RXD;
        PPAR |= PPAR_UPR;
+        platform_device_register(&lart_leds);
 }
 MACHINE_START(LART, "LART")
diff --git a/arch/arm/mach-sa1100/leds-assabet.c b/arch/arm/mach-sa1100/leds-assabet.c
deleted file mode 100644
index 3699176bca94..000000000000
--- a/arch/arm/mach-sa1100/leds-assabet.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-assabet.c
- *
- * Copyright (C) 2000 John Dorsey <john+@cs.cmu.edu>
- *
- * Original (leds-footbridge.c) by Russell King
- *
- * Assabet uses the LEDs as follows:
- *   - Green - toggles state every 50 timer interrupts
- *   - Red   - on if system is not idle
- */
-#include <linux/init.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <mach/assabet.h>
-#include "leds.h"
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-static unsigned int led_state;
-static unsigned int hw_led_state;
-#define ASSABET_BCR_LED_MASK    (ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED)
-void assabet_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        switch (evt) {
-        case led_start:
-                hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-                led_state = LED_STATE_ENABLED;
-                break;
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-                ASSABET_BCR_frob(ASSABET_BCR_LED_MASK, hw_led_state);
-                break;
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= ASSABET_BCR_LED_GREEN;
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= ASSABET_BCR_LED_RED;
-                break;
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~ASSABET_BCR_LED_RED;
-                break;
-#endif
-        case led_halted:
-                break;
-        case led_green_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~ASSABET_BCR_LED_GREEN;
-                break;
-        case led_green_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= ASSABET_BCR_LED_GREEN;
-                break;
-        case led_amber_on:
-                break;
-        case led_amber_off:
-                break;
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~ASSABET_BCR_LED_RED;
-                break;
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= ASSABET_BCR_LED_RED;
-                break;
-        default:
-                break;
-        }
-        if  (led_state & LED_STATE_ENABLED)
-                ASSABET_BCR_frob(ASSABET_BCR_LED_MASK, hw_led_state);
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-badge4.c b/arch/arm/mach-sa1100/leds-badge4.c
deleted file mode 100644
index f99fac3eedb6..000000000000
--- a/arch/arm/mach-sa1100/leds-badge4.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-badge4.c
- *
- * Author: Christopher Hoover <ch@hpl.hp.com>
- * Copyright (C) 2002 Hewlett-Packard Company
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#include <linux/init.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include "leds.h"
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-static unsigned int led_state;
-static unsigned int hw_led_state;
-#define LED_RED         GPIO_GPIO(7)
-#define LED_GREEN       GPIO_GPIO(9)
-#define LED_MASK        (LED_RED|LED_GREEN)
-#define LED_IDLE        LED_GREEN
-#define LED_TIMER       LED_RED
-void badge4_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        switch (evt) {
-        case led_start:
-                GPDR |= LED_MASK;
-                hw_led_state = LED_MASK;
-                led_state = LED_STATE_ENABLED;
-                break;
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= LED_TIMER;
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                /* LED off when system is idle */
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_IDLE;
-                break;
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_IDLE;
-                break;
-#endif
-        case led_red_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_RED;
-                break;
-        case led_red_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_RED;
-                break;
-        case led_green_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_GREEN;
-                break;
-        case led_green_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_GREEN;
-                break;
-        default:
-                break;
-        }
-        if  (led_state & LED_STATE_ENABLED) {
-                GPSR = hw_led_state;
-                GPCR = hw_led_state ^ LED_MASK;
-        }
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-cerf.c b/arch/arm/mach-sa1100/leds-cerf.c
deleted file mode 100644
index 30fc3b2bf555..000000000000
--- a/arch/arm/mach-sa1100/leds-cerf.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-cerf.c
- *
- * Author: ???
- */
-#include <linux/init.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include "leds.h"
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-static unsigned int led_state;
-static unsigned int hw_led_state;
-#define LED_D0          GPIO_GPIO(0)
-#define LED_D1          GPIO_GPIO(1)
-#define LED_D2          GPIO_GPIO(2)
-#define LED_D3          GPIO_GPIO(3)
-#define LED_MASK        (LED_D0|LED_D1|LED_D2|LED_D3)
-void cerf_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        switch (evt) {
-        case led_start:
-                hw_led_state = LED_MASK;
-                led_state = LED_STATE_ENABLED;
-                break;
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= LED_D0;
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D1;
-                break;
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D1;
-                break;
-#endif
-        case led_green_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D2;
-                break;
-        case led_green_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D2;
-                break;
-        case led_amber_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D3;
-                break;
-        case led_amber_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D3;
-                break;
-        case led_red_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D1;
-                break;
-        case led_red_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D1;
-                break;
-        default:
-                break;
-        }
-        if  (led_state & LED_STATE_ENABLED) {
-                GPSR = hw_led_state;
-                GPCR = hw_led_state ^ LED_MASK;
-        }
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-hackkit.c b/arch/arm/mach-sa1100/leds-hackkit.c
deleted file mode 100644
index f8e47235babe..000000000000
--- a/arch/arm/mach-sa1100/leds-hackkit.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-hackkit.c
- *
- * based on leds-lart.c
- *
- * (C) Erik Mouw (J.A.K.Mouw@its.tudelft.nl), April 21, 2000
- * (C) Stefan Eletzhofer <stefan.eletzhofer@eletztrick.de>, 2002
- *
- * The HackKit has two leds (GPIO 22/23). The red led (gpio 22) is used
- * as cpu led, the green one is used as timer led.
- */
-#include <linux/init.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include "leds.h"
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-static unsigned int led_state;
-static unsigned int hw_led_state;
-#define LED_GREEN    GPIO_GPIO23
-#define LED_RED    GPIO_GPIO22
-#define LED_MASK  (LED_RED | LED_GREEN)
-void hackkit_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        switch(evt) {
-                case led_start:
-                        /* pin 22/23 are outputs */
-                        GPDR |= LED_MASK;
-                        hw_led_state = LED_MASK;
-                        led_state = LED_STATE_ENABLED;
-                        break;
-                case led_stop:
-                        led_state &= ~LED_STATE_ENABLED;
-                        break;
-                case led_claim:
-                        led_state |= LED_STATE_CLAIMED;
-                        hw_led_state = LED_MASK;
-                        break;
-                case led_release:
-                        led_state &= ~LED_STATE_CLAIMED;
-                        hw_led_state = LED_MASK;
-                        break;
-#ifdef CONFIG_LEDS_TIMER
-                case led_timer:
-                        if (!(led_state & LED_STATE_CLAIMED))
-                                hw_led_state ^= LED_GREEN;
-                        break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-                case led_idle_start:
-                        /* The LART people like the LED to be off when the
-                           system is idle... */
-                        if (!(led_state & LED_STATE_CLAIMED))
-                                hw_led_state &= ~LED_RED;
-                        break;
-                case led_idle_end:
-                        /* ... and on if the system is not idle */
-                        if (!(led_state & LED_STATE_CLAIMED))
-                                hw_led_state |= LED_RED;
-                        break;
-#endif
-                case led_red_on:
-                        if (led_state & LED_STATE_CLAIMED)
-                                hw_led_state &= ~LED_RED;
-                        break;
-                case led_red_off:
-                        if (led_state & LED_STATE_CLAIMED)
-                                hw_led_state |= LED_RED;
-                        break;
-                case led_green_on:
-                        if (led_state & LED_STATE_CLAIMED)
-                                hw_led_state &= ~LED_GREEN;
-                        break;
-                case led_green_off:
-                        if (led_state & LED_STATE_CLAIMED)
-                                hw_led_state |= LED_GREEN;
-                        break;
-                default:
-                        break;
-        }
-        /* Now set the GPIO state, or nothing will happen at all */
-        if (led_state & LED_STATE_ENABLED) {
-                GPSR = hw_led_state;
-                GPCR = hw_led_state ^ LED_MASK;
-        }
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-lart.c b/arch/arm/mach-sa1100/leds-lart.c
deleted file mode 100644
index 50a5b143b460..000000000000
--- a/arch/arm/mach-sa1100/leds-lart.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-lart.c
- *
- * (C) Erik Mouw (J.A.K.Mouw@its.tudelft.nl), April 21, 2000
- *
- * LART uses the LED as follows:
- *   - GPIO23 is the LED, on if system is not idle
- *  You can use both CONFIG_LEDS_CPU and CONFIG_LEDS_TIMER at the same
- *  time, but in that case the timer events will still dictate the
- *  pace of the LED.
- */
-#include <linux/init.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include "leds.h"
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-static unsigned int led_state;
-static unsigned int hw_led_state;
-#define LED_23    GPIO_GPIO23
-#define LED_MASK  (LED_23)
-void lart_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        switch(evt) {
-        case led_start:
-                /* pin 23 is output pin */
-                GPDR |= LED_23;
-                hw_led_state = LED_MASK;
-                led_state = LED_STATE_ENABLED;
-                break;
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= LED_23;
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                /* The LART people like the LED to be off when the
-                   system is idle... */
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_23;
-                break;
-        case led_idle_end:
-                /* ... and on if the system is not idle */
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_23;
-                break;
-#endif
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~LED_23;
-                break;
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= LED_23;
-                break;
-        default:
-                break;
-        }
-        /* Now set the GPIO state, or nothing will happen at all */
-        if (led_state & LED_STATE_ENABLED) {
-                GPSR = hw_led_state;
-                GPCR = hw_led_state ^ LED_MASK;
-        }
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds.c b/arch/arm/mach-sa1100/leds.c
deleted file mode 100644
index 5fe71a0f1053..000000000000
--- a/arch/arm/mach-sa1100/leds.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds.c
- *
- * SA1100 LEDs dispatcher
- *
- * Copyright (C) 2001 Nicolas Pitre
- */
-#include <linux/compiler.h>
-#include <linux/init.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-#include "leds.h"
-static int __init
-sa1100_leds_init(void)
-{
-        if (machine_is_assabet())
-                leds_event = assabet_leds_event;
-        if (machine_is_consus())
-                leds_event = consus_leds_event;
-        if (machine_is_badge4())
-                leds_event = badge4_leds_event;
-        if (machine_is_brutus())
-                leds_event = brutus_leds_event;
-        if (machine_is_cerf())
-                leds_event = cerf_leds_event;
-        if (machine_is_flexanet())
-                leds_event = flexanet_leds_event;
-        if (machine_is_graphicsclient())
-                leds_event = graphicsclient_leds_event;
-        if (machine_is_hackkit())
-                leds_event = hackkit_leds_event;
-        if (machine_is_lart())
-                leds_event = lart_leds_event;
-        if (machine_is_pfs168())
-                leds_event = pfs168_leds_event;
-        if (machine_is_graphicsmaster())
-                leds_event = graphicsmaster_leds_event;
-        if (machine_is_adsbitsy())
-                leds_event = adsbitsy_leds_event;
-        if (machine_is_pt_system3())
-                leds_event = system3_leds_event;
-        leds_event(led_start);
-        return 0;
-}
-core_initcall(sa1100_leds_init);
diff --git a/arch/arm/mach-sa1100/leds.h b/arch/arm/mach-sa1100/leds.h
deleted file mode 100644
index 776b6020f550..000000000000
--- a/arch/arm/mach-sa1100/leds.h
+++ /dev/null
@@ -1,13 +0,0 @@
-extern void assabet_leds_event(led_event_t evt);
-extern void badge4_leds_event(led_event_t evt);
-extern void consus_leds_event(led_event_t evt);
-extern void brutus_leds_event(led_event_t evt);
-extern void cerf_leds_event(led_event_t evt);
-extern void flexanet_leds_event(led_event_t evt);
-extern void graphicsclient_leds_event(led_event_t evt);
-extern void hackkit_leds_event(led_event_t evt);
-extern void lart_leds_event(led_event_t evt);
-extern void pfs168_leds_event(led_event_t evt);
-extern void graphicsmaster_leds_event(led_event_t evt);
-extern void adsbitsy_leds_event(led_event_t evt);
-extern void system3_leds_event(led_event_t evt);
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 5d33fc3108ef..ff6b7b35bca9 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -19,7 +19,7 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
-#include <mach/mcp.h>
+#include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/shannon.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index fbd53593be54..71790e581d93 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -24,7 +24,7 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
-#include <mach/mcp.h>
+#include <linux/platform_data/mfd-mcp-sa11x0.h>
 #include <mach/simpad.h>
 #include <mach/irqs.h>
@@ -124,7 +124,7 @@ static struct map_desc simpad_io_desc[] __initdata = {
                .length         = 0x00800000,
                .type           = MT_DEVICE
        }, {    /* Simpad CS3 */
-                .virtual        = CS3_BASE,
+                .virtual        = (unsigned long)CS3_BASE,
                .pfn            = __phys_to_pfn(SA1100_CS3_PHYS),
                .length         = 0x00100000,
                .type           = MT_DEVICE
diff --git a/arch/arm/mach-shark/Makefile b/arch/arm/mach-shark/Makefile
index 45be9b04e7ba..29657183c452 100644
--- a/arch/arm/mach-shark/Makefile
+++ b/arch/arm/mach-shark/Makefile
@@ -4,9 +4,7 @@
 # Object file lists.
-obj-y                   := core.o dma.o irq.o pci.o
+obj-y                   := core.o dma.o irq.o pci.o leds.o
 obj-m                   :=
 obj-n                   :=
 obj-                    :=
-obj-$(CONFIG_LEDS)      += leds.o
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 2704bcd869cd..9ad2e9737fb5 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -13,7 +13,6 @@
 #include <asm/setup.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/param.h>
 #include <asm/system_misc.h>
@@ -21,9 +20,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#define IO_BASE                 0xe0000000
-#define IO_SIZE                 0x08000000
-#define IO_START                0x40000000
 #define ROMCARD_SIZE            0x08000000
 #define ROMCARD_START           0x10000000
@@ -104,20 +100,6 @@ arch_initcall(shark_init);
 extern void shark_init_irq(void);
-static struct map_desc shark_io_desc[] __initdata = {
-        {
-                .virtual        = IO_BASE,
-                .pfn            = __phys_to_pfn(IO_START),
-                .length         = IO_SIZE,
-                .type           = MT_DEVICE
-        }
-};
-static void __init shark_map_io(void)
-{
-        iotable_init(shark_io_desc, ARRAY_SIZE(shark_io_desc));
-}
 #define IRQ_TIMER 0
 #define HZ_TIME ((1193180 + HZ/2) / HZ)
@@ -158,7 +140,6 @@ static void shark_init_early(void)
 MACHINE_START(SHARK, "Shark")
        /* Maintainer: Alexander Schulz */
        .atag_offset    = 0x3000,
-        .map_io         = shark_map_io,
        .init_early     = shark_init_early,
        .init_irq       = shark_init_irq,
        .timer          = &shark_timer,
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S
index 20eb2bf2a42b..d129119a3f69 100644
--- a/arch/arm/mach-shark/include/mach/debug-macro.S
+++ b/arch/arm/mach-shark/include/mach/debug-macro.S
@@ -12,9 +12,10 @@
 */
                .macro  addruart, rp, rv, tmp
-                mov     \rp, #0xe0000000
+                mov     \rp, #0x3f8
-                orr     \rp, \rp, #0x000003f8
+                orr     \rv, \rp, #0xfe000000
-                mov     \rv, \rp
+                orr     \rv, \rv, #0x00e00000
+                orr     \rp, \rp, #0x40000000
                .endm
                .macro  senduart,rd,rx
diff --git a/arch/arm/mach-shark/include/mach/entry-macro.S b/arch/arm/mach-shark/include/mach/entry-macro.S
index 5901b09fc96a..c9e49f049532 100644
--- a/arch/arm/mach-shark/include/mach/entry-macro.S
+++ b/arch/arm/mach-shark/include/mach/entry-macro.S
@@ -8,7 +8,8 @@
 * warranty of any kind, whether express or implied.
 */
                .macro  get_irqnr_preamble, base, tmp
-                mov     \base, #0xe0000000
+                mov     \base, #0xfe000000
+                orr     \base, \base, #0x00e00000
                .endm
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h
deleted file mode 100644
index 1a45fc01ff1d..000000000000
--- a/arch/arm/mach-shark/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * arch/arm/mach-shark/include/mach/io.h
- *
- * by Alexander Schulz
- *
- * derived from:
- * arch/arm/mach-ebsa110/include/mach/io.h
- * Copyright (C) 1997,1998 Russell King
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-#define IO_SPACE_LIMIT 0xffffffff
-#define __io(a)                 ((void __iomem *)(0xe0000000 + (a)))
-#endif
diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c
index 25609076921f..081c778a10ac 100644
--- a/arch/arm/mach-shark/leds.c
+++ b/arch/arm/mach-shark/leds.c
@@ -1,165 +1,117 @@
 /*
- * arch/arm/mach-shark/leds.c
- * by Alexander Schulz
- *
- * derived from:
- * arch/arm/kernel/leds-footbridge.c
- * Copyright (C) 1998-1999 Russell King
- *
 * DIGITAL Shark LED control routines.
 *
- * The leds use is as follows:
+ * Driver for the 3 user LEDs found on the Shark
- *  - Green front - toggles state every 50 timer interrupts
+ * Based on Versatile and RealView machine LED code
- *  - Amber front - Unused, this is a dual color led (Amber/Green)
- *  - Amber back  - On if system is not idle
 *
- * Changelog:
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Bryan Wu <bryan.wu@canonical.com>
 */
 #include <linux/kernel.h>
-#include <linux/module.h>
 #include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/ioport.h>
 #include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
-#include <asm/leds.h>
+#include <asm/mach-types.h>
-#define LED_STATE_ENABLED       1
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
-#define LED_STATE_CLAIMED       2
+struct shark_led {
+        struct led_classdev cdev;
+        u8 mask;
+};
-#define SEQUOIA_LED_GREEN       (1<<6)
+/*
-#define SEQUOIA_LED_AMBER       (1<<5)
+ * The triggers lines up below will only be used if the
-#define SEQUOIA_LED_BACK        (1<<7)
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} shark_leds[] = {
+        { "shark:amber0", "default-on", },      /* Bit 5 */
+        { "shark:green", "heartbeat", },        /* Bit 6 */
+        { "shark:amber1", "cpu0" },             /* Bit 7 */
+};
+static u16 led_reg_read(void)
+{
+        outw(0x09, 0x24);
+        return inw(0x26);
+}
-static char led_state;
+static void led_reg_write(u16 value)
-static short hw_led_state;
+{
-static short saved_state;
+        outw(0x09, 0x24);
+        outw(value, 0x26);
+}
-static DEFINE_RAW_SPINLOCK(leds_lock);
+static void shark_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
+{
+        struct shark_led *led = container_of(cdev,
+                                                 struct shark_led, cdev);
+        u16 reg = led_reg_read();
-short sequoia_read(int addr) {
+        if (b != LED_OFF)
-  outw(addr,0x24);
+                reg |= led->mask;
-  return inw(0x26);
+        else
-}
+                reg &= ~led->mask;
-void sequoia_write(short value,short addr) {
+        led_reg_write(reg);
-  outw(addr,0x24);
-  outw(value,0x26);
 }
-static void sequoia_leds_event(led_event_t evt)
+static enum led_brightness shark_led_get(struct led_classdev *cdev)
 {
-        unsigned long flags;
+        struct shark_led *led = container_of(cdev,
+                                                 struct shark_led, cdev);
-        raw_spin_lock_irqsave(&leds_lock, flags);
+        u16 reg = led_reg_read();
-        hw_led_state = sequoia_read(0x09);
+        return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
-        switch (evt) {
+static int __init shark_leds_init(void)
-        case led_start:
+{
-                hw_led_state |= SEQUOIA_LED_GREEN;
+        int i;
-                hw_led_state |= SEQUOIA_LED_AMBER;
+        u16 reg;
-#ifdef CONFIG_LEDS_CPU
-                hw_led_state |= SEQUOIA_LED_BACK;
-#else
-                hw_led_state &= ~SEQUOIA_LED_BACK;
-#endif
-                led_state |= LED_STATE_ENABLED;
-                break;
-        case led_stop:
-                hw_led_state &= ~SEQUOIA_LED_BACK;
-                hw_led_state |= SEQUOIA_LED_GREEN;
-                hw_led_state |= SEQUOIA_LED_AMBER;
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                saved_state = hw_led_state;
-                hw_led_state &= ~SEQUOIA_LED_BACK;
-                hw_led_state |= SEQUOIA_LED_GREEN;
-                hw_led_state |= SEQUOIA_LED_AMBER;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = saved_state;
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= SEQUOIA_LED_GREEN;
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
+        if (!machine_is_shark())
-        case led_idle_start:
+                return -ENODEV;
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~SEQUOIA_LED_BACK;
-                break;
-        case led_idle_end:
+        for (i = 0; i < ARRAY_SIZE(shark_leds); i++) {
-                if (!(led_state & LED_STATE_CLAIMED))
+                struct shark_led *led;
-                        hw_led_state |= SEQUOIA_LED_BACK;
-                break;
-#endif
-        case led_green_on:
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
-                if (led_state & LED_STATE_CLAIMED)
+                if (!led)
-                        hw_led_state &= ~SEQUOIA_LED_GREEN;
+                        break;
-                break;
-        case led_green_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= SEQUOIA_LED_GREEN;
-                break;
-        case led_amber_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~SEQUOIA_LED_AMBER;
-                break;
-        case led_amber_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= SEQUOIA_LED_AMBER;
-                break;
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= SEQUOIA_LED_BACK;
-                break;
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~SEQUOIA_LED_BACK;
-                break;
-        default:
-                break;
-        }
-        if  (led_state & LED_STATE_ENABLED)
+                led->cdev.name = shark_leds[i].name;
-                sequoia_write(hw_led_state,0x09);
+                led->cdev.brightness_set = shark_led_set;
+                led->cdev.brightness_get = shark_led_get;
+                led->cdev.default_trigger = shark_leds[i].trigger;
-        raw_spin_unlock_irqrestore(&leds_lock, flags);
+                /* Count in 5 bits offset */
-}
+                led->mask = BIT(i + 5);
-static int __init leds_init(void)
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
-{
+                        kfree(led);
-        extern void (*leds_event)(led_event_t);
+                        break;
-        short temp;
+                }
-        
+        }
-        leds_event = sequoia_leds_event;
        /* Make LEDs independent of power-state */
-        request_region(0x24,4,"sequoia");
+        request_region(0x24, 4, "led_reg");
-        temp = sequoia_read(0x09);
+        reg = led_reg_read();
-        temp |= 1<<10;
+        reg |= 1 << 10;
-        sequoia_write(temp,0x09);
+        led_reg_write(reg);
-        leds_event(led_start);
        return 0;
 }
-__initcall(leds_init);
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(shark_leds_init);
+#endif
diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c
index 9089407d5326..6d91a914c1dd 100644
--- a/arch/arm/mach-shark/pci.c
+++ b/arch/arm/mach-shark/pci.c
@@ -8,12 +8,15 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <video/vga.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
+#define IO_START        0x40000000
 static int __init shark_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
        if (dev->bus->number == 0)
@@ -38,12 +41,14 @@ static struct hw_pci shark_pci __initdata = {
 static int __init shark_pci_init(void)
 {
        if (!machine_is_shark())
-                return;
+                return -ENODEV;
        pcibios_min_io = 0x6000;
        pcibios_min_mem = 0x50000000;
        vga_base = 0xe8000000;
+        pci_ioremap_io(0, IO_START);
        pci_common_init(&shark_pci);
        return 0;
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 0df5ae6740c6..fe2c97c179d1 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -3,7 +3,7 @@
 #
 # Common objects
-obj-y                           := timer.o console.o clock.o common.o
+obj-y                           := timer.o console.o clock.o
 # CPU objects
 obj-$(CONFIG_ARCH_SH7367)       += setup-sh7367.o clock-sh7367.o intc-sh7367.o
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index d82c010fdfc6..25eb88a923e6 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -40,7 +40,6 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/sh_clk.h>
-#include <linux/videodev2.h>
 #include <video/sh_mobile_lcdc.h>
 #include <video/sh_mipi_dsi.h>
 #include <sound/sh_fsi.h>
@@ -650,6 +649,7 @@ static void __init ag5evm_init(void)
 }
 MACHINE_START(AG5EVM, "ag5evm")
+        .smp            = smp_ops(sh73a0_smp_ops),
        .map_io         = sh73a0_map_io,
        .init_early     = sh73a0_add_early_devices,
        .nr_irqs        = NR_IRQS_LEGACY,
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index f172ca85905c..790dc68c4312 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -66,6 +66,8 @@
 #include <asm/mach/arch.h>
 #include <asm/setup.h>
+#include "sh-gpio.h"
 /*
 * Address      Interface               BusWidth        note
 * ------------------------------------------------------------------
@@ -432,7 +434,7 @@ static void usb1_host_port_power(int port, int power)
                return;
        /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
-        __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
+        __raw_writew(__raw_readw(IOMEM(0xE68B0008)) | 0x600, IOMEM(0xE68B0008));
 }
 static struct r8a66597_platdata usb1_host_data = {
@@ -1224,11 +1226,20 @@ static struct i2c_board_info i2c1_devices[] = {
 };
-#define GPIO_PORT9CR    0xE6051009
+#define GPIO_PORT9CR    IOMEM(0xE6051009)
-#define GPIO_PORT10CR   0xE605100A
+#define GPIO_PORT10CR   IOMEM(0xE605100A)
-#define USCCR1          0xE6058144
+#define USCCR1          IOMEM(0xE6058144)
 static void __init ap4evb_init(void)
 {
+        struct pm_domain_device domain_devices[] = {
+                { "A4LC", &lcdc1_device, },
+                { "A4LC", &lcdc_device, },
+                { "A4MP", &fsi_device, },
+                { "A3SP", &sh_mmcif_device, },
+                { "A3SP", &sdhi0_device, },
+                { "A3SP", &sdhi1_device, },
+                { "A4R", &ceu_device, },
+        };
        u32 srcr4;
        struct clk *clk;
@@ -1304,7 +1315,7 @@ static void __init ap4evb_init(void)
        gpio_request(GPIO_FN_OVCN2_1,    NULL);
        /* setup USB phy */
-        __raw_writew(0x8a0a, 0xE6058130);       /* USBCR4 */
+        __raw_writew(0x8a0a, IOMEM(0xE6058130));        /* USBCR4 */
        /* enable FSI2 port A (ak4643) */
        gpio_request(GPIO_FN_FSIAIBT,   NULL);
@@ -1453,7 +1464,7 @@ static void __init ap4evb_init(void)
        gpio_request(GPIO_FN_HDMI_CEC, NULL);
        /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
-#define SRCR4 0xe61580bc
+#define SRCR4 IOMEM(0xe61580bc)
        srcr4 = __raw_readl(SRCR4);
        __raw_writel(srcr4 | (1 << 13), SRCR4);
        udelay(50);
@@ -1461,14 +1472,8 @@ static void __init ap4evb_init(void)
        platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
-        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc1_device);
+        rmobile_add_devices_to_domains(domain_devices,
-        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device);
+                                       ARRAY_SIZE(domain_devices));
-        rmobile_add_device_to_domain(&sh7372_pd_a4mp, &fsi_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sh_mmcif_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &ceu_device);
        hdmi_init_pm_clock();
        fsi_init_pm_clock();
@@ -1483,6 +1488,6 @@ MACHINE_START(AP4EVB, "ap4evb")
        .init_irq       = sh7372_init_irq,
        .handle_irq     = shmobile_handle_irq_intc,
        .init_machine   = ap4evb_init,
-        .init_late      = shmobile_init_late,
+        .init_late      = sh7372_pm_init_late,
        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 453a6e50db8b..2912eab3b967 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -37,6 +37,7 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/i2c-gpio.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7740.h>
@@ -54,6 +55,8 @@
 #include <sound/sh_fsi.h>
 #include <sound/simple_card.h>
+#include "sh-gpio.h"
 /*
 * CON1         Camera Module
 * CON2         Extension Bus
@@ -135,7 +138,7 @@
 *      usbhsf_power_ctrl()
 */
 #define IRQ7            evt2irq(0x02e0)
-#define USBCR1          0xe605810a
+#define USBCR1          IOMEM(0xe605810a)
 #define USBH            0xC6700000
 #define USBH_USBCTR     0x10834
@@ -877,6 +880,21 @@ static struct platform_device fsi_hdmi_device = {
        },
 };
+/* RTC: RTC connects i2c-gpio. */
+static struct i2c_gpio_platform_data i2c_gpio_data = {
+        .sda_pin        = GPIO_PORT208,
+        .scl_pin        = GPIO_PORT91,
+        .udelay         = 5, /* 100 kHz */
+};
+static struct platform_device i2c_gpio_device = {
+        .name = "i2c-gpio",
+        .id = 2,
+        .dev = {
+                .platform_data = &i2c_gpio_data,
+        },
+};
 /* I2C */
 static struct i2c_board_info i2c0_devices[] = {
        {
@@ -888,6 +906,13 @@ static struct i2c_board_info i2c0_devices[] = {
        },
 };
+static struct i2c_board_info i2c2_devices[] = {
+        {
+                I2C_BOARD_INFO("s35390a", 0x30),
+                .type = "s35390a",
+        },
+};
 /*
 * board devices
 */
@@ -904,6 +929,7 @@ static struct platform_device *eva_devices[] __initdata = {
        &fsi_device,
        &fsi_wm8978_device,
        &fsi_hdmi_device,
+        &i2c_gpio_device,
 };
 static void __init eva_clock_init(void)
@@ -950,8 +976,8 @@ clock_error:
 /*
 * board init
 */
-#define GPIO_PORT7CR    0xe6050007
+#define GPIO_PORT7CR    IOMEM(0xe6050007)
-#define GPIO_PORT8CR    0xe6050008
+#define GPIO_PORT8CR    IOMEM(0xe6050008)
 static void __init eva_init(void)
 {
        struct platform_device *usb = NULL;
@@ -1174,6 +1200,7 @@ static void __init eva_init(void)
 #endif
        i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
+        i2c_register_board_info(2, i2c2_devices, ARRAY_SIZE(i2c2_devices));
        r8a7740_add_standard_devices();
@@ -1182,10 +1209,10 @@ static void __init eva_init(void)
        eva_clock_init();
-        rmobile_add_device_to_domain(&r8a7740_pd_a4lc, &lcdc0_device);
+        rmobile_add_device_to_domain("A4LC", &lcdc0_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a4lc, &hdmi_lcdc_device);
+        rmobile_add_device_to_domain("A4LC", &hdmi_lcdc_device);
        if (usb)
-                rmobile_add_device_to_domain(&r8a7740_pd_a3sp, usb);
+                rmobile_add_device_to_domain("A3SP", usb);
 }
 static void __init eva_earlytimer_init(void)
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index 4129008eae29..cb8c994e1430 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -108,12 +108,12 @@ static struct regulator_consumer_supply dummy_supplies[] = {
 #define FPGA_ETH_IRQ            (FPGA_IRQ0 + 15)
 static u16 bonito_fpga_read(u32 offset)
 {
-        return __raw_readw(0xf0003000 + offset);
+        return __raw_readw(IOMEM(0xf0003000) + offset);
 }
 static void bonito_fpga_write(u32 offset, u16 val)
 {
-        __raw_writew(val, 0xf0003000 + offset);
+        __raw_writew(val, IOMEM(0xf0003000) + offset);
 }
 static void bonito_fpga_irq_disable(struct irq_data *data)
@@ -361,8 +361,8 @@ static void __init bonito_map_io(void)
 #define BIT_ON(sw, bit)         (sw & (1 << bit))
 #define BIT_OFF(sw, bit)        (!(sw & (1 << bit)))
-#define VCCQ1CR         0xE6058140
+#define VCCQ1CR         IOMEM(0xE6058140)
-#define VCCQ1LCDCR      0xE6058186
+#define VCCQ1LCDCR      IOMEM(0xE6058186)
 static void __init bonito_init(void)
 {
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
index 796fa00ad3c4..b179d4c213bb 100644
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -106,7 +106,7 @@ static void usb_host_port_power(int port, int power)
                return;
        /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
-        __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008);
+        __raw_writew(__raw_readw(IOMEM(0xe6890008)) | 0x600, IOMEM(0xe6890008));
 }
 static struct r8a66597_platdata usb_host_data = {
@@ -279,10 +279,10 @@ static void __init g3evm_init(void)
        gpio_request(GPIO_FN_IDIN, NULL);
        /* setup USB phy */
-        __raw_writew(0x0300, 0xe605810a);       /* USBCR1 */
+        __raw_writew(0x0300, IOMEM(0xe605810a));        /* USBCR1 */
-        __raw_writew(0x00e0, 0xe60581c0);       /* CPFCH */
+        __raw_writew(0x00e0, IOMEM(0xe60581c0));        /* CPFCH */
-        __raw_writew(0x6010, 0xe60581c6);       /* CGPOSR */
+        __raw_writew(0x6010, IOMEM(0xe60581c6));        /* CGPOSR */
-        __raw_writew(0x8a0a, 0xe605810c);       /* USBCR2 */
+        __raw_writew(0x8a0a, IOMEM(0xe605810c));        /* USBCR2 */
        /* KEYSC @ CN7 */
        gpio_request(GPIO_FN_PORT42_KEYOUT0, NULL);
@@ -320,7 +320,7 @@ static void __init g3evm_init(void)
        gpio_request(GPIO_FN_WE0_XWR0_FWE, NULL);
        gpio_request(GPIO_FN_FRB, NULL);
        /* FOE, FCDE, FSC on dedicated pins */
-        __raw_writel(__raw_readl(0xe6158048) & ~(1 << 15), 0xe6158048);
+        __raw_writel(__raw_readl(IOMEM(0xe6158048)) & ~(1 << 15), IOMEM(0xe6158048));
        /* IrDA */
        gpio_request(GPIO_FN_IRDA_OUT, NULL);
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index fa5dfc5c8ed6..35c126caa4d8 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -42,6 +42,8 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include "sh-gpio.h"
 /*
 * SDHI
 *
@@ -126,7 +128,7 @@ static void usb_host_port_power(int port, int power)
                return;
        /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
-        __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008);
+        __raw_writew(__raw_readw(IOMEM(0xe6890008)) | 0x600, IOMEM(0xe6890008));
 }
 static struct r8a66597_platdata usb_host_data = {
@@ -270,17 +272,17 @@ static struct platform_device *g4evm_devices[] __initdata = {
        &sdhi1_device,
 };
-#define GPIO_SDHID0_D0  0xe60520fc
+#define GPIO_SDHID0_D0  IOMEM(0xe60520fc)
-#define GPIO_SDHID0_D1  0xe60520fd
+#define GPIO_SDHID0_D1  IOMEM(0xe60520fd)
-#define GPIO_SDHID0_D2  0xe60520fe
+#define GPIO_SDHID0_D2  IOMEM(0xe60520fe)
-#define GPIO_SDHID0_D3  0xe60520ff
+#define GPIO_SDHID0_D3  IOMEM(0xe60520ff)
-#define GPIO_SDHICMD0   0xe6052100
+#define GPIO_SDHICMD0   IOMEM(0xe6052100)
-#define GPIO_SDHID1_D0  0xe6052103
+#define GPIO_SDHID1_D0  IOMEM(0xe6052103)
-#define GPIO_SDHID1_D1  0xe6052104
+#define GPIO_SDHID1_D1  IOMEM(0xe6052104)
-#define GPIO_SDHID1_D2  0xe6052105
+#define GPIO_SDHID1_D2  IOMEM(0xe6052105)
-#define GPIO_SDHID1_D3  0xe6052106
+#define GPIO_SDHID1_D3  IOMEM(0xe6052106)
-#define GPIO_SDHICMD1   0xe6052107
+#define GPIO_SDHICMD1   IOMEM(0xe6052107)
 static void __init g4evm_init(void)
 {
@@ -318,10 +320,10 @@ static void __init g4evm_init(void)
        gpio_request(GPIO_FN_IDIN, NULL);
        /* setup USB phy */
-        __raw_writew(0x0200, 0xe605810a);       /* USBCR1 */
+        __raw_writew(0x0200, IOMEM(0xe605810a));       /* USBCR1 */
-        __raw_writew(0x00e0, 0xe60581c0);       /* CPFCH */
+        __raw_writew(0x00e0, IOMEM(0xe60581c0));       /* CPFCH */
-        __raw_writew(0x6010, 0xe60581c6);       /* CGPOSR */
+        __raw_writew(0x6010, IOMEM(0xe60581c6));       /* CGPOSR */
-        __raw_writew(0x8a0a, 0xe605810c);       /* USBCR2 */
+        __raw_writew(0x8a0a, IOMEM(0xe605810c));       /* USBCR2 */
        /* KEYSC @ CN31 */
        gpio_request(GPIO_FN_PORT60_KEYOUT5, NULL);
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index 21dbe54304d5..bf88f9a8b7ac 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -545,6 +545,7 @@ static void __init kota2_init(void)
 }
 MACHINE_START(KOTA2, "kota2")
+        .smp            = smp_ops(sh73a0_smp_ops),
        .map_io         = sh73a0_map_io,
        .init_early     = sh73a0_add_early_devices,
        .nr_irqs        = NR_IRQS_LEGACY,
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index 2c986eaae7b4..b52bc0d1273f 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -84,6 +84,7 @@ static const char *kzm9d_boards_compat_dt[] __initdata = {
 };
 DT_MACHINE_START(KZM9D_DT, "kzm9d")
+        .smp            = smp_ops(emev2_smp_ops),
        .map_io         = emev2_map_io,
        .init_early     = emev2_add_early_devices,
        .nr_irqs        = NR_IRQS_LEGACY,
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 3b8a0171c3cb..0a43f3189c21 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -133,8 +133,8 @@ static struct platform_device usb_host_device = {
 /* USB Func CN17 */
 struct usbhs_private {
-        unsigned int phy;
+        void __iomem *phy;
-        unsigned int cr2;
+        void __iomem *cr2;
        struct renesas_usbhs_platform_info info;
 };
@@ -232,8 +232,8 @@ static u32 usbhs_pipe_cfg[] = {
 };
 static struct usbhs_private usbhs_private = {
-        .phy    = 0xe60781e0,           /* USBPHYINT */
+        .phy    = IOMEM(0xe60781e0),            /* USBPHYINT */
-        .cr2    = 0xe605810c,           /* USBCR2 */
+        .cr2    = IOMEM(0xe605810c),            /* USBCR2 */
        .info = {
                .platform_callback = {
                        .hardware_init  = usbhs_hardware_init,
@@ -482,12 +482,10 @@ static struct gpio_keys_button gpio_buttons[] = {
 static struct gpio_keys_platform_data gpio_key_info = {
        .buttons        = gpio_buttons,
        .nbuttons       = ARRAY_SIZE(gpio_buttons),
-        .poll_interval  = 250, /* poling at this point */
 };
 static struct platform_device gpio_keys_device = {
-        /* gpio-pcf857x.c driver doesn't support gpio_to_irq() */
+        .name   = "gpio-keys",
-        .name   = "gpio-keys-polled",
        .dev    = {
                .platform_data  = &gpio_key_info,
        },
@@ -550,6 +548,7 @@ static struct platform_device fsi_ak4648_device = {
 /* I2C */
 static struct pcf857x_platform_data pcf8575_pdata = {
        .gpio_base      = GPIO_PCF8575_BASE,
+        .irq            = intcs_evt2irq(0x3260), /* IRQ19 */
 };
 static struct i2c_board_info i2c0_devices[] = {
@@ -763,12 +762,20 @@ static void __init kzm_init(void)
        platform_add_devices(kzm_devices, ARRAY_SIZE(kzm_devices));
 }
+static void kzm9g_restart(char mode, const char *cmd)
+{
+#define RESCNT2 IOMEM(0xe6188020)
+        /* Do soft power on reset */
+        writel((1 << 31), RESCNT2);
+}
 static const char *kzm9g_boards_compat_dt[] __initdata = {
        "renesas,kzm9g",
        NULL,
 };
 DT_MACHINE_START(KZM9G_DT, "kzm9g")
+        .smp            = smp_ops(sh73a0_smp_ops),
        .map_io         = sh73a0_map_io,
        .init_early     = sh73a0_add_early_devices,
        .nr_irqs        = NR_IRQS_LEGACY,
@@ -777,5 +784,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g")
        .init_machine   = kzm_init,
        .init_late      = shmobile_init_late,
        .timer          = &shmobile_timer,
+        .restart        = kzm9g_restart,
        .dt_compat      = kzm9g_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index c129542f6aed..0c27c810cf99 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -64,6 +64,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
+#include "sh-gpio.h"
 /*
 * Address      Interface               BusWidth        note
 * ------------------------------------------------------------------
@@ -583,8 +585,8 @@ out:
 #define USBHS0_POLL_INTERVAL (HZ * 5)
 struct usbhs_private {
-        unsigned int usbphyaddr;
+        void __iomem *usbphyaddr;
-        unsigned int usbcrcaddr;
+        void __iomem *usbcrcaddr;
        struct renesas_usbhs_platform_info info;
        struct delayed_work work;
        struct platform_device *pdev;
@@ -642,7 +644,7 @@ static void usbhs0_hardware_exit(struct platform_device *pdev)
 }
 static struct usbhs_private usbhs0_private = {
-        .usbcrcaddr     = 0xe605810c,           /* USBCR2 */
+        .usbcrcaddr     = IOMEM(0xe605810c),            /* USBCR2 */
        .info = {
                .platform_callback = {
                        .hardware_init  = usbhs0_hardware_init,
@@ -776,8 +778,8 @@ static u32 usbhs1_pipe_cfg[] = {
 };
 static struct usbhs_private usbhs1_private = {
-        .usbphyaddr     = 0xe60581e2,           /* USBPHY1INTAP */
+        .usbphyaddr     = IOMEM(0xe60581e2),    /* USBPHY1INTAP */
-        .usbcrcaddr     = 0xe6058130,           /* USBCR4 */
+        .usbcrcaddr     = IOMEM(0xe6058130),    /* USBCR4 */
        .info = {
                .platform_callback = {
                        .hardware_init  = usbhs1_hardware_init,
@@ -1402,14 +1404,30 @@ static struct i2c_board_info i2c1_devices[] = {
        },
 };
-#define GPIO_PORT9CR    0xE6051009
+#define GPIO_PORT9CR    IOMEM(0xE6051009)
-#define GPIO_PORT10CR   0xE605100A
+#define GPIO_PORT10CR   IOMEM(0xE605100A)
-#define GPIO_PORT167CR  0xE60520A7
+#define GPIO_PORT167CR  IOMEM(0xE60520A7)
-#define GPIO_PORT168CR  0xE60520A8
+#define GPIO_PORT168CR  IOMEM(0xE60520A8)
-#define SRCR4           0xe61580bc
+#define SRCR4           IOMEM(0xe61580bc)
-#define USCCR1          0xE6058144
+#define USCCR1          IOMEM(0xE6058144)
 static void __init mackerel_init(void)
 {
+        struct pm_domain_device domain_devices[] = {
+                { "A4LC", &lcdc_device, },
+                { "A4LC", &hdmi_lcdc_device, },
+                { "A4LC", &meram_device, },
+                { "A4MP", &fsi_device, },
+                { "A3SP", &usbhs0_device, },
+                { "A3SP", &usbhs1_device, },
+                { "A3SP", &nand_flash_device, },
+                { "A3SP", &sh_mmcif_device, },
+                { "A3SP", &sdhi0_device, },
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
+                { "A3SP", &sdhi1_device, },
+#endif
+                { "A3SP", &sdhi2_device, },
+                { "A4R", &ceu_device, },
+        };
        u32 srcr4;
        struct clk *clk;
@@ -1624,20 +1642,8 @@ static void __init mackerel_init(void)
        platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
-        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device);
+        rmobile_add_devices_to_domains(domain_devices,
-        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &hdmi_lcdc_device);
+                                       ARRAY_SIZE(domain_devices));
-        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &meram_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4mp, &fsi_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usbhs0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usbhs1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &nand_flash_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sh_mmcif_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi0_device);
-#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi1_device);
-#endif
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi2_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &ceu_device);
        hdmi_init_pm_clock();
        sh7372_pm_init();
@@ -1651,6 +1657,6 @@ MACHINE_START(MACKEREL, "mackerel")
        .init_irq       = sh7372_init_irq,
        .handle_irq     = shmobile_handle_irq_intc,
        .init_machine   = mackerel_init,
-        .init_late      = shmobile_init_late,
+        .init_late      = sh7372_pm_init_late,
        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index fcf5a47f4772..b8a7525a4e2f 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -30,6 +30,8 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/mfd/tmio.h>
 #include <mach/hardware.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -39,6 +41,12 @@
 #include <asm/hardware/gic.h>
 #include <asm/traps.h>
+/* Fixed 3.3V regulator to be used by SDHI0 */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
 /* Dummy supplies, where voltage doesn't matter */
 static struct regulator_consumer_supply dummy_supplies[] = {
        REGULATOR_SUPPLY("vddvario", "smsc911x"),
@@ -75,13 +83,61 @@ static struct platform_device eth_device = {
        .num_resources  = ARRAY_SIZE(smsc911x_resources),
 };
+static struct resource sdhi0_resources[] = {
+        [0] = {
+                .name   = "sdhi0",
+                .start  = 0xffe4c000,
+                .end    = 0xffe4c0ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(104),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct sh_mobile_sdhi_info sdhi0_platform_data = {
+        .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
+        .tmio_caps = MMC_CAP_SD_HIGHSPEED,
+};
+static struct platform_device sdhi0_device = {
+        .name = "sh_mobile_sdhi",
+        .num_resources = ARRAY_SIZE(sdhi0_resources),
+        .resource = sdhi0_resources,
+        .id = 0,
+        .dev = {
+                .platform_data = &sdhi0_platform_data,
+        }
+};
+/* Thermal */
+static struct resource thermal_resources[] = {
+        [0] = {
+                .start          = 0xFFC48000,
+                .end            = 0xFFC48038 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+static struct platform_device thermal_device = {
+        .name           = "rcar_thermal",
+        .resource       = thermal_resources,
+        .num_resources  = ARRAY_SIZE(thermal_resources),
+};
 static struct platform_device *marzen_devices[] __initdata = {
        &eth_device,
+        &sdhi0_device,
+        &thermal_device,
 };
 static void __init marzen_init(void)
 {
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+        regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
+                                ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+        regulator_register_fixed(1, dummy_supplies,
+                                ARRAY_SIZE(dummy_supplies));
        r8a7779_pinmux_init();
@@ -97,11 +153,22 @@ static void __init marzen_init(void)
        gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
        gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
+        /* SD0 (CN20) */
+        gpio_request(GPIO_FN_SD0_CLK, NULL);
+        gpio_request(GPIO_FN_SD0_CMD, NULL);
+        gpio_request(GPIO_FN_SD0_DAT0, NULL);
+        gpio_request(GPIO_FN_SD0_DAT1, NULL);
+        gpio_request(GPIO_FN_SD0_DAT2, NULL);
+        gpio_request(GPIO_FN_SD0_DAT3, NULL);
+        gpio_request(GPIO_FN_SD0_CD, NULL);
+        gpio_request(GPIO_FN_SD0_WP, NULL);
        r8a7779_add_standard_devices();
        platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
 }
 MACHINE_START(MARZEN, "marzen")
+        .smp            = smp_ops(r8a7779_smp_ops),
        .map_io         = r8a7779_map_io,
        .init_early     = r8a7779_add_early_devices,
        .nr_irqs        = NR_IRQS_LEGACY,
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index ad5fccc7b5e7..6729e0032180 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -41,29 +41,29 @@
 */
 /* CPG registers */
-#define FRQCRA          0xe6150000
+#define FRQCRA          IOMEM(0xe6150000)
-#define FRQCRB          0xe6150004
+#define FRQCRB          IOMEM(0xe6150004)
-#define VCLKCR1         0xE6150008
+#define VCLKCR1         IOMEM(0xE6150008)
-#define VCLKCR2         0xE615000c
+#define VCLKCR2         IOMEM(0xE615000c)
-#define FRQCRC          0xe61500e0
+#define FRQCRC          IOMEM(0xe61500e0)
-#define FSIACKCR        0xe6150018
+#define FSIACKCR        IOMEM(0xe6150018)
-#define PLLC01CR        0xe6150028
+#define PLLC01CR        IOMEM(0xe6150028)
-#define SUBCKCR         0xe6150080
+#define SUBCKCR         IOMEM(0xe6150080)
-#define USBCKCR         0xe615008c
+#define USBCKCR         IOMEM(0xe615008c)
-#define MSTPSR0         0xe6150030
+#define MSTPSR0         IOMEM(0xe6150030)
-#define MSTPSR1         0xe6150038
+#define MSTPSR1         IOMEM(0xe6150038)
-#define MSTPSR2         0xe6150040
+#define MSTPSR2         IOMEM(0xe6150040)
-#define MSTPSR3         0xe6150048
+#define MSTPSR3         IOMEM(0xe6150048)
-#define MSTPSR4         0xe615004c
+#define MSTPSR4         IOMEM(0xe615004c)
-#define FSIBCKCR        0xe6150090
+#define FSIBCKCR        IOMEM(0xe6150090)
-#define HDMICKCR        0xe6150094
+#define HDMICKCR        IOMEM(0xe6150094)
-#define SMSTPCR0        0xe6150130
+#define SMSTPCR0        IOMEM(0xe6150130)
-#define SMSTPCR1        0xe6150134
+#define SMSTPCR1        IOMEM(0xe6150134)
-#define SMSTPCR2        0xe6150138
+#define SMSTPCR2        IOMEM(0xe6150138)
-#define SMSTPCR3        0xe615013c
+#define SMSTPCR3        IOMEM(0xe615013c)
-#define SMSTPCR4        0xe6150140
+#define SMSTPCR4        IOMEM(0xe6150140)
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk extalr_clk = {
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 339c62c824d5..3cafb6ab5e9a 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -86,11 +86,16 @@ static struct clk div4_clks[DIV4_NR] = {
                                      0x0300, CLK_ENABLE_ON_INIT),
 };
-enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
+enum { MSTP323, MSTP322, MSTP321, MSTP320,
+        MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
        MSTP016, MSTP015, MSTP014,
        MSTP_NR };
 static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */
+        [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
+        [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
+        [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
        [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
        [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
        [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
@@ -149,6 +154,10 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
 };
 void __init r8a7779_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
index 162b791b8984..ef0a95e592c4 100644
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -24,28 +24,28 @@
 #include <mach/common.h>
 /* SH7367 registers */
-#define RTFRQCR    0xe6150000
+#define RTFRQCR    IOMEM(0xe6150000)
-#define SYFRQCR    0xe6150004
+#define SYFRQCR    IOMEM(0xe6150004)
-#define CMFRQCR    0xe61500E0
+#define CMFRQCR    IOMEM(0xe61500E0)
-#define VCLKCR1    0xe6150008
+#define VCLKCR1    IOMEM(0xe6150008)
-#define VCLKCR2    0xe615000C
+#define VCLKCR2    IOMEM(0xe615000C)
-#define VCLKCR3    0xe615001C
+#define VCLKCR3    IOMEM(0xe615001C)
-#define SCLKACR    0xe6150010
+#define SCLKACR    IOMEM(0xe6150010)
-#define SCLKBCR    0xe6150014
+#define SCLKBCR    IOMEM(0xe6150014)
-#define SUBUSBCKCR 0xe6158080
+#define SUBUSBCKCR IOMEM(0xe6158080)
-#define SPUCKCR    0xe6150084
+#define SPUCKCR    IOMEM(0xe6150084)
-#define MSUCKCR    0xe6150088
+#define MSUCKCR    IOMEM(0xe6150088)
-#define MVI3CKCR   0xe6150090
+#define MVI3CKCR   IOMEM(0xe6150090)
-#define VOUCKCR    0xe6150094
+#define VOUCKCR    IOMEM(0xe6150094)
-#define MFCK1CR    0xe6150098
+#define MFCK1CR    IOMEM(0xe6150098)
-#define MFCK2CR    0xe615009C
+#define MFCK2CR    IOMEM(0xe615009C)
-#define PLLC1CR    0xe6150028
+#define PLLC1CR    IOMEM(0xe6150028)
-#define PLLC2CR    0xe615002C
+#define PLLC2CR    IOMEM(0xe615002C)
-#define RTMSTPCR0  0xe6158030
+#define RTMSTPCR0  IOMEM(0xe6158030)
-#define RTMSTPCR2  0xe6158038
+#define RTMSTPCR2  IOMEM(0xe6158038)
-#define SYMSTPCR0  0xe6158040
+#define SYMSTPCR0  IOMEM(0xe6158040)
-#define SYMSTPCR2  0xe6158048
+#define SYMSTPCR2  IOMEM(0xe6158048)
-#define CMMSTPCR0  0xe615804c
+#define CMMSTPCR0  IOMEM(0xe615804c)
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk r_clk = {
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 5a2894b1c965..430a90ffa120 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -24,36 +24,36 @@
 #include <mach/common.h>
 /* SH7372 registers */
-#define FRQCRA          0xe6150000
+#define FRQCRA          IOMEM(0xe6150000)
-#define FRQCRB          0xe6150004
+#define FRQCRB          IOMEM(0xe6150004)
-#define FRQCRC          0xe61500e0
+#define FRQCRC          IOMEM(0xe61500e0)
-#define FRQCRD          0xe61500e4
+#define FRQCRD          IOMEM(0xe61500e4)
-#define VCLKCR1         0xe6150008
+#define VCLKCR1         IOMEM(0xe6150008)
-#define VCLKCR2         0xe615000c
+#define VCLKCR2         IOMEM(0xe615000c)
-#define VCLKCR3         0xe615001c
+#define VCLKCR3         IOMEM(0xe615001c)
-#define FMSICKCR        0xe6150010
+#define FMSICKCR        IOMEM(0xe6150010)
-#define FMSOCKCR        0xe6150014
+#define FMSOCKCR        IOMEM(0xe6150014)
-#define FSIACKCR        0xe6150018
+#define FSIACKCR        IOMEM(0xe6150018)
-#define FSIBCKCR        0xe6150090
+#define FSIBCKCR        IOMEM(0xe6150090)
-#define SUBCKCR         0xe6150080
+#define SUBCKCR         IOMEM(0xe6150080)
-#define SPUCKCR         0xe6150084
+#define SPUCKCR         IOMEM(0xe6150084)
-#define VOUCKCR         0xe6150088
+#define VOUCKCR         IOMEM(0xe6150088)
-#define HDMICKCR        0xe6150094
+#define HDMICKCR        IOMEM(0xe6150094)
-#define DSITCKCR        0xe6150060
+#define DSITCKCR        IOMEM(0xe6150060)
-#define DSI0PCKCR       0xe6150064
+#define DSI0PCKCR       IOMEM(0xe6150064)
-#define DSI1PCKCR       0xe6150098
+#define DSI1PCKCR       IOMEM(0xe6150098)
-#define PLLC01CR        0xe6150028
+#define PLLC01CR        IOMEM(0xe6150028)
-#define PLLC2CR         0xe615002c
+#define PLLC2CR         IOMEM(0xe615002c)
-#define RMSTPCR0        0xe6150110
+#define RMSTPCR0        IOMEM(0xe6150110)
-#define RMSTPCR1        0xe6150114
+#define RMSTPCR1        IOMEM(0xe6150114)
-#define RMSTPCR2        0xe6150118
+#define RMSTPCR2        IOMEM(0xe6150118)
-#define RMSTPCR3        0xe615011c
+#define RMSTPCR3        IOMEM(0xe615011c)
-#define RMSTPCR4        0xe6150120
+#define RMSTPCR4        IOMEM(0xe6150120)
-#define SMSTPCR0        0xe6150130
+#define SMSTPCR0        IOMEM(0xe6150130)
-#define SMSTPCR1        0xe6150134
+#define SMSTPCR1        IOMEM(0xe6150134)
-#define SMSTPCR2        0xe6150138
+#define SMSTPCR2        IOMEM(0xe6150138)
-#define SMSTPCR3        0xe615013c
+#define SMSTPCR3        IOMEM(0xe615013c)
-#define SMSTPCR4        0xe6150140
+#define SMSTPCR4        IOMEM(0xe6150140)
 #define FSIDIVA         0xFE1F8000
 #define FSIDIVB         0xFE1F8008
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
index 85f2a3ec2c44..b8480d19e1c8 100644
--- a/arch/arm/mach-shmobile/clock-sh7377.c
+++ b/arch/arm/mach-shmobile/clock-sh7377.c
@@ -24,31 +24,31 @@
 #include <mach/common.h>
 /* SH7377 registers */
-#define RTFRQCR    0xe6150000
+#define RTFRQCR    IOMEM(0xe6150000)
-#define SYFRQCR    0xe6150004
+#define SYFRQCR    IOMEM(0xe6150004)
-#define CMFRQCR    0xe61500E0
+#define CMFRQCR    IOMEM(0xe61500E0)
-#define VCLKCR1    0xe6150008
+#define VCLKCR1    IOMEM(0xe6150008)
-#define VCLKCR2    0xe615000C
+#define VCLKCR2    IOMEM(0xe615000C)
-#define VCLKCR3    0xe615001C
+#define VCLKCR3    IOMEM(0xe615001C)
-#define FMSICKCR   0xe6150010
+#define FMSICKCR   IOMEM(0xe6150010)
-#define FMSOCKCR   0xe6150014
+#define FMSOCKCR   IOMEM(0xe6150014)
-#define FSICKCR    0xe6150018
+#define FSICKCR    IOMEM(0xe6150018)
-#define PLLC1CR    0xe6150028
+#define PLLC1CR    IOMEM(0xe6150028)
-#define PLLC2CR    0xe615002C
+#define PLLC2CR    IOMEM(0xe615002C)
-#define SUBUSBCKCR 0xe6150080
+#define SUBUSBCKCR IOMEM(0xe6150080)
-#define SPUCKCR    0xe6150084
+#define SPUCKCR    IOMEM(0xe6150084)
-#define MSUCKCR    0xe6150088
+#define MSUCKCR    IOMEM(0xe6150088)
-#define MVI3CKCR   0xe6150090
+#define MVI3CKCR   IOMEM(0xe6150090)
-#define HDMICKCR   0xe6150094
+#define HDMICKCR   IOMEM(0xe6150094)
-#define MFCK1CR    0xe6150098
+#define MFCK1CR    IOMEM(0xe6150098)
-#define MFCK2CR    0xe615009C
+#define MFCK2CR    IOMEM(0xe615009C)
-#define DSITCKCR   0xe6150060
+#define DSITCKCR   IOMEM(0xe6150060)
-#define DSIPCKCR   0xe6150064
+#define DSIPCKCR   IOMEM(0xe6150064)
-#define SMSTPCR0   0xe6150130
+#define SMSTPCR0   IOMEM(0xe6150130)
-#define SMSTPCR1   0xe6150134
+#define SMSTPCR1   IOMEM(0xe6150134)
-#define SMSTPCR2   0xe6150138
+#define SMSTPCR2   IOMEM(0xe6150138)
-#define SMSTPCR3   0xe615013C
+#define SMSTPCR3   IOMEM(0xe615013C)
-#define SMSTPCR4   0xe6150140
+#define SMSTPCR4   IOMEM(0xe6150140)
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk r_clk = {
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 7f8da18a8580..516ff7f3e434 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -23,43 +23,43 @@
 #include <linux/clkdev.h>
 #include <mach/common.h>
-#define FRQCRA          0xe6150000
+#define FRQCRA          IOMEM(0xe6150000)
-#define FRQCRB          0xe6150004
+#define FRQCRB          IOMEM(0xe6150004)
-#define FRQCRD          0xe61500e4
+#define FRQCRD          IOMEM(0xe61500e4)
-#define VCLKCR1         0xe6150008
+#define VCLKCR1         IOMEM(0xe6150008)
-#define VCLKCR2         0xe615000C
+#define VCLKCR2         IOMEM(0xe615000C)
-#define VCLKCR3         0xe615001C
+#define VCLKCR3         IOMEM(0xe615001C)
-#define ZBCKCR          0xe6150010
+#define ZBCKCR          IOMEM(0xe6150010)
-#define FLCKCR          0xe6150014
+#define FLCKCR          IOMEM(0xe6150014)
-#define SD0CKCR         0xe6150074
+#define SD0CKCR         IOMEM(0xe6150074)
-#define SD1CKCR         0xe6150078
+#define SD1CKCR         IOMEM(0xe6150078)
-#define SD2CKCR         0xe615007C
+#define SD2CKCR         IOMEM(0xe615007C)
-#define FSIACKCR        0xe6150018
+#define FSIACKCR        IOMEM(0xe6150018)
-#define FSIBCKCR        0xe6150090
+#define FSIBCKCR        IOMEM(0xe6150090)
-#define SUBCKCR         0xe6150080
+#define SUBCKCR         IOMEM(0xe6150080)
-#define SPUACKCR        0xe6150084
+#define SPUACKCR        IOMEM(0xe6150084)
-#define SPUVCKCR        0xe6150094
+#define SPUVCKCR        IOMEM(0xe6150094)
-#define MSUCKCR         0xe6150088
+#define MSUCKCR         IOMEM(0xe6150088)
-#define HSICKCR         0xe615008C
+#define HSICKCR         IOMEM(0xe615008C)
-#define MFCK1CR         0xe6150098
+#define MFCK1CR         IOMEM(0xe6150098)
-#define MFCK2CR         0xe615009C
+#define MFCK2CR         IOMEM(0xe615009C)
-#define DSITCKCR        0xe6150060
+#define DSITCKCR        IOMEM(0xe6150060)
-#define DSI0PCKCR       0xe6150064
+#define DSI0PCKCR       IOMEM(0xe6150064)
-#define DSI1PCKCR       0xe6150068
+#define DSI1PCKCR       IOMEM(0xe6150068)
 #define DSI0PHYCR       0xe615006C
 #define DSI1PHYCR       0xe6150070
-#define PLLECR          0xe61500d0
+#define PLLECR          IOMEM(0xe61500d0)
-#define PLL0CR          0xe61500d8
+#define PLL0CR          IOMEM(0xe61500d8)
-#define PLL1CR          0xe6150028
+#define PLL1CR          IOMEM(0xe6150028)
-#define PLL2CR          0xe615002c
+#define PLL2CR          IOMEM(0xe615002c)
-#define PLL3CR          0xe61500dc
+#define PLL3CR          IOMEM(0xe61500dc)
-#define SMSTPCR0        0xe6150130
+#define SMSTPCR0        IOMEM(0xe6150130)
-#define SMSTPCR1        0xe6150134
+#define SMSTPCR1        IOMEM(0xe6150134)
-#define SMSTPCR2        0xe6150138
+#define SMSTPCR2        IOMEM(0xe6150138)
-#define SMSTPCR3        0xe615013c
+#define SMSTPCR3        IOMEM(0xe615013c)
-#define SMSTPCR4        0xe6150140
+#define SMSTPCR4        IOMEM(0xe6150140)
-#define SMSTPCR5        0xe6150144
+#define SMSTPCR5        IOMEM(0xe6150144)
-#define CKSCR           0xe61500c0
+#define CKSCR           IOMEM(0xe61500c0)
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk r_clk = {
diff --git a/arch/arm/mach-shmobile/common.c b/arch/arm/mach-shmobile/common.c
deleted file mode 100644
index 608aba9d60d7..000000000000
--- a/arch/arm/mach-shmobile/common.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <mach/common.h>
-void __init shmobile_init_late(void)
-{
-        shmobile_suspend_init();
-        shmobile_cpuidle_init();
-}
diff --git a/arch/arm/mach-shmobile/cpuidle.c b/arch/arm/mach-shmobile/cpuidle.c
index 7b541e911ab4..9e050268cde4 100644
--- a/arch/arm/mach-shmobile/cpuidle.c
+++ b/arch/arm/mach-shmobile/cpuidle.c
@@ -16,51 +16,38 @@
 #include <asm/cpuidle.h>
 #include <asm/io.h>
-static void shmobile_enter_wfi(void)
+int shmobile_enter_wfi(struct cpuidle_device *dev, struct cpuidle_driver *drv,
+                       int index)
 {
        cpu_do_idle();
-}
+        return 0;
-void (*shmobile_cpuidle_modes[CPUIDLE_STATE_MAX])(void) = {
-        shmobile_enter_wfi, /* regular sleep mode */
-};
-static int shmobile_cpuidle_enter(struct cpuidle_device *dev,
-                                  struct cpuidle_driver *drv,
-                                  int index)
-{
-        shmobile_cpuidle_modes[index]();
-        return index;
 }
 static struct cpuidle_device shmobile_cpuidle_dev;
-static struct cpuidle_driver shmobile_cpuidle_driver = {
+static struct cpuidle_driver shmobile_cpuidle_default_driver = {
        .name                   = "shmobile_cpuidle",
        .owner                  = THIS_MODULE,
        .en_core_tk_irqen       = 1,
        .states[0]              = ARM_CPUIDLE_WFI_STATE,
+        .states[0].enter        = shmobile_enter_wfi,
        .safe_state_index       = 0, /* C1 */
        .state_count            = 1,
 };
-void (*shmobile_cpuidle_setup)(struct cpuidle_driver *drv);
+static struct cpuidle_driver *cpuidle_drv = &shmobile_cpuidle_default_driver;
+void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv)
+{
+        cpuidle_drv = drv;
+}
 int shmobile_cpuidle_init(void)
 {
        struct cpuidle_device *dev = &shmobile_cpuidle_dev;
-        struct cpuidle_driver *drv = &shmobile_cpuidle_driver;
-        int i;
-        for (i = 0; i < CPUIDLE_STATE_MAX; i++)
-                drv->states[i].enter = shmobile_cpuidle_enter;
-        if (shmobile_cpuidle_setup)
-                shmobile_cpuidle_setup(drv);
-        cpuidle_register_driver(drv);
+        cpuidle_register_driver(cpuidle_drv);
-        dev->state_count = drv->state_count;
+        dev->state_count = cpuidle_drv->state_count;
        cpuidle_register_device(dev);
        return 0;
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
index 828d22f3af57..b09a0bdbf813 100644
--- a/arch/arm/mach-shmobile/hotplug.c
+++ b/arch/arm/mach-shmobile/hotplug.c
@@ -14,30 +14,16 @@
 #include <linux/smp.h>
 #include <linux/cpumask.h>
 #include <linux/delay.h>
+#include <linux/of.h>
 #include <mach/common.h>
+#include <mach/r8a7779.h>
+#include <mach/emev2.h>
 #include <asm/cacheflush.h>
+#include <asm/mach-types.h>
 static cpumask_t dead_cpus;
-int platform_cpu_kill(unsigned int cpu)
+void shmobile_cpu_die(unsigned int cpu)
-{
-        int k;
-        /* this function is running on another CPU than the offline target,
-         * here we need wait for shutdown code in platform_cpu_die() to
-         * finish before asking SoC-specific code to power off the CPU core.
-         */
-        for (k = 0; k < 1000; k++) {
-                if (cpumask_test_cpu(cpu, &dead_cpus))
-                        return shmobile_platform_cpu_kill(cpu);
-                mdelay(1);
-        }
-        return 0;
-}
-void platform_cpu_die(unsigned int cpu)
 {
        /* hardware shutdown code running on the CPU that is being offlined */
        flush_cache_all();
@@ -60,7 +46,7 @@ void platform_cpu_die(unsigned int cpu)
        }
 }
-int platform_cpu_disable(unsigned int cpu)
+int shmobile_cpu_disable(unsigned int cpu)
 {
        cpumask_clear_cpu(cpu, &dead_cpus);
        /*
@@ -69,3 +55,8 @@ int platform_cpu_disable(unsigned int cpu)
         */
        return cpu == 0 ? -EPERM : 0;
 }
+int shmobile_cpu_is_dead(unsigned int cpu)
+{
+        return cpumask_test_cpu(cpu, &dead_cpus);
+}
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 45e61dada030..d47e215aca87 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -4,18 +4,19 @@
 extern void shmobile_earlytimer_init(void);
 extern struct sys_timer shmobile_timer;
 extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
-                                 unsigned int mult, unsigned int div);
+                         unsigned int mult, unsigned int div);
 struct twd_local_timer;
 extern void shmobile_setup_console(void);
 extern void shmobile_secondary_vector(void);
-extern int shmobile_platform_cpu_kill(unsigned int cpu);
 struct clk;
 extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
 extern struct platform_suspend_ops shmobile_suspend_ops;
 struct cpuidle_driver;
-extern void (*shmobile_cpuidle_modes[])(void);
+struct cpuidle_device;
-extern void (*shmobile_cpuidle_setup)(struct cpuidle_driver *drv);
+extern int shmobile_enter_wfi(struct cpuidle_device *dev,
+                              struct cpuidle_driver *drv, int index);
+extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
 extern void sh7367_init_irq(void);
 extern void sh7367_map_io(void);
@@ -58,11 +59,6 @@ extern struct clk sh73a0_extal2_clk;
 extern struct clk sh73a0_extcki_clk;
 extern struct clk sh73a0_extalr_clk;
-extern unsigned int sh73a0_get_core_count(void);
-extern void sh73a0_secondary_init(unsigned int cpu);
-extern int sh73a0_boot_secondary(unsigned int cpu);
-extern void sh73a0_smp_prepare_cpus(void);
 extern void r8a7740_init_irq(void);
 extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
@@ -79,15 +75,8 @@ extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
 extern void r8a7740_meram_workaround(void);
-extern unsigned int r8a7779_get_core_count(void);
-extern int r8a7779_platform_cpu_kill(unsigned int cpu);
-extern void r8a7779_secondary_init(unsigned int cpu);
-extern int r8a7779_boot_secondary(unsigned int cpu);
-extern void r8a7779_smp_prepare_cpus(void);
 extern void r8a7779_register_twd(void);
-extern void shmobile_init_late(void);
 #ifdef CONFIG_SUSPEND
 int shmobile_suspend_init(void);
 #else
@@ -100,4 +89,21 @@ int shmobile_cpuidle_init(void);
 static inline int shmobile_cpuidle_init(void) { return 0; }
 #endif
+extern void shmobile_cpu_die(unsigned int cpu);
+extern int shmobile_cpu_disable(unsigned int cpu);
+#ifdef CONFIG_HOTPLUG_CPU
+extern int shmobile_cpu_is_dead(unsigned int cpu);
+#else
+static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
+#endif
+extern void shmobile_smp_init_cpus(unsigned int ncores);
+static inline void __init shmobile_init_late(void)
+{
+        shmobile_suspend_init();
+        shmobile_cpuidle_init();
+}
 #endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h
index e6b0c1bf4b7e..ac3751705cab 100644
--- a/arch/arm/mach-shmobile/include/mach/emev2.h
+++ b/arch/arm/mach-shmobile/include/mach/emev2.h
@@ -7,13 +7,10 @@ extern void emev2_add_early_devices(void);
 extern void emev2_add_standard_devices(void);
 extern void emev2_clock_init(void);
 extern void emev2_set_boot_vector(unsigned long value);
-extern unsigned int emev2_get_core_count(void);
-extern int emev2_platform_cpu_kill(unsigned int cpu);
-extern void emev2_secondary_init(unsigned int cpu);
-extern int emev2_boot_secondary(unsigned int cpu);
-extern void emev2_smp_prepare_cpus(void);
 #define EMEV2_GPIO_BASE 200
 #define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n))
+extern struct smp_operations emev2_smp_ops;
 #endif /* __ASM_EMEV2_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/pm-rmobile.h b/arch/arm/mach-shmobile/include/mach/pm-rmobile.h
index 5a402840fe28..690553a06887 100644
--- a/arch/arm/mach-shmobile/include/mach/pm-rmobile.h
+++ b/arch/arm/mach-shmobile/include/mach/pm-rmobile.h
@@ -12,6 +12,8 @@
 #include <linux/pm_domain.h>
+#define DEFAULT_DEV_LATENCY_NS  250000
 struct platform_device;
 struct rmobile_pm_domain {
@@ -29,16 +31,33 @@ struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d)
        return container_of(d, struct rmobile_pm_domain, genpd);
 }
+struct pm_domain_device {
+        const char *domain_name;
+        struct platform_device *pdev;
+};
 #ifdef CONFIG_PM
-extern void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd);
+extern void rmobile_init_domains(struct rmobile_pm_domain domains[], int num);
-extern void rmobile_add_device_to_domain(struct rmobile_pm_domain *rmobile_pd,
+extern void rmobile_add_device_to_domain_td(const char *domain_name,
-                                        struct platform_device *pdev);
+                                            struct platform_device *pdev,
-extern void rmobile_pm_add_subdomain(struct rmobile_pm_domain *rmobile_pd,
+                                            struct gpd_timing_data *td);
-                                    struct rmobile_pm_domain *rmobile_sd);
+static inline void rmobile_add_device_to_domain(const char *domain_name,
+                                                struct platform_device *pdev)
+{
+        rmobile_add_device_to_domain_td(domain_name, pdev, NULL);
+}
+extern void rmobile_add_devices_to_domains(struct pm_domain_device data[],
+                                           int size);
 #else
-#define rmobile_init_pm_domain(pd) do { } while (0)
-#define rmobile_add_device_to_domain(pd, pdev) do { } while (0)
+#define rmobile_init_domains(domains, num) do { } while (0)
-#define rmobile_pm_add_subdomain(pd, sd) do { } while (0)
+#define rmobile_add_device_to_domain_td(name, pdev, td) do { } while (0)
+#define rmobile_add_device_to_domain(name, pdev) do { } while (0)
+static inline void rmobile_add_devices_to_domains(struct pm_domain_device d[],
+                                                  int size) {}
 #endif /* CONFIG_PM */
 #endif /* PM_RMOBILE_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 7143147780df..59d252f4cf97 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -607,9 +607,9 @@ enum {
 };
 #ifdef CONFIG_PM
-extern struct rmobile_pm_domain r8a7740_pd_a4s;
+extern void __init r8a7740_init_pm_domains(void);
-extern struct rmobile_pm_domain r8a7740_pd_a3sp;
+#else
-extern struct rmobile_pm_domain r8a7740_pd_a4lc;
+static inline void r8a7740_init_pm_domains(void) {}
 #endif /* CONFIG_PM */
 #endif /* __ASM_R8A7740_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index b07ad318eb2e..499f52d2a4a1 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -347,17 +347,11 @@ extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
 extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
 #ifdef CONFIG_PM
-extern struct r8a7779_pm_domain r8a7779_sh4a;
+extern void __init r8a7779_init_pm_domains(void);
-extern struct r8a7779_pm_domain r8a7779_sgx;
-extern struct r8a7779_pm_domain r8a7779_vdp1;
-extern struct r8a7779_pm_domain r8a7779_impx3;
-extern void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd);
-extern void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
-                                        struct platform_device *pdev);
 #else
-#define r8a7779_init_pm_domain(pd) do { } while (0)
+static inline void r8a7779_init_pm_domains(void) {}
-#define r8a7779_add_device_to_domain(pd, pdev) do { } while (0)
 #endif /* CONFIG_PM */
+extern struct smp_operations r8a7779_smp_ops;
 #endif /* __ASM_R8A7779_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index b59048e6d8fd..eb98b45c5089 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -478,21 +478,17 @@ extern struct clk sh7372_fsibck_clk;
 extern struct clk sh7372_fsidiva_clk;
 extern struct clk sh7372_fsidivb_clk;
-#ifdef CONFIG_PM
-extern struct rmobile_pm_domain sh7372_pd_a4lc;
-extern struct rmobile_pm_domain sh7372_pd_a4mp;
-extern struct rmobile_pm_domain sh7372_pd_d4;
-extern struct rmobile_pm_domain sh7372_pd_a4r;
-extern struct rmobile_pm_domain sh7372_pd_a3rv;
-extern struct rmobile_pm_domain sh7372_pd_a3ri;
-extern struct rmobile_pm_domain sh7372_pd_a4s;
-extern struct rmobile_pm_domain sh7372_pd_a3sp;
-extern struct rmobile_pm_domain sh7372_pd_a3sg;
-#endif /* CONFIG_PM */
 extern void sh7372_intcs_suspend(void);
 extern void sh7372_intcs_resume(void);
 extern void sh7372_intca_suspend(void);
 extern void sh7372_intca_resume(void);
+#ifdef CONFIG_PM
+extern void __init sh7372_init_pm_domains(void);
+#else
+static inline void sh7372_init_pm_domains(void) {}
+#endif
+extern void __init sh7372_pm_init_late(void);
 #endif /* __ASM_SH7372_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index fe950f25d793..606d31d02a4e 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -557,4 +557,6 @@ enum {
 #define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
 #define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
+extern struct smp_operations sh73a0_smp_ops;
 #endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index f04fad4ec4fb..ef66f1a8aa2e 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -29,14 +29,14 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#define INT2SMSKCR0 0xfe7822a0
+#define INT2SMSKCR0 IOMEM(0xfe7822a0)
-#define INT2SMSKCR1 0xfe7822a4
+#define INT2SMSKCR1 IOMEM(0xfe7822a4)
-#define INT2SMSKCR2 0xfe7822a8
+#define INT2SMSKCR2 IOMEM(0xfe7822a8)
-#define INT2SMSKCR3 0xfe7822ac
+#define INT2SMSKCR3 IOMEM(0xfe7822ac)
-#define INT2SMSKCR4 0xfe7822b0
+#define INT2SMSKCR4 IOMEM(0xfe7822b0)
-#define INT2NTSR0 0xfe700060
+#define INT2NTSR0 IOMEM(0xfe700060)
-#define INT2NTSR1 0xfe700064
+#define INT2NTSR1 IOMEM(0xfe700064)
 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 {
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 2587a22842f2..a91caad7db7c 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -624,6 +624,9 @@ void sh7372_intcs_resume(void)
                __raw_writeb(ffd5[k], intcs_ffd5 + k);
 }
+#define E694_BASE IOMEM(0xe6940000)
+#define E695_BASE IOMEM(0xe6950000)
 static unsigned short e694[0x200];
 static unsigned short e695[0x200];
@@ -632,22 +635,22 @@ void sh7372_intca_suspend(void)
        int k;
        for (k = 0x00; k <= 0x38; k += 4)
-                e694[k] = __raw_readw(0xe6940000 + k);
+                e694[k] = __raw_readw(E694_BASE + k);
        for (k = 0x80; k <= 0xb4; k += 4)
-                e694[k] = __raw_readb(0xe6940000 + k);
+                e694[k] = __raw_readb(E694_BASE + k);
        for (k = 0x180; k <= 0x1b4; k += 4)
-                e694[k] = __raw_readb(0xe6940000 + k);
+                e694[k] = __raw_readb(E694_BASE + k);
        for (k = 0x00; k <= 0x50; k += 4)
-                e695[k] = __raw_readw(0xe6950000 + k);
+                e695[k] = __raw_readw(E695_BASE + k);
        for (k = 0x80; k <= 0xa8; k += 4)
-                e695[k] = __raw_readb(0xe6950000 + k);
+                e695[k] = __raw_readb(E695_BASE + k);
        for (k = 0x180; k <= 0x1a8; k += 4)
-                e695[k] = __raw_readb(0xe6950000 + k);
+                e695[k] = __raw_readb(E695_BASE + k);
 }
 void sh7372_intca_resume(void)
@@ -655,20 +658,20 @@ void sh7372_intca_resume(void)
        int k;
        for (k = 0x00; k <= 0x38; k += 4)
-                __raw_writew(e694[k], 0xe6940000 + k);
+                __raw_writew(e694[k], E694_BASE + k);
        for (k = 0x80; k <= 0xb4; k += 4)
-                __raw_writeb(e694[k], 0xe6940000 + k);
+                __raw_writeb(e694[k], E694_BASE + k);
        for (k = 0x180; k <= 0x1b4; k += 4)
-                __raw_writeb(e694[k], 0xe6940000 + k);
+                __raw_writeb(e694[k], E694_BASE + k);
        for (k = 0x00; k <= 0x50; k += 4)
-                __raw_writew(e695[k], 0xe6950000 + k);
+                __raw_writew(e695[k], E695_BASE + k);
        for (k = 0x80; k <= 0xa8; k += 4)
-                __raw_writeb(e695[k], 0xe6950000 + k);
+                __raw_writeb(e695[k], E695_BASE + k);
        for (k = 0x180; k <= 0x1a8; k += 4)
-                __raw_writeb(e695[k], 0xe6950000 + k);
+                __raw_writeb(e695[k], E695_BASE + k);
 }
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 588555a67d9c..f0c5e5190601 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -366,10 +366,12 @@ static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
 static struct irqaction sh73a0_irq_pin_cascade[32];
-#define PINTER0 0xe69000a0
+#define PINTER0_PHYS 0xe69000a0
-#define PINTER1 0xe69000a4
+#define PINTER1_PHYS 0xe69000a4
-#define PINTRR0 0xe69000d0
+#define PINTER0_VIRT IOMEM(0xe69000a0)
-#define PINTRR1 0xe69000d4
+#define PINTER1_VIRT IOMEM(0xe69000a4)
+#define PINTRR0 IOMEM(0xe69000d0)
+#define PINTRR1 IOMEM(0xe69000d4)
 #define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq))
 #define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8))
@@ -377,14 +379,14 @@ static struct irqaction sh73a0_irq_pin_cascade[32];
 #define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24))
 #define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq))
-INTC_PINT(intc_pint0, PINTER0, 0xe69000b0, "sh73a0-pint0",              \
+INTC_PINT(intc_pint0, PINTER0_PHYS, 0xe69000b0, "sh73a0-pint0",         \
  INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D),       \
  INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ),               \
  INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ),               \
  INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D),       \
  INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D));
-INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1",              \
+INTC_PINT(intc_pint1, PINTER1_PHYS, 0xe69000c0, "sh73a0-pint1",         \
  INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \
  INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE,                         \
  INTC_PINT_V_NONE, INTC_PINT_V_NONE,                                   \
@@ -394,7 +396,7 @@ INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1",		\
 static struct irqaction sh73a0_pint0_cascade;
 static struct irqaction sh73a0_pint1_cascade;
-static void pint_demux(unsigned long rr, unsigned long er, int base_irq)
+static void pint_demux(void __iomem *rr, void __iomem *er, int base_irq)
 {
        unsigned long value =  ioread32(rr) & ioread32(er);
        int k;
@@ -409,13 +411,13 @@ static void pint_demux(unsigned long rr, unsigned long er, int base_irq)
 static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id)
 {
-        pint_demux(PINTRR0, PINTER0, SH73A0_PINT0_IRQ(0));
+        pint_demux(PINTRR0, PINTER0_VIRT, SH73A0_PINT0_IRQ(0));
        return IRQ_HANDLED;
 }
 static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id)
 {
-        pint_demux(PINTRR1, PINTER1, SH73A0_PINT1_IRQ(0));
+        pint_demux(PINTRR1, PINTER1_VIRT, SH73A0_PINT1_IRQ(0));
        return IRQ_HANDLED;
 }
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c
index ce9e7fa5cc8a..134d1b9a8821 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7740.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7740.c
@@ -20,7 +20,7 @@
 */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/r8a7740.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
index d14c9b048077..cbc26ba2a0a2 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7779.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -19,7 +19,7 @@
 */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <linux/ioport.h>
 #include <mach/r8a7779.h>
diff --git a/arch/arm/mach-shmobile/pfc-sh7367.c b/arch/arm/mach-shmobile/pfc-sh7367.c
index e6e524654e67..c0c137f39052 100644
--- a/arch/arm/mach-shmobile/pfc-sh7367.c
+++ b/arch/arm/mach-shmobile/pfc-sh7367.c
@@ -18,7 +18,7 @@
 */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/sh7367.h>
 #define CPU_ALL_PORT(fn, pfx, sfx)                              \
diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c
index 336093f9210a..7a1525fd6ada 100644
--- a/arch/arm/mach-shmobile/pfc-sh7372.c
+++ b/arch/arm/mach-shmobile/pfc-sh7372.c
@@ -22,7 +22,7 @@
 */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/irqs.h>
 #include <mach/sh7372.h>
diff --git a/arch/arm/mach-shmobile/pfc-sh7377.c b/arch/arm/mach-shmobile/pfc-sh7377.c
index 2f10511946ad..f3117f67fa25 100644
--- a/arch/arm/mach-shmobile/pfc-sh7377.c
+++ b/arch/arm/mach-shmobile/pfc-sh7377.c
@@ -19,7 +19,7 @@
 */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/sh7377.h>
 #define CPU_ALL_PORT(fn, pfx, sfx)                              \
diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c
index 4a547b803268..b442f9d8c716 100644
--- a/arch/arm/mach-shmobile/pfc-sh73a0.c
+++ b/arch/arm/mach-shmobile/pfc-sh73a0.c
@@ -20,7 +20,7 @@
 */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/sh73a0.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index fde0d23121dc..ed8d2351915e 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -11,100 +11,11 @@
 * published by the Free Software Foundation.
 */
 #include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/device.h>
 #include <linux/smp.h>
-#include <linux/io.h>
-#include <linux/of.h>
 #include <asm/hardware/gic.h>
-#include <asm/mach-types.h>
-#include <mach/common.h>
-#include <mach/emev2.h>
-#ifdef CONFIG_ARCH_SH73A0
+void __init shmobile_smp_init_cpus(unsigned int ncores)
-#define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2() || \
-                        of_machine_is_compatible("renesas,sh73a0"))
-#else
-#define is_sh73a0() (0)
-#endif
-#define is_r8a7779() machine_is_marzen()
-#ifdef CONFIG_ARCH_EMEV2
-#define is_emev2() of_machine_is_compatible("renesas,emev2")
-#else
-#define is_emev2() (0)
-#endif
-static unsigned int __init shmobile_smp_get_core_count(void)
-{
-        if (is_sh73a0())
-                return sh73a0_get_core_count();
-        if (is_r8a7779())
-                return r8a7779_get_core_count();
-        if (is_emev2())
-                return emev2_get_core_count();
-        return 1;
-}
-static void __init shmobile_smp_prepare_cpus(void)
-{
-        if (is_sh73a0())
-                sh73a0_smp_prepare_cpus();
-        if (is_r8a7779())
-                r8a7779_smp_prepare_cpus();
-        if (is_emev2())
-                emev2_smp_prepare_cpus();
-}
-int shmobile_platform_cpu_kill(unsigned int cpu)
-{
-        if (is_r8a7779())
-                return r8a7779_platform_cpu_kill(cpu);
-        if (is_emev2())
-                return emev2_platform_cpu_kill(cpu);
-        return 1;
-}
-void __cpuinit platform_secondary_init(unsigned int cpu)
 {
-        trace_hardirqs_off();
-        if (is_sh73a0())
-                sh73a0_secondary_init(cpu);
-        if (is_r8a7779())
-                r8a7779_secondary_init(cpu);
-        if (is_emev2())
-                emev2_secondary_init(cpu);
-}
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-        if (is_sh73a0())
-                return sh73a0_boot_secondary(cpu);
-        if (is_r8a7779())
-                return r8a7779_boot_secondary(cpu);
-        if (is_emev2())
-                return emev2_boot_secondary(cpu);
-        return -ENOSYS;
-}
-void __init smp_init_cpus(void)
-{
-        unsigned int ncores = shmobile_smp_get_core_count();
        unsigned int i;
        if (ncores > nr_cpu_ids) {
@@ -118,8 +29,3 @@ void __init smp_init_cpus(void)
        set_smp_cross_call(gic_raise_softirq);
 }
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
-{
-        shmobile_smp_prepare_cpus();
-}
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
index 893504d012a6..21e5316d2d88 100644
--- a/arch/arm/mach-shmobile/pm-r8a7740.c
+++ b/arch/arm/mach-shmobile/pm-r8a7740.c
@@ -21,14 +21,6 @@ static int r8a7740_pd_a4s_suspend(void)
        return -EBUSY;
 }
-struct rmobile_pm_domain r8a7740_pd_a4s = {
-        .genpd.name     = "A4S",
-        .bit_shift      = 10,
-        .gov            = &pm_domain_always_on_gov,
-        .no_debug       = true,
-        .suspend        = r8a7740_pd_a4s_suspend,
-};
 static int r8a7740_pd_a3sp_suspend(void)
 {
        /*
@@ -38,17 +30,31 @@ static int r8a7740_pd_a3sp_suspend(void)
        return console_suspend_enabled ? 0 : -EBUSY;
 }
-struct rmobile_pm_domain r8a7740_pd_a3sp = {
+static struct rmobile_pm_domain r8a7740_pm_domains[] = {
-        .genpd.name     = "A3SP",
+        {
-        .bit_shift      = 11,
+                .genpd.name     = "A4S",
-        .gov            = &pm_domain_always_on_gov,
+                .bit_shift      = 10,
-        .no_debug       = true,
+                .gov            = &pm_domain_always_on_gov,
-        .suspend        = r8a7740_pd_a3sp_suspend,
+                .no_debug       = true,
+                .suspend        = r8a7740_pd_a4s_suspend,
+        },
+        {
+                .genpd.name     = "A3SP",
+                .bit_shift      = 11,
+                .gov            = &pm_domain_always_on_gov,
+                .no_debug       = true,
+                .suspend        = r8a7740_pd_a3sp_suspend,
+        },
+        {
+                .genpd.name     = "A4LC",
+                .bit_shift      = 1,
+        },
 };
-struct rmobile_pm_domain r8a7740_pd_a4lc = {
+void __init r8a7740_init_pm_domains(void)
-        .genpd.name     = "A4LC",
+{
-        .bit_shift      = 1,
+        rmobile_init_domains(r8a7740_pm_domains, ARRAY_SIZE(r8a7740_pm_domains));
-};
+        pm_genpd_add_subdomain_names("A4S", "A3SP");
+}
 #endif /* CONFIG_PM */
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
index a18a4ae16d2b..d50a8e9b94a4 100644
--- a/arch/arm/mach-shmobile/pm-r8a7779.c
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -183,7 +183,7 @@ static bool pd_active_wakeup(struct device *dev)
        return true;
 }
-void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
+static void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
 {
        struct generic_pm_domain *genpd = &r8a7779_pd->genpd;
@@ -199,43 +199,44 @@ void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
                pd_power_up(&r8a7779_pd->genpd);
 }
-void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
+static struct r8a7779_pm_domain r8a7779_pm_domains[] = {
-                                 struct platform_device *pdev)
+        {
-{
+                .genpd.name = "SH4A",
-        struct device *dev = &pdev->dev;
+                .ch = {
+                        .chan_offs = 0x80, /* PWRSR1 .. PWRER1 */
-        pm_genpd_add_device(&r8a7779_pd->genpd, dev);
+                        .isr_bit = 16, /* SH4A */
-        if (pm_clk_no_clocks(dev))
+                },
-                pm_clk_add(dev, NULL);
+        },
-}
+        {
+                .genpd.name = "SGX",
-struct r8a7779_pm_domain r8a7779_sh4a = {
+                .ch = {
-        .ch = {
+                        .chan_offs = 0xc0, /* PWRSR2 .. PWRER2 */
-                .chan_offs = 0x80, /* PWRSR1 .. PWRER1 */
+                        .isr_bit = 20, /* SGX */
-                .isr_bit = 16, /* SH4A */
+                },
-        }
+        },
-};
+        {
+                .genpd.name = "VDP1",
-struct r8a7779_pm_domain r8a7779_sgx = {
+                .ch = {
-        .ch = {
+                        .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */
-                .chan_offs = 0xc0, /* PWRSR2 .. PWRER2 */
+                        .isr_bit = 21, /* VDP */
-                .isr_bit = 20, /* SGX */
+                },
-        }
+        },
+        {
+                .genpd.name = "IMPX3",
+                .ch = {
+                        .chan_offs = 0x140, /* PWRSR4 .. PWRER4 */
+                        .isr_bit = 24, /* IMP */
+                },
+        },
 };
-struct r8a7779_pm_domain r8a7779_vdp1 = {
+void __init r8a7779_init_pm_domains(void)
-        .ch = {
+{
-                .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */
+        int j;
-                .isr_bit = 21, /* VDP */
-        }
-};
-struct r8a7779_pm_domain r8a7779_impx3 = {
+        for (j = 0; j < ARRAY_SIZE(r8a7779_pm_domains); j++)
-        .ch = {
+                r8a7779_init_pm_domain(&r8a7779_pm_domains[j]);
-                .chan_offs = 0x140, /* PWRSR4 .. PWRER4 */
+}
-                .isr_bit = 24, /* IMP */
-        }
-};
 #endif /* CONFIG_PM */
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index a8562540f1d6..1fc05d9453d0 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -20,9 +20,9 @@
 #include <mach/pm-rmobile.h>
 /* SYSC */
-#define SPDCR           0xe6180008
+#define SPDCR           IOMEM(0xe6180008)
-#define SWUCR           0xe6180014
+#define SWUCR           IOMEM(0xe6180014)
-#define PSTR            0xe6180080
+#define PSTR            IOMEM(0xe6180080)
 #define PSTR_RETRIES    100
 #define PSTR_DELAY_US   10
@@ -134,7 +134,7 @@ static int rmobile_pd_start_dev(struct device *dev)
        return ret;
 }
-void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
+static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
 {
        struct generic_pm_domain *genpd = &rmobile_pd->genpd;
        struct dev_power_governor *gov = rmobile_pd->gov;
@@ -149,19 +149,38 @@ void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
        __rmobile_pd_power_up(rmobile_pd, false);
 }
-void rmobile_add_device_to_domain(struct rmobile_pm_domain *rmobile_pd,
+void rmobile_init_domains(struct rmobile_pm_domain domains[], int num)
-                                 struct platform_device *pdev)
+{
+        int j;
+        for (j = 0; j < num; j++)
+                rmobile_init_pm_domain(&domains[j]);
+}
+void rmobile_add_device_to_domain_td(const char *domain_name,
+                                     struct platform_device *pdev,
+                                     struct gpd_timing_data *td)
 {
        struct device *dev = &pdev->dev;
-        pm_genpd_add_device(&rmobile_pd->genpd, dev);
+        __pm_genpd_name_add_device(domain_name, dev, td);
        if (pm_clk_no_clocks(dev))
                pm_clk_add(dev, NULL);
 }
-void rmobile_pm_add_subdomain(struct rmobile_pm_domain *rmobile_pd,
+void rmobile_add_devices_to_domains(struct pm_domain_device data[],
-                             struct rmobile_pm_domain *rmobile_sd)
+                                    int size)
 {
-        pm_genpd_add_subdomain(&rmobile_pd->genpd, &rmobile_sd->genpd);
+        struct gpd_timing_data latencies = {
+                .stop_latency_ns = DEFAULT_DEV_LATENCY_NS,
+                .start_latency_ns = DEFAULT_DEV_LATENCY_NS,
+                .save_state_latency_ns = DEFAULT_DEV_LATENCY_NS,
+                .restore_state_latency_ns = DEFAULT_DEV_LATENCY_NS,
+        };
+        int j;
+        for (j = 0; j < size; j++)
+                rmobile_add_device_to_domain_td(data[j].domain_name,
+                                                data[j].pdev, &latencies);
 }
 #endif /* CONFIG_PM */
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index 792037069226..a0826a48dd08 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -21,6 +21,7 @@
 #include <linux/irq.h>
 #include <linux/bitrev.h>
 #include <linux/console.h>
+#include <asm/cpuidle.h>
 #include <asm/io.h>
 #include <asm/tlbflush.h>
 #include <asm/suspend.h>
@@ -29,62 +30,50 @@
 #include <mach/pm-rmobile.h>
 /* DBG */
-#define DBGREG1 0xe6100020
+#define DBGREG1 IOMEM(0xe6100020)
-#define DBGREG9 0xe6100040
+#define DBGREG9 IOMEM(0xe6100040)
 /* CPGA */
-#define SYSTBCR 0xe6150024
+#define SYSTBCR IOMEM(0xe6150024)
-#define MSTPSR0 0xe6150030
+#define MSTPSR0 IOMEM(0xe6150030)
-#define MSTPSR1 0xe6150038
+#define MSTPSR1 IOMEM(0xe6150038)
-#define MSTPSR2 0xe6150040
+#define MSTPSR2 IOMEM(0xe6150040)
-#define MSTPSR3 0xe6150048
+#define MSTPSR3 IOMEM(0xe6150048)
-#define MSTPSR4 0xe615004c
+#define MSTPSR4 IOMEM(0xe615004c)
-#define PLLC01STPCR 0xe61500c8
+#define PLLC01STPCR IOMEM(0xe61500c8)
 /* SYSC */
-#define SBAR 0xe6180020
+#define SBAR IOMEM(0xe6180020)
-#define WUPRMSK 0xe6180028
+#define WUPRMSK IOMEM(0xe6180028)
-#define WUPSMSK 0xe618002c
+#define WUPSMSK IOMEM(0xe618002c)
-#define WUPSMSK2 0xe6180048
+#define WUPSMSK2 IOMEM(0xe6180048)
-#define WUPSFAC 0xe6180098
+#define WUPSFAC IOMEM(0xe6180098)
-#define IRQCR 0xe618022c
+#define IRQCR IOMEM(0xe618022c)
-#define IRQCR2 0xe6180238
+#define IRQCR2 IOMEM(0xe6180238)
-#define IRQCR3 0xe6180244
+#define IRQCR3 IOMEM(0xe6180244)
-#define IRQCR4 0xe6180248
+#define IRQCR4 IOMEM(0xe6180248)
-#define PDNSEL 0xe6180254
+#define PDNSEL IOMEM(0xe6180254)
 /* INTC */
-#define ICR1A 0xe6900000
+#define ICR1A IOMEM(0xe6900000)
-#define ICR2A 0xe6900004
+#define ICR2A IOMEM(0xe6900004)
-#define ICR3A 0xe6900008
+#define ICR3A IOMEM(0xe6900008)
-#define ICR4A 0xe690000c
+#define ICR4A IOMEM(0xe690000c)
-#define INTMSK00A 0xe6900040
+#define INTMSK00A IOMEM(0xe6900040)
-#define INTMSK10A 0xe6900044
+#define INTMSK10A IOMEM(0xe6900044)
-#define INTMSK20A 0xe6900048
+#define INTMSK20A IOMEM(0xe6900048)
-#define INTMSK30A 0xe690004c
+#define INTMSK30A IOMEM(0xe690004c)
 /* MFIS */
+/* FIXME: pointing where? */
 #define SMFRAM 0xe6a70000
 /* AP-System Core */
-#define APARMBAREA 0xe6f10020
+#define APARMBAREA IOMEM(0xe6f10020)
 #ifdef CONFIG_PM
-struct rmobile_pm_domain sh7372_pd_a4lc = {
+#define PM_DOMAIN_ON_OFF_LATENCY_NS     250000
-        .genpd.name = "A4LC",
-        .bit_shift = 1,
-};
-struct rmobile_pm_domain sh7372_pd_a4mp = {
-        .genpd.name = "A4MP",
-        .bit_shift = 2,
-};
-struct rmobile_pm_domain sh7372_pd_d4 = {
-        .genpd.name = "D4",
-        .bit_shift = 3,
-};
 static int sh7372_a4r_pd_suspend(void)
 {
@@ -93,39 +82,25 @@ static int sh7372_a4r_pd_suspend(void)
        return 0;
 }
-struct rmobile_pm_domain sh7372_pd_a4r = {
+static bool a4s_suspend_ready;
-        .genpd.name = "A4R",
-        .bit_shift = 5,
-        .suspend = sh7372_a4r_pd_suspend,
-        .resume = sh7372_intcs_resume,
-};
-struct rmobile_pm_domain sh7372_pd_a3rv = {
+static int sh7372_a4s_pd_suspend(void)
-        .genpd.name = "A3RV",
-        .bit_shift = 6,
-};
-struct rmobile_pm_domain sh7372_pd_a3ri = {
-        .genpd.name = "A3RI",
-        .bit_shift = 8,
-};
-static int sh7372_pd_a4s_suspend(void)
 {
        /*
         * The A4S domain contains the CPU core and therefore it should
-         * only be turned off if the CPU is in use.
+         * only be turned off if the CPU is not in use.  This may happen
+         * during system suspend, when SYSC is going to be used for generating
+         * resume signals and a4s_suspend_ready is set to let
+         * sh7372_enter_suspend() know that it can turn A4S off.
         */
+        a4s_suspend_ready = true;
        return -EBUSY;
 }
-struct rmobile_pm_domain sh7372_pd_a4s = {
+static void sh7372_a4s_pd_resume(void)
-        .genpd.name = "A4S",
+{
-        .bit_shift = 10,
+        a4s_suspend_ready = false;
-        .gov = &pm_domain_always_on_gov,
+}
-        .no_debug = true,
-        .suspend = sh7372_pd_a4s_suspend,
-};
 static int sh7372_a3sp_pd_suspend(void)
 {
@@ -136,18 +111,80 @@ static int sh7372_a3sp_pd_suspend(void)
        return console_suspend_enabled ? 0 : -EBUSY;
 }
-struct rmobile_pm_domain sh7372_pd_a3sp = {
+static struct rmobile_pm_domain sh7372_pm_domains[] = {
-        .genpd.name = "A3SP",
+        {
-        .bit_shift = 11,
+                .genpd.name = "A4LC",
-        .gov = &pm_domain_always_on_gov,
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-        .no_debug = true,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
-        .suspend = sh7372_a3sp_pd_suspend,
+                .bit_shift = 1,
+        },
+        {
+                .genpd.name = "A4MP",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 2,
+        },
+        {
+                .genpd.name = "D4",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 3,
+        },
+        {
+                .genpd.name = "A4R",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 5,
+                .suspend = sh7372_a4r_pd_suspend,
+                .resume = sh7372_intcs_resume,
+        },
+        {
+                .genpd.name = "A3RV",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 6,
+        },
+        {
+                .genpd.name = "A3RI",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 8,
+        },
+        {
+                .genpd.name = "A4S",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 10,
+                .gov = &pm_domain_always_on_gov,
+                .no_debug = true,
+                .suspend = sh7372_a4s_pd_suspend,
+                .resume = sh7372_a4s_pd_resume,
+        },
+        {
+                .genpd.name = "A3SP",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 11,
+                .gov = &pm_domain_always_on_gov,
+                .no_debug = true,
+                .suspend = sh7372_a3sp_pd_suspend,
+        },
+        {
+                .genpd.name = "A3SG",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 13,
+        },
 };
-struct rmobile_pm_domain sh7372_pd_a3sg = {
+void __init sh7372_init_pm_domains(void)
-        .genpd.name = "A3SG",
+{
-        .bit_shift = 13,
+        rmobile_init_domains(sh7372_pm_domains, ARRAY_SIZE(sh7372_pm_domains));
-};
+        pm_genpd_add_subdomain_names("A4LC", "A3RV");
+        pm_genpd_add_subdomain_names("A4R", "A4LC");
+        pm_genpd_add_subdomain_names("A4S", "A3SG");
+        pm_genpd_add_subdomain_names("A4S", "A3SP");
+}
 #endif /* CONFIG_PM */
@@ -303,6 +340,21 @@ static void sh7372_enter_a3sm_common(int pllc0_on)
        sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
        sh7372_enter_sysc(pllc0_on, 1 << 12);
 }
+static void sh7372_enter_a4s_common(int pllc0_on)
+{
+        sh7372_intca_suspend();
+        sh7372_set_reset_vector(SMFRAM);
+        sh7372_enter_sysc(pllc0_on, 1 << 10);
+        sh7372_intca_resume();
+}
+static void sh7372_pm_setup_smfram(void)
+{
+        memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
+}
+#else
+static inline void sh7372_pm_setup_smfram(void) {}
 #endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */
 #ifdef CONFIG_CPU_IDLE
@@ -312,7 +364,8 @@ static int sh7372_do_idle_core_standby(unsigned long unused)
        return 0;
 }
-static void sh7372_enter_core_standby(void)
+static int sh7372_enter_core_standby(struct cpuidle_device *dev,
+                                     struct cpuidle_driver *drv, int index)
 {
        sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
@@ -323,83 +376,102 @@ static void sh7372_enter_core_standby(void)
         /* disable reset vector translation */
        __raw_writel(0, SBAR);
+        return 1;
 }
-static void sh7372_enter_a3sm_pll_on(void)
+static int sh7372_enter_a3sm_pll_on(struct cpuidle_device *dev,
+                                    struct cpuidle_driver *drv, int index)
 {
        sh7372_enter_a3sm_common(1);
+        return 2;
 }
-static void sh7372_enter_a3sm_pll_off(void)
+static int sh7372_enter_a3sm_pll_off(struct cpuidle_device *dev,
+                                     struct cpuidle_driver *drv, int index)
 {
        sh7372_enter_a3sm_common(0);
+        return 3;
 }
-static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
+static int sh7372_enter_a4s(struct cpuidle_device *dev,
+                            struct cpuidle_driver *drv, int index)
 {
-        struct cpuidle_state *state = &drv->states[drv->state_count];
+        unsigned long msk, msk2;
-        snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
+        if (!sh7372_sysc_valid(&msk, &msk2))
-        strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
+                return sh7372_enter_a3sm_pll_off(dev, drv, index);
-        state->exit_latency = 10;
-        state->target_residency = 20 + 10;
+        sh7372_setup_sysc(msk, msk2);
-        state->flags = CPUIDLE_FLAG_TIME_VALID;
+        sh7372_enter_a4s_common(0);
-        shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby;
+        return 4;
-        drv->state_count++;
-        state = &drv->states[drv->state_count];
-        snprintf(state->name, CPUIDLE_NAME_LEN, "C3");
-        strncpy(state->desc, "A3SM PLL ON", CPUIDLE_DESC_LEN);
-        state->exit_latency = 20;
-        state->target_residency = 30 + 20;
-        state->flags = CPUIDLE_FLAG_TIME_VALID;
-        shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_on;
-        drv->state_count++;
-        state = &drv->states[drv->state_count];
-        snprintf(state->name, CPUIDLE_NAME_LEN, "C4");
-        strncpy(state->desc, "A3SM PLL OFF", CPUIDLE_DESC_LEN);
-        state->exit_latency = 120;
-        state->target_residency = 30 + 120;
-        state->flags = CPUIDLE_FLAG_TIME_VALID;
-        shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_off;
-        drv->state_count++;
 }
+static struct cpuidle_driver sh7372_cpuidle_driver = {
+        .name                   = "sh7372_cpuidle",
+        .owner                  = THIS_MODULE,
+        .en_core_tk_irqen       = 1,
+        .state_count            = 5,
+        .safe_state_index       = 0, /* C1 */
+        .states[0] = ARM_CPUIDLE_WFI_STATE,
+        .states[0].enter = shmobile_enter_wfi,
+        .states[1] = {
+                .name = "C2",
+                .desc = "Core Standby Mode",
+                .exit_latency = 10,
+                .target_residency = 20 + 10,
+                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .enter = sh7372_enter_core_standby,
+        },
+        .states[2] = {
+                .name = "C3",
+                .desc = "A3SM PLL ON",
+                .exit_latency = 20,
+                .target_residency = 30 + 20,
+                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .enter = sh7372_enter_a3sm_pll_on,
+        },
+        .states[3] = {
+                .name = "C4",
+                .desc = "A3SM PLL OFF",
+                .exit_latency = 120,
+                .target_residency = 30 + 120,
+                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .enter = sh7372_enter_a3sm_pll_off,
+        },
+        .states[4] = {
+                .name = "C5",
+                .desc = "A4S PLL OFF",
+                .exit_latency = 240,
+                .target_residency = 30 + 240,
+                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .enter = sh7372_enter_a4s,
+                .disabled = true,
+        },
+};
 static void sh7372_cpuidle_init(void)
 {
-        shmobile_cpuidle_setup = sh7372_cpuidle_setup;
+        shmobile_cpuidle_set_driver(&sh7372_cpuidle_driver);
 }
 #else
 static void sh7372_cpuidle_init(void) {}
 #endif
 #ifdef CONFIG_SUSPEND
-static void sh7372_enter_a4s_common(int pllc0_on)
-{
-        sh7372_intca_suspend();
-        memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
-        sh7372_set_reset_vector(SMFRAM);
-        sh7372_enter_sysc(pllc0_on, 1 << 10);
-        sh7372_intca_resume();
-}
 static int sh7372_enter_suspend(suspend_state_t suspend_state)
 {
        unsigned long msk, msk2;
        /* check active clocks to determine potential wakeup sources */
-        if (sh7372_sysc_valid(&msk, &msk2)) {
+        if (sh7372_sysc_valid(&msk, &msk2) && a4s_suspend_ready) {
-                if (!console_suspend_enabled &&
+                /* convert INTC mask/sense to SYSC mask/sense */
-                    sh7372_pd_a4s.genpd.status == GPD_STATE_POWER_OFF) {
+                sh7372_setup_sysc(msk, msk2);
-                        /* convert INTC mask/sense to SYSC mask/sense */
-                        sh7372_setup_sysc(msk, msk2);
+                /* enter A4S sleep with PLLC0 off */
+                pr_debug("entering A4S\n");
-                        /* enter A4S sleep with PLLC0 off */
+                sh7372_enter_a4s_common(0);
-                        pr_debug("entering A4S\n");
+                return 0;
-                        sh7372_enter_a4s_common(0);
-                        return 0;
-                }
        }
        /* default to enter A3SM sleep with PLLC0 off */
@@ -425,7 +497,7 @@ static int sh7372_pm_notifier_fn(struct notifier_block *notifier,
                 * executed during system suspend and resume, respectively, so
                 * that those functions don't crash while accessing the INTCS.
                 */
-                pm_genpd_poweron(&sh7372_pd_a4r.genpd);
+                pm_genpd_name_poweron("A4R");
                break;
        case PM_POST_SUSPEND:
                pm_genpd_poweroff_unused();
@@ -454,6 +526,14 @@ void __init sh7372_pm_init(void)
        /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
        __raw_writel(0, PDNSEL);
+        sh7372_pm_setup_smfram();
        sh7372_suspend_init();
        sh7372_cpuidle_init();
 }
+void __init sh7372_pm_init_late(void)
+{
+        shmobile_init_late();
+        pm_genpd_name_attach_cpuidle("A4S", 4);
+}
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index dae9aa68bb09..a47beeb18283 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -356,6 +356,26 @@ static struct platform_device gio4_device = {
        },
 };
+static struct resource pmu_resources[] = {
+        [0] = {
+                .start  = 152,
+                .end    = 152,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [1] = {
+                .start  = 153,
+                .end    = 153,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device pmu_device = {
+        .name           = "arm-pmu",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pmu_resources),
+        .resource       = pmu_resources,
+};
 static struct platform_device *emev2_early_devices[] __initdata = {
        &uart0_device,
        &uart1_device,
@@ -370,6 +390,7 @@ static struct platform_device *emev2_late_devices[] __initdata = {
        &gio2_device,
        &gio3_device,
        &gio4_device,
+        &pmu_device,
 };
 void __init emev2_add_standard_devices(void)
@@ -440,6 +461,7 @@ void __init emev2_init_irq_dt(void)
 }
 DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
+        .smp            = smp_ops(emev2_smp_ops),
        .init_early     = emev2_init_delay,
        .nr_irqs        = NR_IRQS_LEGACY,
        .init_irq       = emev2_init_irq_dt,
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 78948a9dba0e..11bb1d984197 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -673,12 +673,7 @@ void __init r8a7740_add_standard_devices(void)
        r8a7740_i2c_workaround(&i2c0_device);
        r8a7740_i2c_workaround(&i2c1_device);
-        /* PM domain */
+        r8a7740_init_pm_domains();
-        rmobile_init_pm_domain(&r8a7740_pd_a4s);
-        rmobile_init_pm_domain(&r8a7740_pd_a3sp);
-        rmobile_init_pm_domain(&r8a7740_pd_a4lc);
-        rmobile_pm_add_subdomain(&r8a7740_pd_a4s, &r8a7740_pd_a3sp);
        /* add devices */
        platform_add_devices(r8a7740_early_devices,
@@ -688,16 +683,16 @@ void __init r8a7740_add_standard_devices(void)
        /* add devices to PM domain  */
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif0_device);
+        rmobile_add_device_to_domain("A3SP",    &scif0_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif1_device);
+        rmobile_add_device_to_domain("A3SP",    &scif1_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif2_device);
+        rmobile_add_device_to_domain("A3SP",    &scif2_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif3_device);
+        rmobile_add_device_to_domain("A3SP",    &scif3_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif4_device);
+        rmobile_add_device_to_domain("A3SP",    &scif4_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif5_device);
+        rmobile_add_device_to_domain("A3SP",    &scif5_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif6_device);
+        rmobile_add_device_to_domain("A3SP",    &scif6_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif7_device);
+        rmobile_add_device_to_domain("A3SP",    &scif7_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scifb_device);
+        rmobile_add_device_to_domain("A3SP",    &scifb_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &i2c1_device);
+        rmobile_add_device_to_domain("A3SP",    &i2c1_device);
 }
 static void __init r8a7740_earlytimer_init(void)
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index e98e46f6cf55..2917668f0091 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -251,10 +251,7 @@ void __init r8a7779_add_standard_devices(void)
 #endif
        r8a7779_pm_init();
-        r8a7779_init_pm_domain(&r8a7779_sh4a);
+        r8a7779_init_pm_domains();
-        r8a7779_init_pm_domain(&r8a7779_sgx);
-        r8a7779_init_pm_domain(&r8a7779_vdp1);
-        r8a7779_init_pm_domain(&r8a7779_impx3);
        platform_add_devices(r8a7779_early_devices,
                            ARRAY_SIZE(r8a7779_early_devices));
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
index 2e3074ab75b3..e647f5410879 100644
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -462,7 +462,7 @@ static void __init sh7367_earlytimer_init(void)
        shmobile_earlytimer_init();
 }
-#define SYMSTPCR2 0xe6158048
+#define SYMSTPCR2 IOMEM(0xe6158048)
 #define SYMSTPCR2_CMT1 (1 << 29)
 void __init sh7367_add_early_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 838a87be1d5c..a07954fbcd22 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -1001,21 +1001,34 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
 void __init sh7372_add_standard_devices(void)
 {
-        rmobile_init_pm_domain(&sh7372_pd_a4lc);
+        struct pm_domain_device domain_devices[] = {
-        rmobile_init_pm_domain(&sh7372_pd_a4mp);
+                { "A3RV", &vpu_device, },
-        rmobile_init_pm_domain(&sh7372_pd_d4);
+                { "A4MP", &spu0_device, },
-        rmobile_init_pm_domain(&sh7372_pd_a4r);
+                { "A4MP", &spu1_device, },
-        rmobile_init_pm_domain(&sh7372_pd_a3rv);
+                { "A3SP", &scif0_device, },
-        rmobile_init_pm_domain(&sh7372_pd_a3ri);
+                { "A3SP", &scif1_device, },
-        rmobile_init_pm_domain(&sh7372_pd_a4s);
+                { "A3SP", &scif2_device, },
-        rmobile_init_pm_domain(&sh7372_pd_a3sp);
+                { "A3SP", &scif3_device, },
-        rmobile_init_pm_domain(&sh7372_pd_a3sg);
+                { "A3SP", &scif4_device, },
+                { "A3SP", &scif5_device, },
-        rmobile_pm_add_subdomain(&sh7372_pd_a4lc, &sh7372_pd_a3rv);
+                { "A3SP", &scif6_device, },
-        rmobile_pm_add_subdomain(&sh7372_pd_a4r, &sh7372_pd_a4lc);
+                { "A3SP", &iic1_device, },
+                { "A3SP", &dma0_device, },
-        rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sg);
+                { "A3SP", &dma1_device, },
-        rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sp);
+                { "A3SP", &dma2_device, },
+                { "A3SP", &usb_dma0_device, },
+                { "A3SP", &usb_dma1_device, },
+                { "A4R", &iic0_device, },
+                { "A4R", &veu0_device, },
+                { "A4R", &veu1_device, },
+                { "A4R", &veu2_device, },
+                { "A4R", &veu3_device, },
+                { "A4R", &jpu_device, },
+                { "A4R", &tmu00_device, },
+                { "A4R", &tmu01_device, },
+        };
+        sh7372_init_pm_domains();
        platform_add_devices(sh7372_early_devices,
                            ARRAY_SIZE(sh7372_early_devices));
@@ -1023,30 +1036,8 @@ void __init sh7372_add_standard_devices(void)
        platform_add_devices(sh7372_late_devices,
                            ARRAY_SIZE(sh7372_late_devices));
-        rmobile_add_device_to_domain(&sh7372_pd_a3rv, &vpu_device);
+        rmobile_add_devices_to_domains(domain_devices,
-        rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu0_device);
+                                       ARRAY_SIZE(domain_devices));
-        rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif2_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif3_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif4_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif5_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif6_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &iic1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma2_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &iic0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu2_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu3_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &jpu_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu00_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu01_device);
 }
 static void __init sh7372_earlytimer_init(void)
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index 855b1506caf8..edcf98bb7012 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -484,7 +484,7 @@ static void __init sh7377_earlytimer_init(void)
        shmobile_earlytimer_init();
 }
-#define SMSTPCR3 0xe615013c
+#define SMSTPCR3 IOMEM(0xe615013c)
 #define SMSTPCR3_CMT1 (1 << 29)
 void __init sh7377_add_early_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index d230af656fc9..db99a4ade80c 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -734,6 +734,26 @@ static struct platform_device mpdma0_device = {
        },
 };
+static struct resource pmu_resources[] = {
+        [0] = {
+                .start  = gic_spi(55),
+                .end    = gic_spi(55),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [1] = {
+                .start  = gic_spi(56),
+                .end    = gic_spi(56),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device pmu_device = {
+        .name           = "arm-pmu",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pmu_resources),
+        .resource       = pmu_resources,
+};
 static struct platform_device *sh73a0_early_devices[] __initdata = {
        &scif0_device,
        &scif1_device,
@@ -757,9 +777,10 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
        &i2c4_device,
        &dma0_device,
        &mpdma0_device,
+        &pmu_device,
 };
-#define SRCR2          0xe61580b0
+#define SRCR2          IOMEM(0xe61580b0)
 void __init sh73a0_add_standard_devices(void)
 {
diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/sh-gpio.h
index 844507d937cb..e834763ac2a5 100644
--- a/arch/arm/mach-shmobile/include/mach/gpio.h
+++ b/arch/arm/mach-shmobile/sh-gpio.h
@@ -12,22 +12,8 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
-#include <linux/sh_pfc.h>
 #include <linux/io.h>
-#ifdef CONFIG_GPIOLIB
-static inline int irq_to_gpio(unsigned int irq)
-{
-        return -ENOSYS;
-}
-#else
-#define __ARM_GPIOLIB_COMPLEX
-#endif /* CONFIG_GPIOLIB */
 /*
 * FIXME !!
 *
@@ -35,12 +21,12 @@ static inline int irq_to_gpio(unsigned int irq)
 * the method to control only pull up/down/free.
 * this function should be replaced by correct gpio function
 */
-static inline void __init gpio_direction_none(u32 addr)
+static inline void __init gpio_direction_none(void __iomem * addr)
 {
        __raw_writeb(0x00, addr);
 }
-static inline void __init gpio_request_pullup(u32 addr)
+static inline void __init gpio_request_pullup(void __iomem * addr)
 {
        u8 data = __raw_readb(addr);
@@ -49,7 +35,7 @@ static inline void __init gpio_request_pullup(u32 addr)
        __raw_writeb(data, addr);
 }
-static inline void __init gpio_request_pulldown(u32 addr)
+static inline void __init gpio_request_pulldown(void __iomem * addr)
 {
        u8 data = __raw_readb(addr);
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 6a35c4a31e6c..f67456286280 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -50,7 +50,7 @@ static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
 }
-unsigned int __init emev2_get_core_count(void)
+static unsigned int __init emev2_get_core_count(void)
 {
        if (!scu_base) {
                scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
@@ -62,17 +62,35 @@ unsigned int __init emev2_get_core_count(void)
        return scu_base ? scu_get_core_count(scu_base) : 1;
 }
-int emev2_platform_cpu_kill(unsigned int cpu)
+static int emev2_platform_cpu_kill(unsigned int cpu)
 {
        return 0; /* not supported yet */
 }
-void __cpuinit emev2_secondary_init(unsigned int cpu)
+static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
+{
+        int k;
+        /* this function is running on another CPU than the offline target,
+         * here we need wait for shutdown code in platform_cpu_die() to
+         * finish before asking SoC-specific code to power off the CPU core.
+         */
+        for (k = 0; k < 1000; k++) {
+                if (shmobile_cpu_is_dead(cpu))
+                        return emev2_platform_cpu_kill(cpu);
+                mdelay(1);
+        }
+        return 0;
+}
+static void __cpuinit emev2_secondary_init(unsigned int cpu)
 {
        gic_secondary_init(0);
 }
-int __cpuinit emev2_boot_secondary(unsigned int cpu)
+static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        cpu = cpu_logical_map(cpu);
@@ -82,11 +100,11 @@ int __cpuinit emev2_boot_secondary(unsigned int cpu)
        /* Tell ROM loader about our vector (in headsmp.S) */
        emev2_set_boot_vector(__pa(shmobile_secondary_vector));
-        gic_raise_softirq(cpumask_of(cpu), 1);
+        gic_raise_softirq(cpumask_of(cpu), 0);
        return 0;
 }
-void __init emev2_smp_prepare_cpus(void)
+static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
 {
        int cpu = cpu_logical_map(0);
@@ -95,3 +113,22 @@ void __init emev2_smp_prepare_cpus(void)
        /* enable cache coherency on CPU0 */
        modify_scu_cpu_psr(0, 3 << (cpu * 8));
 }
+static void __init emev2_smp_init_cpus(void)
+{
+        unsigned int ncores = emev2_get_core_count();
+        shmobile_smp_init_cpus(ncores);
+}
+struct smp_operations emev2_smp_ops __initdata = {
+        .smp_init_cpus          = emev2_smp_init_cpus,
+        .smp_prepare_cpus       = emev2_smp_prepare_cpus,
+        .smp_secondary_init     = emev2_secondary_init,
+        .smp_boot_secondary     = emev2_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_kill               = emev2_cpu_kill,
+        .cpu_die                = shmobile_cpu_die,
+        .cpu_disable            = shmobile_cpu_disable,
+#endif
+};
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 6d1d0238cbf7..2ce6af9a6a37 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -87,14 +87,14 @@ static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
        __raw_writel(tmp, scu_base + 8);
 }
-unsigned int __init r8a7779_get_core_count(void)
+static unsigned int __init r8a7779_get_core_count(void)
 {
        void __iomem *scu_base = scu_base_addr();
        return scu_get_core_count(scu_base);
 }
-int r8a7779_platform_cpu_kill(unsigned int cpu)
+static int r8a7779_platform_cpu_kill(unsigned int cpu)
 {
        struct r8a7779_pm_ch *ch = NULL;
        int ret = -EIO;
@@ -113,12 +113,31 @@ int r8a7779_platform_cpu_kill(unsigned int cpu)
        return ret ? ret : 1;
 }
-void __cpuinit r8a7779_secondary_init(unsigned int cpu)
+static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
+{
+        int k;
+        /* this function is running on another CPU than the offline target,
+         * here we need wait for shutdown code in platform_cpu_die() to
+         * finish before asking SoC-specific code to power off the CPU core.
+         */
+        for (k = 0; k < 1000; k++) {
+                if (shmobile_cpu_is_dead(cpu))
+                        return r8a7779_platform_cpu_kill(cpu);
+                mdelay(1);
+        }
+        return 0;
+}
+static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
 {
        gic_secondary_init(0);
 }
-int __cpuinit r8a7779_boot_secondary(unsigned int cpu)
+static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        struct r8a7779_pm_ch *ch = NULL;
        int ret = -EIO;
@@ -137,7 +156,7 @@ int __cpuinit r8a7779_boot_secondary(unsigned int cpu)
        return ret;
 }
-void __init r8a7779_smp_prepare_cpus(void)
+static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 {
        int cpu = cpu_logical_map(0);
@@ -156,3 +175,22 @@ void __init r8a7779_smp_prepare_cpus(void)
        r8a7779_platform_cpu_kill(2);
        r8a7779_platform_cpu_kill(3);
 }
+static void __init r8a7779_smp_init_cpus(void)
+{
+        unsigned int ncores = r8a7779_get_core_count();
+        shmobile_smp_init_cpus(ncores);
+}
+struct smp_operations r8a7779_smp_ops  __initdata = {
+        .smp_init_cpus          = r8a7779_smp_init_cpus,
+        .smp_prepare_cpus       = r8a7779_smp_prepare_cpus,
+        .smp_secondary_init     = r8a7779_secondary_init,
+        .smp_boot_secondary     = r8a7779_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_kill               = r8a7779_cpu_kill,
+        .cpu_die                = shmobile_cpu_die,
+        .cpu_disable            = shmobile_cpu_disable,
+#endif
+};
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index e36c41c4ab40..624f00f70abf 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -22,8 +22,10 @@
 #include <linux/smp.h>
 #include <linux/spinlock.h>
 #include <linux/io.h>
+#include <linux/delay.h>
 #include <mach/common.h>
 #include <asm/smp_plat.h>
+#include <mach/sh73a0.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/gic.h>
@@ -64,19 +66,19 @@ static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
        __raw_writel(tmp, scu_base + 8);
 }
-unsigned int __init sh73a0_get_core_count(void)
+static unsigned int __init sh73a0_get_core_count(void)
 {
        void __iomem *scu_base = scu_base_addr();
        return scu_get_core_count(scu_base);
 }
-void __cpuinit sh73a0_secondary_init(unsigned int cpu)
+static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
 {
        gic_secondary_init(0);
 }
-int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
+static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        cpu = cpu_logical_map(cpu);
@@ -91,7 +93,7 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
        return 0;
 }
-void __init sh73a0_smp_prepare_cpus(void)
+static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
 {
        int cpu = cpu_logical_map(0);
@@ -104,3 +106,41 @@ void __init sh73a0_smp_prepare_cpus(void)
        /* enable cache coherency on CPU0 */
        modify_scu_cpu_psr(0, 3 << (cpu * 8));
 }
+static void __init sh73a0_smp_init_cpus(void)
+{
+        unsigned int ncores = sh73a0_get_core_count();
+        shmobile_smp_init_cpus(ncores);
+}
+static int __maybe_unused sh73a0_cpu_kill(unsigned int cpu)
+{
+        int k;
+        /* this function is running on another CPU than the offline target,
+         * here we need wait for shutdown code in platform_cpu_die() to
+         * finish before asking SoC-specific code to power off the CPU core.
+         */
+        for (k = 0; k < 1000; k++) {
+                if (shmobile_cpu_is_dead(cpu))
+                        return 1;
+                mdelay(1);
+        }
+        return 0;
+}
+struct smp_operations sh73a0_smp_ops __initdata = {
+        .smp_init_cpus          = sh73a0_smp_init_cpus,
+        .smp_prepare_cpus       = sh73a0_smp_prepare_cpus,
+        .smp_secondary_init     = sh73a0_secondary_init,
+        .smp_boot_secondary     = sh73a0_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_kill               = sh73a0_cpu_kill,
+        .cpu_die                = shmobile_cpu_die,
+        .cpu_disable            = shmobile_cpu_disable,
+#endif
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
new file mode 100644
index 000000000000..803a3281feb5
--- /dev/null
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -0,0 +1,16 @@
+config ARCH_SOCFPGA
+        bool "Altera SOCFPGA family" if ARCH_MULTI_V7
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_AMBA
+        select ARM_GIC
+        select CACHE_L2X0
+        select CLKDEV_LOOKUP
+        select COMMON_CLK
+        select CPU_V7
+        select DW_APB_TIMER
+        select DW_APB_TIMER_OF
+        select GENERIC_CLOCKEVENTS
+        select GPIO_PL061 if GPIOLIB
+        select HAVE_ARM_SCU
+        select SPARSE_IRQ
+        select USE_OF
diff --git a/arch/arm/mach-socfpga/Makefile.boot b/arch/arm/mach-socfpga/Makefile.boot
deleted file mode 100644
index dae9661a7689..000000000000
--- a/arch/arm/mach-socfpga/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
-zreladdr-y      := 0x00008000
diff --git a/arch/arm/mach-socfpga/include/mach/timex.h b/arch/arm/mach-socfpga/include/mach/timex.h
deleted file mode 100644
index 43df4354e461..000000000000
--- a/arch/arm/mach-socfpga/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/arch/arm/mach-socfpga/include/mach/uncompress.h b/arch/arm/mach-socfpga/include/mach/uncompress.h
deleted file mode 100644
index bbe20e696325..000000000000
--- a/arch/arm/mach-socfpga/include/mach/uncompress.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __MACH_UNCOMPRESS_H
-#define __MACH_UNCOMPRESS_H
-#define putc(c)
-#define flush()
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
-#endif
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear13xx/Makefile.boot
index 403efd7e6d27..4674a4c221db 100644
--- a/arch/arm/mach-spear13xx/Makefile.boot
+++ b/arch/arm/mach-spear13xx/Makefile.boot
@@ -1,6 +1,3 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
-dtb-$(CONFIG_MACH_SPEAR1310)    += spear1310-evb.dtb
-dtb-$(CONFIG_MACH_SPEAR1340)    += spear1340-evb.dtb
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear13xx/hotplug.c
index 5c6867b46d09..a7d2dd11a4f2 100644
--- a/arch/arm/mach-spear13xx/hotplug.c
+++ b/arch/arm/mach-spear13xx/hotplug.c
@@ -17,8 +17,6 @@
 #include <asm/cp15.h>
 #include <asm/smp_plat.h>
-extern volatile int pen_release;
 static inline void cpu_enter_lowpower(void)
 {
        unsigned int v;
@@ -56,7 +54,7 @@ static inline void cpu_leave_lowpower(void)
        : "cc");
 }
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+static inline void spear13xx_do_lowpower(unsigned int cpu, int *spurious)
 {
        for (;;) {
                wfi();
@@ -79,17 +77,12 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
        }
 }
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
 /*
 * platform-specific code to shutdown a CPU
 *
 * Called with IRQs disabled
 */
-void __cpuinit platform_cpu_die(unsigned int cpu)
+void __ref spear13xx_cpu_die(unsigned int cpu)
 {
        int spurious = 0;
@@ -97,7 +90,7 @@ void __cpuinit platform_cpu_die(unsigned int cpu)
         * we're ready for shutdown now, so do it
         */
        cpu_enter_lowpower();
-        platform_do_lowpower(cpu, &spurious);
+        spear13xx_do_lowpower(cpu, &spurious);
        /*
         * bring this CPU back into the world of cache
@@ -108,12 +101,3 @@ void __cpuinit platform_cpu_die(unsigned int cpu)
        if (spurious)
                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 }
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
index dac57fd0cdfd..c33f4d9361bd 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -33,6 +33,9 @@ void __init spear13xx_l2x0_init(void);
 bool dw_dma_filter(struct dma_chan *chan, void *slave);
 void spear_restart(char, const char *);
 void spear13xx_secondary_startup(void);
+void __cpuinit spear13xx_cpu_die(unsigned int cpu);
+extern struct smp_operations spear13xx_smp_ops;
 #ifdef CONFIG_MACH_SPEAR1310
 void __init spear1310_clk_init(void);
diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h
deleted file mode 100644
index 85f176311f63..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/gpio.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/gpio.h
- *
- * GPIO macros for SPEAr13xx machine family
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_GPIO_H
-#define __MACH_GPIO_H
-#include <plat/gpio.h>
-#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index 65f27def239b..07d90acc92c8 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -17,26 +17,26 @@
 #include <asm/memory.h>
 #define PERIP_GRP2_BASE                         UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE                      UL(0xFE000000)
+#define VA_PERIP_GRP2_BASE                      IOMEM(0xFE000000)
 #define MCIF_SDHCI_BASE                         UL(0xB3000000)
 #define SYSRAM0_BASE                            UL(0xB3800000)
-#define VA_SYSRAM0_BASE                         UL(0xFE800000)
+#define VA_SYSRAM0_BASE                         IOMEM(0xFE800000)
 #define SYS_LOCATION                            (VA_SYSRAM0_BASE + 0x600)
 #define PERIP_GRP1_BASE                         UL(0xE0000000)
-#define VA_PERIP_GRP1_BASE                      UL(0xFD000000)
+#define VA_PERIP_GRP1_BASE                      IOMEM(0xFD000000)
 #define UART_BASE                               UL(0xE0000000)
-#define VA_UART_BASE                            UL(0xFD000000)
+#define VA_UART_BASE                            IOMEM(0xFD000000)
 #define SSP_BASE                                UL(0xE0100000)
 #define MISC_BASE                               UL(0xE0700000)
-#define VA_MISC_BASE                            IOMEM(UL(0xFD700000))
+#define VA_MISC_BASE                            IOMEM(0xFD700000)
 #define A9SM_AND_MPMC_BASE                      UL(0xEC000000)
-#define VA_A9SM_AND_MPMC_BASE                   UL(0xFC000000)
+#define VA_A9SM_AND_MPMC_BASE                   IOMEM(0xFC000000)
 /* A9SM peripheral offsets */
 #define A9SM_PERIP_BASE                         UL(0xEC800000)
-#define VA_A9SM_PERIP_BASE                      UL(0xFC800000)
+#define VA_A9SM_PERIP_BASE                      IOMEM(0xFC800000)
 #define VA_SCU_BASE                             (VA_A9SM_PERIP_BASE + 0x00)
 #define L2CC_BASE                               UL(0xED000000)
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
index f5d07f2663d7..2eaa3fa7b432 100644
--- a/arch/arm/mach-spear13xx/platsmp.c
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -19,18 +19,13 @@
 #include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <mach/spear.h>
+#include <mach/generic.h>
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-volatile int __cpuinitdata pen_release = -1;
 static DEFINE_SPINLOCK(boot_lock);
 static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
-extern void spear13xx_secondary_startup(void);
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
 {
        /*
         * if any interrupts are already enabled for the primary
@@ -53,7 +48,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
        spin_unlock(&boot_lock);
 }
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        unsigned long timeout;
@@ -97,7 +92,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 * Initialise the CPU possible map early - this describes the CPUs
 * which may be present or become present in the system.
 */
-void __init smp_init_cpus(void)
+static void __init spear13xx_smp_init_cpus(void)
 {
        unsigned int i, ncores = scu_get_core_count(scu_base);
@@ -113,7 +108,7 @@ void __init smp_init_cpus(void)
        set_smp_cross_call(gic_raise_softirq);
 }
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus)
 {
        scu_enable(scu_base);
@@ -125,3 +120,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
         */
        __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION);
 }
+struct smp_operations spear13xx_smp_ops __initdata = {
+       .smp_init_cpus           = spear13xx_smp_init_cpus,
+       .smp_prepare_cpus        = spear13xx_smp_prepare_cpus,
+       .smp_secondary_init      = spear13xx_secondary_init,
+       .smp_boot_secondary      = spear13xx_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+       .cpu_die                 = spear13xx_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index 732d29bc7330..9fbbfc5650aa 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -78,6 +78,7 @@ static void __init spear1310_map_io(void)
 }
 DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree")
+        .smp            =       smp_ops(spear13xx_smp_ops),
        .map_io         =       spear1310_map_io,
        .init_irq       =       spear13xx_dt_init_irq,
        .handle_irq     =       gic_handle_irq,
diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c
index 81e4ed76ad06..081014fb314a 100644
--- a/arch/arm/mach-spear13xx/spear1340.c
+++ b/arch/arm/mach-spear13xx/spear1340.c
@@ -182,6 +182,7 @@ static const char * const spear1340_dt_board_compat[] = {
 };
 DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree")
+        .smp            =       smp_ops(spear13xx_smp_ops),
        .map_io         =       spear13xx_map_io,
        .init_irq       =       spear13xx_dt_init_irq,
        .handle_irq     =       gic_handle_irq,
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index cf936b106e27..5633d698f1e1 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -78,6 +78,9 @@ struct dw_dma_platform_data dmac_plat_data = {
        .nr_channels = 8,
        .chan_allocation_order = CHAN_ALLOCATION_DESCENDING,
        .chan_priority = CHAN_PRIORITY_DESCENDING,
+        .block_size = 4095U,
+        .nr_masters = 2,
+        .data_width = { 3, 3, 0, 0 },
 };
 void __init spear13xx_l2x0_init(void)
@@ -114,17 +117,17 @@ void __init spear13xx_l2x0_init(void)
 */
 struct map_desc spear13xx_io_desc[] __initdata = {
        {
-                .virtual        = VA_PERIP_GRP2_BASE,
+                .virtual        = (unsigned long)VA_PERIP_GRP2_BASE,
                .pfn            = __phys_to_pfn(PERIP_GRP2_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
        }, {
-                .virtual        = VA_PERIP_GRP1_BASE,
+                .virtual        = (unsigned long)VA_PERIP_GRP1_BASE,
                .pfn            = __phys_to_pfn(PERIP_GRP1_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
        }, {
-                .virtual        = VA_A9SM_AND_MPMC_BASE,
+                .virtual        = (unsigned long)VA_A9SM_AND_MPMC_BASE,
                .pfn            = __phys_to_pfn(A9SM_AND_MPMC_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index d93e2177e6ec..4674a4c221db 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,7 +1,3 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
-dtb-$(CONFIG_MACH_SPEAR300)     += spear300-evb.dtb
-dtb-$(CONFIG_MACH_SPEAR310)     += spear310-evb.dtb
-dtb-$(CONFIG_MACH_SPEAR320)     += spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/include/mach/gpio.h b/arch/arm/mach-spear3xx/include/mach/gpio.h
deleted file mode 100644
index 2ac74c6db7f1..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/gpio.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/gpio.h
- *
- * GPIO macros for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_GPIO_H
-#define __MACH_GPIO_H
-#include <plat/gpio.h>
-#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index af493da37ab6..4674a4c221db 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,5 +1,3 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
-dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb
diff --git a/arch/arm/mach-spear6xx/include/mach/gpio.h b/arch/arm/mach-spear6xx/include/mach/gpio.h
deleted file mode 100644
index d42cefc0356d..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/gpio.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/gpio.h
- *
- * GPIO macros for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_GPIO_H
-#define __MACH_GPIO_H
-#include <plat/gpio.h>
-#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 9077aaa398d9..11680c532b38 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -16,7 +16,7 @@ config ARCH_TEGRA_2x_SOC
        select ARM_ERRATA_742230
        select ARM_ERRATA_751472
        select ARM_ERRATA_754327
-        select ARM_ERRATA_764369
+        select ARM_ERRATA_764369 if SMP
        select PL310_ERRATA_727915 if CACHE_L2X0
        select PL310_ERRATA_769419 if CACHE_L2X0
        select CPU_FREQ_TABLE if CPU_FREQ
@@ -34,11 +34,10 @@ config ARCH_TEGRA_3x_SOC
        select USB_ARCH_HAS_EHCI if USB_SUPPORT
        select USB_ULPI if USB
        select USB_ULPI_VIEWPORT if USB_SUPPORT
-        select USE_OF
        select ARM_ERRATA_743622
        select ARM_ERRATA_751472
        select ARM_ERRATA_754322
-        select ARM_ERRATA_764369
+        select ARM_ERRATA_764369 if SMP
        select PL310_ERRATA_769419 if CACHE_L2X0
        select CPU_FREQ_TABLE if CPU_FREQ
        help
@@ -58,27 +57,6 @@ config TEGRA_AHB
          which controls AHB bus master arbitration and some
          perfomance parameters(priority, prefech size).
-comment "Tegra board type"
-config MACH_HARMONY
-       bool "Harmony board"
-       depends on ARCH_TEGRA_2x_SOC
-       help
-         Support for nVidia Harmony development platform
-config MACH_PAZ00
-       bool "Paz00 board"
-       depends on ARCH_TEGRA_2x_SOC
-       help
-         Support for the Toshiba AC100/Dynabook AZ netbook
-config MACH_TRIMSLICE
-       bool "TrimSlice board"
-       depends on ARCH_TEGRA_2x_SOC
-       select TEGRA_PCI
-       help
-         Support for CompuLab TrimSlice platform
 choice
        prompt "Default low-level debug console UART"
        default TEGRA_DEBUG_UART_NONE
@@ -130,13 +108,6 @@ config TEGRA_DEBUG_UART_AUTO_SCRATCH
 endchoice
-config TEGRA_SYSTEM_DMA
-        bool "Enable system DMA driver for NVIDIA Tegra SoCs"
-        default y
-        help
-          Adds system DMA functionality for NVIDIA Tegra SoCs, used by
-          several Tegra device drivers
 config TEGRA_EMC_SCALING_ENABLE
        bool "Enable scaling the memory frequency"
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index c3d7303b9ac8..9aa653b3eb32 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,6 +1,4 @@
-obj-y                                   += board-pinmux.o
 obj-y                                   += common.o
-obj-y                                   += devices.o
 obj-y                                   += io.o
 obj-y                                   += irq.o
 obj-y                                   += clock.o
@@ -12,27 +10,22 @@ obj-y					+= powergate.o
 obj-y                                   += apbio.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_CPU_IDLE)                  += sleep.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += sleep-t20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks_data.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += sleep-t30.o
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
 obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
-obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
-obj-$(CONFIG_USB_SUPPORT)               += usb_phy.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-dt-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-harmony-pcie.o
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pinmux.o
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pcie.o
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony-power.o
-obj-$(CONFIG_MACH_PAZ00)                += board-paz00.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-paz00.o
-obj-$(CONFIG_MACH_PAZ00)                += board-paz00-pinmux.o
-obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice.o
-obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice-pinmux.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index 7a1bb62ddcf0..29433816233c 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -1,11 +1,3 @@
 zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC)    += 0x00008000
 params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100
 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
-dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-harmony.dtb
-dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-paz00.dtb
-dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-seaboard.dtb
-dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-trimslice.dtb
-dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-ventana.dtb
-dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb
-dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index dc0fe389be56..b5015d0f1912 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -28,7 +28,7 @@
 #include "apbio.h"
-#if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA)
+#if defined(CONFIG_TEGRA20_APB_DMA)
 static DEFINE_MUTEX(tegra_apb_dma_lock);
 static u32 *tegra_apb_bb;
 static dma_addr_t tegra_apb_bb_phys;
@@ -37,121 +37,6 @@ static DECLARE_COMPLETION(tegra_apb_wait);
 static u32 tegra_apb_readl_direct(unsigned long offset);
 static void tegra_apb_writel_direct(u32 value, unsigned long offset);
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-static struct tegra_dma_channel *tegra_apb_dma;
-bool tegra_apb_init(void)
-{
-        struct tegra_dma_channel *ch;
-        mutex_lock(&tegra_apb_dma_lock);
-        /* Check to see if we raced to setup */
-        if (tegra_apb_dma)
-                goto out;
-        ch = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT |
-                TEGRA_DMA_SHARED);
-        if (!ch)
-                goto out_fail;
-        tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
-                &tegra_apb_bb_phys, GFP_KERNEL);
-        if (!tegra_apb_bb) {
-                pr_err("%s: can not allocate bounce buffer\n", __func__);
-                tegra_dma_free_channel(ch);
-                goto out_fail;
-        }
-        tegra_apb_dma = ch;
-out:
-        mutex_unlock(&tegra_apb_dma_lock);
-        return true;
-out_fail:
-        mutex_unlock(&tegra_apb_dma_lock);
-        return false;
-}
-static void apb_dma_complete(struct tegra_dma_req *req)
-{
-        complete(&tegra_apb_wait);
-}
-static u32 tegra_apb_readl_using_dma(unsigned long offset)
-{
-        struct tegra_dma_req req;
-        int ret;
-        if (!tegra_apb_dma && !tegra_apb_init())
-                return tegra_apb_readl_direct(offset);
-        mutex_lock(&tegra_apb_dma_lock);
-        req.complete = apb_dma_complete;
-        req.to_memory = 1;
-        req.dest_addr = tegra_apb_bb_phys;
-        req.dest_bus_width = 32;
-        req.dest_wrap = 1;
-        req.source_addr = offset;
-        req.source_bus_width = 32;
-        req.source_wrap = 4;
-        req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
-        req.size = 4;
-        INIT_COMPLETION(tegra_apb_wait);
-        tegra_dma_enqueue_req(tegra_apb_dma, &req);
-        ret = wait_for_completion_timeout(&tegra_apb_wait,
-                msecs_to_jiffies(50));
-        if (WARN(ret == 0, "apb read dma timed out")) {
-                tegra_dma_dequeue_req(tegra_apb_dma, &req);
-                *(u32 *)tegra_apb_bb = 0;
-        }
-        mutex_unlock(&tegra_apb_dma_lock);
-        return *((u32 *)tegra_apb_bb);
-}
-static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
-{
-        struct tegra_dma_req req;
-        int ret;
-        if (!tegra_apb_dma && !tegra_apb_init()) {
-                tegra_apb_writel_direct(value, offset);
-                return;
-        }
-        mutex_lock(&tegra_apb_dma_lock);
-        *((u32 *)tegra_apb_bb) = value;
-        req.complete = apb_dma_complete;
-        req.to_memory = 0;
-        req.dest_addr = offset;
-        req.dest_wrap = 4;
-        req.dest_bus_width = 32;
-        req.source_addr = tegra_apb_bb_phys;
-        req.source_bus_width = 32;
-        req.source_wrap = 1;
-        req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
-        req.size = 4;
-        INIT_COMPLETION(tegra_apb_wait);
-        tegra_dma_enqueue_req(tegra_apb_dma, &req);
-        ret = wait_for_completion_timeout(&tegra_apb_wait,
-                msecs_to_jiffies(50));
-        if (WARN(ret == 0, "apb write dma timed out"))
-                tegra_dma_dequeue_req(tegra_apb_dma, &req);
-        mutex_unlock(&tegra_apb_dma_lock);
-}
-#else
 static struct dma_chan *tegra_apb_dma_chan;
 static struct dma_slave_config dma_sconfig;
@@ -279,7 +164,6 @@ static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
                pr_err("error in writing offset 0x%08lx using dma\n", offset);
        mutex_unlock(&tegra_apb_dma_lock);
 }
-#endif
 #else
 #define tegra_apb_readl_using_dma tegra_apb_readl_direct
 #define tegra_apb_writel_using_dma tegra_apb_writel_direct
@@ -293,12 +177,12 @@ static apbio_write_fptr apbio_write;
 static u32 tegra_apb_readl_direct(unsigned long offset)
 {
-        return readl(IO_TO_VIRT(offset));
+        return readl(IO_ADDRESS(offset));
 }
 static void tegra_apb_writel_direct(u32 value, unsigned long offset)
 {
-        writel(value, IO_TO_VIRT(offset));
+        writel(value, IO_ADDRESS(offset));
 }
 void tegra_apb_io_init(void)
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index c0999633a9ab..57e235f4ac74 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -28,9 +28,11 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/pda_power.h>
+#include <linux/platform_data/tegra_usb.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/i2c-tegra.h>
+#include <linux/usb/tegra_usb_phy.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
@@ -42,9 +44,32 @@
 #include <mach/irqs.h>
 #include "board.h"
-#include "board-harmony.h"
 #include "clock.h"
-#include "devices.h"
+#include "common.h"
+struct tegra_ehci_platform_data tegra_ehci1_pdata = {
+        .operating_mode = TEGRA_USB_OTG,
+        .power_down_on_bus_suspend = 1,
+        .vbus_gpio = -1,
+};
+struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
+        .reset_gpio = -1,
+        .clk = "cdev2",
+};
+struct tegra_ehci_platform_data tegra_ehci2_pdata = {
+        .phy_config = &tegra_ehci2_ulpi_phy_config,
+        .operating_mode = TEGRA_USB_HOST,
+        .power_down_on_bus_suspend = 1,
+        .vbus_gpio = -1,
+};
+struct tegra_ehci_platform_data tegra_ehci3_pdata = {
+        .operating_mode = TEGRA_USB_HOST,
+        .power_down_on_bus_suspend = 1,
+        .vbus_gpio = -1,
+};
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
@@ -71,6 +96,7 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
        /* name         parent          rate            enabled */
+        { "uarta",      "pll_p",        216000000,      true },
        { "uartd",      "pll_p",        216000000,      true },
        { "usbd",       "clk_m",        12000000,       false },
        { "usb2",       "clk_m",        12000000,       false },
@@ -95,54 +121,40 @@ static void __init tegra_dt_init(void)
                                tegra20_auxdata_lookup, NULL);
 }
-#ifdef CONFIG_MACH_TRIMSLICE
 static void __init trimslice_init(void)
 {
+#ifdef CONFIG_TEGRA_PCI
        int ret;
        ret = tegra_pcie_init(true, true);
        if (ret)
                pr_err("tegra_pci_init() failed: %d\n", ret);
-}
 #endif
+}
-#ifdef CONFIG_MACH_HARMONY
 static void __init harmony_init(void)
 {
+#ifdef CONFIG_TEGRA_PCI
        int ret;
-        ret = harmony_regulator_init();
-        if (ret) {
-                pr_err("harmony_regulator_init() failed: %d\n", ret);
-                return;
-        }
        ret = harmony_pcie_init();
        if (ret)
                pr_err("harmony_pcie_init() failed: %d\n", ret);
-}
 #endif
+}
-#ifdef CONFIG_MACH_PAZ00
 static void __init paz00_init(void)
 {
        tegra_paz00_wifikill_init();
 }
-#endif
 static struct {
        char *machine;
        void (*init)(void);
 } board_init_funcs[] = {
-#ifdef CONFIG_MACH_TRIMSLICE
        { "compulab,trimslice", trimslice_init },
-#endif
-#ifdef CONFIG_MACH_HARMONY
        { "nvidia,harmony", harmony_init },
-#endif
-#ifdef CONFIG_MACH_PAZ00
        { "compal,paz00", paz00_init },
-#endif
 };
 static void __init tegra_dt_init_late(void)
@@ -166,6 +178,7 @@ static const char *tegra20_dt_board_compat[] = {
 DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
        .map_io         = tegra_map_common_io,
+        .smp            = smp_ops(tegra_smp_ops),
        .init_early     = tegra20_init_early,
        .init_irq       = tegra_dt_init_irq,
        .handle_irq     = gic_handle_irq,
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 53bf60f11580..e4a676d4ddf7 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -37,6 +37,7 @@
 #include "board.h"
 #include "clock.h"
+#include "common.h"
 struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
@@ -83,6 +84,7 @@ static const char *tegra30_dt_board_compat[] = {
 };
 DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
+        .smp            = smp_ops(tegra_smp_ops),
        .map_io         = tegra_map_common_io,
        .init_early     = tegra30_init_early,
        .init_irq       = tegra_dt_init_irq,
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index e8c3fda9bec2..3cdc1bb8254c 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -18,35 +18,57 @@
 #include <linux/kernel.h>
 #include <linux/gpio.h>
 #include <linux/err.h>
+#include <linux/of_gpio.h>
 #include <linux/regulator/consumer.h>
 #include <asm/mach-types.h>
 #include "board.h"
-#include "board-harmony.h"
 #ifdef CONFIG_TEGRA_PCI
 int __init harmony_pcie_init(void)
 {
+        struct device_node *np;
+        int en_vdd_1v05;
        struct regulator *regulator = NULL;
        int err;
-        err = gpio_request(TEGRA_GPIO_EN_VDD_1V05_GPIO, "EN_VDD_1V05");
+        np = of_find_node_by_path("/regulators/regulator@3");
-        if (err)
+        if (!np) {
+                pr_err("%s: of_find_node_by_path failed\n", __func__);
+                return -ENODEV;
+        }
+        en_vdd_1v05 = of_get_named_gpio(np, "gpio", 0);
+        if (en_vdd_1v05 < 0) {
+                pr_err("%s: of_get_named_gpio failed: %d\n", __func__,
+                       en_vdd_1v05);
+                return en_vdd_1v05;
+        }
+        err = gpio_request(en_vdd_1v05, "EN_VDD_1V05");
+        if (err) {
+                pr_err("%s: gpio_request failed: %d\n", __func__, err);
                return err;
+        }
-        gpio_direction_output(TEGRA_GPIO_EN_VDD_1V05_GPIO, 1);
+        gpio_direction_output(en_vdd_1v05, 1);
-        regulator = regulator_get(NULL, "pex_clk");
+        regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk");
-        if (IS_ERR_OR_NULL(regulator))
+        if (IS_ERR_OR_NULL(regulator)) {
+                pr_err("%s: regulator_get failed: %d\n", __func__,
+                       (int)PTR_ERR(regulator));
                goto err_reg;
+        }
        regulator_enable(regulator);
        err = tegra_pcie_init(true, true);
-        if (err)
+        if (err) {
+                pr_err("%s: tegra_pcie_init failed: %d\n", __func__, err);
                goto err_pcie;
+        }
        return 0;
@@ -54,20 +76,9 @@ err_pcie:
        regulator_disable(regulator);
        regulator_put(regulator);
 err_reg:
-        gpio_free(TEGRA_GPIO_EN_VDD_1V05_GPIO);
+        gpio_free(en_vdd_1v05);
        return err;
 }
-static int __init harmony_pcie_initcall(void)
-{
-        if (!machine_is_harmony())
-                return 0;
-        return harmony_pcie_init();
-}
-/* PCI should be initialized after I2C, mfd and regulators */
-subsys_initcall_sync(harmony_pcie_initcall);
 #endif
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
deleted file mode 100644
index 83d420fbc58c..000000000000
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony-pinmux.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include "board-harmony.h"
-#include "board-pinmux.h"
-static struct pinctrl_map harmony_map[] = {
-        TEGRA_MAP_MUXCONF("ata",   "ide",           none, driven),
-        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("atc",   "nand",          none, driven),
-        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, tristate),
-        TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-        TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", down, tristate),
-        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-        TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, tristate),
-        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-        TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-        TEGRA_MAP_MUXCONF("dta",   "sdio2",         up,   driven),
-        TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, driven),
-        TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
-        TEGRA_MAP_MUXCONF("dtd",   "sdio2",         up,   driven),
-        TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
-        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, tristate),
-        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("gmc",   "uartd",         none, driven),
-        TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("gpu",   "gmi",           none, tristate),
-        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
-        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
-        TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   tristate),
-        TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   tristate),
-        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("owc",   "rsvd2",         na,   tristate),
-        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
-        TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
-        TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
-        TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
-        TEGRA_MAP_MUXCONF("sdc",   "pwm",           up,   driven),
-        TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
-        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, tristate),
-        TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("slxc",  "spdif",         none, tristate),
-        TEGRA_MAP_MUXCONF("slxd",  "spdif",         none, tristate),
-        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
-        TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, tristate),
-        TEGRA_MAP_MUXCONF("spia",  "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("spib",  "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   tristate),
-        TEGRA_MAP_MUXCONF("spid",  "spi1",          down, tristate),
-        TEGRA_MAP_MUXCONF("spie",  "spi1",          up,   tristate),
-        TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
-        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      none, tristate),
-        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   tristate),
-        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   tristate),
-        TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, tristate),
-        TEGRA_MAP_MUXCONF("uad",   "irda",          up,   tristate),
-        TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-        TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, tristate),
-        TEGRA_MAP_CONF("ck32",    none, na),
-        TEGRA_MAP_CONF("ddrc",    none, na),
-        TEGRA_MAP_CONF("pmca",    none, na),
-        TEGRA_MAP_CONF("pmcb",    none, na),
-        TEGRA_MAP_CONF("pmcc",    none, na),
-        TEGRA_MAP_CONF("pmcd",    none, na),
-        TEGRA_MAP_CONF("pmce",    none, na),
-        TEGRA_MAP_CONF("xm2c",    none, na),
-        TEGRA_MAP_CONF("xm2d",    none, na),
-        TEGRA_MAP_CONF("ls",      up,   na),
-        TEGRA_MAP_CONF("lc",      up,   na),
-        TEGRA_MAP_CONF("ld17_0",  down, na),
-        TEGRA_MAP_CONF("ld19_18", down, na),
-        TEGRA_MAP_CONF("ld21_20", down, na),
-        TEGRA_MAP_CONF("ld23_22", down, na),
-};
-static struct tegra_board_pinmux_conf conf = {
-        .maps = harmony_map,
-        .map_count = ARRAY_SIZE(harmony_map),
-};
-void harmony_pinmux_init(void)
-{
-        tegra_board_pinmux_init(&conf, NULL);
-}
diff --git a/arch/arm/mach-tegra/board-harmony-power.c b/arch/arm/mach-tegra/board-harmony-power.c
deleted file mode 100644
index b7344beec102..000000000000
--- a/arch/arm/mach-tegra/board-harmony-power.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (C) 2010 NVIDIA, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- * 02111-1307, USA
- */
-#include <linux/i2c.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/tps6586x.h>
-#include <linux/of.h>
-#include <linux/of_i2c.h>
-#include <asm/mach-types.h>
-#include <mach/irqs.h>
-#include "board-harmony.h"
-static struct regulator_consumer_supply tps658621_ldo0_supply[] = {
-        REGULATOR_SUPPLY("pex_clk", NULL),
-};
-static struct regulator_init_data ldo0_data = {
-        .supply_regulator = "vdd_sm2",
-        .constraints = {
-                .name = "vdd_ldo0",
-                .min_uV = 3300 * 1000,
-                .max_uV = 3300 * 1000,
-                .valid_modes_mask = (REGULATOR_MODE_NORMAL |
-                                     REGULATOR_MODE_STANDBY),
-                .valid_ops_mask = (REGULATOR_CHANGE_MODE |
-                                   REGULATOR_CHANGE_STATUS |
-                                   REGULATOR_CHANGE_VOLTAGE),
-                .apply_uV = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(tps658621_ldo0_supply),
-        .consumer_supplies = tps658621_ldo0_supply,
-};
-#define HARMONY_REGULATOR_INIT(_id, _name, _supply, _minmv, _maxmv, _on)\
-        static struct regulator_init_data _id##_data = {                \
-                .supply_regulator = _supply,                            \
-                .constraints = {                                        \
-                        .name = _name,                                  \
-                        .min_uV = (_minmv)*1000,                        \
-                        .max_uV = (_maxmv)*1000,                        \
-                        .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
-                                             REGULATOR_MODE_STANDBY),   \
-                        .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
-                                           REGULATOR_CHANGE_STATUS |    \
-                                           REGULATOR_CHANGE_VOLTAGE),   \
-                        .always_on = _on,                               \
-                },                                                      \
-        }
-HARMONY_REGULATOR_INIT(sm0,  "vdd_sm0",  "vdd_sys", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(sm1,  "vdd_sm1",  "vdd_sys", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(sm2,  "vdd_sm2",  "vdd_sys", 3000, 4550, 1);
-HARMONY_REGULATOR_INIT(ldo1, "vdd_ldo1", "vdd_sm2", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(ldo2, "vdd_ldo2", "vdd_sm2", 725, 1500, 0);
-HARMONY_REGULATOR_INIT(ldo3, "vdd_ldo3", "vdd_sm2", 1250, 3300, 1);
-HARMONY_REGULATOR_INIT(ldo4, "vdd_ldo4", "vdd_sm2", 1700, 2475, 1);
-HARMONY_REGULATOR_INIT(ldo5, "vdd_ldo5", NULL,      1250, 3300, 1);
-HARMONY_REGULATOR_INIT(ldo6, "vdd_ldo6", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo7, "vdd_ldo7", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo8, "vdd_ldo8", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo9, "vdd_ldo9", "vdd_sm2", 1250, 3300, 1);
-#define TPS_REG(_id, _data)                     \
-        {                                       \
-                .id = TPS6586X_ID_##_id,        \
-                .name = "tps6586x-regulator",   \
-                .platform_data = _data,         \
-        }
-static struct tps6586x_subdev_info tps_devs[] = {
-        TPS_REG(SM_0, &sm0_data),
-        TPS_REG(SM_1, &sm1_data),
-        TPS_REG(SM_2, &sm2_data),
-        TPS_REG(LDO_0, &ldo0_data),
-        TPS_REG(LDO_1, &ldo1_data),
-        TPS_REG(LDO_2, &ldo2_data),
-        TPS_REG(LDO_3, &ldo3_data),
-        TPS_REG(LDO_4, &ldo4_data),
-        TPS_REG(LDO_5, &ldo5_data),
-        TPS_REG(LDO_6, &ldo6_data),
-        TPS_REG(LDO_7, &ldo7_data),
-        TPS_REG(LDO_8, &ldo8_data),
-        TPS_REG(LDO_9, &ldo9_data),
-};
-static struct tps6586x_platform_data tps_platform = {
-        .irq_base       = TEGRA_NR_IRQS,
-        .num_subdevs    = ARRAY_SIZE(tps_devs),
-        .subdevs        = tps_devs,
-        .gpio_base      = HARMONY_GPIO_TPS6586X(0),
-};
-static struct i2c_board_info __initdata harmony_regulators[] = {
-        {
-                I2C_BOARD_INFO("tps6586x", 0x34),
-                .irq            = INT_EXTERNAL_PMU,
-                .platform_data  = &tps_platform,
-        },
-};
-int __init harmony_regulator_init(void)
-{
-        regulator_register_always_on(0, "vdd_sys",
-                NULL, 0, 5000000);
-        if (machine_is_harmony()) {
-                i2c_register_board_info(3, harmony_regulators, 1);
-        } else { /* Harmony, booted using device tree */
-                struct device_node *np;
-                struct i2c_adapter *adapter;
-                np = of_find_node_by_path("/i2c@7000d000");
-                if (np == NULL) {
-                        pr_err("Could not find device_node for DVC I2C\n");
-                        return -ENODEV;
-                }
-                adapter = of_find_i2c_adapter_by_node(np);
-                if (!adapter) {
-                        pr_err("Could not find i2c_adapter for DVC I2C\n");
-                        return -ENODEV;
-                }
-                i2c_new_device(adapter, harmony_regulators);
-        }
-        return 0;
-}
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
deleted file mode 100644
index e65e837f4013..000000000000
--- a/arch/arm/mach-tegra/board-harmony.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2011 NVIDIA, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-#include <linux/pda_power.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-#include <sound/wm8903.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/hardware/gic.h>
-#include <asm/setup.h>
-#include <mach/tegra_wm8903_pdata.h>
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/sdhci.h>
-#include "board.h"
-#include "board-harmony.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-static struct plat_serial8250_port debug_uart_platform_data[] = {
-        {
-                .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
-                .mapbase        = TEGRA_UARTD_BASE,
-                .irq            = INT_UARTD,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-                .type           = PORT_TEGRA,
-                .handle_break   = tegra_serial_handle_break,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 216000000,
-        }, {
-                .flags          = 0
-        }
-};
-static struct platform_device debug_uart = {
-        .name = "serial8250",
-        .id = PLAT8250_DEV_PLATFORM,
-        .dev = {
-                .platform_data = debug_uart_platform_data,
-        },
-};
-static struct tegra_wm8903_platform_data harmony_audio_pdata = {
-        .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
-        .gpio_hp_det            = TEGRA_GPIO_HP_DET,
-        .gpio_hp_mute           = -1,
-        .gpio_int_mic_en        = TEGRA_GPIO_INT_MIC_EN,
-        .gpio_ext_mic_en        = TEGRA_GPIO_EXT_MIC_EN,
-};
-static struct platform_device harmony_audio_device = {
-        .name   = "tegra-snd-wm8903",
-        .id     = 0,
-        .dev    = {
-                .platform_data  = &harmony_audio_pdata,
-        },
-};
-static struct wm8903_platform_data harmony_wm8903_pdata = {
-        .irq_active_low = 0,
-        .micdet_cfg = 0,
-        .micdet_delay = 100,
-        .gpio_base = HARMONY_GPIO_WM8903(0),
-        .gpio_cfg = {
-                0,
-                0,
-                WM8903_GPIO_CONFIG_ZERO,
-                0,
-                0,
-        },
-};
-static struct i2c_board_info __initdata wm8903_board_info = {
-        I2C_BOARD_INFO("wm8903", 0x1a),
-        .platform_data = &harmony_wm8903_pdata,
-};
-static void __init harmony_i2c_init(void)
-{
-        platform_device_register(&tegra_i2c_device1);
-        platform_device_register(&tegra_i2c_device2);
-        platform_device_register(&tegra_i2c_device3);
-        platform_device_register(&tegra_i2c_device4);
-        wm8903_board_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
-        i2c_register_board_info(0, &wm8903_board_info, 1);
-}
-static struct platform_device *harmony_devices[] __initdata = {
-        &debug_uart,
-        &tegra_sdhci_device1,
-        &tegra_sdhci_device2,
-        &tegra_sdhci_device4,
-        &tegra_ehci3_device,
-        &tegra_i2s_device1,
-        &tegra_das_device,
-        &harmony_audio_device,
-};
-static void __init tegra_harmony_fixup(struct tag *tags, char **cmdline,
-        struct meminfo *mi)
-{
-        mi->nr_banks = 2;
-        mi->bank[0].start = PHYS_OFFSET;
-        mi->bank[0].size = 448 * SZ_1M;
-        mi->bank[1].start = SZ_512M;
-        mi->bank[1].size = SZ_512M;
-}
-static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "uartd",      "pll_p",        216000000,      true },
-        { "pll_a",      "pll_p_out1",   56448000,       true },
-        { "pll_a_out0", "pll_a",        11289600,       true },
-        { "cdev1",      NULL,           0,              true },
-        { "i2s1",       "pll_a_out0",   11289600,       false},
-        { "usb3",       "clk_m",        12000000,       true },
-        { NULL,         NULL,           0,              0},
-};
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
-        .cd_gpio        = -1,
-        .wp_gpio        = -1,
-        .power_gpio     = -1,
-};
-static struct tegra_sdhci_platform_data sdhci_pdata2 = {
-        .cd_gpio        = TEGRA_GPIO_SD2_CD,
-        .wp_gpio        = TEGRA_GPIO_SD2_WP,
-        .power_gpio     = TEGRA_GPIO_SD2_POWER,
-};
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
-        .cd_gpio        = TEGRA_GPIO_SD4_CD,
-        .wp_gpio        = TEGRA_GPIO_SD4_WP,
-        .power_gpio     = TEGRA_GPIO_SD4_POWER,
-        .is_8bit        = 1,
-};
-static void __init tegra_harmony_init(void)
-{
-        tegra_clk_init_from_table(harmony_clk_init_table);
-        harmony_pinmux_init();
-        tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
-        tegra_sdhci_device2.dev.platform_data = &sdhci_pdata2;
-        tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-        platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices));
-        harmony_i2c_init();
-        harmony_regulator_init();
-}
-MACHINE_START(HARMONY, "harmony")
-        .atag_offset    = 0x100,
-        .fixup          = tegra_harmony_fixup,
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra20_init_early,
-        .init_irq       = tegra_init_irq,
-        .handle_irq     = gic_handle_irq,
-        .timer          = &tegra_timer,
-        .init_machine   = tegra_harmony_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-harmony.h b/arch/arm/mach-tegra/board-harmony.h
deleted file mode 100644
index 139d96c93843..000000000000
--- a/arch/arm/mach-tegra/board-harmony.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef _MACH_TEGRA_BOARD_HARMONY_H
-#define _MACH_TEGRA_BOARD_HARMONY_H
-#include <mach/gpio-tegra.h>
-#define HARMONY_GPIO_TPS6586X(_x_)      (TEGRA_NR_GPIOS + (_x_))
-#define HARMONY_GPIO_WM8903(_x_)        (HARMONY_GPIO_TPS6586X(4) + (_x_))
-#define TEGRA_GPIO_SD2_CD               TEGRA_GPIO_PI5
-#define TEGRA_GPIO_SD2_WP               TEGRA_GPIO_PH1
-#define TEGRA_GPIO_SD2_POWER            TEGRA_GPIO_PT3
-#define TEGRA_GPIO_SD4_CD               TEGRA_GPIO_PH2
-#define TEGRA_GPIO_SD4_WP               TEGRA_GPIO_PH3
-#define TEGRA_GPIO_SD4_POWER            TEGRA_GPIO_PI6
-#define TEGRA_GPIO_CDC_IRQ              TEGRA_GPIO_PX3
-#define TEGRA_GPIO_SPKR_EN              HARMONY_GPIO_WM8903(2)
-#define TEGRA_GPIO_HP_DET               TEGRA_GPIO_PW2
-#define TEGRA_GPIO_INT_MIC_EN           TEGRA_GPIO_PX0
-#define TEGRA_GPIO_EXT_MIC_EN           TEGRA_GPIO_PX1
-#define TEGRA_GPIO_EN_VDD_1V05_GPIO     HARMONY_GPIO_TPS6586X(2)
-void harmony_pinmux_init(void);
-int harmony_regulator_init(void);
-#endif
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
deleted file mode 100644
index 6f1111b48e7c..000000000000
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-paz00-pinmux.c
- *
- * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include "board-paz00.h"
-#include "board-pinmux.h"
-static struct pinctrl_map paz00_map[] = {
-        TEGRA_MAP_MUXCONF("ata",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("atc",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, driven),
-        TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-        TEGRA_MAP_MUXCONF("csus",  "pllc_out1",     down, tristate),
-        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-        TEGRA_MAP_MUXCONF("dap2",  "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-        TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-        TEGRA_MAP_MUXCONF("dta",   "rsvd1",         up,   tristate),
-        TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, tristate),
-        TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
-        TEGRA_MAP_MUXCONF("dtd",   "rsvd1",         up,   tristate),
-        TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
-        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, driven),
-        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("gmc",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("gpu",   "pwm",           none, driven),
-        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   driven),
-        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
-        TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   driven),
-        TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   driven),
-        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcb",  "sdio2",         up,   driven),
-        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcd",  "sdio2",         up,   driven),
-        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("owc",   "owr",           up,   tristate),
-        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
-        TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
-        TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
-        TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
-        TEGRA_MAP_MUXCONF("sdc",   "twc",           up,   tristate),
-        TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
-        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
-        TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, tristate),
-        TEGRA_MAP_MUXCONF("slxc",  "spi4",          none, tristate),
-        TEGRA_MAP_MUXCONF("slxd",  "spi4",          none, tristate),
-        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
-        TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, driven),
-        TEGRA_MAP_MUXCONF("spia",  "gmi",           down, tristate),
-        TEGRA_MAP_MUXCONF("spib",  "gmi",           down, tristate),
-        TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   driven),
-        TEGRA_MAP_MUXCONF("spid",  "gmi",           down, tristate),
-        TEGRA_MAP_MUXCONF("spie",  "gmi",           up,   tristate),
-        TEGRA_MAP_MUXCONF("spif",  "rsvd4",         down, tristate),
-        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   driven),
-        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   driven),
-        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   driven),
-        TEGRA_MAP_MUXCONF("uac",   "rsvd4",         none, driven),
-        TEGRA_MAP_MUXCONF("uad",   "spdif",         up,   tristate),
-        TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-        TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, driven),
-        TEGRA_MAP_CONF("ck32",    none, na),
-        TEGRA_MAP_CONF("ddrc",    none, na),
-        TEGRA_MAP_CONF("pmca",    none, na),
-        TEGRA_MAP_CONF("pmcb",    none, na),
-        TEGRA_MAP_CONF("pmcc",    none, na),
-        TEGRA_MAP_CONF("pmcd",    none, na),
-        TEGRA_MAP_CONF("pmce",    none, na),
-        TEGRA_MAP_CONF("xm2c",    none, na),
-        TEGRA_MAP_CONF("xm2d",    none, na),
-        TEGRA_MAP_CONF("ls",      up,   na),
-        TEGRA_MAP_CONF("lc",      up,   na),
-        TEGRA_MAP_CONF("ld17_0",  down, na),
-        TEGRA_MAP_CONF("ld19_18", down, na),
-        TEGRA_MAP_CONF("ld21_20", down, na),
-        TEGRA_MAP_CONF("ld23_22", down, na),
-};
-static struct tegra_board_pinmux_conf conf = {
-        .maps = paz00_map,
-        .map_count = ARRAY_SIZE(paz00_map),
-};
-void paz00_pinmux_init(void)
-{
-        tegra_board_pinmux_init(&conf, NULL);
-}
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 4b64af5cab27..740e16f64728 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -17,72 +17,10 @@
 *
 */
-#include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio_keys.h>
-#include <linux/pda_power.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
 #include <linux/rfkill-gpio.h>
-#include <asm/hardware/gic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/setup.h>
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/sdhci.h>
 #include "board.h"
 #include "board-paz00.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-static struct plat_serial8250_port debug_uart_platform_data[] = {
-        {
-                /* serial port on JP1 */
-                .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
-                .mapbase        = TEGRA_UARTA_BASE,
-                .irq            = INT_UARTA,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-                .type           = PORT_TEGRA,
-                .handle_break   = tegra_serial_handle_break,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 216000000,
-        }, {
-                /* serial port on mini-pcie */
-                .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
-                .mapbase        = TEGRA_UARTC_BASE,
-                .irq            = INT_UARTC,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-                .type           = PORT_TEGRA,
-                .handle_break   = tegra_serial_handle_break,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 216000000,
-        }, {
-                .flags          = 0
-        }
-};
-static struct platform_device debug_uart = {
-        .name = "serial8250",
-        .id = PLAT8250_DEV_PLATFORM,
-        .dev = {
-                .platform_data = debug_uart_platform_data,
-        },
-};
 static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = {
        .name           = "wifi_rfkill",
@@ -99,137 +37,7 @@ static struct platform_device wifi_rfkill_device = {
        },
 };
-static struct gpio_led gpio_leds[] = {
-        {
-                .name                   = "wifi-led",
-                .default_trigger        = "rfkill0",
-                .gpio                   = TEGRA_WIFI_LED,
-        },
-};
-static struct gpio_led_platform_data gpio_led_info = {
-        .leds           = gpio_leds,
-        .num_leds       = ARRAY_SIZE(gpio_leds),
-};
-static struct platform_device leds_gpio = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &gpio_led_info,
-        },
-};
-static struct gpio_keys_button paz00_gpio_keys_buttons[] = {
-        {
-                .code           = KEY_POWER,
-                .gpio           = TEGRA_GPIO_POWERKEY,
-                .active_low     = 1,
-                .desc           = "Power",
-                .type           = EV_KEY,
-                .wakeup         = 1,
-        },
-};
-static struct gpio_keys_platform_data paz00_gpio_keys = {
-        .buttons        = paz00_gpio_keys_buttons,
-        .nbuttons       = ARRAY_SIZE(paz00_gpio_keys_buttons),
-};
-static struct platform_device gpio_keys_device = {
-        .name   = "gpio-keys",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &paz00_gpio_keys,
-        },
-};
-static struct platform_device *paz00_devices[] __initdata = {
-        &debug_uart,
-        &tegra_sdhci_device4,
-        &tegra_sdhci_device1,
-        &leds_gpio,
-        &gpio_keys_device,
-};
-static void paz00_i2c_init(void)
-{
-        platform_device_register(&tegra_i2c_device1);
-        platform_device_register(&tegra_i2c_device2);
-        platform_device_register(&tegra_i2c_device4);
-}
-static void paz00_usb_init(void)
-{
-        tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_ULPI_RST;
-        platform_device_register(&tegra_ehci2_device);
-        platform_device_register(&tegra_ehci3_device);
-}
-static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
-        struct meminfo *mi)
-{
-        mi->nr_banks = 1;
-        mi->bank[0].start = PHYS_OFFSET;
-        mi->bank[0].size = 448 * SZ_1M;
-}
-static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "uarta",      "pll_p",        216000000,      true },
-        { "uartc",      "pll_p",        216000000,      true },
-        { "usbd",       "clk_m",        12000000,       false },
-        { "usb2",       "clk_m",        12000000,       false },
-        { "usb3",       "clk_m",        12000000,       false },
-        { NULL,         NULL,           0,              0},
-};
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
-        .cd_gpio        = TEGRA_GPIO_SD1_CD,
-        .wp_gpio        = TEGRA_GPIO_SD1_WP,
-        .power_gpio     = TEGRA_GPIO_SD1_POWER,
-};
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
-        .cd_gpio        = -1,
-        .wp_gpio        = -1,
-        .power_gpio     = -1,
-        .is_8bit        = 1,
-};
 void __init tegra_paz00_wifikill_init(void)
 {
        platform_device_register(&wifi_rfkill_device);
 }
-static void __init tegra_paz00_init(void)
-{
-        tegra_clk_init_from_table(paz00_clk_init_table);
-        paz00_pinmux_init();
-        tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
-        tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-        platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices));
-        tegra_paz00_wifikill_init();
-        paz00_i2c_init();
-        paz00_usb_init();
-}
-MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
-        .atag_offset    = 0x100,
-        .fixup          = tegra_paz00_fixup,
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra20_init_early,
-        .init_irq       = tegra_init_irq,
-        .handle_irq     = gic_handle_irq,
-        .timer          = &tegra_timer,
-        .init_machine   = tegra_paz00_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index 3c9f8da37ea3..25c08ecef52f 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -17,24 +17,9 @@
 #ifndef _MACH_TEGRA_BOARD_PAZ00_H
 #define _MACH_TEGRA_BOARD_PAZ00_H
-#include <mach/gpio-tegra.h>
+#include "gpio-names.h"
-/* SDCARD */
-#define TEGRA_GPIO_SD1_CD               TEGRA_GPIO_PV5
-#define TEGRA_GPIO_SD1_WP               TEGRA_GPIO_PH1
-#define TEGRA_GPIO_SD1_POWER            TEGRA_GPIO_PV1
-/* ULPI */
-#define TEGRA_ULPI_RST                  TEGRA_GPIO_PV0
-/* WIFI */
 #define TEGRA_WIFI_PWRN                 TEGRA_GPIO_PK5
 #define TEGRA_WIFI_RST                  TEGRA_GPIO_PD1
-#define TEGRA_WIFI_LED                  TEGRA_GPIO_PD0
-/* WakeUp */
-#define TEGRA_GPIO_POWERKEY     TEGRA_GPIO_PJ7
-void paz00_pinmux_init(void);
 #endif
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
deleted file mode 100644
index a5574c71b931..000000000000
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (c) 2011,2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/device.h>
-#include <linux/kernel.h>
-#include <linux/notifier.h>
-#include <linux/string.h>
-#include "board-pinmux.h"
-#include "devices.h"
-unsigned long tegra_pincfg_pullnone_driven[2] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-};
-unsigned long tegra_pincfg_pullnone_tristate[2] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
-};
-unsigned long tegra_pincfg_pullnone_na[1] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
-};
-unsigned long tegra_pincfg_pullup_driven[2] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-};
-unsigned long tegra_pincfg_pullup_tristate[2] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
-};
-unsigned long tegra_pincfg_pullup_na[1] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
-};
-unsigned long tegra_pincfg_pulldown_driven[2] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-};
-unsigned long tegra_pincfg_pulldown_tristate[2] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
-};
-unsigned long tegra_pincfg_pulldown_na[1] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
-};
-unsigned long tegra_pincfg_pullna_driven[1] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-};
-unsigned long tegra_pincfg_pullna_tristate[1] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
-};
-static struct platform_device *devices[] = {
-        &tegra_gpio_device,
-        &tegra_pinmux_device,
-};
-void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
-                             struct tegra_board_pinmux_conf *conf_b)
-{
-        if (conf_a)
-                pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
-        if (conf_b)
-                pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-}
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
deleted file mode 100644
index c5f3f3381e86..000000000000
--- a/arch/arm/mach-tegra/board-pinmux.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2011,2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_TEGRA_BOARD_PINMUX_H
-#define __MACH_TEGRA_BOARD_PINMUX_H
-#include <linux/pinctrl/machine.h>
-#include <mach/pinconf-tegra.h>
-#define PINMUX_DEV "tegra20-pinctrl"
-#define TEGRA_MAP_MUX(_group_, _function_) \
-        PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
-#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
-        PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
-#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
-        TEGRA_MAP_MUX(_group_, _function_), \
-        TEGRA_MAP_CONF(_group_, _pull_, _drive_)
-extern unsigned long tegra_pincfg_pullnone_driven[2];
-extern unsigned long tegra_pincfg_pullnone_tristate[2];
-extern unsigned long tegra_pincfg_pullnone_na[1];
-extern unsigned long tegra_pincfg_pullup_driven[2];
-extern unsigned long tegra_pincfg_pullup_tristate[2];
-extern unsigned long tegra_pincfg_pullup_na[1];
-extern unsigned long tegra_pincfg_pulldown_driven[2];
-extern unsigned long tegra_pincfg_pulldown_tristate[2];
-extern unsigned long tegra_pincfg_pulldown_na[1];
-extern unsigned long tegra_pincfg_pullna_driven[1];
-extern unsigned long tegra_pincfg_pullna_tristate[1];
-struct tegra_board_pinmux_conf {
-        struct pinctrl_map *maps;
-        int map_count;
-};
-void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
-                             struct tegra_board_pinmux_conf *conf_b);
-#endif
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
deleted file mode 100644
index 7b39511c0d4d..000000000000
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice-pinmux.c
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include "board-trimslice.h"
-#include "board-pinmux.h"
-static struct pinctrl_map trimslice_map[] = {
-        TEGRA_MAP_MUXCONF("ata",   "ide",           none, tristate),
-        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("atc",   "nand",          none, tristate),
-        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, tristate),
-        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, tristate),
-        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, tristate),
-        TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-        TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", down, tristate),
-        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-        TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, tristate),
-        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-        TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-        TEGRA_MAP_MUXCONF("dta",   "vi",            none, tristate),
-        TEGRA_MAP_MUXCONF("dtb",   "vi",            none, tristate),
-        TEGRA_MAP_MUXCONF("dtc",   "vi",            none, tristate),
-        TEGRA_MAP_MUXCONF("dtd",   "vi",            none, tristate),
-        TEGRA_MAP_MUXCONF("dte",   "vi",            none, tristate),
-        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          up,   driven),
-        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("gmb",   "nand",          none, tristate),
-        TEGRA_MAP_MUXCONF("gmc",   "sflash",        none, driven),
-        TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, driven),
-        TEGRA_MAP_MUXCONF("gme",   "gmi",           none, tristate),
-        TEGRA_MAP_MUXCONF("gpu",   "uarta",         none, driven),
-        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
-        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, tristate),
-        TEGRA_MAP_MUXCONF("irrx",  "uartb",         up,   tristate),
-        TEGRA_MAP_MUXCONF("irtx",  "uartb",         up,   tristate),
-        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   tristate),
-        TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   tristate),
-        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   tristate),
-        TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   tristate),
-        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   tristate),
-        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   tristate),
-        TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("owc",   "rsvd2",         up,   tristate),
-        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   tristate),
-        TEGRA_MAP_MUXCONF("pta",   "gmi",           none, tristate),
-        TEGRA_MAP_MUXCONF("rm",    "i2c1",          up,   driven),
-        TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   driven),
-        TEGRA_MAP_MUXCONF("sdc",   "pwm",           up,   driven),
-        TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   driven),
-        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
-        TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("slxc",  "sdio3",         none, tristate),
-        TEGRA_MAP_MUXCONF("slxd",  "sdio3",         none, tristate),
-        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("spdi",  "spdif",         none, tristate),
-        TEGRA_MAP_MUXCONF("spdo",  "spdif",         none, tristate),
-        TEGRA_MAP_MUXCONF("spia",  "spi2",          down, tristate),
-        TEGRA_MAP_MUXCONF("spib",  "spi2",          down, tristate),
-        TEGRA_MAP_MUXCONF("spic",  "spi2",          up,   tristate),
-        TEGRA_MAP_MUXCONF("spid",  "spi1",          down, tristate),
-        TEGRA_MAP_MUXCONF("spie",  "spi1",          up,   tristate),
-        TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
-        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   tristate),
-        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   tristate),
-        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   tristate),
-        TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, driven),
-        TEGRA_MAP_MUXCONF("uad",   "irda",          up,   tristate),
-        TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-        TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, tristate),
-        TEGRA_MAP_CONF("ck32",    none, na),
-        TEGRA_MAP_CONF("ddrc",    none, na),
-        TEGRA_MAP_CONF("pmca",    none, na),
-        TEGRA_MAP_CONF("pmcb",    none, na),
-        TEGRA_MAP_CONF("pmcc",    none, na),
-        TEGRA_MAP_CONF("pmcd",    none, na),
-        TEGRA_MAP_CONF("pmce",    none, na),
-        TEGRA_MAP_CONF("xm2c",    none, na),
-        TEGRA_MAP_CONF("xm2d",    none, na),
-        TEGRA_MAP_CONF("ls",      up,   na),
-        TEGRA_MAP_CONF("lc",      up,   na),
-        TEGRA_MAP_CONF("ld17_0",  down, na),
-        TEGRA_MAP_CONF("ld19_18", down, na),
-        TEGRA_MAP_CONF("ld21_20", down, na),
-        TEGRA_MAP_CONF("ld23_22", down, na),
-};
-static struct tegra_board_pinmux_conf conf = {
-        .maps = trimslice_map,
-        .map_count = ARRAY_SIZE(trimslice_map),
-};
-void trimslice_pinmux_init(void)
-{
-        tegra_board_pinmux_init(&conf, NULL);
-}
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
deleted file mode 100644
index 776aa9564d5d..000000000000
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice.c
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- * Author: Mike Rapoport <mike@compulab.co.il>
- *
- * Based on board-harmony.c
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/platform_data/tegra_usb.h>
-#include <asm/hardware/gic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/setup.h>
-#include <mach/iomap.h>
-#include <mach/sdhci.h>
-#include "board.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-#include "board-trimslice.h"
-static struct plat_serial8250_port debug_uart_platform_data[] = {
-        {
-                .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
-                .mapbase        = TEGRA_UARTA_BASE,
-                .irq            = INT_UARTA,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-                .type           = PORT_TEGRA,
-                .handle_break   = tegra_serial_handle_break,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 216000000,
-        }, {
-                .flags          = 0
-        }
-};
-static struct platform_device debug_uart = {
-        .name   = "serial8250",
-        .id     = PLAT8250_DEV_PLATFORM,
-        .dev    = {
-                .platform_data  = debug_uart_platform_data,
-        },
-};
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
-        .cd_gpio        = -1,
-        .wp_gpio        = -1,
-        .power_gpio     = -1,
-};
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
-        .cd_gpio        = TRIMSLICE_GPIO_SD4_CD,
-        .wp_gpio        = TRIMSLICE_GPIO_SD4_WP,
-        .power_gpio     = -1,
-};
-static struct platform_device trimslice_audio_device = {
-        .name   = "tegra-snd-trimslice",
-        .id     = 0,
-};
-static struct platform_device *trimslice_devices[] __initdata = {
-        &debug_uart,
-        &tegra_sdhci_device1,
-        &tegra_sdhci_device4,
-        &tegra_i2s_device1,
-        &tegra_das_device,
-        &trimslice_audio_device,
-};
-static struct i2c_board_info trimslice_i2c3_board_info[] = {
-        {
-                I2C_BOARD_INFO("tlv320aic23", 0x1a),
-        },
-        {
-                I2C_BOARD_INFO("em3027", 0x56),
-        },
-};
-static void trimslice_i2c_init(void)
-{
-        platform_device_register(&tegra_i2c_device1);
-        platform_device_register(&tegra_i2c_device2);
-        platform_device_register(&tegra_i2c_device3);
-        i2c_register_board_info(2, trimslice_i2c3_board_info,
-                                ARRAY_SIZE(trimslice_i2c3_board_info));
-}
-static void trimslice_usb_init(void)
-{
-        struct tegra_ehci_platform_data *pdata;
-        pdata = tegra_ehci1_device.dev.platform_data;
-        pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
-        tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_GPIO_PV0;
-        platform_device_register(&tegra_ehci3_device);
-        platform_device_register(&tegra_ehci2_device);
-        platform_device_register(&tegra_ehci1_device);
-}
-static void __init tegra_trimslice_fixup(struct tag *tags, char **cmdline,
-        struct meminfo *mi)
-{
-        mi->nr_banks = 2;
-        mi->bank[0].start = PHYS_OFFSET;
-        mi->bank[0].size = 448 * SZ_1M;
-        mi->bank[1].start = SZ_512M;
-        mi->bank[1].size = SZ_512M;
-}
-static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "uarta",      "pll_p",        216000000,      true },
-        { "pll_a",      "pll_p_out1",   56448000,       true },
-        { "pll_a_out0", "pll_a",        11289600,       true },
-        { "cdev1",      NULL,           0,              true },
-        { "i2s1",       "pll_a_out0",   11289600,       false},
-        { NULL,         NULL,           0,              0},
-};
-static int __init tegra_trimslice_pci_init(void)
-{
-        if (!machine_is_trimslice())
-                return 0;
-        return tegra_pcie_init(true, true);
-}
-subsys_initcall(tegra_trimslice_pci_init);
-static void __init tegra_trimslice_init(void)
-{
-        tegra_clk_init_from_table(trimslice_clk_init_table);
-        trimslice_pinmux_init();
-        tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
-        tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-        platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices));
-        trimslice_i2c_init();
-        trimslice_usb_init();
-}
-MACHINE_START(TRIMSLICE, "trimslice")
-        .atag_offset    = 0x100,
-        .fixup          = tegra_trimslice_fixup,
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra20_init_early,
-        .init_irq       = tegra_init_irq,
-        .handle_irq     = gic_handle_irq,
-        .timer          = &tegra_timer,
-        .init_machine   = tegra_trimslice_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-trimslice.h b/arch/arm/mach-tegra/board-trimslice.h
deleted file mode 100644
index 50f128d87779..000000000000
--- a/arch/arm/mach-tegra/board-trimslice.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice.h
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef _MACH_TEGRA_BOARD_TRIMSLICE_H
-#define _MACH_TEGRA_BOARD_TRIMSLICE_H
-#include <mach/gpio-tegra.h>
-#define TRIMSLICE_GPIO_SD4_CD   TEGRA_GPIO_PP1  /* mmc4 cd */
-#define TRIMSLICE_GPIO_SD4_WP   TEGRA_GPIO_PP2  /* mmc4 wp */
-#define TRIMSLICE_GPIO_USB1_MODE        TEGRA_GPIO_PV2 /* USB1 mode */
-#define TRIMSLICE_GPIO_USB2_RST         TEGRA_GPIO_PV0 /* USB2 PHY reset */
-void trimslice_pinmux_init(void);
-#endif
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 58f981c0819c..fd82085eca5d 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -1,6 +1,7 @@
 /*
 *
 * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
 *
 * Author:
 *      Colin Cross <ccross@google.com>
@@ -19,8 +20,6 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/module.h>
@@ -32,325 +31,75 @@
 #include "board.h"
 #include "clock.h"
+#include "tegra_cpu_car.h"
+/* Global data of Tegra CPU CAR ops */
+struct tegra_cpu_car_ops *tegra_cpu_car_ops;
 /*
 * Locking:
 *
- * Each struct clk has a spinlock.
- *
- * To avoid AB-BA locking problems, locks must always be traversed from child
- * clock to parent clock.  For example, when enabling a clock, the clock's lock
- * is taken, and then clk_enable is called on the parent, which take's the
- * parent clock's lock.  There is one exceptions to this ordering: When dumping
- * the clock tree through debugfs.  In this case, clk_lock_all is called,
- * which attemps to iterate through the entire list of clocks and take every
- * clock lock.  If any call to spin_trylock fails, all locked clocks are
- * unlocked, and the process is retried.  When all the locks are held,
- * the only clock operation that can be called is clk_get_rate_all_locked.
- *
- * Within a single clock, no clock operation can call another clock operation
- * on itself, except for clk_get_rate_locked and clk_set_rate_locked.  Any
- * clock operation can call any other clock operation on any of it's possible
- * parents.
- *
 * An additional mutex, clock_list_lock, is used to protect the list of all
 * clocks.
 *
- * The clock operations must lock internally to protect against
- * read-modify-write on registers that are shared by multiple clocks
 */
 static DEFINE_MUTEX(clock_list_lock);
 static LIST_HEAD(clocks);
-struct clk *tegra_get_clock_by_name(const char *name)
+void tegra_clk_add(struct clk *clk)
-{
-        struct clk *c;
-        struct clk *ret = NULL;
-        mutex_lock(&clock_list_lock);
-        list_for_each_entry(c, &clocks, node) {
-                if (strcmp(c->name, name) == 0) {
-                        ret = c;
-                        break;
-                }
-        }
-        mutex_unlock(&clock_list_lock);
-        return ret;
-}
-/* Must be called with c->spinlock held */
-static unsigned long clk_predict_rate_from_parent(struct clk *c, struct clk *p)
-{
-        u64 rate;
-        rate = clk_get_rate(p);
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-        return rate;
-}
-/* Must be called with c->spinlock held */
-unsigned long clk_get_rate_locked(struct clk *c)
-{
-        unsigned long rate;
-        if (c->parent)
-                rate = clk_predict_rate_from_parent(c, c->parent);
-        else
-                rate = c->rate;
-        return rate;
-}
-unsigned long clk_get_rate(struct clk *c)
 {
-        unsigned long flags;
+        struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
-        unsigned long rate;
-        spin_lock_irqsave(&c->spinlock, flags);
-        rate = clk_get_rate_locked(c);
-        spin_unlock_irqrestore(&c->spinlock, flags);
-        return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-int clk_reparent(struct clk *c, struct clk *parent)
-{
-        c->parent = parent;
-        return 0;
-}
-void clk_init(struct clk *c)
-{
-        spin_lock_init(&c->spinlock);
-        if (c->ops && c->ops->init)
-                c->ops->init(c);
-        if (!c->ops || !c->ops->enable) {
-                c->refcnt++;
-                c->set = true;
-                if (c->parent)
-                        c->state = c->parent->state;
-                else
-                        c->state = ON;
-        }
        mutex_lock(&clock_list_lock);
        list_add(&c->node, &clocks);
        mutex_unlock(&clock_list_lock);
 }
-int clk_enable(struct clk *c)
+struct clk *tegra_get_clock_by_name(const char *name)
-{
-        int ret = 0;
-        unsigned long flags;
-        spin_lock_irqsave(&c->spinlock, flags);
-        if (c->refcnt == 0) {
-                if (c->parent) {
-                        ret = clk_enable(c->parent);
-                        if (ret)
-                                goto out;
-                }
-                if (c->ops && c->ops->enable) {
-                        ret = c->ops->enable(c);
-                        if (ret) {
-                                if (c->parent)
-                                        clk_disable(c->parent);
-                                goto out;
-                        }
-                        c->state = ON;
-                        c->set = true;
-                }
-        }
-        c->refcnt++;
-out:
-        spin_unlock_irqrestore(&c->spinlock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-void clk_disable(struct clk *c)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&c->spinlock, flags);
-        if (c->refcnt == 0) {
-                WARN(1, "Attempting to disable clock %s with refcnt 0", c->name);
-                spin_unlock_irqrestore(&c->spinlock, flags);
-                return;
-        }
-        if (c->refcnt == 1) {
-                if (c->ops && c->ops->disable)
-                        c->ops->disable(c);
-                if (c->parent)
-                        clk_disable(c->parent);
-                c->state = OFF;
-        }
-        c->refcnt--;
-        spin_unlock_irqrestore(&c->spinlock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-int clk_set_parent(struct clk *c, struct clk *parent)
-{
-        int ret;
-        unsigned long flags;
-        unsigned long new_rate;
-        unsigned long old_rate;
-        spin_lock_irqsave(&c->spinlock, flags);
-        if (!c->ops || !c->ops->set_parent) {
-                ret = -ENOSYS;
-                goto out;
-        }
-        new_rate = clk_predict_rate_from_parent(c, parent);
-        old_rate = clk_get_rate_locked(c);
-        ret = c->ops->set_parent(c, parent);
-        if (ret)
-                goto out;
-out:
-        spin_unlock_irqrestore(&c->spinlock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-struct clk *clk_get_parent(struct clk *c)
-{
-        return c->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-int clk_set_rate_locked(struct clk *c, unsigned long rate)
-{
-        long new_rate;
-        if (!c->ops || !c->ops->set_rate)
-                return -ENOSYS;
-        if (rate > c->max_rate)
-                rate = c->max_rate;
-        if (c->ops && c->ops->round_rate) {
-                new_rate = c->ops->round_rate(c, rate);
-                if (new_rate < 0)
-                        return new_rate;
-                rate = new_rate;
-        }
-        return c->ops->set_rate(c, rate);
-}
-int clk_set_rate(struct clk *c, unsigned long rate)
-{
-        int ret;
-        unsigned long flags;
-        spin_lock_irqsave(&c->spinlock, flags);
-        ret = clk_set_rate_locked(c, rate);
-        spin_unlock_irqrestore(&c->spinlock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-/* Must be called with clocks lock and all indvidual clock locks held */
-unsigned long clk_get_rate_all_locked(struct clk *c)
 {
-        u64 rate;
+        struct clk_tegra *c;
-        int mul = 1;
+        struct clk *ret = NULL;
-        int div = 1;
+        mutex_lock(&clock_list_lock);
-        struct clk *p = c;
+        list_for_each_entry(c, &clocks, node) {
+                if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
-        while (p) {
+                        ret = c->hw.clk;
-                c = p;
+                        break;
-                if (c->mul != 0 && c->div != 0) {
-                        mul *= c->mul;
-                        div *= c->div;
                }
-                p = c->parent;
-        }
-        rate = c->rate;
-        rate *= mul;
-        do_div(rate, div);
-        return rate;
-}
-long clk_round_rate(struct clk *c, unsigned long rate)
-{
-        unsigned long flags;
-        long ret;
-        spin_lock_irqsave(&c->spinlock, flags);
-        if (!c->ops || !c->ops->round_rate) {
-                ret = -ENOSYS;
-                goto out;
        }
+        mutex_unlock(&clock_list_lock);
-        if (rate > c->max_rate)
-                rate = c->max_rate;
-        ret = c->ops->round_rate(c, rate);
-out:
-        spin_unlock_irqrestore(&c->spinlock, flags);
        return ret;
 }
-EXPORT_SYMBOL(clk_round_rate);
 static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
 {
        struct clk *c;
        struct clk *p;
+        struct clk *parent;
        int ret = 0;
        c = tegra_get_clock_by_name(table->name);
        if (!c) {
-                pr_warning("Unable to initialize clock %s\n",
+                pr_warn("Unable to initialize clock %s\n",
                        table->name);
                return -ENODEV;
        }
+        parent = clk_get_parent(c);
        if (table->parent) {
                p = tegra_get_clock_by_name(table->parent);
                if (!p) {
-                        pr_warning("Unable to find parent %s of clock %s\n",
+                        pr_warn("Unable to find parent %s of clock %s\n",
                                table->parent, table->name);
                        return -ENODEV;
                }
-                if (c->parent != p) {
+                if (parent != p) {
                        ret = clk_set_parent(c, p);
                        if (ret) {
-                                pr_warning("Unable to set parent %s of clock %s: %d\n",
+                                pr_warn("Unable to set parent %s of clock %s: %d\n",
                                        table->parent, table->name, ret);
                                return -EINVAL;
                        }
@@ -360,16 +109,16 @@ static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
        if (table->rate && table->rate != clk_get_rate(c)) {
                ret = clk_set_rate(c, table->rate);
                if (ret) {
-                        pr_warning("Unable to set clock %s to rate %lu: %d\n",
+                        pr_warn("Unable to set clock %s to rate %lu: %d\n",
                                table->name, table->rate, ret);
                        return -EINVAL;
                }
        }
        if (table->enabled) {
-                ret = clk_enable(c);
+                ret = clk_prepare_enable(c);
                if (ret) {
-                        pr_warning("Unable to enable clock %s: %d\n",
+                        pr_warn("Unable to enable clock %s: %d\n",
                                table->name, ret);
                        return -EINVAL;
                }
@@ -383,19 +132,20 @@ void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
        for (; table->name; table++)
                tegra_clk_init_one_from_table(table);
 }
-EXPORT_SYMBOL(tegra_clk_init_from_table);
 void tegra_periph_reset_deassert(struct clk *c)
 {
-        BUG_ON(!c->ops->reset);
+        struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
-        c->ops->reset(c, false);
+        BUG_ON(!clk->reset);
+        clk->reset(__clk_get_hw(c), false);
 }
 EXPORT_SYMBOL(tegra_periph_reset_deassert);
 void tegra_periph_reset_assert(struct clk *c)
 {
-        BUG_ON(!c->ops->reset);
+        struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
-        c->ops->reset(c, true);
+        BUG_ON(!clk->reset);
+        clk->reset(__clk_get_hw(c), true);
 }
 EXPORT_SYMBOL(tegra_periph_reset_assert);
@@ -405,268 +155,14 @@ EXPORT_SYMBOL(tegra_periph_reset_assert);
 int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 {
        int ret = 0;
-        unsigned long flags;
+        struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
-        spin_lock_irqsave(&c->spinlock, flags);
+        if (!clk->clk_cfg_ex) {
-        if (!c->ops || !c->ops->clk_cfg_ex) {
                ret = -ENOSYS;
                goto out;
        }
-        ret = c->ops->clk_cfg_ex(c, p, setting);
+        ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);
 out:
-        spin_unlock_irqrestore(&c->spinlock, flags);
        return ret;
 }
-#ifdef CONFIG_DEBUG_FS
-static int __clk_lock_all_spinlocks(void)
-{
-        struct clk *c;
-        list_for_each_entry(c, &clocks, node)
-                if (!spin_trylock(&c->spinlock))
-                        goto unlock_spinlocks;
-        return 0;
-unlock_spinlocks:
-        list_for_each_entry_continue_reverse(c, &clocks, node)
-                spin_unlock(&c->spinlock);
-        return -EAGAIN;
-}
-static void __clk_unlock_all_spinlocks(void)
-{
-        struct clk *c;
-        list_for_each_entry_reverse(c, &clocks, node)
-                spin_unlock(&c->spinlock);
-}
-/*
- * This function retries until it can take all locks, and may take
- * an arbitrarily long time to complete.
- * Must be called with irqs enabled, returns with irqs disabled
- * Must be called with clock_list_lock held
- */
-static void clk_lock_all(void)
-{
-        int ret;
-retry:
-        local_irq_disable();
-        ret = __clk_lock_all_spinlocks();
-        if (ret)
-                goto failed_spinlocks;
-        /* All locks taken successfully, return */
-        return;
-failed_spinlocks:
-        local_irq_enable();
-        yield();
-        goto retry;
-}
-/*
- * Unlocks all clocks after a clk_lock_all
- * Must be called with irqs disabled, returns with irqs enabled
- * Must be called with clock_list_lock held
- */
-static void clk_unlock_all(void)
-{
-        __clk_unlock_all_spinlocks();
-        local_irq_enable();
-}
-static struct dentry *clk_debugfs_root;
-static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
-{
-        struct clk *child;
-        const char *state = "uninit";
-        char div[8] = {0};
-        if (c->state == ON)
-                state = "on";
-        else if (c->state == OFF)
-                state = "off";
-        if (c->mul != 0 && c->div != 0) {
-                if (c->mul > c->div) {
-                        int mul = c->mul / c->div;
-                        int mul2 = (c->mul * 10 / c->div) % 10;
-                        int mul3 = (c->mul * 10) % c->div;
-                        if (mul2 == 0 && mul3 == 0)
-                                snprintf(div, sizeof(div), "x%d", mul);
-                        else if (mul3 == 0)
-                                snprintf(div, sizeof(div), "x%d.%d", mul, mul2);
-                        else
-                                snprintf(div, sizeof(div), "x%d.%d..", mul, mul2);
-                } else {
-                        snprintf(div, sizeof(div), "%d%s", c->div / c->mul,
-                                (c->div % c->mul) ? ".5" : "");
-                }
-        }
-        seq_printf(s, "%*s%c%c%-*s %-6s %-3d %-8s %-10lu\n",
-                level * 3 + 1, "",
-                c->rate > c->max_rate ? '!' : ' ',
-                !c->set ? '*' : ' ',
-                30 - level * 3, c->name,
-                state, c->refcnt, div, clk_get_rate_all_locked(c));
-        list_for_each_entry(child, &clocks, node) {
-                if (child->parent != c)
-                        continue;
-                clock_tree_show_one(s, child, level + 1);
-        }
-}
-static int clock_tree_show(struct seq_file *s, void *data)
-{
-        struct clk *c;
-        seq_printf(s, "   clock                          state  ref div      rate\n");
-        seq_printf(s, "--------------------------------------------------------------\n");
-        mutex_lock(&clock_list_lock);
-        clk_lock_all();
-        list_for_each_entry(c, &clocks, node)
-                if (c->parent == NULL)
-                        clock_tree_show_one(s, c, 0);
-        clk_unlock_all();
-        mutex_unlock(&clock_list_lock);
-        return 0;
-}
-static int clock_tree_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, clock_tree_show, inode->i_private);
-}
-static const struct file_operations clock_tree_fops = {
-        .open           = clock_tree_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-static int possible_parents_show(struct seq_file *s, void *data)
-{
-        struct clk *c = s->private;
-        int i;
-        for (i = 0; c->inputs[i].input; i++) {
-                char *first = (i == 0) ? "" : " ";
-                seq_printf(s, "%s%s", first, c->inputs[i].input->name);
-        }
-        seq_printf(s, "\n");
-        return 0;
-}
-static int possible_parents_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, possible_parents_show, inode->i_private);
-}
-static const struct file_operations possible_parents_fops = {
-        .open           = possible_parents_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-static int clk_debugfs_register_one(struct clk *c)
-{
-        struct dentry *d;
-        d = debugfs_create_dir(c->name, clk_debugfs_root);
-        if (!d)
-                return -ENOMEM;
-        c->dent = d;
-        d = debugfs_create_u8("refcnt", S_IRUGO, c->dent, (u8 *)&c->refcnt);
-        if (!d)
-                goto err_out;
-        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
-        if (!d)
-                goto err_out;
-        d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
-        if (!d)
-                goto err_out;
-        if (c->inputs) {
-                d = debugfs_create_file("possible_parents", S_IRUGO, c->dent,
-                        c, &possible_parents_fops);
-                if (!d)
-                        goto err_out;
-        }
-        return 0;
-err_out:
-        debugfs_remove_recursive(c->dent);
-        return -ENOMEM;
-}
-static int clk_debugfs_register(struct clk *c)
-{
-        int err;
-        struct clk *pa = c->parent;
-        if (pa && !pa->dent) {
-                err = clk_debugfs_register(pa);
-                if (err)
-                        return err;
-        }
-        if (!c->dent) {
-                err = clk_debugfs_register_one(c);
-                if (err)
-                        return err;
-        }
-        return 0;
-}
-int __init tegra_clk_debugfs_init(void)
-{
-        struct clk *c;
-        struct dentry *d;
-        int err = -ENOMEM;
-        d = debugfs_create_dir("clock", NULL);
-        if (!d)
-                return -ENOMEM;
-        clk_debugfs_root = d;
-        d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
-                &clock_tree_fops);
-        if (!d)
-                goto err_out;
-        list_for_each_entry(c, &clocks, node) {
-                err = clk_debugfs_register(c);
-                if (err)
-                        goto err_out;
-        }
-        return 0;
-err_out:
-        debugfs_remove_recursive(clk_debugfs_root);
-        return err;
-}
-#endif
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index bc300657deba..2aa37f5c44c0 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -2,6 +2,7 @@
 * arch/arm/mach-tegra/include/mach/clock.h
 *
 * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
 *
 * Author:
 *      Colin Cross <ccross@google.com>
@@ -20,9 +21,9 @@
 #ifndef __MACH_TEGRA_CLOCK_H
 #define __MACH_TEGRA_CLOCK_H
+#include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/list.h>
-#include <linux/spinlock.h>
 #include <mach/clk.h>
@@ -52,7 +53,8 @@
 #define ENABLE_ON_INIT          (1 << 28)
 #define PERIPH_ON_APB           (1 << 29)
-struct clk;
+struct clk_tegra;
+#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
 struct clk_mux_sel {
        struct clk      *input;
@@ -68,47 +70,29 @@ struct clk_pll_freq_table {
        u8              cpcon;
 };
-struct clk_ops {
-        void            (*init)(struct clk *);
-        int             (*enable)(struct clk *);
-        void            (*disable)(struct clk *);
-        int             (*set_parent)(struct clk *, struct clk *);
-        int             (*set_rate)(struct clk *, unsigned long);
-        long            (*round_rate)(struct clk *, unsigned long);
-        void            (*reset)(struct clk *, bool);
-        int             (*clk_cfg_ex)(struct clk *,
-                                enum tegra_clk_ex_param, u32);
-};
 enum clk_state {
        UNINITIALIZED = 0,
        ON,
        OFF,
 };
-struct clk {
+struct clk_tegra {
        /* node for master clocks list */
-        struct list_head        node;           /* node for list of all clocks */
+        struct list_head        node;   /* node for list of all clocks */
        struct clk_lookup       lookup;
+        struct clk_hw           hw;
-#ifdef CONFIG_DEBUG_FS
-        struct dentry           *dent;
-#endif
        bool                    set;
-        struct clk_ops          *ops;
+        unsigned long           fixed_rate;
-        unsigned long           rate;
        unsigned long           max_rate;
        unsigned long           min_rate;
        u32                     flags;
        const char              *name;
-        u32                     refcnt;
        enum clk_state          state;
-        struct clk              *parent;
        u32                     div;
        u32                     mul;
-        const struct clk_mux_sel        *inputs;
        u32                             reg;
        u32                             reg_shift;
@@ -144,7 +128,8 @@ struct clk {
                } shared_bus_user;
        } u;
-        spinlock_t spinlock;
+        void (*reset)(struct clk_hw *, bool);
+        int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
 };
 struct clk_duplicate {
@@ -159,13 +144,10 @@ struct tegra_clk_init_table {
        bool enabled;
 };
+void tegra_clk_add(struct clk *c);
 void tegra2_init_clocks(void);
 void tegra30_init_clocks(void);
-void clk_init(struct clk *clk);
 struct clk *tegra_get_clock_by_name(const char *name);
-int clk_reparent(struct clk *c, struct clk *parent);
 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
-unsigned long clk_get_rate_locked(struct clk *c);
-int clk_set_rate_locked(struct clk *c, unsigned long rate);
 #endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 96fef6bcc651..0b0a5f556d34 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -31,9 +31,11 @@
 #include "board.h"
 #include "clock.h"
+#include "common.h"
 #include "fuse.h"
 #include "pmc.h"
 #include "apbio.h"
+#include "sleep.h"
 /*
 * Storage for debug-macro.S's state.
@@ -135,6 +137,7 @@ void __init tegra20_init_early(void)
        tegra_init_cache(0x331, 0x441);
        tegra_pmc_init();
        tegra_powergate_init();
+        tegra20_hotplug_init();
 }
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
@@ -147,11 +150,11 @@ void __init tegra30_init_early(void)
        tegra_init_cache(0x441, 0x551);
        tegra_pmc_init();
        tegra_powergate_init();
+        tegra30_hotplug_init();
 }
 #endif
 void __init tegra_init_late(void)
 {
-        tegra_clk_debugfs_init();
        tegra_powergate_debugfs_init();
 }
diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h
new file mode 100644
index 000000000000..02f71b4f1e51
--- /dev/null
+++ b/arch/arm/mach-tegra/common.h
@@ -0,0 +1,4 @@
+extern struct smp_operations tegra_smp_ops;
+extern void tegra_cpu_die(unsigned int cpu);
+extern int tegra_cpu_disable(unsigned int cpu);
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index ceb52db1e2f1..627bf0f4262e 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -49,6 +49,8 @@ static struct cpufreq_frequency_table freq_table[] = {
 #define NUM_CPUS        2
 static struct clk *cpu_clk;
+static struct clk *pll_x_clk;
+static struct clk *pll_p_clk;
 static struct clk *emc_clk;
 static unsigned long target_cpu_speed[NUM_CPUS];
@@ -71,6 +73,42 @@ static unsigned int tegra_getspeed(unsigned int cpu)
        return rate;
 }
+static int tegra_cpu_clk_set_rate(unsigned long rate)
+{
+        int ret;
+        /*
+         * Take an extra reference to the main pll so it doesn't turn
+         * off when we move the cpu off of it
+         */
+        clk_prepare_enable(pll_x_clk);
+        ret = clk_set_parent(cpu_clk, pll_p_clk);
+        if (ret) {
+                pr_err("Failed to switch cpu to clock pll_p\n");
+                goto out;
+        }
+        if (rate == clk_get_rate(pll_p_clk))
+                goto out;
+        ret = clk_set_rate(pll_x_clk, rate);
+        if (ret) {
+                pr_err("Failed to change pll_x to %lu\n", rate);
+                goto out;
+        }
+        ret = clk_set_parent(cpu_clk, pll_x_clk);
+        if (ret) {
+                pr_err("Failed to switch cpu to clock pll_x\n");
+                goto out;
+        }
+out:
+        clk_disable_unprepare(pll_x_clk);
+        return ret;
+}
 static int tegra_update_cpu_speed(unsigned long rate)
 {
        int ret = 0;
@@ -101,7 +139,7 @@ static int tegra_update_cpu_speed(unsigned long rate)
               freqs.old, freqs.new);
 #endif
-        ret = clk_set_rate(cpu_clk, freqs.new * 1000);
+        ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
        if (ret) {
                pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
                        freqs.new);
@@ -183,6 +221,14 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
        if (IS_ERR(cpu_clk))
                return PTR_ERR(cpu_clk);
+        pll_x_clk = clk_get_sys(NULL, "pll_x");
+        if (IS_ERR(pll_x_clk))
+                return PTR_ERR(pll_x_clk);
+        pll_p_clk = clk_get_sys(NULL, "pll_p");
+        if (IS_ERR(pll_p_clk))
+                return PTR_ERR(pll_p_clk);
        emc_clk = clk_get_sys("cpu", "emc");
        if (IS_ERR(emc_clk)) {
                clk_put(cpu_clk);
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
deleted file mode 100644
index c70e65ffa36b..000000000000
--- a/arch/arm/mach-tegra/devices.c
+++ /dev/null
@@ -1,702 +0,0 @@
-/*
- * Copyright (C) 2010,2011 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@android.com>
- *      Erik Gilling <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/resource.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/fsl_devices.h>
-#include <linux/serial_8250.h>
-#include <linux/i2c-tegra.h>
-#include <asm/pmu.h>
-#include <mach/irqs.h>
-#include <mach/iomap.h>
-#include <mach/dma.h>
-#include <mach/usb_phy.h>
-#include "gpio-names.h"
-#include "devices.h"
-static struct resource gpio_resource[] = {
-        [0] = {
-                .start  = TEGRA_GPIO_BASE,
-                .end    = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_GPIO1,
-                .end    = INT_GPIO1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = INT_GPIO2,
-                .end    = INT_GPIO2,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = INT_GPIO3,
-                .end    = INT_GPIO3,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [4] = {
-                .start  = INT_GPIO4,
-                .end    = INT_GPIO4,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [5] = {
-                .start  = INT_GPIO5,
-                .end    = INT_GPIO5,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [6] = {
-                .start  = INT_GPIO6,
-                .end    = INT_GPIO6,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [7] = {
-                .start  = INT_GPIO7,
-                .end    = INT_GPIO7,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device tegra_gpio_device = {
-        .name           = "tegra-gpio",
-        .id             = -1,
-        .resource       = gpio_resource,
-        .num_resources  = ARRAY_SIZE(gpio_resource),
-};
-static struct resource pinmux_resource[] = {
-        [0] = {
-                /* Tri-state registers */
-                .start  = TEGRA_APB_MISC_BASE + 0x14,
-                .end    = TEGRA_APB_MISC_BASE + 0x20 + 3,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                /* Mux registers */
-                .start  = TEGRA_APB_MISC_BASE + 0x80,
-                .end    = TEGRA_APB_MISC_BASE + 0x9c + 3,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                /* Pull-up/down registers */
-                .start  = TEGRA_APB_MISC_BASE + 0xa0,
-                .end    = TEGRA_APB_MISC_BASE + 0xb0 + 3,
-                .flags  = IORESOURCE_MEM,
-        },
-        [3] = {
-                /* Pad control registers */
-                .start  = TEGRA_APB_MISC_BASE + 0x868,
-                .end    = TEGRA_APB_MISC_BASE + 0x90c + 3,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-struct platform_device tegra_pinmux_device = {
-        .name           = "tegra20-pinctrl",
-        .id             = -1,
-        .resource       = pinmux_resource,
-        .num_resources  = ARRAY_SIZE(pinmux_resource),
-};
-static struct resource i2c_resource1[] = {
-        [0] = {
-                .start  = INT_I2C,
-                .end    = INT_I2C,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_I2C_BASE,
-                .end    = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct resource i2c_resource2[] = {
-        [0] = {
-                .start  = INT_I2C2,
-                .end    = INT_I2C2,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_I2C2_BASE,
-                .end    = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct resource i2c_resource3[] = {
-        [0] = {
-                .start  = INT_I2C3,
-                .end    = INT_I2C3,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_I2C3_BASE,
-                .end    = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct resource i2c_resource4[] = {
-        [0] = {
-                .start  = INT_DVC,
-                .end    = INT_DVC,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_DVC_BASE,
-                .end    = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-struct platform_device tegra_i2c_device1 = {
-        .name           = "tegra-i2c",
-        .id             = 0,
-        .resource       = i2c_resource1,
-        .num_resources  = ARRAY_SIZE(i2c_resource1),
-        .dev = {
-                .platform_data = &tegra_i2c1_platform_data,
-        },
-};
-struct platform_device tegra_i2c_device2 = {
-        .name           = "tegra-i2c",
-        .id             = 1,
-        .resource       = i2c_resource2,
-        .num_resources  = ARRAY_SIZE(i2c_resource2),
-        .dev = {
-                .platform_data = &tegra_i2c2_platform_data,
-        },
-};
-struct platform_device tegra_i2c_device3 = {
-        .name           = "tegra-i2c",
-        .id             = 2,
-        .resource       = i2c_resource3,
-        .num_resources  = ARRAY_SIZE(i2c_resource3),
-        .dev = {
-                .platform_data = &tegra_i2c3_platform_data,
-        },
-};
-struct platform_device tegra_i2c_device4 = {
-        .name           = "tegra-i2c",
-        .id             = 3,
-        .resource       = i2c_resource4,
-        .num_resources  = ARRAY_SIZE(i2c_resource4),
-        .dev = {
-                .platform_data = &tegra_dvc_platform_data,
-        },
-};
-static struct resource spi_resource1[] = {
-        [0] = {
-                .start  = INT_S_LINK1,
-                .end    = INT_S_LINK1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SPI1_BASE,
-                .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct resource spi_resource2[] = {
-        [0] = {
-                .start  = INT_SPI_2,
-                .end    = INT_SPI_2,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SPI2_BASE,
-                .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct resource spi_resource3[] = {
-        [0] = {
-                .start  = INT_SPI_3,
-                .end    = INT_SPI_3,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SPI3_BASE,
-                .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct resource spi_resource4[] = {
-        [0] = {
-                .start  = INT_SPI_4,
-                .end    = INT_SPI_4,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SPI4_BASE,
-                .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-struct platform_device tegra_spi_device1 = {
-        .name           = "spi_tegra",
-        .id             = 0,
-        .resource       = spi_resource1,
-        .num_resources  = ARRAY_SIZE(spi_resource1),
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-struct platform_device tegra_spi_device2 = {
-        .name           = "spi_tegra",
-        .id             = 1,
-        .resource       = spi_resource2,
-        .num_resources  = ARRAY_SIZE(spi_resource2),
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-struct platform_device tegra_spi_device3 = {
-        .name           = "spi_tegra",
-        .id             = 2,
-        .resource       = spi_resource3,
-        .num_resources  = ARRAY_SIZE(spi_resource3),
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-struct platform_device tegra_spi_device4 = {
-        .name           = "spi_tegra",
-        .id             = 3,
-        .resource       = spi_resource4,
-        .num_resources  = ARRAY_SIZE(spi_resource4),
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-static struct resource sdhci_resource1[] = {
-        [0] = {
-                .start  = INT_SDMMC1,
-                .end    = INT_SDMMC1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SDMMC1_BASE,
-                .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct resource sdhci_resource2[] = {
-        [0] = {
-                .start  = INT_SDMMC2,
-                .end    = INT_SDMMC2,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SDMMC2_BASE,
-                .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct resource sdhci_resource3[] = {
-        [0] = {
-                .start  = INT_SDMMC3,
-                .end    = INT_SDMMC3,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SDMMC3_BASE,
-                .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct resource sdhci_resource4[] = {
-        [0] = {
-                .start  = INT_SDMMC4,
-                .end    = INT_SDMMC4,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SDMMC4_BASE,
-                .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-/* board files should fill in platform_data register the devices themselvs.
- * See board-harmony.c for an example
- */
-struct platform_device tegra_sdhci_device1 = {
-        .name           = "sdhci-tegra",
-        .id             = 0,
-        .resource       = sdhci_resource1,
-        .num_resources  = ARRAY_SIZE(sdhci_resource1),
-};
-struct platform_device tegra_sdhci_device2 = {
-        .name           = "sdhci-tegra",
-        .id             = 1,
-        .resource       = sdhci_resource2,
-        .num_resources  = ARRAY_SIZE(sdhci_resource2),
-};
-struct platform_device tegra_sdhci_device3 = {
-        .name           = "sdhci-tegra",
-        .id             = 2,
-        .resource       = sdhci_resource3,
-        .num_resources  = ARRAY_SIZE(sdhci_resource3),
-};
-struct platform_device tegra_sdhci_device4 = {
-        .name           = "sdhci-tegra",
-        .id             = 3,
-        .resource       = sdhci_resource4,
-        .num_resources  = ARRAY_SIZE(sdhci_resource4),
-};
-static struct resource tegra_usb1_resources[] = {
-        [0] = {
-                .start  = TEGRA_USB_BASE,
-                .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_USB,
-                .end    = INT_USB,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct resource tegra_usb2_resources[] = {
-        [0] = {
-                .start  = TEGRA_USB2_BASE,
-                .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_USB2,
-                .end    = INT_USB2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct resource tegra_usb3_resources[] = {
-        [0] = {
-                .start  = TEGRA_USB3_BASE,
-                .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_USB3,
-                .end    = INT_USB3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
-        .reset_gpio = -1,
-        .clk = "cdev2",
-};
-struct tegra_ehci_platform_data tegra_ehci1_pdata = {
-        .operating_mode = TEGRA_USB_OTG,
-        .power_down_on_bus_suspend = 1,
-        .vbus_gpio = -1,
-};
-struct tegra_ehci_platform_data tegra_ehci2_pdata = {
-        .phy_config = &tegra_ehci2_ulpi_phy_config,
-        .operating_mode = TEGRA_USB_HOST,
-        .power_down_on_bus_suspend = 1,
-        .vbus_gpio = -1,
-};
-struct tegra_ehci_platform_data tegra_ehci3_pdata = {
-        .operating_mode = TEGRA_USB_HOST,
-        .power_down_on_bus_suspend = 1,
-        .vbus_gpio = -1,
-};
-static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
-struct platform_device tegra_ehci1_device = {
-        .name   = "tegra-ehci",
-        .id     = 0,
-        .dev    = {
-                .dma_mask       = &tegra_ehci_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &tegra_ehci1_pdata,
-        },
-        .resource = tegra_usb1_resources,
-        .num_resources = ARRAY_SIZE(tegra_usb1_resources),
-};
-struct platform_device tegra_ehci2_device = {
-        .name   = "tegra-ehci",
-        .id     = 1,
-        .dev    = {
-                .dma_mask       = &tegra_ehci_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &tegra_ehci2_pdata,
-        },
-        .resource = tegra_usb2_resources,
-        .num_resources = ARRAY_SIZE(tegra_usb2_resources),
-};
-struct platform_device tegra_ehci3_device = {
-        .name   = "tegra-ehci",
-        .id     = 2,
-        .dev    = {
-                .dma_mask       = &tegra_ehci_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &tegra_ehci3_pdata,
-        },
-        .resource = tegra_usb3_resources,
-        .num_resources = ARRAY_SIZE(tegra_usb3_resources),
-};
-static struct resource tegra_pmu_resources[] = {
-        [0] = {
-                .start  = INT_CPU0_PMU_INTR,
-                .end    = INT_CPU0_PMU_INTR,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = INT_CPU1_PMU_INTR,
-                .end    = INT_CPU1_PMU_INTR,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device tegra_pmu_device = {
-        .name           = "arm-pmu",
-        .id             = ARM_PMU_DEVICE_CPU,
-        .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
-        .resource       = tegra_pmu_resources,
-};
-static struct resource tegra_uarta_resources[] = {
-        [0] = {
-                .start  = TEGRA_UARTA_BASE,
-                .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_UARTA,
-                .end    = INT_UARTA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct resource tegra_uartb_resources[] = {
-        [0] = {
-                .start  = TEGRA_UARTB_BASE,
-                .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_UARTB,
-                .end    = INT_UARTB,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct resource tegra_uartc_resources[] = {
-        [0] = {
-                .start  = TEGRA_UARTC_BASE,
-                .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_UARTC,
-                .end    = INT_UARTC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct resource tegra_uartd_resources[] = {
-        [0] = {
-                .start  = TEGRA_UARTD_BASE,
-                .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_UARTD,
-                .end    = INT_UARTD,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct resource tegra_uarte_resources[] = {
-        [0] = {
-                .start  = TEGRA_UARTE_BASE,
-                .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_UARTE,
-                .end    = INT_UARTE,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-struct platform_device tegra_uarta_device = {
-        .name   = "tegra_uart",
-        .id     = 0,
-        .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
-        .resource       = tegra_uarta_resources,
-        .dev    = {
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-struct platform_device tegra_uartb_device = {
-        .name   = "tegra_uart",
-        .id     = 1,
-        .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
-        .resource       = tegra_uartb_resources,
-        .dev    = {
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-struct platform_device tegra_uartc_device = {
-        .name   = "tegra_uart",
-        .id     = 2,
-        .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
-        .resource       = tegra_uartc_resources,
-        .dev    = {
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-struct platform_device tegra_uartd_device = {
-        .name   = "tegra_uart",
-        .id     = 3,
-        .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
-        .resource       = tegra_uartd_resources,
-        .dev    = {
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-struct platform_device tegra_uarte_device = {
-        .name   = "tegra_uart",
-        .id     = 4,
-        .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
-        .resource       = tegra_uarte_resources,
-        .dev    = {
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-static struct resource i2s_resource1[] = {
-        [0] = {
-                .start  = INT_I2S1,
-                .end    = INT_I2S1,
-                .flags  = IORESOURCE_IRQ
-        },
-        [1] = {
-                .start  = TEGRA_DMA_REQ_SEL_I2S_1,
-                .end    = TEGRA_DMA_REQ_SEL_I2S_1,
-                .flags  = IORESOURCE_DMA
-        },
-        [2] = {
-                .start  = TEGRA_I2S1_BASE,
-                .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
-                .flags  = IORESOURCE_MEM
-        }
-};
-static struct resource i2s_resource2[] = {
-        [0] = {
-                .start  = INT_I2S2,
-                .end    = INT_I2S2,
-                .flags  = IORESOURCE_IRQ
-        },
-        [1] = {
-                .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
-                .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
-                .flags  = IORESOURCE_DMA
-        },
-        [2] = {
-                .start  = TEGRA_I2S2_BASE,
-                .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
-                .flags  = IORESOURCE_MEM
-        }
-};
-struct platform_device tegra_i2s_device1 = {
-        .name           = "tegra20-i2s",
-        .id             = 0,
-        .resource       = i2s_resource1,
-        .num_resources  = ARRAY_SIZE(i2s_resource1),
-};
-struct platform_device tegra_i2s_device2 = {
-        .name           = "tegra20-i2s",
-        .id             = 1,
-        .resource       = i2s_resource2,
-        .num_resources  = ARRAY_SIZE(i2s_resource2),
-};
-static struct resource tegra_das_resources[] = {
-        [0] = {
-                .start = TEGRA_APB_MISC_DAS_BASE,
-                .end = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-struct platform_device tegra_das_device = {
-        .name           = "tegra20-das",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(tegra_das_resources),
-        .resource       = tegra_das_resources,
-};
diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
deleted file mode 100644
index 4f5052726495..000000000000
--- a/arch/arm/mach-tegra/devices.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 2010,2011 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@android.com>
- *      Erik Gilling <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_TEGRA_DEVICES_H
-#define __MACH_TEGRA_DEVICES_H
-#include <linux/platform_device.h>
-#include <linux/platform_data/tegra_usb.h>
-#include <mach/usb_phy.h>
-extern struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config;
-extern struct tegra_ehci_platform_data tegra_ehci1_pdata;
-extern struct tegra_ehci_platform_data tegra_ehci2_pdata;
-extern struct tegra_ehci_platform_data tegra_ehci3_pdata;
-extern struct platform_device tegra_gpio_device;
-extern struct platform_device tegra_pinmux_device;
-extern struct platform_device tegra_sdhci_device1;
-extern struct platform_device tegra_sdhci_device2;
-extern struct platform_device tegra_sdhci_device3;
-extern struct platform_device tegra_sdhci_device4;
-extern struct platform_device tegra_i2c_device1;
-extern struct platform_device tegra_i2c_device2;
-extern struct platform_device tegra_i2c_device3;
-extern struct platform_device tegra_i2c_device4;
-extern struct platform_device tegra_spi_device1;
-extern struct platform_device tegra_spi_device2;
-extern struct platform_device tegra_spi_device3;
-extern struct platform_device tegra_spi_device4;
-extern struct platform_device tegra_ehci1_device;
-extern struct platform_device tegra_ehci2_device;
-extern struct platform_device tegra_ehci3_device;
-extern struct platform_device tegra_uarta_device;
-extern struct platform_device tegra_uartb_device;
-extern struct platform_device tegra_uartc_device;
-extern struct platform_device tegra_uartd_device;
-extern struct platform_device tegra_uarte_device;
-extern struct platform_device tegra_pmu_device;
-extern struct platform_device tegra_i2s_device1;
-extern struct platform_device tegra_i2s_device2;
-extern struct platform_device tegra_das_device;
-#endif
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
deleted file mode 100644
index 29c5114d607c..000000000000
--- a/arch/arm/mach-tegra/dma.c
+++ /dev/null
@@ -1,823 +0,0 @@
-/*
- * arch/arm/mach-tegra/dma.c
- *
- * System DMA driver for NVIDIA Tegra SoCs
- *
- * Copyright (c) 2008-2009, NVIDIA Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/err.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <mach/dma.h>
-#include <mach/irqs.h>
-#include <mach/iomap.h>
-#include <mach/suspend.h>
-#include "apbio.h"
-#define APB_DMA_GEN                             0x000
-#define GEN_ENABLE                              (1<<31)
-#define APB_DMA_CNTRL                           0x010
-#define APB_DMA_IRQ_MASK                        0x01c
-#define APB_DMA_IRQ_MASK_SET                    0x020
-#define APB_DMA_CHAN_CSR                        0x000
-#define CSR_ENB                                 (1<<31)
-#define CSR_IE_EOC                              (1<<30)
-#define CSR_HOLD                                (1<<29)
-#define CSR_DIR                                 (1<<28)
-#define CSR_ONCE                                (1<<27)
-#define CSR_FLOW                                (1<<21)
-#define CSR_REQ_SEL_SHIFT                       16
-#define CSR_WCOUNT_SHIFT                        2
-#define CSR_WCOUNT_MASK                         0xFFFC
-#define APB_DMA_CHAN_STA                                0x004
-#define STA_BUSY                                (1<<31)
-#define STA_ISE_EOC                             (1<<30)
-#define STA_HALT                                (1<<29)
-#define STA_PING_PONG                           (1<<28)
-#define STA_COUNT_SHIFT                         2
-#define STA_COUNT_MASK                          0xFFFC
-#define APB_DMA_CHAN_AHB_PTR                            0x010
-#define APB_DMA_CHAN_AHB_SEQ                            0x014
-#define AHB_SEQ_INTR_ENB                        (1<<31)
-#define AHB_SEQ_BUS_WIDTH_SHIFT                 28
-#define AHB_SEQ_BUS_WIDTH_MASK                  (0x7<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_8                     (0<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_16                    (1<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_32                    (2<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_64                    (3<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_128                   (4<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_DATA_SWAP                       (1<<27)
-#define AHB_SEQ_BURST_MASK                      (0x7<<24)
-#define AHB_SEQ_BURST_1                         (4<<24)
-#define AHB_SEQ_BURST_4                         (5<<24)
-#define AHB_SEQ_BURST_8                         (6<<24)
-#define AHB_SEQ_DBL_BUF                         (1<<19)
-#define AHB_SEQ_WRAP_SHIFT                      16
-#define AHB_SEQ_WRAP_MASK                       (0x7<<AHB_SEQ_WRAP_SHIFT)
-#define APB_DMA_CHAN_APB_PTR                            0x018
-#define APB_DMA_CHAN_APB_SEQ                            0x01c
-#define APB_SEQ_BUS_WIDTH_SHIFT                 28
-#define APB_SEQ_BUS_WIDTH_MASK                  (0x7<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_8                     (0<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_16                    (1<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_32                    (2<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_64                    (3<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_128                   (4<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_DATA_SWAP                       (1<<27)
-#define APB_SEQ_WRAP_SHIFT                      16
-#define APB_SEQ_WRAP_MASK                       (0x7<<APB_SEQ_WRAP_SHIFT)
-#define TEGRA_SYSTEM_DMA_CH_NR                  16
-#define TEGRA_SYSTEM_DMA_AVP_CH_NUM             4
-#define TEGRA_SYSTEM_DMA_CH_MIN                 0
-#define TEGRA_SYSTEM_DMA_CH_MAX \
-        (TEGRA_SYSTEM_DMA_CH_NR - TEGRA_SYSTEM_DMA_AVP_CH_NUM - 1)
-#define NV_DMA_MAX_TRASFER_SIZE 0x10000
-static const unsigned int ahb_addr_wrap_table[8] = {
-        0, 32, 64, 128, 256, 512, 1024, 2048
-};
-static const unsigned int apb_addr_wrap_table[8] = {
-        0, 1, 2, 4, 8, 16, 32, 64
-};
-static const unsigned int bus_width_table[5] = {
-        8, 16, 32, 64, 128
-};
-#define TEGRA_DMA_NAME_SIZE 16
-struct tegra_dma_channel {
-        struct list_head        list;
-        int                     id;
-        spinlock_t              lock;
-        char                    name[TEGRA_DMA_NAME_SIZE];
-        void  __iomem           *addr;
-        int                     mode;
-        int                     irq;
-        int                     req_transfer_count;
-};
-#define  NV_DMA_MAX_CHANNELS  32
-static bool tegra_dma_initialized;
-static DEFINE_MUTEX(tegra_dma_lock);
-static DEFINE_SPINLOCK(enable_lock);
-static DECLARE_BITMAP(channel_usage, NV_DMA_MAX_CHANNELS);
-static struct tegra_dma_channel dma_channels[NV_DMA_MAX_CHANNELS];
-static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-static void tegra_dma_stop(struct tegra_dma_channel *ch);
-void tegra_dma_flush(struct tegra_dma_channel *ch)
-{
-}
-EXPORT_SYMBOL(tegra_dma_flush);
-void tegra_dma_dequeue(struct tegra_dma_channel *ch)
-{
-        struct tegra_dma_req *req;
-        if (tegra_dma_is_empty(ch))
-                return;
-        req = list_entry(ch->list.next, typeof(*req), node);
-        tegra_dma_dequeue_req(ch, req);
-        return;
-}
-static void tegra_dma_stop(struct tegra_dma_channel *ch)
-{
-        u32 csr;
-        u32 status;
-        csr = readl(ch->addr + APB_DMA_CHAN_CSR);
-        csr &= ~CSR_IE_EOC;
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-        csr &= ~CSR_ENB;
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-        status = readl(ch->addr + APB_DMA_CHAN_STA);
-        if (status & STA_ISE_EOC)
-                writel(status, ch->addr + APB_DMA_CHAN_STA);
-}
-static int tegra_dma_cancel(struct tegra_dma_channel *ch)
-{
-        unsigned long irq_flags;
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        while (!list_empty(&ch->list))
-                list_del(ch->list.next);
-        tegra_dma_stop(ch);
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-        return 0;
-}
-static unsigned int get_channel_status(struct tegra_dma_channel *ch,
-                        struct tegra_dma_req *req, bool is_stop_dma)
-{
-        void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-        unsigned int status;
-        if (is_stop_dma) {
-                /*
-                 * STOP the DMA and get the transfer count.
-                 * Getting the transfer count is tricky.
-                 *  - Globally disable DMA on all channels
-                 *  - Read the channel's status register to know the number
-                 *    of pending bytes to be transfered.
-                 *  - Stop the dma channel
-                 *  - Globally re-enable DMA to resume other transfers
-                 */
-                spin_lock(&enable_lock);
-                writel(0, addr + APB_DMA_GEN);
-                udelay(20);
-                status = readl(ch->addr + APB_DMA_CHAN_STA);
-                tegra_dma_stop(ch);
-                writel(GEN_ENABLE, addr + APB_DMA_GEN);
-                spin_unlock(&enable_lock);
-                if (status & STA_ISE_EOC) {
-                        pr_err("Got Dma Int here clearing");
-                        writel(status, ch->addr + APB_DMA_CHAN_STA);
-                }
-                req->status = TEGRA_DMA_REQ_ERROR_ABORTED;
-        } else {
-                status = readl(ch->addr + APB_DMA_CHAN_STA);
-        }
-        return status;
-}
-/* should be called with the channel lock held */
-static unsigned int dma_active_count(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req, unsigned int status)
-{
-        unsigned int to_transfer;
-        unsigned int req_transfer_count;
-        unsigned int bytes_transferred;
-        to_transfer = ((status & STA_COUNT_MASK) >> STA_COUNT_SHIFT) + 1;
-        req_transfer_count = ch->req_transfer_count + 1;
-        bytes_transferred = req_transfer_count;
-        if (status & STA_BUSY)
-                bytes_transferred -= to_transfer;
-        /*
-         * In continuous transfer mode, DMA only tracks the count of the
-         * half DMA buffer. So, if the DMA already finished half the DMA
-         * then add the half buffer to the completed count.
-         */
-        if (ch->mode & TEGRA_DMA_MODE_CONTINOUS) {
-                if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL)
-                        bytes_transferred += req_transfer_count;
-                if (status & STA_ISE_EOC)
-                        bytes_transferred += req_transfer_count;
-        }
-        bytes_transferred *= 4;
-        return bytes_transferred;
-}
-int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *_req)
-{
-        unsigned int status;
-        struct tegra_dma_req *req = NULL;
-        int found = 0;
-        unsigned long irq_flags;
-        int stop = 0;
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        if (list_entry(ch->list.next, struct tegra_dma_req, node) == _req)
-                stop = 1;
-        list_for_each_entry(req, &ch->list, node) {
-                if (req == _req) {
-                        list_del(&req->node);
-                        found = 1;
-                        break;
-                }
-        }
-        if (!found) {
-                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                return 0;
-        }
-        if (!stop)
-                goto skip_stop_dma;
-        status = get_channel_status(ch, req, true);
-        req->bytes_transferred = dma_active_count(ch, req, status);
-        if (!list_empty(&ch->list)) {
-                /* if the list is not empty, queue the next request */
-                struct tegra_dma_req *next_req;
-                next_req = list_entry(ch->list.next,
-                        typeof(*next_req), node);
-                tegra_dma_update_hw(ch, next_req);
-        }
-skip_stop_dma:
-        req->status = -TEGRA_DMA_REQ_ERROR_ABORTED;
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-        /* Callback should be called without any lock */
-        req->complete(req);
-        return 0;
-}
-EXPORT_SYMBOL(tegra_dma_dequeue_req);
-bool tegra_dma_is_empty(struct tegra_dma_channel *ch)
-{
-        unsigned long irq_flags;
-        bool is_empty;
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        if (list_empty(&ch->list))
-                is_empty = true;
-        else
-                is_empty = false;
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-        return is_empty;
-}
-EXPORT_SYMBOL(tegra_dma_is_empty);
-bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *_req)
-{
-        unsigned long irq_flags;
-        struct tegra_dma_req *req;
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        list_for_each_entry(req, &ch->list, node) {
-                if (req == _req) {
-                        spin_unlock_irqrestore(&ch->lock, irq_flags);
-                        return true;
-                }
-        }
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-        return false;
-}
-EXPORT_SYMBOL(tegra_dma_is_req_inflight);
-int tegra_dma_enqueue_req(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req)
-{
-        unsigned long irq_flags;
-        struct tegra_dma_req *_req;
-        int start_dma = 0;
-        if (req->size > NV_DMA_MAX_TRASFER_SIZE ||
-                req->source_addr & 0x3 || req->dest_addr & 0x3) {
-                pr_err("Invalid DMA request for channel %d\n", ch->id);
-                return -EINVAL;
-        }
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        list_for_each_entry(_req, &ch->list, node) {
-                if (req == _req) {
-                    spin_unlock_irqrestore(&ch->lock, irq_flags);
-                    return -EEXIST;
-                }
-        }
-        req->bytes_transferred = 0;
-        req->status = 0;
-        req->buffer_status = 0;
-        if (list_empty(&ch->list))
-                start_dma = 1;
-        list_add_tail(&req->node, &ch->list);
-        if (start_dma)
-                tegra_dma_update_hw(ch, req);
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-        return 0;
-}
-EXPORT_SYMBOL(tegra_dma_enqueue_req);
-struct tegra_dma_channel *tegra_dma_allocate_channel(int mode)
-{
-        int channel;
-        struct tegra_dma_channel *ch = NULL;
-        if (!tegra_dma_initialized)
-                return NULL;
-        mutex_lock(&tegra_dma_lock);
-        /* first channel is the shared channel */
-        if (mode & TEGRA_DMA_SHARED) {
-                channel = TEGRA_SYSTEM_DMA_CH_MIN;
-        } else {
-                channel = find_first_zero_bit(channel_usage,
-                        ARRAY_SIZE(dma_channels));
-                if (channel >= ARRAY_SIZE(dma_channels))
-                        goto out;
-        }
-        __set_bit(channel, channel_usage);
-        ch = &dma_channels[channel];
-        ch->mode = mode;
-out:
-        mutex_unlock(&tegra_dma_lock);
-        return ch;
-}
-EXPORT_SYMBOL(tegra_dma_allocate_channel);
-void tegra_dma_free_channel(struct tegra_dma_channel *ch)
-{
-        if (ch->mode & TEGRA_DMA_SHARED)
-                return;
-        tegra_dma_cancel(ch);
-        mutex_lock(&tegra_dma_lock);
-        __clear_bit(ch->id, channel_usage);
-        mutex_unlock(&tegra_dma_lock);
-}
-EXPORT_SYMBOL(tegra_dma_free_channel);
-static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req)
-{
-        u32 apb_ptr;
-        u32 ahb_ptr;
-        if (req->to_memory) {
-                apb_ptr = req->source_addr;
-                ahb_ptr = req->dest_addr;
-        } else {
-                apb_ptr = req->dest_addr;
-                ahb_ptr = req->source_addr;
-        }
-        writel(apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR);
-        writel(ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR);
-        req->status = TEGRA_DMA_REQ_INFLIGHT;
-        return;
-}
-static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req)
-{
-        int ahb_addr_wrap;
-        int apb_addr_wrap;
-        int ahb_bus_width;
-        int apb_bus_width;
-        int index;
-        u32 ahb_seq;
-        u32 apb_seq;
-        u32 ahb_ptr;
-        u32 apb_ptr;
-        u32 csr;
-        csr = CSR_IE_EOC | CSR_FLOW;
-        ahb_seq = AHB_SEQ_INTR_ENB | AHB_SEQ_BURST_1;
-        apb_seq = 0;
-        csr |= req->req_sel << CSR_REQ_SEL_SHIFT;
-        /* One shot mode is always single buffered,
-         * continuous mode is always double buffered
-         * */
-        if (ch->mode & TEGRA_DMA_MODE_ONESHOT) {
-                csr |= CSR_ONCE;
-                ch->req_transfer_count = (req->size >> 2) - 1;
-        } else {
-                ahb_seq |= AHB_SEQ_DBL_BUF;
-                /* In double buffered mode, we set the size to half the
-                 * requested size and interrupt when half the buffer
-                 * is full */
-                ch->req_transfer_count = (req->size >> 3) - 1;
-        }
-        csr |= ch->req_transfer_count << CSR_WCOUNT_SHIFT;
-        if (req->to_memory) {
-                apb_ptr = req->source_addr;
-                ahb_ptr = req->dest_addr;
-                apb_addr_wrap = req->source_wrap;
-                ahb_addr_wrap = req->dest_wrap;
-                apb_bus_width = req->source_bus_width;
-                ahb_bus_width = req->dest_bus_width;
-        } else {
-                csr |= CSR_DIR;
-                apb_ptr = req->dest_addr;
-                ahb_ptr = req->source_addr;
-                apb_addr_wrap = req->dest_wrap;
-                ahb_addr_wrap = req->source_wrap;
-                apb_bus_width = req->dest_bus_width;
-                ahb_bus_width = req->source_bus_width;
-        }
-        apb_addr_wrap >>= 2;
-        ahb_addr_wrap >>= 2;
-        /* set address wrap for APB size */
-        index = 0;
-        do  {
-                if (apb_addr_wrap_table[index] == apb_addr_wrap)
-                        break;
-                index++;
-        } while (index < ARRAY_SIZE(apb_addr_wrap_table));
-        BUG_ON(index == ARRAY_SIZE(apb_addr_wrap_table));
-        apb_seq |= index << APB_SEQ_WRAP_SHIFT;
-        /* set address wrap for AHB size */
-        index = 0;
-        do  {
-                if (ahb_addr_wrap_table[index] == ahb_addr_wrap)
-                        break;
-                index++;
-        } while (index < ARRAY_SIZE(ahb_addr_wrap_table));
-        BUG_ON(index == ARRAY_SIZE(ahb_addr_wrap_table));
-        ahb_seq |= index << AHB_SEQ_WRAP_SHIFT;
-        for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) {
-                if (bus_width_table[index] == ahb_bus_width)
-                        break;
-        }
-        BUG_ON(index == ARRAY_SIZE(bus_width_table));
-        ahb_seq |= index << AHB_SEQ_BUS_WIDTH_SHIFT;
-        for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) {
-                if (bus_width_table[index] == apb_bus_width)
-                        break;
-        }
-        BUG_ON(index == ARRAY_SIZE(bus_width_table));
-        apb_seq |= index << APB_SEQ_BUS_WIDTH_SHIFT;
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-        writel(apb_seq, ch->addr + APB_DMA_CHAN_APB_SEQ);
-        writel(apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR);
-        writel(ahb_seq, ch->addr + APB_DMA_CHAN_AHB_SEQ);
-        writel(ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR);
-        csr |= CSR_ENB;
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-        req->status = TEGRA_DMA_REQ_INFLIGHT;
-}
-static void handle_oneshot_dma(struct tegra_dma_channel *ch)
-{
-        struct tegra_dma_req *req;
-        unsigned long irq_flags;
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        if (list_empty(&ch->list)) {
-                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                return;
-        }
-        req = list_entry(ch->list.next, typeof(*req), node);
-        if (req) {
-                int bytes_transferred;
-                bytes_transferred = ch->req_transfer_count;
-                bytes_transferred += 1;
-                bytes_transferred <<= 2;
-                list_del(&req->node);
-                req->bytes_transferred = bytes_transferred;
-                req->status = TEGRA_DMA_REQ_SUCCESS;
-                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                /* Callback should be called without any lock */
-                pr_debug("%s: transferred %d bytes\n", __func__,
-                        req->bytes_transferred);
-                req->complete(req);
-                spin_lock_irqsave(&ch->lock, irq_flags);
-        }
-        if (!list_empty(&ch->list)) {
-                req = list_entry(ch->list.next, typeof(*req), node);
-                /* the complete function we just called may have enqueued
-                   another req, in which case dma has already started */
-                if (req->status != TEGRA_DMA_REQ_INFLIGHT)
-                        tegra_dma_update_hw(ch, req);
-        }
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-}
-static void handle_continuous_dma(struct tegra_dma_channel *ch)
-{
-        struct tegra_dma_req *req;
-        unsigned long irq_flags;
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        if (list_empty(&ch->list)) {
-                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                return;
-        }
-        req = list_entry(ch->list.next, typeof(*req), node);
-        if (req) {
-                if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_EMPTY) {
-                        bool is_dma_ping_complete;
-                        is_dma_ping_complete = (readl(ch->addr + APB_DMA_CHAN_STA)
-                                                & STA_PING_PONG) ? true : false;
-                        if (req->to_memory)
-                                is_dma_ping_complete = !is_dma_ping_complete;
-                        /* Out of sync - Release current buffer */
-                        if (!is_dma_ping_complete) {
-                                int bytes_transferred;
-                                bytes_transferred = ch->req_transfer_count;
-                                bytes_transferred += 1;
-                                bytes_transferred <<= 3;
-                                req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_FULL;
-                                req->bytes_transferred = bytes_transferred;
-                                req->status = TEGRA_DMA_REQ_SUCCESS;
-                                tegra_dma_stop(ch);
-                                if (!list_is_last(&req->node, &ch->list)) {
-                                        struct tegra_dma_req *next_req;
-                                        next_req = list_entry(req->node.next,
-                                                typeof(*next_req), node);
-                                        tegra_dma_update_hw(ch, next_req);
-                                }
-                                list_del(&req->node);
-                                /* DMA lock is NOT held when callbak is called */
-                                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                                req->complete(req);
-                                return;
-                        }
-                        /* Load the next request into the hardware, if available
-                         * */
-                        if (!list_is_last(&req->node, &ch->list)) {
-                                struct tegra_dma_req *next_req;
-                                next_req = list_entry(req->node.next,
-                                        typeof(*next_req), node);
-                                tegra_dma_update_hw_partial(ch, next_req);
-                        }
-                        req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL;
-                        req->status = TEGRA_DMA_REQ_SUCCESS;
-                        /* DMA lock is NOT held when callback is called */
-                        spin_unlock_irqrestore(&ch->lock, irq_flags);
-                        if (likely(req->threshold))
-                                req->threshold(req);
-                        return;
-                } else if (req->buffer_status ==
-                        TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL) {
-                        /* Callback when the buffer is completely full (i.e on
-                         * the second  interrupt */
-                        int bytes_transferred;
-                        bytes_transferred = ch->req_transfer_count;
-                        bytes_transferred += 1;
-                        bytes_transferred <<= 3;
-                        req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_FULL;
-                        req->bytes_transferred = bytes_transferred;
-                        req->status = TEGRA_DMA_REQ_SUCCESS;
-                        list_del(&req->node);
-                        /* DMA lock is NOT held when callbak is called */
-                        spin_unlock_irqrestore(&ch->lock, irq_flags);
-                        req->complete(req);
-                        return;
-                } else {
-                        BUG();
-                }
-        }
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-}
-static irqreturn_t dma_isr(int irq, void *data)
-{
-        struct tegra_dma_channel *ch = data;
-        unsigned long status;
-        status = readl(ch->addr + APB_DMA_CHAN_STA);
-        if (status & STA_ISE_EOC)
-                writel(status, ch->addr + APB_DMA_CHAN_STA);
-        else {
-                pr_warning("Got a spurious ISR for DMA channel %d\n", ch->id);
-                return IRQ_HANDLED;
-        }
-        return IRQ_WAKE_THREAD;
-}
-static irqreturn_t dma_thread_fn(int irq, void *data)
-{
-        struct tegra_dma_channel *ch = data;
-        if (ch->mode & TEGRA_DMA_MODE_ONESHOT)
-                handle_oneshot_dma(ch);
-        else
-                handle_continuous_dma(ch);
-        return IRQ_HANDLED;
-}
-int __init tegra_dma_init(void)
-{
-        int ret = 0;
-        int i;
-        unsigned int irq;
-        void __iomem *addr;
-        struct clk *c;
-        bitmap_fill(channel_usage, NV_DMA_MAX_CHANNELS);
-        c = clk_get_sys("tegra-apbdma", NULL);
-        if (IS_ERR(c)) {
-                pr_err("Unable to get clock for APB DMA\n");
-                ret = PTR_ERR(c);
-                goto fail;
-        }
-        ret = clk_prepare_enable(c);
-        if (ret != 0) {
-                pr_err("Unable to enable clock for APB DMA\n");
-                goto fail;
-        }
-        addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-        writel(GEN_ENABLE, addr + APB_DMA_GEN);
-        writel(0, addr + APB_DMA_CNTRL);
-        writel(0xFFFFFFFFul >> (31 - TEGRA_SYSTEM_DMA_CH_MAX),
-               addr + APB_DMA_IRQ_MASK_SET);
-        for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) {
-                struct tegra_dma_channel *ch = &dma_channels[i];
-                ch->id = i;
-                snprintf(ch->name, TEGRA_DMA_NAME_SIZE, "dma_channel_%d", i);
-                ch->addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
-                        TEGRA_APB_DMA_CH0_SIZE * i);
-                spin_lock_init(&ch->lock);
-                INIT_LIST_HEAD(&ch->list);
-                irq = INT_APB_DMA_CH0 + i;
-                ret = request_threaded_irq(irq, dma_isr, dma_thread_fn, 0,
-                        dma_channels[i].name, ch);
-                if (ret) {
-                        pr_err("Failed to register IRQ %d for DMA %d\n",
-                                irq, i);
-                        goto fail;
-                }
-                ch->irq = irq;
-                __clear_bit(i, channel_usage);
-        }
-        /* mark the shared channel allocated */
-        __set_bit(TEGRA_SYSTEM_DMA_CH_MIN, channel_usage);
-        tegra_dma_initialized = true;
-        return 0;
-fail:
-        writel(0, addr + APB_DMA_GEN);
-        for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) {
-                struct tegra_dma_channel *ch = &dma_channels[i];
-                if (ch->irq)
-                        free_irq(ch->irq, ch);
-        }
-        return ret;
-}
-postcore_initcall(tegra_dma_init);
-#ifdef CONFIG_PM
-static u32 apb_dma[5*TEGRA_SYSTEM_DMA_CH_NR + 3];
-void tegra_dma_suspend(void)
-{
-        void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-        u32 *ctx = apb_dma;
-        int i;
-        *ctx++ = readl(addr + APB_DMA_GEN);
-        *ctx++ = readl(addr + APB_DMA_CNTRL);
-        *ctx++ = readl(addr + APB_DMA_IRQ_MASK);
-        for (i = 0; i < TEGRA_SYSTEM_DMA_CH_NR; i++) {
-                addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
-                                  TEGRA_APB_DMA_CH0_SIZE * i);
-                *ctx++ = readl(addr + APB_DMA_CHAN_CSR);
-                *ctx++ = readl(addr + APB_DMA_CHAN_AHB_PTR);
-                *ctx++ = readl(addr + APB_DMA_CHAN_AHB_SEQ);
-                *ctx++ = readl(addr + APB_DMA_CHAN_APB_PTR);
-                *ctx++ = readl(addr + APB_DMA_CHAN_APB_SEQ);
-        }
-}
-void tegra_dma_resume(void)
-{
-        void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-        u32 *ctx = apb_dma;
-        int i;
-        writel(*ctx++, addr + APB_DMA_GEN);
-        writel(*ctx++, addr + APB_DMA_CNTRL);
-        writel(*ctx++, addr + APB_DMA_IRQ_MASK);
-        for (i = 0; i < TEGRA_SYSTEM_DMA_CH_NR; i++) {
-                addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
-                                  TEGRA_APB_DMA_CH0_SIZE * i);
-                writel(*ctx++, addr + APB_DMA_CHAN_CSR);
-                writel(*ctx++, addr + APB_DMA_CHAN_AHB_PTR);
-                writel(*ctx++, addr + APB_DMA_CHAN_AHB_SEQ);
-                writel(*ctx++, addr + APB_DMA_CHAN_APB_PTR);
-                writel(*ctx++, addr + APB_DMA_CHAN_APB_SEQ);
-        }
-}
-#endif
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index f946d129423c..0b7db174a5de 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -93,9 +93,9 @@ void tegra_init_fuse(void)
 {
        u32 id;
-        u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
+        u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
        reg |= 1 << 28;
-        writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
+        writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
        reg = tegra_fuse_readl(FUSE_SKU_INFO);
        tegra_sku_id = reg & 0xFF;
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fef9c2c51370..6addc78cb6b2 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,17 +7,13 @@
 #include "flowctrl.h"
 #include "reset.h"
+#include "sleep.h"
 #define APB_MISC_GP_HIDREV      0x804
 #define PMC_SCRATCH41   0x140
 #define RESET_DATA(x)   ((TEGRA_RESET_##x)*4)
-        .macro mov32, reg, val
-        movw    \reg, #:lower16:\val
-        movt    \reg, #:upper16:\val
-        .endm
        .section ".text.head", "ax"
        __CPUINIT
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index d8dc9ddd6d18..dca5141a2c31 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -1,123 +1,48 @@
 /*
- *  linux/arch/arm/mach-realview/hotplug.c
 *
 *  Copyright (C) 2002 ARM Ltd.
 *  All Rights Reserved
+ *  Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
 #include <linux/kernel.h>
-#include <linux/errno.h>
 #include <linux/smp.h>
 #include <asm/cacheflush.h>
-#include <asm/cp15.h>
+#include <asm/smp_plat.h>
-static inline void cpu_enter_lowpower(void)
+#include "sleep.h"
-{
+#include "tegra_cpu_car.h"
-        unsigned int v;
-        flush_cache_all();
-        asm volatile(
-        "       mcr     p15, 0, %1, c7, c5, 0\n"
-        "       mcr     p15, 0, %1, c7, c10, 4\n"
-        /*
-         * Turn off coherency
-         */
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       bic     %0, %0, #0x20\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-        "       mrc     p15, 0, %0, c1, c0, 0\n"
-        "       bic     %0, %0, %2\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-          : "=&r" (v)
-          : "r" (0), "Ir" (CR_C)
-          : "cc");
-}
-static inline void cpu_leave_lowpower(void)
-{
-        unsigned int v;
-        asm volatile(
+static void (*tegra_hotplug_shutdown)(void);
-        "mrc    p15, 0, %0, c1, c0, 0\n"
-        "       orr     %0, %0, %1\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       orr     %0, %0, #0x20\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-          : "=&r" (v)
-          : "Ir" (CR_C)
-          : "cc");
-}
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-{
-        /*
-         * there is no power-control hardware on this platform, so all
-         * we can do is put the core into WFI; this is safe as the calling
-         * code will have already disabled interrupts
-         */
-        for (;;) {
-                /*
-                 * here's the WFI
-                 */
-                asm(".word      0xe320f003\n"
-                    :
-                    :
-                    : "memory", "cc");
-                /*if (pen_release == cpu) {*/
-                        /*
-                         * OK, proper wakeup, we're done
-                         */
-                        break;
-                /*}*/
-                /*
-                 * Getting here, means that we have come out of WFI without
-                 * having been woken up - this shouldn't happen
-                 *
-                 * Just note it happening - when we're woken, we can report
-                 * its occurrence.
-                 */
-                (*spurious)++;
-        }
-}
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
 /*
 * platform-specific code to shutdown a CPU
 *
 * Called with IRQs disabled
 */
-void platform_cpu_die(unsigned int cpu)
+void __ref tegra_cpu_die(unsigned int cpu)
 {
-        int spurious = 0;
+        cpu = cpu_logical_map(cpu);
-        /*
+        /* Flush the L1 data cache. */
-         * we're ready for shutdown now, so do it
+        flush_cache_all();
-         */
-        cpu_enter_lowpower();
-        platform_do_lowpower(cpu, &spurious);
-        /*
+        /* Shut down the current CPU. */
-         * bring this CPU back into the world of cache
+        tegra_hotplug_shutdown();
-         * coherency, and then restore interrupts
-         */
-        cpu_leave_lowpower();
-        if (spurious)
+        /* Clock gate the CPU */
-                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+        tegra_wait_cpu_in_reset(cpu);
+        tegra_disable_cpu_clock(cpu);
+        /* Should never return here. */
+        BUG();
 }
-int platform_cpu_disable(unsigned int cpu)
+int tegra_cpu_disable(unsigned int cpu)
 {
        /*
         * we don't allow CPU 0 to be shutdown (it is still too special
@@ -125,3 +50,19 @@ int platform_cpu_disable(unsigned int cpu)
         */
        return cpu == 0 ? -EPERM : 0;
 }
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+extern void tegra20_hotplug_shutdown(void);
+void __init tegra20_hotplug_init(void)
+{
+        tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
+}
+#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+extern void tegra30_hotplug_shutdown(void);
+void __init tegra30_hotplug_init(void)
+{
+        tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+}
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index d97e403303a0..95f3a547c770 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -34,7 +34,10 @@ enum tegra_clk_ex_param {
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
+#ifndef CONFIG_COMMON_CLK
 unsigned long clk_get_rate_all_locked(struct clk *c);
+#endif
 void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
 int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index 9077092812c0..3081cc6dda3b 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -51,101 +51,4 @@
 #define TEGRA_DMA_REQ_SEL_OWR                   25
 #define TEGRA_DMA_REQ_SEL_INVALID               31
-struct tegra_dma_req;
-struct tegra_dma_channel;
-enum tegra_dma_mode {
-        TEGRA_DMA_SHARED = 1,
-        TEGRA_DMA_MODE_CONTINOUS = 2,
-        TEGRA_DMA_MODE_ONESHOT = 4,
-};
-enum tegra_dma_req_error {
-        TEGRA_DMA_REQ_SUCCESS = 0,
-        TEGRA_DMA_REQ_ERROR_ABORTED,
-        TEGRA_DMA_REQ_INFLIGHT,
-};
-enum tegra_dma_req_buff_status {
-        TEGRA_DMA_REQ_BUF_STATUS_EMPTY = 0,
-        TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL,
-        TEGRA_DMA_REQ_BUF_STATUS_FULL,
-};
-struct tegra_dma_req {
-        struct list_head node;
-        unsigned int modid;
-        int instance;
-        /* Called when the req is complete and from the DMA ISR context.
-         * When this is called the req structure is no longer queued by
-         * the DMA channel.
-         *
-         * State of the DMA depends on the number of req it has. If there are
-         * no DMA requests queued up, then it will STOP the DMA. It there are
-         * more requests in the DMA, then it will queue the next request.
-         */
-        void (*complete)(struct tegra_dma_req *req);
-        /*  This is a called from the DMA ISR context when the DMA is still in
-         *  progress and is actively filling same buffer.
-         *
-         *  In case of continuous mode receive, this threshold is 1/2 the buffer
-         *  size. In other cases, this will not even be called as there is no
-         *  hardware support for it.
-         *
-         * In the case of continuous mode receive, if there is next req already
-         * queued, DMA programs the HW to use that req when this req is
-         * completed. If there is no "next req" queued, then DMA ISR doesn't do
-         * anything before calling this callback.
-         *
-         *      This is mainly used by the cases, where the clients has queued
-         *      only one req and want to get some sort of DMA threshold
-         *      callback to program the next buffer.
-         *
-         */
-        void (*threshold)(struct tegra_dma_req *req);
-        /* 1 to copy to memory.
-         * 0 to copy from the memory to device FIFO */
-        int to_memory;
-        void *virt_addr;
-        unsigned long source_addr;
-        unsigned long dest_addr;
-        unsigned long dest_wrap;
-        unsigned long source_wrap;
-        unsigned long source_bus_width;
-        unsigned long dest_bus_width;
-        unsigned long req_sel;
-        unsigned int size;
-        /* Updated by the DMA driver on the conpletion of the request. */
-        int bytes_transferred;
-        int status;
-        /* DMA completion tracking information */
-        int buffer_status;
-        /* Client specific data */
-        void *dev;
-};
-int tegra_dma_enqueue_req(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-void tegra_dma_dequeue(struct tegra_dma_channel *ch);
-void tegra_dma_flush(struct tegra_dma_channel *ch);
-bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-bool tegra_dma_is_empty(struct tegra_dma_channel *ch);
-struct tegra_dma_channel *tegra_dma_allocate_channel(int mode);
-void tegra_dma_free_channel(struct tegra_dma_channel *ch);
-int __init tegra_dma_init(void);
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-tegra/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
deleted file mode 100644
index fe700f9ce7dc..000000000000
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/io.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *      Erik Gilling <konkers@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_TEGRA_IO_H
-#define __MACH_TEGRA_IO_H
-#define IO_SPACE_LIMIT 0xffff
-#ifndef __ASSEMBLER__
-#ifdef CONFIG_TEGRA_PCI
-extern void __iomem *tegra_pcie_io_base;
-static inline void __iomem *__io(unsigned long addr)
-{
-        return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT);
-}
-#else
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)addr;
-}
-#endif
-#define __io(a)         __io(a)
-#endif
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 7e76da73121c..fee3a94c4549 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -303,6 +303,9 @@
 #define IO_APB_VIRT     IOMEM(0xFE300000)
 #define IO_APB_SIZE     SZ_1M
+#define TEGRA_PCIE_BASE         0x80000000
+#define TEGRA_PCIE_IO_BASE      (TEGRA_PCIE_BASE + SZ_4M)
 #define IO_TO_VIRT_BETWEEN(p, st, sz)   ((p) >= (st) && (p) < ((st) + (sz)))
 #define IO_TO_VIRT_XLATE(p, pst, vst)   (((p) - (pst) + (vst)))
diff --git a/arch/arm/mach-tegra/include/mach/kbc.h b/arch/arm/mach-tegra/include/mach/kbc.h
deleted file mode 100644
index a13025612939..000000000000
--- a/arch/arm/mach-tegra/include/mach/kbc.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Platform definitions for tegra-kbc keyboard input driver
- *
- * Copyright (c) 2010-2011, NVIDIA Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-#ifndef ASMARM_ARCH_TEGRA_KBC_H
-#define ASMARM_ARCH_TEGRA_KBC_H
-#include <linux/types.h>
-#include <linux/input/matrix_keypad.h>
-#define KBC_MAX_GPIO    24
-#define KBC_MAX_KPENT   8
-#define KBC_MAX_ROW     16
-#define KBC_MAX_COL     8
-#define KBC_MAX_KEY     (KBC_MAX_ROW * KBC_MAX_COL)
-enum tegra_pin_type {
-        PIN_CFG_IGNORE,
-        PIN_CFG_COL,
-        PIN_CFG_ROW,
-};
-struct tegra_kbc_pin_cfg {
-        enum tegra_pin_type type;
-        unsigned char num;
-};
-struct tegra_kbc_wake_key {
-        u8 row:4;
-        u8 col:4;
-};
-struct tegra_kbc_platform_data {
-        unsigned int debounce_cnt;
-        unsigned int repeat_cnt;
-        struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
-        const struct matrix_keymap_data *keymap_data;
-        u32 wakeup_key;
-        bool wakeup;
-        bool use_fn_map;
-        bool use_ghost_filter;
-};
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinconf-tegra.h b/arch/arm/mach-tegra/include/mach/pinconf-tegra.h
deleted file mode 100644
index 1f24d304921e..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinconf-tegra.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * pinctrl configuration definitions for the NVIDIA Tegra pinmux
- *
- * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- */
-#ifndef __PINCONF_TEGRA_H__
-#define __PINCONF_TEGRA_H__
-enum tegra_pinconf_param {
-        /* argument: tegra_pinconf_pull */
-        TEGRA_PINCONF_PARAM_PULL,
-        /* argument: tegra_pinconf_tristate */
-        TEGRA_PINCONF_PARAM_TRISTATE,
-        /* argument: Boolean */
-        TEGRA_PINCONF_PARAM_ENABLE_INPUT,
-        /* argument: Boolean */
-        TEGRA_PINCONF_PARAM_OPEN_DRAIN,
-        /* argument: Boolean */
-        TEGRA_PINCONF_PARAM_LOCK,
-        /* argument: Boolean */
-        TEGRA_PINCONF_PARAM_IORESET,
-        /* argument: Boolean */
-        TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
-        /* argument: Boolean */
-        TEGRA_PINCONF_PARAM_SCHMITT,
-        /* argument: Boolean */
-        TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
-        /* argument: Integer, range is HW-dependant */
-        TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
-        /* argument: Integer, range is HW-dependant */
-        TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
-        /* argument: Integer, range is HW-dependant */
-        TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
-        /* argument: Integer, range is HW-dependant */
-        TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
-};
-enum tegra_pinconf_pull {
-        TEGRA_PINCONFIG_PULL_NONE,
-        TEGRA_PINCONFIG_PULL_DOWN,
-        TEGRA_PINCONFIG_PULL_UP,
-};
-enum tegra_pinconf_tristate {
-        TEGRA_PINCONFIG_DRIVEN,
-        TEGRA_PINCONFIG_TRISTATE,
-};
-#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
-#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
-#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/sdhci.h b/arch/arm/mach-tegra/include/mach/sdhci.h
deleted file mode 100644
index 4231bc7b8652..000000000000
--- a/arch/arm/mach-tegra/include/mach/sdhci.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * include/asm-arm/arch-tegra/include/mach/sdhci.h
- *
- * Copyright (C) 2009 Palm, Inc.
- * Author: Yvonne Yip <y@palm.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ASM_ARM_ARCH_TEGRA_SDHCI_H
-#define __ASM_ARM_ARCH_TEGRA_SDHCI_H
-#include <linux/mmc/host.h>
-struct tegra_sdhci_platform_data {
-        int cd_gpio;
-        int wp_gpio;
-        int power_gpio;
-        int is_8bit;
-        int pm_flags;
-};
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/smmu.h b/arch/arm/mach-tegra/include/mach/smmu.h
deleted file mode 100644
index dad403a9cf00..000000000000
--- a/arch/arm/mach-tegra/include/mach/smmu.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * IOMMU API for SMMU in Tegra30
- *
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#ifndef MACH_SMMU_H
-#define MACH_SMMU_H
-enum smmu_hwgrp {
-        HWGRP_AFI,
-        HWGRP_AVPC,
-        HWGRP_DC,
-        HWGRP_DCB,
-        HWGRP_EPP,
-        HWGRP_G2,
-        HWGRP_HC,
-        HWGRP_HDA,
-        HWGRP_ISP,
-        HWGRP_MPE,
-        HWGRP_NV,
-        HWGRP_NV2,
-        HWGRP_PPCS,
-        HWGRP_SATA,
-        HWGRP_VDE,
-        HWGRP_VI,
-        HWGRP_COUNT,
-        HWGRP_END = ~0,
-};
-#define HWG_AFI         (1 << HWGRP_AFI)
-#define HWG_AVPC        (1 << HWGRP_AVPC)
-#define HWG_DC          (1 << HWGRP_DC)
-#define HWG_DCB         (1 << HWGRP_DCB)
-#define HWG_EPP         (1 << HWGRP_EPP)
-#define HWG_G2          (1 << HWGRP_G2)
-#define HWG_HC          (1 << HWGRP_HC)
-#define HWG_HDA         (1 << HWGRP_HDA)
-#define HWG_ISP         (1 << HWGRP_ISP)
-#define HWG_MPE         (1 << HWGRP_MPE)
-#define HWG_NV          (1 << HWGRP_NV)
-#define HWG_NV2         (1 << HWGRP_NV2)
-#define HWG_PPCS        (1 << HWGRP_PPCS)
-#define HWG_SATA        (1 << HWGRP_SATA)
-#define HWG_VDE         (1 << HWGRP_VDE)
-#define HWG_VI          (1 << HWGRP_VI)
-#endif  /* MACH_SMMU_H */
diff --git a/arch/arm/mach-tegra/include/mach/suspend.h b/arch/arm/mach-tegra/include/mach/suspend.h
deleted file mode 100644
index 5af8715d2e1e..000000000000
--- a/arch/arm/mach-tegra/include/mach/suspend.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/suspend.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef _MACH_TEGRA_SUSPEND_H_
-#define _MACH_TEGRA_SUSPEND_H_
-void tegra_pinmux_suspend(void);
-void tegra_irq_suspend(void);
-void tegra_gpio_suspend(void);
-void tegra_clk_suspend(void);
-void tegra_dma_suspend(void);
-void tegra_timer_suspend(void);
-void tegra_pinmux_resume(void);
-void tegra_irq_resume(void);
-void tegra_gpio_resume(void);
-void tegra_clk_resume(void);
-void tegra_dma_resume(void);
-void tegra_timer_resume(void);
-#endif /* _MACH_TEGRA_SUSPEND_H_ */
diff --git a/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h
deleted file mode 100644
index 9d293344a7ff..000000000000
--- a/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h
- *
- * Copyright 2011 NVIDIA, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-struct tegra_wm8903_platform_data {
-        int gpio_spkr_en;
-        int gpio_hp_det;
-        int gpio_hp_mute;
-        int gpio_int_mic_en;
-        int gpio_ext_mic_en;
-};
diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/arch/arm/mach-tegra/include/mach/usb_phy.h
deleted file mode 100644
index 935ce9f65590..000000000000
--- a/arch/arm/mach-tegra/include/mach/usb_phy.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/usb_phy.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_USB_PHY_H
-#define __MACH_USB_PHY_H
-#include <linux/clk.h>
-#include <linux/usb/otg.h>
-struct tegra_utmip_config {
-        u8 hssync_start_delay;
-        u8 elastic_limit;
-        u8 idle_wait_delay;
-        u8 term_range_adj;
-        u8 xcvr_setup;
-        u8 xcvr_lsfslew;
-        u8 xcvr_lsrslew;
-};
-struct tegra_ulpi_config {
-        int reset_gpio;
-        const char *clk;
-};
-enum tegra_usb_phy_port_speed {
-        TEGRA_USB_PHY_PORT_SPEED_FULL = 0,
-        TEGRA_USB_PHY_PORT_SPEED_LOW,
-        TEGRA_USB_PHY_PORT_SPEED_HIGH,
-};
-enum tegra_usb_phy_mode {
-        TEGRA_USB_PHY_MODE_DEVICE,
-        TEGRA_USB_PHY_MODE_HOST,
-};
-struct tegra_xtal_freq;
-struct tegra_usb_phy {
-        int instance;
-        const struct tegra_xtal_freq *freq;
-        void __iomem *regs;
-        void __iomem *pad_regs;
-        struct clk *clk;
-        struct clk *pll_u;
-        struct clk *pad_clk;
-        enum tegra_usb_phy_mode mode;
-        void *config;
-        struct usb_phy *ulpi;
-};
-struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
-        void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode);
-int tegra_usb_phy_power_on(struct tegra_usb_phy *phy);
-void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy);
-void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy);
-void tegra_usb_phy_power_off(struct tegra_usb_phy *phy);
-void tegra_usb_phy_preresume(struct tegra_usb_phy *phy);
-void tegra_usb_phy_postresume(struct tegra_usb_phy *phy);
-void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
-                                 enum tegra_usb_phy_port_speed port_speed);
-void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy);
-void tegra_usb_phy_close(struct tegra_usb_phy *phy);
-#endif /* __MACH_USB_PHY_H */
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index d3ad5150d660..a8dba6489c9b 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -171,8 +171,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 * 0x90000000 - 0x9fffffff - non-prefetchable memory
 * 0xa0000000 - 0xbfffffff - prefetchable memory
 */
-#define TEGRA_PCIE_BASE         0x80000000
 #define PCIE_REGS_SZ            SZ_16K
 #define PCIE_CFG_OFF            PCIE_REGS_SZ
 #define PCIE_CFG_SZ             SZ_1M
@@ -180,8 +178,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 #define PCIE_EXT_CFG_SZ         SZ_1M
 #define PCIE_IOMAP_SZ           (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
-#define MMIO_BASE               (TEGRA_PCIE_BASE + SZ_4M)
-#define MMIO_SIZE               SZ_64K
 #define MEM_BASE_0              (TEGRA_PCIE_BASE + SZ_256M)
 #define MEM_SIZE_0              SZ_128M
 #define MEM_BASE_1              (MEM_BASE_0 + MEM_SIZE_0)
@@ -204,10 +200,9 @@ struct tegra_pcie_port {
        bool                    link_up;
-        char                    io_space_name[16];
        char                    mem_space_name[16];
        char                    prefetch_space_name[20];
-        struct resource         res[3];
+        struct resource         res[2];
 };
 struct tegra_pcie_info {
@@ -223,17 +218,7 @@ struct tegra_pcie_info {
        struct clk              *pll_e;
 };
-static struct tegra_pcie_info tegra_pcie = {
+static struct tegra_pcie_info tegra_pcie;
-        .res_mmio = {
-                .name = "PCI IO",
-                .start = MMIO_BASE,
-                .end = MMIO_BASE + MMIO_SIZE - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-void __iomem *tegra_pcie_io_base;
-EXPORT_SYMBOL(tegra_pcie_io_base);
 static inline void afi_writel(u32 value, unsigned long offset)
 {
@@ -367,17 +352,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
 /* Tegra PCIE requires relaxed ordering */
 static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev)
 {
-        u16 val16;
+        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
-        int pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
-        if (pos <= 0) {
-                dev_err(&dev->dev, "skipping relaxed ordering fixup\n");
-                return;
-        }
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16);
-        val16 |= PCI_EXP_DEVCTL_RELAX_EN;
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
@@ -391,24 +366,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
        pp = tegra_pcie.port + nr;
        pp->root_bus_nr = sys->busnr;
-        /*
+        pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE);
-         * IORESOURCE_IO
-         */
-        snprintf(pp->io_space_name, sizeof(pp->io_space_name),
-                 "PCIe %d I/O", pp->index);
-        pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
-        pp->res[0].name = pp->io_space_name;
-        if (pp->index == 0) {
-                pp->res[0].start = PCIBIOS_MIN_IO;
-                pp->res[0].end = pp->res[0].start + SZ_32K - 1;
-        } else {
-                pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K;
-                pp->res[0].end = IO_SPACE_LIMIT;
-        }
-        pp->res[0].flags = IORESOURCE_IO;
-        if (request_resource(&ioport_resource, &pp->res[0]))
-                panic("Request PCIe IO resource failed\n");
-        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
        /*
         * IORESOURCE_MEM
@@ -416,18 +374,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
        snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
                 "PCIe %d MEM", pp->index);
        pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
-        pp->res[1].name = pp->mem_space_name;
+        pp->res[0].name = pp->mem_space_name;
        if (pp->index == 0) {
-                pp->res[1].start = MEM_BASE_0;
+                pp->res[0].start = MEM_BASE_0;
-                pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1;
+                pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1;
        } else {
-                pp->res[1].start = MEM_BASE_1;
+                pp->res[0].start = MEM_BASE_1;
-                pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1;
+                pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1;
        }
-        pp->res[1].flags = IORESOURCE_MEM;
+        pp->res[0].flags = IORESOURCE_MEM;
-        if (request_resource(&iomem_resource, &pp->res[1]))
+        if (request_resource(&iomem_resource, &pp->res[0]))
                panic("Request PCIe Memory resource failed\n");
-        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset);
        /*
         * IORESOURCE_MEM | IORESOURCE_PREFETCH
@@ -435,18 +393,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
        snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
                 "PCIe %d PREFETCH MEM", pp->index);
        pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
-        pp->res[2].name = pp->prefetch_space_name;
+        pp->res[1].name = pp->prefetch_space_name;
        if (pp->index == 0) {
-                pp->res[2].start = PREFETCH_MEM_BASE_0;
+                pp->res[1].start = PREFETCH_MEM_BASE_0;
-                pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1;
+                pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1;
        } else {
-                pp->res[2].start = PREFETCH_MEM_BASE_1;
+                pp->res[1].start = PREFETCH_MEM_BASE_1;
-                pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1;
+                pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1;
        }
-        pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+        pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-        if (request_resource(&iomem_resource, &pp->res[2]))
+        if (request_resource(&iomem_resource, &pp->res[1]))
                panic("Request PCIe Prefetch Memory resource failed\n");
-        pci_add_resource_offset(&sys->resources, &pp->res[2], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
        return 1;
 }
@@ -541,8 +499,8 @@ static void tegra_pcie_setup_translations(void)
        /* Bar 2: downstream IO bar */
        fpci_bar = ((__u32)0xfdfc << 16);
-        size = MMIO_SIZE;
+        size = SZ_128K;
-        axi_address = MMIO_BASE;
+        axi_address = TEGRA_PCIE_IO_BASE;
        afi_writel(axi_address, AFI_AXI_BAR2_START);
        afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
        afi_writel(fpci_bar, AFI_FPCI_BAR2);
@@ -776,7 +734,6 @@ static void tegra_pcie_clocks_put(void)
 static int __init tegra_pcie_get_resources(void)
 {
-        struct resource *res_mmio = &tegra_pcie.res_mmio;
        int err;
        err = tegra_pcie_clocks_get();
@@ -798,34 +755,16 @@ static int __init tegra_pcie_get_resources(void)
                goto err_map_reg;
        }
-        err = request_resource(&iomem_resource, res_mmio);
-        if (err) {
-                pr_err("PCIE: Failed to request resources: %d\n", err);
-                goto err_req_io;
-        }
-        tegra_pcie_io_base = ioremap_nocache(res_mmio->start,
-                                             resource_size(res_mmio));
-        if (tegra_pcie_io_base == NULL) {
-                pr_err("PCIE: Failed to map IO\n");
-                err = -ENOMEM;
-                goto err_map_io;
-        }
        err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
                          IRQF_SHARED, "PCIE", &tegra_pcie);
        if (err) {
                pr_err("PCIE: Failed to register IRQ: %d\n", err);
-                goto err_irq;
+                goto err_req_io;
        }
        set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
        return 0;
-err_irq:
-        iounmap(tegra_pcie_io_base);
-err_map_io:
-        release_resource(&tegra_pcie.res_mmio);
 err_req_io:
        iounmap(tegra_pcie.regs);
 err_map_reg:
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 1a208dbf682f..81cb26591acf 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -31,6 +31,9 @@
 #include "fuse.h"
 #include "flowctrl.h"
 #include "reset.h"
+#include "tegra_cpu_car.h"
+#include "common.h"
 extern void tegra_secondary_startup(void);
@@ -38,19 +41,8 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
 #define EVP_CPU_RESET_VECTOR \
        (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
-#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
-        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
+static void __cpuinit tegra_secondary_init(unsigned int cpu)
-#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
-        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
-#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
-        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
-#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
-        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
-#define CPU_CLOCK(cpu)  (0x1<<(8+cpu))
-#define CPU_RESET(cpu)  (0x1111ul<<(cpu))
-void __cpuinit platform_secondary_init(unsigned int cpu)
 {
        /*
         * if any interrupts are already enabled for the primary
@@ -63,13 +55,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 static int tegra20_power_up_cpu(unsigned int cpu)
 {
-        u32 reg;
        /* Enable the CPU clock. */
-        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        tegra_enable_cpu_clock(cpu);
-        writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-        barrier();
-        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
        /* Clear flow controller CSR. */
        flowctrl_write_cpu_csr(cpu, 0);
@@ -79,7 +66,6 @@ static int tegra20_power_up_cpu(unsigned int cpu)
 static int tegra30_power_up_cpu(unsigned int cpu)
 {
-        u32 reg;
        int ret, pwrgateid;
        unsigned long timeout;
@@ -103,8 +89,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
        }
        /* CPU partition is powered. Enable the CPU clock. */
-        writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+        tegra_enable_cpu_clock(cpu);
-        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
        udelay(10);
        /* Remove I/O clamps. */
@@ -117,7 +102,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
        return 0;
 }
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        int status;
@@ -128,8 +113,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         * via the flow controller). This will have no effect on first boot
         * of the CPU since it should already be in reset.
         */
-        writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+        tegra_put_cpu_in_reset(cpu);
-        dmb();
        /*
         * Unhalt the CPU. If the flow controller was used to power-gate the
@@ -155,8 +139,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
                goto done;
        /* Take the CPU out of reset. */
-        writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+        tegra_cpu_out_of_reset(cpu);
-        wmb();
 done:
        return status;
 }
@@ -165,7 +148,7 @@ done:
 * Initialise the CPU possible map early - this describes the CPUs
 * which may be present or become present in the system.
 */
-void __init smp_init_cpus(void)
+static void __init tegra_smp_init_cpus(void)
 {
        unsigned int i, ncores = scu_get_core_count(scu_base);
@@ -181,8 +164,19 @@ void __init smp_init_cpus(void)
        set_smp_cross_call(gic_raise_softirq);
 }
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
 {
        tegra_cpu_reset_handler_init();
        scu_enable(scu_base);
 }
+struct smp_operations tegra_smp_ops __initdata = {
+        .smp_init_cpus          = tegra_smp_init_cpus,
+        .smp_prepare_cpus       = tegra_smp_prepare_cpus,
+        .smp_secondary_init     = tegra_secondary_init,
+        .smp_boot_secondary     = tegra_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = tegra_cpu_die,
+        .cpu_disable            = tegra_cpu_disable,
+#endif
+};
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 15d506501ccc..de0662de28a0 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -199,7 +199,9 @@ int __init tegra_powergate_init(void)
 #ifdef CONFIG_DEBUG_FS
-static const char * const powergate_name[] = {
+static const char * const *powergate_name;
+static const char * const powergate_name_t20[] = {
        [TEGRA_POWERGATE_CPU]   = "cpu",
        [TEGRA_POWERGATE_3D]    = "3d",
        [TEGRA_POWERGATE_VENC]  = "venc",
@@ -209,6 +211,23 @@ static const char * const powergate_name[] = {
        [TEGRA_POWERGATE_MPE]   = "mpe",
 };
+static const char * const powergate_name_t30[] = {
+        [TEGRA_POWERGATE_CPU]   = "cpu0",
+        [TEGRA_POWERGATE_3D]    = "3d0",
+        [TEGRA_POWERGATE_VENC]  = "venc",
+        [TEGRA_POWERGATE_VDEC]  = "vdec",
+        [TEGRA_POWERGATE_PCIE]  = "pcie",
+        [TEGRA_POWERGATE_L2]    = "l2",
+        [TEGRA_POWERGATE_MPE]   = "mpe",
+        [TEGRA_POWERGATE_HEG]   = "heg",
+        [TEGRA_POWERGATE_SATA]  = "sata",
+        [TEGRA_POWERGATE_CPU1]  = "cpu1",
+        [TEGRA_POWERGATE_CPU2]  = "cpu2",
+        [TEGRA_POWERGATE_CPU3]  = "cpu3",
+        [TEGRA_POWERGATE_CELP]  = "celp",
+        [TEGRA_POWERGATE_3D1]   = "3d1",
+};
 static int powergate_show(struct seq_file *s, void *data)
 {
        int i;
@@ -237,14 +256,24 @@ static const struct file_operations powergate_fops = {
 int __init tegra_powergate_debugfs_init(void)
 {
        struct dentry *d;
-        int err = -ENOMEM;
-        d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
+        switch (tegra_chip_id) {
-                &powergate_fops);
+        case TEGRA20:
-        if (!d)
+                powergate_name = powergate_name_t20;
-                return -ENOMEM;
+                break;
+        case TEGRA30:
+                powergate_name = powergate_name_t30;
+                break;
+        }
+        if (powergate_name) {
+                d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
+                        &powergate_fops);
+                if (!d)
+                        return -ENOMEM;
+        }
-        return err;
+        return 0;
 }
 #endif
diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-t20.S
new file mode 100644
index 000000000000..a36ae413e2b8
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t20.S
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2011, Google, Inc.
+ *
+ * Author: Colin Cross <ccross@android.com>
+ *         Gary King <gking@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/iomap.h>
+#include "sleep.h"
+#include "flowctrl.h"
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
+/*
+ * tegra20_hotplug_shutdown(void)
+ *
+ * puts the current cpu in reset
+ * should never return
+ */
+ENTRY(tegra20_hotplug_shutdown)
+        /* Turn off SMP coherency */
+        exit_smp r4, r5
+        /* Put this CPU down */
+        cpu_id  r0
+        bl      tegra20_cpu_shutdown
+        mov     pc, lr                  @ should never get here
+ENDPROC(tegra20_hotplug_shutdown)
+/*
+ * tegra20_cpu_shutdown(int cpu)
+ *
+ * r0 is cpu to reset
+ *
+ * puts the specified CPU in wait-for-event mode on the flow controller
+ * and puts the CPU in reset
+ * can be called on the current cpu or another cpu
+ * if called on the current cpu, does not return
+ * MUST NOT BE CALLED FOR CPU 0.
+ *
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra20_cpu_shutdown)
+        cmp     r0, #0
+        moveq   pc, lr                  @ must not be called for CPU 0
+        cpu_to_halt_reg r1, r0
+        ldr     r3, =TEGRA_FLOW_CTRL_VIRT
+        mov     r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME
+        str     r2, [r3, r1]            @ put flow controller in wait event mode
+        ldr     r2, [r3, r1]
+        isb
+        dsb
+        movw    r1, 0x1011
+        mov     r1, r1, lsl r0
+        ldr     r3, =TEGRA_CLK_RESET_VIRT
+        str     r1, [r3, #0x340]        @ put slave CPU in reset
+        isb
+        dsb
+        cpu_id  r3
+        cmp     r3, r0
+        beq     .
+        mov     pc, lr
+ENDPROC(tegra20_cpu_shutdown)
+#endif
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S
new file mode 100644
index 000000000000..777d9cee8b90
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t30.S
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/iomap.h>
+#include "sleep.h"
+#include "flowctrl.h"
+#define TEGRA30_POWER_HOTPLUG_SHUTDOWN  (1 << 27) /* Hotplug shutdown */
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
+/*
+ * tegra30_hotplug_shutdown(void)
+ *
+ * Powergates the current CPU.
+ * Should never return.
+ */
+ENTRY(tegra30_hotplug_shutdown)
+        /* Turn off SMP coherency */
+        exit_smp r4, r5
+        /* Powergate this CPU */
+        mov     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+        bl      tegra30_cpu_shutdown
+        mov     pc, lr                  @ should never get here
+ENDPROC(tegra30_hotplug_shutdown)
+/*
+ * tegra30_cpu_shutdown(unsigned long flags)
+ *
+ * Puts the current CPU in wait-for-event mode on the flow controller
+ * and powergates it -- flags (in R0) indicate the request type.
+ * Must never be called for CPU 0.
+ *
+ * corrupts r0-r4, r12
+ */
+ENTRY(tegra30_cpu_shutdown)
+        cpu_id  r3
+        cmp     r3, #0
+        moveq   pc, lr          @ Must never be called for CPU 0
+        ldr     r12, =TEGRA_FLOW_CTRL_VIRT
+        cpu_to_csr_reg r1, r3
+        add     r1, r1, r12     @ virtual CSR address for this CPU
+        cpu_to_halt_reg r2, r3
+        add     r2, r2, r12     @ virtual HALT_EVENTS address for this CPU
+        /*
+         * Clear this CPU's "event" and "interrupt" flags and power gate
+         * it when halting but not before it is in the "WFE" state.
+         */
+        movw    r12, \
+                FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
+                FLOW_CTRL_CSR_ENABLE
+        mov     r4, #(1 << 4)
+        orr     r12, r12, r4, lsl r3
+        str     r12, [r1]
+        /* Halt this CPU. */
+        mov     r3, #0x400
+delay_1:
+        subs    r3, r3, #1                      @ delay as a part of wfe war.
+        bge     delay_1;
+        cpsid   a                               @ disable imprecise aborts.
+        ldr     r3, [r1]                        @ read CSR
+        str     r3, [r1]                        @ clear CSR
+        tst     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+        movne   r3, #FLOW_CTRL_WAITEVENT                @ For hotplug
+        str     r3, [r2]
+        ldr     r0, [r2]
+        b       wfe_war
+__cpu_reset_again:
+        dsb
+        .align 5
+        wfe                                     @ CPU should be power gated here
+wfe_war:
+        b       __cpu_reset_again
+        /*
+         * 38 nop's, which fills reset of wfe cache line and
+         * 4 more cachelines with nop
+         */
+        .rept 38
+        nop
+        .endr
+        b       .                               @ should never get here
+ENDPROC(tegra30_cpu_shutdown)
+#endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index d29b156a8011..ea81554c4833 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -29,36 +29,5 @@
 #include <mach/iomap.h>
 #include "flowctrl.h"
+#include "sleep.h"
-#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
-                                        + IO_PPSB_VIRT)
-/* returns the offset of the flow controller halt register for a cpu */
-.macro cpu_to_halt_reg rd, rcpu
-        cmp     \rcpu, #0
-        subne   \rd, \rcpu, #1
-        movne   \rd, \rd, lsl #3
-        addne   \rd, \rd, #0x14
-        moveq   \rd, #0
-.endm
-/* returns the offset of the flow controller csr register for a cpu */
-.macro cpu_to_csr_reg rd, rcpu
-        cmp     \rcpu, #0
-        subne   \rd, \rcpu, #1
-        movne   \rd, \rd, lsl #3
-        addne   \rd, \rd, #0x18
-        moveq   \rd, #8
-.endm
-/* returns the ID of the current processor */
-.macro cpu_id, rd
-        mrc     p15, 0, \rd, c0, c0, 5
-        and     \rd, \rd, #0xF
-.endm
-/* loads a 32-bit value into a register without a data access */
-.macro mov32, reg, val
-        movw    \reg, #:lower16:\val
-        movt    \reg, #:upper16:\val
-.endm
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
new file mode 100644
index 000000000000..e25a7cd703d9
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __MACH_TEGRA_SLEEP_H
+#define __MACH_TEGRA_SLEEP_H
+#include <mach/iomap.h>
+#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
+                                        + IO_CPU_VIRT)
+#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
+                                        + IO_PPSB_VIRT)
+#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
+                                        + IO_PPSB_VIRT)
+#ifdef __ASSEMBLY__
+/* returns the offset of the flow controller halt register for a cpu */
+.macro cpu_to_halt_reg rd, rcpu
+        cmp     \rcpu, #0
+        subne   \rd, \rcpu, #1
+        movne   \rd, \rd, lsl #3
+        addne   \rd, \rd, #0x14
+        moveq   \rd, #0
+.endm
+/* returns the offset of the flow controller csr register for a cpu */
+.macro cpu_to_csr_reg rd, rcpu
+        cmp     \rcpu, #0
+        subne   \rd, \rcpu, #1
+        movne   \rd, \rd, lsl #3
+        addne   \rd, \rd, #0x18
+        moveq   \rd, #8
+.endm
+/* returns the ID of the current processor */
+.macro cpu_id, rd
+        mrc     p15, 0, \rd, c0, c0, 5
+        and     \rd, \rd, #0xF
+.endm
+/* loads a 32-bit value into a register without a data access */
+.macro mov32, reg, val
+        movw    \reg, #:lower16:\val
+        movt    \reg, #:upper16:\val
+.endm
+/* Macro to exit SMP coherency. */
+.macro exit_smp, tmp1, tmp2
+        mrc     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
+        bic     \tmp1, \tmp1, #(1<<6) | (1<<0)  @ clear ACTLR.SMP | ACTLR.FW
+        mcr     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
+        isb
+        cpu_id  \tmp1
+        mov     \tmp1, \tmp1, lsl #2
+        mov     \tmp2, #0xf
+        mov     \tmp2, \tmp2, lsl \tmp1
+        mov32   \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
+        str     \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
+        dsb
+.endm
+#else
+#ifdef CONFIG_HOTPLUG_CPU
+void tegra20_hotplug_init(void);
+void tegra30_hotplug_init(void);
+#else
+static inline void tegra20_hotplug_init(void) {}
+static inline void tegra30_hotplug_init(void) {}
+#endif
+#endif
+#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
new file mode 100644
index 000000000000..deb873fb12b6
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -0,0 +1,1624 @@
+/*
+ * arch/arm/mach-tegra/tegra20_clocks.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/clk.h>
+#include <mach/iomap.h>
+#include "clock.h"
+#include "fuse.h"
+#include "tegra2_emc.h"
+#include "tegra_cpu_car.h"
+#define RST_DEVICES                     0x004
+#define RST_DEVICES_SET                 0x300
+#define RST_DEVICES_CLR                 0x304
+#define RST_DEVICES_NUM                 3
+#define CLK_OUT_ENB                     0x010
+#define CLK_OUT_ENB_SET                 0x320
+#define CLK_OUT_ENB_CLR                 0x324
+#define CLK_OUT_ENB_NUM                 3
+#define CLK_MASK_ARM                    0x44
+#define MISC_CLK_ENB                    0x48
+#define OSC_CTRL                        0x50
+#define OSC_CTRL_OSC_FREQ_MASK          (3<<30)
+#define OSC_CTRL_OSC_FREQ_13MHZ         (0<<30)
+#define OSC_CTRL_OSC_FREQ_19_2MHZ       (1<<30)
+#define OSC_CTRL_OSC_FREQ_12MHZ         (2<<30)
+#define OSC_CTRL_OSC_FREQ_26MHZ         (3<<30)
+#define OSC_CTRL_MASK                   (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
+#define OSC_FREQ_DET                    0x58
+#define OSC_FREQ_DET_TRIG               (1<<31)
+#define OSC_FREQ_DET_STATUS             0x5C
+#define OSC_FREQ_DET_BUSY               (1<<31)
+#define OSC_FREQ_DET_CNT_MASK           0xFFFF
+#define PERIPH_CLK_SOURCE_I2S1          0x100
+#define PERIPH_CLK_SOURCE_EMC           0x19c
+#define PERIPH_CLK_SOURCE_OSC           0x1fc
+#define PERIPH_CLK_SOURCE_NUM \
+        ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
+#define PERIPH_CLK_SOURCE_MASK          (3<<30)
+#define PERIPH_CLK_SOURCE_SHIFT         30
+#define PERIPH_CLK_SOURCE_PWM_MASK      (7<<28)
+#define PERIPH_CLK_SOURCE_PWM_SHIFT     28
+#define PERIPH_CLK_SOURCE_ENABLE        (1<<28)
+#define PERIPH_CLK_SOURCE_DIVU71_MASK   0xFF
+#define PERIPH_CLK_SOURCE_DIVU16_MASK   0xFFFF
+#define PERIPH_CLK_SOURCE_DIV_SHIFT     0
+#define SDMMC_CLK_INT_FB_SEL            (1 << 23)
+#define SDMMC_CLK_INT_FB_DLY_SHIFT      16
+#define SDMMC_CLK_INT_FB_DLY_MASK       (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
+#define PLL_BASE                        0x0
+#define PLL_BASE_BYPASS                 (1<<31)
+#define PLL_BASE_ENABLE                 (1<<30)
+#define PLL_BASE_REF_ENABLE             (1<<29)
+#define PLL_BASE_OVERRIDE               (1<<28)
+#define PLL_BASE_DIVP_MASK              (0x7<<20)
+#define PLL_BASE_DIVP_SHIFT             20
+#define PLL_BASE_DIVN_MASK              (0x3FF<<8)
+#define PLL_BASE_DIVN_SHIFT             8
+#define PLL_BASE_DIVM_MASK              (0x1F)
+#define PLL_BASE_DIVM_SHIFT             0
+#define PLL_OUT_RATIO_MASK              (0xFF<<8)
+#define PLL_OUT_RATIO_SHIFT             8
+#define PLL_OUT_OVERRIDE                (1<<2)
+#define PLL_OUT_CLKEN                   (1<<1)
+#define PLL_OUT_RESET_DISABLE           (1<<0)
+#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
+#define PLL_MISC_DCCON_SHIFT            20
+#define PLL_MISC_CPCON_SHIFT            8
+#define PLL_MISC_CPCON_MASK             (0xF<<PLL_MISC_CPCON_SHIFT)
+#define PLL_MISC_LFCON_SHIFT            4
+#define PLL_MISC_LFCON_MASK             (0xF<<PLL_MISC_LFCON_SHIFT)
+#define PLL_MISC_VCOCON_SHIFT           0
+#define PLL_MISC_VCOCON_MASK            (0xF<<PLL_MISC_VCOCON_SHIFT)
+#define PLLU_BASE_POST_DIV              (1<<20)
+#define PLLD_MISC_CLKENABLE             (1<<30)
+#define PLLD_MISC_DIV_RST               (1<<23)
+#define PLLD_MISC_DCCON_SHIFT           12
+#define PLLE_MISC_READY                 (1 << 15)
+#define PERIPH_CLK_TO_ENB_REG(c)        ((c->u.periph.clk_num / 32) * 4)
+#define PERIPH_CLK_TO_ENB_SET_REG(c)    ((c->u.periph.clk_num / 32) * 8)
+#define PERIPH_CLK_TO_ENB_BIT(c)        (1 << (c->u.periph.clk_num % 32))
+#define SUPER_CLK_MUX                   0x00
+#define SUPER_STATE_SHIFT               28
+#define SUPER_STATE_MASK                (0xF << SUPER_STATE_SHIFT)
+#define SUPER_STATE_STANDBY             (0x0 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IDLE                (0x1 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_RUN                 (0x2 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IRQ                 (0x3 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_FIQ                 (0x4 << SUPER_STATE_SHIFT)
+#define SUPER_SOURCE_MASK               0xF
+#define SUPER_FIQ_SOURCE_SHIFT          12
+#define SUPER_IRQ_SOURCE_SHIFT          8
+#define SUPER_RUN_SOURCE_SHIFT          4
+#define SUPER_IDLE_SOURCE_SHIFT         0
+#define SUPER_CLK_DIVIDER               0x04
+#define BUS_CLK_DISABLE                 (1<<3)
+#define BUS_CLK_DIV_MASK                0x3
+#define PMC_CTRL                        0x0
+ #define PMC_CTRL_BLINK_ENB             (1 << 7)
+#define PMC_DPD_PADS_ORIDE              0x1c
+ #define PMC_DPD_PADS_ORIDE_BLINK_ENB   (1 << 20)
+#define PMC_BLINK_TIMER_DATA_ON_SHIFT   0
+#define PMC_BLINK_TIMER_DATA_ON_MASK    0x7fff
+#define PMC_BLINK_TIMER_ENB             (1 << 15)
+#define PMC_BLINK_TIMER_DATA_OFF_SHIFT  16
+#define PMC_BLINK_TIMER_DATA_OFF_MASK   0xffff
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX          0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET      0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR      0x344
+#define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
+#define CPU_RESET(cpu)  (0x1111ul << (cpu))
+static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
+static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+/*
+ * Some clocks share a register with other clocks.  Any clock op that
+ * non-atomically modifies a register used by another clock must lock
+ * clock_register_lock first.
+ */
+static DEFINE_SPINLOCK(clock_register_lock);
+/*
+ * Some peripheral clocks share an enable bit, so refcount the enable bits
+ * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
+ */
+static int tegra_periph_clk_enable_refcount[3 * 32];
+#define clk_writel(value, reg) \
+        __raw_writel(value, reg_clk_base + (reg))
+#define clk_readl(reg) \
+        __raw_readl(reg_clk_base + (reg))
+#define pmc_writel(value, reg) \
+        __raw_writel(value, reg_pmc_base + (reg))
+#define pmc_readl(reg) \
+        __raw_readl(reg_pmc_base + (reg))
+static unsigned long clk_measure_input_freq(void)
+{
+        u32 clock_autodetect;
+        clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
+        do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
+        clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
+        if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
+                return 12000000;
+        } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
+                return 13000000;
+        } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
+                return 19200000;
+        } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
+                return 26000000;
+        } else {
+                pr_err("%s: Unexpected clock autodetect value %d",
+                                                __func__, clock_autodetect);
+                BUG();
+                return 0;
+        }
+}
+static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
+{
+        s64 divider_u71 = parent_rate * 2;
+        divider_u71 += rate - 1;
+        do_div(divider_u71, rate);
+        if (divider_u71 - 2 < 0)
+                return 0;
+        if (divider_u71 - 2 > 255)
+                return -EINVAL;
+        return divider_u71 - 2;
+}
+static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
+{
+        s64 divider_u16;
+        divider_u16 = parent_rate;
+        divider_u16 += rate - 1;
+        do_div(divider_u16, rate);
+        if (divider_u16 - 1 < 0)
+                return 0;
+        if (divider_u16 - 1 > 0xFFFF)
+                return -EINVAL;
+        return divider_u16 - 1;
+}
+static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        return to_clk_tegra(hw)->fixed_rate;
+}
+struct clk_ops tegra_clk_32k_ops = {
+        .recalc_rate = tegra_clk_fixed_recalc_rate,
+};
+/* clk_m functions */
+static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        if (!to_clk_tegra(hw)->fixed_rate)
+                to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
+        return to_clk_tegra(hw)->fixed_rate;
+}
+static void tegra20_clk_m_init(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 osc_ctrl = clk_readl(OSC_CTRL);
+        u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
+        switch (c->fixed_rate) {
+        case 12000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
+                break;
+        case 13000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
+                break;
+        case 19200000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
+                break;
+        case 26000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
+                break;
+        default:
+                BUG();
+        }
+        clk_writel(auto_clock_control, OSC_CTRL);
+}
+struct clk_ops tegra_clk_m_ops = {
+        .init = tegra20_clk_m_init,
+        .recalc_rate = tegra20_clk_m_recalc_rate,
+};
+/* super clock functions */
+/* "super clocks" on tegra have two-stage muxes and a clock skipping
+ * super divider.  We will ignore the clock skipping divider, since we
+ * can't lower the voltage when using the clock skip, but we can if we
+ * lower the PLL frequency.
+ */
+static int tegra20_super_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        val = clk_readl(c->reg + SUPER_CLK_MUX);
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        c->state = ON;
+        return c->state;
+}
+static int tegra20_super_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
+        return 0;
+}
+static void tegra20_super_clk_disable(struct clk_hw *hw)
+{
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+        /* oops - don't disable the CPU clock! */
+        BUG();
+}
+static u8 tegra20_super_clk_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        int val = clk_readl(c->reg + SUPER_CLK_MUX);
+        int source;
+        int shift;
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+        source = (val >> shift) & SUPER_SOURCE_MASK;
+        return source;
+}
+static int tegra20_super_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg + SUPER_CLK_MUX);
+        int shift;
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+        val &= ~(SUPER_SOURCE_MASK << shift);
+        val |= index << shift;
+        clk_writel(val, c->reg);
+        return 0;
+}
+/* FIX ME: Need to switch parents to change the source PLL rate */
+static unsigned long tegra20_super_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        return prate;
+}
+static long tegra20_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        return *prate;
+}
+static int tegra20_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        return 0;
+}
+struct clk_ops tegra_super_ops = {
+        .is_enabled = tegra20_super_clk_is_enabled,
+        .enable = tegra20_super_clk_enable,
+        .disable = tegra20_super_clk_disable,
+        .set_parent = tegra20_super_clk_set_parent,
+        .get_parent = tegra20_super_clk_get_parent,
+        .set_rate = tegra20_super_clk_set_rate,
+        .round_rate = tegra20_super_clk_round_rate,
+        .recalc_rate = tegra20_super_clk_recalc_rate,
+};
+static unsigned long tegra20_twd_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+struct clk_ops tegra_twd_ops = {
+        .recalc_rate = tegra20_twd_clk_recalc_rate,
+};
+static u8 tegra20_cop_clk_get_parent(struct clk_hw *hw)
+{
+        return 0;
+}
+struct clk_ops tegra_cop_ops = {
+        .get_parent = tegra20_cop_clk_get_parent,
+};
+/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
+ * reset the COP block (i.e. AVP) */
+void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert)
+{
+        unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
+        pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
+        clk_writel(1 << 1, reg);
+}
+/* bus clock functions */
+static int tegra20_bus_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
+        return c->state;
+}
+static int tegra20_bus_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 val;
+        spin_lock_irqsave(&clock_register_lock, flags);
+        val = clk_readl(c->reg);
+        val &= ~(BUS_CLK_DISABLE << c->reg_shift);
+        clk_writel(val, c->reg);
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+        return 0;
+}
+static void tegra20_bus_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 val;
+        spin_lock_irqsave(&clock_register_lock, flags);
+        val = clk_readl(c->reg);
+        val |= BUS_CLK_DISABLE << c->reg_shift;
+        clk_writel(val, c->reg);
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+}
+static unsigned long tegra20_bus_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        u64 rate = prate;
+        c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
+        c->mul = 1;
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+static int tegra20_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        int ret = -EINVAL;
+        unsigned long flags;
+        u32 val;
+        int i;
+        spin_lock_irqsave(&clock_register_lock, flags);
+        val = clk_readl(c->reg);
+        for (i = 1; i <= 4; i++) {
+                if (rate == parent_rate / i) {
+                        val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
+                        val |= (i - 1) << c->reg_shift;
+                        clk_writel(val, c->reg);
+                        c->div = i;
+                        c->mul = 1;
+                        ret = 0;
+                        break;
+                }
+        }
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+        return ret;
+}
+static long tegra20_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        unsigned long parent_rate = *prate;
+        s64 divider;
+        if (rate >= parent_rate)
+                return rate;
+        divider = parent_rate;
+        divider += rate - 1;
+        do_div(divider, rate);
+        if (divider < 0)
+                return divider;
+        if (divider > 4)
+                divider = 4;
+        do_div(parent_rate, divider);
+        return parent_rate;
+}
+struct clk_ops tegra_bus_ops = {
+        .is_enabled = tegra20_bus_clk_is_enabled,
+        .enable = tegra20_bus_clk_enable,
+        .disable = tegra20_bus_clk_disable,
+        .set_rate = tegra20_bus_clk_set_rate,
+        .round_rate = tegra20_bus_clk_round_rate,
+        .recalc_rate = tegra20_bus_clk_recalc_rate,
+};
+/* Blink output functions */
+static int tegra20_blink_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        val = pmc_readl(PMC_CTRL);
+        c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
+        return c->state;
+}
+static unsigned long tegra20_blink_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = prate;
+        u32 val;
+        c->mul = 1;
+        val = pmc_readl(c->reg);
+        if (val & PMC_BLINK_TIMER_ENB) {
+                unsigned int on_off;
+                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
+                        PMC_BLINK_TIMER_DATA_ON_MASK;
+                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+                on_off += val;
+                /* each tick in the blink timer is 4 32KHz clocks */
+                c->div = on_off * 4;
+        } else {
+                c->div = 1;
+        }
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+static int tegra20_blink_clk_enable(struct clk_hw *hw)
+{
+        u32 val;
+        val = pmc_readl(PMC_DPD_PADS_ORIDE);
+        pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
+        val = pmc_readl(PMC_CTRL);
+        pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
+        return 0;
+}
+static void tegra20_blink_clk_disable(struct clk_hw *hw)
+{
+        u32 val;
+        val = pmc_readl(PMC_CTRL);
+        pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
+        val = pmc_readl(PMC_DPD_PADS_ORIDE);
+        pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
+}
+static int tegra20_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        if (rate >= parent_rate) {
+                c->div = 1;
+                pmc_writel(0, c->reg);
+        } else {
+                unsigned int on_off;
+                u32 val;
+                on_off = DIV_ROUND_UP(parent_rate / 8, rate);
+                c->div = on_off * 8;
+                val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
+                        PMC_BLINK_TIMER_DATA_ON_SHIFT;
+                on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+                on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+                val |= on_off;
+                val |= PMC_BLINK_TIMER_ENB;
+                pmc_writel(val, c->reg);
+        }
+        return 0;
+}
+static long tegra20_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        int div;
+        int mul;
+        long round_rate = *prate;
+        mul = 1;
+        if (rate >= *prate) {
+                div = 1;
+        } else {
+                div = DIV_ROUND_UP(*prate / 8, rate);
+                div *= 8;
+        }
+        round_rate *= mul;
+        round_rate += div - 1;
+        do_div(round_rate, div);
+        return round_rate;
+}
+struct clk_ops tegra_blink_clk_ops = {
+        .is_enabled = tegra20_blink_clk_is_enabled,
+        .enable = tegra20_blink_clk_enable,
+        .disable = tegra20_blink_clk_disable,
+        .set_rate = tegra20_blink_clk_set_rate,
+        .round_rate = tegra20_blink_clk_round_rate,
+        .recalc_rate = tegra20_blink_clk_recalc_rate,
+};
+/* PLL Functions */
+static int tegra20_pll_clk_wait_for_lock(struct clk_tegra *c)
+{
+        udelay(c->u.pll.lock_delay);
+        return 0;
+}
+static int tegra20_pll_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg + PLL_BASE);
+        c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+        return c->state;
+}
+static unsigned long tegra20_pll_clk_recalc_rate(struct clk_hw *hw,
+                                unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg + PLL_BASE);
+        u64 rate = prate;
+        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
+                const struct clk_pll_freq_table *sel;
+                for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                        if (sel->input_rate == prate &&
+                                sel->output_rate == c->u.pll.fixed_rate) {
+                                c->mul = sel->n;
+                                c->div = sel->m * sel->p;
+                                break;
+                        }
+                }
+                pr_err("Clock %s has unknown fixed frequency\n",
+                        __clk_get_name(hw->clk));
+                BUG();
+        } else if (val & PLL_BASE_BYPASS) {
+                c->mul = 1;
+                c->div = 1;
+        } else {
+                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+                if (c->flags & PLLU)
+                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
+                else
+                        c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
+        }
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+static int tegra20_pll_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+        val = clk_readl(c->reg + PLL_BASE);
+        val &= ~PLL_BASE_BYPASS;
+        val |= PLL_BASE_ENABLE;
+        clk_writel(val, c->reg + PLL_BASE);
+        tegra20_pll_clk_wait_for_lock(c);
+        return 0;
+}
+static void tegra20_pll_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+        val = clk_readl(c->reg);
+        val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+        clk_writel(val, c->reg);
+}
+static int tegra20_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long input_rate = parent_rate;
+        const struct clk_pll_freq_table *sel;
+        u32 val;
+        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+        if (c->flags & PLL_FIXED) {
+                int ret = 0;
+                if (rate != c->u.pll.fixed_rate) {
+                        pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
+                                __func__, __clk_get_name(hw->clk),
+                                c->u.pll.fixed_rate, rate);
+                        ret = -EINVAL;
+                }
+                return ret;
+        }
+        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                if (sel->input_rate == input_rate && sel->output_rate == rate) {
+                        c->mul = sel->n;
+                        c->div = sel->m * sel->p;
+                        val = clk_readl(c->reg + PLL_BASE);
+                        if (c->flags & PLL_FIXED)
+                                val |= PLL_BASE_OVERRIDE;
+                        val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
+                                 PLL_BASE_DIVM_MASK);
+                        val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
+                                (sel->n << PLL_BASE_DIVN_SHIFT);
+                        BUG_ON(sel->p < 1 || sel->p > 2);
+                        if (c->flags & PLLU) {
+                                if (sel->p == 1)
+                                        val |= PLLU_BASE_POST_DIV;
+                        } else {
+                                if (sel->p == 2)
+                                        val |= 1 << PLL_BASE_DIVP_SHIFT;
+                        }
+                        clk_writel(val, c->reg + PLL_BASE);
+                        if (c->flags & PLL_HAS_CPCON) {
+                                val = clk_readl(c->reg + PLL_MISC(c));
+                                val &= ~PLL_MISC_CPCON_MASK;
+                                val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
+                                clk_writel(val, c->reg + PLL_MISC(c));
+                        }
+                        if (c->state == ON)
+                                tegra20_pll_clk_enable(hw);
+                        return 0;
+                }
+        }
+        return -EINVAL;
+}
+static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        const struct clk_pll_freq_table *sel;
+        unsigned long input_rate = *prate;
+        u64 output_rate = *prate;
+        int mul;
+        int div;
+        if (c->flags & PLL_FIXED)
+                return c->u.pll.fixed_rate;
+        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++)
+                if (sel->input_rate == input_rate && sel->output_rate == rate) {
+                        mul = sel->n;
+                        div = sel->m * sel->p;
+                        break;
+                }
+        if (sel->input_rate == 0)
+                return -EINVAL;
+        output_rate *= mul;
+        output_rate += div - 1; /* round up */
+        do_div(output_rate, div);
+        return output_rate;
+}
+struct clk_ops tegra_pll_ops = {
+        .is_enabled = tegra20_pll_clk_is_enabled,
+        .enable = tegra20_pll_clk_enable,
+        .disable = tegra20_pll_clk_disable,
+        .set_rate = tegra20_pll_clk_set_rate,
+        .recalc_rate = tegra20_pll_clk_recalc_rate,
+        .round_rate = tegra20_pll_clk_round_rate,
+};
+static void tegra20_pllx_clk_init(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        if (tegra_sku_id == 7)
+                c->max_rate = 750000000;
+}
+struct clk_ops tegra_pllx_ops = {
+        .init = tegra20_pllx_clk_init,
+        .is_enabled = tegra20_pll_clk_is_enabled,
+        .enable = tegra20_pll_clk_enable,
+        .disable = tegra20_pll_clk_disable,
+        .set_rate = tegra20_pll_clk_set_rate,
+        .recalc_rate = tegra20_pll_clk_recalc_rate,
+        .round_rate = tegra20_pll_clk_round_rate,
+};
+static int tegra20_plle_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+        mdelay(1);
+        val = clk_readl(c->reg + PLL_BASE);
+        if (!(val & PLLE_MISC_READY))
+                return -EBUSY;
+        val = clk_readl(c->reg + PLL_BASE);
+        val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
+        clk_writel(val, c->reg + PLL_BASE);
+        return 0;
+}
+struct clk_ops tegra_plle_ops = {
+        .is_enabled = tegra20_pll_clk_is_enabled,
+        .enable = tegra20_plle_clk_enable,
+        .set_rate = tegra20_pll_clk_set_rate,
+        .recalc_rate = tegra20_pll_clk_recalc_rate,
+        .round_rate = tegra20_pll_clk_round_rate,
+};
+/* Clock divider ops */
+static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        val >>= c->reg_shift;
+        c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
+        if (!(val & PLL_OUT_RESET_DISABLE))
+                c->state = OFF;
+        return c->state;
+}
+static unsigned long tegra20_pll_div_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = prate;
+        u32 val = clk_readl(c->reg);
+        u32 divu71;
+        val >>= c->reg_shift;
+        if (c->flags & DIV_U71) {
+                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
+                c->div = (divu71 + 2);
+                c->mul = 2;
+        } else if (c->flags & DIV_2) {
+                c->div = 2;
+                c->mul = 1;
+        } else {
+                c->div = 1;
+                c->mul = 1;
+        }
+        rate *= c->mul;
+        rate += c->div - 1; /* round up */
+        do_div(rate, c->div);
+        return rate;
+}
+static int tegra20_pll_div_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 new_val;
+        u32 val;
+        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
+        if (c->flags & DIV_U71) {
+                spin_lock_irqsave(&clock_register_lock, flags);
+                val = clk_readl(c->reg);
+                new_val = val >> c->reg_shift;
+                new_val &= 0xFFFF;
+                new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
+                val &= ~(0xFFFF << c->reg_shift);
+                val |= new_val << c->reg_shift;
+                clk_writel(val, c->reg);
+                spin_unlock_irqrestore(&clock_register_lock, flags);
+                return 0;
+        } else if (c->flags & DIV_2) {
+                BUG_ON(!(c->flags & PLLD));
+                spin_lock_irqsave(&clock_register_lock, flags);
+                val = clk_readl(c->reg);
+                val &= ~PLLD_MISC_DIV_RST;
+                clk_writel(val, c->reg);
+                spin_unlock_irqrestore(&clock_register_lock, flags);
+                return 0;
+        }
+        return -EINVAL;
+}
+static void tegra20_pll_div_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 new_val;
+        u32 val;
+        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
+        if (c->flags & DIV_U71) {
+                spin_lock_irqsave(&clock_register_lock, flags);
+                val = clk_readl(c->reg);
+                new_val = val >> c->reg_shift;
+                new_val &= 0xFFFF;
+                new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
+                val &= ~(0xFFFF << c->reg_shift);
+                val |= new_val << c->reg_shift;
+                clk_writel(val, c->reg);
+                spin_unlock_irqrestore(&clock_register_lock, flags);
+        } else if (c->flags & DIV_2) {
+                BUG_ON(!(c->flags & PLLD));
+                spin_lock_irqsave(&clock_register_lock, flags);
+                val = clk_readl(c->reg);
+                val |= PLLD_MISC_DIV_RST;
+                clk_writel(val, c->reg);
+                spin_unlock_irqrestore(&clock_register_lock, flags);
+        }
+}
+static int tegra20_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        int divider_u71;
+        u32 new_val;
+        u32 val;
+        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+        if (c->flags & DIV_U71) {
+                divider_u71 = clk_div71_get_divider(parent_rate, rate);
+                if (divider_u71 >= 0) {
+                        spin_lock_irqsave(&clock_register_lock, flags);
+                        val = clk_readl(c->reg);
+                        new_val = val >> c->reg_shift;
+                        new_val &= 0xFFFF;
+                        if (c->flags & DIV_U71_FIXED)
+                                new_val |= PLL_OUT_OVERRIDE;
+                        new_val &= ~PLL_OUT_RATIO_MASK;
+                        new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
+                        val &= ~(0xFFFF << c->reg_shift);
+                        val |= new_val << c->reg_shift;
+                        clk_writel(val, c->reg);
+                        c->div = divider_u71 + 2;
+                        c->mul = 2;
+                        spin_unlock_irqrestore(&clock_register_lock, flags);
+                        return 0;
+                }
+        } else if (c->flags & DIV_2) {
+                if (parent_rate == rate * 2)
+                        return 0;
+        }
+        return -EINVAL;
+}
+static long tegra20_pll_div_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long parent_rate = *prate;
+        int divider;
+        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(parent_rate, rate);
+                if (divider < 0)
+                        return divider;
+                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
+        } else if (c->flags & DIV_2) {
+                return DIV_ROUND_UP(parent_rate, 2);
+        }
+        return -EINVAL;
+}
+struct clk_ops tegra_pll_div_ops = {
+        .is_enabled = tegra20_pll_div_clk_is_enabled,
+        .enable = tegra20_pll_div_clk_enable,
+        .disable = tegra20_pll_div_clk_disable,
+        .set_rate = tegra20_pll_div_clk_set_rate,
+        .round_rate = tegra20_pll_div_clk_round_rate,
+        .recalc_rate = tegra20_pll_div_clk_recalc_rate,
+};
+/* Periph clk ops */
+static int tegra20_periph_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        c->state = ON;
+        if (!c->u.periph.clk_num)
+                goto out;
+        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+                        PERIPH_CLK_TO_ENB_BIT(c)))
+                c->state = OFF;
+        if (!(c->flags & PERIPH_NO_RESET))
+                if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
+                                PERIPH_CLK_TO_ENB_BIT(c))
+                        c->state = OFF;
+out:
+        return c->state;
+}
+static int tegra20_periph_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 val;
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+        if (!c->u.periph.clk_num)
+                return 0;
+        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
+        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
+                return 0;
+        spin_lock_irqsave(&clock_register_lock, flags);
+        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
+        if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
+                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                        RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+        if (c->flags & PERIPH_EMC_ENB) {
+                /* The EMC peripheral clock has 2 extra enable bits */
+                /* FIXME: Do they need to be disabled? */
+                val = clk_readl(c->reg);
+                val |= 0x3 << 24;
+                clk_writel(val, c->reg);
+        }
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+        return 0;
+}
+static void tegra20_periph_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+        if (!c->u.periph.clk_num)
+                return;
+        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
+        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
+                return;
+        spin_lock_irqsave(&clock_register_lock, flags);
+        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+}
+void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
+        pr_debug("%s %s on clock %s\n", __func__,
+                assert ? "assert" : "deassert", __clk_get_name(hw->clk));
+        BUG_ON(!c->u.periph.clk_num);
+        if (!(c->flags & PERIPH_NO_RESET))
+                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                           base + PERIPH_CLK_TO_ENB_SET_REG(c));
+}
+static int tegra20_periph_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        u32 mask;
+        u32 shift;
+        pr_debug("%s: %s %d\n", __func__, __clk_get_name(hw->clk), index);
+        if (c->flags & MUX_PWM) {
+                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+                mask = PERIPH_CLK_SOURCE_PWM_MASK;
+        } else {
+                shift = PERIPH_CLK_SOURCE_SHIFT;
+                mask = PERIPH_CLK_SOURCE_MASK;
+        }
+        val = clk_readl(c->reg);
+        val &= ~mask;
+        val |= (index) << shift;
+        clk_writel(val, c->reg);
+        return 0;
+}
+static u8 tegra20_periph_clk_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        u32 mask;
+        u32 shift;
+        if (c->flags & MUX_PWM) {
+                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+                mask = PERIPH_CLK_SOURCE_PWM_MASK;
+        } else {
+                shift = PERIPH_CLK_SOURCE_SHIFT;
+                mask = PERIPH_CLK_SOURCE_MASK;
+        }
+        if (c->flags & MUX)
+                return (val & mask) >> shift;
+        else
+                return 0;
+}
+static unsigned long tegra20_periph_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long rate = prate;
+        u32 val = clk_readl(c->reg);
+        if (c->flags & DIV_U71) {
+                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
+                c->div = divu71 + 2;
+                c->mul = 2;
+        } else if (c->flags & DIV_U16) {
+                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
+                c->div = divu16 + 1;
+                c->mul = 1;
+        } else {
+                c->div = 1;
+                c->mul = 1;
+                return rate;
+        }
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+static int tegra20_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        int divider;
+        val = clk_readl(c->reg);
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(parent_rate, rate);
+                if (divider >= 0) {
+                        val = clk_readl(c->reg);
+                        val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
+                        val |= divider;
+                        clk_writel(val, c->reg);
+                        c->div = divider + 2;
+                        c->mul = 2;
+                        return 0;
+                }
+        } else if (c->flags & DIV_U16) {
+                divider = clk_div16_get_divider(parent_rate, rate);
+                if (divider >= 0) {
+                        val = clk_readl(c->reg);
+                        val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
+                        val |= divider;
+                        clk_writel(val, c->reg);
+                        c->div = divider + 1;
+                        c->mul = 1;
+                        return 0;
+                }
+        } else if (parent_rate <= rate) {
+                c->div = 1;
+                c->mul = 1;
+                return 0;
+        }
+        return -EINVAL;
+}
+static long tegra20_periph_clk_round_rate(struct clk_hw *hw,
+        unsigned long rate, unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
+        int divider;
+        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+        if (prate)
+                parent_rate = *prate;
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(parent_rate, rate);
+                if (divider < 0)
+                        return divider;
+                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
+        } else if (c->flags & DIV_U16) {
+                divider = clk_div16_get_divider(parent_rate, rate);
+                if (divider < 0)
+                        return divider;
+                return DIV_ROUND_UP(parent_rate, divider + 1);
+        }
+        return -EINVAL;
+}
+struct clk_ops tegra_periph_clk_ops = {
+        .is_enabled = tegra20_periph_clk_is_enabled,
+        .enable = tegra20_periph_clk_enable,
+        .disable = tegra20_periph_clk_disable,
+        .set_parent = tegra20_periph_clk_set_parent,
+        .get_parent = tegra20_periph_clk_get_parent,
+        .set_rate = tegra20_periph_clk_set_rate,
+        .round_rate = tegra20_periph_clk_round_rate,
+        .recalc_rate = tegra20_periph_clk_recalc_rate,
+};
+/* External memory controller clock ops */
+static void tegra20_emc_clk_init(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        c->max_rate = __clk_get_rate(hw->clk);
+}
+static long tegra20_emc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        long emc_rate;
+        long clk_rate;
+        /*
+         * The slowest entry in the EMC clock table that is at least as
+         * fast as rate.
+         */
+        emc_rate = tegra_emc_round_rate(rate);
+        if (emc_rate < 0)
+                return c->max_rate;
+        /*
+         * The fastest rate the PLL will generate that is at most the
+         * requested rate.
+         */
+        clk_rate = tegra20_periph_clk_round_rate(hw, emc_rate, NULL);
+        /*
+         * If this fails, and emc_rate > clk_rate, it's because the maximum
+         * rate in the EMC tables is larger than the maximum rate of the EMC
+         * clock. The EMC clock's max rate is the rate it was running when the
+         * kernel booted. Such a mismatch is probably due to using the wrong
+         * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
+         */
+        WARN_ONCE(emc_rate != clk_rate,
+                "emc_rate %ld != clk_rate %ld",
+                emc_rate, clk_rate);
+        return emc_rate;
+}
+static int tegra20_emc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        int ret;
+        /*
+         * The Tegra2 memory controller has an interlock with the clock
+         * block that allows memory shadowed registers to be updated,
+         * and then transfer them to the main registers at the same
+         * time as the clock update without glitches.
+         */
+        ret = tegra_emc_set_rate(rate);
+        if (ret < 0)
+                return ret;
+        ret = tegra20_periph_clk_set_rate(hw, rate, parent_rate);
+        udelay(1);
+        return ret;
+}
+struct clk_ops tegra_emc_clk_ops = {
+        .init = tegra20_emc_clk_init,
+        .is_enabled = tegra20_periph_clk_is_enabled,
+        .enable = tegra20_periph_clk_enable,
+        .disable = tegra20_periph_clk_disable,
+        .set_parent = tegra20_periph_clk_set_parent,
+        .get_parent = tegra20_periph_clk_get_parent,
+        .set_rate = tegra20_emc_clk_set_rate,
+        .round_rate = tegra20_emc_clk_round_rate,
+        .recalc_rate = tegra20_periph_clk_recalc_rate,
+};
+/* Clock doubler ops */
+static int tegra20_clk_double_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        c->state = ON;
+        if (!c->u.periph.clk_num)
+                goto out;
+        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+                        PERIPH_CLK_TO_ENB_BIT(c)))
+                c->state = OFF;
+out:
+        return c->state;
+};
+static unsigned long tegra20_clk_double_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = prate;
+        c->mul = 2;
+        c->div = 1;
+        rate *= c->mul;
+        rate += c->div - 1; /* round up */
+        do_div(rate, c->div);
+        return rate;
+}
+static long tegra20_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        unsigned long output_rate = *prate;
+        do_div(output_rate, 2);
+        return output_rate;
+}
+static int tegra20_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        if (rate != 2 * parent_rate)
+                return -EINVAL;
+        return 0;
+}
+struct clk_ops tegra_clk_double_ops = {
+        .is_enabled = tegra20_clk_double_is_enabled,
+        .enable = tegra20_periph_clk_enable,
+        .disable = tegra20_periph_clk_disable,
+        .set_rate = tegra20_clk_double_set_rate,
+        .recalc_rate = tegra20_clk_double_recalc_rate,
+        .round_rate = tegra20_clk_double_round_rate,
+};
+/* Audio sync clock ops */
+static int tegra20_audio_sync_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        c->state = (val & (1<<4)) ? OFF : ON;
+        return c->state;
+}
+static int tegra20_audio_sync_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        clk_writel(0, c->reg);
+        return 0;
+}
+static void tegra20_audio_sync_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        clk_writel(1, c->reg);
+}
+static u8 tegra20_audio_sync_clk_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        int source;
+        source = val & 0xf;
+        return source;
+}
+static int tegra20_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        val = clk_readl(c->reg);
+        val &= ~0xf;
+        val |= index;
+        clk_writel(val, c->reg);
+        return 0;
+}
+struct clk_ops tegra_audio_sync_clk_ops = {
+        .is_enabled = tegra20_audio_sync_clk_is_enabled,
+        .enable = tegra20_audio_sync_clk_enable,
+        .disable = tegra20_audio_sync_clk_disable,
+        .set_parent = tegra20_audio_sync_clk_set_parent,
+        .get_parent = tegra20_audio_sync_clk_get_parent,
+};
+/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
+static int tegra20_cdev_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
+         * currently done in the pinmux code. */
+        c->state = ON;
+        BUG_ON(!c->u.periph.clk_num);
+        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+                        PERIPH_CLK_TO_ENB_BIT(c)))
+                c->state = OFF;
+        return c->state;
+}
+static int tegra20_cdev_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        BUG_ON(!c->u.periph.clk_num);
+        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
+        return 0;
+}
+static void tegra20_cdev_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        BUG_ON(!c->u.periph.clk_num);
+        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+}
+static unsigned long tegra20_cdev_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        return to_clk_tegra(hw)->fixed_rate;
+}
+struct clk_ops tegra_cdev_clk_ops = {
+        .is_enabled = tegra20_cdev_clk_is_enabled,
+        .enable = tegra20_cdev_clk_enable,
+        .disable = tegra20_cdev_clk_disable,
+        .recalc_rate = tegra20_cdev_recalc_rate,
+};
+/* Tegra20 CPU clock and reset control functions */
+static void tegra20_wait_cpu_in_reset(u32 cpu)
+{
+        unsigned int reg;
+        do {
+                reg = readl(reg_clk_base +
+                            TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+                cpu_relax();
+        } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
+        return;
+}
+static void tegra20_put_cpu_in_reset(u32 cpu)
+{
+        writel(CPU_RESET(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+        dmb();
+}
+static void tegra20_cpu_out_of_reset(u32 cpu)
+{
+        writel(CPU_RESET(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+        wmb();
+}
+static void tegra20_enable_cpu_clock(u32 cpu)
+{
+        unsigned int reg;
+        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        writel(reg & ~CPU_CLOCK(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        barrier();
+        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+static void tegra20_disable_cpu_clock(u32 cpu)
+{
+        unsigned int reg;
+        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        writel(reg | CPU_CLOCK(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
+        .wait_for_reset = tegra20_wait_cpu_in_reset,
+        .put_in_reset   = tegra20_put_cpu_in_reset,
+        .out_of_reset   = tegra20_cpu_out_of_reset,
+        .enable_clock   = tegra20_enable_cpu_clock,
+        .disable_clock  = tegra20_disable_cpu_clock,
+};
+void __init tegra20_cpu_car_ops_init(void)
+{
+        tegra_cpu_car_ops = &tegra20_cpu_car_ops;
+}
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
new file mode 100644
index 000000000000..8bfd31bcc490
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __MACH_TEGRA20_CLOCK_H
+#define __MACH_TEGRA20_CLOCK_H
+extern struct clk_ops tegra_clk_32k_ops;
+extern struct clk_ops tegra_pll_ops;
+extern struct clk_ops tegra_clk_m_ops;
+extern struct clk_ops tegra_pll_div_ops;
+extern struct clk_ops tegra_pllx_ops;
+extern struct clk_ops tegra_plle_ops;
+extern struct clk_ops tegra_clk_double_ops;
+extern struct clk_ops tegra_cdev_clk_ops;
+extern struct clk_ops tegra_audio_sync_clk_ops;
+extern struct clk_ops tegra_super_ops;
+extern struct clk_ops tegra_cpu_ops;
+extern struct clk_ops tegra_twd_ops;
+extern struct clk_ops tegra_cop_ops;
+extern struct clk_ops tegra_bus_ops;
+extern struct clk_ops tegra_blink_clk_ops;
+extern struct clk_ops tegra_emc_clk_ops;
+extern struct clk_ops tegra_periph_clk_ops;
+extern struct clk_ops tegra_clk_shared_bus_ops;
+void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert);
+void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert);
+#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
new file mode 100644
index 000000000000..cc9b5fd8c3d3
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -0,0 +1,1139 @@
+/*
+ * arch/arm/mach-tegra/tegra2_clocks.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/clk-private.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <mach/iomap.h>
+#include "clock.h"
+#include "fuse.h"
+#include "tegra2_emc.h"
+#include "tegra20_clocks.h"
+#include "tegra_cpu_car.h"
+/* Clock definitions */
+#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,            \
+                   _parent_names, _parents, _parent)            \
+        static struct clk tegra_##_name = {                     \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .name = #_name,                                 \
+                .rate = _rate,                                  \
+                .ops = _ops,                                    \
+                .flags = _flags,                                \
+                .parent_names = _parent_names,                  \
+                .parents = _parents,                            \
+                .num_parents = ARRAY_SIZE(_parent_names),       \
+                .parent = _parent,                              \
+        };
+static struct clk tegra_clk_32k;
+static struct clk_tegra tegra_clk_32k_hw = {
+        .hw = {
+                .clk = &tegra_clk_32k,
+        },
+        .fixed_rate = 32768,
+};
+static struct clk tegra_clk_32k = {
+        .name = "clk_32k",
+        .rate = 32768,
+        .ops = &tegra_clk_32k_ops,
+        .hw = &tegra_clk_32k_hw.hw,
+        .flags = CLK_IS_ROOT,
+};
+static struct clk tegra_clk_m;
+static struct clk_tegra tegra_clk_m_hw = {
+        .hw = {
+                .clk = &tegra_clk_m,
+        },
+        .flags = ENABLE_ON_INIT,
+        .reg = 0x1fc,
+        .reg_shift = 28,
+        .max_rate = 26000000,
+        .fixed_rate = 0,
+};
+static struct clk tegra_clk_m = {
+        .name = "clk_m",
+        .ops = &tegra_clk_m_ops,
+        .hw = &tegra_clk_m_hw.hw,
+        .flags = CLK_IS_ROOT,
+};
+#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min,  \
+                   _input_max, _cf_min, _cf_max, _vco_min,      \
+                   _vco_max, _freq_table, _lock_delay, _ops,    \
+                   _fixed_rate, _parent)                        \
+        static const char *tegra_##_name##_parent_names[] = {   \
+                #_parent,                                       \
+        };                                                      \
+        static struct clk *tegra_##_name##_parents[] = {        \
+                &tegra_##_parent,                               \
+        };                                                      \
+        static struct clk tegra_##_name;                        \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .flags = _flags,                                \
+                .reg = _reg,                                    \
+                .max_rate = _max_rate,                          \
+                .u.pll = {                                      \
+                        .input_min = _input_min,                \
+                        .input_max = _input_max,                \
+                        .cf_min = _cf_min,                      \
+                        .cf_max = _cf_max,                      \
+                        .vco_min = _vco_min,                    \
+                        .vco_max = _vco_max,                    \
+                        .freq_table = _freq_table,              \
+                        .lock_delay = _lock_delay,              \
+                        .fixed_rate = _fixed_rate,              \
+                },                                              \
+        };                                                      \
+        static struct clk tegra_##_name = {                     \
+                .name = #_name,                                 \
+                .ops = &_ops,                                   \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .parent = &tegra_##_parent,                     \
+                .parent_names = tegra_##_name##_parent_names,   \
+                .parents = tegra_##_name##_parents,             \
+                .num_parents = 1,                               \
+        };
+#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift,         \
+                _max_rate, _ops, _parent, _clk_flags)           \
+        static const char *tegra_##_name##_parent_names[] = {   \
+                #_parent,                                       \
+        };                                                      \
+        static struct clk *tegra_##_name##_parents[] = {        \
+                &tegra_##_parent,                               \
+        };                                                      \
+        static struct clk tegra_##_name;                        \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .flags = _flags,                                \
+                .reg = _reg,                                    \
+                .max_rate = _max_rate,                          \
+                .reg_shift = _reg_shift,                        \
+        };                                                      \
+        static struct clk tegra_##_name = {                     \
+                .name = #_name,                                 \
+                .ops = &tegra_pll_div_ops,                      \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .parent = &tegra_##_parent,                     \
+                .parent_names = tegra_##_name##_parent_names,   \
+                .parents = tegra_##_name##_parents,             \
+                .num_parents = 1,                               \
+                .flags = _clk_flags,                            \
+        };
+static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
+        {32768, 12000000, 366, 1, 1, 0},
+        {32768, 13000000, 397, 1, 1, 0},
+        {32768, 19200000, 586, 1, 1, 0},
+        {32768, 26000000, 793, 1, 1, 0},
+        {0, 0, 0, 0, 0, 0},
+};
+DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0,
+                0, 12000000, 26000000, tegra_pll_s_freq_table, 300,
+                tegra_pll_ops, 0, clk_32k);
+static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+        { 12000000, 600000000, 600, 12, 1, 8 },
+        { 13000000, 600000000, 600, 13, 1, 8 },
+        { 19200000, 600000000, 500, 16, 1, 6 },
+        { 26000000, 600000000, 600, 26, 1, 8 },
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
+                tegra_pll_ops, 0, clk_m);
+DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000,
+                tegra_pll_div_ops, pll_c, 0);
+static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
+        { 12000000, 666000000, 666, 12, 1, 8},
+        { 13000000, 666000000, 666, 13, 1, 8},
+        { 19200000, 666000000, 555, 16, 1, 8},
+        { 26000000, 666000000, 666, 26, 1, 8},
+        { 12000000, 600000000, 600, 12, 1, 8},
+        { 13000000, 600000000, 600, 13, 1, 8},
+        { 19200000, 600000000, 375, 12, 1, 6},
+        { 26000000, 600000000, 600, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300,
+                tegra_pll_ops, 0, clk_m);
+DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
+                tegra_pll_div_ops, pll_m, 0);
+static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
+        { 12000000, 216000000, 432, 12, 2, 8},
+        { 13000000, 216000000, 432, 13, 2, 8},
+        { 19200000, 216000000, 90,   4, 2, 1},
+        { 26000000, 216000000, 432, 26, 2, 8},
+        { 12000000, 432000000, 432, 12, 1, 8},
+        { 13000000, 432000000, 432, 13, 1, 8},
+        { 19200000, 432000000, 90,   4, 1, 1},
+        { 26000000, 432000000, 432, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
+                2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
+                tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m);
+DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0,
+                432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16,
+                432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0,
+                432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16,
+                432000000, tegra_pll_div_ops, pll_p, 0);
+static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
+        { 28800000, 56448000, 49, 25, 1, 1},
+        { 28800000, 73728000, 64, 25, 1, 1},
+        { 28800000, 24000000,  5,  6, 1, 1},
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300,
+                tegra_pll_ops, 0, pll_p_out1);
+DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
+                tegra_pll_div_ops, pll_a, 0);
+static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
+        { 12000000, 216000000, 216, 12, 1, 4},
+        { 13000000, 216000000, 216, 13, 1, 4},
+        { 19200000, 216000000, 135, 12, 1, 3},
+        { 26000000, 216000000, 216, 26, 1, 4},
+        { 12000000, 594000000, 594, 12, 1, 8},
+        { 13000000, 594000000, 594, 13, 1, 8},
+        { 19200000, 594000000, 495, 16, 1, 8},
+        { 26000000, 594000000, 594, 26, 1, 8},
+        { 12000000, 1000000000, 1000, 12, 1, 12},
+        { 13000000, 1000000000, 1000, 13, 1, 12},
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 12},
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
+                1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
+                1000, tegra_pll_ops, 0, clk_m);
+DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
+                tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
+static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
+        { 12000000, 480000000, 960, 12, 2, 0},
+        { 13000000, 480000000, 960, 13, 2, 0},
+        { 19200000, 480000000, 200, 4,  2, 0},
+        { 26000000, 480000000, 960, 26, 2, 0},
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000,
+                48000000, 960000000, tegra_pll_u_freq_table, 1000,
+                tegra_pll_ops, 0, clk_m);
+static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+        /* 1 GHz */
+        { 12000000, 1000000000, 1000, 12, 1, 12},
+        { 13000000, 1000000000, 1000, 13, 1, 12},
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 12},
+        /* 912 MHz */
+        { 12000000, 912000000,  912,  12, 1, 12},
+        { 13000000, 912000000,  912,  13, 1, 12},
+        { 19200000, 912000000,  760,  16, 1, 8},
+        { 26000000, 912000000,  912,  26, 1, 12},
+        /* 816 MHz */
+        { 12000000, 816000000,  816,  12, 1, 12},
+        { 13000000, 816000000,  816,  13, 1, 12},
+        { 19200000, 816000000,  680,  16, 1, 8},
+        { 26000000, 816000000,  816,  26, 1, 12},
+        /* 760 MHz */
+        { 12000000, 760000000,  760,  12, 1, 12},
+        { 13000000, 760000000,  760,  13, 1, 12},
+        { 19200000, 760000000,  950,  24, 1, 8},
+        { 26000000, 760000000,  760,  26, 1, 12},
+        /* 750 MHz */
+        { 12000000, 750000000,  750,  12, 1, 12},
+        { 13000000, 750000000,  750,  13, 1, 12},
+        { 19200000, 750000000,  625,  16, 1, 8},
+        { 26000000, 750000000,  750,  26, 1, 12},
+        /* 608 MHz */
+        { 12000000, 608000000,  608,  12, 1, 12},
+        { 13000000, 608000000,  608,  13, 1, 12},
+        { 19200000, 608000000,  380,  12, 1, 8},
+        { 26000000, 608000000,  608,  26, 1, 12},
+        /* 456 MHz */
+        { 12000000, 456000000,  456,  12, 1, 12},
+        { 13000000, 456000000,  456,  13, 1, 12},
+        { 19200000, 456000000,  380,  16, 1, 8},
+        { 26000000, 456000000,  456,  26, 1, 12},
+        /* 312 MHz */
+        { 12000000, 312000000,  312,  12, 1, 12},
+        { 13000000, 312000000,  312,  13, 1, 12},
+        { 19200000, 312000000,  260,  16, 1, 8},
+        { 26000000, 312000000,  312,  26, 1, 12},
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000,
+                31000000, 1000000, 6000000, 20000000, 1200000000,
+                tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m);
+static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
+        { 12000000, 100000000,  200,  24, 1, 0 },
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0,
+                0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m);
+static const char *tegra_common_parent_names[] = {
+        "clk_m",
+};
+static struct clk *tegra_common_parents[] = {
+        &tegra_clk_m,
+};
+static struct clk tegra_clk_d;
+static struct clk_tegra tegra_clk_d_hw = {
+        .hw = {
+                .clk = &tegra_clk_d,
+        },
+        .flags = PERIPH_NO_RESET,
+        .reg = 0x34,
+        .reg_shift = 12,
+        .max_rate = 52000000,
+        .u.periph = {
+                .clk_num = 90,
+        },
+};
+static struct clk tegra_clk_d = {
+        .name = "clk_d",
+        .hw = &tegra_clk_d_hw.hw,
+        .ops = &tegra_clk_double_ops,
+        .parent = &tegra_clk_m,
+        .parent_names = tegra_common_parent_names,
+        .parents = tegra_common_parents,
+        .num_parents = ARRAY_SIZE(tegra_common_parent_names),
+};
+static struct clk tegra_cdev1;
+static struct clk_tegra tegra_cdev1_hw = {
+        .hw = {
+                .clk = &tegra_cdev1,
+        },
+        .fixed_rate = 26000000,
+        .u.periph = {
+                .clk_num = 94,
+        },
+};
+static struct clk tegra_cdev1 = {
+        .name = "cdev1",
+        .hw = &tegra_cdev1_hw.hw,
+        .ops = &tegra_cdev_clk_ops,
+        .flags = CLK_IS_ROOT,
+};
+/* dap_mclk2, belongs to the cdev2 pingroup. */
+static struct clk tegra_cdev2;
+static struct clk_tegra tegra_cdev2_hw = {
+        .hw = {
+                .clk = &tegra_cdev2,
+        },
+        .fixed_rate = 26000000,
+        .u.periph = {
+                .clk_num  = 93,
+        },
+};
+static struct clk tegra_cdev2 = {
+        .name = "cdev2",
+        .hw = &tegra_cdev2_hw.hw,
+        .ops = &tegra_cdev_clk_ops,
+        .flags = CLK_IS_ROOT,
+};
+/* initialized before peripheral clocks */
+static struct clk_mux_sel mux_audio_sync_clk[8+1];
+static const struct audio_sources {
+        const char *name;
+        int value;
+} mux_audio_sync_clk_sources[] = {
+        { .name = "spdif_in", .value = 0 },
+        { .name = "i2s1", .value = 1 },
+        { .name = "i2s2", .value = 2 },
+        { .name = "pll_a_out0", .value = 4 },
+#if 0 /* FIXME: not implemented */
+        { .name = "ac97", .value = 3 },
+        { .name = "ext_audio_clk2", .value = 5 },
+        { .name = "ext_audio_clk1", .value = 6 },
+        { .name = "ext_vimclk", .value = 7 },
+#endif
+        { NULL, 0 }
+};
+static const char *audio_parent_names[] = {
+        "spdif_in",
+        "i2s1",
+        "i2s2",
+        "dummy",
+        "pll_a_out0",
+        "dummy",
+        "dummy",
+        "dummy",
+};
+static struct clk *audio_parents[] = {
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+};
+static struct clk tegra_audio;
+static struct clk_tegra tegra_audio_hw = {
+        .hw = {
+                .clk = &tegra_audio,
+        },
+        .reg = 0x38,
+        .max_rate = 73728000,
+};
+DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names,
+                audio_parents, NULL);
+static const char *audio_2x_parent_names[] = {
+        "audio",
+};
+static struct clk *audio_2x_parents[] = {
+        &tegra_audio,
+};
+static struct clk tegra_audio_2x;
+static struct clk_tegra tegra_audio_2x_hw = {
+        .hw = {
+                .clk = &tegra_audio_2x,
+        },
+        .flags = PERIPH_NO_RESET,
+        .max_rate = 48000000,
+        .reg = 0x34,
+        .reg_shift = 8,
+        .u.periph = {
+                .clk_num = 89,
+        },
+};
+DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names,
+                audio_2x_parents, &tegra_audio);
+static struct clk_lookup tegra_audio_clk_lookups[] = {
+        { .con_id = "audio", .clk = &tegra_audio },
+        { .con_id = "audio_2x", .clk = &tegra_audio_2x }
+};
+/* This is called after peripheral clocks are initialized, as the
+ * audio_sync clock depends on some of the peripheral clocks.
+ */
+static void init_audio_sync_clock_mux(void)
+{
+        int i;
+        struct clk_mux_sel *sel = mux_audio_sync_clk;
+        const struct audio_sources *src = mux_audio_sync_clk_sources;
+        struct clk_lookup *lookup;
+        for (i = 0; src->name; i++, sel++, src++) {
+                sel->input = tegra_get_clock_by_name(src->name);
+                if (!sel->input)
+                        pr_err("%s: could not find clk %s\n", __func__,
+                                src->name);
+                audio_parents[src->value] = sel->input;
+                sel->value = src->value;
+        }
+        lookup = tegra_audio_clk_lookups;
+        for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
+                struct clk *c = lookup->clk;
+                struct clk_tegra *clk = to_clk_tegra(c->hw);
+                __clk_init(NULL, c);
+                INIT_LIST_HEAD(&clk->shared_bus_list);
+                clk->lookup.con_id = lookup->con_id;
+                clk->lookup.clk = c;
+                clkdev_add(&clk->lookup);
+                tegra_clk_add(c);
+        }
+}
+static const char *mux_cclk[] = {
+        "clk_m",
+        "pll_c",
+        "clk_32k",
+        "pll_m",
+        "pll_p",
+        "pll_p_out4",
+        "pll_p_out3",
+        "clk_d",
+        "pll_x",
+};
+static struct clk *mux_cclk_p[] = {
+        &tegra_clk_m,
+        &tegra_pll_c,
+        &tegra_clk_32k,
+        &tegra_pll_m,
+        &tegra_pll_p,
+        &tegra_pll_p_out4,
+        &tegra_pll_p_out3,
+        &tegra_clk_d,
+        &tegra_pll_x,
+};
+static const char *mux_sclk[] = {
+        "clk_m",
+        "pll_c_out1",
+        "pll_p_out4",
+        "pllp_p_out3",
+        "pll_p_out2",
+        "clk_d",
+        "clk_32k",
+        "pll_m_out1",
+};
+static struct clk *mux_sclk_p[] = {
+        &tegra_clk_m,
+        &tegra_pll_c_out1,
+        &tegra_pll_p_out4,
+        &tegra_pll_p_out3,
+        &tegra_pll_p_out2,
+        &tegra_clk_d,
+        &tegra_clk_32k,
+        &tegra_pll_m_out1,
+};
+static struct clk tegra_cclk;
+static struct clk_tegra tegra_cclk_hw = {
+        .hw = {
+                .clk = &tegra_cclk,
+        },
+        .reg = 0x20,
+        .max_rate = 1000000000,
+};
+DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
+                mux_cclk_p, NULL);
+static const char *mux_twd[] = {
+        "cclk",
+};
+static struct clk *mux_twd_p[] = {
+        &tegra_cclk,
+};
+static struct clk tegra_clk_twd;
+static struct clk_tegra tegra_clk_twd_hw = {
+        .hw = {
+                .clk = &tegra_clk_twd,
+        },
+        .max_rate = 1000000000,
+        .mul = 1,
+        .div = 4,
+};
+static struct clk tegra_clk_twd = {
+        .name = "twd",
+        .ops = &tegra_twd_ops,
+        .hw = &tegra_clk_twd_hw.hw,
+        .parent = &tegra_cclk,
+        .parent_names = mux_twd,
+        .parents = mux_twd_p,
+        .num_parents = ARRAY_SIZE(mux_twd),
+};
+static struct clk tegra_sclk;
+static struct clk_tegra tegra_sclk_hw = {
+        .hw = {
+                .clk = &tegra_sclk,
+        },
+        .reg = 0x28,
+        .max_rate = 240000000,
+        .min_rate = 120000000,
+};
+DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk,
+                mux_sclk_p, NULL);
+static const char *tegra_cop_parent_names[] = {
+        "tegra_sclk",
+};
+static struct clk *tegra_cop_parents[] = {
+        &tegra_sclk,
+};
+static struct clk tegra_cop;
+static struct clk_tegra tegra_cop_hw = {
+        .hw = {
+                .clk = &tegra_cop,
+        },
+        .max_rate  = 240000000,
+        .reset = &tegra2_cop_clk_reset,
+};
+DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT,
+                tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk);
+static const char *tegra_hclk_parent_names[] = {
+        "tegra_sclk",
+};
+static struct clk *tegra_hclk_parents[] = {
+        &tegra_sclk,
+};
+static struct clk tegra_hclk;
+static struct clk_tegra tegra_hclk_hw = {
+        .hw = {
+                .clk = &tegra_hclk,
+        },
+        .flags = DIV_BUS,
+        .reg = 0x30,
+        .reg_shift = 4,
+        .max_rate = 240000000,
+};
+DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names,
+                tegra_hclk_parents, &tegra_sclk);
+static const char *tegra_pclk_parent_names[] = {
+        "tegra_hclk",
+};
+static struct clk *tegra_pclk_parents[] = {
+        &tegra_hclk,
+};
+static struct clk tegra_pclk;
+static struct clk_tegra tegra_pclk_hw = {
+        .hw = {
+                .clk = &tegra_pclk,
+        },
+        .flags = DIV_BUS,
+        .reg = 0x30,
+        .reg_shift = 0,
+        .max_rate = 120000000,
+};
+DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names,
+                tegra_pclk_parents, &tegra_hclk);
+static const char *tegra_blink_parent_names[] = {
+        "clk_32k",
+};
+static struct clk *tegra_blink_parents[] = {
+        &tegra_clk_32k,
+};
+static struct clk tegra_blink;
+static struct clk_tegra tegra_blink_hw = {
+        .hw = {
+                .clk = &tegra_blink,
+        },
+        .reg = 0x40,
+        .max_rate = 32768,
+};
+DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names,
+                tegra_blink_parents, &tegra_clk_32k);
+static const char *mux_pllm_pllc_pllp_plla[] = {
+        "pll_m",
+        "pll_c",
+        "pll_p",
+        "pll_a_out0",
+};
+static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
+        &tegra_pll_m,
+        &tegra_pll_c,
+        &tegra_pll_p,
+        &tegra_pll_a_out0,
+};
+static const char *mux_pllm_pllc_pllp_clkm[] = {
+        "pll_m",
+        "pll_c",
+        "pll_p",
+        "clk_m",
+};
+static struct clk *mux_pllm_pllc_pllp_clkm_p[] = {
+        &tegra_pll_m,
+        &tegra_pll_c,
+        &tegra_pll_p,
+        &tegra_clk_m,
+};
+static const char *mux_pllp_pllc_pllm_clkm[] = {
+        "pll_p",
+        "pll_c",
+        "pll_m",
+        "clk_m",
+};
+static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_pll_m,
+        &tegra_clk_m,
+};
+static const char *mux_pllaout0_audio2x_pllp_clkm[] = {
+        "pll_a_out0",
+        "audio_2x",
+        "pll_p",
+        "clk_m",
+};
+static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = {
+        &tegra_pll_a_out0,
+        &tegra_audio_2x,
+        &tegra_pll_p,
+        &tegra_clk_m,
+};
+static const char *mux_pllp_plld_pllc_clkm[] = {
+        "pllp",
+        "pll_d_out0",
+        "pll_c",
+        "clk_m",
+};
+static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_d_out0,
+        &tegra_pll_c,
+        &tegra_clk_m,
+};
+static const char *mux_pllp_pllc_audio_clkm_clk32[] = {
+        "pll_p",
+        "pll_c",
+        "audio",
+        "clk_m",
+        "clk_32k",
+};
+static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_audio,
+        &tegra_clk_m,
+        &tegra_clk_32k,
+};
+static const char *mux_pllp_pllc_pllm[] = {
+        "pll_p",
+        "pll_c",
+        "pll_m"
+};
+static struct clk *mux_pllp_pllc_pllm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_pll_m,
+};
+static const char *mux_clk_m[] = {
+        "clk_m",
+};
+static struct clk *mux_clk_m_p[] = {
+        &tegra_clk_m,
+};
+static const char *mux_pllp_out3[] = {
+        "pll_p_out3",
+};
+static struct clk *mux_pllp_out3_p[] = {
+        &tegra_pll_p_out3,
+};
+static const char *mux_plld[] = {
+        "pll_d",
+};
+static struct clk *mux_plld_p[] = {
+        &tegra_pll_d,
+};
+static const char *mux_clk_32k[] = {
+        "clk_32k",
+};
+static struct clk *mux_clk_32k_p[] = {
+        &tegra_clk_32k,
+};
+static const char *mux_pclk[] = {
+        "pclk",
+};
+static struct clk *mux_pclk_p[] = {
+        &tegra_pclk,
+};
+static struct clk tegra_emc;
+static struct clk_tegra tegra_emc_hw = {
+        .hw = {
+                .clk = &tegra_emc,
+        },
+        .reg = 0x19c,
+        .max_rate = 800000000,
+        .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
+        .reset = &tegra2_periph_clk_reset,
+        .u.periph = {
+                .clk_num = 57,
+        },
+};
+DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
+                mux_pllm_pllc_pllp_clkm_p, NULL);
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg,   \
+                _max, _inputs, _flags)                  \
+        static struct clk tegra_##_name;                \
+        static struct clk_tegra tegra_##_name##_hw = {  \
+                .hw = {                                 \
+                        .clk = &tegra_##_name,          \
+                },                                      \
+                .lookup = {                             \
+                        .dev_id = _dev,                 \
+                        .con_id = _con,                 \
+                },                                      \
+                .reg = _reg,                            \
+                .flags = _flags,                        \
+                .max_rate = _max,                       \
+                .u.periph = {                           \
+                        .clk_num = _clk_num,            \
+                },                                      \
+                .reset = tegra2_periph_clk_reset,       \
+        };                                              \
+        static struct clk tegra_##_name = {             \
+                .name = #_name,                         \
+                .ops = &tegra_periph_clk_ops,           \
+                .hw = &tegra_##_name##_hw.hw,           \
+                .parent_names = _inputs,                \
+                .parents = _inputs##_p,                 \
+                .num_parents = ARRAY_SIZE(_inputs),     \
+        };
+PERIPH_CLK(apbdma,      "tegra-apbdma",         NULL,   34,     0,      108000000, mux_pclk,                    0);
+PERIPH_CLK(rtc,         "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET);
+PERIPH_CLK(timer,       "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(i2s1,        "tegra20-i2s.0",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71);
+PERIPH_CLK(i2s2,        "tegra20-i2s.1",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71);
+PERIPH_CLK(spdif_out,   "spdif_out",            NULL,   10,     0x108,  100000000, mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71);
+PERIPH_CLK(spdif_in,    "spdif_in",             NULL,   10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71);
+PERIPH_CLK(pwm,         "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_audio_clkm_clk32,      MUX | DIV_U71 | MUX_PWM);
+PERIPH_CLK(spi,         "spi",                  NULL,   43,     0x114,  40000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(xio,         "xio",                  NULL,   45,     0x120,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(twc,         "twc",                  NULL,   16,     0x12c,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sbc1,        "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sbc2,        "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sbc3,        "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sbc4,        "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(ide,         "ide",                  NULL,   25,     0x144,  100000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(ndflash,     "tegra_nand",           NULL,   13,     0x160,  164000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vfir,        "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sdmmc1,      "sdhci-tegra.0",        NULL,   14,     0x150,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc2,      "sdhci-tegra.1",        NULL,   9,      0x154,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc3,      "sdhci-tegra.2",        NULL,   69,     0x1bc,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc4,      "sdhci-tegra.3",        NULL,   15,     0x164,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vcp,         "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(bsea,        "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(bsev,        "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(vde,         "tegra-avp",            "vde",  61,     0x1c8,  250000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(csite,       "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* max rate ??? */
+/* FIXME: what is la? */
+PERIPH_CLK(la,          "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(owr,         "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(nor,         "nor",                  NULL,   42,     0x1d0,  92000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(mipi,        "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(i2c1,        "tegra-i2c.0",          "div-clk", 12,  0x124,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(i2c2,        "tegra-i2c.1",          "div-clk", 54,  0x198,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(i2c3,        "tegra-i2c.2",          "div-clk", 67,  0x1b8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(dvc,         "tegra-i2c.3",          "div-clk", 47,  0x128,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(uarta,       "tegra-uart.0",         NULL,   6,      0x178,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(uartb,       "tegra-uart.1",         NULL,   7,      0x17c,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(uartc,       "tegra-uart.2",         NULL,   55,     0x1a0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(uartd,       "tegra-uart.3",         NULL,   65,     0x1c0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(uarte,       "tegra-uart.4",         NULL,   66,     0x1c4,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(3d,          "3d",                   NULL,   24,     0x158,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */
+PERIPH_CLK(2d,          "2d",                   NULL,   21,     0x15c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(vi,          "tegra_camera",         "vi",   20,     0x148,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(vi_sensor,   "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */
+PERIPH_CLK(epp,         "epp",                  NULL,   19,     0x16c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(mpe,         "mpe",                  NULL,   60,     0x170,  250000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(host1x,      "host1x",               NULL,   28,     0x180,  166000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(cve,         "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvo,         "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(hdmi,        "hdmi",                 NULL,   51,     0x18c,  600000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvdac,       "tvdac",                NULL,   53,     0x194,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(disp1,       "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_plld_pllc_clkm,     MUX); /* scales with voltage and process_id */
+PERIPH_CLK(disp2,       "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_plld_pllc_clkm,     MUX); /* scales with voltage and process_id */
+PERIPH_CLK(usbd,        "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(usb2,        "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(usb3,        "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(dsi,         "dsi",                  NULL,   48,     0,      500000000, mux_plld,                    0); /* scales with voltage */
+PERIPH_CLK(csi,         "tegra_camera",         "csi",  52,     0,      72000000,  mux_pllp_out3,               0);
+PERIPH_CLK(isp,         "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0); /* same frequency as VI */
+PERIPH_CLK(csus,        "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET);
+PERIPH_CLK(pex,         NULL,                   "pex",  70,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET);
+PERIPH_CLK(afi,         NULL,                   "afi",  72,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET);
+PERIPH_CLK(pcie_xclk,   NULL,             "pcie_xclk",  74,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET);
+static struct clk *tegra_list_clks[] = {
+        &tegra_apbdma,
+        &tegra_rtc,
+        &tegra_i2s1,
+        &tegra_i2s2,
+        &tegra_spdif_out,
+        &tegra_spdif_in,
+        &tegra_pwm,
+        &tegra_spi,
+        &tegra_xio,
+        &tegra_twc,
+        &tegra_sbc1,
+        &tegra_sbc2,
+        &tegra_sbc3,
+        &tegra_sbc4,
+        &tegra_ide,
+        &tegra_ndflash,
+        &tegra_vfir,
+        &tegra_sdmmc1,
+        &tegra_sdmmc2,
+        &tegra_sdmmc3,
+        &tegra_sdmmc4,
+        &tegra_vcp,
+        &tegra_bsea,
+        &tegra_bsev,
+        &tegra_vde,
+        &tegra_csite,
+        &tegra_la,
+        &tegra_owr,
+        &tegra_nor,
+        &tegra_mipi,
+        &tegra_i2c1,
+        &tegra_i2c2,
+        &tegra_i2c3,
+        &tegra_dvc,
+        &tegra_uarta,
+        &tegra_uartb,
+        &tegra_uartc,
+        &tegra_uartd,
+        &tegra_uarte,
+        &tegra_3d,
+        &tegra_2d,
+        &tegra_vi,
+        &tegra_vi_sensor,
+        &tegra_epp,
+        &tegra_mpe,
+        &tegra_host1x,
+        &tegra_cve,
+        &tegra_tvo,
+        &tegra_hdmi,
+        &tegra_tvdac,
+        &tegra_disp1,
+        &tegra_disp2,
+        &tegra_usbd,
+        &tegra_usb2,
+        &tegra_usb3,
+        &tegra_dsi,
+        &tegra_csi,
+        &tegra_isp,
+        &tegra_csus,
+        &tegra_pex,
+        &tegra_afi,
+        &tegra_pcie_xclk,
+};
+#define CLK_DUPLICATE(_name, _dev, _con)        \
+        {                                       \
+                .name   = _name,                \
+                .lookup = {                     \
+                        .dev_id = _dev,         \
+                        .con_id = _con,         \
+                },                              \
+        }
+/* Some clocks may be used by different drivers depending on the board
+ * configuration.  List those here to register them twice in the clock lookup
+ * table under two names.
+ */
+static struct clk_duplicate tegra_clk_duplicates[] = {
+        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
+        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
+        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
+        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
+        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
+        CLK_DUPLICATE("usbd",   "utmip-pad",    NULL),
+        CLK_DUPLICATE("usbd",   "tegra-ehci.0", NULL),
+        CLK_DUPLICATE("usbd",   "tegra-otg",    NULL),
+        CLK_DUPLICATE("hdmi",   "tegradc.0",    "hdmi"),
+        CLK_DUPLICATE("hdmi",   "tegradc.1",    "hdmi"),
+        CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
+        CLK_DUPLICATE("2d",     "tegra_grhost", "gr2d"),
+        CLK_DUPLICATE("3d",     "tegra_grhost", "gr3d"),
+        CLK_DUPLICATE("epp",    "tegra_grhost", "epp"),
+        CLK_DUPLICATE("mpe",    "tegra_grhost", "mpe"),
+        CLK_DUPLICATE("cop",    "tegra-avp",    "cop"),
+        CLK_DUPLICATE("vde",    "tegra-aes",    "vde"),
+        CLK_DUPLICATE("cclk",   NULL,           "cpu"),
+        CLK_DUPLICATE("twd",    "smp_twd",      NULL),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
+};
+#define CLK(dev, con, ck)       \
+        {                       \
+                .dev_id = dev,  \
+                .con_id = con,  \
+                .clk    = ck,   \
+        }
+static struct clk *tegra_ptr_clks[] = {
+        &tegra_clk_32k,
+        &tegra_pll_s,
+        &tegra_clk_m,
+        &tegra_pll_m,
+        &tegra_pll_m_out1,
+        &tegra_pll_c,
+        &tegra_pll_c_out1,
+        &tegra_pll_p,
+        &tegra_pll_p_out1,
+        &tegra_pll_p_out2,
+        &tegra_pll_p_out3,
+        &tegra_pll_p_out4,
+        &tegra_pll_a,
+        &tegra_pll_a_out0,
+        &tegra_pll_d,
+        &tegra_pll_d_out0,
+        &tegra_pll_u,
+        &tegra_pll_x,
+        &tegra_pll_e,
+        &tegra_cclk,
+        &tegra_clk_twd,
+        &tegra_sclk,
+        &tegra_hclk,
+        &tegra_pclk,
+        &tegra_clk_d,
+        &tegra_cdev1,
+        &tegra_cdev2,
+        &tegra_blink,
+        &tegra_cop,
+        &tegra_emc,
+};
+static void tegra2_init_one_clock(struct clk *c)
+{
+        struct clk_tegra *clk = to_clk_tegra(c->hw);
+        int ret;
+        ret = __clk_init(NULL, c);
+        if (ret)
+                pr_err("clk init failed %s\n", __clk_get_name(c));
+        INIT_LIST_HEAD(&clk->shared_bus_list);
+        if (!clk->lookup.dev_id && !clk->lookup.con_id)
+                clk->lookup.con_id = c->name;
+        clk->lookup.clk = c;
+        clkdev_add(&clk->lookup);
+        tegra_clk_add(c);
+}
+void __init tegra2_init_clocks(void)
+{
+        int i;
+        struct clk *c;
+        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
+                tegra2_init_one_clock(tegra_ptr_clks[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
+                tegra2_init_one_clock(tegra_list_clks[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+                if (!c) {
+                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
+                                tegra_clk_duplicates[i].name);
+                        continue;
+                }
+                tegra_clk_duplicates[i].lookup.clk = c;
+                clkdev_add(&tegra_clk_duplicates[i].lookup);
+        }
+        init_audio_sync_clock_mux();
+        tegra20_cpu_car_ops_init();
+}
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
deleted file mode 100644
index a703844b2061..000000000000
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ /dev/null
@@ -1,2484 +0,0 @@
-/*
- * arch/arm/mach-tegra/tegra2_clocks.c
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/clk.h>
-#include <mach/iomap.h>
-#include <mach/suspend.h>
-#include "clock.h"
-#include "fuse.h"
-#include "tegra2_emc.h"
-#define RST_DEVICES                     0x004
-#define RST_DEVICES_SET                 0x300
-#define RST_DEVICES_CLR                 0x304
-#define RST_DEVICES_NUM                 3
-#define CLK_OUT_ENB                     0x010
-#define CLK_OUT_ENB_SET                 0x320
-#define CLK_OUT_ENB_CLR                 0x324
-#define CLK_OUT_ENB_NUM                 3
-#define CLK_MASK_ARM                    0x44
-#define MISC_CLK_ENB                    0x48
-#define OSC_CTRL                        0x50
-#define OSC_CTRL_OSC_FREQ_MASK          (3<<30)
-#define OSC_CTRL_OSC_FREQ_13MHZ         (0<<30)
-#define OSC_CTRL_OSC_FREQ_19_2MHZ       (1<<30)
-#define OSC_CTRL_OSC_FREQ_12MHZ         (2<<30)
-#define OSC_CTRL_OSC_FREQ_26MHZ         (3<<30)
-#define OSC_CTRL_MASK                   (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
-#define OSC_FREQ_DET                    0x58
-#define OSC_FREQ_DET_TRIG               (1<<31)
-#define OSC_FREQ_DET_STATUS             0x5C
-#define OSC_FREQ_DET_BUSY               (1<<31)
-#define OSC_FREQ_DET_CNT_MASK           0xFFFF
-#define PERIPH_CLK_SOURCE_I2S1          0x100
-#define PERIPH_CLK_SOURCE_EMC           0x19c
-#define PERIPH_CLK_SOURCE_OSC           0x1fc
-#define PERIPH_CLK_SOURCE_NUM \
-        ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
-#define PERIPH_CLK_SOURCE_MASK          (3<<30)
-#define PERIPH_CLK_SOURCE_SHIFT         30
-#define PERIPH_CLK_SOURCE_PWM_MASK      (7<<28)
-#define PERIPH_CLK_SOURCE_PWM_SHIFT     28
-#define PERIPH_CLK_SOURCE_ENABLE        (1<<28)
-#define PERIPH_CLK_SOURCE_DIVU71_MASK   0xFF
-#define PERIPH_CLK_SOURCE_DIVU16_MASK   0xFFFF
-#define PERIPH_CLK_SOURCE_DIV_SHIFT     0
-#define SDMMC_CLK_INT_FB_SEL            (1 << 23)
-#define SDMMC_CLK_INT_FB_DLY_SHIFT      16
-#define SDMMC_CLK_INT_FB_DLY_MASK       (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
-#define PLL_BASE                        0x0
-#define PLL_BASE_BYPASS                 (1<<31)
-#define PLL_BASE_ENABLE                 (1<<30)
-#define PLL_BASE_REF_ENABLE             (1<<29)
-#define PLL_BASE_OVERRIDE               (1<<28)
-#define PLL_BASE_DIVP_MASK              (0x7<<20)
-#define PLL_BASE_DIVP_SHIFT             20
-#define PLL_BASE_DIVN_MASK              (0x3FF<<8)
-#define PLL_BASE_DIVN_SHIFT             8
-#define PLL_BASE_DIVM_MASK              (0x1F)
-#define PLL_BASE_DIVM_SHIFT             0
-#define PLL_OUT_RATIO_MASK              (0xFF<<8)
-#define PLL_OUT_RATIO_SHIFT             8
-#define PLL_OUT_OVERRIDE                (1<<2)
-#define PLL_OUT_CLKEN                   (1<<1)
-#define PLL_OUT_RESET_DISABLE           (1<<0)
-#define PLL_MISC(c)                     (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
-#define PLL_MISC_DCCON_SHIFT            20
-#define PLL_MISC_CPCON_SHIFT            8
-#define PLL_MISC_CPCON_MASK             (0xF<<PLL_MISC_CPCON_SHIFT)
-#define PLL_MISC_LFCON_SHIFT            4
-#define PLL_MISC_LFCON_MASK             (0xF<<PLL_MISC_LFCON_SHIFT)
-#define PLL_MISC_VCOCON_SHIFT           0
-#define PLL_MISC_VCOCON_MASK            (0xF<<PLL_MISC_VCOCON_SHIFT)
-#define PLLU_BASE_POST_DIV              (1<<20)
-#define PLLD_MISC_CLKENABLE             (1<<30)
-#define PLLD_MISC_DIV_RST               (1<<23)
-#define PLLD_MISC_DCCON_SHIFT           12
-#define PLLE_MISC_READY                 (1 << 15)
-#define PERIPH_CLK_TO_ENB_REG(c)        ((c->u.periph.clk_num / 32) * 4)
-#define PERIPH_CLK_TO_ENB_SET_REG(c)    ((c->u.periph.clk_num / 32) * 8)
-#define PERIPH_CLK_TO_ENB_BIT(c)        (1 << (c->u.periph.clk_num % 32))
-#define SUPER_CLK_MUX                   0x00
-#define SUPER_STATE_SHIFT               28
-#define SUPER_STATE_MASK                (0xF << SUPER_STATE_SHIFT)
-#define SUPER_STATE_STANDBY             (0x0 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_IDLE                (0x1 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_RUN                 (0x2 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_IRQ                 (0x3 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_FIQ                 (0x4 << SUPER_STATE_SHIFT)
-#define SUPER_SOURCE_MASK               0xF
-#define SUPER_FIQ_SOURCE_SHIFT          12
-#define SUPER_IRQ_SOURCE_SHIFT          8
-#define SUPER_RUN_SOURCE_SHIFT          4
-#define SUPER_IDLE_SOURCE_SHIFT         0
-#define SUPER_CLK_DIVIDER               0x04
-#define BUS_CLK_DISABLE                 (1<<3)
-#define BUS_CLK_DIV_MASK                0x3
-#define PMC_CTRL                        0x0
- #define PMC_CTRL_BLINK_ENB             (1 << 7)
-#define PMC_DPD_PADS_ORIDE              0x1c
- #define PMC_DPD_PADS_ORIDE_BLINK_ENB   (1 << 20)
-#define PMC_BLINK_TIMER_DATA_ON_SHIFT   0
-#define PMC_BLINK_TIMER_DATA_ON_MASK    0x7fff
-#define PMC_BLINK_TIMER_ENB             (1 << 15)
-#define PMC_BLINK_TIMER_DATA_OFF_SHIFT  16
-#define PMC_BLINK_TIMER_DATA_OFF_MASK   0xffff
-static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
-static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
-/*
- * Some clocks share a register with other clocks.  Any clock op that
- * non-atomically modifies a register used by another clock must lock
- * clock_register_lock first.
- */
-static DEFINE_SPINLOCK(clock_register_lock);
-/*
- * Some peripheral clocks share an enable bit, so refcount the enable bits
- * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
- */
-static int tegra_periph_clk_enable_refcount[3 * 32];
-#define clk_writel(value, reg) \
-        __raw_writel(value, reg_clk_base + (reg))
-#define clk_readl(reg) \
-        __raw_readl(reg_clk_base + (reg))
-#define pmc_writel(value, reg) \
-        __raw_writel(value, reg_pmc_base + (reg))
-#define pmc_readl(reg) \
-        __raw_readl(reg_pmc_base + (reg))
-static unsigned long clk_measure_input_freq(void)
-{
-        u32 clock_autodetect;
-        clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
-        do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
-        clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
-        if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
-                return 12000000;
-        } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
-                return 13000000;
-        } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
-                return 19200000;
-        } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
-                return 26000000;
-        } else {
-                pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
-                BUG();
-                return 0;
-        }
-}
-static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
-{
-        s64 divider_u71 = parent_rate * 2;
-        divider_u71 += rate - 1;
-        do_div(divider_u71, rate);
-        if (divider_u71 - 2 < 0)
-                return 0;
-        if (divider_u71 - 2 > 255)
-                return -EINVAL;
-        return divider_u71 - 2;
-}
-static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
-{
-        s64 divider_u16;
-        divider_u16 = parent_rate;
-        divider_u16 += rate - 1;
-        do_div(divider_u16, rate);
-        if (divider_u16 - 1 < 0)
-                return 0;
-        if (divider_u16 - 1 > 255)
-                return -EINVAL;
-        return divider_u16 - 1;
-}
-/* clk_m functions */
-static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
-{
-        u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
-        c->rate = clk_measure_input_freq();
-        switch (c->rate) {
-        case 12000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
-                break;
-        case 13000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
-                break;
-        case 19200000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
-                break;
-        case 26000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
-                break;
-        default:
-                pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
-                BUG();
-        }
-        clk_writel(auto_clock_control, OSC_CTRL);
-        return c->rate;
-}
-static void tegra2_clk_m_init(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        tegra2_clk_m_autodetect_rate(c);
-}
-static int tegra2_clk_m_enable(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        return 0;
-}
-static void tegra2_clk_m_disable(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        BUG();
-}
-static struct clk_ops tegra_clk_m_ops = {
-        .init           = tegra2_clk_m_init,
-        .enable         = tegra2_clk_m_enable,
-        .disable        = tegra2_clk_m_disable,
-};
-/* super clock functions */
-/* "super clocks" on tegra have two-stage muxes and a clock skipping
- * super divider.  We will ignore the clock skipping divider, since we
- * can't lower the voltage when using the clock skip, but we can if we
- * lower the PLL frequency.
- */
-static void tegra2_super_clk_init(struct clk *c)
-{
-        u32 val;
-        int source;
-        int shift;
-        const struct clk_mux_sel *sel;
-        val = clk_readl(c->reg + SUPER_CLK_MUX);
-        c->state = ON;
-        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        source = (val >> shift) & SUPER_SOURCE_MASK;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->value == source)
-                        break;
-        }
-        BUG_ON(sel->input == NULL);
-        c->parent = sel->input;
-}
-static int tegra2_super_clk_enable(struct clk *c)
-{
-        clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
-        return 0;
-}
-static void tegra2_super_clk_disable(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        /* oops - don't disable the CPU clock! */
-        BUG();
-}
-static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
-{
-        u32 val;
-        const struct clk_mux_sel *sel;
-        int shift;
-        val = clk_readl(c->reg + SUPER_CLK_MUX);
-        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val &= ~(SUPER_SOURCE_MASK << shift);
-                        val |= sel->value << shift;
-                        if (c->refcnt)
-                                clk_enable(p);
-                        clk_writel(val, c->reg);
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
-        return -EINVAL;
-}
-/*
- * Super clocks have "clock skippers" instead of dividers.  Dividing using
- * a clock skipper does not allow the voltage to be scaled down, so instead
- * adjust the rate of the parent clock.  This requires that the parent of a
- * super clock have no other children, otherwise the rate will change
- * underneath the other children.
- */
-static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        return clk_set_rate(c->parent, rate);
-}
-static struct clk_ops tegra_super_ops = {
-        .init                   = tegra2_super_clk_init,
-        .enable                 = tegra2_super_clk_enable,
-        .disable                = tegra2_super_clk_disable,
-        .set_parent             = tegra2_super_clk_set_parent,
-        .set_rate               = tegra2_super_clk_set_rate,
-};
-/* virtual cpu clock functions */
-/* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
-   To change the frequency of these clocks, the parent pll may need to be
-   reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
-   and then the clock moved back to the pll.  To hide this sequence, a virtual
-   clock handles it.
- */
-static void tegra2_cpu_clk_init(struct clk *c)
-{
-}
-static int tegra2_cpu_clk_enable(struct clk *c)
-{
-        return 0;
-}
-static void tegra2_cpu_clk_disable(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        /* oops - don't disable the CPU clock! */
-        BUG();
-}
-static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        int ret;
-        /*
-         * Take an extra reference to the main pll so it doesn't turn
-         * off when we move the cpu off of it
-         */
-        clk_enable(c->u.cpu.main);
-        ret = clk_set_parent(c->parent, c->u.cpu.backup);
-        if (ret) {
-                pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
-                goto out;
-        }
-        if (rate == clk_get_rate(c->u.cpu.backup))
-                goto out;
-        ret = clk_set_rate(c->u.cpu.main, rate);
-        if (ret) {
-                pr_err("Failed to change cpu pll to %lu\n", rate);
-                goto out;
-        }
-        ret = clk_set_parent(c->parent, c->u.cpu.main);
-        if (ret) {
-                pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
-                goto out;
-        }
-out:
-        clk_disable(c->u.cpu.main);
-        return ret;
-}
-static struct clk_ops tegra_cpu_ops = {
-        .init     = tegra2_cpu_clk_init,
-        .enable   = tegra2_cpu_clk_enable,
-        .disable  = tegra2_cpu_clk_disable,
-        .set_rate = tegra2_cpu_clk_set_rate,
-};
-/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
- * reset the COP block (i.e. AVP) */
-static void tegra2_cop_clk_reset(struct clk *c, bool assert)
-{
-        unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
-        pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
-        clk_writel(1 << 1, reg);
-}
-static struct clk_ops tegra_cop_ops = {
-        .reset    = tegra2_cop_clk_reset,
-};
-/* bus clock functions */
-static void tegra2_bus_clk_init(struct clk *c)
-{
-        u32 val = clk_readl(c->reg);
-        c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
-        c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
-        c->mul = 1;
-}
-static int tegra2_bus_clk_enable(struct clk *c)
-{
-        u32 val;
-        unsigned long flags;
-        spin_lock_irqsave(&clock_register_lock, flags);
-        val = clk_readl(c->reg);
-        val &= ~(BUS_CLK_DISABLE << c->reg_shift);
-        clk_writel(val, c->reg);
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-        return 0;
-}
-static void tegra2_bus_clk_disable(struct clk *c)
-{
-        u32 val;
-        unsigned long flags;
-        spin_lock_irqsave(&clock_register_lock, flags);
-        val = clk_readl(c->reg);
-        val |= BUS_CLK_DISABLE << c->reg_shift;
-        clk_writel(val, c->reg);
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-}
-static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        u32 val;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        unsigned long flags;
-        int ret = -EINVAL;
-        int i;
-        spin_lock_irqsave(&clock_register_lock, flags);
-        val = clk_readl(c->reg);
-        for (i = 1; i <= 4; i++) {
-                if (rate == parent_rate / i) {
-                        val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
-                        val |= (i - 1) << c->reg_shift;
-                        clk_writel(val, c->reg);
-                        c->div = i;
-                        c->mul = 1;
-                        ret = 0;
-                        break;
-                }
-        }
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-        return ret;
-}
-static struct clk_ops tegra_bus_ops = {
-        .init                   = tegra2_bus_clk_init,
-        .enable                 = tegra2_bus_clk_enable,
-        .disable                = tegra2_bus_clk_disable,
-        .set_rate               = tegra2_bus_clk_set_rate,
-};
-/* Blink output functions */
-static void tegra2_blink_clk_init(struct clk *c)
-{
-        u32 val;
-        val = pmc_readl(PMC_CTRL);
-        c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
-        c->mul = 1;
-        val = pmc_readl(c->reg);
-        if (val & PMC_BLINK_TIMER_ENB) {
-                unsigned int on_off;
-                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
-                        PMC_BLINK_TIMER_DATA_ON_MASK;
-                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
-                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
-                on_off += val;
-                /* each tick in the blink timer is 4 32KHz clocks */
-                c->div = on_off * 4;
-        } else {
-                c->div = 1;
-        }
-}
-static int tegra2_blink_clk_enable(struct clk *c)
-{
-        u32 val;
-        val = pmc_readl(PMC_DPD_PADS_ORIDE);
-        pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
-        val = pmc_readl(PMC_CTRL);
-        pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
-        return 0;
-}
-static void tegra2_blink_clk_disable(struct clk *c)
-{
-        u32 val;
-        val = pmc_readl(PMC_CTRL);
-        pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
-        val = pmc_readl(PMC_DPD_PADS_ORIDE);
-        pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
-}
-static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        if (rate >= parent_rate) {
-                c->div = 1;
-                pmc_writel(0, c->reg);
-        } else {
-                unsigned int on_off;
-                u32 val;
-                on_off = DIV_ROUND_UP(parent_rate / 8, rate);
-                c->div = on_off * 8;
-                val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
-                        PMC_BLINK_TIMER_DATA_ON_SHIFT;
-                on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
-                on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
-                val |= on_off;
-                val |= PMC_BLINK_TIMER_ENB;
-                pmc_writel(val, c->reg);
-        }
-        return 0;
-}
-static struct clk_ops tegra_blink_clk_ops = {
-        .init                   = &tegra2_blink_clk_init,
-        .enable                 = &tegra2_blink_clk_enable,
-        .disable                = &tegra2_blink_clk_disable,
-        .set_rate               = &tegra2_blink_clk_set_rate,
-};
-/* PLL Functions */
-static int tegra2_pll_clk_wait_for_lock(struct clk *c)
-{
-        udelay(c->u.pll.lock_delay);
-        return 0;
-}
-static void tegra2_pll_clk_init(struct clk *c)
-{
-        u32 val = clk_readl(c->reg + PLL_BASE);
-        c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
-        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
-                pr_warning("Clock %s has unknown fixed frequency\n", c->name);
-                c->mul = 1;
-                c->div = 1;
-        } else if (val & PLL_BASE_BYPASS) {
-                c->mul = 1;
-                c->div = 1;
-        } else {
-                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
-                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
-                if (c->flags & PLLU)
-                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
-                else
-                        c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
-        }
-}
-static int tegra2_pll_clk_enable(struct clk *c)
-{
-        u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        val = clk_readl(c->reg + PLL_BASE);
-        val &= ~PLL_BASE_BYPASS;
-        val |= PLL_BASE_ENABLE;
-        clk_writel(val, c->reg + PLL_BASE);
-        tegra2_pll_clk_wait_for_lock(c);
-        return 0;
-}
-static void tegra2_pll_clk_disable(struct clk *c)
-{
-        u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        val = clk_readl(c->reg);
-        val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
-        clk_writel(val, c->reg);
-}
-static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        u32 val;
-        unsigned long input_rate;
-        const struct clk_pll_freq_table *sel;
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-        input_rate = clk_get_rate(c->parent);
-        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
-                if (sel->input_rate == input_rate && sel->output_rate == rate) {
-                        c->mul = sel->n;
-                        c->div = sel->m * sel->p;
-                        val = clk_readl(c->reg + PLL_BASE);
-                        if (c->flags & PLL_FIXED)
-                                val |= PLL_BASE_OVERRIDE;
-                        val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
-                                 PLL_BASE_DIVM_MASK);
-                        val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
-                                (sel->n << PLL_BASE_DIVN_SHIFT);
-                        BUG_ON(sel->p < 1 || sel->p > 2);
-                        if (c->flags & PLLU) {
-                                if (sel->p == 1)
-                                        val |= PLLU_BASE_POST_DIV;
-                        } else {
-                                if (sel->p == 2)
-                                        val |= 1 << PLL_BASE_DIVP_SHIFT;
-                        }
-                        clk_writel(val, c->reg + PLL_BASE);
-                        if (c->flags & PLL_HAS_CPCON) {
-                                val = clk_readl(c->reg + PLL_MISC(c));
-                                val &= ~PLL_MISC_CPCON_MASK;
-                                val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
-                                clk_writel(val, c->reg + PLL_MISC(c));
-                        }
-                        if (c->state == ON)
-                                tegra2_pll_clk_enable(c);
-                        return 0;
-                }
-        }
-        return -EINVAL;
-}
-static struct clk_ops tegra_pll_ops = {
-        .init                   = tegra2_pll_clk_init,
-        .enable                 = tegra2_pll_clk_enable,
-        .disable                = tegra2_pll_clk_disable,
-        .set_rate               = tegra2_pll_clk_set_rate,
-};
-static void tegra2_pllx_clk_init(struct clk *c)
-{
-        tegra2_pll_clk_init(c);
-        if (tegra_sku_id == 7)
-                c->max_rate = 750000000;
-}
-static struct clk_ops tegra_pllx_ops = {
-        .init     = tegra2_pllx_clk_init,
-        .enable   = tegra2_pll_clk_enable,
-        .disable  = tegra2_pll_clk_disable,
-        .set_rate = tegra2_pll_clk_set_rate,
-};
-static int tegra2_plle_clk_enable(struct clk *c)
-{
-        u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        mdelay(1);
-        val = clk_readl(c->reg + PLL_BASE);
-        if (!(val & PLLE_MISC_READY))
-                return -EBUSY;
-        val = clk_readl(c->reg + PLL_BASE);
-        val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
-        clk_writel(val, c->reg + PLL_BASE);
-        return 0;
-}
-static struct clk_ops tegra_plle_ops = {
-        .init       = tegra2_pll_clk_init,
-        .enable     = tegra2_plle_clk_enable,
-        .set_rate   = tegra2_pll_clk_set_rate,
-};
-/* Clock divider ops */
-static void tegra2_pll_div_clk_init(struct clk *c)
-{
-        u32 val = clk_readl(c->reg);
-        u32 divu71;
-        val >>= c->reg_shift;
-        c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
-        if (!(val & PLL_OUT_RESET_DISABLE))
-                c->state = OFF;
-        if (c->flags & DIV_U71) {
-                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
-                c->div = (divu71 + 2);
-                c->mul = 2;
-        } else if (c->flags & DIV_2) {
-                c->div = 2;
-                c->mul = 1;
-        } else {
-                c->div = 1;
-                c->mul = 1;
-        }
-}
-static int tegra2_pll_div_clk_enable(struct clk *c)
-{
-        u32 val;
-        u32 new_val;
-        unsigned long flags;
-        pr_debug("%s: %s\n", __func__, c->name);
-        if (c->flags & DIV_U71) {
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                new_val = val >> c->reg_shift;
-                new_val &= 0xFFFF;
-                new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
-                val &= ~(0xFFFF << c->reg_shift);
-                val |= new_val << c->reg_shift;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-                return 0;
-        } else if (c->flags & DIV_2) {
-                BUG_ON(!(c->flags & PLLD));
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                val &= ~PLLD_MISC_DIV_RST;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-                return 0;
-        }
-        return -EINVAL;
-}
-static void tegra2_pll_div_clk_disable(struct clk *c)
-{
-        u32 val;
-        u32 new_val;
-        unsigned long flags;
-        pr_debug("%s: %s\n", __func__, c->name);
-        if (c->flags & DIV_U71) {
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                new_val = val >> c->reg_shift;
-                new_val &= 0xFFFF;
-                new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
-                val &= ~(0xFFFF << c->reg_shift);
-                val |= new_val << c->reg_shift;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-        } else if (c->flags & DIV_2) {
-                BUG_ON(!(c->flags & PLLD));
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                val |= PLLD_MISC_DIV_RST;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-        }
-}
-static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        u32 val;
-        u32 new_val;
-        int divider_u71;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        unsigned long flags;
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-        if (c->flags & DIV_U71) {
-                divider_u71 = clk_div71_get_divider(parent_rate, rate);
-                if (divider_u71 >= 0) {
-                        spin_lock_irqsave(&clock_register_lock, flags);
-                        val = clk_readl(c->reg);
-                        new_val = val >> c->reg_shift;
-                        new_val &= 0xFFFF;
-                        if (c->flags & DIV_U71_FIXED)
-                                new_val |= PLL_OUT_OVERRIDE;
-                        new_val &= ~PLL_OUT_RATIO_MASK;
-                        new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
-                        val &= ~(0xFFFF << c->reg_shift);
-                        val |= new_val << c->reg_shift;
-                        clk_writel(val, c->reg);
-                        c->div = divider_u71 + 2;
-                        c->mul = 2;
-                        spin_unlock_irqrestore(&clock_register_lock, flags);
-                        return 0;
-                }
-        } else if (c->flags & DIV_2) {
-                if (parent_rate == rate * 2)
-                        return 0;
-        }
-        return -EINVAL;
-}
-static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
-{
-        int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(parent_rate, rate);
-                if (divider < 0)
-                        return divider;
-                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
-        } else if (c->flags & DIV_2) {
-                return DIV_ROUND_UP(parent_rate, 2);
-        }
-        return -EINVAL;
-}
-static struct clk_ops tegra_pll_div_ops = {
-        .init                   = tegra2_pll_div_clk_init,
-        .enable                 = tegra2_pll_div_clk_enable,
-        .disable                = tegra2_pll_div_clk_disable,
-        .set_rate               = tegra2_pll_div_clk_set_rate,
-        .round_rate             = tegra2_pll_div_clk_round_rate,
-};
-/* Periph clk ops */
-static void tegra2_periph_clk_init(struct clk *c)
-{
-        u32 val = clk_readl(c->reg);
-        const struct clk_mux_sel *mux = NULL;
-        const struct clk_mux_sel *sel;
-        u32 shift;
-        u32 mask;
-        if (c->flags & MUX_PWM) {
-                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
-                mask = PERIPH_CLK_SOURCE_PWM_MASK;
-        } else {
-                shift = PERIPH_CLK_SOURCE_SHIFT;
-                mask = PERIPH_CLK_SOURCE_MASK;
-        }
-        if (c->flags & MUX) {
-                for (sel = c->inputs; sel->input != NULL; sel++) {
-                        if ((val & mask) >> shift == sel->value)
-                                mux = sel;
-                }
-                BUG_ON(!mux);
-                c->parent = mux->input;
-        } else {
-                c->parent = c->inputs[0].input;
-        }
-        if (c->flags & DIV_U71) {
-                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
-                c->div = divu71 + 2;
-                c->mul = 2;
-        } else if (c->flags & DIV_U16) {
-                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
-                c->div = divu16 + 1;
-                c->mul = 1;
-        } else {
-                c->div = 1;
-                c->mul = 1;
-        }
-        c->state = ON;
-        if (!c->u.periph.clk_num)
-                return;
-        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
-                        PERIPH_CLK_TO_ENB_BIT(c)))
-                c->state = OFF;
-        if (!(c->flags & PERIPH_NO_RESET))
-                if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
-                                PERIPH_CLK_TO_ENB_BIT(c))
-                        c->state = OFF;
-}
-static int tegra2_periph_clk_enable(struct clk *c)
-{
-        u32 val;
-        unsigned long flags;
-        int refcount;
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        if (!c->u.periph.clk_num)
-                return 0;
-        spin_lock_irqsave(&clock_register_lock, flags);
-        refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
-        if (refcount > 1)
-                goto out;
-        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
-        if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
-                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                        RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
-        if (c->flags & PERIPH_EMC_ENB) {
-                /* The EMC peripheral clock has 2 extra enable bits */
-                /* FIXME: Do they need to be disabled? */
-                val = clk_readl(c->reg);
-                val |= 0x3 << 24;
-                clk_writel(val, c->reg);
-        }
-out:
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-        return 0;
-}
-static void tegra2_periph_clk_disable(struct clk *c)
-{
-        unsigned long flags;
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        if (!c->u.periph.clk_num)
-                return;
-        spin_lock_irqsave(&clock_register_lock, flags);
-        if (c->refcnt)
-                tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
-        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0)
-                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                        CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-}
-static void tegra2_periph_clk_reset(struct clk *c, bool assert)
-{
-        unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
-        pr_debug("%s %s on clock %s\n", __func__,
-                 assert ? "assert" : "deassert", c->name);
-        BUG_ON(!c->u.periph.clk_num);
-        if (!(c->flags & PERIPH_NO_RESET))
-                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                           base + PERIPH_CLK_TO_ENB_SET_REG(c));
-}
-static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
-{
-        u32 val;
-        const struct clk_mux_sel *sel;
-        u32 mask, shift;
-        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
-        if (c->flags & MUX_PWM) {
-                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
-                mask = PERIPH_CLK_SOURCE_PWM_MASK;
-        } else {
-                shift = PERIPH_CLK_SOURCE_SHIFT;
-                mask = PERIPH_CLK_SOURCE_MASK;
-        }
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val = clk_readl(c->reg);
-                        val &= ~mask;
-                        val |= (sel->value) << shift;
-                        if (c->refcnt)
-                                clk_enable(p);
-                        clk_writel(val, c->reg);
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
-        return -EINVAL;
-}
-static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        u32 val;
-        int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(parent_rate, rate);
-                if (divider >= 0) {
-                        val = clk_readl(c->reg);
-                        val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
-                        val |= divider;
-                        clk_writel(val, c->reg);
-                        c->div = divider + 2;
-                        c->mul = 2;
-                        return 0;
-                }
-        } else if (c->flags & DIV_U16) {
-                divider = clk_div16_get_divider(parent_rate, rate);
-                if (divider >= 0) {
-                        val = clk_readl(c->reg);
-                        val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
-                        val |= divider;
-                        clk_writel(val, c->reg);
-                        c->div = divider + 1;
-                        c->mul = 1;
-                        return 0;
-                }
-        } else if (parent_rate <= rate) {
-                c->div = 1;
-                c->mul = 1;
-                return 0;
-        }
-        return -EINVAL;
-}
-static long tegra2_periph_clk_round_rate(struct clk *c,
-        unsigned long rate)
-{
-        int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(parent_rate, rate);
-                if (divider < 0)
-                        return divider;
-                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
-        } else if (c->flags & DIV_U16) {
-                divider = clk_div16_get_divider(parent_rate, rate);
-                if (divider < 0)
-                        return divider;
-                return DIV_ROUND_UP(parent_rate, divider + 1);
-        }
-        return -EINVAL;
-}
-static struct clk_ops tegra_periph_clk_ops = {
-        .init                   = &tegra2_periph_clk_init,
-        .enable                 = &tegra2_periph_clk_enable,
-        .disable                = &tegra2_periph_clk_disable,
-        .set_parent             = &tegra2_periph_clk_set_parent,
-        .set_rate               = &tegra2_periph_clk_set_rate,
-        .round_rate             = &tegra2_periph_clk_round_rate,
-        .reset                  = &tegra2_periph_clk_reset,
-};
-/* The SDMMC controllers have extra bits in the clock source register that
- * adjust the delay between the clock and data to compenstate for delays
- * on the PCB. */
-void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
-{
-        u32 reg;
-        unsigned long flags;
-        spin_lock_irqsave(&c->spinlock, flags);
-        delay = clamp(delay, 0, 15);
-        reg = clk_readl(c->reg);
-        reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
-        reg |= SDMMC_CLK_INT_FB_SEL;
-        reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
-        clk_writel(reg, c->reg);
-        spin_unlock_irqrestore(&c->spinlock, flags);
-}
-/* External memory controller clock ops */
-static void tegra2_emc_clk_init(struct clk *c)
-{
-        tegra2_periph_clk_init(c);
-        c->max_rate = clk_get_rate_locked(c);
-}
-static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
-{
-        long emc_rate;
-        long clk_rate;
-        /*
-         * The slowest entry in the EMC clock table that is at least as
-         * fast as rate.
-         */
-        emc_rate = tegra_emc_round_rate(rate);
-        if (emc_rate < 0)
-                return c->max_rate;
-        /*
-         * The fastest rate the PLL will generate that is at most the
-         * requested rate.
-         */
-        clk_rate = tegra2_periph_clk_round_rate(c, emc_rate);
-        /*
-         * If this fails, and emc_rate > clk_rate, it's because the maximum
-         * rate in the EMC tables is larger than the maximum rate of the EMC
-         * clock. The EMC clock's max rate is the rate it was running when the
-         * kernel booted. Such a mismatch is probably due to using the wrong
-         * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
-         */
-        WARN_ONCE(emc_rate != clk_rate,
-                "emc_rate %ld != clk_rate %ld",
-                emc_rate, clk_rate);
-        return emc_rate;
-}
-static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        int ret;
-        /*
-         * The Tegra2 memory controller has an interlock with the clock
-         * block that allows memory shadowed registers to be updated,
-         * and then transfer them to the main registers at the same
-         * time as the clock update without glitches.
-         */
-        ret = tegra_emc_set_rate(rate);
-        if (ret < 0)
-                return ret;
-        ret = tegra2_periph_clk_set_rate(c, rate);
-        udelay(1);
-        return ret;
-}
-static struct clk_ops tegra_emc_clk_ops = {
-        .init                   = &tegra2_emc_clk_init,
-        .enable                 = &tegra2_periph_clk_enable,
-        .disable                = &tegra2_periph_clk_disable,
-        .set_parent             = &tegra2_periph_clk_set_parent,
-        .set_rate               = &tegra2_emc_clk_set_rate,
-        .round_rate             = &tegra2_emc_clk_round_rate,
-        .reset                  = &tegra2_periph_clk_reset,
-};
-/* Clock doubler ops */
-static void tegra2_clk_double_init(struct clk *c)
-{
-        c->mul = 2;
-        c->div = 1;
-        c->state = ON;
-        if (!c->u.periph.clk_num)
-                return;
-        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
-                        PERIPH_CLK_TO_ENB_BIT(c)))
-                c->state = OFF;
-};
-static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
-{
-        if (rate != 2 * clk_get_rate(c->parent))
-                return -EINVAL;
-        c->mul = 2;
-        c->div = 1;
-        return 0;
-}
-static struct clk_ops tegra_clk_double_ops = {
-        .init                   = &tegra2_clk_double_init,
-        .enable                 = &tegra2_periph_clk_enable,
-        .disable                = &tegra2_periph_clk_disable,
-        .set_rate               = &tegra2_clk_double_set_rate,
-};
-/* Audio sync clock ops */
-static void tegra2_audio_sync_clk_init(struct clk *c)
-{
-        int source;
-        const struct clk_mux_sel *sel;
-        u32 val = clk_readl(c->reg);
-        c->state = (val & (1<<4)) ? OFF : ON;
-        source = val & 0xf;
-        for (sel = c->inputs; sel->input != NULL; sel++)
-                if (sel->value == source)
-                        break;
-        BUG_ON(sel->input == NULL);
-        c->parent = sel->input;
-}
-static int tegra2_audio_sync_clk_enable(struct clk *c)
-{
-        clk_writel(0, c->reg);
-        return 0;
-}
-static void tegra2_audio_sync_clk_disable(struct clk *c)
-{
-        clk_writel(1, c->reg);
-}
-static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
-{
-        u32 val;
-        const struct clk_mux_sel *sel;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val = clk_readl(c->reg);
-                        val &= ~0xf;
-                        val |= sel->value;
-                        if (c->refcnt)
-                                clk_enable(p);
-                        clk_writel(val, c->reg);
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
-        return -EINVAL;
-}
-static struct clk_ops tegra_audio_sync_clk_ops = {
-        .init       = tegra2_audio_sync_clk_init,
-        .enable     = tegra2_audio_sync_clk_enable,
-        .disable    = tegra2_audio_sync_clk_disable,
-        .set_parent = tegra2_audio_sync_clk_set_parent,
-};
-/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
-static void tegra2_cdev_clk_init(struct clk *c)
-{
-        /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
-         * currently done in the pinmux code. */
-        c->state = ON;
-        BUG_ON(!c->u.periph.clk_num);
-        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
-                        PERIPH_CLK_TO_ENB_BIT(c)))
-                c->state = OFF;
-}
-static int tegra2_cdev_clk_enable(struct clk *c)
-{
-        BUG_ON(!c->u.periph.clk_num);
-        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
-        return 0;
-}
-static void tegra2_cdev_clk_disable(struct clk *c)
-{
-        BUG_ON(!c->u.periph.clk_num);
-        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
-}
-static struct clk_ops tegra_cdev_clk_ops = {
-        .init                   = &tegra2_cdev_clk_init,
-        .enable                 = &tegra2_cdev_clk_enable,
-        .disable                = &tegra2_cdev_clk_disable,
-};
-/* shared bus ops */
-/*
- * Some clocks may have multiple downstream users that need to request a
- * higher clock rate.  Shared bus clocks provide a unique shared_bus_user
- * clock to each user.  The frequency of the bus is set to the highest
- * enabled shared_bus_user clock, with a minimum value set by the
- * shared bus.
- */
-static int tegra_clk_shared_bus_update(struct clk *bus)
-{
-        struct clk *c;
-        unsigned long rate = bus->min_rate;
-        list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node)
-                if (c->u.shared_bus_user.enabled)
-                        rate = max(c->u.shared_bus_user.rate, rate);
-        if (rate == clk_get_rate_locked(bus))
-                return 0;
-        return clk_set_rate_locked(bus, rate);
-};
-static void tegra_clk_shared_bus_init(struct clk *c)
-{
-        unsigned long flags;
-        c->max_rate = c->parent->max_rate;
-        c->u.shared_bus_user.rate = c->parent->max_rate;
-        c->state = OFF;
-        c->set = true;
-        spin_lock_irqsave(&c->parent->spinlock, flags);
-        list_add_tail(&c->u.shared_bus_user.node,
-                &c->parent->shared_bus_list);
-        spin_unlock_irqrestore(&c->parent->spinlock, flags);
-}
-static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
-{
-        unsigned long flags;
-        int ret;
-        long new_rate = rate;
-        new_rate = clk_round_rate(c->parent, new_rate);
-        if (new_rate < 0)
-                return new_rate;
-        spin_lock_irqsave(&c->parent->spinlock, flags);
-        c->u.shared_bus_user.rate = new_rate;
-        ret = tegra_clk_shared_bus_update(c->parent);
-        spin_unlock_irqrestore(&c->parent->spinlock, flags);
-        return ret;
-}
-static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
-{
-        return clk_round_rate(c->parent, rate);
-}
-static int tegra_clk_shared_bus_enable(struct clk *c)
-{
-        unsigned long flags;
-        int ret;
-        spin_lock_irqsave(&c->parent->spinlock, flags);
-        c->u.shared_bus_user.enabled = true;
-        ret = tegra_clk_shared_bus_update(c->parent);
-        spin_unlock_irqrestore(&c->parent->spinlock, flags);
-        return ret;
-}
-static void tegra_clk_shared_bus_disable(struct clk *c)
-{
-        unsigned long flags;
-        int ret;
-        spin_lock_irqsave(&c->parent->spinlock, flags);
-        c->u.shared_bus_user.enabled = false;
-        ret = tegra_clk_shared_bus_update(c->parent);
-        WARN_ON_ONCE(ret);
-        spin_unlock_irqrestore(&c->parent->spinlock, flags);
-}
-static struct clk_ops tegra_clk_shared_bus_ops = {
-        .init = tegra_clk_shared_bus_init,
-        .enable = tegra_clk_shared_bus_enable,
-        .disable = tegra_clk_shared_bus_disable,
-        .set_rate = tegra_clk_shared_bus_set_rate,
-        .round_rate = tegra_clk_shared_bus_round_rate,
-};
-/* Clock definitions */
-static struct clk tegra_clk_32k = {
-        .name = "clk_32k",
-        .rate = 32768,
-        .ops  = NULL,
-        .max_rate = 32768,
-};
-static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
-        {32768, 12000000, 366, 1, 1, 0},
-        {32768, 13000000, 397, 1, 1, 0},
-        {32768, 19200000, 586, 1, 1, 0},
-        {32768, 26000000, 793, 1, 1, 0},
-        {0, 0, 0, 0, 0, 0},
-};
-static struct clk tegra_pll_s = {
-        .name      = "pll_s",
-        .flags     = PLL_ALT_MISC_REG,
-        .ops       = &tegra_pll_ops,
-        .parent    = &tegra_clk_32k,
-        .max_rate  = 26000000,
-        .reg       = 0xf0,
-        .u.pll = {
-                .input_min = 32768,
-                .input_max = 32768,
-                .cf_min    = 0, /* FIXME */
-                .cf_max    = 0, /* FIXME */
-                .vco_min   = 12000000,
-                .vco_max   = 26000000,
-                .freq_table = tegra_pll_s_freq_table,
-                .lock_delay = 300,
-        },
-};
-static struct clk_mux_sel tegra_clk_m_sel[] = {
-        { .input = &tegra_clk_32k, .value = 0},
-        { .input = &tegra_pll_s,  .value = 1},
-        { NULL , 0},
-};
-static struct clk tegra_clk_m = {
-        .name      = "clk_m",
-        .flags     = ENABLE_ON_INIT,
-        .ops       = &tegra_clk_m_ops,
-        .inputs    = tegra_clk_m_sel,
-        .reg       = 0x1fc,
-        .reg_shift = 28,
-        .max_rate  = 26000000,
-};
-static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
-        { 12000000, 600000000, 600, 12, 1, 8 },
-        { 13000000, 600000000, 600, 13, 1, 8 },
-        { 19200000, 600000000, 500, 16, 1, 6 },
-        { 26000000, 600000000, 600, 26, 1, 8 },
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_c = {
-        .name      = "pll_c",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0x80,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 600000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_c_freq_table,
-                .lock_delay = 300,
-        },
-};
-static struct clk tegra_pll_c_out1 = {
-        .name      = "pll_c_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_c,
-        .reg       = 0x84,
-        .reg_shift = 0,
-        .max_rate  = 600000000,
-};
-static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
-        { 12000000, 666000000, 666, 12, 1, 8},
-        { 13000000, 666000000, 666, 13, 1, 8},
-        { 19200000, 666000000, 555, 16, 1, 8},
-        { 26000000, 666000000, 666, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_m = {
-        .name      = "pll_m",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0x90,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 800000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1200000000,
-                .freq_table = tegra_pll_m_freq_table,
-                .lock_delay = 300,
-        },
-};
-static struct clk tegra_pll_m_out1 = {
-        .name      = "pll_m_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_m,
-        .reg       = 0x94,
-        .reg_shift = 0,
-        .max_rate  = 600000000,
-};
-static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
-        { 12000000, 216000000, 432, 12, 2, 8},
-        { 13000000, 216000000, 432, 13, 2, 8},
-        { 19200000, 216000000, 90,   4, 2, 1},
-        { 26000000, 216000000, 432, 26, 2, 8},
-        { 12000000, 432000000, 432, 12, 1, 8},
-        { 13000000, 432000000, 432, 13, 1, 8},
-        { 19200000, 432000000, 90,   4, 1, 1},
-        { 26000000, 432000000, 432, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_p = {
-        .name      = "pll_p",
-        .flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xa0,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 432000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_p_freq_table,
-                .lock_delay = 300,
-        },
-};
-static struct clk tegra_pll_p_out1 = {
-        .name      = "pll_p_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa4,
-        .reg_shift = 0,
-        .max_rate  = 432000000,
-};
-static struct clk tegra_pll_p_out2 = {
-        .name      = "pll_p_out2",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa4,
-        .reg_shift = 16,
-        .max_rate  = 432000000,
-};
-static struct clk tegra_pll_p_out3 = {
-        .name      = "pll_p_out3",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa8,
-        .reg_shift = 0,
-        .max_rate  = 432000000,
-};
-static struct clk tegra_pll_p_out4 = {
-        .name      = "pll_p_out4",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa8,
-        .reg_shift = 16,
-        .max_rate  = 432000000,
-};
-static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
-        { 28800000, 56448000, 49, 25, 1, 1},
-        { 28800000, 73728000, 64, 25, 1, 1},
-        { 28800000, 24000000,  5,  6, 1, 1},
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_a = {
-        .name      = "pll_a",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xb0,
-        .parent    = &tegra_pll_p_out1,
-        .max_rate  = 73728000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_a_freq_table,
-                .lock_delay = 300,
-        },
-};
-static struct clk tegra_pll_a_out0 = {
-        .name      = "pll_a_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_a,
-        .reg       = 0xb4,
-        .reg_shift = 0,
-        .max_rate  = 73728000,
-};
-static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
-        { 12000000, 216000000, 216, 12, 1, 4},
-        { 13000000, 216000000, 216, 13, 1, 4},
-        { 19200000, 216000000, 135, 12, 1, 3},
-        { 26000000, 216000000, 216, 26, 1, 4},
-        { 12000000, 594000000, 594, 12, 1, 8},
-        { 13000000, 594000000, 594, 13, 1, 8},
-        { 19200000, 594000000, 495, 16, 1, 8},
-        { 26000000, 594000000, 594, 26, 1, 8},
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_d = {
-        .name      = "pll_d",
-        .flags     = PLL_HAS_CPCON | PLLD,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xd0,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 1000000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 40000000,
-                .vco_max   = 1000000000,
-                .freq_table = tegra_pll_d_freq_table,
-                .lock_delay = 1000,
-        },
-};
-static struct clk tegra_pll_d_out0 = {
-        .name      = "pll_d_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_2 | PLLD,
-        .parent    = &tegra_pll_d,
-        .max_rate  = 500000000,
-};
-static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
-        { 12000000, 480000000, 960, 12, 2, 0},
-        { 13000000, 480000000, 960, 13, 2, 0},
-        { 19200000, 480000000, 200, 4,  2, 0},
-        { 26000000, 480000000, 960, 26, 2, 0},
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_u = {
-        .name      = "pll_u",
-        .flags     = PLLU,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xc0,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 480000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 480000000,
-                .vco_max   = 960000000,
-                .freq_table = tegra_pll_u_freq_table,
-                .lock_delay = 1000,
-        },
-};
-static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
-        /* 1 GHz */
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
-        /* 912 MHz */
-        { 12000000, 912000000,  912,  12, 1, 12},
-        { 13000000, 912000000,  912,  13, 1, 12},
-        { 19200000, 912000000,  760,  16, 1, 8},
-        { 26000000, 912000000,  912,  26, 1, 12},
-        /* 816 MHz */
-        { 12000000, 816000000,  816,  12, 1, 12},
-        { 13000000, 816000000,  816,  13, 1, 12},
-        { 19200000, 816000000,  680,  16, 1, 8},
-        { 26000000, 816000000,  816,  26, 1, 12},
-        /* 760 MHz */
-        { 12000000, 760000000,  760,  12, 1, 12},
-        { 13000000, 760000000,  760,  13, 1, 12},
-        { 19200000, 760000000,  950,  24, 1, 8},
-        { 26000000, 760000000,  760,  26, 1, 12},
-        /* 750 MHz */
-        { 12000000, 750000000,  750,  12, 1, 12},
-        { 13000000, 750000000,  750,  13, 1, 12},
-        { 19200000, 750000000,  625,  16, 1, 8},
-        { 26000000, 750000000,  750,  26, 1, 12},
-        /* 608 MHz */
-        { 12000000, 608000000,  608,  12, 1, 12},
-        { 13000000, 608000000,  608,  13, 1, 12},
-        { 19200000, 608000000,  380,  12, 1, 8},
-        { 26000000, 608000000,  608,  26, 1, 12},
-        /* 456 MHz */
-        { 12000000, 456000000,  456,  12, 1, 12},
-        { 13000000, 456000000,  456,  13, 1, 12},
-        { 19200000, 456000000,  380,  16, 1, 8},
-        { 26000000, 456000000,  456,  26, 1, 12},
-        /* 312 MHz */
-        { 12000000, 312000000,  312,  12, 1, 12},
-        { 13000000, 312000000,  312,  13, 1, 12},
-        { 19200000, 312000000,  260,  16, 1, 8},
-        { 26000000, 312000000,  312,  26, 1, 12},
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_x = {
-        .name      = "pll_x",
-        .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
-        .ops       = &tegra_pllx_ops,
-        .reg       = 0xe0,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 1000000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1200000000,
-                .freq_table = tegra_pll_x_freq_table,
-                .lock_delay = 300,
-        },
-};
-static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
-        { 12000000, 100000000,  200,  24, 1, 0 },
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_e = {
-        .name      = "pll_e",
-        .flags     = PLL_ALT_MISC_REG,
-        .ops       = &tegra_plle_ops,
-        .parent    = &tegra_clk_m,
-        .reg       = 0xe8,
-        .max_rate  = 100000000,
-        .u.pll = {
-                .input_min = 12000000,
-                .input_max = 12000000,
-                .freq_table = tegra_pll_e_freq_table,
-        },
-};
-static struct clk tegra_clk_d = {
-        .name      = "clk_d",
-        .flags     = PERIPH_NO_RESET,
-        .ops       = &tegra_clk_double_ops,
-        .reg       = 0x34,
-        .reg_shift = 12,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 52000000,
-        .u.periph  = {
-                .clk_num = 90,
-        },
-};
-/* dap_mclk1, belongs to the cdev1 pingroup. */
-static struct clk tegra_clk_cdev1 = {
-        .name      = "cdev1",
-        .ops       = &tegra_cdev_clk_ops,
-        .rate      = 26000000,
-        .max_rate  = 26000000,
-        .u.periph  = {
-                .clk_num = 94,
-        },
-};
-/* dap_mclk2, belongs to the cdev2 pingroup. */
-static struct clk tegra_clk_cdev2 = {
-        .name      = "cdev2",
-        .ops       = &tegra_cdev_clk_ops,
-        .rate      = 26000000,
-        .max_rate  = 26000000,
-        .u.periph  = {
-                .clk_num   = 93,
-        },
-};
-/* initialized before peripheral clocks */
-static struct clk_mux_sel mux_audio_sync_clk[8+1];
-static const struct audio_sources {
-        const char *name;
-        int value;
-} mux_audio_sync_clk_sources[] = {
-        { .name = "spdif_in", .value = 0 },
-        { .name = "i2s1", .value = 1 },
-        { .name = "i2s2", .value = 2 },
-        { .name = "pll_a_out0", .value = 4 },
-#if 0 /* FIXME: not implemented */
-        { .name = "ac97", .value = 3 },
-        { .name = "ext_audio_clk2", .value = 5 },
-        { .name = "ext_audio_clk1", .value = 6 },
-        { .name = "ext_vimclk", .value = 7 },
-#endif
-        { NULL, 0 }
-};
-static struct clk tegra_clk_audio = {
-        .name      = "audio",
-        .inputs    = mux_audio_sync_clk,
-        .reg       = 0x38,
-        .max_rate  = 73728000,
-        .ops       = &tegra_audio_sync_clk_ops
-};
-static struct clk tegra_clk_audio_2x = {
-        .name      = "audio_2x",
-        .flags     = PERIPH_NO_RESET,
-        .max_rate  = 48000000,
-        .ops       = &tegra_clk_double_ops,
-        .reg       = 0x34,
-        .reg_shift = 8,
-        .parent    = &tegra_clk_audio,
-        .u.periph = {
-                .clk_num = 89,
-        },
-};
-static struct clk_lookup tegra_audio_clk_lookups[] = {
-        { .con_id = "audio", .clk = &tegra_clk_audio },
-        { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
-};
-/* This is called after peripheral clocks are initialized, as the
- * audio_sync clock depends on some of the peripheral clocks.
- */
-static void init_audio_sync_clock_mux(void)
-{
-        int i;
-        struct clk_mux_sel *sel = mux_audio_sync_clk;
-        const struct audio_sources *src = mux_audio_sync_clk_sources;
-        struct clk_lookup *lookup;
-        for (i = 0; src->name; i++, sel++, src++) {
-                sel->input = tegra_get_clock_by_name(src->name);
-                if (!sel->input)
-                        pr_err("%s: could not find clk %s\n", __func__,
-                                src->name);
-                sel->value = src->value;
-        }
-        lookup = tegra_audio_clk_lookups;
-        for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
-                clk_init(lookup->clk);
-                clkdev_add(lookup);
-        }
-}
-static struct clk_mux_sel mux_cclk[] = {
-        { .input = &tegra_clk_m,        .value = 0},
-        { .input = &tegra_pll_c,        .value = 1},
-        { .input = &tegra_clk_32k,      .value = 2},
-        { .input = &tegra_pll_m,        .value = 3},
-        { .input = &tegra_pll_p,        .value = 4},
-        { .input = &tegra_pll_p_out4,   .value = 5},
-        { .input = &tegra_pll_p_out3,   .value = 6},
-        { .input = &tegra_clk_d,        .value = 7},
-        { .input = &tegra_pll_x,        .value = 8},
-        { NULL, 0},
-};
-static struct clk_mux_sel mux_sclk[] = {
-        { .input = &tegra_clk_m,        .value = 0},
-        { .input = &tegra_pll_c_out1,   .value = 1},
-        { .input = &tegra_pll_p_out4,   .value = 2},
-        { .input = &tegra_pll_p_out3,   .value = 3},
-        { .input = &tegra_pll_p_out2,   .value = 4},
-        { .input = &tegra_clk_d,        .value = 5},
-        { .input = &tegra_clk_32k,      .value = 6},
-        { .input = &tegra_pll_m_out1,   .value = 7},
-        { NULL, 0},
-};
-static struct clk tegra_clk_cclk = {
-        .name   = "cclk",
-        .inputs = mux_cclk,
-        .reg    = 0x20,
-        .ops    = &tegra_super_ops,
-        .max_rate = 1000000000,
-};
-static struct clk tegra_clk_sclk = {
-        .name   = "sclk",
-        .inputs = mux_sclk,
-        .reg    = 0x28,
-        .ops    = &tegra_super_ops,
-        .max_rate = 240000000,
-        .min_rate = 120000000,
-};
-static struct clk tegra_clk_virtual_cpu = {
-        .name      = "cpu",
-        .parent    = &tegra_clk_cclk,
-        .ops       = &tegra_cpu_ops,
-        .max_rate  = 1000000000,
-        .u.cpu = {
-                .main      = &tegra_pll_x,
-                .backup    = &tegra_pll_p,
-        },
-};
-static struct clk tegra_clk_cop = {
-        .name      = "cop",
-        .parent    = &tegra_clk_sclk,
-        .ops       = &tegra_cop_ops,
-        .max_rate  = 240000000,
-};
-static struct clk tegra_clk_hclk = {
-        .name           = "hclk",
-        .flags          = DIV_BUS,
-        .parent         = &tegra_clk_sclk,
-        .reg            = 0x30,
-        .reg_shift      = 4,
-        .ops            = &tegra_bus_ops,
-        .max_rate       = 240000000,
-};
-static struct clk tegra_clk_pclk = {
-        .name           = "pclk",
-        .flags          = DIV_BUS,
-        .parent         = &tegra_clk_hclk,
-        .reg            = 0x30,
-        .reg_shift      = 0,
-        .ops            = &tegra_bus_ops,
-        .max_rate       = 120000000,
-};
-static struct clk tegra_clk_blink = {
-        .name           = "blink",
-        .parent         = &tegra_clk_32k,
-        .reg            = 0x40,
-        .ops            = &tegra_blink_clk_ops,
-        .max_rate       = 32768,
-};
-static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
-        { .input = &tegra_pll_m, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_p, .value = 2},
-        { .input = &tegra_pll_a_out0, .value = 3},
-        { NULL, 0},
-};
-static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
-        { .input = &tegra_pll_m, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_p, .value = 2},
-        { .input = &tegra_clk_m, .value = 3},
-        { NULL, 0},
-};
-static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
-        { .input = &tegra_pll_p, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_m, .value = 2},
-        { .input = &tegra_clk_m, .value = 3},
-        { NULL, 0},
-};
-static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
-        {.input = &tegra_pll_a_out0, .value = 0},
-        {.input = &tegra_clk_audio_2x, .value = 1},
-        {.input = &tegra_pll_p, .value = 2},
-        {.input = &tegra_clk_m, .value = 3},
-        { NULL, 0},
-};
-static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
-        {.input = &tegra_pll_p, .value = 0},
-        {.input = &tegra_pll_d_out0, .value = 1},
-        {.input = &tegra_pll_c, .value = 2},
-        {.input = &tegra_clk_m, .value = 3},
-        { NULL, 0},
-};
-static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_clk_audio,     .value = 2},
-        {.input = &tegra_clk_m,     .value = 3},
-        {.input = &tegra_clk_32k,   .value = 4},
-        { NULL, 0},
-};
-static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_pll_m,     .value = 2},
-        { NULL, 0},
-};
-static struct clk_mux_sel mux_clk_m[] = {
-        { .input = &tegra_clk_m, .value = 0},
-        { NULL, 0},
-};
-static struct clk_mux_sel mux_pllp_out3[] = {
-        { .input = &tegra_pll_p_out3, .value = 0},
-        { NULL, 0},
-};
-static struct clk_mux_sel mux_plld[] = {
-        { .input = &tegra_pll_d, .value = 0},
-        { NULL, 0},
-};
-static struct clk_mux_sel mux_clk_32k[] = {
-        { .input = &tegra_clk_32k, .value = 0},
-        { NULL, 0},
-};
-static struct clk_mux_sel mux_pclk[] = {
-        { .input = &tegra_clk_pclk, .value = 0},
-        { NULL, 0},
-};
-static struct clk tegra_clk_emc = {
-        .name = "emc",
-        .ops = &tegra_emc_clk_ops,
-        .reg = 0x19c,
-        .max_rate = 800000000,
-        .inputs = mux_pllm_pllc_pllp_clkm,
-        .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
-        .u.periph = {
-                .clk_num = 57,
-        },
-};
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = &tegra_periph_clk_ops,     \
-                .reg       = _reg,                      \
-                .inputs    = _inputs,                   \
-                .flags     = _flags,                    \
-                .max_rate  = _max,                      \
-                .u.periph = {                           \
-                        .clk_num   = _clk_num,          \
-                },                                      \
-        }
-#define SHARED_CLK(_name, _dev, _con, _parent)          \
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = &tegra_clk_shared_bus_ops, \
-                .parent = _parent,                      \
-        }
-static struct clk tegra_list_clks[] = {
-        PERIPH_CLK("apbdma",    "tegra-apbdma",         NULL,   34,     0,      108000000, mux_pclk,                    0),
-        PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET),
-        PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("i2s1",      "tegra20-i2s.0",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
-        PERIPH_CLK("i2s2",      "tegra20-i2s.1",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
-        PERIPH_CLK("spdif_out", "spdif_out",            NULL,   10,     0x108,  100000000, mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
-        PERIPH_CLK("spdif_in",  "spdif_in",             NULL,   10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71),
-        PERIPH_CLK("pwm",       "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_audio_clkm_clk32,      MUX | DIV_U71 | MUX_PWM),
-        PERIPH_CLK("spi",       "spi",                  NULL,   43,     0x114,  40000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("xio",       "xio",                  NULL,   45,     0x120,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("twc",       "twc",                  NULL,   16,     0x12c,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sbc1",      "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sbc2",      "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sbc3",      "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sbc4",      "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("ide",       "ide",                  NULL,   25,     0x144,  100000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("ndflash",   "tegra_nand",           NULL,   13,     0x160,  164000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sdmmc1",    "sdhci-tegra.0",        NULL,   14,     0x150,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc2",    "sdhci-tegra.1",        NULL,   9,      0x154,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc3",    "sdhci-tegra.2",        NULL,   69,     0x1bc,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc4",    "sdhci-tegra.3",        NULL,   15,     0x164,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("vcp",       "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("bsea",      "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("bsev",      "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("vde",       "tegra-avp",            "vde",  61,     0x1c8,  250000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("csite",     "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* max rate ??? */
-        /* FIXME: what is la? */
-        PERIPH_CLK("la",        "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("owr",       "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("nor",       "nor",                  NULL,   42,     0x1d0,  92000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("mipi",      "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("i2c1",      "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
-        PERIPH_CLK("i2c2",      "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
-        PERIPH_CLK("i2c3",      "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
-        PERIPH_CLK("dvc",       "tegra-i2c.3",          NULL,   47,     0x128,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
-        PERIPH_CLK("i2c1_i2c",  "tegra-i2c.0",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
-        PERIPH_CLK("i2c2_i2c",  "tegra-i2c.1",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
-        PERIPH_CLK("i2c3_i2c",  "tegra-i2c.2",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
-        PERIPH_CLK("dvc_i2c",   "tegra-i2c.3",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
-        PERIPH_CLK("uarta",     "tegra-uart.0",         NULL,   6,      0x178,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uartb",     "tegra-uart.1",         NULL,   7,      0x17c,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uartc",     "tegra-uart.2",         NULL,   55,     0x1a0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uartd",     "tegra-uart.3",         NULL,   65,     0x1c0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uarte",     "tegra-uart.4",         NULL,   66,     0x1c4,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
-        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("vi",        "tegra_camera",         "vi",   20,     0x148,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("vi_sensor", "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
-        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("mpe",       "mpe",                  NULL,   60,     0x170,  250000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("host1x",    "host1x",               NULL,   28,     0x180,  166000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("cve",       "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("tvo",       "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("hdmi",      "hdmi",                 NULL,   51,     0x18c,  600000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("tvdac",     "tvdac",                NULL,   53,     0x194,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("disp1",     "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_plld_pllc_clkm,     MUX), /* scales with voltage and process_id */
-        PERIPH_CLK("disp2",     "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_plld_pllc_clkm,     MUX), /* scales with voltage and process_id */
-        PERIPH_CLK("usbd",      "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("usb2",      "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("usb3",      "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("dsi",       "dsi",                  NULL,   48,     0,      500000000, mux_plld,                    0), /* scales with voltage */
-        PERIPH_CLK("csi",       "tegra_camera",         "csi",  52,     0,      72000000,  mux_pllp_out3,               0),
-        PERIPH_CLK("isp",       "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
-        PERIPH_CLK("csus",      "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
-        PERIPH_CLK("pex",       NULL,                   "pex",  70,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET),
-        PERIPH_CLK("afi",       NULL,                   "afi",  72,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET),
-        PERIPH_CLK("pcie_xclk", NULL,             "pcie_xclk",  74,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET),
-        SHARED_CLK("avp.sclk",  "tegra-avp",            "sclk", &tegra_clk_sclk),
-        SHARED_CLK("avp.emc",   "tegra-avp",            "emc",  &tegra_clk_emc),
-        SHARED_CLK("cpu.emc",   "cpu",                  "emc",  &tegra_clk_emc),
-        SHARED_CLK("disp1.emc", "tegradc.0",            "emc",  &tegra_clk_emc),
-        SHARED_CLK("disp2.emc", "tegradc.1",            "emc",  &tegra_clk_emc),
-        SHARED_CLK("hdmi.emc",  "hdmi",                 "emc",  &tegra_clk_emc),
-        SHARED_CLK("host.emc",  "tegra_grhost",         "emc",  &tegra_clk_emc),
-        SHARED_CLK("usbd.emc",  "fsl-tegra-udc",        "emc",  &tegra_clk_emc),
-        SHARED_CLK("usb1.emc",  "tegra-ehci.0",         "emc",  &tegra_clk_emc),
-        SHARED_CLK("usb2.emc",  "tegra-ehci.1",         "emc",  &tegra_clk_emc),
-        SHARED_CLK("usb3.emc",  "tegra-ehci.2",         "emc",  &tegra_clk_emc),
-};
-#define CLK_DUPLICATE(_name, _dev, _con)                \
-        {                                               \
-                .name   = _name,                        \
-                .lookup = {                             \
-                        .dev_id = _dev,                 \
-                        .con_id         = _con,         \
-                },                                      \
-        }
-/* Some clocks may be used by different drivers depending on the board
- * configuration.  List those here to register them twice in the clock lookup
- * table under two names.
- */
-static struct clk_duplicate tegra_clk_duplicates[] = {
-        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
-        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
-        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
-        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
-        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
-        CLK_DUPLICATE("usbd", "utmip-pad", NULL),
-        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
-        CLK_DUPLICATE("usbd", "tegra-otg", NULL),
-        CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
-        CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
-        CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
-        CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
-        CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
-        CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
-        CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
-        CLK_DUPLICATE("cop", "tegra-avp", "cop"),
-        CLK_DUPLICATE("vde", "tegra-aes", "vde"),
-};
-#define CLK(dev, con, ck)       \
-        {                       \
-                .dev_id = dev,  \
-                .con_id = con,  \
-                .clk = ck,      \
-        }
-static struct clk *tegra_ptr_clks[] = {
-        &tegra_clk_32k,
-        &tegra_pll_s,
-        &tegra_clk_m,
-        &tegra_pll_m,
-        &tegra_pll_m_out1,
-        &tegra_pll_c,
-        &tegra_pll_c_out1,
-        &tegra_pll_p,
-        &tegra_pll_p_out1,
-        &tegra_pll_p_out2,
-        &tegra_pll_p_out3,
-        &tegra_pll_p_out4,
-        &tegra_pll_a,
-        &tegra_pll_a_out0,
-        &tegra_pll_d,
-        &tegra_pll_d_out0,
-        &tegra_pll_u,
-        &tegra_pll_x,
-        &tegra_pll_e,
-        &tegra_clk_cclk,
-        &tegra_clk_sclk,
-        &tegra_clk_hclk,
-        &tegra_clk_pclk,
-        &tegra_clk_d,
-        &tegra_clk_cdev1,
-        &tegra_clk_cdev2,
-        &tegra_clk_virtual_cpu,
-        &tegra_clk_blink,
-        &tegra_clk_cop,
-        &tegra_clk_emc,
-};
-static void tegra2_init_one_clock(struct clk *c)
-{
-        clk_init(c);
-        INIT_LIST_HEAD(&c->shared_bus_list);
-        if (!c->lookup.dev_id && !c->lookup.con_id)
-                c->lookup.con_id = c->name;
-        c->lookup.clk = c;
-        clkdev_add(&c->lookup);
-}
-void __init tegra2_init_clocks(void)
-{
-        int i;
-        struct clk *c;
-        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
-                tegra2_init_one_clock(tegra_ptr_clks[i]);
-        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
-                tegra2_init_one_clock(&tegra_list_clks[i]);
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
-                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
-                if (!c) {
-                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
-                                tegra_clk_duplicates[i].name);
-                        continue;
-                }
-                tegra_clk_duplicates[i].lookup.clk = c;
-                clkdev_add(&tegra_clk_duplicates[i].lookup);
-        }
-        init_audio_sync_clock_mux();
-}
-#ifdef CONFIG_PM
-static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
-                           PERIPH_CLK_SOURCE_NUM + 22];
-void tegra_clk_suspend(void)
-{
-        unsigned long off, i;
-        u32 *ctx = clk_rst_suspend;
-        *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
-        *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
-        *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
-        *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
-        *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
-        *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
-        *ctx++ = clk_readl(tegra_pll_m_out1.reg);
-        *ctx++ = clk_readl(tegra_pll_a_out0.reg);
-        *ctx++ = clk_readl(tegra_pll_c_out1.reg);
-        *ctx++ = clk_readl(tegra_clk_cclk.reg);
-        *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
-        *ctx++ = clk_readl(tegra_clk_sclk.reg);
-        *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
-        *ctx++ = clk_readl(tegra_clk_pclk.reg);
-        *ctx++ = clk_readl(tegra_clk_audio.reg);
-        for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
-                        off += 4) {
-                if (off == PERIPH_CLK_SOURCE_EMC)
-                        continue;
-                *ctx++ = clk_readl(off);
-        }
-        off = RST_DEVICES;
-        for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
-                *ctx++ = clk_readl(off);
-        off = CLK_OUT_ENB;
-        for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
-                *ctx++ = clk_readl(off);
-        *ctx++ = clk_readl(MISC_CLK_ENB);
-        *ctx++ = clk_readl(CLK_MASK_ARM);
-        BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
-}
-void tegra_clk_resume(void)
-{
-        unsigned long off, i;
-        const u32 *ctx = clk_rst_suspend;
-        u32 val;
-        val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
-        val |= *ctx++;
-        clk_writel(val, OSC_CTRL);
-        clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
-        clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
-        clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
-        clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
-        clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
-        udelay(1000);
-        clk_writel(*ctx++, tegra_pll_m_out1.reg);
-        clk_writel(*ctx++, tegra_pll_a_out0.reg);
-        clk_writel(*ctx++, tegra_pll_c_out1.reg);
-        clk_writel(*ctx++, tegra_clk_cclk.reg);
-        clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
-        clk_writel(*ctx++, tegra_clk_sclk.reg);
-        clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
-        clk_writel(*ctx++, tegra_clk_pclk.reg);
-        clk_writel(*ctx++, tegra_clk_audio.reg);
-        /* enable all clocks before configuring clock sources */
-        clk_writel(0xbffffff9ul, CLK_OUT_ENB);
-        clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
-        clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
-        wmb();
-        for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
-                        off += 4) {
-                if (off == PERIPH_CLK_SOURCE_EMC)
-                        continue;
-                clk_writel(*ctx++, off);
-        }
-        wmb();
-        off = RST_DEVICES;
-        for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
-                clk_writel(*ctx++, off);
-        wmb();
-        off = CLK_OUT_ENB;
-        for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
-                clk_writel(*ctx++, off);
-        wmb();
-        clk_writel(*ctx++, MISC_CLK_ENB);
-        clk_writel(*ctx++, CLK_MASK_ARM);
-}
-#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 6674f100e16f..5cd502c27163 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -1,7 +1,7 @@
 /*
 * arch/arm/mach-tegra/tegra30_clocks.c
 *
- * Copyright (c) 2010-2011 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -35,6 +35,7 @@
 #include "clock.h"
 #include "fuse.h"
+#include "tegra_cpu_car.h"
 #define USE_PLL_LOCK_BITS 0
@@ -299,6 +300,16 @@
 /* FIXME: recommended safety delay after lock is detected */
 #define PLL_POST_LOCK_DELAY             100
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX          0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET      0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR      0x344
+#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR    0x34c
+#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
+#define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
+#define CPU_RESET(cpu)  (0x1111ul << (cpu))
 /**
 * Structure defining the fields for USB UTMI clocks Parameters.
 */
@@ -365,30 +376,32 @@ static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
 static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
 #define clk_writel(value, reg) \
-        __raw_writel(value, (u32)reg_clk_base + (reg))
+        __raw_writel(value, reg_clk_base + (reg))
 #define clk_readl(reg) \
-        __raw_readl((u32)reg_clk_base + (reg))
+        __raw_readl(reg_clk_base + (reg))
 #define pmc_writel(value, reg) \
-        __raw_writel(value, (u32)reg_pmc_base + (reg))
+        __raw_writel(value, reg_pmc_base + (reg))
 #define pmc_readl(reg) \
-        __raw_readl((u32)reg_pmc_base + (reg))
+        __raw_readl(reg_pmc_base + (reg))
 #define chipid_readl() \
-        __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV)
+        __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)
 #define clk_writel_delay(value, reg)                                    \
        do {                                                            \
-                __raw_writel((value), (u32)reg_clk_base + (reg));       \
+                __raw_writel((value), reg_clk_base + (reg));    \
                udelay(2);                                              \
        } while (0)
+static inline int clk_set_div(struct clk_tegra *c, u32 n)
-static inline int clk_set_div(struct clk *c, u32 n)
 {
-        return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n);
+        struct clk *clk = c->hw.clk;
+        return clk_set_rate(clk,
+                        (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n);
 }
 static inline u32 periph_clk_to_reg(
-        struct clk *c, u32 reg_L, u32 reg_V, int offs)
+        struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs)
 {
        u32 reg = c->u.periph.clk_num / 32;
        BUG_ON(reg >= RST_DEVICES_NUM);
@@ -470,15 +483,32 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
        return divider_u16 - 1;
 }
+static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        return to_clk_tegra(hw)->fixed_rate;
+}
+struct clk_ops tegra30_clk_32k_ops = {
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
+};
 /* clk_m functions */
-static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
+static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        if (!to_clk_tegra(hw)->fixed_rate)
+                to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
+        return to_clk_tegra(hw)->fixed_rate;
+}
+static void tegra30_clk_m_init(struct clk_hw *hw)
 {
        u32 osc_ctrl = clk_readl(OSC_CTRL);
        u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
        u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
-        c->rate = clk_measure_input_freq();
+        switch (to_clk_tegra(hw)->fixed_rate) {
-        switch (c->rate) {
        case 12000000:
                auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
@@ -508,46 +538,44 @@ static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
                break;
        default:
-                pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
+                pr_err("%s: Unexpected clock rate %ld", __func__,
+                                to_clk_tegra(hw)->fixed_rate);
                BUG();
        }
        clk_writel(auto_clock_control, OSC_CTRL);
-        return c->rate;
 }
-static void tegra30_clk_m_init(struct clk *c)
+struct clk_ops tegra30_clk_m_ops = {
-{
+        .init = tegra30_clk_m_init,
-        pr_debug("%s on clock %s\n", __func__, c->name);
+        .recalc_rate = tegra30_clk_m_recalc_rate,
-        tegra30_clk_m_autodetect_rate(c);
+};
-}
-static int tegra30_clk_m_enable(struct clk *c)
+static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
 {
-        pr_debug("%s on clock %s\n", __func__, c->name);
+        struct clk_tegra *c = to_clk_tegra(hw);
-        return 0;
+        u64 rate = parent_rate;
-}
-static void tegra30_clk_m_disable(struct clk *c)
+        if (c->mul != 0 && c->div != 0) {
-{
+                rate *= c->mul;
-        pr_debug("%s on clock %s\n", __func__, c->name);
+                rate += c->div - 1; /* round up */
-        WARN(1, "Attempting to disable main SoC clock\n");
+                do_div(rate, c->div);
-}
+        }
-static struct clk_ops tegra_clk_m_ops = {
+        return rate;
-        .init           = tegra30_clk_m_init,
+}
-        .enable         = tegra30_clk_m_enable,
-        .disable        = tegra30_clk_m_disable,
-};
-static struct clk_ops tegra_clk_m_div_ops = {
+struct clk_ops tegra_clk_m_div_ops = {
-        .enable         = tegra30_clk_m_enable,
+        .recalc_rate = tegra30_clk_m_div_recalc_rate,
 };
 /* PLL reference divider functions */
-static void tegra30_pll_ref_init(struct clk *c)
+static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw,
+                        unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long rate = parent_rate;
        u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
-        pr_debug("%s on clock %s\n", __func__, c->name);
        switch (pll_ref_div) {
        case OSC_CTRL_PLL_REF_DIV_1:
@@ -564,13 +592,18 @@ static void tegra30_pll_ref_init(struct clk *c)
                BUG();
        }
        c->mul = 1;
-        c->state = ON;
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
 }
-static struct clk_ops tegra_pll_ref_ops = {
+struct clk_ops tegra_pll_ref_ops = {
-        .init           = tegra30_pll_ref_init,
+        .recalc_rate = tegra30_pll_ref_recalc_rate,
-        .enable         = tegra30_clk_m_enable,
-        .disable        = tegra30_clk_m_disable,
 };
 /* super clock functions */
@@ -581,56 +614,50 @@ static struct clk_ops tegra_pll_ref_ops = {
 * only when its parent is a fixed rate PLL, since we can't change PLL rate
 * in this case.
 */
-static void tegra30_super_clk_init(struct clk *c)
+static void tegra30_super_clk_init(struct clk_hw *hw)
 {
-        u32 val;
+        struct clk_tegra *c = to_clk_tegra(hw);
-        int source;
+        struct clk_tegra *p =
-        int shift;
+                        to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk)));
-        const struct clk_mux_sel *sel;
-        val = clk_readl(c->reg + SUPER_CLK_MUX);
-        c->state = ON;
-        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        source = (val >> shift) & SUPER_SOURCE_MASK;
-        if (c->flags & DIV_2)
-                source |= val & SUPER_LP_DIV2_BYPASS;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->value == source)
-                        break;
-        }
-        BUG_ON(sel->input == NULL);
-        c->parent = sel->input;
+        c->state = ON;
        if (c->flags & DIV_U71) {
                /* Init safe 7.1 divider value (does not affect PLLX path) */
                clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
                           c->reg + SUPER_CLK_DIVIDER);
                c->mul = 2;
                c->div = 2;
-                if (!(c->parent->flags & PLLX))
+                if (!(p->flags & PLLX))
                        c->div += SUPER_CLOCK_DIV_U71_MIN;
        } else
                clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
 }
-static int tegra30_super_clk_enable(struct clk *c)
+static u8 tegra30_super_clk_get_parent(struct clk_hw *hw)
 {
-        return 0;
+        struct clk_tegra *c = to_clk_tegra(hw);
-}
+        u32 val;
+        int source;
+        int shift;
-static void tegra30_super_clk_disable(struct clk *c)
+        val = clk_readl(c->reg + SUPER_CLK_MUX);
-{
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-        /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-           geared up g-mode super clock - mode switch may request to disable
+        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-           either of them; accept request with no affect on h/w */
+                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+        source = (val >> shift) & SUPER_SOURCE_MASK;
+        if (c->flags & DIV_2)
+                source |= val & SUPER_LP_DIV2_BYPASS;
+        return source;
 }
-static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+        struct clk_tegra *p =
+                        to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk)));
        u32 val;
-        const struct clk_mux_sel *sel;
        int shift;
        val = clk_readl(c->reg + SUPER_CLK_MUX);
@@ -638,48 +665,36 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        /* For LP mode super-clock switch between PLLX direct
-                           and divided-by-2 outputs is allowed only when other
-                           than PLLX clock source is current parent */
-                        if ((c->flags & DIV_2) && (p->flags & PLLX) &&
-                            ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
-                                if (c->parent->flags & PLLX)
-                                        return -EINVAL;
-                                val ^= SUPER_LP_DIV2_BYPASS;
-                                clk_writel_delay(val, c->reg);
-                        }
-                        val &= ~(SUPER_SOURCE_MASK << shift);
-                        val |= (sel->value & SUPER_SOURCE_MASK) << shift;
-                        /* 7.1 divider for CPU super-clock does not affect
-                           PLLX path */
-                        if (c->flags & DIV_U71) {
-                                u32 div = 0;
-                                if (!(p->flags & PLLX)) {
-                                        div = clk_readl(c->reg +
-                                                        SUPER_CLK_DIVIDER);
-                                        div &= SUPER_CLOCK_DIV_U71_MASK;
-                                        div >>= SUPER_CLOCK_DIV_U71_SHIFT;
-                                }
-                                c->div = div + 2;
-                                c->mul = 2;
-                        }
-                        if (c->refcnt)
-                                clk_enable(p);
-                        clk_writel_delay(val, c->reg);
-                        if (c->refcnt && c->parent)
+        /* For LP mode super-clock switch between PLLX direct
-                                clk_disable(c->parent);
+           and divided-by-2 outputs is allowed only when other
+           than PLLX clock source is current parent */
+        if ((c->flags & DIV_2) && (p->flags & PLLX) &&
+            ((index ^ val) & SUPER_LP_DIV2_BYPASS)) {
+                if (p->flags & PLLX)
+                        return -EINVAL;
+                val ^= SUPER_LP_DIV2_BYPASS;
+                clk_writel_delay(val, c->reg);
+        }
+        val &= ~(SUPER_SOURCE_MASK << shift);
+        val |= (index & SUPER_SOURCE_MASK) << shift;
-                        clk_reparent(c, p);
+        /* 7.1 divider for CPU super-clock does not affect
-                        return 0;
+           PLLX path */
+        if (c->flags & DIV_U71) {
+                u32 div = 0;
+                if (!(p->flags & PLLX)) {
+                        div = clk_readl(c->reg +
+                                        SUPER_CLK_DIVIDER);
+                        div &= SUPER_CLOCK_DIV_U71_MASK;
+                        div >>= SUPER_CLOCK_DIV_U71_SHIFT;
                }
+                c->div = div + 2;
+                c->mul = 2;
        }
-        return -EINVAL;
+        clk_writel_delay(val, c->reg);
+        return 0;
 }
 /*
@@ -691,10 +706,15 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
 * rate of this PLL can't be changed, and it has many other children. In
 * this case use 7.1 fractional divider to adjust the super clock rate.
 */
-static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
-        if ((c->flags & DIV_U71) && (c->parent->flags & PLL_FIXED)) {
+        struct clk_tegra *c = to_clk_tegra(hw);
-                int div = clk_div71_get_divider(c->parent->u.pll.fixed_rate,
+        struct clk *parent = __clk_get_parent(hw->clk);
+        struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
+        if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
+                int div = clk_div71_get_divider(parent_rate,
                                        rate, c->flags, ROUND_DIVIDER_DOWN);
                div = max(div, SUPER_CLOCK_DIV_U71_MIN);
@@ -704,55 +724,86 @@ static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
                c->mul = 2;
                return 0;
        }
-        return clk_set_rate(c->parent, rate);
+        return 0;
+}
+static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
 }
-static struct clk_ops tegra_super_ops = {
+static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-        .init                   = tegra30_super_clk_init,
+                                unsigned long *prate)
-        .enable                 = tegra30_super_clk_enable,
+{
-        .disable                = tegra30_super_clk_disable,
+        struct clk_tegra *c = to_clk_tegra(hw);
-        .set_parent             = tegra30_super_clk_set_parent,
+        struct clk *parent = __clk_get_parent(hw->clk);
-        .set_rate               = tegra30_super_clk_set_rate,
+        struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
+        int mul = 2;
+        int div;
+        if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
+                div = clk_div71_get_divider(*prate,
+                                rate, c->flags, ROUND_DIVIDER_DOWN);
+                div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2;
+                rate = *prate * mul;
+                rate += div - 1; /* round up */
+                do_div(rate, c->div);
+                return rate;
+        }
+        return *prate;
+}
+struct clk_ops tegra30_super_ops = {
+        .init = tegra30_super_clk_init,
+        .set_parent = tegra30_super_clk_set_parent,
+        .get_parent = tegra30_super_clk_get_parent,
+        .recalc_rate = tegra30_super_clk_recalc_rate,
+        .round_rate = tegra30_super_clk_round_rate,
+        .set_rate = tegra30_super_clk_set_rate,
 };
-static int tegra30_twd_clk_set_rate(struct clk *c, unsigned long rate)
+static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
 {
-        /* The input value 'rate' is the clock rate of the CPU complex. */
+        struct clk_tegra *c = to_clk_tegra(hw);
-        c->rate = (rate * c->mul) / c->div;
+        u64 rate = parent_rate;
-        return 0;
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
 }
-static struct clk_ops tegra30_twd_ops = {
+struct clk_ops tegra30_twd_ops = {
-        .set_rate       = tegra30_twd_clk_set_rate,
+        .recalc_rate = tegra30_twd_clk_recalc_rate,
 };
 /* Blink output functions */
+static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
-static void tegra30_blink_clk_init(struct clk *c)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
        val = pmc_readl(PMC_CTRL);
        c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
-        c->mul = 1;
+        return c->state;
-        val = pmc_readl(c->reg);
-        if (val & PMC_BLINK_TIMER_ENB) {
-                unsigned int on_off;
-                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
-                        PMC_BLINK_TIMER_DATA_ON_MASK;
-                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
-                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
-                on_off += val;
-                /* each tick in the blink timer is 4 32KHz clocks */
-                c->div = on_off * 4;
-        } else {
-                c->div = 1;
-        }
 }
-static int tegra30_blink_clk_enable(struct clk *c)
+static int tegra30_blink_clk_enable(struct clk_hw *hw)
 {
        u32 val;
@@ -765,7 +816,7 @@ static int tegra30_blink_clk_enable(struct clk *c)
        return 0;
 }
-static void tegra30_blink_clk_disable(struct clk *c)
+static void tegra30_blink_clk_disable(struct clk_hw *hw)
 {
        u32 val;
@@ -776,9 +827,11 @@ static void tegra30_blink_clk_disable(struct clk *c)
        pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
 }
-static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
-        unsigned long parent_rate = clk_get_rate(c->parent);
+        struct clk_tegra *c = to_clk_tegra(hw);
        if (rate >= parent_rate) {
                c->div = 1;
                pmc_writel(0, c->reg);
@@ -801,41 +854,77 @@ static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
        return 0;
 }
-static struct clk_ops tegra_blink_clk_ops = {
+static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw,
-        .init                   = &tegra30_blink_clk_init,
+                unsigned long parent_rate)
-        .enable                 = &tegra30_blink_clk_enable,
+{
-        .disable                = &tegra30_blink_clk_disable,
+        struct clk_tegra *c = to_clk_tegra(hw);
-        .set_rate               = &tegra30_blink_clk_set_rate,
+        u64 rate = parent_rate;
-};
+        u32 val;
+        u32 mul;
+        u32 div;
+        u32 on_off;
-/* PLL Functions */
+        mul = 1;
-static int tegra30_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg,
+        val = pmc_readl(c->reg);
-                                         u32 lock_bit)
+        if (val & PMC_BLINK_TIMER_ENB) {
+                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
+                        PMC_BLINK_TIMER_DATA_ON_MASK;
+                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+                on_off += val;
+                /* each tick in the blink timer is 4 32KHz clocks */
+                div = on_off * 4;
+        } else {
+                div = 1;
+        }
+        if (mul != 0 && div != 0) {
+                rate *= mul;
+                rate += div - 1; /* round up */
+                do_div(rate, div);
+        }
+        return rate;
+}
+static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
 {
-#if USE_PLL_LOCK_BITS
+        int div;
-        int i;
+        int mul;
-        for (i = 0; i < c->u.pll.lock_delay; i++) {
+        long round_rate = *prate;
-                if (clk_readl(lock_reg) & lock_bit) {
-                        udelay(PLL_POST_LOCK_DELAY);
+        mul = 1;
-                        return 0;
-                }
+        if (rate >= *prate) {
-                udelay(2);              /* timeout = 2 * lock time */
+                div = 1;
+        } else {
+                div = DIV_ROUND_UP(*prate / 8, rate);
+                div *= 8;
        }
-        pr_err("Timed out waiting for lock bit on pll %s", c->name);
-        return -1;
-#endif
-        udelay(c->u.pll.lock_delay);
-        return 0;
+        round_rate *= mul;
+        round_rate += div - 1;
+        do_div(round_rate, div);
+        return round_rate;
 }
+struct clk_ops tegra30_blink_clk_ops = {
+        .is_enabled = tegra30_blink_clk_is_enabled,
+        .enable = tegra30_blink_clk_enable,
+        .disable = tegra30_blink_clk_disable,
+        .recalc_rate = tegra30_blink_clk_recalc_rate,
+        .round_rate = tegra30_blink_clk_round_rate,
+        .set_rate = tegra30_blink_clk_set_rate,
+};
-static void tegra30_utmi_param_configure(struct clk *c)
+static void tegra30_utmi_param_configure(struct clk_hw *hw)
 {
+        unsigned long main_rate =
+                __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
        u32 reg;
        int i;
-        unsigned long main_rate =
-                clk_get_rate(c->parent->parent);
        for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
                if (main_rate == utmi_parameters[i].osc_frequency)
@@ -886,50 +975,52 @@ static void tegra30_utmi_param_configure(struct clk *c)
        clk_writel(reg, UTMIP_PLL_CFG1);
 }
-static void tegra30_pll_clk_init(struct clk *c)
+/* PLL Functions */
+static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg,
+                                         u32 lock_bit)
+{
+        int ret = 0;
+#if USE_PLL_LOCK_BITS
+        int i;
+        for (i = 0; i < c->u.pll.lock_delay; i++) {
+                if (clk_readl(lock_reg) & lock_bit) {
+                        udelay(PLL_POST_LOCK_DELAY);
+                        return 0;
+                }
+                udelay(2);      /* timeout = 2 * lock time */
+        }
+        pr_err("Timed out waiting for lock bit on pll %s",
+                                        __clk_get_name(hw->clk));
+        ret = -1;
+#else
+        udelay(c->u.pll.lock_delay);
+#endif
+        return ret;
+}
+static int tegra30_pll_clk_is_enabled(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val = clk_readl(c->reg + PLL_BASE);
        c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+        return c->state;
+}
-        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
+static void tegra30_pll_clk_init(struct clk_hw *hw)
-                const struct clk_pll_freq_table *sel;
+{
-                unsigned long input_rate = clk_get_rate(c->parent);
+        struct clk_tegra *c = to_clk_tegra(hw);
-                for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
-                        if (sel->input_rate == input_rate &&
-                                sel->output_rate == c->u.pll.fixed_rate) {
-                                c->mul = sel->n;
-                                c->div = sel->m * sel->p;
-                                return;
-                        }
-                }
-                pr_err("Clock %s has unknown fixed frequency\n", c->name);
-                BUG();
-        } else if (val & PLL_BASE_BYPASS) {
-                c->mul = 1;
-                c->div = 1;
-        } else {
-                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
-                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
-                if (c->flags & PLLU)
-                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
-                else
-                        c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
-                                        PLL_BASE_DIVP_SHIFT));
-                if (c->flags & PLL_FIXED) {
-                        unsigned long rate = clk_get_rate_locked(c);
-                        BUG_ON(rate != c->u.pll.fixed_rate);
-                }
-        }
        if (c->flags & PLLU)
-                tegra30_utmi_param_configure(c);
+                tegra30_utmi_param_configure(hw);
 }
-static int tegra30_pll_clk_enable(struct clk *c)
+static int tegra30_pll_clk_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
 #if USE_PLL_LOCK_BITS
        val = clk_readl(c->reg + PLL_MISC(c));
@@ -952,10 +1043,11 @@ static int tegra30_pll_clk_enable(struct clk *c)
        return 0;
 }
-static void tegra30_pll_clk_disable(struct clk *c)
+static void tegra30_pll_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
        val = clk_readl(c->reg);
        val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
@@ -968,36 +1060,36 @@ static void tegra30_pll_clk_disable(struct clk *c)
        }
 }
-static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val, p_div, old_base;
        unsigned long input_rate;
        const struct clk_pll_freq_table *sel;
        struct clk_pll_freq_table cfg;
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
        if (c->flags & PLL_FIXED) {
                int ret = 0;
                if (rate != c->u.pll.fixed_rate) {
                        pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
-                               __func__, c->name, c->u.pll.fixed_rate, rate);
+                               __func__, __clk_get_name(hw->clk),
+                                c->u.pll.fixed_rate, rate);
                        ret = -EINVAL;
                }
                return ret;
        }
        if (c->flags & PLLM) {
-                if (rate != clk_get_rate_locked(c)) {
+                if (rate != __clk_get_rate(hw->clk)) {
                        pr_err("%s: Can not change memory %s rate in flight\n",
-                               __func__, c->name);
+                                __func__, __clk_get_name(hw->clk));
                        return -EINVAL;
                }
-                return 0;
        }
        p_div = 0;
-        input_rate = clk_get_rate(c->parent);
+        input_rate = parent_rate;
        /* Check if the target rate is tabulated */
        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
@@ -1055,7 +1147,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
                    (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
                    (cfg.output_rate > c->u.pll.vco_max)) {
                        pr_err("%s: Failed to set %s out-of-table rate %lu\n",
-                               __func__, c->name, rate);
+                               __func__, __clk_get_name(hw->clk), rate);
                        return -EINVAL;
                }
                p_div <<= PLL_BASE_DIVP_SHIFT;
@@ -1073,7 +1165,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
                return 0;
        if (c->state == ON) {
-                tegra30_pll_clk_disable(c);
+                tegra30_pll_clk_disable(hw);
                val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
        }
        clk_writel(val, c->reg + PLL_BASE);
@@ -1095,21 +1187,149 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
        }
        if (c->state == ON)
-                tegra30_pll_clk_enable(c);
+                tegra30_pll_clk_enable(hw);
+        c->u.pll.fixed_rate = rate;
        return 0;
 }
-static struct clk_ops tegra_pll_ops = {
+static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
-        .init                   = tegra30_pll_clk_init,
+                                unsigned long *prate)
-        .enable                 = tegra30_pll_clk_enable,
+{
-        .disable                = tegra30_pll_clk_disable,
+        struct clk_tegra *c = to_clk_tegra(hw);
-        .set_rate               = tegra30_pll_clk_set_rate,
+        unsigned long input_rate = *prate;
+        unsigned long output_rate = *prate;
+        const struct clk_pll_freq_table *sel;
+        struct clk_pll_freq_table cfg;
+        int mul;
+        int div;
+        u32 p_div;
+        u32 val;
+        if (c->flags & PLL_FIXED)
+                return c->u.pll.fixed_rate;
+        if (c->flags & PLLM)
+                return __clk_get_rate(hw->clk);
+        p_div = 0;
+        /* Check if the target rate is tabulated */
+        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                if (sel->input_rate == input_rate && sel->output_rate == rate) {
+                        if (c->flags & PLLU) {
+                                BUG_ON(sel->p < 1 || sel->p > 2);
+                                if (sel->p == 1)
+                                        p_div = PLLU_BASE_POST_DIV;
+                        } else {
+                                BUG_ON(sel->p < 1);
+                                for (val = sel->p; val > 1; val >>= 1)
+                                        p_div++;
+                                p_div <<= PLL_BASE_DIVP_SHIFT;
+                        }
+                        break;
+                }
+        }
+        if (sel->input_rate == 0) {
+                unsigned long cfreq;
+                BUG_ON(c->flags & PLLU);
+                sel = &cfg;
+                switch (input_rate) {
+                case 12000000:
+                case 26000000:
+                        cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
+                        break;
+                case 13000000:
+                        cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
+                        break;
+                case 16800000:
+                case 19200000:
+                        cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
+                        break;
+                default:
+                        pr_err("%s: Unexpected reference rate %lu\n",
+                               __func__, input_rate);
+                        BUG();
+                }
+                /* Raise VCO to guarantee 0.5% accuracy */
+                for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
+                      cfg.output_rate <<= 1)
+                        p_div++;
+                cfg.p = 0x1 << p_div;
+                cfg.m = input_rate / cfreq;
+                cfg.n = cfg.output_rate / cfreq;
+        }
+        mul = sel->n;
+        div = sel->m * sel->p;
+        output_rate *= mul;
+        output_rate += div - 1; /* round up */
+        do_div(output_rate, div);
+        return output_rate;
+}
+static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+        u32 val = clk_readl(c->reg + PLL_BASE);
+        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
+                const struct clk_pll_freq_table *sel;
+                for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                        if (sel->input_rate == parent_rate &&
+                                sel->output_rate == c->u.pll.fixed_rate) {
+                                c->mul = sel->n;
+                                c->div = sel->m * sel->p;
+                                break;
+                        }
+                }
+                pr_err("Clock %s has unknown fixed frequency\n",
+                                                __clk_get_name(hw->clk));
+                BUG();
+        } else if (val & PLL_BASE_BYPASS) {
+                c->mul = 1;
+                c->div = 1;
+        } else {
+                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+                if (c->flags & PLLU)
+                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
+                else
+                        c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
+                                        PLL_BASE_DIVP_SHIFT));
+        }
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+struct clk_ops tegra30_pll_ops = {
+        .is_enabled = tegra30_pll_clk_is_enabled,
+        .init = tegra30_pll_clk_init,
+        .enable = tegra30_pll_clk_enable,
+        .disable = tegra30_pll_clk_disable,
+        .recalc_rate = tegra30_pll_recalc_rate,
+        .round_rate = tegra30_pll_round_rate,
+        .set_rate = tegra30_pll_clk_set_rate,
 };
-static int
+int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
-tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+                                enum tegra_clk_ex_param p, u32 setting)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val, mask, reg;
        switch (p) {
@@ -1141,41 +1361,27 @@ tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
        return 0;
 }
-static struct clk_ops tegra_plld_ops = {
+static int tegra30_plle_clk_is_enabled(struct clk_hw *hw)
-        .init                   = tegra30_pll_clk_init,
-        .enable                 = tegra30_pll_clk_enable,
-        .disable                = tegra30_pll_clk_disable,
-        .set_rate               = tegra30_pll_clk_set_rate,
-        .clk_cfg_ex             = tegra30_plld_clk_cfg_ex,
-};
-static void tegra30_plle_clk_init(struct clk *c)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
-        val = clk_readl(PLLE_AUX);
-        c->parent = (val & PLLE_AUX_PLLP_SEL) ?
-                tegra_get_clock_by_name("pll_p") :
-                tegra_get_clock_by_name("pll_ref");
        val = clk_readl(c->reg + PLL_BASE);
        c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
-        c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
+        return c->state;
-        c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
-        c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
 }
-static void tegra30_plle_clk_disable(struct clk *c)
+static void tegra30_plle_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
        val = clk_readl(c->reg + PLL_BASE);
        val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
        clk_writel(val, c->reg + PLL_BASE);
 }
-static void tegra30_plle_training(struct clk *c)
+static void tegra30_plle_training(struct clk_tegra *c)
 {
        u32 val;
@@ -1198,12 +1404,15 @@ static void tegra30_plle_training(struct clk *c)
        } while (!(val & PLLE_MISC_READY));
 }
-static int tegra30_plle_configure(struct clk *c, bool force_training)
+static int tegra30_plle_configure(struct clk_hw *hw, bool force_training)
 {
-        u32 val;
+        struct clk_tegra *c = to_clk_tegra(hw);
+        struct clk *parent = __clk_get_parent(hw->clk);
        const struct clk_pll_freq_table *sel;
+        u32 val;
        unsigned long rate = c->u.pll.fixed_rate;
-        unsigned long input_rate = clk_get_rate(c->parent);
+        unsigned long input_rate = __clk_get_rate(parent);
        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
                if (sel->input_rate == input_rate && sel->output_rate == rate)
@@ -1214,7 +1423,7 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
                return -ENOSYS;
        /* disable PLLE, clear setup fiels */
-        tegra30_plle_clk_disable(c);
+        tegra30_plle_clk_disable(hw);
        val = clk_readl(c->reg + PLL_MISC(c));
        val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
@@ -1252,52 +1461,64 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
        return 0;
 }
-static int tegra30_plle_clk_enable(struct clk *c)
+static int tegra30_plle_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        return tegra30_plle_configure(hw, !c->set);
+}
+static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long parent_rate)
 {
-        pr_debug("%s on clock %s\n", __func__, c->name);
+        struct clk_tegra *c = to_clk_tegra(hw);
-        return tegra30_plle_configure(c, !c->set);
+        unsigned long rate = parent_rate;
+        u32 val;
+        val = clk_readl(c->reg + PLL_BASE);
+        c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
+        c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
+        c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
 }
-static struct clk_ops tegra_plle_ops = {
+struct clk_ops tegra30_plle_ops = {
-        .init                   = tegra30_plle_clk_init,
+        .is_enabled = tegra30_plle_clk_is_enabled,
-        .enable                 = tegra30_plle_clk_enable,
+        .enable = tegra30_plle_clk_enable,
-        .disable                = tegra30_plle_clk_disable,
+        .disable = tegra30_plle_clk_disable,
+        .recalc_rate = tegra30_plle_clk_recalc_rate,
 };
 /* Clock divider ops */
-static void tegra30_pll_div_clk_init(struct clk *c)
+static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        if (c->flags & DIV_U71) {
-                u32 divu71;
                u32 val = clk_readl(c->reg);
                val >>= c->reg_shift;
                c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
                if (!(val & PLL_OUT_RESET_DISABLE))
                        c->state = OFF;
-                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
-                c->div = (divu71 + 2);
-                c->mul = 2;
-        } else if (c->flags & DIV_2) {
-                c->state = ON;
-                if (c->flags & (PLLD | PLLX)) {
-                        c->div = 2;
-                        c->mul = 1;
-                } else
-                        BUG();
        } else {
                c->state = ON;
-                c->div = 1;
-                c->mul = 1;
        }
+        return c->state;
 }
-static int tegra30_pll_div_clk_enable(struct clk *c)
+static int tegra30_pll_div_clk_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
        u32 new_val;
-        pr_debug("%s: %s\n", __func__, c->name);
+        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
        if (c->flags & DIV_U71) {
                val = clk_readl(c->reg);
                new_val = val >> c->reg_shift;
@@ -1315,12 +1536,13 @@ static int tegra30_pll_div_clk_enable(struct clk *c)
        return -EINVAL;
 }
-static void tegra30_pll_div_clk_disable(struct clk *c)
+static void tegra30_pll_div_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
        u32 new_val;
-        pr_debug("%s: %s\n", __func__, c->name);
+        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
        if (c->flags & DIV_U71) {
                val = clk_readl(c->reg);
                new_val = val >> c->reg_shift;
@@ -1334,14 +1556,14 @@ static void tegra30_pll_div_clk_disable(struct clk *c)
        }
 }
-static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
        u32 new_val;
        int divider_u71;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
        if (c->flags & DIV_U71) {
                divider_u71 = clk_div71_get_divider(
                        parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
@@ -1359,19 +1581,59 @@ static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
                        clk_writel_delay(val, c->reg);
                        c->div = divider_u71 + 2;
                        c->mul = 2;
+                        c->fixed_rate = rate;
                        return 0;
                }
-        } else if (c->flags & DIV_2)
+        } else if (c->flags & DIV_2) {
-                return clk_set_rate(c->parent, rate * 2);
+                c->fixed_rate = rate;
+                return 0;
+        }
        return -EINVAL;
 }
-static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
+static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+        if (c->flags & DIV_U71) {
+                u32 divu71;
+                u32 val = clk_readl(c->reg);
+                val >>= c->reg_shift;
+                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
+                c->div = (divu71 + 2);
+                c->mul = 2;
+        } else if (c->flags & DIV_2) {
+                if (c->flags & (PLLD | PLLX)) {
+                        c->div = 2;
+                        c->mul = 1;
+                } else
+                        BUG();
+        } else {
+                c->div = 1;
+                c->mul = 1;
+        }
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw,
+                                unsigned long rate, unsigned long *prate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
        int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+        if (prate)
+                parent_rate = *prate;
        if (c->flags & DIV_U71) {
                divider = clk_div71_get_divider(
@@ -1379,23 +1641,25 @@ static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
                if (divider < 0)
                        return divider;
                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
-        } else if (c->flags & DIV_2)
+        } else if (c->flags & DIV_2) {
-                /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */
+                *prate = rate * 2;
                return rate;
+        }
        return -EINVAL;
 }
-static struct clk_ops tegra_pll_div_ops = {
+struct clk_ops tegra30_pll_div_ops = {
-        .init                   = tegra30_pll_div_clk_init,
+        .is_enabled = tegra30_pll_div_clk_is_enabled,
-        .enable                 = tegra30_pll_div_clk_enable,
+        .enable = tegra30_pll_div_clk_enable,
-        .disable                = tegra30_pll_div_clk_disable,
+        .disable = tegra30_pll_div_clk_disable,
-        .set_rate               = tegra30_pll_div_clk_set_rate,
+        .set_rate = tegra30_pll_div_clk_set_rate,
-        .round_rate             = tegra30_pll_div_clk_round_rate,
+        .recalc_rate = tegra30_pll_div_clk_recalc_rate,
+        .round_rate = tegra30_pll_div_clk_round_rate,
 };
 /* Periph clk ops */
-static inline u32 periph_clk_source_mask(struct clk *c)
+static inline u32 periph_clk_source_mask(struct clk_tegra *c)
 {
        if (c->flags & MUX8)
                return 7 << 29;
@@ -1409,7 +1673,7 @@ static inline u32 periph_clk_source_mask(struct clk *c)
                return 3 << 30;
 }
-static inline u32 periph_clk_source_shift(struct clk *c)
+static inline u32 periph_clk_source_shift(struct clk_tegra *c)
 {
        if (c->flags & MUX8)
                return 29;
@@ -1423,47 +1687,9 @@ static inline u32 periph_clk_source_shift(struct clk *c)
                return 30;
 }
-static void tegra30_periph_clk_init(struct clk *c)
+static int tegra30_periph_clk_is_enabled(struct clk_hw *hw)
 {
-        u32 val = clk_readl(c->reg);
+        struct clk_tegra *c = to_clk_tegra(hw);
-        const struct clk_mux_sel *mux = 0;
-        const struct clk_mux_sel *sel;
-        if (c->flags & MUX) {
-                for (sel = c->inputs; sel->input != NULL; sel++) {
-                        if (((val & periph_clk_source_mask(c)) >>
-                            periph_clk_source_shift(c)) == sel->value)
-                                mux = sel;
-                }
-                BUG_ON(!mux);
-                c->parent = mux->input;
-        } else {
-                c->parent = c->inputs[0].input;
-        }
-        if (c->flags & DIV_U71) {
-                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
-                if ((c->flags & DIV_U71_UART) &&
-                    (!(val & PERIPH_CLK_UART_DIV_ENB))) {
-                        divu71 = 0;
-                }
-                if (c->flags & DIV_U71_IDLE) {
-                        val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
-                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
-                        val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
-                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
-                        clk_writel(val, c->reg);
-                }
-                c->div = divu71 + 2;
-                c->mul = 2;
-        } else if (c->flags & DIV_U16) {
-                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
-                c->div = divu16 + 1;
-                c->mul = 1;
-        } else {
-                c->div = 1;
-                c->mul = 1;
-        }
        c->state = ON;
        if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
@@ -1471,11 +1697,12 @@ static void tegra30_periph_clk_init(struct clk *c)
        if (!(c->flags & PERIPH_NO_RESET))
                if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
                        c->state = OFF;
+        return c->state;
 }
-static int tegra30_periph_clk_enable(struct clk *c)
+static int tegra30_periph_clk_enable(struct clk_hw *hw)
 {
-        pr_debug("%s on clock %s\n", __func__, c->name);
+        struct clk_tegra *c = to_clk_tegra(hw);
        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
@@ -1494,31 +1721,29 @@ static int tegra30_periph_clk_enable(struct clk *c)
        return 0;
 }
-static void tegra30_periph_clk_disable(struct clk *c)
+static void tegra30_periph_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        unsigned long val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        if (c->refcnt)
+        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
-                tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
+        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
+                return;
-        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) {
+        /* If peripheral is in the APB bus then read the APB bus to
-                /* If peripheral is in the APB bus then read the APB bus to
+         * flush the write operation in apb bus. This will avoid the
-                 * flush the write operation in apb bus. This will avoid the
+         * peripheral access after disabling clock*/
-                 * peripheral access after disabling clock*/
+        if (c->flags & PERIPH_ON_APB)
-                if (c->flags & PERIPH_ON_APB)
+                val = chipid_readl();
-                        val = chipid_readl();
-                clk_writel_delay(
+        clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
-                        PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
-        }
 }
-static void tegra30_periph_clk_reset(struct clk *c, bool assert)
+void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        unsigned long val;
-        pr_debug("%s %s on clock %s\n", __func__,
-                 assert ? "assert" : "deassert", c->name);
        if (!(c->flags & PERIPH_NO_RESET)) {
                if (assert) {
@@ -1537,42 +1762,40 @@ static void tegra30_periph_clk_reset(struct clk *c, bool assert)
        }
 }
-static int tegra30_periph_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
-        const struct clk_mux_sel *sel;
-        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
        if (!(c->flags & MUX))
-                return (p == c->parent) ? 0 : (-EINVAL);
+                return (index == 0) ? 0 : (-EINVAL);
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val = clk_readl(c->reg);
-                        val &= ~periph_clk_source_mask(c);
-                        val |= (sel->value << periph_clk_source_shift(c));
-                        if (c->refcnt)
-                                clk_enable(p);
-                        clk_writel_delay(val, c->reg);
+        val = clk_readl(c->reg);
+        val &= ~periph_clk_source_mask(c);
+        val |= (index << periph_clk_source_shift(c));
+        clk_writel_delay(val, c->reg);
+        return 0;
+}
-                        if (c->refcnt && c->parent)
+static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw)
-                                clk_disable(c->parent);
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        int source  = (val & periph_clk_source_mask(c)) >>
+                                        periph_clk_source_shift(c);
-                        clk_reparent(c, p);
+        if (!(c->flags & MUX))
-                        return 0;
+                return 0;
-                }
-        }
-        return -EINVAL;
+        return source;
 }
-static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
        int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
        if (c->flags & DIV_U71) {
                divider = clk_div71_get_divider(
@@ -1611,12 +1834,15 @@ static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
        return -EINVAL;
 }
-static long tegra30_periph_clk_round_rate(struct clk *c,
+static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-        unsigned long rate)
+                                unsigned long *prate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
        int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+        if (prate)
+                parent_rate = *prate;
        if (c->flags & DIV_U71) {
                divider = clk_div71_get_divider(
@@ -1634,21 +1860,85 @@ static long tegra30_periph_clk_round_rate(struct clk *c,
        return -EINVAL;
 }
-static struct clk_ops tegra_periph_clk_ops = {
+static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw,
-        .init                   = &tegra30_periph_clk_init,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+        u32 val = clk_readl(c->reg);
+        if (c->flags & DIV_U71) {
+                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
+                if ((c->flags & DIV_U71_UART) &&
+                    (!(val & PERIPH_CLK_UART_DIV_ENB))) {
+                        divu71 = 0;
+                }
+                if (c->flags & DIV_U71_IDLE) {
+                        val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
+                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
+                        val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
+                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
+                        clk_writel(val, c->reg);
+                }
+                c->div = divu71 + 2;
+                c->mul = 2;
+        } else if (c->flags & DIV_U16) {
+                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
+                c->div = divu16 + 1;
+                c->mul = 1;
+        } else {
+                c->div = 1;
+                c->mul = 1;
+        }
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+struct clk_ops tegra30_periph_clk_ops = {
+        .is_enabled = tegra30_periph_clk_is_enabled,
+        .enable = tegra30_periph_clk_enable,
+        .disable = tegra30_periph_clk_disable,
+        .set_parent = tegra30_periph_clk_set_parent,
+        .get_parent = tegra30_periph_clk_get_parent,
+        .set_rate = tegra30_periph_clk_set_rate,
+        .round_rate = tegra30_periph_clk_round_rate,
+        .recalc_rate = tegra30_periph_clk_recalc_rate,
+};
+static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk *d = clk_get_sys(NULL, "pll_d");
+        /* The DSIB parent selection bit is in PLLD base
+           register - can not do direct r-m-w, must be
+           protected by PLLD lock */
+        tegra_clk_cfg_ex(
+                d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
+        return 0;
+}
+struct clk_ops tegra30_dsib_clk_ops = {
+        .is_enabled = tegra30_periph_clk_is_enabled,
        .enable                 = &tegra30_periph_clk_enable,
        .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_periph_clk_set_parent,
+        .set_parent             = &tegra30_dsib_clk_set_parent,
+        .get_parent             = &tegra30_periph_clk_get_parent,
        .set_rate               = &tegra30_periph_clk_set_rate,
        .round_rate             = &tegra30_periph_clk_round_rate,
-        .reset                  = &tegra30_periph_clk_reset,
+        .recalc_rate            = &tegra30_periph_clk_recalc_rate,
 };
 /* Periph extended clock configuration ops */
-static int
+int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
-tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+                                enum tegra_clk_ex_param p, u32 setting)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        if (p == TEGRA_CLK_VI_INP_SEL) {
                u32 val = clk_readl(c->reg);
                val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
@@ -1660,20 +1950,11 @@ tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
        return -EINVAL;
 }
-static struct clk_ops tegra_vi_clk_ops = {
+int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
-        .init                   = &tegra30_periph_clk_init,
+                                enum tegra_clk_ex_param p, u32 setting)
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_periph_clk_set_parent,
-        .set_rate               = &tegra30_periph_clk_set_rate,
-        .round_rate             = &tegra30_periph_clk_round_rate,
-        .clk_cfg_ex             = &tegra30_vi_clk_cfg_ex,
-        .reset                  = &tegra30_periph_clk_reset,
-};
-static int
-tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
                u32 val = clk_readl(c->reg);
                if (setting)
@@ -1686,21 +1967,11 @@ tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
        return -EINVAL;
 }
-static struct clk_ops tegra_nand_clk_ops = {
+int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
-        .init                   = &tegra30_periph_clk_init,
+                                enum tegra_clk_ex_param p, u32 setting)
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_periph_clk_set_parent,
-        .set_rate               = &tegra30_periph_clk_set_rate,
-        .round_rate             = &tegra30_periph_clk_round_rate,
-        .clk_cfg_ex             = &tegra30_nand_clk_cfg_ex,
-        .reset                  = &tegra30_periph_clk_reset,
-};
-static int
-tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        if (p == TEGRA_CLK_DTV_INVERT) {
                u32 val = clk_readl(c->reg);
                if (setting)
@@ -1713,91 +1984,27 @@ tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
        return -EINVAL;
 }
-static struct clk_ops tegra_dtv_clk_ops = {
-        .init                   = &tegra30_periph_clk_init,
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_periph_clk_set_parent,
-        .set_rate               = &tegra30_periph_clk_set_rate,
-        .round_rate             = &tegra30_periph_clk_round_rate,
-        .clk_cfg_ex             = &tegra30_dtv_clk_cfg_ex,
-        .reset                  = &tegra30_periph_clk_reset,
-};
-static int tegra30_dsib_clk_set_parent(struct clk *c, struct clk *p)
-{
-        const struct clk_mux_sel *sel;
-        struct clk *d = tegra_get_clock_by_name("pll_d");
-        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        if (c->refcnt)
-                                clk_enable(p);
-                        /* The DSIB parent selection bit is in PLLD base
-                           register - can not do direct r-m-w, must be
-                           protected by PLLD lock */
-                        tegra_clk_cfg_ex(
-                                d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
-        return -EINVAL;
-}
-static struct clk_ops tegra_dsib_clk_ops = {
-        .init                   = &tegra30_periph_clk_init,
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_dsib_clk_set_parent,
-        .set_rate               = &tegra30_periph_clk_set_rate,
-        .round_rate             = &tegra30_periph_clk_round_rate,
-        .reset                  = &tegra30_periph_clk_reset,
-};
-/* pciex clock support only reset function */
-static struct clk_ops tegra_pciex_clk_ops = {
-        .reset    = tegra30_periph_clk_reset,
-};
 /* Output clock ops */
 static DEFINE_SPINLOCK(clk_out_lock);
-static void tegra30_clk_out_init(struct clk *c)
+static int tegra30_clk_out_is_enabled(struct clk_hw *hw)
 {
-        const struct clk_mux_sel *mux = 0;
+        struct clk_tegra *c = to_clk_tegra(hw);
-        const struct clk_mux_sel *sel;
        u32 val = pmc_readl(c->reg);
        c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
        c->mul = 1;
        c->div = 1;
+        return c->state;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (((val & periph_clk_source_mask(c)) >>
-                     periph_clk_source_shift(c)) == sel->value)
-                        mux = sel;
-        }
-        BUG_ON(!mux);
-        c->parent = mux->input;
 }
-static int tegra30_clk_out_enable(struct clk *c)
+static int tegra30_clk_out_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
        unsigned long flags;
-        pr_debug("%s on clock %s\n", __func__, c->name);
        spin_lock_irqsave(&clk_out_lock, flags);
        val = pmc_readl(c->reg);
        val |= (0x1 << c->u.periph.clk_num);
@@ -1807,13 +2014,12 @@ static int tegra30_clk_out_enable(struct clk *c)
        return 0;
 }
-static void tegra30_clk_out_disable(struct clk *c)
+static void tegra30_clk_out_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
        unsigned long flags;
-        pr_debug("%s on clock %s\n", __func__, c->name);
        spin_lock_irqsave(&clk_out_lock, flags);
        val = pmc_readl(c->reg);
        val &= ~(0x1 << c->u.periph.clk_num);
@@ -1821,59 +2027,59 @@ static void tegra30_clk_out_disable(struct clk *c)
        spin_unlock_irqrestore(&clk_out_lock, flags);
 }
-static int tegra30_clk_out_set_parent(struct clk *c, struct clk *p)
+static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
        unsigned long flags;
-        const struct clk_mux_sel *sel;
-        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
+        spin_lock_irqsave(&clk_out_lock, flags);
+        val = pmc_readl(c->reg);
-        for (sel = c->inputs; sel->input != NULL; sel++) {
+        val &= ~periph_clk_source_mask(c);
-                if (sel->input == p) {
+        val |= (index << periph_clk_source_shift(c));
-                        if (c->refcnt)
+        pmc_writel(val, c->reg);
-                                clk_enable(p);
+        spin_unlock_irqrestore(&clk_out_lock, flags);
-                        spin_lock_irqsave(&clk_out_lock, flags);
+        return 0;
-                        val = pmc_readl(c->reg);
+}
-                        val &= ~periph_clk_source_mask(c);
-                        val |= (sel->value << periph_clk_source_shift(c));
-                        pmc_writel(val, c->reg);
-                        spin_unlock_irqrestore(&clk_out_lock, flags);
-                        if (c->refcnt && c->parent)
+static u8 tegra30_clk_out_get_parent(struct clk_hw *hw)
-                                clk_disable(c->parent);
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = pmc_readl(c->reg);
+        int source;
-                        clk_reparent(c, p);
+        source = (val & periph_clk_source_mask(c)) >>
-                        return 0;
+                                periph_clk_source_shift(c);
-                }
+        return source;
-        }
-        return -EINVAL;
 }
-static struct clk_ops tegra_clk_out_ops = {
+struct clk_ops tegra_clk_out_ops = {
-        .init                   = &tegra30_clk_out_init,
+        .is_enabled = tegra30_clk_out_is_enabled,
-        .enable                 = &tegra30_clk_out_enable,
+        .enable = tegra30_clk_out_enable,
-        .disable                = &tegra30_clk_out_disable,
+        .disable = tegra30_clk_out_disable,
-        .set_parent             = &tegra30_clk_out_set_parent,
+        .set_parent = tegra30_clk_out_set_parent,
+        .get_parent = tegra30_clk_out_get_parent,
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 /* Clock doubler ops */
-static void tegra30_clk_double_init(struct clk *c)
+static int tegra30_clk_double_is_enabled(struct clk_hw *hw)
 {
-        u32 val = clk_readl(c->reg);
+        struct clk_tegra *c = to_clk_tegra(hw);
-        c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
-        c->div = 1;
        c->state = ON;
        if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
                c->state = OFF;
+        return c->state;
 };
-static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
-        unsigned long parent_rate = clk_get_rate(c->parent);
        if (rate == parent_rate) {
                val = clk_readl(c->reg) | (0x1 << c->reg_shift);
                clk_writel(val, c->reg);
@@ -1890,1215 +2096,200 @@ static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
        return -EINVAL;
 }
-static struct clk_ops tegra_clk_double_ops = {
+static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw,
-        .init                   = &tegra30_clk_double_init,
+                unsigned long parent_rate)
-        .enable                 = &tegra30_periph_clk_enable,
+{
-        .disable                = &tegra30_periph_clk_disable,
+        struct clk_tegra *c = to_clk_tegra(hw);
-        .set_rate               = &tegra30_clk_double_set_rate,
+        u64 rate = parent_rate;
-};
-/* Audio sync clock ops */
+        u32 val = clk_readl(c->reg);
-static int tegra30_sync_source_set_rate(struct clk *c, unsigned long rate)
+        c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
+        c->div = 1;
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
 {
-        c->rate = rate;
+        unsigned long output_rate = *prate;
-        return 0;
+        do_div(output_rate, 2);
+        return output_rate;
 }
-static struct clk_ops tegra_sync_source_ops = {
+struct clk_ops tegra30_clk_double_ops = {
-        .set_rate               = &tegra30_sync_source_set_rate,
+        .is_enabled = tegra30_clk_double_is_enabled,
+        .enable = tegra30_periph_clk_enable,
+        .disable = tegra30_periph_clk_disable,
+        .recalc_rate = tegra30_clk_double_recalc_rate,
+        .round_rate = tegra30_clk_double_round_rate,
+        .set_rate = tegra30_clk_double_set_rate,
+};
+/* Audio sync clock ops */
+struct clk_ops tegra_sync_source_ops = {
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
-static void tegra30_audio_sync_clk_init(struct clk *c)
+static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw)
 {
-        int source;
+        struct clk_tegra *c = to_clk_tegra(hw);
-        const struct clk_mux_sel *sel;
        u32 val = clk_readl(c->reg);
        c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
-        source = val & AUDIO_SYNC_SOURCE_MASK;
+        return c->state;
-        for (sel = c->inputs; sel->input != NULL; sel++)
-                if (sel->value == source)
-                        break;
-        BUG_ON(sel->input == NULL);
-        c->parent = sel->input;
 }
-static int tegra30_audio_sync_clk_enable(struct clk *c)
+static int tegra30_audio_sync_clk_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val = clk_readl(c->reg);
        clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
        return 0;
 }
-static void tegra30_audio_sync_clk_disable(struct clk *c)
+static void tegra30_audio_sync_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val = clk_readl(c->reg);
        clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
 }
-static int tegra30_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val;
-        const struct clk_mux_sel *sel;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val = clk_readl(c->reg);
-                        val &= ~AUDIO_SYNC_SOURCE_MASK;
-                        val |= sel->value;
-                        if (c->refcnt)
-                                clk_enable(p);
-                        clk_writel(val, c->reg);
+        val = clk_readl(c->reg);
+        val &= ~AUDIO_SYNC_SOURCE_MASK;
+        val |= index;
-                        if (c->refcnt && c->parent)
+        clk_writel(val, c->reg);
-                                clk_disable(c->parent);
+        return 0;
+}
-                        clk_reparent(c, p);
+static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw)
-                        return 0;
+{
-                }
+        struct clk_tegra *c = to_clk_tegra(hw);
-        }
+        u32 val = clk_readl(c->reg);
+        int source;
-        return -EINVAL;
+        source = val & AUDIO_SYNC_SOURCE_MASK;
+        return source;
 }
-static struct clk_ops tegra_audio_sync_clk_ops = {
+struct clk_ops tegra30_audio_sync_clk_ops = {
-        .init       = tegra30_audio_sync_clk_init,
+        .is_enabled = tegra30_audio_sync_clk_is_enabled,
-        .enable     = tegra30_audio_sync_clk_enable,
+        .enable = tegra30_audio_sync_clk_enable,
-        .disable    = tegra30_audio_sync_clk_disable,
+        .disable = tegra30_audio_sync_clk_disable,
        .set_parent = tegra30_audio_sync_clk_set_parent,
+        .get_parent = tegra30_audio_sync_clk_get_parent,
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 /* cml0 (pcie), and cml1 (sata) clock ops */
-static void tegra30_cml_clk_init(struct clk *c)
+static int tegra30_cml_clk_is_enabled(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val = clk_readl(c->reg);
        c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
+        return c->state;
 }
-static int tegra30_cml_clk_enable(struct clk *c)
+static int tegra30_cml_clk_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val = clk_readl(c->reg);
        val |= (0x1 << c->u.periph.clk_num);
        clk_writel(val, c->reg);
        return 0;
 }
-static void tegra30_cml_clk_disable(struct clk *c)
+static void tegra30_cml_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
        u32 val = clk_readl(c->reg);
        val &= ~(0x1 << c->u.periph.clk_num);
        clk_writel(val, c->reg);
 }
-static struct clk_ops tegra_cml_clk_ops = {
+struct clk_ops tegra_cml_clk_ops = {
-        .init                   = &tegra30_cml_clk_init,
+        .is_enabled = tegra30_cml_clk_is_enabled,
-        .enable                 = &tegra30_cml_clk_enable,
+        .enable = tegra30_cml_clk_enable,
-        .disable                = &tegra30_cml_clk_disable,
+        .disable = tegra30_cml_clk_disable,
-};
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
-/* Clock definitions */
-static struct clk tegra_clk_32k = {
-        .name = "clk_32k",
-        .rate = 32768,
-        .ops  = NULL,
-        .max_rate = 32768,
-};
-static struct clk tegra_clk_m = {
-        .name      = "clk_m",
-        .flags     = ENABLE_ON_INIT,
-        .ops       = &tegra_clk_m_ops,
-        .reg       = 0x1fc,
-        .reg_shift = 28,
-        .max_rate  = 48000000,
-};
-static struct clk tegra_clk_m_div2 = {
-        .name      = "clk_m_div2",
-        .ops       = &tegra_clk_m_div_ops,
-        .parent    = &tegra_clk_m,
-        .mul       = 1,
-        .div       = 2,
-        .state     = ON,
-        .max_rate  = 24000000,
-};
-static struct clk tegra_clk_m_div4 = {
-        .name      = "clk_m_div4",
-        .ops       = &tegra_clk_m_div_ops,
-        .parent    = &tegra_clk_m,
-        .mul       = 1,
-        .div       = 4,
-        .state     = ON,
-        .max_rate  = 12000000,
-};
-static struct clk tegra_pll_ref = {
-        .name      = "pll_ref",
-        .flags     = ENABLE_ON_INIT,
-        .ops       = &tegra_pll_ref_ops,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 26000000,
-};
-static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
-        { 12000000, 1040000000, 520,  6, 1, 8},
-        { 13000000, 1040000000, 480,  6, 1, 8},
-        { 16800000, 1040000000, 495,  8, 1, 8},         /* actual: 1039.5 MHz */
-        { 19200000, 1040000000, 325,  6, 1, 6},
-        { 26000000, 1040000000, 520, 13, 1, 8},
-        { 12000000, 832000000, 416,  6, 1, 8},
-        { 13000000, 832000000, 832, 13, 1, 8},
-        { 16800000, 832000000, 396,  8, 1, 8},          /* actual: 831.6 MHz */
-        { 19200000, 832000000, 260,  6, 1, 8},
-        { 26000000, 832000000, 416, 13, 1, 8},
-        { 12000000, 624000000, 624, 12, 1, 8},
-        { 13000000, 624000000, 624, 13, 1, 8},
-        { 16800000, 600000000, 520, 14, 1, 8},
-        { 19200000, 624000000, 520, 16, 1, 8},
-        { 26000000, 624000000, 624, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 16800000, 600000000, 500, 14, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
-        { 12000000, 520000000, 520, 12, 1, 8},
-        { 13000000, 520000000, 520, 13, 1, 8},
-        { 16800000, 520000000, 495, 16, 1, 8},          /* actual: 519.75 MHz */
-        { 19200000, 520000000, 325, 12, 1, 6},
-        { 26000000, 520000000, 520, 26, 1, 8},
-        { 12000000, 416000000, 416, 12, 1, 8},
-        { 13000000, 416000000, 416, 13, 1, 8},
-        { 16800000, 416000000, 396, 16, 1, 8},          /* actual: 415.8 MHz */
-        { 19200000, 416000000, 260, 12, 1, 6},
-        { 26000000, 416000000, 416, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_c = {
-        .name      = "pll_c",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0x80,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 1400000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_c_freq_table,
-                .lock_delay = 300,
-        },
-};
-static struct clk tegra_pll_c_out1 = {
-        .name      = "pll_c_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_c,
-        .reg       = 0x84,
-        .reg_shift = 0,
-        .max_rate  = 700000000,
-};
-static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
-        { 12000000, 666000000, 666, 12, 1, 8},
-        { 13000000, 666000000, 666, 13, 1, 8},
-        { 16800000, 666000000, 555, 14, 1, 8},
-        { 19200000, 666000000, 555, 16, 1, 8},
-        { 26000000, 666000000, 666, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 16800000, 600000000, 500, 14, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_m = {
-        .name      = "pll_m",
-        .flags     = PLL_HAS_CPCON | PLLM,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0x90,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 800000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1200000000,
-                .freq_table = tegra_pll_m_freq_table,
-                .lock_delay = 300,
-        },
-};
-static struct clk tegra_pll_m_out1 = {
-        .name      = "pll_m_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_m,
-        .reg       = 0x94,
-        .reg_shift = 0,
-        .max_rate  = 600000000,
-};
-static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
-        { 12000000, 216000000, 432, 12, 2, 8},
-        { 13000000, 216000000, 432, 13, 2, 8},
-        { 16800000, 216000000, 360, 14, 2, 8},
-        { 19200000, 216000000, 360, 16, 2, 8},
-        { 26000000, 216000000, 432, 26, 2, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_p = {
-        .name      = "pll_p",
-        .flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xa0,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 432000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_p_freq_table,
-                .lock_delay = 300,
-                .fixed_rate = 408000000,
-        },
-};
-static struct clk tegra_pll_p_out1 = {
-        .name      = "pll_p_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa4,
-        .reg_shift = 0,
-        .max_rate  = 432000000,
-};
-static struct clk tegra_pll_p_out2 = {
-        .name      = "pll_p_out2",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa4,
-        .reg_shift = 16,
-        .max_rate  = 432000000,
-};
-static struct clk tegra_pll_p_out3 = {
-        .name      = "pll_p_out3",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa8,
-        .reg_shift = 0,
-        .max_rate  = 432000000,
-};
-static struct clk tegra_pll_p_out4 = {
-        .name      = "pll_p_out4",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa8,
-        .reg_shift = 16,
-        .max_rate  = 432000000,
-};
-static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
-        { 9600000, 564480000, 294, 5, 1, 4},
-        { 9600000, 552960000, 288, 5, 1, 4},
-        { 9600000, 24000000,  5,   2, 1, 1},
-        { 28800000, 56448000, 49, 25, 1, 1},
-        { 28800000, 73728000, 64, 25, 1, 1},
-        { 28800000, 24000000,  5,  6, 1, 1},
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_a = {
-        .name      = "pll_a",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xb0,
-        .parent    = &tegra_pll_p_out1,
-        .max_rate  = 700000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_a_freq_table,
-                .lock_delay = 300,
-        },
-};
-static struct clk tegra_pll_a_out0 = {
-        .name      = "pll_a_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_a,
-        .reg       = 0xb4,
-        .reg_shift = 0,
-        .max_rate  = 100000000,
-};
-static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
-        { 12000000, 216000000, 216, 12, 1, 4},
-        { 13000000, 216000000, 216, 13, 1, 4},
-        { 16800000, 216000000, 180, 14, 1, 4},
-        { 19200000, 216000000, 180, 16, 1, 4},
-        { 26000000, 216000000, 216, 26, 1, 4},
-        { 12000000, 594000000, 594, 12, 1, 8},
-        { 13000000, 594000000, 594, 13, 1, 8},
-        { 16800000, 594000000, 495, 14, 1, 8},
-        { 19200000, 594000000, 495, 16, 1, 8},
-        { 26000000, 594000000, 594, 26, 1, 8},
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_d = {
-        .name      = "pll_d",
-        .flags     = PLL_HAS_CPCON | PLLD,
-        .ops       = &tegra_plld_ops,
-        .reg       = 0xd0,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 1000000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 40000000,
-                .vco_max   = 1000000000,
-                .freq_table = tegra_pll_d_freq_table,
-                .lock_delay = 1000,
-        },
-};
-static struct clk tegra_pll_d_out0 = {
-        .name      = "pll_d_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_2 | PLLD,
-        .parent    = &tegra_pll_d,
-        .max_rate  = 500000000,
-};
-static struct clk tegra_pll_d2 = {
-        .name      = "pll_d2",
-        .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
-        .ops       = &tegra_plld_ops,
-        .reg       = 0x4b8,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 1000000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 40000000,
-                .vco_max   = 1000000000,
-                .freq_table = tegra_pll_d_freq_table,
-                .lock_delay = 1000,
-        },
-};
-static struct clk tegra_pll_d2_out0 = {
-        .name      = "pll_d2_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_2 | PLLD,
-        .parent    = &tegra_pll_d2,
-        .max_rate  = 500000000,
-};
-static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
-        { 12000000, 480000000, 960, 12, 2, 12},
-        { 13000000, 480000000, 960, 13, 2, 12},
-        { 16800000, 480000000, 400, 7,  2, 5},
-        { 19200000, 480000000, 200, 4,  2, 3},
-        { 26000000, 480000000, 960, 26, 2, 12},
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_u = {
-        .name      = "pll_u",
-        .flags     = PLL_HAS_CPCON | PLLU,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xc0,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 480000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 480000000,
-                .vco_max   = 960000000,
-                .freq_table = tegra_pll_u_freq_table,
-                .lock_delay = 1000,
-        },
-};
-static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
-        /* 1.7 GHz */
-        { 12000000, 1700000000, 850,  6,  1, 8},
-        { 13000000, 1700000000, 915,  7,  1, 8},        /* actual: 1699.2 MHz */
-        { 16800000, 1700000000, 708,  7,  1, 8},        /* actual: 1699.2 MHz */
-        { 19200000, 1700000000, 885,  10, 1, 8},        /* actual: 1699.2 MHz */
-        { 26000000, 1700000000, 850,  13, 1, 8},
-        /* 1.6 GHz */
-        { 12000000, 1600000000, 800,  6,  1, 8},
-        { 13000000, 1600000000, 738,  6,  1, 8},        /* actual: 1599.0 MHz */
-        { 16800000, 1600000000, 857,  9,  1, 8},        /* actual: 1599.7 MHz */
-        { 19200000, 1600000000, 500,  6,  1, 8},
-        { 26000000, 1600000000, 800,  13, 1, 8},
-        /* 1.5 GHz */
-        { 12000000, 1500000000, 750,  6,  1, 8},
-        { 13000000, 1500000000, 923,  8,  1, 8},        /* actual: 1499.8 MHz */
-        { 16800000, 1500000000, 625,  7,  1, 8},
-        { 19200000, 1500000000, 625,  8,  1, 8},
-        { 26000000, 1500000000, 750,  13, 1, 8},
-        /* 1.4 GHz */
-        { 12000000, 1400000000, 700,  6,  1, 8},
-        { 13000000, 1400000000, 969,  9,  1, 8},        /* actual: 1399.7 MHz */
-        { 16800000, 1400000000, 1000, 12, 1, 8},
-        { 19200000, 1400000000, 875,  12, 1, 8},
-        { 26000000, 1400000000, 700,  13, 1, 8},
-        /* 1.3 GHz */
-        { 12000000, 1300000000, 975,  9,  1, 8},
-        { 13000000, 1300000000, 1000, 10, 1, 8},
-        { 16800000, 1300000000, 928,  12, 1, 8},        /* actual: 1299.2 MHz */
-        { 19200000, 1300000000, 812,  12, 1, 8},        /* actual: 1299.2 MHz */
-        { 26000000, 1300000000, 650,  13, 1, 8},
-        /* 1.2 GHz */
-        { 12000000, 1200000000, 1000, 10, 1, 8},
-        { 13000000, 1200000000, 923,  10, 1, 8},        /* actual: 1199.9 MHz */
-        { 16800000, 1200000000, 1000, 14, 1, 8},
-        { 19200000, 1200000000, 1000, 16, 1, 8},
-        { 26000000, 1200000000, 600,  13, 1, 8},
-        /* 1.1 GHz */
-        { 12000000, 1100000000, 825,  9,  1, 8},
-        { 13000000, 1100000000, 846,  10, 1, 8},        /* actual: 1099.8 MHz */
-        { 16800000, 1100000000, 982,  15, 1, 8},        /* actual: 1099.8 MHz */
-        { 19200000, 1100000000, 859,  15, 1, 8},        /* actual: 1099.5 MHz */
-        { 26000000, 1100000000, 550,  13, 1, 8},
-        /* 1 GHz */
-        { 12000000, 1000000000, 1000, 12, 1, 8},
-        { 13000000, 1000000000, 1000, 13, 1, 8},
-        { 16800000, 1000000000, 833,  14, 1, 8},        /* actual: 999.6 MHz */
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_x = {
-        .name      = "pll_x",
-        .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xe0,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 1700000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1700000000,
-                .freq_table = tegra_pll_x_freq_table,
-                .lock_delay = 300,
-        },
-};
-static struct clk tegra_pll_x_out0 = {
-        .name      = "pll_x_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_2 | PLLX,
-        .parent    = &tegra_pll_x,
-        .max_rate  = 850000000,
-};
-static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
-        /* PLLE special case: use cpcon field to store cml divider value */
-        { 12000000,  100000000, 150, 1,  18, 11},
-        { 216000000, 100000000, 200, 18, 24, 13},
-        { 0, 0, 0, 0, 0, 0 },
-};
-static struct clk tegra_pll_e = {
-        .name      = "pll_e",
-        .flags     = PLL_ALT_MISC_REG,
-        .ops       = &tegra_plle_ops,
-        .reg       = 0xe8,
-        .max_rate  = 100000000,
-        .u.pll = {
-                .input_min = 12000000,
-                .input_max = 216000000,
-                .cf_min    = 12000000,
-                .cf_max    = 12000000,
-                .vco_min   = 1200000000,
-                .vco_max   = 2400000000U,
-                .freq_table = tegra_pll_e_freq_table,
-                .lock_delay = 300,
-                .fixed_rate = 100000000,
-        },
-};
-static struct clk tegra_cml0_clk = {
-        .name      = "cml0",
-        .parent    = &tegra_pll_e,
-        .ops       = &tegra_cml_clk_ops,
-        .reg       = PLLE_AUX,
-        .max_rate  = 100000000,
-        .u.periph  = {
-                .clk_num = 0,
-        },
-};
-static struct clk tegra_cml1_clk = {
-        .name      = "cml1",
-        .parent    = &tegra_pll_e,
-        .ops       = &tegra_cml_clk_ops,
-        .reg       = PLLE_AUX,
-        .max_rate  = 100000000,
-        .u.periph  = {
-                .clk_num   = 1,
-        },
-};
-static struct clk tegra_pciex_clk = {
-        .name      = "pciex",
-        .parent    = &tegra_pll_e,
-        .ops       = &tegra_pciex_clk_ops,
-        .max_rate  = 100000000,
-        .u.periph  = {
-                .clk_num   = 74,
-        },
-};
-/* Audio sync clocks */
-#define SYNC_SOURCE(_id)                                \
-        {                                               \
-                .name      = #_id "_sync",              \
-                .rate      = 24000000,                  \
-                .max_rate  = 24000000,                  \
-                .ops       = &tegra_sync_source_ops     \
-        }
-static struct clk tegra_sync_source_list[] = {
-        SYNC_SOURCE(spdif_in),
-        SYNC_SOURCE(i2s0),
-        SYNC_SOURCE(i2s1),
-        SYNC_SOURCE(i2s2),
-        SYNC_SOURCE(i2s3),
-        SYNC_SOURCE(i2s4),
-        SYNC_SOURCE(vimclk),
-};
-static struct clk_mux_sel mux_audio_sync_clk[] = {
-        { .input = &tegra_sync_source_list[0],  .value = 0},
-        { .input = &tegra_sync_source_list[1],  .value = 1},
-        { .input = &tegra_sync_source_list[2],  .value = 2},
-        { .input = &tegra_sync_source_list[3],  .value = 3},
-        { .input = &tegra_sync_source_list[4],  .value = 4},
-        { .input = &tegra_sync_source_list[5],  .value = 5},
-        { .input = &tegra_pll_a_out0,           .value = 6},
-        { .input = &tegra_sync_source_list[6],  .value = 7},
-        { 0, 0 }
 };
-#define AUDIO_SYNC_CLK(_id, _index)                     \
+struct clk_ops tegra_pciex_clk_ops = {
-        {                                               \
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
-                .name      = #_id,                      \
-                .inputs    = mux_audio_sync_clk,        \
-                .reg       = 0x4A0 + (_index) * 4,      \
-                .max_rate  = 24000000,                  \
-                .ops       = &tegra_audio_sync_clk_ops  \
-        }
-static struct clk tegra_clk_audio_list[] = {
-        AUDIO_SYNC_CLK(audio0, 0),
-        AUDIO_SYNC_CLK(audio1, 1),
-        AUDIO_SYNC_CLK(audio2, 2),
-        AUDIO_SYNC_CLK(audio3, 3),
-        AUDIO_SYNC_CLK(audio4, 4),
-        AUDIO_SYNC_CLK(audio, 5),       /* SPDIF */
 };
-#define AUDIO_SYNC_2X_CLK(_id, _index)                          \
+/* Tegra30 CPU clock and reset control functions */
-        {                                                       \
+static void tegra30_wait_cpu_in_reset(u32 cpu)
-                .name      = #_id "_2x",                        \
+{
-                .flags     = PERIPH_NO_RESET,                   \
+        unsigned int reg;
-                .max_rate  = 48000000,                          \
-                .ops       = &tegra_clk_double_ops,             \
-                .reg       = 0x49C,                             \
-                .reg_shift = 24 + (_index),                     \
-                .parent    = &tegra_clk_audio_list[(_index)],   \
-                .u.periph = {                                   \
-                        .clk_num = 113 + (_index),              \
-                },                                              \
-        }
-static struct clk tegra_clk_audio_2x_list[] = {
-        AUDIO_SYNC_2X_CLK(audio0, 0),
-        AUDIO_SYNC_2X_CLK(audio1, 1),
-        AUDIO_SYNC_2X_CLK(audio2, 2),
-        AUDIO_SYNC_2X_CLK(audio3, 3),
-        AUDIO_SYNC_2X_CLK(audio4, 4),
-        AUDIO_SYNC_2X_CLK(audio, 5),    /* SPDIF */
-};
-#define MUX_I2S_SPDIF(_id, _index)                                      \
+        do {
-static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = {       \
+                reg = readl(reg_clk_base +
-        {.input = &tegra_pll_a_out0, .value = 0},                       \
+                            TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
-        {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1},      \
+                cpu_relax();
-        {.input = &tegra_pll_p, .value = 2},                            \
+        } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
-        {.input = &tegra_clk_m, .value = 3},                            \
-        { 0, 0},                                                        \
-}
-MUX_I2S_SPDIF(audio0, 0);
-MUX_I2S_SPDIF(audio1, 1);
-MUX_I2S_SPDIF(audio2, 2);
-MUX_I2S_SPDIF(audio3, 3);
-MUX_I2S_SPDIF(audio4, 4);
-MUX_I2S_SPDIF(audio, 5);                /* SPDIF */
-/* External clock outputs (through PMC) */
-#define MUX_EXTERN_OUT(_id)                                             \
-static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = {        \
-        {.input = &tegra_clk_m,         .value = 0},                    \
-        {.input = &tegra_clk_m_div2,    .value = 1},                    \
-        {.input = &tegra_clk_m_div4,    .value = 2},                    \
-        {.input = NULL,                 .value = 3}, /* placeholder */  \
-        { 0, 0},                                                        \
-}
-MUX_EXTERN_OUT(1);
-MUX_EXTERN_OUT(2);
-MUX_EXTERN_OUT(3);
-static struct clk_mux_sel *mux_extern_out_list[] = {
-        mux_clkm_clkm2_clkm4_extern1,
-        mux_clkm_clkm2_clkm4_extern2,
-        mux_clkm_clkm2_clkm4_extern3,
-};
-#define CLK_OUT_CLK(_id)                                        \
+        return;
-        {                                                       \
+}
-                .name      = "clk_out_" #_id,                   \
-                .lookup    = {                                  \
-                        .dev_id    = "clk_out_" #_id,           \
-                        .con_id    = "extern" #_id,             \
-                },                                              \
-                .ops       = &tegra_clk_out_ops,                \
-                .reg       = 0x1a8,                             \
-                .inputs    = mux_clkm_clkm2_clkm4_extern##_id,  \
-                .flags     = MUX_CLK_OUT,                       \
-                .max_rate  = 216000000,                         \
-                .u.periph = {                                   \
-                        .clk_num   = (_id - 1) * 8 + 2,         \
-                },                                              \
-        }
-static struct clk tegra_clk_out_list[] = {
-        CLK_OUT_CLK(1),
-        CLK_OUT_CLK(2),
-        CLK_OUT_CLK(3),
-};
-/* called after peripheral external clocks are initialized */
+static void tegra30_put_cpu_in_reset(u32 cpu)
-static void init_clk_out_mux(void)
 {
-        int i;
+        writel(CPU_RESET(cpu),
-        struct clk *c;
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+        dmb();
-        /* output clock con_id is the name of peripheral
-           external clock connected to input 3 of the output mux */
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
-                c = tegra_get_clock_by_name(
-                        tegra_clk_out_list[i].lookup.con_id);
-                if (!c)
-                        pr_err("%s: could not find clk %s\n", __func__,
-                               tegra_clk_out_list[i].lookup.con_id);
-                mux_extern_out_list[i][3].input = c;
-        }
 }
-/* Peripheral muxes */
+static void tegra30_cpu_out_of_reset(u32 cpu)
-static struct clk_mux_sel mux_sclk[] = {
-        { .input = &tegra_clk_m,        .value = 0},
-        { .input = &tegra_pll_c_out1,   .value = 1},
-        { .input = &tegra_pll_p_out4,   .value = 2},
-        { .input = &tegra_pll_p_out3,   .value = 3},
-        { .input = &tegra_pll_p_out2,   .value = 4},
-        /* { .input = &tegra_clk_d,     .value = 5}, - no use on tegra30 */
-        { .input = &tegra_clk_32k,      .value = 6},
-        { .input = &tegra_pll_m_out1,   .value = 7},
-        { 0, 0},
-};
-static struct clk tegra_clk_sclk = {
-        .name   = "sclk",
-        .inputs = mux_sclk,
-        .reg    = 0x28,
-        .ops    = &tegra_super_ops,
-        .max_rate = 334000000,
-        .min_rate = 40000000,
-};
-static struct clk tegra_clk_blink = {
-        .name           = "blink",
-        .parent         = &tegra_clk_32k,
-        .reg            = 0x40,
-        .ops            = &tegra_blink_clk_ops,
-        .max_rate       = 32768,
-};
-static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
-        { .input = &tegra_pll_m, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_p, .value = 2},
-        { .input = &tegra_pll_a_out0, .value = 3},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
-        { .input = &tegra_pll_p, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_m, .value = 2},
-        { .input = &tegra_clk_m, .value = 3},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_pllp_clkm[] = {
-        { .input = &tegra_pll_p, .value = 0},
-        { .input = &tegra_clk_m, .value = 3},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
-        {.input = &tegra_pll_p, .value = 0},
-        {.input = &tegra_pll_d_out0, .value = 1},
-        {.input = &tegra_pll_c, .value = 2},
-        {.input = &tegra_clk_m, .value = 3},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
-        {.input = &tegra_pll_p, .value = 0},
-        {.input = &tegra_pll_m, .value = 1},
-        {.input = &tegra_pll_d_out0, .value = 2},
-        {.input = &tegra_pll_a_out0, .value = 3},
-        {.input = &tegra_pll_c, .value = 4},
-        {.input = &tegra_pll_d2_out0, .value = 5},
-        {.input = &tegra_clk_m, .value = 6},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
-        { .input = &tegra_pll_a_out0, .value = 0},
-        /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
-        { .input = &tegra_pll_p, .value = 2},
-        { .input = &tegra_clk_m, .value = 3},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_clk_32k,   .value = 2},
-        {.input = &tegra_clk_m,     .value = 3},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_clk_m,     .value = 2},
-        {.input = &tegra_clk_32k,   .value = 3},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_pll_m,     .value = 2},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_clk_m[] = {
-        { .input = &tegra_clk_m, .value = 0},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_pllp_out3[] = {
-        { .input = &tegra_pll_p_out3, .value = 0},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_plld_out0[] = {
-        { .input = &tegra_pll_d_out0, .value = 0},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
-        { .input = &tegra_pll_d_out0,  .value = 0},
-        { .input = &tegra_pll_d2_out0, .value = 1},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_clk_32k[] = {
-        { .input = &tegra_clk_32k, .value = 0},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
-        { .input = &tegra_pll_a_out0, .value = 0},
-        { .input = &tegra_clk_32k,    .value = 1},
-        { .input = &tegra_pll_p,      .value = 2},
-        { .input = &tegra_clk_m,      .value = 3},
-        { .input = &tegra_pll_e,      .value = 4},
-        { 0, 0},
-};
-static struct clk_mux_sel mux_cclk_g[] = {
-        { .input = &tegra_clk_m,        .value = 0},
-        { .input = &tegra_pll_c,        .value = 1},
-        { .input = &tegra_clk_32k,      .value = 2},
-        { .input = &tegra_pll_m,        .value = 3},
-        { .input = &tegra_pll_p,        .value = 4},
-        { .input = &tegra_pll_p_out4,   .value = 5},
-        { .input = &tegra_pll_p_out3,   .value = 6},
-        { .input = &tegra_pll_x,        .value = 8},
-        { 0, 0},
-};
-static struct clk tegra_clk_cclk_g = {
-        .name   = "cclk_g",
-        .flags  = DIV_U71 | DIV_U71_INT,
-        .inputs = mux_cclk_g,
-        .reg    = 0x368,
-        .ops    = &tegra_super_ops,
-        .max_rate = 1700000000,
-};
-static struct clk tegra30_clk_twd = {
-        .parent   = &tegra_clk_cclk_g,
-        .name     = "twd",
-        .ops      = &tegra30_twd_ops,
-        .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
-        .mul      = 1,
-        .div      = 2,
-};
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = &tegra_periph_clk_ops,     \
-                .reg       = _reg,                      \
-                .inputs    = _inputs,                   \
-                .flags     = _flags,                    \
-                .max_rate  = _max,                      \
-                .u.periph = {                           \
-                        .clk_num   = _clk_num,          \
-                },                                      \
-        }
-#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
-                        _flags, _ops)                                   \
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = _ops,                      \
-                .reg       = _reg,                      \
-                .inputs    = _inputs,                   \
-                .flags     = _flags,                    \
-                .max_rate  = _max,                      \
-                .u.periph = {                           \
-                        .clk_num   = _clk_num,          \
-                },                                      \
-        }
-#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = &tegra_clk_shared_bus_ops, \
-                .parent = _parent,                      \
-                .u.shared_bus_user = {                  \
-                        .client_id = _id,               \
-                        .client_div = _div,             \
-                        .mode = _mode,                  \
-                },                                      \
-        }
-struct clk tegra_list_clks[] = {
-        PERIPH_CLK("apbdma",    "tegra-apbdma",         NULL,   34,     0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB),
-        PERIPH_CLK("kbc",       "tegra-kbc",            NULL,   36,     0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB),
-        PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("kfuse",     "kfuse-tegra",          NULL,   40,     0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("fuse",      "fuse-tegra",           "fuse", 39,     0,      26000000,  mux_clk_m,                   PERIPH_ON_APB),
-        PERIPH_CLK("fuse_burn", "fuse-tegra",           "fuse_burn",    39,     0,      26000000,  mux_clk_m,           PERIPH_ON_APB),
-        PERIPH_CLK("apbif",     "tegra30-ahub",         "apbif", 107,   0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("i2s0",      "tegra30-i2s.0",        NULL,   30,     0x1d8,  26000000,  mux_pllaout0_audio0_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("i2s1",      "tegra30-i2s.1",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio1_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("i2s2",      "tegra30-i2s.2",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("i2s3",      "tegra30-i2s.3",        NULL,   101,    0x3bc,  26000000,  mux_pllaout0_audio3_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("i2s4",      "tegra30-i2s.4",        NULL,   102,    0x3c0,  26000000,  mux_pllaout0_audio4_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("spdif_out", "tegra30-spdif",        "spdif_out",    10,     0x108,  100000000, mux_pllaout0_audio_2x_pllp_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("spdif_in",  "tegra30-spdif",        "spdif_in",     10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("pwm",       "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_clk32_clkm,    MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("d_audio",   "tegra30-ahub",         "d_audio", 106, 0x3d0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("dam0",      "tegra30-dam.0",        NULL,   108,    0x3d8,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("dam1",      "tegra30-dam.1",        NULL,   109,    0x3dc,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("dam2",      "tegra30-dam.2",        NULL,   110,    0x3e0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("hda",       "tegra30-hda",          "hda",   125,   0x428,  108000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("hda2codec_2x",      "tegra30-hda",  "hda2codec",   111,     0x3e4,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("hda2hdmi",  "tegra30-hda",          "hda2hdmi",     128,    0,      48000000,  mux_clk_m,                   0),
-        PERIPH_CLK("sbc1",      "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc2",      "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc3",      "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc4",      "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc5",      "spi_tegra.4",          NULL,   104,    0x3c8,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc6",      "spi_tegra.5",          NULL,   105,    0x3cc,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sata_oob",  "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sata",      "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sata_cold", "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   0),
-        PERIPH_CLK_EX("ndflash", "tegra_nand",          NULL,   13,     0x160,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71,  &tegra_nand_clk_ops),
-        PERIPH_CLK("ndspeed",   "tegra_nand_speed",     NULL,   80,     0x3f8,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sdmmc1",    "sdhci-tegra.0",        NULL,   14,     0x150,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc2",    "sdhci-tegra.1",        NULL,   9,      0x154,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc3",    "sdhci-tegra.2",        NULL,   69,     0x1bc,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc4",    "sdhci-tegra.3",        NULL,   15,     0x164,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("vcp",       "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("bsea",      "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("bsev",      "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("vde",       "vde",                  NULL,   61,     0x1c8,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT),
-        PERIPH_CLK("csite",     "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* max rate ??? */
-        PERIPH_CLK("la",        "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("owr",       "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("nor",       "nor",                  NULL,   42,     0x1d0,  127000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("mipi",      "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
-        PERIPH_CLK("i2c1",      "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("i2c2",      "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("i2c3",      "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("i2c4",      "tegra-i2c.3",          NULL,   103,    0x3c4,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("i2c5",      "tegra-i2c.4",          NULL,   47,     0x128,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("uarta",     "tegra-uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartb",     "tegra-uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartc",     "tegra-uart.2",         NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartd",     "tegra-uart.3",         NULL,   65,     0x1c0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uarte",     "tegra-uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK_EX("vi",     "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT,    &tegra_vi_clk_ops),
-        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
-        PERIPH_CLK("3d2",       "3d2",                  NULL,   98,     0x3b0,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
-        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
-        PERIPH_CLK("vi_sensor", "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
-        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
-        PERIPH_CLK("mpe",       "mpe",                  NULL,   60,     0x170,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
-        PERIPH_CLK("host1x",    "host1x",               NULL,   28,     0x180,  260000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
-        PERIPH_CLK("cve",       "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("tvo",       "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK_EX("dtv",    "dtv",                  NULL,   79,     0x1dc,  250000000, mux_clk_m,                   0,              &tegra_dtv_clk_ops),
-        PERIPH_CLK("hdmi",      "hdmi",                 NULL,   51,     0x18c,  148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8 | DIV_U71),
-        PERIPH_CLK("tvdac",     "tvdac",                NULL,   53,     0x194,  220000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("disp1",     "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8),
-        PERIPH_CLK("disp2",     "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8),
-        PERIPH_CLK("usbd",      "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("usb2",      "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("usb3",      "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("dsia",      "tegradc.0",            "dsia", 48,     0,      500000000, mux_plld_out0,               0),
-        PERIPH_CLK_EX("dsib",   "tegradc.1",            "dsib", 82,     0xd0,   500000000, mux_plld_out0_plld2_out0,    MUX | PLLD,     &tegra_dsib_clk_ops),
-        PERIPH_CLK("csi",       "tegra_camera",         "csi",  52,     0,      102000000, mux_pllp_out3,               0),
-        PERIPH_CLK("isp",       "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
-        PERIPH_CLK("csus",      "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
-        PERIPH_CLK("tsensor",   "tegra-tsensor",        NULL,   100,    0x3b8,  216000000, mux_pllp_pllc_clkm_clk32,    MUX | DIV_U71),
-        PERIPH_CLK("actmon",    "actmon",               NULL,   119,    0x3e8,  216000000, mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71),
-        PERIPH_CLK("extern1",   "extern1",              NULL,   120,    0x3ec,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
-        PERIPH_CLK("extern2",   "extern2",              NULL,   121,    0x3f0,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
-        PERIPH_CLK("extern3",   "extern3",              NULL,   122,    0x3f4,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
-        PERIPH_CLK("i2cslow",   "i2cslow",              NULL,   81,     0x3fc,  26000000,  mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("pcie",      "tegra-pcie",           "pcie", 70,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("afi",       "tegra-pcie",           "afi",  72,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("se",        "se",                   NULL,   127,    0x42c,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT),
-};
-#define CLK_DUPLICATE(_name, _dev, _con)                \
-        {                                               \
-                .name   = _name,                        \
-                .lookup = {                             \
-                        .dev_id = _dev,                 \
-                        .con_id         = _con,         \
-                },                                      \
-        }
-/* Some clocks may be used by different drivers depending on the board
- * configuration.  List those here to register them twice in the clock lookup
- * table under two names.
- */
-struct clk_duplicate tegra_clk_duplicates[] = {
-        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
-        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
-        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
-        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
-        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
-        CLK_DUPLICATE("usbd", "utmip-pad", NULL),
-        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
-        CLK_DUPLICATE("usbd", "tegra-otg", NULL),
-        CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
-        CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
-        CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
-        CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
-        CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
-        CLK_DUPLICATE("bsev", "nvavp", "bsev"),
-        CLK_DUPLICATE("vde", "tegra-aes", "vde"),
-        CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
-        CLK_DUPLICATE("bsea", "nvavp", "bsea"),
-        CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
-        CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
-        CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
-        CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
-        CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
-        CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
-        CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
-        CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
-        CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
-        CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
-        CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
-        CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
-        CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
-        CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
-        CLK_DUPLICATE("twd", "smp_twd", NULL),
-        CLK_DUPLICATE("vcp", "nvavp", "vcp"),
-        CLK_DUPLICATE("i2s0", NULL, "i2s0"),
-        CLK_DUPLICATE("i2s1", NULL, "i2s1"),
-        CLK_DUPLICATE("i2s2", NULL, "i2s2"),
-        CLK_DUPLICATE("i2s3", NULL, "i2s3"),
-        CLK_DUPLICATE("i2s4", NULL, "i2s4"),
-        CLK_DUPLICATE("dam0", NULL, "dam0"),
-        CLK_DUPLICATE("dam1", NULL, "dam1"),
-        CLK_DUPLICATE("dam2", NULL, "dam2"),
-        CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
-};
-struct clk *tegra_ptr_clks[] = {
-        &tegra_clk_32k,
-        &tegra_clk_m,
-        &tegra_clk_m_div2,
-        &tegra_clk_m_div4,
-        &tegra_pll_ref,
-        &tegra_pll_m,
-        &tegra_pll_m_out1,
-        &tegra_pll_c,
-        &tegra_pll_c_out1,
-        &tegra_pll_p,
-        &tegra_pll_p_out1,
-        &tegra_pll_p_out2,
-        &tegra_pll_p_out3,
-        &tegra_pll_p_out4,
-        &tegra_pll_a,
-        &tegra_pll_a_out0,
-        &tegra_pll_d,
-        &tegra_pll_d_out0,
-        &tegra_pll_d2,
-        &tegra_pll_d2_out0,
-        &tegra_pll_u,
-        &tegra_pll_x,
-        &tegra_pll_x_out0,
-        &tegra_pll_e,
-        &tegra_clk_cclk_g,
-        &tegra_cml0_clk,
-        &tegra_cml1_clk,
-        &tegra_pciex_clk,
-        &tegra_clk_sclk,
-        &tegra_clk_blink,
-        &tegra30_clk_twd,
-};
-static void tegra30_init_one_clock(struct clk *c)
 {
-        clk_init(c);
+        writel(CPU_RESET(cpu),
-        INIT_LIST_HEAD(&c->shared_bus_list);
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
-        if (!c->lookup.dev_id && !c->lookup.con_id)
+        wmb();
-                c->lookup.con_id = c->name;
-        c->lookup.clk = c;
-        clkdev_add(&c->lookup);
 }
-void __init tegra30_init_clocks(void)
+static void tegra30_enable_cpu_clock(u32 cpu)
 {
-        int i;
+        unsigned int reg;
-        struct clk *c;
-        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
+        writel(CPU_CLOCK(cpu),
-                tegra30_init_one_clock(tegra_ptr_clks[i]);
+               reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+        reg = readl(reg_clk_base +
-        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
+                    TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
-                tegra30_init_one_clock(&tegra_list_clks[i]);
+}
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+static void tegra30_disable_cpu_clock(u32 cpu)
-                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+{
-                if (!c) {
-                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
-                                tegra_clk_duplicates[i].name);
-                        continue;
-                }
-                tegra_clk_duplicates[i].lookup.clk = c;
+        unsigned int reg;
-                clkdev_add(&tegra_clk_duplicates[i].lookup);
-        }
-        for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
+        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-                tegra30_init_one_clock(&tegra_sync_source_list[i]);
+        writel(reg | CPU_CLOCK(cpu),
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-                tegra30_init_one_clock(&tegra_clk_audio_list[i]);
+}
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
-                tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
-        init_clk_out_mux();
+static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
+        .wait_for_reset = tegra30_wait_cpu_in_reset,
-                tegra30_init_one_clock(&tegra_clk_out_list[i]);
+        .put_in_reset   = tegra30_put_cpu_in_reset,
+        .out_of_reset   = tegra30_cpu_out_of_reset,
+        .enable_clock   = tegra30_enable_cpu_clock,
+        .disable_clock  = tegra30_disable_cpu_clock,
+};
+void __init tegra30_cpu_car_ops_init(void)
+{
+        tegra_cpu_car_ops = &tegra30_cpu_car_ops;
 }
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
new file mode 100644
index 000000000000..f2f88fef6b8b
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __MACH_TEGRA30_CLOCK_H
+#define __MACH_TEGRA30_CLOCK_H
+extern struct clk_ops tegra30_clk_32k_ops;
+extern struct clk_ops tegra30_clk_m_ops;
+extern struct clk_ops tegra_clk_m_div_ops;
+extern struct clk_ops tegra_pll_ref_ops;
+extern struct clk_ops tegra30_pll_ops;
+extern struct clk_ops tegra30_pll_div_ops;
+extern struct clk_ops tegra_plld_ops;
+extern struct clk_ops tegra30_plle_ops;
+extern struct clk_ops tegra_cml_clk_ops;
+extern struct clk_ops tegra_pciex_clk_ops;
+extern struct clk_ops tegra_sync_source_ops;
+extern struct clk_ops tegra30_audio_sync_clk_ops;
+extern struct clk_ops tegra30_clk_double_ops;
+extern struct clk_ops tegra_clk_out_ops;
+extern struct clk_ops tegra30_super_ops;
+extern struct clk_ops tegra30_blink_clk_ops;
+extern struct clk_ops tegra30_twd_ops;
+extern struct clk_ops tegra30_periph_clk_ops;
+extern struct clk_ops tegra30_dsib_clk_ops;
+extern struct clk_ops tegra_nand_clk_ops;
+extern struct clk_ops tegra_vi_clk_ops;
+extern struct clk_ops tegra_dtv_clk_ops;
+extern struct clk_ops tegra_clk_shared_bus_ops;
+int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting);
+void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert);
+int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting);
+int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting);
+int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting);
+#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
new file mode 100644
index 000000000000..d92cb556ae35
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -0,0 +1,1377 @@
+/*
+ * arch/arm/mach-tegra/tegra30_clocks.c
+ *
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ */
+#include <linux/clk-private.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+#include "clock.h"
+#include "fuse.h"
+#include "tegra30_clocks.h"
+#include "tegra_cpu_car.h"
+#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,            \
+                   _parent_names, _parents, _parent)            \
+        static struct clk tegra_##_name = {                     \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .name = #_name,                                 \
+                .rate = _rate,                                  \
+                .ops = _ops,                                    \
+                .flags = _flags,                                \
+                .parent_names = _parent_names,                  \
+                .parents = _parents,                            \
+                .num_parents = ARRAY_SIZE(_parent_names),       \
+                .parent = _parent,                              \
+        };
+static struct clk tegra_clk_32k;
+static struct clk_tegra tegra_clk_32k_hw = {
+        .hw = {
+                .clk = &tegra_clk_32k,
+        },
+        .fixed_rate = 32768,
+};
+static struct clk tegra_clk_32k = {
+        .name = "clk_32k",
+        .hw = &tegra_clk_32k_hw.hw,
+        .ops = &tegra30_clk_32k_ops,
+        .flags = CLK_IS_ROOT,
+};
+static struct clk tegra_clk_m;
+static struct clk_tegra tegra_clk_m_hw = {
+        .hw = {
+                .clk = &tegra_clk_m,
+        },
+        .flags = ENABLE_ON_INIT,
+        .reg = 0x1fc,
+        .reg_shift = 28,
+        .max_rate = 48000000,
+};
+static struct clk tegra_clk_m = {
+        .name = "clk_m",
+        .hw = &tegra_clk_m_hw.hw,
+        .ops = &tegra30_clk_m_ops,
+        .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
+};
+static const char *clk_m_div_parent_names[] = {
+        "clk_m",
+};
+static struct clk *clk_m_div_parents[] = {
+        &tegra_clk_m,
+};
+static struct clk tegra_clk_m_div2;
+static struct clk_tegra tegra_clk_m_div2_hw = {
+        .hw = {
+                .clk = &tegra_clk_m_div2,
+        },
+        .mul = 1,
+        .div = 2,
+        .max_rate = 24000000,
+};
+DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
+                clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
+static struct clk tegra_clk_m_div4;
+static struct clk_tegra tegra_clk_m_div4_hw = {
+        .hw = {
+                .clk = &tegra_clk_m_div4,
+        },
+        .mul = 1,
+        .div = 4,
+        .max_rate = 12000000,
+};
+DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
+                clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
+static struct clk tegra_pll_ref;
+static struct clk_tegra tegra_pll_ref_hw = {
+        .hw = {
+                .clk = &tegra_pll_ref,
+        },
+        .flags = ENABLE_ON_INIT,
+        .max_rate = 26000000,
+};
+DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
+                clk_m_div_parents, &tegra_clk_m);
+#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min,  \
+                   _input_max, _cf_min, _cf_max, _vco_min,      \
+                   _vco_max, _freq_table, _lock_delay, _ops,    \
+                   _fixed_rate, _clk_cfg_ex, _parent)           \
+        static struct clk tegra_##_name;                        \
+        static const char *_name##_parent_names[] = {           \
+                #_parent,                                       \
+        };                                                      \
+        static struct clk *_name##_parents[] = {                \
+                &tegra_##_parent,                               \
+        };                                                      \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .flags = _flags,                                \
+                .reg = _reg,                                    \
+                .max_rate = _max_rate,                          \
+                .u.pll = {                                      \
+                        .input_min = _input_min,                \
+                        .input_max = _input_max,                \
+                        .cf_min = _cf_min,                      \
+                        .cf_max = _cf_max,                      \
+                        .vco_min = _vco_min,                    \
+                        .vco_max = _vco_max,                    \
+                        .freq_table = _freq_table,              \
+                        .lock_delay = _lock_delay,              \
+                        .fixed_rate = _fixed_rate,              \
+                },                                              \
+                .clk_cfg_ex = _clk_cfg_ex,                      \
+        };                                                      \
+        DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED,    \
+                         _name##_parent_names, _name##_parents, \
+                        &tegra_##_parent);
+#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift,         \
+                _max_rate, _ops, _parent, _clk_flags)           \
+        static const char *_name##_parent_names[] = {           \
+                #_parent,                                       \
+        };                                                      \
+        static struct clk *_name##_parents[] = {                \
+                &tegra_##_parent,                               \
+        };                                                      \
+        static struct clk tegra_##_name;                        \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .flags = _flags,                                \
+                .reg = _reg,                                    \
+                .max_rate = _max_rate,                          \
+                .reg_shift = _reg_shift,                        \
+        };                                                      \
+        DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops,        \
+                _clk_flags,  _name##_parent_names,              \
+                _name##_parents, &tegra_##_parent);
+static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+        { 12000000, 1040000000, 520,  6, 1, 8},
+        { 13000000, 1040000000, 480,  6, 1, 8},
+        { 16800000, 1040000000, 495,  8, 1, 8}, /* actual: 1039.5 MHz */
+        { 19200000, 1040000000, 325,  6, 1, 6},
+        { 26000000, 1040000000, 520, 13, 1, 8},
+        { 12000000, 832000000, 416,  6, 1, 8},
+        { 13000000, 832000000, 832, 13, 1, 8},
+        { 16800000, 832000000, 396,  8, 1, 8},  /* actual: 831.6 MHz */
+        { 19200000, 832000000, 260,  6, 1, 8},
+        { 26000000, 832000000, 416, 13, 1, 8},
+        { 12000000, 624000000, 624, 12, 1, 8},
+        { 13000000, 624000000, 624, 13, 1, 8},
+        { 16800000, 600000000, 520, 14, 1, 8},
+        { 19200000, 624000000, 520, 16, 1, 8},
+        { 26000000, 624000000, 624, 26, 1, 8},
+        { 12000000, 600000000, 600, 12, 1, 8},
+        { 13000000, 600000000, 600, 13, 1, 8},
+        { 16800000, 600000000, 500, 14, 1, 8},
+        { 19200000, 600000000, 375, 12, 1, 6},
+        { 26000000, 600000000, 600, 26, 1, 8},
+        { 12000000, 520000000, 520, 12, 1, 8},
+        { 13000000, 520000000, 520, 13, 1, 8},
+        { 16800000, 520000000, 495, 16, 1, 8},  /* actual: 519.75 MHz */
+        { 19200000, 520000000, 325, 12, 1, 6},
+        { 26000000, 520000000, 520, 26, 1, 8},
+        { 12000000, 416000000, 416, 12, 1, 8},
+        { 13000000, 416000000, 416, 13, 1, 8},
+        { 16800000, 416000000, 396, 16, 1, 8},  /* actual: 415.8 MHz */
+        { 19200000, 416000000, 260, 12, 1, 6},
+        { 26000000, 416000000, 416, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
+                tegra30_pll_ops, 0, NULL, pll_ref);
+DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
+                tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
+static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
+        { 12000000, 666000000, 666, 12, 1, 8},
+        { 13000000, 666000000, 666, 13, 1, 8},
+        { 16800000, 666000000, 555, 14, 1, 8},
+        { 19200000, 666000000, 555, 16, 1, 8},
+        { 26000000, 666000000, 666, 26, 1, 8},
+        { 12000000, 600000000, 600, 12, 1, 8},
+        { 13000000, 600000000, 600, 13, 1, 8},
+        { 16800000, 600000000, 500, 14, 1, 8},
+        { 19200000, 600000000, 375, 12, 1, 6},
+        { 26000000, 600000000, 600, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
+                1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
+                300, tegra30_pll_ops, 0, NULL, pll_ref);
+DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
+                tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
+static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
+        { 12000000, 216000000, 432, 12, 2, 8},
+        { 13000000, 216000000, 432, 13, 2, 8},
+        { 16800000, 216000000, 360, 14, 2, 8},
+        { 19200000, 216000000, 360, 16, 2, 8},
+        { 26000000, 216000000, 432, 26, 2, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
+                2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
+                tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
+                pll_ref);
+DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
+                0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
+                16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
+                0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
+                16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
+        { 9600000, 564480000, 294, 5, 1, 4},
+        { 9600000, 552960000, 288, 5, 1, 4},
+        { 9600000, 24000000,  5,   2, 1, 1},
+        { 28800000, 56448000, 49, 25, 1, 1},
+        { 28800000, 73728000, 64, 25, 1, 1},
+        { 28800000, 24000000,  5,  6, 1, 1},
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
+                300, tegra30_pll_ops, 0, NULL, pll_p_out1);
+DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
+                pll_a, CLK_IGNORE_UNUSED);
+static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
+        { 12000000, 216000000, 216, 12, 1, 4},
+        { 13000000, 216000000, 216, 13, 1, 4},
+        { 16800000, 216000000, 180, 14, 1, 4},
+        { 19200000, 216000000, 180, 16, 1, 4},
+        { 26000000, 216000000, 216, 26, 1, 4},
+        { 12000000, 594000000, 594, 12, 1, 8},
+        { 13000000, 594000000, 594, 13, 1, 8},
+        { 16800000, 594000000, 495, 14, 1, 8},
+        { 19200000, 594000000, 495, 16, 1, 8},
+        { 26000000, 594000000, 594, 26, 1, 8},
+        { 12000000, 1000000000, 1000, 12, 1, 12},
+        { 13000000, 1000000000, 1000, 13, 1, 12},
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 12},
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
+                1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
+                1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
+DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
+                pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
+DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
+                2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
+                tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
+                pll_ref);
+DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
+                pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
+static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
+        { 12000000, 480000000, 960, 12, 2, 12},
+        { 13000000, 480000000, 960, 13, 2, 12},
+        { 16800000, 480000000, 400, 7,  2, 5},
+        { 19200000, 480000000, 200, 4,  2, 3},
+        { 26000000, 480000000, 960, 26, 2, 12},
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
+                1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
+                1000, tegra30_pll_ops, 0, NULL, pll_ref);
+static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+        /* 1.7 GHz */
+        { 12000000, 1700000000, 850,  6,  1, 8},
+        { 13000000, 1700000000, 915,  7,  1, 8},        /* actual: 1699.2 MHz */
+        { 16800000, 1700000000, 708,  7,  1, 8},        /* actual: 1699.2 MHz */
+        { 19200000, 1700000000, 885,  10, 1, 8},        /* actual: 1699.2 MHz */
+        { 26000000, 1700000000, 850,  13, 1, 8},
+        /* 1.6 GHz */
+        { 12000000, 1600000000, 800,  6,  1, 8},
+        { 13000000, 1600000000, 738,  6,  1, 8},        /* actual: 1599.0 MHz */
+        { 16800000, 1600000000, 857,  9,  1, 8},        /* actual: 1599.7 MHz */
+        { 19200000, 1600000000, 500,  6,  1, 8},
+        { 26000000, 1600000000, 800,  13, 1, 8},
+        /* 1.5 GHz */
+        { 12000000, 1500000000, 750,  6,  1, 8},
+        { 13000000, 1500000000, 923,  8,  1, 8},        /* actual: 1499.8 MHz */
+        { 16800000, 1500000000, 625,  7,  1, 8},
+        { 19200000, 1500000000, 625,  8,  1, 8},
+        { 26000000, 1500000000, 750,  13, 1, 8},
+        /* 1.4 GHz */
+        { 12000000, 1400000000, 700,  6,  1, 8},
+        { 13000000, 1400000000, 969,  9,  1, 8},        /* actual: 1399.7 MHz */
+        { 16800000, 1400000000, 1000, 12, 1, 8},
+        { 19200000, 1400000000, 875,  12, 1, 8},
+        { 26000000, 1400000000, 700,  13, 1, 8},
+        /* 1.3 GHz */
+        { 12000000, 1300000000, 975,  9,  1, 8},
+        { 13000000, 1300000000, 1000, 10, 1, 8},
+        { 16800000, 1300000000, 928,  12, 1, 8},        /* actual: 1299.2 MHz */
+        { 19200000, 1300000000, 812,  12, 1, 8},        /* actual: 1299.2 MHz */
+        { 26000000, 1300000000, 650,  13, 1, 8},
+        /* 1.2 GHz */
+        { 12000000, 1200000000, 1000, 10, 1, 8},
+        { 13000000, 1200000000, 923,  10, 1, 8},        /* actual: 1199.9 MHz */
+        { 16800000, 1200000000, 1000, 14, 1, 8},
+        { 19200000, 1200000000, 1000, 16, 1, 8},
+        { 26000000, 1200000000, 600,  13, 1, 8},
+        /* 1.1 GHz */
+        { 12000000, 1100000000, 825,  9,  1, 8},
+        { 13000000, 1100000000, 846,  10, 1, 8},        /* actual: 1099.8 MHz */
+        { 16800000, 1100000000, 982,  15, 1, 8},        /* actual: 1099.8 MHz */
+        { 19200000, 1100000000, 859,  15, 1, 8},        /* actual: 1099.5 MHz */
+        { 26000000, 1100000000, 550,  13, 1, 8},
+        /* 1 GHz */
+        { 12000000, 1000000000, 1000, 12, 1, 8},
+        { 13000000, 1000000000, 1000, 13, 1, 8},
+        { 16800000, 1000000000, 833,  14, 1, 8},        /* actual: 999.6 MHz */
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
+                2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
+                tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
+DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
+                pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
+static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
+        /* PLLE special case: use cpcon field to store cml divider value */
+        { 12000000,  100000000, 150, 1,  18, 11},
+        { 216000000, 100000000, 200, 18, 24, 13},
+        { 0, 0, 0, 0, 0, 0 },
+};
+DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
+                12000000, 12000000, 1200000000, 2400000000U,
+                tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
+                pll_ref);
+static const char *mux_plle[] = {
+        "pll_e",
+};
+static struct clk *mux_plle_p[] = {
+        &tegra_pll_e,
+};
+static struct clk tegra_cml0;
+static struct clk_tegra tegra_cml0_hw = {
+        .hw = {
+                .clk = &tegra_cml0,
+        },
+        .reg = 0x48c,
+        .fixed_rate = 100000000,
+        .u.periph = {
+                .clk_num = 0,
+        },
+};
+DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
+                mux_plle_p, &tegra_pll_e);
+static struct clk tegra_cml1;
+static struct clk_tegra tegra_cml1_hw = {
+        .hw = {
+                .clk = &tegra_cml1,
+        },
+        .reg = 0x48c,
+        .fixed_rate = 100000000,
+        .u.periph = {
+                .clk_num = 1,
+        },
+};
+DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
+                mux_plle_p, &tegra_pll_e);
+static struct clk tegra_pciex;
+static struct clk_tegra tegra_pciex_hw = {
+        .hw = {
+                .clk = &tegra_pciex,
+        },
+        .reg = 0x48c,
+        .fixed_rate = 100000000,
+        .reset = tegra30_periph_clk_reset,
+        .u.periph = {
+                .clk_num = 74,
+        },
+};
+DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
+                mux_plle_p, &tegra_pll_e);
+#define SYNC_SOURCE(_name)                                      \
+        static struct clk tegra_##_name##_sync;                 \
+        static struct clk_tegra tegra_##_name##_sync_hw = {     \
+                .hw = {                                         \
+                        .clk = &tegra_##_name##_sync,           \
+                },                                              \
+                .max_rate = 24000000,                           \
+                .fixed_rate = 24000000,                         \
+        };                                                      \
+        static struct clk tegra_##_name##_sync = {              \
+                .name = #_name "_sync",                         \
+                .hw = &tegra_##_name##_sync_hw.hw,              \
+                .ops = &tegra_sync_source_ops,                  \
+                .flags = CLK_IS_ROOT,                           \
+        };
+SYNC_SOURCE(spdif_in);
+SYNC_SOURCE(i2s0);
+SYNC_SOURCE(i2s1);
+SYNC_SOURCE(i2s2);
+SYNC_SOURCE(i2s3);
+SYNC_SOURCE(i2s4);
+SYNC_SOURCE(vimclk);
+static struct clk *tegra_sync_source_list[] = {
+        &tegra_spdif_in_sync,
+        &tegra_i2s0_sync,
+        &tegra_i2s1_sync,
+        &tegra_i2s2_sync,
+        &tegra_i2s3_sync,
+        &tegra_i2s4_sync,
+        &tegra_vimclk_sync,
+};
+static const char *mux_audio_sync_clk[] = {
+        "spdif_in_sync",
+        "i2s0_sync",
+        "i2s1_sync",
+        "i2s2_sync",
+        "i2s3_sync",
+        "i2s4_sync",
+        "vimclk_sync",
+};
+#define AUDIO_SYNC_CLK(_name, _index)                           \
+        static struct clk tegra_##_name;                        \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .max_rate = 24000000,                           \
+                .reg = 0x4A0 + (_index) * 4,                    \
+        };                                                      \
+        static struct clk tegra_##_name = {                     \
+                .name = #_name,                                 \
+                .ops = &tegra30_audio_sync_clk_ops,             \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .parent_names = mux_audio_sync_clk,             \
+                .parents = tegra_sync_source_list,              \
+                .num_parents = ARRAY_SIZE(mux_audio_sync_clk),  \
+        };
+AUDIO_SYNC_CLK(audio0, 0);
+AUDIO_SYNC_CLK(audio1, 1);
+AUDIO_SYNC_CLK(audio2, 2);
+AUDIO_SYNC_CLK(audio3, 3);
+AUDIO_SYNC_CLK(audio4, 4);
+AUDIO_SYNC_CLK(audio5, 5);
+static struct clk *tegra_clk_audio_list[] = {
+        &tegra_audio0,
+        &tegra_audio1,
+        &tegra_audio2,
+        &tegra_audio3,
+        &tegra_audio4,
+        &tegra_audio5,  /* SPDIF */
+};
+#define AUDIO_SYNC_2X_CLK(_name, _index)                        \
+        static const char *_name##_parent_names[] = {           \
+                "tegra_" #_name,                                \
+        };                                                      \
+        static struct clk *_name##_parents[] = {                \
+                &tegra_##_name,                                 \
+        };                                                      \
+        static struct clk tegra_##_name##_2x;                   \
+        static struct clk_tegra tegra_##_name##_2x_hw = {       \
+                .hw = {                                         \
+                        .clk = &tegra_##_name##_2x,             \
+                },                                              \
+                .flags = PERIPH_NO_RESET,                       \
+                .max_rate = 48000000,                           \
+                .reg = 0x49C,                                   \
+                .reg_shift = 24 + (_index),                     \
+                .u.periph = {                                   \
+                        .clk_num = 113 + (_index),              \
+                },                                              \
+        };                                                      \
+        static struct clk tegra_##_name##_2x = {                \
+                .name = #_name "_2x",                           \
+                .ops = &tegra30_clk_double_ops,                 \
+                .hw = &tegra_##_name##_2x_hw.hw,                \
+                .parent_names = _name##_parent_names,           \
+                .parents = _name##_parents,                     \
+                .parent = &tegra_##_name,                       \
+                .num_parents = 1,                               \
+        };
+AUDIO_SYNC_2X_CLK(audio0, 0);
+AUDIO_SYNC_2X_CLK(audio1, 1);
+AUDIO_SYNC_2X_CLK(audio2, 2);
+AUDIO_SYNC_2X_CLK(audio3, 3);
+AUDIO_SYNC_2X_CLK(audio4, 4);
+AUDIO_SYNC_2X_CLK(audio5, 5);   /* SPDIF */
+static struct clk *tegra_clk_audio_2x_list[] = {
+        &tegra_audio0_2x,
+        &tegra_audio1_2x,
+        &tegra_audio2_2x,
+        &tegra_audio3_2x,
+        &tegra_audio4_2x,
+        &tegra_audio5_2x,       /* SPDIF */
+};
+#define MUX_I2S_SPDIF(_id)                                      \
+static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = {      \
+        "pll_a_out0",                                           \
+        #_id "_2x",                                             \
+        "pll_p",                                                \
+        "clk_m",                                                \
+};                                                              \
+static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = {    \
+        &tegra_pll_a_out0,                                      \
+        &tegra_##_id##_2x,                                      \
+        &tegra_pll_p,                                           \
+        &tegra_clk_m,                                           \
+};
+MUX_I2S_SPDIF(audio0);
+MUX_I2S_SPDIF(audio1);
+MUX_I2S_SPDIF(audio2);
+MUX_I2S_SPDIF(audio3);
+MUX_I2S_SPDIF(audio4);
+MUX_I2S_SPDIF(audio5);          /* SPDIF */
+static struct clk tegra_extern1;
+static struct clk tegra_extern2;
+static struct clk tegra_extern3;
+/* External clock outputs (through PMC) */
+#define MUX_EXTERN_OUT(_id)                                     \
+static const char *mux_clkm_clkm2_clkm4_extern##_id[] = {       \
+        "clk_m",                                                \
+        "clk_m_div2",                                           \
+        "clk_m_div4",                                           \
+        "extern" #_id,                                          \
+};                                                              \
+static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = {   \
+        &tegra_clk_m,                                           \
+        &tegra_clk_m_div2,                                      \
+        &tegra_clk_m_div4,                                      \
+        &tegra_extern##_id,                                     \
+};
+MUX_EXTERN_OUT(1);
+MUX_EXTERN_OUT(2);
+MUX_EXTERN_OUT(3);
+#define CLK_OUT_CLK(_name, _index)                                      \
+        static struct clk tegra_##_name;                                \
+        static struct clk_tegra tegra_##_name##_hw = {                  \
+                .hw = {                                                 \
+                        .clk = &tegra_##_name,                          \
+                },                                                      \
+                .lookup = {                                             \
+                        .dev_id = #_name,                               \
+                        .con_id = "extern" #_index,                     \
+                },                                                      \
+                .flags = MUX_CLK_OUT,                                   \
+                .fixed_rate = 216000000,                                        \
+                .reg = 0x1a8,                                           \
+                .u.periph = {                                           \
+                        .clk_num = (_index - 1) * 8 + 2,                \
+                },                                                      \
+        };                                                              \
+        static struct clk tegra_##_name = {                             \
+                .name = #_name,                                         \
+                .ops = &tegra_clk_out_ops,                              \
+                .hw = &tegra_##_name##_hw.hw,                           \
+                .parent_names = mux_clkm_clkm2_clkm4_extern##_index,    \
+                .parents = mux_clkm_clkm2_clkm4_extern##_index##_p,     \
+                .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
+        };
+CLK_OUT_CLK(clk_out_1, 1);
+CLK_OUT_CLK(clk_out_2, 2);
+CLK_OUT_CLK(clk_out_3, 3);
+static struct clk *tegra_clk_out_list[] = {
+        &tegra_clk_out_1,
+        &tegra_clk_out_2,
+        &tegra_clk_out_3,
+};
+static const char *mux_sclk[] = {
+        "clk_m",
+        "pll_c_out1",
+        "pll_p_out4",
+        "pll_p_out3",
+        "pll_p_out2",
+        "dummy",
+        "clk_32k",
+        "pll_m_out1",
+};
+static struct clk *mux_sclk_p[] = {
+        &tegra_clk_m,
+        &tegra_pll_c_out1,
+        &tegra_pll_p_out4,
+        &tegra_pll_p_out3,
+        &tegra_pll_p_out2,
+        NULL,
+        &tegra_clk_32k,
+        &tegra_pll_m_out1,
+};
+static struct clk tegra_clk_sclk;
+static struct clk_tegra tegra_clk_sclk_hw = {
+        .hw = {
+                .clk = &tegra_clk_sclk,
+        },
+        .reg = 0x28,
+        .max_rate = 334000000,
+        .min_rate = 40000000,
+};
+static struct clk tegra_clk_sclk = {
+        .name = "sclk",
+        .ops = &tegra30_super_ops,
+        .hw = &tegra_clk_sclk_hw.hw,
+        .parent_names = mux_sclk,
+        .parents = mux_sclk_p,
+        .num_parents = ARRAY_SIZE(mux_sclk),
+};
+static const char *mux_blink[] = {
+        "clk_32k",
+};
+static struct clk *mux_blink_p[] = {
+        &tegra_clk_32k,
+};
+static struct clk tegra_clk_blink;
+static struct clk_tegra tegra_clk_blink_hw = {
+        .hw = {
+                .clk = &tegra_clk_blink,
+        },
+        .reg = 0x40,
+        .max_rate = 32768,
+};
+static struct clk tegra_clk_blink = {
+        .name = "blink",
+        .ops = &tegra30_blink_clk_ops,
+        .hw = &tegra_clk_blink_hw.hw,
+        .parent = &tegra_clk_32k,
+        .parent_names = mux_blink,
+        .parents = mux_blink_p,
+        .num_parents = ARRAY_SIZE(mux_blink),
+};
+static const char *mux_pllm_pllc_pllp_plla[] = {
+        "pll_m",
+        "pll_c",
+        "pll_p",
+        "pll_a_out0",
+};
+static const char *mux_pllp_pllc_pllm_clkm[] = {
+        "pll_p",
+        "pll_c",
+        "pll_m",
+        "clk_m",
+};
+static const char *mux_pllp_clkm[] = {
+        "pll_p",
+        "dummy",
+        "dummy",
+        "clk_m",
+};
+static const char *mux_pllp_plld_pllc_clkm[] = {
+        "pll_p",
+        "pll_d_out0",
+        "pll_c",
+        "clk_m",
+};
+static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
+        "pll_p",
+        "pll_m",
+        "pll_d_out0",
+        "pll_a_out0",
+        "pll_c",
+        "pll_d2_out0",
+        "clk_m",
+};
+static const char *mux_plla_pllc_pllp_clkm[] = {
+        "pll_a_out0",
+        "dummy",
+        "pll_p",
+        "clk_m"
+};
+static const char *mux_pllp_pllc_clk32_clkm[] = {
+        "pll_p",
+        "pll_c",
+        "clk_32k",
+        "clk_m",
+};
+static const char *mux_pllp_pllc_clkm_clk32[] = {
+        "pll_p",
+        "pll_c",
+        "clk_m",
+        "clk_32k",
+};
+static const char *mux_pllp_pllc_pllm[] = {
+        "pll_p",
+        "pll_c",
+        "pll_m",
+};
+static const char *mux_clk_m[] = {
+        "clk_m",
+};
+static const char *mux_pllp_out3[] = {
+        "pll_p_out3",
+};
+static const char *mux_plld_out0[] = {
+        "pll_d_out0",
+};
+static const char *mux_plld_out0_plld2_out0[] = {
+        "pll_d_out0",
+        "pll_d2_out0",
+};
+static const char *mux_clk_32k[] = {
+        "clk_32k",
+};
+static const char *mux_plla_clk32_pllp_clkm_plle[] = {
+        "pll_a_out0",
+        "clk_32k",
+        "pll_p",
+        "clk_m",
+        "pll_e",
+};
+static const char *mux_cclk_g[] = {
+        "clk_m",
+        "pll_c",
+        "clk_32k",
+        "pll_m",
+        "pll_p",
+        "pll_p_out4",
+        "pll_p_out3",
+        "dummy",
+        "pll_x",
+};
+static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
+        &tegra_pll_m,
+        &tegra_pll_c,
+        &tegra_pll_p,
+        &tegra_pll_a_out0,
+};
+static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_pll_m,
+        &tegra_clk_m,
+};
+static struct clk *mux_pllp_clkm_p[] = {
+        &tegra_pll_p,
+        NULL,
+        NULL,
+        &tegra_clk_m,
+};
+static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_d_out0,
+        &tegra_pll_c,
+        &tegra_clk_m,
+};
+static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_m,
+        &tegra_pll_d_out0,
+        &tegra_pll_a_out0,
+        &tegra_pll_c,
+        &tegra_pll_d2_out0,
+        &tegra_clk_m,
+};
+static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
+        &tegra_pll_a_out0,
+        NULL,
+        &tegra_pll_p,
+        &tegra_clk_m,
+};
+static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_clk_32k,
+        &tegra_clk_m,
+};
+static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_clk_m,
+        &tegra_clk_32k,
+};
+static struct clk *mux_pllp_pllc_pllm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_pll_m,
+};
+static struct clk *mux_clk_m_p[] = {
+        &tegra_clk_m,
+};
+static struct clk *mux_pllp_out3_p[] = {
+        &tegra_pll_p_out3,
+};
+static struct clk *mux_plld_out0_p[] = {
+        &tegra_pll_d_out0,
+};
+static struct clk *mux_plld_out0_plld2_out0_p[] = {
+        &tegra_pll_d_out0,
+        &tegra_pll_d2_out0,
+};
+static struct clk *mux_clk_32k_p[] = {
+        &tegra_clk_32k,
+};
+static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
+        &tegra_pll_a_out0,
+        &tegra_clk_32k,
+        &tegra_pll_p,
+        &tegra_clk_m,
+        &tegra_pll_e,
+};
+static struct clk *mux_cclk_g_p[] = {
+        &tegra_clk_m,
+        &tegra_pll_c,
+        &tegra_clk_32k,
+        &tegra_pll_m,
+        &tegra_pll_p,
+        &tegra_pll_p_out4,
+        &tegra_pll_p_out3,
+        NULL,
+        &tegra_pll_x,
+};
+static struct clk tegra_clk_cclk_g;
+static struct clk_tegra tegra_clk_cclk_g_hw = {
+        .hw = {
+                .clk = &tegra_clk_cclk_g,
+        },
+        .flags = DIV_U71 | DIV_U71_INT,
+        .reg = 0x368,
+        .max_rate = 1700000000,
+};
+static struct clk tegra_clk_cclk_g = {
+        .name = "cclk_g",
+        .ops = &tegra30_super_ops,
+        .hw = &tegra_clk_cclk_g_hw.hw,
+        .parent_names = mux_cclk_g,
+        .parents = mux_cclk_g_p,
+        .num_parents = ARRAY_SIZE(mux_cclk_g),
+};
+static const char *mux_twd[] = {
+        "cclk_g",
+};
+static struct clk *mux_twd_p[] = {
+        &tegra_clk_cclk_g,
+};
+static struct clk tegra30_clk_twd;
+static struct clk_tegra tegra30_clk_twd_hw = {
+        .hw = {
+                .clk = &tegra30_clk_twd,
+        },
+        .max_rate = 1400000000,
+        .mul = 1,
+        .div = 2,
+};
+static struct clk tegra30_clk_twd = {
+        .name = "twd",
+        .ops = &tegra30_twd_ops,
+        .hw = &tegra30_clk_twd_hw.hw,
+        .parent = &tegra_clk_cclk_g,
+        .parent_names = mux_twd,
+        .parents = mux_twd_p,
+        .num_parents = ARRAY_SIZE(mux_twd),
+};
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg,   \
+                _max, _inputs, _flags)                  \
+        static struct clk tegra_##_name;                \
+        static struct clk_tegra tegra_##_name##_hw = {  \
+                .hw = {                                 \
+                        .clk = &tegra_##_name,          \
+                },                                      \
+                .lookup = {                             \
+                        .dev_id = _dev,                 \
+                        .con_id = _con,                 \
+                },                                      \
+                .reg = _reg,                            \
+                .flags = _flags,                        \
+                .max_rate = _max,                       \
+                .u.periph = {                           \
+                        .clk_num = _clk_num,            \
+                },                                      \
+                .reset = &tegra30_periph_clk_reset,     \
+        };                                              \
+        static struct clk tegra_##_name = {             \
+                .name = #_name,                         \
+                .ops = &tegra30_periph_clk_ops,         \
+                .hw = &tegra_##_name##_hw.hw,           \
+                .parent_names = _inputs,                \
+                .parents = _inputs##_p,                 \
+                .num_parents = ARRAY_SIZE(_inputs),     \
+        };
+PERIPH_CLK(apbdma,      "tegra-apbdma",         NULL,   34,     0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(rtc,         "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB);
+PERIPH_CLK(kbc,         "tegra-kbc",            NULL,   36,     0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB);
+PERIPH_CLK(timer,       "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(kfuse,       "kfuse-tegra",          NULL,   40,     0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(fuse,        "fuse-tegra",           "fuse", 39,     0,      26000000,  mux_clk_m,                   PERIPH_ON_APB);
+PERIPH_CLK(fuse_burn,   "fuse-tegra",           "fuse_burn",    39,     0,      26000000,  mux_clk_m,           PERIPH_ON_APB);
+PERIPH_CLK(apbif,       "tegra30-ahub",         "apbif", 107,   0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(i2s0,        "tegra30-i2s.0",        NULL,   30,     0x1d8,  26000000,  mux_pllaout0_audio0_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s1,        "tegra30-i2s.1",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio1_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s2,        "tegra30-i2s.2",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s3,        "tegra30-i2s.3",        NULL,   101,    0x3bc,  26000000,  mux_pllaout0_audio3_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s4,        "tegra30-i2s.4",        NULL,   102,    0x3c0,  26000000,  mux_pllaout0_audio4_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(spdif_out,   "tegra30-spdif",        "spdif_out",    10,     0x108,  100000000, mux_pllaout0_audio5_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(spdif_in,    "tegra30-spdif",        "spdif_in",     10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(pwm,         "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_clk32_clkm,    MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(d_audio,     "tegra30-ahub",         "d_audio", 106, 0x3d0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
+PERIPH_CLK(dam0,        "tegra30-dam.0",        NULL,   108,    0x3d8,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
+PERIPH_CLK(dam1,        "tegra30-dam.1",        NULL,   109,    0x3dc,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
+PERIPH_CLK(dam2,        "tegra30-dam.2",        NULL,   110,    0x3e0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
+PERIPH_CLK(hda,         "tegra30-hda",          "hda",  125,    0x428,  108000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(hda2codec_2x,        "tegra30-hda",  "hda2codec",    111,    0x3e4,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(hda2hdmi,    "tegra30-hda",          "hda2hdmi",     128,    0,      48000000,  mux_clk_m,                   0);
+PERIPH_CLK(sbc1,        "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc2,        "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc3,        "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc4,        "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc5,        "spi_tegra.4",          NULL,   104,    0x3c8,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc6,        "spi_tegra.5",          NULL,   105,    0x3cc,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sata_oob,    "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sata,        "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sata_cold,   "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   0);
+PERIPH_CLK(ndflash,     "tegra_nand",           NULL,   13,     0x160,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(ndspeed,     "tegra_nand_speed",     NULL,   80,     0x3f8,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(vfir,        "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sdmmc1,      "sdhci-tegra.0",        NULL,   14,     0x150,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc2,      "sdhci-tegra.1",        NULL,   9,      0x154,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc3,      "sdhci-tegra.2",        NULL,   69,     0x1bc,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc4,      "sdhci-tegra.3",        NULL,   15,     0x164,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vcp,         "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(bsea,        "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(bsev,        "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(vde,         "vde",                  NULL,   61,     0x1c8,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(csite,       "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* max rate ??? */
+PERIPH_CLK(la,          "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(owr,         "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(nor,         "nor",                  NULL,   42,     0x1d0,  127000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(mipi,        "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
+PERIPH_CLK(i2c1,        "tegra-i2c.0",          "div-clk", 12,  0x124,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c2,        "tegra-i2c.1",          "div-clk", 54,  0x198,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c3,        "tegra-i2c.2",          "div-clk", 67,  0x1b8,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c4,        "tegra-i2c.3",          "div-clk", 103, 0x3c4,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c5,        "tegra-i2c.4",          "div-clk", 47,  0x128,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(uarta,       "tegra-uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartb,       "tegra-uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartc,       "tegra-uart.2",         NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartd,       "tegra-uart.3",         NULL,   65,     0x1c0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uarte,       "tegra-uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(vi,          "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(3d,          "3d",                   NULL,   24,     0x158,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
+PERIPH_CLK(3d2,         "3d2",                  NULL,   98,     0x3b0,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
+PERIPH_CLK(2d,          "2d",                   NULL,   21,     0x15c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
+PERIPH_CLK(vi_sensor,   "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET);
+PERIPH_CLK(epp,         "epp",                  NULL,   19,     0x16c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(mpe,         "mpe",                  NULL,   60,     0x170,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(host1x,      "host1x",               NULL,   28,     0x180,  260000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(cve,         "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvo,         "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(dtv,         "dtv",                  NULL,   79,     0x1dc,  250000000, mux_clk_m,                   0);
+PERIPH_CLK(hdmi,        "hdmi",                 NULL,   51,     0x18c,  148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8 | DIV_U71);
+PERIPH_CLK(tvdac,       "tvdac",                NULL,   53,     0x194,  220000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(disp1,       "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8);
+PERIPH_CLK(disp2,       "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8);
+PERIPH_CLK(usbd,        "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(usb2,        "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(usb3,        "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(dsia,        "tegradc.0",            "dsia", 48,     0,      500000000, mux_plld_out0,               0);
+PERIPH_CLK(csi,         "tegra_camera",         "csi",  52,     0,      102000000, mux_pllp_out3,               0);
+PERIPH_CLK(isp,         "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0); /* same frequency as VI */
+PERIPH_CLK(csus,        "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET);
+PERIPH_CLK(tsensor,     "tegra-tsensor",        NULL,   100,    0x3b8,  216000000, mux_pllp_pllc_clkm_clk32,    MUX | DIV_U71);
+PERIPH_CLK(actmon,      "actmon",               NULL,   119,    0x3e8,  216000000, mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71);
+PERIPH_CLK(extern1,     "extern1",              NULL,   120,    0x3ec,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
+PERIPH_CLK(extern2,     "extern2",              NULL,   121,    0x3f0,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
+PERIPH_CLK(extern3,     "extern3",              NULL,   122,    0x3f4,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
+PERIPH_CLK(i2cslow,     "i2cslow",              NULL,   81,     0x3fc,  26000000,  mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(pcie,        "tegra-pcie",           "pcie", 70,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(afi,         "tegra-pcie",           "afi",  72,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(se,          "se",                   NULL,   127,    0x42c,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT);
+static struct clk tegra_dsib;
+static struct clk_tegra tegra_dsib_hw = {
+        .hw = {
+                .clk = &tegra_dsib,
+        },
+        .lookup = {
+                .dev_id = "tegradc.1",
+                .con_id = "dsib",
+        },
+        .reg = 0xd0,
+        .flags = MUX | PLLD,
+        .max_rate = 500000000,
+        .u.periph = {
+                .clk_num = 82,
+        },
+        .reset = &tegra30_periph_clk_reset,
+};
+static struct clk tegra_dsib = {
+        .name = "dsib",
+        .ops = &tegra30_dsib_clk_ops,
+        .hw = &tegra_dsib_hw.hw,
+        .parent_names = mux_plld_out0_plld2_out0,
+        .parents = mux_plld_out0_plld2_out0_p,
+        .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
+};
+struct clk *tegra_list_clks[] = {
+        &tegra_apbdma,
+        &tegra_rtc,
+        &tegra_kbc,
+        &tegra_kfuse,
+        &tegra_fuse,
+        &tegra_fuse_burn,
+        &tegra_apbif,
+        &tegra_i2s0,
+        &tegra_i2s1,
+        &tegra_i2s2,
+        &tegra_i2s3,
+        &tegra_i2s4,
+        &tegra_spdif_out,
+        &tegra_spdif_in,
+        &tegra_pwm,
+        &tegra_d_audio,
+        &tegra_dam0,
+        &tegra_dam1,
+        &tegra_dam2,
+        &tegra_hda,
+        &tegra_hda2codec_2x,
+        &tegra_hda2hdmi,
+        &tegra_sbc1,
+        &tegra_sbc2,
+        &tegra_sbc3,
+        &tegra_sbc4,
+        &tegra_sbc5,
+        &tegra_sbc6,
+        &tegra_sata_oob,
+        &tegra_sata,
+        &tegra_sata_cold,
+        &tegra_ndflash,
+        &tegra_ndspeed,
+        &tegra_vfir,
+        &tegra_sdmmc1,
+        &tegra_sdmmc2,
+        &tegra_sdmmc3,
+        &tegra_sdmmc4,
+        &tegra_vcp,
+        &tegra_bsea,
+        &tegra_bsev,
+        &tegra_vde,
+        &tegra_csite,
+        &tegra_la,
+        &tegra_owr,
+        &tegra_nor,
+        &tegra_mipi,
+        &tegra_i2c1,
+        &tegra_i2c2,
+        &tegra_i2c3,
+        &tegra_i2c4,
+        &tegra_i2c5,
+        &tegra_uarta,
+        &tegra_uartb,
+        &tegra_uartc,
+        &tegra_uartd,
+        &tegra_uarte,
+        &tegra_vi,
+        &tegra_3d,
+        &tegra_3d2,
+        &tegra_2d,
+        &tegra_vi_sensor,
+        &tegra_epp,
+        &tegra_mpe,
+        &tegra_host1x,
+        &tegra_cve,
+        &tegra_tvo,
+        &tegra_dtv,
+        &tegra_hdmi,
+        &tegra_tvdac,
+        &tegra_disp1,
+        &tegra_disp2,
+        &tegra_usbd,
+        &tegra_usb2,
+        &tegra_usb3,
+        &tegra_dsia,
+        &tegra_dsib,
+        &tegra_csi,
+        &tegra_isp,
+        &tegra_csus,
+        &tegra_tsensor,
+        &tegra_actmon,
+        &tegra_extern1,
+        &tegra_extern2,
+        &tegra_extern3,
+        &tegra_i2cslow,
+        &tegra_pcie,
+        &tegra_afi,
+        &tegra_se,
+};
+#define CLK_DUPLICATE(_name, _dev, _con)        \
+        {                                       \
+                .name   = _name,                \
+                .lookup = {                     \
+                        .dev_id = _dev,         \
+                        .con_id = _con,         \
+                },                              \
+        }
+/* Some clocks may be used by different drivers depending on the board
+ * configuration.  List those here to register them twice in the clock lookup
+ * table under two names.
+ */
+struct clk_duplicate tegra_clk_duplicates[] = {
+        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
+        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
+        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
+        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
+        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
+        CLK_DUPLICATE("usbd", "utmip-pad", NULL),
+        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
+        CLK_DUPLICATE("usbd", "tegra-otg", NULL),
+        CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
+        CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
+        CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
+        CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
+        CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
+        CLK_DUPLICATE("bsev", "nvavp", "bsev"),
+        CLK_DUPLICATE("vde", "tegra-aes", "vde"),
+        CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
+        CLK_DUPLICATE("bsea", "nvavp", "bsea"),
+        CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
+        CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
+        CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
+        CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
+        CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
+        CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
+        CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
+        CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
+        CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
+        CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
+        CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
+        CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
+        CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
+        CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
+        CLK_DUPLICATE("twd", "smp_twd", NULL),
+        CLK_DUPLICATE("vcp", "nvavp", "vcp"),
+        CLK_DUPLICATE("i2s0", NULL, "i2s0"),
+        CLK_DUPLICATE("i2s1", NULL, "i2s1"),
+        CLK_DUPLICATE("i2s2", NULL, "i2s2"),
+        CLK_DUPLICATE("i2s3", NULL, "i2s3"),
+        CLK_DUPLICATE("i2s4", NULL, "i2s4"),
+        CLK_DUPLICATE("dam0", NULL, "dam0"),
+        CLK_DUPLICATE("dam1", NULL, "dam1"),
+        CLK_DUPLICATE("dam2", NULL, "dam2"),
+        CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"),
+};
+struct clk *tegra_ptr_clks[] = {
+        &tegra_clk_32k,
+        &tegra_clk_m,
+        &tegra_clk_m_div2,
+        &tegra_clk_m_div4,
+        &tegra_pll_ref,
+        &tegra_pll_m,
+        &tegra_pll_m_out1,
+        &tegra_pll_c,
+        &tegra_pll_c_out1,
+        &tegra_pll_p,
+        &tegra_pll_p_out1,
+        &tegra_pll_p_out2,
+        &tegra_pll_p_out3,
+        &tegra_pll_p_out4,
+        &tegra_pll_a,
+        &tegra_pll_a_out0,
+        &tegra_pll_d,
+        &tegra_pll_d_out0,
+        &tegra_pll_d2,
+        &tegra_pll_d2_out0,
+        &tegra_pll_u,
+        &tegra_pll_x,
+        &tegra_pll_x_out0,
+        &tegra_pll_e,
+        &tegra_clk_cclk_g,
+        &tegra_cml0,
+        &tegra_cml1,
+        &tegra_pciex,
+        &tegra_clk_sclk,
+        &tegra_clk_blink,
+        &tegra30_clk_twd,
+};
+static void tegra30_init_one_clock(struct clk *c)
+{
+        struct clk_tegra *clk = to_clk_tegra(c->hw);
+        __clk_init(NULL, c);
+        INIT_LIST_HEAD(&clk->shared_bus_list);
+        if (!clk->lookup.dev_id && !clk->lookup.con_id)
+                clk->lookup.con_id = c->name;
+        clk->lookup.clk = c;
+        clkdev_add(&clk->lookup);
+        tegra_clk_add(c);
+}
+void __init tegra30_init_clocks(void)
+{
+        int i;
+        struct clk *c;
+        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
+                tegra30_init_one_clock(tegra_ptr_clks[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
+                tegra30_init_one_clock(tegra_list_clks[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+                if (!c) {
+                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
+                                tegra_clk_duplicates[i].name);
+                        continue;
+                }
+                tegra_clk_duplicates[i].lookup.clk = c;
+                clkdev_add(&tegra_clk_duplicates[i].lookup);
+        }
+        for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
+                tegra30_init_one_clock(tegra_sync_source_list[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
+                tegra30_init_one_clock(tegra_clk_audio_list[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
+                tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
+                tegra30_init_one_clock(tegra_clk_out_list[i]);
+        tegra30_cpu_car_ops_init();
+}
diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/arch/arm/mach-tegra/tegra_cpu_car.h
new file mode 100644
index 000000000000..30d063ad2bef
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra_cpu_car.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __MACH_TEGRA_CPU_CAR_H
+#define __MACH_TEGRA_CPU_CAR_H
+/*
+ * Tegra CPU clock and reset control ops
+ *
+ * wait_for_reset:
+ *      keep waiting until the CPU in reset state
+ * put_in_reset:
+ *      put the CPU in reset state
+ * out_of_reset:
+ *      release the CPU from reset state
+ * enable_clock:
+ *      CPU clock un-gate
+ * disable_clock:
+ *      CPU clock gate
+ */
+struct tegra_cpu_car_ops {
+        void (*wait_for_reset)(u32 cpu);
+        void (*put_in_reset)(u32 cpu);
+        void (*out_of_reset)(u32 cpu);
+        void (*enable_clock)(u32 cpu);
+        void (*disable_clock)(u32 cpu);
+};
+extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
+static inline void tegra_wait_cpu_in_reset(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
+                return;
+        tegra_cpu_car_ops->wait_for_reset(cpu);
+}
+static inline void tegra_put_cpu_in_reset(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
+                return;
+        tegra_cpu_car_ops->put_in_reset(cpu);
+}
+static inline void tegra_cpu_out_of_reset(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
+                return;
+        tegra_cpu_car_ops->out_of_reset(cpu);
+}
+static inline void tegra_enable_cpu_clock(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
+                return;
+        tegra_cpu_car_ops->enable_clock(cpu);
+}
+static inline void tegra_disable_cpu_clock(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
+                return;
+        tegra_cpu_car_ops->disable_clock(cpu);
+}
+void tegra20_cpu_car_ops_init(void);
+void tegra30_cpu_car_ops_init(void);
+#endif /* __MACH_TEGRA_CPU_CAR_H */
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 57b5bdc13b9b..eccdce983043 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -33,7 +33,6 @@
 #include <mach/iomap.h>
 #include <mach/irqs.h>
-#include <mach/suspend.h>
 #include "board.h"
 #include "clock.h"
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
deleted file mode 100644
index 022b33a05c3a..000000000000
--- a/arch/arm/mach-tegra/usb_phy.c
+++ /dev/null
@@ -1,817 +0,0 @@
-/*
- * arch/arm/mach-tegra/usb_phy.c
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Erik Gilling <konkers@google.com>
- *      Benoit Goby <benoit@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/resource.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/of_gpio.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <asm/mach-types.h>
-#include <mach/gpio-tegra.h>
-#include <mach/usb_phy.h>
-#include <mach/iomap.h>
-#define ULPI_VIEWPORT           0x170
-#define USB_PORTSC1             0x184
-#define   USB_PORTSC1_PTS(x)    (((x) & 0x3) << 30)
-#define   USB_PORTSC1_PSPD(x)   (((x) & 0x3) << 26)
-#define   USB_PORTSC1_PHCD      (1 << 23)
-#define   USB_PORTSC1_WKOC      (1 << 22)
-#define   USB_PORTSC1_WKDS      (1 << 21)
-#define   USB_PORTSC1_WKCN      (1 << 20)
-#define   USB_PORTSC1_PTC(x)    (((x) & 0xf) << 16)
-#define   USB_PORTSC1_PP        (1 << 12)
-#define   USB_PORTSC1_SUSP      (1 << 7)
-#define   USB_PORTSC1_PE        (1 << 2)
-#define   USB_PORTSC1_CCS       (1 << 0)
-#define USB_SUSP_CTRL           0x400
-#define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
-#define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
-#define   USB_SUSP_CLR          (1 << 5)
-#define   USB_PHY_CLK_VALID     (1 << 7)
-#define   UTMIP_RESET                   (1 << 11)
-#define   UHSIC_RESET                   (1 << 11)
-#define   UTMIP_PHY_ENABLE              (1 << 12)
-#define   ULPI_PHY_ENABLE       (1 << 13)
-#define   USB_SUSP_SET          (1 << 14)
-#define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
-#define USB1_LEGACY_CTRL        0x410
-#define   USB1_NO_LEGACY_MODE                   (1 << 0)
-#define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
-#define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
-#define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
-                                                (1 << 1)
-#define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
-#define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
-#define ULPI_TIMING_CTRL_0      0x424
-#define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
-#define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
-#define ULPI_TIMING_CTRL_1      0x428
-#define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
-#define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
-#define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
-#define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
-#define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
-#define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
-#define UTMIP_PLL_CFG1          0x804
-#define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
-#define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
-#define UTMIP_XCVR_CFG0         0x808
-#define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
-#define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
-#define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
-#define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
-#define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
-#define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
-#define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
-#define UTMIP_BIAS_CFG0         0x80c
-#define   UTMIP_OTGPD                   (1 << 11)
-#define   UTMIP_BIASPD                  (1 << 10)
-#define UTMIP_HSRX_CFG0         0x810
-#define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
-#define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
-#define UTMIP_HSRX_CFG1         0x814
-#define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
-#define UTMIP_TX_CFG0           0x820
-#define   UTMIP_FS_PREABMLE_J           (1 << 19)
-#define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
-#define UTMIP_MISC_CFG0         0x824
-#define   UTMIP_DPDM_OBSERVE            (1 << 26)
-#define   UTMIP_DPDM_OBSERVE_SEL(x)     (((x) & 0xf) << 27)
-#define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
-#define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
-#define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
-#define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
-#define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
-#define UTMIP_MISC_CFG1         0x828
-#define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
-#define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
-#define UTMIP_DEBOUNCE_CFG0     0x82c
-#define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
-#define UTMIP_BAT_CHRG_CFG0     0x830
-#define   UTMIP_PD_CHRG                 (1 << 0)
-#define UTMIP_SPARE_CFG0        0x834
-#define   FUSE_SETUP_SEL                (1 << 3)
-#define UTMIP_XCVR_CFG1         0x838
-#define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
-#define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
-#define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
-#define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
-#define UTMIP_BIAS_CFG1         0x83c
-#define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
-static DEFINE_SPINLOCK(utmip_pad_lock);
-static int utmip_pad_count;
-struct tegra_xtal_freq {
-        int freq;
-        u8 enable_delay;
-        u8 stable_count;
-        u8 active_delay;
-        u8 xtal_freq_count;
-        u16 debounce;
-};
-static const struct tegra_xtal_freq tegra_freq_table[] = {
-        {
-                .freq = 12000000,
-                .enable_delay = 0x02,
-                .stable_count = 0x2F,
-                .active_delay = 0x04,
-                .xtal_freq_count = 0x76,
-                .debounce = 0x7530,
-        },
-        {
-                .freq = 13000000,
-                .enable_delay = 0x02,
-                .stable_count = 0x33,
-                .active_delay = 0x05,
-                .xtal_freq_count = 0x7F,
-                .debounce = 0x7EF4,
-        },
-        {
-                .freq = 19200000,
-                .enable_delay = 0x03,
-                .stable_count = 0x4B,
-                .active_delay = 0x06,
-                .xtal_freq_count = 0xBB,
-                .debounce = 0xBB80,
-        },
-        {
-                .freq = 26000000,
-                .enable_delay = 0x04,
-                .stable_count = 0x66,
-                .active_delay = 0x09,
-                .xtal_freq_count = 0xFE,
-                .debounce = 0xFDE8,
-        },
-};
-static struct tegra_utmip_config utmip_default[] = {
-        [0] = {
-                .hssync_start_delay = 9,
-                .idle_wait_delay = 17,
-                .elastic_limit = 16,
-                .term_range_adj = 6,
-                .xcvr_setup = 9,
-                .xcvr_lsfslew = 1,
-                .xcvr_lsrslew = 1,
-        },
-        [2] = {
-                .hssync_start_delay = 9,
-                .idle_wait_delay = 17,
-                .elastic_limit = 16,
-                .term_range_adj = 6,
-                .xcvr_setup = 9,
-                .xcvr_lsfslew = 2,
-                .xcvr_lsrslew = 2,
-        },
-};
-static inline bool phy_is_ulpi(struct tegra_usb_phy *phy)
-{
-        return (phy->instance == 1);
-}
-static int utmip_pad_open(struct tegra_usb_phy *phy)
-{
-        phy->pad_clk = clk_get_sys("utmip-pad", NULL);
-        if (IS_ERR(phy->pad_clk)) {
-                pr_err("%s: can't get utmip pad clock\n", __func__);
-                return PTR_ERR(phy->pad_clk);
-        }
-        if (phy->instance == 0) {
-                phy->pad_regs = phy->regs;
-        } else {
-                phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
-                if (!phy->pad_regs) {
-                        pr_err("%s: can't remap usb registers\n", __func__);
-                        clk_put(phy->pad_clk);
-                        return -ENOMEM;
-                }
-        }
-        return 0;
-}
-static void utmip_pad_close(struct tegra_usb_phy *phy)
-{
-        if (phy->instance != 0)
-                iounmap(phy->pad_regs);
-        clk_put(phy->pad_clk);
-}
-static void utmip_pad_power_on(struct tegra_usb_phy *phy)
-{
-        unsigned long val, flags;
-        void __iomem *base = phy->pad_regs;
-        clk_prepare_enable(phy->pad_clk);
-        spin_lock_irqsave(&utmip_pad_lock, flags);
-        if (utmip_pad_count++ == 0) {
-                val = readl(base + UTMIP_BIAS_CFG0);
-                val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
-                writel(val, base + UTMIP_BIAS_CFG0);
-        }
-        spin_unlock_irqrestore(&utmip_pad_lock, flags);
-        clk_disable_unprepare(phy->pad_clk);
-}
-static int utmip_pad_power_off(struct tegra_usb_phy *phy)
-{
-        unsigned long val, flags;
-        void __iomem *base = phy->pad_regs;
-        if (!utmip_pad_count) {
-                pr_err("%s: utmip pad already powered off\n", __func__);
-                return -EINVAL;
-        }
-        clk_prepare_enable(phy->pad_clk);
-        spin_lock_irqsave(&utmip_pad_lock, flags);
-        if (--utmip_pad_count == 0) {
-                val = readl(base + UTMIP_BIAS_CFG0);
-                val |= UTMIP_OTGPD | UTMIP_BIASPD;
-                writel(val, base + UTMIP_BIAS_CFG0);
-        }
-        spin_unlock_irqrestore(&utmip_pad_lock, flags);
-        clk_disable_unprepare(phy->pad_clk);
-        return 0;
-}
-static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
-{
-        unsigned long timeout = 2000;
-        do {
-                if ((readl(reg) & mask) == result)
-                        return 0;
-                udelay(1);
-                timeout--;
-        } while (timeout);
-        return -1;
-}
-static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-        if (phy->instance == 0) {
-                val = readl(base + USB_SUSP_CTRL);
-                val |= USB_SUSP_SET;
-                writel(val, base + USB_SUSP_CTRL);
-                udelay(10);
-                val = readl(base + USB_SUSP_CTRL);
-                val &= ~USB_SUSP_SET;
-                writel(val, base + USB_SUSP_CTRL);
-        }
-        if (phy->instance == 2) {
-                val = readl(base + USB_PORTSC1);
-                val |= USB_PORTSC1_PHCD;
-                writel(val, base + USB_PORTSC1);
-        }
-        if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
-                pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
-}
-static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-        if (phy->instance == 0) {
-                val = readl(base + USB_SUSP_CTRL);
-                val |= USB_SUSP_CLR;
-                writel(val, base + USB_SUSP_CTRL);
-                udelay(10);
-                val = readl(base + USB_SUSP_CTRL);
-                val &= ~USB_SUSP_CLR;
-                writel(val, base + USB_SUSP_CTRL);
-        }
-        if (phy->instance == 2) {
-                val = readl(base + USB_PORTSC1);
-                val &= ~USB_PORTSC1_PHCD;
-                writel(val, base + USB_PORTSC1);
-        }
-        if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
-                                                     USB_PHY_CLK_VALID))
-                pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
-}
-static int utmi_phy_power_on(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-        struct tegra_utmip_config *config = phy->config;
-        val = readl(base + USB_SUSP_CTRL);
-        val |= UTMIP_RESET;
-        writel(val, base + USB_SUSP_CTRL);
-        if (phy->instance == 0) {
-                val = readl(base + USB1_LEGACY_CTRL);
-                val |= USB1_NO_LEGACY_MODE;
-                writel(val, base + USB1_LEGACY_CTRL);
-        }
-        val = readl(base + UTMIP_TX_CFG0);
-        val &= ~UTMIP_FS_PREABMLE_J;
-        writel(val, base + UTMIP_TX_CFG0);
-        val = readl(base + UTMIP_HSRX_CFG0);
-        val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
-        val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
-        val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
-        writel(val, base + UTMIP_HSRX_CFG0);
-        val = readl(base + UTMIP_HSRX_CFG1);
-        val &= ~UTMIP_HS_SYNC_START_DLY(~0);
-        val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
-        writel(val, base + UTMIP_HSRX_CFG1);
-        val = readl(base + UTMIP_DEBOUNCE_CFG0);
-        val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
-        val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
-        writel(val, base + UTMIP_DEBOUNCE_CFG0);
-        val = readl(base + UTMIP_MISC_CFG0);
-        val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
-        writel(val, base + UTMIP_MISC_CFG0);
-        val = readl(base + UTMIP_MISC_CFG1);
-        val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
-        val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
-                UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
-        writel(val, base + UTMIP_MISC_CFG1);
-        val = readl(base + UTMIP_PLL_CFG1);
-        val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
-        val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
-                UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
-        writel(val, base + UTMIP_PLL_CFG1);
-        if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
-                val = readl(base + USB_SUSP_CTRL);
-                val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
-                writel(val, base + USB_SUSP_CTRL);
-        }
-        utmip_pad_power_on(phy);
-        val = readl(base + UTMIP_XCVR_CFG0);
-        val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
-                 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) |
-                 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) |
-                 UTMIP_XCVR_HSSLEW_MSB(~0));
-        val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
-        val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
-        val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
-        writel(val, base + UTMIP_XCVR_CFG0);
-        val = readl(base + UTMIP_XCVR_CFG1);
-        val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
-                 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
-        val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
-        writel(val, base + UTMIP_XCVR_CFG1);
-        val = readl(base + UTMIP_BAT_CHRG_CFG0);
-        val &= ~UTMIP_PD_CHRG;
-        writel(val, base + UTMIP_BAT_CHRG_CFG0);
-        val = readl(base + UTMIP_BIAS_CFG1);
-        val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
-        val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
-        writel(val, base + UTMIP_BIAS_CFG1);
-        if (phy->instance == 0) {
-                val = readl(base + UTMIP_SPARE_CFG0);
-                if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
-                        val &= ~FUSE_SETUP_SEL;
-                else
-                        val |= FUSE_SETUP_SEL;
-                writel(val, base + UTMIP_SPARE_CFG0);
-        }
-        if (phy->instance == 2) {
-                val = readl(base + USB_SUSP_CTRL);
-                val |= UTMIP_PHY_ENABLE;
-                writel(val, base + USB_SUSP_CTRL);
-        }
-        val = readl(base + USB_SUSP_CTRL);
-        val &= ~UTMIP_RESET;
-        writel(val, base + USB_SUSP_CTRL);
-        if (phy->instance == 0) {
-                val = readl(base + USB1_LEGACY_CTRL);
-                val &= ~USB1_VBUS_SENSE_CTL_MASK;
-                val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
-                writel(val, base + USB1_LEGACY_CTRL);
-                val = readl(base + USB_SUSP_CTRL);
-                val &= ~USB_SUSP_SET;
-                writel(val, base + USB_SUSP_CTRL);
-        }
-        utmi_phy_clk_enable(phy);
-        if (phy->instance == 2) {
-                val = readl(base + USB_PORTSC1);
-                val &= ~USB_PORTSC1_PTS(~0);
-                writel(val, base + USB_PORTSC1);
-        }
-        return 0;
-}
-static void utmi_phy_power_off(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-        utmi_phy_clk_disable(phy);
-        if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
-                val = readl(base + USB_SUSP_CTRL);
-                val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
-                val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
-                writel(val, base + USB_SUSP_CTRL);
-        }
-        val = readl(base + USB_SUSP_CTRL);
-        val |= UTMIP_RESET;
-        writel(val, base + USB_SUSP_CTRL);
-        val = readl(base + UTMIP_BAT_CHRG_CFG0);
-        val |= UTMIP_PD_CHRG;
-        writel(val, base + UTMIP_BAT_CHRG_CFG0);
-        val = readl(base + UTMIP_XCVR_CFG0);
-        val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
-               UTMIP_FORCE_PDZI_POWERDOWN;
-        writel(val, base + UTMIP_XCVR_CFG0);
-        val = readl(base + UTMIP_XCVR_CFG1);
-        val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
-               UTMIP_FORCE_PDDR_POWERDOWN;
-        writel(val, base + UTMIP_XCVR_CFG1);
-        utmip_pad_power_off(phy);
-}
-static void utmi_phy_preresume(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-        val = readl(base + UTMIP_TX_CFG0);
-        val |= UTMIP_HS_DISCON_DISABLE;
-        writel(val, base + UTMIP_TX_CFG0);
-}
-static void utmi_phy_postresume(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-        val = readl(base + UTMIP_TX_CFG0);
-        val &= ~UTMIP_HS_DISCON_DISABLE;
-        writel(val, base + UTMIP_TX_CFG0);
-}
-static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
-                                   enum tegra_usb_phy_port_speed port_speed)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-        val = readl(base + UTMIP_MISC_CFG0);
-        val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
-        if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
-                val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
-        else
-                val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
-        writel(val, base + UTMIP_MISC_CFG0);
-        udelay(1);
-        val = readl(base + UTMIP_MISC_CFG0);
-        val |= UTMIP_DPDM_OBSERVE;
-        writel(val, base + UTMIP_MISC_CFG0);
-        udelay(10);
-}
-static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-        val = readl(base + UTMIP_MISC_CFG0);
-        val &= ~UTMIP_DPDM_OBSERVE;
-        writel(val, base + UTMIP_MISC_CFG0);
-        udelay(10);
-}
-static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
-{
-        int ret;
-        unsigned long val;
-        void __iomem *base = phy->regs;
-        struct tegra_ulpi_config *config = phy->config;
-        gpio_direction_output(config->reset_gpio, 0);
-        msleep(5);
-        gpio_direction_output(config->reset_gpio, 1);
-        clk_prepare_enable(phy->clk);
-        msleep(1);
-        val = readl(base + USB_SUSP_CTRL);
-        val |= UHSIC_RESET;
-        writel(val, base + USB_SUSP_CTRL);
-        val = readl(base + ULPI_TIMING_CTRL_0);
-        val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
-        writel(val, base + ULPI_TIMING_CTRL_0);
-        val = readl(base + USB_SUSP_CTRL);
-        val |= ULPI_PHY_ENABLE;
-        writel(val, base + USB_SUSP_CTRL);
-        val = 0;
-        writel(val, base + ULPI_TIMING_CTRL_1);
-        val |= ULPI_DATA_TRIMMER_SEL(4);
-        val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
-        val |= ULPI_DIR_TRIMMER_SEL(4);
-        writel(val, base + ULPI_TIMING_CTRL_1);
-        udelay(10);
-        val |= ULPI_DATA_TRIMMER_LOAD;
-        val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
-        val |= ULPI_DIR_TRIMMER_LOAD;
-        writel(val, base + ULPI_TIMING_CTRL_1);
-        /* Fix VbusInvalid due to floating VBUS */
-        ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
-        if (ret) {
-                pr_err("%s: ulpi write failed\n", __func__);
-                return ret;
-        }
-        ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
-        if (ret) {
-                pr_err("%s: ulpi write failed\n", __func__);
-                return ret;
-        }
-        val = readl(base + USB_PORTSC1);
-        val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
-        writel(val, base + USB_PORTSC1);
-        val = readl(base + USB_SUSP_CTRL);
-        val |= USB_SUSP_CLR;
-        writel(val, base + USB_SUSP_CTRL);
-        udelay(100);
-        val = readl(base + USB_SUSP_CTRL);
-        val &= ~USB_SUSP_CLR;
-        writel(val, base + USB_SUSP_CTRL);
-        return 0;
-}
-static void ulpi_phy_power_off(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-        struct tegra_ulpi_config *config = phy->config;
-        /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
-         * Controller to immediately bring the ULPI PHY out of low power
-         */
-        val = readl(base + USB_PORTSC1);
-        val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
-        writel(val, base + USB_PORTSC1);
-        gpio_direction_output(config->reset_gpio, 0);
-        clk_disable(phy->clk);
-}
-struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
-        void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode)
-{
-        struct tegra_usb_phy *phy;
-        struct tegra_ulpi_config *ulpi_config;
-        unsigned long parent_rate;
-        int i;
-        int err;
-        phy = kmalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
-        if (!phy)
-                return ERR_PTR(-ENOMEM);
-        phy->instance = instance;
-        phy->regs = regs;
-        phy->config = config;
-        phy->mode = phy_mode;
-        if (!phy->config) {
-                if (phy_is_ulpi(phy)) {
-                        pr_err("%s: ulpi phy configuration missing", __func__);
-                        err = -EINVAL;
-                        goto err0;
-                } else {
-                        phy->config = &utmip_default[instance];
-                }
-        }
-        phy->pll_u = clk_get_sys(NULL, "pll_u");
-        if (IS_ERR(phy->pll_u)) {
-                pr_err("Can't get pll_u clock\n");
-                err = PTR_ERR(phy->pll_u);
-                goto err0;
-        }
-        clk_prepare_enable(phy->pll_u);
-        parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
-        for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
-                if (tegra_freq_table[i].freq == parent_rate) {
-                        phy->freq = &tegra_freq_table[i];
-                        break;
-                }
-        }
-        if (!phy->freq) {
-                pr_err("invalid pll_u parent rate %ld\n", parent_rate);
-                err = -EINVAL;
-                goto err1;
-        }
-        if (phy_is_ulpi(phy)) {
-                ulpi_config = config;
-                phy->clk = clk_get_sys(NULL, ulpi_config->clk);
-                if (IS_ERR(phy->clk)) {
-                        pr_err("%s: can't get ulpi clock\n", __func__);
-                        err = -ENXIO;
-                        goto err1;
-                }
-                if (!gpio_is_valid(ulpi_config->reset_gpio))
-                        ulpi_config->reset_gpio =
-                                of_get_named_gpio(dev->of_node,
-                                                  "nvidia,phy-reset-gpio", 0);
-                if (!gpio_is_valid(ulpi_config->reset_gpio)) {
-                        pr_err("%s: invalid reset gpio: %d\n", __func__,
-                               ulpi_config->reset_gpio);
-                        err = -EINVAL;
-                        goto err1;
-                }
-                gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
-                gpio_direction_output(ulpi_config->reset_gpio, 0);
-                phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
-                phy->ulpi->io_priv = regs + ULPI_VIEWPORT;
-        } else {
-                err = utmip_pad_open(phy);
-                if (err < 0)
-                        goto err1;
-        }
-        return phy;
-err1:
-        clk_disable_unprepare(phy->pll_u);
-        clk_put(phy->pll_u);
-err0:
-        kfree(phy);
-        return ERR_PTR(err);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_open);
-int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
-{
-        if (phy_is_ulpi(phy))
-                return ulpi_phy_power_on(phy);
-        else
-                return utmi_phy_power_on(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_power_on);
-void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
-{
-        if (phy_is_ulpi(phy))
-                ulpi_phy_power_off(phy);
-        else
-                utmi_phy_power_off(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_power_off);
-void tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
-{
-        if (!phy_is_ulpi(phy))
-                utmi_phy_preresume(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
-void tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
-{
-        if (!phy_is_ulpi(phy))
-                utmi_phy_postresume(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
-void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
-                                 enum tegra_usb_phy_port_speed port_speed)
-{
-        if (!phy_is_ulpi(phy))
-                utmi_phy_restore_start(phy, port_speed);
-}
-EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
-void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
-{
-        if (!phy_is_ulpi(phy))
-                utmi_phy_restore_end(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
-void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
-{
-        if (!phy_is_ulpi(phy))
-                utmi_phy_clk_disable(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_disable);
-void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
-{
-        if (!phy_is_ulpi(phy))
-                utmi_phy_clk_enable(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_enable);
-void tegra_usb_phy_close(struct tegra_usb_phy *phy)
-{
-        if (phy_is_ulpi(phy))
-                clk_put(phy->clk);
-        else
-                utmip_pad_close(phy);
-        clk_disable_unprepare(phy->pll_u);
-        clk_put(phy->pll_u);
-        kfree(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_close);
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 54d8f34fdee5..f7e12ede008c 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,6 +1,6 @@
 if ARCH_U300
-menu "ST-Ericsson AB U300/U330/U335/U365 Platform"
+menu "ST-Ericsson AB U300/U335 Platform"
 comment "ST-Ericsson Mobile Platform Products"
@@ -10,46 +10,7 @@ config MACH_U300
        select PINCTRL_U300
        select PINCTRL_COH901
-comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
+comment "ST-Ericsson U300/U335 Feature Selections"
-choice
-        prompt "U300/U330/U335/U365 system type"
-        default MACH_U300_BS2X
-        ---help---
-        You need to select the target system, i.e. the
-        U300/U330/U335/U365 board that you want to compile your kernel
-        for.
-config MACH_U300_BS2X
-        bool "S26/S26/B25/B26 Test Products"
-        depends on MACH_U300
-        help
-                Select this if you're developing on the
-                S26/S25 test products. (Also works on
-                B26/B25 big boards.)
-config MACH_U300_BS330
-        bool "S330/B330 Test Products"
-        depends on MACH_U300
-        help
-                Select this if you're developing on the
-                S330/B330 test products.
-config MACH_U300_BS335
-        bool "S335/B335 Test Products"
-        depends on MACH_U300
-        help
-                Select this if you're developing on the
-                S335/B335 test products.
-config MACH_U300_BS365
-        bool "S365/B365 Test Products"
-        depends on MACH_U300
-        help
-                Select this if you're developing on the
-                S365/B365 test products.
-endchoice
 config U300_DEBUG
        bool "Debug support for U300"
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 7e47d37aeb0e..5a86c58da396 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -7,7 +7,6 @@ obj-m		:=
 obj-n           :=
 obj-            :=
-obj-$(CONFIG_ARCH_U300)           += u300.o
 obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
 obj-$(CONFIG_I2C_STU300)          += i2c.o
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 03acf1883ec7..b8efac4daed8 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
 * arch/arm/mach-u300/core.c
 *
 *
- * Copyright (C) 2007-2010 ST-Ericsson SA
+ * Copyright (C) 2007-2012 ST-Ericsson SA
 * License terms: GNU General Public License (GPL) version 2
 * Core platform support, IRQ handling and device definitions.
 * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -31,23 +31,26 @@
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_data/clk-u300.h>
+#include <linux/platform_data/pinctrl-coh901.h>
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/map.h>
-#include <asm/mach/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
 #include <mach/coh901318.h>
 #include <mach/hardware.h>
 #include <mach/syscon.h>
-#include <mach/dma_channels.h>
+#include <mach/irqs.h>
-#include <mach/gpio-u300.h>
+#include "timer.h"
 #include "spi.h"
 #include "i2c.h"
 #include "u300-gpio.h"
+#include "dma_channels.h"
 /*
 * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -76,7 +79,7 @@ static struct map_desc u300_io_desc[] __initdata = {
        },
 };
-void __init u300_map_io(void)
+static void __init u300_map_io(void)
 {
        iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
        /* We enable a real big DMA buffer if need be. */
@@ -101,7 +104,6 @@ static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
        { IRQ_U300_UART0 }, &uart0_plat_data);
 /* The U335 have an additional UART1 on the APP CPU */
-#ifdef CONFIG_MACH_U300_BS335
 static struct amba_pl011_data uart1_plat_data = {
 #ifdef CONFIG_COH901318
        .dma_filter = coh901318_filter_id,
@@ -113,7 +115,6 @@ static struct amba_pl011_data uart1_plat_data = {
 /* Fast device at 0x7000 offset */
 static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
        { IRQ_U300_UART1 }, &uart1_plat_data);
-#endif
 /* AHB device at 0x4000 offset */
 static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
@@ -152,9 +153,7 @@ static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
 */
 static struct amba_device *amba_devs[] __initdata = {
        &uart0_device,
-#ifdef CONFIG_MACH_U300_BS335
        &uart1_device,
-#endif
        &pl022_device,
        &pl172_device,
        &mmcsd_device,
@@ -188,7 +187,6 @@ static struct resource gpio_resources[] = {
                .end   = IRQ_U300_GPIO_PORT2,
                .flags = IORESOURCE_IRQ,
        },
-#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
        {
                .name  = "gpio3",
                .start = IRQ_U300_GPIO_PORT3,
@@ -201,8 +199,6 @@ static struct resource gpio_resources[] = {
                .end   = IRQ_U300_GPIO_PORT4,
                .flags = IORESOURCE_IRQ,
        },
-#endif
-#ifdef CONFIG_MACH_U300_BS335
        {
                .name  = "gpio5",
                .start = IRQ_U300_GPIO_PORT5,
@@ -215,7 +211,6 @@ static struct resource gpio_resources[] = {
                .end   = IRQ_U300_GPIO_PORT6,
                .flags = IORESOURCE_IRQ,
        },
-#endif /* CONFIG_MACH_U300_BS335 */
 };
 static struct resource keypad_resources[] = {
@@ -323,7 +318,6 @@ static struct resource dma_resource[] = {
        }
 };
-#ifdef CONFIG_MACH_U300_BS335
 /* points out all dma slave channels.
 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 * Select all channels from A to B, end of list is marked with -1,-1
@@ -336,14 +330,6 @@ static int dma_slave_channels[] = {
 static int dma_memcpy_channels[] = {
        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
-#else /* CONFIG_MACH_U300_BS335 */
-static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
-static int dma_memcpy_channels[] = {
-        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
-#endif
 /** register dma for memory access
 *
 * active  1 means dma intends to access memory
@@ -1395,7 +1381,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .param.ctrl_lli = flags_memcpy_lli,
                .param.ctrl_lli_last = flags_memcpy_lli_last,
        },
-#ifdef CONFIG_MACH_U300_BS335
        {
                .number = U300_DMA_UART1_TX,
                .name = "UART1 TX",
@@ -1406,28 +1391,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .name = "UART1 RX",
                .priority_high = 0,
        }
-#else
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_9,
-                .name = "GENERAL 09",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        },
-        {
-                .number = U300_DMA_GENERAL_PURPOSE_10,
-                .name = "GENERAL 10",
-                .priority_high = 0,
-                .param.config = flags_memcpy_config,
-                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-                .param.ctrl_lli = flags_memcpy_lli,
-                .param.ctrl_lli_last = flags_memcpy_lli_last,
-        }
-#endif
 };
@@ -1480,18 +1443,7 @@ static struct platform_device pinctrl_device = {
 * GPIO block, with different number of ports.
 */
 static struct u300_gpio_platform u300_gpio_plat = {
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-        .variant = U300_GPIO_COH901335,
-        .ports = 3,
-#endif
-#ifdef CONFIG_MACH_U300_BS335
-        .variant = U300_GPIO_COH901571_3_BS335,
        .ports = 7,
-#endif
-#ifdef CONFIG_MACH_U300_BS365
-        .variant = U300_GPIO_COH901571_3_BS365,
-        .ports = 5,
-#endif
        .gpio_base = 0,
        .gpio_irq_base = IRQ_U300_GPIO_BASE,
        .pinctrl_device = &pinctrl_device,
@@ -1605,9 +1557,6 @@ static struct u300_mux_hog u300_mux_hogs[] = {
                .dev = &uart0_device.dev,
        },
        {
-                .dev = &pl022_device.dev,
-        },
-        {
                .dev = &mmcsd_device.dev,
        },
 };
@@ -1651,7 +1600,7 @@ static struct platform_device *platform_devs[] __initdata = {
 * together so some interrupts are connected to the first one and some
 * to the second one.
 */
-void __init u300_init_irq(void)
+static void __init u300_init_irq(void)
 {
        u32 mask[2] = {0, 0};
        struct clk *clk;
@@ -1756,29 +1705,11 @@ static void __init u300_init_check_chip(void)
        printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
               "(chip ID 0x%04x)\n", chipname, val);
-#ifdef CONFIG_MACH_U300_BS330
-        if ((val & 0xFF00U) != 0xd800) {
-                printk(KERN_ERR "Platform configured for BS330 " \
-                       "with DB3200 but %s detected, expect problems!",
-                       chipname);
-        }
-#endif
-#ifdef CONFIG_MACH_U300_BS335
        if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
                printk(KERN_ERR "Platform configured for BS335 " \
                       " with DB3350 but %s detected, expect problems!",
                       chipname);
        }
-#endif
-#ifdef CONFIG_MACH_U300_BS365
-        if ((val & 0xFF00U) != 0xe800) {
-                printk(KERN_ERR "Platform configured for BS365 " \
-                       "with DB3210 but %s detected, expect problems!",
-                       chipname);
-        }
-#endif
 }
 /*
@@ -1811,7 +1742,7 @@ static void __init u300_assign_physmem(void)
        }
 }
-void __init u300_init_devices(void)
+static void __init u300_init_machine(void)
 {
        int i;
        u16 val;
@@ -1852,7 +1783,7 @@ void __init u300_init_devices(void)
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
-void u300_restart(char mode, const char *cmd)
+static void u300_restart(char mode, const char *cmd)
 {
        switch (mode) {
        case 's':
@@ -1868,3 +1799,15 @@ void u300_restart(char mode, const char *cmd)
        /* Wait for system do die/reset. */
        while (1);
 }
+MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
+        /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
+        .atag_offset    = 0x100,
+        .map_io         = u300_map_io,
+        .nr_irqs        = NR_IRQS_U300,
+        .init_irq       = u300_init_irq,
+        .handle_irq     = vic_handle_irq,
+        .timer          = &u300_timer,
+        .init_machine   = u300_init_machine,
+        .restart        = u300_restart,
+MACHINE_END
diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/dma_channels.h
index b239149ba0d0..4e8a88fbca49 100644
--- a/arch/arm/mach-u300/include/mach/dma_channels.h
+++ b/arch/arm/mach-u300/dma_channels.h
@@ -3,7 +3,7 @@
 * arch/arm/mach-u300/include/mach/dma_channels.h
 *
 *
- * Copyright (C) 2007-2009 ST-Ericsson
+ * Copyright (C) 2007-2012 ST-Ericsson
 * License terms: GNU General Public License (GPL) version 2
 * Map file for the U300 dma driver.
 * Author: Per Friden <per.friden@stericsson.com>
@@ -50,19 +50,10 @@
 #define U300_DMA_GENERAL_PURPOSE_6    35
 #define U300_DMA_GENERAL_PURPOSE_7    36
 #define U300_DMA_GENERAL_PURPOSE_8    37
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_DMA_UART1_TX             38
 #define U300_DMA_UART1_RX             39
-#else
-#define U300_DMA_GENERAL_PURPOSE_9    38
-#define U300_DMA_GENERAL_PURPOSE_10   39
-#endif
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_DMA_DEVICE_CHANNELS      32
-#else
-#define U300_DMA_DEVICE_CHANNELS      30
-#endif
 #define U300_DMA_CHANNELS             40
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index cb04bd6ab3e7..96800aa1316d 100644
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -1,7 +1,7 @@
 /*
 * arch/arm/mach-u300/i2c.c
 *
- * Copyright (C) 2009 ST-Ericsson AB
+ * Copyright (C) 2009-2012 ST-Ericsson AB
 * License terms: GNU General Public License (GPL) version 2
 *
 * Register board i2c devices
@@ -9,7 +9,7 @@
 */
 #include <linux/kernel.h>
 #include <linux/i2c.h>
-#include <linux/mfd/abx500.h>
+#include <linux/mfd/ab3100.h>
 #include <linux/regulator/machine.h>
 #include <linux/amba/bus.h>
 #include <mach/irqs.h>
@@ -261,7 +261,6 @@ static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
 };
 static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
-#ifdef CONFIG_MACH_U300_BS335
        {
                .type = "fwcam",
                .addr = 0x10,
@@ -270,9 +269,6 @@ static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
                .type = "fwcam",
                .addr = 0x5d,
        },
-#else
-        { },
-#endif
 };
 void __init u300_i2c_register_board_devices(void)
diff --git a/arch/arm/mach-u300/include/mach/clkdev.h b/arch/arm/mach-u300/include/mach/clkdev.h
deleted file mode 100644
index 92e3cc872c66..000000000000
--- a/arch/arm/mach-u300/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-int __clk_get(struct clk *clk);
-void __clk_put(struct clk *clk);
-#endif
diff --git a/arch/arm/mach-u300/include/mach/gpio-u300.h b/arch/arm/mach-u300/include/mach/gpio-u300.h
deleted file mode 100644
index e81400c1753a..000000000000
--- a/arch/arm/mach-u300/include/mach/gpio-u300.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2007-2011 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * GPIO block resgister definitions and inline macros for
- * U300 GPIO COH 901 335 or COH 901 571/3
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#ifndef __MACH_U300_GPIO_U300_H
-#define __MACH_U300_GPIO_U300_H
-/**
- * enum u300_gpio_variant - the type of U300 GPIO employed
- */
-enum u300_gpio_variant {
-        U300_GPIO_COH901335,
-        U300_GPIO_COH901571_3_BS335,
-        U300_GPIO_COH901571_3_BS365,
-};
-/**
- * struct u300_gpio_platform - U300 GPIO platform data
- * @variant: IP block variant
- * @ports: number of GPIO block ports
- * @gpio_base: first GPIO number for this block (use a free range)
- * @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
- * @pinctrl_device: pin control device to spawn as child
- */
-struct u300_gpio_platform {
-        enum u300_gpio_variant variant;
-        u8 ports;
-        int gpio_base;
-        int gpio_irq_base;
-        struct platform_device *pinctrl_device;
-};
-#endif /* __MACH_U300_GPIO_U300_H */
diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-u300/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index ec09c1e07b1a..e27425a63fa1 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -3,7 +3,7 @@
 * arch/arm/mach-u300/include/mach/irqs.h
 *
 *
- * Copyright (C) 2006-2009 ST-Ericsson AB
+ * Copyright (C) 2006-2012 ST-Ericsson AB
 * License terms: GNU General Public License (GPL) version 2
 * IRQ channel definitions for the U300 platforms.
 * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -31,10 +31,6 @@
 #define IRQ_U300_XGAM_GAMCON            14
 #define IRQ_U300_XGAM_CDI               15
 #define IRQ_U300_XGAM_CDICON            16
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-/* MMIACC not used on the DB3210 or DB3350 chips */
-#define IRQ_U300_XGAM_MMIACC            17
-#endif
 #define IRQ_U300_XGAM_PDI               18
 #define IRQ_U300_XGAM_PDICON            19
 #define IRQ_U300_XGAM_GAMEACC           20
@@ -55,8 +51,6 @@
 #define IRQ_U300_GPIO_PORT1             34
 #define IRQ_U300_GPIO_PORT2             35
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
-    defined(CONFIG_MACH_U300_BS335)
 /* These are for DB3150, DB3200 and DB3350 */
 #define IRQ_U300_WDOG                   36
 #define IRQ_U300_EVHIST                 37
@@ -68,15 +62,8 @@
 #define IRQ_U300_RTC                    43
 #define IRQ_U300_NFIF                   44
 #define IRQ_U300_NFIF2                  45
-#endif
-/* DB3150 and DB3200 have only 45 IRQs */
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-#define U300_VIC_IRQS_END               46
-#endif
 /* The DB3350-specific interrupt lines */
-#ifdef CONFIG_MACH_U300_BS335
 #define IRQ_U300_ISP_F0                 46
 #define IRQ_U300_ISP_F1                 47
 #define IRQ_U300_ISP_F2                 48
@@ -89,25 +76,6 @@
 #define IRQ_U300_GPIO_PORT5             55
 #define IRQ_U300_GPIO_PORT6             56
 #define U300_VIC_IRQS_END               57
-#endif
-/* The DB3210-specific interrupt lines */
-#ifdef CONFIG_MACH_U300_BS365
-#define IRQ_U300_GPIO_PORT3             36
-#define IRQ_U300_GPIO_PORT4             37
-#define IRQ_U300_WDOG                   38
-#define IRQ_U300_EVHIST                 39
-#define IRQ_U300_MSPRO                  40
-#define IRQ_U300_MMCSD_MCIINTR0         41
-#define IRQ_U300_MMCSD_MCIINTR1         42
-#define IRQ_U300_I2C0                   43
-#define IRQ_U300_I2C1                   44
-#define IRQ_U300_RTC                    45
-#define IRQ_U300_NFIF                   46
-#define IRQ_U300_NFIF2                  47
-#define IRQ_U300_SYSCON_PLL_LOCK        48
-#define U300_VIC_IRQS_END               49
-#endif
 /* Maximum 8*7 GPIO lines */
 #ifdef CONFIG_PINCTRL_COH901
@@ -117,6 +85,6 @@
 #define IRQ_U300_GPIO_END               (U300_VIC_IRQS_END)
 #endif
-#define NR_IRQS                         (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
+#define NR_IRQS_U300                    (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
 #endif
diff --git a/arch/arm/mach-u300/include/mach/platform.h b/arch/arm/mach-u300/include/mach/platform.h
deleted file mode 100644
index 096333f32fc3..000000000000
--- a/arch/arm/mach-u300/include/mach/platform.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/platform.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Basic platform init and mapping functions.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#ifndef __ASSEMBLY__
-void u300_map_io(void);
-void u300_init_irq(void);
-void u300_init_devices(void);
-void u300_restart(char, const char *);
-extern struct sys_timer u300_timer;
-#endif
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
index 6e84f07a7c6f..10bdd0be9774 100644
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ b/arch/arm/mach-u300/include/mach/syscon.h
@@ -3,7 +3,7 @@
 * arch/arm/mach-u300/include/mach/syscon.h
 *
 *
- * Copyright (C) 2008 ST-Ericsson AB
+ * Copyright (C) 2008-2012 ST-Ericsson AB
 *
 * Author: Rickard Andersson <rickard.andersson@stericsson.com>
 */
@@ -36,9 +36,7 @@
 #define U300_SYSCON_CSR_PLL13_LOCK_IND                          (0x0001)
 /* Reset lines for SLOW devices 16bit (R/W) */
 #define U300_SYSCON_RSR                                         (0x0014)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RSR_PPM_RESET_EN                            (0x0200)
-#endif
 #define U300_SYSCON_RSR_ACC_TMR_RESET_EN                        (0x0100)
 #define U300_SYSCON_RSR_APP_TMR_RESET_EN                        (0x0080)
 #define U300_SYSCON_RSR_RTC_RESET_EN                            (0x0040)
@@ -50,9 +48,7 @@
 #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN                    (0x0001)
 /* Reset lines for FAST devices 16bit (R/W) */
 #define U300_SYSCON_RFR                                         (0x0018)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RFR_UART1_RESET_ENABLE                      (0x0080)
-#endif
 #define U300_SYSCON_RFR_SPI_RESET_ENABLE                        (0x0040)
 #define U300_SYSCON_RFR_MMC_RESET_ENABLE                        (0x0020)
 #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE                   (0x0010)
@@ -62,10 +58,8 @@
 #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE                (0x0001)
 /* Reset lines for the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_RRR                                         (0x001c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RRR_CDS_RESET_EN                            (0x4000)
 #define U300_SYSCON_RRR_ISP_RESET_EN                            (0x2000)
-#endif
 #define U300_SYSCON_RRR_INTCON_RESET_EN                         (0x1000)
 #define U300_SYSCON_RRR_MSPRO_RESET_EN                          (0x0800)
 #define U300_SYSCON_RRR_XGAM_RESET_EN                           (0x0100)
@@ -79,9 +73,7 @@
 #define U300_SYSCON_RRR_AAIF_RESET_EN                           (0x0001)
 /* Clock enable for SLOW peripherals 16bit (R/W) */
 #define U300_SYSCON_CESR                                        (0x0020)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CESR_PPM_CLK_EN                             (0x0200)
-#endif
 #define U300_SYSCON_CESR_ACC_TMR_CLK_EN                         (0x0100)
 #define U300_SYSCON_CESR_APP_TMR_CLK_EN                         (0x0080)
 #define U300_SYSCON_CESR_KEYPAD_CLK_EN                          (0x0040)
@@ -92,24 +84,20 @@
 #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN                     (0x0001)
 /* Clock enable for FAST peripherals 16bit (R/W) */
 #define U300_SYSCON_CEFR                                        (0x0024)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CEFR_UART1_CLK_EN                           (0x0200)
-#endif
 #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN                       (0x0100)
 #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN                       (0x0080)
 #define U300_SYSCON_CEFR_SPI_CLK_EN                             (0x0040)
 #define U300_SYSCON_CEFR_MMC_CLK_EN                             (0x0020)
-#define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
-#define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
-#define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
-#define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
 #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN                     (0x0001)
 /* Clock enable for the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_CERR                                        (0x0028)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CERR_CDS_CLK_EN                             (0x2000)
 #define U300_SYSCON_CERR_ISP_CLK_EN                             (0x1000)
-#endif
 #define U300_SYSCON_CERR_MSPRO_CLK_EN                           (0x0800)
 #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN               (0x0400)
 #define U300_SYSCON_CERR_SEMI_CLK_EN                            (0x0200)
@@ -124,9 +112,7 @@
 #define U300_SYSCON_CERR_AAIF_CLK_EN                            (0x0001)
 /* Single block clock enable 16bit (-/W) */
 #define U300_SYSCON_SBCER                                       (0x002c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_PPM_CLK_EN                            (0x0009)
-#endif
 #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN                        (0x0008)
 #define U300_SYSCON_SBCER_APP_TMR_CLK_EN                        (0x0007)
 #define U300_SYSCON_SBCER_KEYPAD_CLK_EN                         (0x0006)
@@ -135,9 +121,7 @@
 #define U300_SYSCON_SBCER_BTR_CLK_EN                            (0x0002)
 #define U300_SYSCON_SBCER_UART_CLK_EN                           (0x0001)
 #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN                    (0x0000)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_UART1_CLK_EN                          (0x0019)
-#endif
 #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN                      (0x0018)
 #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN                      (0x0017)
 #define U300_SYSCON_SBCER_SPI_CLK_EN                            (0x0016)
@@ -147,10 +131,8 @@
 #define U300_SYSCON_SBCER_I2C1_CLK_EN                           (0x0012)
 #define U300_SYSCON_SBCER_I2C0_CLK_EN                           (0x0011)
 #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN                    (0x0010)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_CDS_CLK_EN                            (0x002D)
 #define U300_SYSCON_SBCER_ISP_CLK_EN                            (0x002C)
-#endif
 #define U300_SYSCON_SBCER_MSPRO_CLK_EN                          (0x002B)
 #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN              (0x002A)
 #define U300_SYSCON_SBCER_SEMI_CLK_EN                           (0x0029)
@@ -168,9 +150,7 @@
 /* Same values as above for SBCER */
 /* Clock force SLOW peripherals 16bit (R/W) */
 #define U300_SYSCON_CFSR                                        (0x003c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN                       (0x0200)
-#endif
 #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN                   (0x0100)
 #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN                   (0x0080)
 #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN                    (0x0020)
@@ -184,10 +164,8 @@
 /* Values not defined. Define if you want to use them. */
 /* Clock force the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_CFRR                                        (0x44)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN                       (0x2000)
 #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN                       (0x1000)
-#endif
 #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN                     (0x0800)
 #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN         (0x0400)
 #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN                      (0x0200)
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
index 65f87c523892..1e49d901f2c9 100644
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -28,7 +28,6 @@
 #define PLAT_NAND_CLE                   (1 << 16)
 #define PLAT_NAND_ALE                   (1 << 17)
 /* AHB Peripherals */
 #define U300_AHB_PER_PHYS_BASE          0xa0000000
 #define U300_AHB_PER_VIRT_BASE          0xff010000
@@ -46,11 +45,7 @@
 #define U300_BOOTROM_VIRT_BASE          0xffff0000
 /* SEMI config base */
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SEMI_CONFIG_BASE           0x2FFE0000
-#else
-#define U300_SEMI_CONFIG_BASE           0x30000000
-#endif
 /*
 * AHB peripherals
@@ -99,10 +94,8 @@
 /* SPI controller */
 #define U300_SPI_BASE                   (U300_FAST_PER_PHYS_BASE+0x6000)
-#ifdef CONFIG_MACH_U300_BS335
 /* Fast UART1 on U335 only */
 #define U300_UART1_BASE                 (U300_SLOW_PER_PHYS_BASE+0x7000)
-#endif
 /*
 * SLOW peripherals
@@ -151,10 +144,8 @@
 * REST peripherals
 */
-/* ISP (image signal processor) is only available in U335 */
+/* ISP (image signal processor) */
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_ISP_BASE                   (0xA0008000)
-#endif
 /* DMA Controller base */
 #define U300_DMAC_BASE                  (0xC0020000)
@@ -166,17 +157,9 @@
 #define U300_APEX_BASE                  (0xc0030000)
 /* Video Encoder Base */
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_VIDEOENC_BASE              (0xc0080000)
-#else
-#define U300_VIDEOENC_BASE              (0xc0040000)
-#endif
 /* XGAM Base */
 #define U300_XGAM_BASE                  (0xd0000000)
-/*
- * Virtual accessor macros for static devices
- */
 #endif
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index a1affacfa59c..02e6659286d5 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -12,7 +12,7 @@
 #include <linux/amba/pl022.h>
 #include <linux/err.h>
 #include <mach/coh901318.h>
-#include <mach/dma_channels.h>
+#include "dma_channels.h"
 /*
 * The following is for the actual devices on the SSP/SPI bus
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 56ac06d38ec1..1da10e20e996 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -17,14 +17,17 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/irq.h>
 #include <mach/hardware.h>
+#include <mach/irqs.h>
 /* Generic stuff */
 #include <asm/sched_clock.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/mach/irq.h>
+#include "timer.h"
 /*
 * APP side special timer registers
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
new file mode 100644
index 000000000000..b5e9791762e0
--- /dev/null
+++ b/arch/arm/mach-u300/timer.h
@@ -0,0 +1 @@
+extern struct sys_timer u300_timer;
diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h
index 847dc25300c6..83f50772e169 100644
--- a/arch/arm/mach-u300/u300-gpio.h
+++ b/arch/arm/mach-u300/u300-gpio.h
@@ -1,50 +1,11 @@
 /*
- * Individual pin assignments for the B26/S26. Notice that the
+ * Individual pin assignments for the B335/S335.
- * actual usage of these pins depends on the PAD MUX settings, that
- * is why the same number can potentially appear several times.
- * In the reference design each pin is only used for one purpose.
- * These were determined by inspecting the B26/S26 schematic:
- * 2/1911-ROA 128 1603
- */
-#ifdef CONFIG_MACH_U300_BS2X
-#define U300_GPIO_PIN_UART_RX           0
-#define U300_GPIO_PIN_UART_TX           1
-#define U300_GPIO_PIN_GPIO02            2  /* Unrouted */
-#define U300_GPIO_PIN_GPIO03            3  /* Unrouted */
-#define U300_GPIO_PIN_CAM_SLEEP         4
-#define U300_GPIO_PIN_CAM_REG_EN        5
-#define U300_GPIO_PIN_GPIO06            6  /* Unrouted */
-#define U300_GPIO_PIN_GPIO07            7  /* Unrouted */
-#define U300_GPIO_PIN_GPIO08            8  /* Service point SP2321 */
-#define U300_GPIO_PIN_GPIO09            9  /* Service point SP2322 */
-#define U300_GPIO_PIN_PHFSENSE          10 /* Headphone jack sensing */
-#define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
-#define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
-#define U300_GPIO_PIN_FLIPSENSE         13 /* Mechanical flip sensing */
-#define U300_GPIO_PIN_GPIO14            14 /* DSP JTAG Port RTCK */
-#define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
-#define U300_GPIO_PIN_GPIO16            16 /* Unrouted */
-#define U300_GPIO_PIN_GPIO17            17 /* Unrouted */
-#define U300_GPIO_PIN_GPIO18            18 /* Unrouted */
-#define U300_GPIO_PIN_GPIO19            19 /* Unrouted */
-#define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
-#define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
-#define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
-#define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
-#endif
-/*
- * Individual pin assignments for the B330/S330 and B365/S365.
 * Notice that the actual usage of these pins depends on the
 * PAD MUX settings, that is why the same number can potentially
 * appear several times. In the reference design each pin is only
 * used for one purpose. These were determined by inspecting the
 * S365 schematic.
 */
-#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
-    defined(CONFIG_MACH_U300_BS335)
 #define U300_GPIO_PIN_UART_RX           0
 #define U300_GPIO_PIN_UART_TX           1
 #define U300_GPIO_PIN_UART_CTS          2
@@ -90,8 +51,6 @@
 #define U300_GPIO_PIN_GPIO38            38 /* Unrouted */
 #define U300_GPIO_PIN_GPIO39            39 /* Unrouted */
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_GPIO_PIN_GPIO40            40 /* Unrouted */
 #define U300_GPIO_PIN_GPIO41            41 /* Unrouted */
 #define U300_GPIO_PIN_GPIO42            42 /* Unrouted */
@@ -109,6 +68,3 @@
 #define U300_GPIO_PIN_GPIO53            53 /* Unrouted */
 #define U300_GPIO_PIN_GPIO54            54 /* Unrouted */
 #define U300_GPIO_PIN_GPIO55            55 /* Unrouted */
-#endif
-#endif
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
deleted file mode 100644
index f30c69d91d99..000000000000
--- a/arch/arm/mach-u300/u300.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/u300.c
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Platform machine definition.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/memblock.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <asm/hardware/vic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/memory.h>
-static void __init u300_init_machine(void)
-{
-        u300_init_devices();
-}
-#ifdef CONFIG_MACH_U300_BS2X
-#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board"
-#endif
-#ifdef CONFIG_MACH_U300_BS330
-#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board"
-#endif
-#ifdef CONFIG_MACH_U300_BS335
-#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board"
-#endif
-#ifdef CONFIG_MACH_U300_BS365
-#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board"
-#endif
-MACHINE_START(U300, MACH_U300_STRING)
-        /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
-        .atag_offset    = 0x100,
-        .map_io         = u300_map_io,
-        .init_irq       = u300_init_irq,
-        .handle_irq     = vic_handle_irq,
-        .timer          = &u300_timer,
-        .init_machine   = u300_init_machine,
-        .restart        = u300_restart,
-MACHINE_END
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 53d3d46dec12..5848206ee9b9 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -5,12 +5,13 @@ config UX500_SOC_COMMON
        default y
        select ARM_GIC
        select HAS_MTU
-        select PL310_ERRATA_753970
+        select PL310_ERRATA_753970 if CACHE_PL310
        select ARM_ERRATA_754322
-        select ARM_ERRATA_764369
+        select ARM_ERRATA_764369 if SMP
        select CACHE_L2X0
        select PINCTRL
        select PINCTRL_NOMADIK
+        select COMMON_CLK
 config UX500_SOC_DB8500
        bool
@@ -28,6 +29,7 @@ config MACH_MOP500
        select I2C
        select I2C_NOMADIK
        select SOC_BUS
+        select REGULATOR_FIXED_VOLTAGE
        help
          Include support for the MOP500 development platform.
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 026086ff9e6c..f24710dfc395 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel, U8500 machine.
 #
-obj-y                           := clock.o cpu.o devices.o devices-common.o \
+obj-y                           := cpu.o devices.o devices-common.o \
                                   id.o usb.o timer.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
@@ -12,6 +12,6 @@ obj-$(CONFIG_MACH_MOP500)	+= board-mop500.o board-mop500-sdi.o \
                                board-mop500-uib.o board-mop500-stuib.o \
                                board-mop500-u8500uib.o \
                                board-mop500-pins.o \
-                                board-mop500-msp.o
+                                board-mop500-audio.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
diff --git a/arch/arm/mach-ux500/Makefile.boot b/arch/arm/mach-ux500/Makefile.boot
index dd5cd00e2554..760a0efe7580 100644
--- a/arch/arm/mach-ux500/Makefile.boot
+++ b/arch/arm/mach-ux500/Makefile.boot
@@ -1,5 +1,3 @@
   zreladdr-y   += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
-dtb-$(CONFIG_MACH_SNOWBALL) += snowball.dtb
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-audio.c
index df15646036aa..070629a95625 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -7,7 +7,6 @@
 #include <linux/platform_device.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
-#include <linux/pinctrl/consumer.h>
 #include <plat/gpio-nomadik.h>
 #include <plat/pincfg.h>
@@ -23,53 +22,6 @@
 #include "devices-db8500.h"
 #include "pins-db8500.h"
-/* MSP1/3 Tx/Rx usage protection */
-static DEFINE_SPINLOCK(msp_rxtx_lock);
-/* Reference Count */
-static int msp_rxtx_ref;
-/* Pin modes */
-struct pinctrl *msp1_p;
-struct pinctrl_state *msp1_def;
-struct pinctrl_state *msp1_sleep;
-int msp13_i2s_init(void)
-{
-        int retval = 0;
-        unsigned long flags;
-        spin_lock_irqsave(&msp_rxtx_lock, flags);
-        if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) {
-                retval = pinctrl_select_state(msp1_p, msp1_def);
-                if (retval)
-                        pr_err("could not set MSP1 defstate\n");
-        }
-        if (!retval)
-                msp_rxtx_ref++;
-        spin_unlock_irqrestore(&msp_rxtx_lock, flags);
-        return retval;
-}
-int msp13_i2s_exit(void)
-{
-        int retval = 0;
-        unsigned long flags;
-        spin_lock_irqsave(&msp_rxtx_lock, flags);
-        WARN_ON(!msp_rxtx_ref);
-        msp_rxtx_ref--;
-        if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) {
-                retval = pinctrl_select_state(msp1_p, msp1_sleep);
-                if (retval)
-                        pr_err("could not set MSP1 sleepstate\n");
-        }
-        spin_unlock_irqrestore(&msp_rxtx_lock, flags);
-        return retval;
-}
 static struct stedma40_chan_cfg msp0_dma_rx = {
        .high_priority = true,
        .dir = STEDMA40_PERIPH_TO_MEM,
@@ -96,7 +48,7 @@ static struct stedma40_chan_cfg msp0_dma_tx = {
        /* data_width is set during configuration */
 };
-static struct msp_i2s_platform_data msp0_platform_data = {
+struct msp_i2s_platform_data msp0_platform_data = {
        .id = MSP_I2S_0,
        .msp_i2s_dma_rx = &msp0_dma_rx,
        .msp_i2s_dma_tx = &msp0_dma_tx,
@@ -128,12 +80,10 @@ static struct stedma40_chan_cfg msp1_dma_tx = {
        /* data_width is set during configuration */
 };
-static struct msp_i2s_platform_data msp1_platform_data = {
+struct msp_i2s_platform_data msp1_platform_data = {
        .id = MSP_I2S_1,
        .msp_i2s_dma_rx = NULL,
        .msp_i2s_dma_tx = &msp1_dma_tx,
-        .msp_i2s_init = msp13_i2s_init,
-        .msp_i2s_exit = msp13_i2s_exit,
 };
 static struct stedma40_chan_cfg msp2_dma_rx = {
@@ -193,11 +143,11 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent,
 /* Platform device for ASoC MOP500 machine */
 static struct platform_device snd_soc_mop500 = {
-                .name = "snd-soc-mop500",
+        .name = "snd-soc-mop500",
-                .id = 0,
+        .id = 0,
-                .dev = {
+        .dev = {
-                        .platform_data = NULL,
+                .platform_data = NULL,
-                },
+        },
 };
 /* Platform device for Ux500-PCM */
@@ -209,59 +159,37 @@ static struct platform_device ux500_pcm = {
                },
 };
-static struct msp_i2s_platform_data msp2_platform_data = {
+struct msp_i2s_platform_data msp2_platform_data = {
        .id = MSP_I2S_2,
        .msp_i2s_dma_rx = &msp2_dma_rx,
        .msp_i2s_dma_tx = &msp2_dma_tx,
 };
-static struct msp_i2s_platform_data msp3_platform_data = {
+struct msp_i2s_platform_data msp3_platform_data = {
        .id             = MSP_I2S_3,
        .msp_i2s_dma_rx = &msp1_dma_rx,
        .msp_i2s_dma_tx = NULL,
-        .msp_i2s_init = msp13_i2s_init,
-        .msp_i2s_exit = msp13_i2s_exit,
 };
-int mop500_msp_init(struct device *parent)
+void mop500_audio_init(struct device *parent)
 {
-        struct platform_device *msp1;
        pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
        platform_device_register(&snd_soc_mop500);
        pr_info("Initialize MSP I2S-devices.\n");
        db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
                           &msp0_platform_data);
-        msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
+        db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
                           &msp1_platform_data);
        db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
                           &msp2_platform_data);
        db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
                           &msp3_platform_data);
+}
-        /* Get the pinctrl handle for MSP1 */
+/* Due for removal once the MSP driver has been fully DT:ed. */
-        if (msp1) {
+void mop500_of_audio_init(struct device *parent)
-                msp1_p = pinctrl_get(&msp1->dev);
+{
-                if (IS_ERR(msp1_p))
-                        dev_err(&msp1->dev, "could not get MSP1 pinctrl\n");
-                else {
-                        msp1_def = pinctrl_lookup_state(msp1_p,
-                                                        PINCTRL_STATE_DEFAULT);
-                        if (IS_ERR(msp1_def)) {
-                                dev_err(&msp1->dev,
-                                        "could not get MSP1 defstate\n");
-                        }
-                        msp1_sleep = pinctrl_lookup_state(msp1_p,
-                                                          PINCTRL_STATE_SLEEP);
-                        if (IS_ERR(msp1_sleep))
-                                dev_err(&msp1->dev,
-                                        "could not get MSP1 idlestate\n");
-                }
-        }
        pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
        platform_device_register(&ux500_pcm);
-        return 0;
 }
diff --git a/arch/arm/mach-ux500/board-mop500-msp.h b/arch/arm/mach-ux500/board-mop500-msp.h
deleted file mode 100644
index 6fcfb5e2cc94..000000000000
--- a/arch/arm/mach-ux500/board-mop500-msp.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2012
- *
- * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
- *         for ST-Ericsson.
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-void mop500_msp_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 32fd99204464..a267c6d30e37 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -30,16 +30,15 @@ static enum custom_pin_cfg_t pinsfor;
 #define BIAS(a,b) static unsigned long a[] = { b }
 BIAS(pd, PIN_PULL_DOWN);
-BIAS(slpm_gpio_nopull, PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
 BIAS(in_nopull, PIN_INPUT_NOPULL);
-BIAS(in_nopull_sleep_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
+BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
 BIAS(in_pu, PIN_INPUT_PULLUP);
 BIAS(in_pd, PIN_INPUT_PULLDOWN);
 BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP);
 BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW);
 BIAS(out_hi, PIN_OUTPUT_HIGH);
 BIAS(out_lo, PIN_OUTPUT_LOW);
-BIAS(out_lo_sleep_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
+BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
 /* These also force them into GPIO mode */
 BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
 BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
@@ -48,23 +47,32 @@ BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SL
 BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
 BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
 /* Sleep modes */
-BIAS(sleep_in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(sleep_in_nopull_wkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE);
+BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
-BIAS(sleep_out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(sleep_out_lo_wkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
+BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(sleep_out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
+BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
 /* We use these to define hog settings that are always done on boot */
 #define DB8500_MUX_HOG(group,func) \
        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
 #define DB8500_PIN_HOG(pin,conf) \
        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
+#define DB8500_PIN_SLEEP(pin, conf, dev) \
+        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
+                            pin, conf)
 /* These are default states associated with device and changed runtime */
 #define DB8500_MUX(group,func,dev) \
        PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
 #define DB8500_PIN(pin,conf,dev) \
        PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
+#define DB8500_PIN_SLEEP(pin, conf, dev) \
+        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
+                            pin, conf)
 #define DB8500_PIN_SLEEP(pin,conf,dev) \
        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
@@ -134,40 +142,47 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
        DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
        DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
        /* UART0 sleep state */
-        DB8500_PIN_SLEEP("GPIO0_AJ5", sleep_in_wkup_pdis, "uart0"),
+        DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
-        DB8500_PIN_SLEEP("GPIO1_AJ3", sleep_out_hi_wkup_pdis, "uart0"),
+        DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
-        DB8500_PIN_SLEEP("GPIO2_AH4", sleep_in_wkup_pdis, "uart0"),
+        DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
-        DB8500_PIN_SLEEP("GPIO3_AH3", sleep_out_wkup_pdis, "uart0"),
+        DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
        /* MSP1 for ALSA codec */
        DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
        DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO33_AF2", out_lo_sleep_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN("GPIO33_AF2", out_lo_slpm_nowkup, "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO34_AE1", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN("GPIO34_AE1", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO35_AE2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN("GPIO35_AE2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO36_AG2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN("GPIO36_AG2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
        /* MSP1 sleep state */
-        DB8500_PIN_SLEEP("GPIO33_AF2", sleep_out_lo_wkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_SLEEP("GPIO33_AF2", slpm_out_lo_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO34_AE1", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_SLEEP("GPIO34_AE1", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO35_AE2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_SLEEP("GPIO35_AE2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO36_AG2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_SLEEP("GPIO36_AG2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
        /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
        DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
        DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
        /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
        DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"),
-        /* Mux in I2C blocks, put pins into GPIO in sleepmode no pull-up */
+        /* Mux in i2c0 block, default state */
        DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
-        DB8500_PIN("GPIO147_C15", slpm_gpio_nopull, "nmk-i2c.0"),
+        /* i2c0 sleep state */
-        DB8500_PIN("GPIO148_B16", slpm_gpio_nopull, "nmk-i2c.0"),
+        DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
+        DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
+        /* Mux in i2c1 block, default state  */
        DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
-        DB8500_PIN("GPIO16_AD3", slpm_gpio_nopull, "nmk-i2c.1"),
+        /* i2c1 sleep state */
-        DB8500_PIN("GPIO17_AD4", slpm_gpio_nopull, "nmk-i2c.1"),
+        DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
+        DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
+        /* Mux in i2c2 block, default state  */
        DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
-        DB8500_PIN("GPIO10_AF5", slpm_gpio_nopull, "nmk-i2c.2"),
+        /* i2c2 sleep state */
-        DB8500_PIN("GPIO11_AG4", slpm_gpio_nopull, "nmk-i2c.2"),
+        DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
+        DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
+        /* Mux in i2c3 block, default state  */
        DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
-        DB8500_PIN("GPIO229_AG7", slpm_gpio_nopull, "nmk-i2c.3"),
+        /* i2c3 sleep state */
-        DB8500_PIN("GPIO230_AF7", slpm_gpio_nopull, "nmk-i2c.3"),
+        DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
+        DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
        /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
        DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
        DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
@@ -219,11 +234,15 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
        DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
        DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
        /* Mux in SPI2 pins on the "other C1" altfunction */
-        DB8500_MUX("spi2_oc1_1", "spi2", "spi2"),
+        DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
        DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
        DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
        DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
        DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
+        /* SPI2 sleep state */
+        DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
+        DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
+        DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
 };
 /*
@@ -410,7 +429,7 @@ static struct pinctrl_map __initdata u9500_pinmap[] = {
        DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
        /* HSI */
        DB8500_MUX_HOG("hsir_a_1", "hsi"),
-        DB8500_MUX_HOG("hsit_a_1", "hsi"),
+        DB8500_MUX_HOG("hsit_a_2", "hsi"),
        DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
        DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
        DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
@@ -418,7 +437,7 @@ static struct pinctrl_map __initdata u9500_pinmap[] = {
        DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
        DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
        DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
-        DB8500_PIN_HOG("GPIO226_AF8", out_hi), /* ACWAKE0 */
+        DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
 };
 static struct pinctrl_map __initdata u8500_pinmap[] = {
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 52426a425787..2a17bc506cff 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -13,6 +13,21 @@
 #include <linux/regulator/ab8500.h>
 #include "board-mop500-regulators.h"
+static struct regulator_consumer_supply gpio_en_3v3_consumers[] = {
+       REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
+};
+struct regulator_init_data gpio_en_3v3_regulator = {
+       .constraints = {
+               .name = "EN-3V3",
+               .min_uV = 3300000,
+               .max_uV = 3300000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+       },
+       .num_consumer_supplies = ARRAY_SIZE(gpio_en_3v3_consumers),
+       .consumer_supplies = gpio_en_3v3_consumers,
+};
 /*
 * TPS61052 regulator
 */
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
index 94992158d962..78a0642a2206 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.h
+++ b/arch/arm/mach-ux500/board-mop500-regulators.h
@@ -18,5 +18,6 @@ extern struct ab8500_regulator_reg_init
 ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS];
 extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS];
 extern struct regulator_init_data tps61052_regulator;
+extern struct regulator_init_data gpio_en_3v3_regulator;
 #endif
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 18ff781cfbe4..9c8e4a9e83ee 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -152,7 +152,7 @@ static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
 };
 #endif
-static struct mmci_platform_data mop500_sdi1_data = {
+struct mmci_platform_data mop500_sdi1_data = {
        .ocr_mask       = MMC_VDD_29_30,
        .f_max          = 50000000,
        .capabilities   = MMC_CAP_4_BIT_DATA,
@@ -189,7 +189,7 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
 };
 #endif
-static struct mmci_platform_data mop500_sdi2_data = {
+struct mmci_platform_data mop500_sdi2_data = {
        .ocr_mask       = MMC_VDD_165_195,
        .f_max          = 50000000,
        .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index a534d8880de1..416d436111f2 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -23,6 +23,7 @@
 #include <linux/spi/spi.h>
 #include <linux/mfd/abx500/ab8500.h>
 #include <linux/regulator/ab8500.h>
+#include <linux/regulator/fixed.h>
 #include <linux/mfd/tc3589x.h>
 #include <linux/mfd/tps6105x.h>
 #include <linux/mfd/abx500/ab8500-gpio.h>
@@ -48,13 +49,12 @@
 #include <mach/setup.h>
 #include <mach/devices.h>
 #include <mach/irqs.h>
-#include <mach/crypto-ux500.h>
+#include <linux/platform_data/crypto-ux500.h>
 #include "ste-dma40-db8500.h"
 #include "devices-db8500.h"
 #include "board-mop500.h"
 #include "board-mop500-regulators.h"
-#include "board-mop500-msp.h"
 static struct gpio_led snowball_led_array[] = {
        {
@@ -76,6 +76,23 @@ static struct platform_device snowball_led_dev = {
        },
 };
+static struct fixed_voltage_config snowball_gpio_en_3v3_data = {
+       .supply_name            = "EN-3V3",
+       .gpio                   = SNOWBALL_EN_3V3_ETH_GPIO,
+       .microvolts             = 3300000,
+       .enable_high            = 1,
+       .init_data              = &gpio_en_3v3_regulator,
+       .startup_delay          = 5000, /* 1200us */
+};
+static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
+       .name   = "reg-fixed-voltage",
+       .id     = 1,
+       .dev    = {
+               .platform_data  = &snowball_gpio_en_3v3_data,
+       },
+};
 static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
        .gpio_base              = MOP500_AB8500_PIN_GPIO(1),
        .irq_base               = MOP500_AB8500_VIR_GPIO_IRQ_BASE,
@@ -524,33 +541,12 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
 };
 #endif
-#define PRCC_K_SOFTRST_SET      0x18
-#define PRCC_K_SOFTRST_CLEAR    0x1C
-static void ux500_uart0_reset(void)
-{
-        void __iomem *prcc_rst_set, *prcc_rst_clr;
-        prcc_rst_set = (void __iomem *)IO_ADDRESS(U8500_CLKRST1_BASE +
-                        PRCC_K_SOFTRST_SET);
-        prcc_rst_clr = (void __iomem *)IO_ADDRESS(U8500_CLKRST1_BASE +
-                        PRCC_K_SOFTRST_CLEAR);
-        /* Activate soft reset PRCC_K_SOFTRST_CLEAR */
-        writel((readl(prcc_rst_clr) | 0x1), prcc_rst_clr);
-        udelay(1);
-        /* Release soft reset PRCC_K_SOFTRST_SET */
-        writel((readl(prcc_rst_set) | 0x1), prcc_rst_set);
-        udelay(1);
-}
 static struct amba_pl011_data uart0_plat = {
 #ifdef CONFIG_STE_DMA40
        .dma_filter = stedma40_filter,
        .dma_rx_param = &uart0_dma_cfg_rx,
        .dma_tx_param = &uart0_dma_cfg_tx,
 #endif
-        .reset = ux500_uart0_reset,
 };
 static struct amba_pl011_data uart1_plat = {
@@ -586,6 +582,7 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
        &snowball_led_dev,
        &snowball_key_dev,
        &snowball_sbnet_dev,
+        &snowball_gpio_en_3v3_regulator_dev,
 };
 static void __init mop500_init_machine(void)
@@ -608,7 +605,7 @@ static void __init mop500_init_machine(void)
        mop500_i2c_init(parent);
        mop500_sdi_init(parent);
        mop500_spi_init(parent);
-        mop500_msp_init(parent);
+        mop500_audio_init(parent);
        mop500_uart_init(parent);
        u8500_cryp1_hash1_init(parent);
@@ -642,7 +639,7 @@ static void __init snowball_init_machine(void)
        mop500_i2c_init(parent);
        snowball_sdi_init(parent);
        mop500_spi_init(parent);
-        mop500_msp_init(parent);
+        mop500_audio_init(parent);
        mop500_uart_init(parent);
        /* This board has full regulator constraints */
@@ -674,7 +671,7 @@ static void __init hrefv60_init_machine(void)
        mop500_i2c_init(parent);
        hrefv60_sdi_init(parent);
        mop500_spi_init(parent);
-        mop500_msp_init(parent);
+        mop500_audio_init(parent);
        mop500_uart_init(parent);
        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -694,6 +691,7 @@ static void __init hrefv60_init_machine(void)
 MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
        /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */
        .atag_offset    = 0x100,
+        .smp            = smp_ops(ux500_smp_ops),
        .map_io         = u8500_map_io,
        .init_irq       = ux500_init_irq,
        /* we re-use nomadik timer here */
@@ -705,6 +703,7 @@ MACHINE_END
 MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
        .atag_offset    = 0x100,
+        .smp            = smp_ops(ux500_smp_ops),
        .map_io         = u8500_map_io,
        .init_irq       = ux500_init_irq,
        .timer          = &ux500_timer,
@@ -715,6 +714,7 @@ MACHINE_END
 MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
        .atag_offset    = 0x100,
+        .smp            = smp_ops(ux500_smp_ops),
        .map_io         = u8500_map_io,
        .init_irq       = ux500_init_irq,
        /* we re-use nomadik timer here */
@@ -726,12 +726,9 @@ MACHINE_END
 #ifdef CONFIG_MACH_UX500_DT
-static struct platform_device *snowball_of_platform_devs[] __initdata = {
-        &snowball_led_dev,
-        &snowball_key_dev,
-};
 struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
+        /* Requires call-back bindings. */
+        OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
        /* Requires DMA and call-back bindings. */
        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
@@ -739,6 +736,8 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
        /* Requires DMA bindings. */
        OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
        OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
+        OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
+        OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  &mop500_sdi2_data),
        OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  &mop500_sdi4_data),
        /* Requires clock name bindings. */
        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
@@ -757,6 +756,15 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
        /* Requires device name bindings. */
        OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
+        /* Requires clock name and DMA bindings. */
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
+                "ux500-msp-i2s.0", &msp0_platform_data),
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
+                "ux500-msp-i2s.1", &msp1_platform_data),
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
+                "ux500-msp-i2s.2", &msp2_platform_data),
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
+                "ux500-msp-i2s.3", &msp3_platform_data),
        {},
 };
@@ -797,7 +805,7 @@ static void __init u8500_init_machine(void)
                                ARRAY_SIZE(mop500_platform_devs));
                mop500_sdi_init(parent);
-                mop500_msp_init(parent);
+                mop500_audio_init(parent);
                i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
                i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
                i2c_register_board_info(2, mop500_i2c2_devices,
@@ -806,7 +814,7 @@ static void __init u8500_init_machine(void)
                mop500_uib_init();
        } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
-                mop500_msp_init(parent);
+                mop500_of_audio_init(parent);
        } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
                /*
                 * The HREFv60 board removed a GPIO expander and routed
@@ -817,16 +825,6 @@ static void __init u8500_init_machine(void)
                platform_add_devices(mop500_platform_devs,
                                ARRAY_SIZE(mop500_platform_devs));
-                hrefv60_sdi_init(parent);
-                mop500_msp_init(parent);
-                i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
-                i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
-                i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
-                i2c_register_board_info(2, mop500_i2c2_devices,
-                                        ARRAY_SIZE(mop500_i2c2_devices));
                mop500_uib_init();
        }
@@ -844,6 +842,7 @@ static const char * u8500_dt_board_compat[] = {
 DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)")
+        .smp            = smp_ops(ux500_smp_ops),
        .map_io         = u8500_map_io,
        .init_irq       = ux500_init_irq,
        /* we re-use nomadik timer here */
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index b5bfc1a78b1a..aca39a68712a 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -9,6 +9,7 @@
 /* For NOMADIK_NR_GPIO */
 #include <mach/irqs.h>
+#include <mach/msp.h>
 #include <linux/amba/mmci.h>
 /* Snowball specific GPIO assignments, this board has no GPIO expander */
@@ -80,7 +81,14 @@
 struct device;
 struct i2c_board_info;
 extern struct mmci_platform_data mop500_sdi0_data;
+extern struct mmci_platform_data mop500_sdi1_data;
+extern struct mmci_platform_data mop500_sdi2_data;
 extern struct mmci_platform_data mop500_sdi4_data;
+extern struct msp_i2s_platform_data msp0_platform_data;
+extern struct msp_i2s_platform_data msp1_platform_data;
+extern struct msp_i2s_platform_data msp2_platform_data;
+extern struct msp_i2s_platform_data msp3_platform_data;
+extern struct arm_pmu_platdata db8500_pmu_platdata;
 extern void mop500_sdi_init(struct device *parent);
 extern void snowball_sdi_init(struct device *parent);
@@ -91,6 +99,9 @@ void __init mop500_stuib_init(void);
 void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
 void __init hrefv60_pinmaps_init(void);
+void mop500_audio_init(struct device *parent);
+/* Due for removal once the MSP driver has been fully DT:ed. */
+void mop500_of_audio_init(struct device *parent);
 int __init mop500_uib_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index dc12394295d5..75d5b512a3d5 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -38,7 +38,7 @@ static int __init ux500_l2x0_init(void)
 {
        u32 aux_val = 0x3e000000;
-        if (cpu_is_u8500_family())
+        if (cpu_is_u8500_family() || cpu_is_ux540_family())
                l2x0_base = __io_address(U8500_L2CC_BASE);
        else
                ux500_unknown_soc();
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
deleted file mode 100644
index 8d73b066a18d..000000000000
--- a/arch/arm/mach-ux500/clock.c
+++ /dev/null
@@ -1,715 +0,0 @@
-/*
- *  Copyright (C) 2009 ST-Ericsson
- *  Copyright (C) 2009 STMicroelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/cpufreq.h>
-#include <plat/mtu.h>
-#include <mach/hardware.h>
-#include "clock.h"
-#ifdef CONFIG_DEBUG_FS
-#include <linux/debugfs.h>
-#include <linux/uaccess.h>      /* for copy_from_user */
-static LIST_HEAD(clk_list);
-#endif
-#define PRCC_PCKEN              0x00
-#define PRCC_PCKDIS             0x04
-#define PRCC_KCKEN              0x08
-#define PRCC_KCKDIS             0x0C
-#define PRCM_YYCLKEN0_MGT_SET   0x510
-#define PRCM_YYCLKEN1_MGT_SET   0x514
-#define PRCM_YYCLKEN0_MGT_CLR   0x518
-#define PRCM_YYCLKEN1_MGT_CLR   0x51C
-#define PRCM_YYCLKEN0_MGT_VAL   0x520
-#define PRCM_YYCLKEN1_MGT_VAL   0x524
-#define PRCM_SVAMMDSPCLK_MGT    0x008
-#define PRCM_SIAMMDSPCLK_MGT    0x00C
-#define PRCM_SGACLK_MGT         0x014
-#define PRCM_UARTCLK_MGT        0x018
-#define PRCM_MSP02CLK_MGT       0x01C
-#define PRCM_MSP1CLK_MGT        0x288
-#define PRCM_I2CCLK_MGT         0x020
-#define PRCM_SDMMCCLK_MGT       0x024
-#define PRCM_SLIMCLK_MGT        0x028
-#define PRCM_PER1CLK_MGT        0x02C
-#define PRCM_PER2CLK_MGT        0x030
-#define PRCM_PER3CLK_MGT        0x034
-#define PRCM_PER5CLK_MGT        0x038
-#define PRCM_PER6CLK_MGT        0x03C
-#define PRCM_PER7CLK_MGT        0x040
-#define PRCM_LCDCLK_MGT         0x044
-#define PRCM_BMLCLK_MGT         0x04C
-#define PRCM_HSITXCLK_MGT       0x050
-#define PRCM_HSIRXCLK_MGT       0x054
-#define PRCM_HDMICLK_MGT        0x058
-#define PRCM_APEATCLK_MGT       0x05C
-#define PRCM_APETRACECLK_MGT    0x060
-#define PRCM_MCDECLK_MGT        0x064
-#define PRCM_IPI2CCLK_MGT       0x068
-#define PRCM_DSIALTCLK_MGT      0x06C
-#define PRCM_DMACLK_MGT         0x074
-#define PRCM_B2R2CLK_MGT        0x078
-#define PRCM_TVCLK_MGT          0x07C
-#define PRCM_TCR                0x1C8
-#define PRCM_TCR_STOPPED        (1 << 16)
-#define PRCM_TCR_DOZE_MODE      (1 << 17)
-#define PRCM_UNIPROCLK_MGT      0x278
-#define PRCM_SSPCLK_MGT         0x280
-#define PRCM_RNGCLK_MGT         0x284
-#define PRCM_UICCCLK_MGT        0x27C
-#define PRCM_MGT_ENABLE         (1 << 8)
-static DEFINE_SPINLOCK(clocks_lock);
-static void __clk_enable(struct clk *clk)
-{
-        if (clk->enabled++ == 0) {
-                if (clk->parent_cluster)
-                        __clk_enable(clk->parent_cluster);
-                if (clk->parent_periph)
-                        __clk_enable(clk->parent_periph);
-                if (clk->ops && clk->ops->enable)
-                        clk->ops->enable(clk);
-        }
-}
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&clocks_lock, flags);
-        __clk_enable(clk);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-static void __clk_disable(struct clk *clk)
-{
-        if (--clk->enabled == 0) {
-                if (clk->ops && clk->ops->disable)
-                        clk->ops->disable(clk);
-                if (clk->parent_periph)
-                        __clk_disable(clk->parent_periph);
-                if (clk->parent_cluster)
-                        __clk_disable(clk->parent_cluster);
-        }
-}
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-        WARN_ON(!clk->enabled);
-        spin_lock_irqsave(&clocks_lock, flags);
-        __clk_disable(clk);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-/*
- * The MTU has a separate, rather complex muxing setup
- * with alternative parents (peripheral cluster or
- * ULP or fixed 32768 Hz) depending on settings
- */
-static unsigned long clk_mtu_get_rate(struct clk *clk)
-{
-        void __iomem *addr;
-        u32 tcr;
-        int mtu = (int) clk->data;
-        /*
-         * One of these is selected eventually
-         * TODO: Replace the constant with a reference
-         * to the ULP source once this is modeled.
-         */
-        unsigned long clk32k = 32768;
-        unsigned long mturate;
-        unsigned long retclk;
-        if (cpu_is_u8500_family())
-                addr = __io_address(U8500_PRCMU_BASE);
-        else
-                ux500_unknown_soc();
-        /*
-         * On a startup, always conifgure the TCR to the doze mode;
-         * bootloaders do it for us. Do this in the kernel too.
-         */
-        writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR);
-        tcr = readl(addr + PRCM_TCR);
-        /* Get the rate from the parent as a default */
-        if (clk->parent_periph)
-                mturate = clk_get_rate(clk->parent_periph);
-        else if (clk->parent_cluster)
-                mturate = clk_get_rate(clk->parent_cluster);
-        else
-                /* We need to be connected SOMEWHERE */
-                BUG();
-        /* Return the clock selected for this MTU */
-        if (tcr & (1 << mtu))
-                retclk = clk32k;
-        else
-                retclk = mturate;
-        pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
-        return retclk;
-}
-unsigned long clk_get_rate(struct clk *clk)
-{
-        unsigned long rate;
-        /*
-         * If there is a custom getrate callback for this clock,
-         * it will take precedence.
-         */
-        if (clk->get_rate)
-                return clk->get_rate(clk);
-        if (clk->ops && clk->ops->get_rate)
-                return clk->ops->get_rate(clk);
-        rate = clk->rate;
-        if (!rate) {
-                if (clk->parent_periph)
-                        rate = clk_get_rate(clk->parent_periph);
-                else if (clk->parent_cluster)
-                        rate = clk_get_rate(clk->parent_cluster);
-        }
-        return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        /*TODO*/
-        return rate;
-}
-EXPORT_SYMBOL(clk_round_rate);
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        clk->rate = rate;
-        return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        /*TODO*/
-        return -ENOSYS;
-}
-EXPORT_SYMBOL(clk_set_parent);
-static void clk_prcmu_enable(struct clk *clk)
-{
-        void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
-                                   + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;
-        writel(1 << clk->prcmu_cg_bit, cg_set_reg);
-}
-static void clk_prcmu_disable(struct clk *clk)
-{
-        void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
-                                   + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;
-        writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
-}
-static struct clkops clk_prcmu_ops = {
-        .enable = clk_prcmu_enable,
-        .disable = clk_prcmu_disable,
-};
-static unsigned int clkrst_base[] = {
-        [1] = U8500_CLKRST1_BASE,
-        [2] = U8500_CLKRST2_BASE,
-        [3] = U8500_CLKRST3_BASE,
-        [5] = U8500_CLKRST5_BASE,
-        [6] = U8500_CLKRST6_BASE,
-};
-static void clk_prcc_enable(struct clk *clk)
-{
-        void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
-        if (clk->prcc_kernel != -1)
-                writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);
-        if (clk->prcc_bus != -1)
-                writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
-}
-static void clk_prcc_disable(struct clk *clk)
-{
-        void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
-        if (clk->prcc_bus != -1)
-                writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);
-        if (clk->prcc_kernel != -1)
-                writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
-}
-static struct clkops clk_prcc_ops = {
-        .enable = clk_prcc_enable,
-        .disable = clk_prcc_disable,
-};
-static struct clk clk_32khz = {
-        .name =  "clk_32khz",
-        .rate = 32000,
-};
-/*
- * PRCMU level clock gating
- */
-/* Bank 0 */
-static DEFINE_PRCMU_CLK(svaclk,         0x0, 2, SVAMMDSPCLK);
-static DEFINE_PRCMU_CLK(siaclk,         0x0, 3, SIAMMDSPCLK);
-static DEFINE_PRCMU_CLK(sgaclk,         0x0, 4, SGACLK);
-static DEFINE_PRCMU_CLK_RATE(uartclk,   0x0, 5, UARTCLK, 38400000);
-static DEFINE_PRCMU_CLK(msp02clk,       0x0, 6, MSP02CLK);
-static DEFINE_PRCMU_CLK(msp1clk,        0x0, 7, MSP1CLK); /* v1 */
-static DEFINE_PRCMU_CLK_RATE(i2cclk,    0x0, 8, I2CCLK, 48000000);
-static DEFINE_PRCMU_CLK_RATE(sdmmcclk,  0x0, 9, SDMMCCLK, 100000000);
-static DEFINE_PRCMU_CLK(slimclk,        0x0, 10, SLIMCLK);
-static DEFINE_PRCMU_CLK(per1clk,        0x0, 11, PER1CLK);
-static DEFINE_PRCMU_CLK(per2clk,        0x0, 12, PER2CLK);
-static DEFINE_PRCMU_CLK(per3clk,        0x0, 13, PER3CLK);
-static DEFINE_PRCMU_CLK(per5clk,        0x0, 14, PER5CLK);
-static DEFINE_PRCMU_CLK_RATE(per6clk,   0x0, 15, PER6CLK, 133330000);
-static DEFINE_PRCMU_CLK(lcdclk,         0x0, 17, LCDCLK);
-static DEFINE_PRCMU_CLK(bmlclk,         0x0, 18, BMLCLK);
-static DEFINE_PRCMU_CLK(hsitxclk,       0x0, 19, HSITXCLK);
-static DEFINE_PRCMU_CLK(hsirxclk,       0x0, 20, HSIRXCLK);
-static DEFINE_PRCMU_CLK(hdmiclk,        0x0, 21, HDMICLK);
-static DEFINE_PRCMU_CLK(apeatclk,       0x0, 22, APEATCLK);
-static DEFINE_PRCMU_CLK(apetraceclk,    0x0, 23, APETRACECLK);
-static DEFINE_PRCMU_CLK(mcdeclk,        0x0, 24, MCDECLK);
-static DEFINE_PRCMU_CLK(ipi2clk,        0x0, 25, IPI2CCLK);
-static DEFINE_PRCMU_CLK(dsialtclk,      0x0, 26, DSIALTCLK); /* v1 */
-static DEFINE_PRCMU_CLK(dmaclk,         0x0, 27, DMACLK);
-static DEFINE_PRCMU_CLK(b2r2clk,        0x0, 28, B2R2CLK);
-static DEFINE_PRCMU_CLK(tvclk,          0x0, 29, TVCLK);
-static DEFINE_PRCMU_CLK(uniproclk,      0x0, 30, UNIPROCLK); /* v1 */
-static DEFINE_PRCMU_CLK_RATE(sspclk,    0x0, 31, SSPCLK, 48000000); /* v1 */
-/* Bank 1 */
-static DEFINE_PRCMU_CLK(rngclk,         0x4, 0, RNGCLK); /* v1 */
-static DEFINE_PRCMU_CLK(uiccclk,        0x4, 1, UICCCLK); /* v1 */
-/*
- * PRCC level clock gating
- * Format: per#, clk, PCKEN bit, KCKEN bit, parent
- */
-/* Peripheral Cluster #1 */
-static DEFINE_PRCC_CLK(1, msp3,         11, 10, &clk_msp1clk);
-static DEFINE_PRCC_CLK(1, i2c4,         10, 9, &clk_i2cclk);
-static DEFINE_PRCC_CLK(1, gpio0,        9, -1, NULL);
-static DEFINE_PRCC_CLK(1, slimbus0,     8,  8, &clk_slimclk);
-static DEFINE_PRCC_CLK(1, spi3,         7, -1, NULL);
-static DEFINE_PRCC_CLK(1, i2c2,         6,  6, &clk_i2cclk);
-static DEFINE_PRCC_CLK(1, sdi0,         5,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(1, msp1,         4,  4, &clk_msp1clk);
-static DEFINE_PRCC_CLK(1, msp0,         3,  3, &clk_msp02clk);
-static DEFINE_PRCC_CLK(1, i2c1,         2,  2, &clk_i2cclk);
-static DEFINE_PRCC_CLK(1, uart1,        1,  1, &clk_uartclk);
-static DEFINE_PRCC_CLK(1, uart0,        0,  0, &clk_uartclk);
-/* Peripheral Cluster #2 */
-static DEFINE_PRCC_CLK(2, gpio1,        11, -1, NULL);
-static DEFINE_PRCC_CLK(2, ssitx,        10,  7, NULL);
-static DEFINE_PRCC_CLK(2, ssirx,         9,  6, NULL);
-static DEFINE_PRCC_CLK(2, spi0,         8, -1, NULL);
-static DEFINE_PRCC_CLK(2, sdi3,         7,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, sdi1,         6,  4, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, msp2,         5,  3, &clk_msp02clk);
-static DEFINE_PRCC_CLK(2, sdi4,         4,  2, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, pwl,          3,  1, NULL);
-static DEFINE_PRCC_CLK(2, spi1,         2, -1, NULL);
-static DEFINE_PRCC_CLK(2, spi2,         1, -1, NULL);
-static DEFINE_PRCC_CLK(2, i2c3,         0,  0, &clk_i2cclk);
-/* Peripheral Cluster #3 */
-static DEFINE_PRCC_CLK(3, gpio2,        8, -1, NULL);
-static DEFINE_PRCC_CLK(3, sdi5,         7,  7, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(3, uart2,        6,  6, &clk_uartclk);
-static DEFINE_PRCC_CLK(3, ske,          5,  5, &clk_32khz);
-static DEFINE_PRCC_CLK(3, sdi2,         4,  4, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(3, i2c0,         3,  3, &clk_i2cclk);
-static DEFINE_PRCC_CLK(3, ssp1,         2,  2, &clk_sspclk);
-static DEFINE_PRCC_CLK(3, ssp0,         1,  1, &clk_sspclk);
-static DEFINE_PRCC_CLK(3, fsmc,         0, -1, NULL);
-/* Peripheral Cluster #4 is in the always on domain */
-/* Peripheral Cluster #5 */
-static DEFINE_PRCC_CLK(5, gpio3,        1, -1, NULL);
-static DEFINE_PRCC_CLK(5, usb,          0,  0, NULL);
-/* Peripheral Cluster #6 */
-/* MTU ID in data */
-static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1);
-static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0);
-static DEFINE_PRCC_CLK(6, cfgreg,       7,  7, NULL);
-static DEFINE_PRCC_CLK(6, hash1,        6, -1, NULL);
-static DEFINE_PRCC_CLK(6, unipro,       5,  1, &clk_uniproclk);
-static DEFINE_PRCC_CLK(6, pka,          4, -1, NULL);
-static DEFINE_PRCC_CLK(6, hash0,        3, -1, NULL);
-static DEFINE_PRCC_CLK(6, cryp0,        2, -1, NULL);
-static DEFINE_PRCC_CLK(6, cryp1,    1, -1, NULL);
-static DEFINE_PRCC_CLK(6, rng,  0,  0, &clk_rngclk);
-static struct clk clk_dummy_apb_pclk = {
-        .name = "apb_pclk",
-};
-static struct clk_lookup u8500_clks[] = {
-        CLK(dummy_apb_pclk, NULL,       "apb_pclk"),
-        /* Peripheral Cluster #1 */
-        CLK(gpio0,      "gpio.0",       NULL),
-        CLK(gpio0,      "gpio.1",       NULL),
-        CLK(slimbus0,   "slimbus0",     NULL),
-        CLK(i2c2,       "nmk-i2c.2",    NULL),
-        CLK(sdi0,       "sdi0",         NULL),
-        CLK(msp0,       "ux500-msp-i2s.0",      NULL),
-        CLK(i2c1,       "nmk-i2c.1",    NULL),
-        CLK(uart1,      "uart1",        NULL),
-        CLK(uart0,      "uart0",        NULL),
-        /* Peripheral Cluster #3 */
-        CLK(gpio2,      "gpio.2",       NULL),
-        CLK(gpio2,      "gpio.3",       NULL),
-        CLK(gpio2,      "gpio.4",       NULL),
-        CLK(gpio2,      "gpio.5",       NULL),
-        CLK(sdi5,       "sdi5",         NULL),
-        CLK(uart2,      "uart2",        NULL),
-        CLK(ske,        "ske",          NULL),
-        CLK(ske,        "nmk-ske-keypad",       NULL),
-        CLK(sdi2,       "sdi2",         NULL),
-        CLK(i2c0,       "nmk-i2c.0",    NULL),
-        CLK(fsmc,       "fsmc",         NULL),
-        /* Peripheral Cluster #5 */
-        CLK(gpio3,      "gpio.8",       NULL),
-        /* Peripheral Cluster #6 */
-        CLK(hash1,      "hash1",        NULL),
-        CLK(pka,        "pka",          NULL),
-        CLK(hash0,      "hash0",        NULL),
-        CLK(cryp0,      "cryp0",        NULL),
-        CLK(cryp1,  "cryp1",    NULL),
-        /* PRCMU level clock gating */
-        /* Bank 0 */
-        CLK(svaclk,     "sva",          NULL),
-        CLK(siaclk,     "sia",          NULL),
-        CLK(sgaclk,     "sga",          NULL),
-        CLK(slimclk,    "slim",         NULL),
-        CLK(lcdclk,     "lcd",          NULL),
-        CLK(bmlclk,     "bml",          NULL),
-        CLK(hsitxclk,   "stm-hsi.0",    NULL),
-        CLK(hsirxclk,   "stm-hsi.1",    NULL),
-        CLK(hdmiclk,    "hdmi",         NULL),
-        CLK(apeatclk,   "apeat",        NULL),
-        CLK(apetraceclk,        "apetrace",     NULL),
-        CLK(mcdeclk,    "mcde",         NULL),
-        CLK(ipi2clk,    "ipi2",         NULL),
-        CLK(dmaclk,     "dma40.0",      NULL),
-        CLK(b2r2clk,    "b2r2",         NULL),
-        CLK(tvclk,      "tv",           NULL),
-        /* Peripheral Cluster #1 */
-        CLK(i2c4,       "nmk-i2c.4",    NULL),
-        CLK(spi3,       "spi3",         NULL),
-        CLK(msp1,       "ux500-msp-i2s.1",      NULL),
-        CLK(msp3,       "ux500-msp-i2s.3",      NULL),
-        /* Peripheral Cluster #2 */
-        CLK(gpio1,      "gpio.6",       NULL),
-        CLK(gpio1,      "gpio.7",       NULL),
-        CLK(ssitx,      "ssitx",        NULL),
-        CLK(ssirx,      "ssirx",        NULL),
-        CLK(spi0,       "spi0",         NULL),
-        CLK(sdi3,       "sdi3",         NULL),
-        CLK(sdi1,       "sdi1",         NULL),
-        CLK(msp2,       "ux500-msp-i2s.2",      NULL),
-        CLK(sdi4,       "sdi4",         NULL),
-        CLK(pwl,        "pwl",          NULL),
-        CLK(spi1,       "spi1",         NULL),
-        CLK(spi2,       "spi2",         NULL),
-        CLK(i2c3,       "nmk-i2c.3",    NULL),
-        /* Peripheral Cluster #3 */
-        CLK(ssp1,       "ssp1",         NULL),
-        CLK(ssp0,       "ssp0",         NULL),
-        /* Peripheral Cluster #5 */
-        CLK(usb,        "musb-ux500.0", "usb"),
-        /* Peripheral Cluster #6 */
-        CLK(mtu1,       "mtu1",         NULL),
-        CLK(mtu0,       "mtu0",         NULL),
-        CLK(cfgreg,     "cfgreg",       NULL),
-        CLK(hash1,      "hash1",        NULL),
-        CLK(unipro,     "unipro",       NULL),
-        CLK(rng,        "rng",          NULL),
-        /* PRCMU level clock gating */
-        /* Bank 0 */
-        CLK(uniproclk,  "uniproclk",    NULL),
-        CLK(dsialtclk,  "dsialt",       NULL),
-        /* Bank 1 */
-        CLK(rngclk,     "rng",          NULL),
-        CLK(uiccclk,    "uicc",         NULL),
-};
-#ifdef CONFIG_DEBUG_FS
-/*
- *      debugfs support to trace clock tree hierarchy and attributes with
- *      powerdebug
- */
-static struct dentry *clk_debugfs_root;
-void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num)
-{
-        while (num--) {
-                /* Check that the clock has not been already registered */
-                if (!(cl->clk->list.prev != cl->clk->list.next))
-                        list_add_tail(&cl->clk->list, &clk_list);
-                cl++;
-        }
-}
-static ssize_t usecount_dbg_read(struct file *file, char __user *buf,
-                                                  size_t size, loff_t *off)
-{
-        struct clk *clk = file->f_dentry->d_inode->i_private;
-        char cusecount[128];
-        unsigned int len;
-        len = sprintf(cusecount, "%u\n", clk->enabled);
-        return simple_read_from_buffer(buf, size, off, cusecount, len);
-}
-static ssize_t rate_dbg_read(struct file *file, char __user *buf,
-                                          size_t size, loff_t *off)
-{
-        struct clk *clk = file->f_dentry->d_inode->i_private;
-        char crate[128];
-        unsigned int rate;
-        unsigned int len;
-        rate = clk_get_rate(clk);
-        len = sprintf(crate, "%u\n", rate);
-        return simple_read_from_buffer(buf, size, off, crate, len);
-}
-static const struct file_operations usecount_fops = {
-        .read = usecount_dbg_read,
-};
-static const struct file_operations set_rate_fops = {
-        .read = rate_dbg_read,
-};
-static struct dentry *clk_debugfs_register_dir(struct clk *c,
-                                                struct dentry *p_dentry)
-{
-        struct dentry *d, *clk_d;
-        const char *p = c->name;
-        if (!p)
-                p = "BUG";
-        clk_d = debugfs_create_dir(p, p_dentry);
-        if (!clk_d)
-                return NULL;
-        d = debugfs_create_file("usecount", S_IRUGO,
-                                clk_d, c, &usecount_fops);
-        if (!d)
-                goto err_out;
-        d = debugfs_create_file("rate", S_IRUGO,
-                                clk_d, c, &set_rate_fops);
-        if (!d)
-                goto err_out;
-        /*
-         * TODO : not currently available in ux500
-         * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags);
-         * if (!d)
-         *      goto err_out;
-         */
-        return clk_d;
-err_out:
-        debugfs_remove_recursive(clk_d);
-        return NULL;
-}
-static int clk_debugfs_register_one(struct clk *c)
-{
-        struct clk *pa = c->parent_periph;
-        struct clk *bpa = c->parent_cluster;
-        if (!(bpa && !pa)) {
-                c->dent = clk_debugfs_register_dir(c,
-                                pa ? pa->dent : clk_debugfs_root);
-                if (!c->dent)
-                        return -ENOMEM;
-        }
-        if (bpa) {
-                c->dent_bus = clk_debugfs_register_dir(c,
-                                bpa->dent_bus ? bpa->dent_bus : bpa->dent);
-                if ((!c->dent_bus) &&  (c->dent)) {
-                        debugfs_remove_recursive(c->dent);
-                        c->dent = NULL;
-                        return -ENOMEM;
-                }
-        }
-        return 0;
-}
-static int clk_debugfs_register(struct clk *c)
-{
-        int err;
-        struct clk *pa = c->parent_periph;
-        struct clk *bpa = c->parent_cluster;
-        if (pa && (!pa->dent && !pa->dent_bus)) {
-                err = clk_debugfs_register(pa);
-                if (err)
-                        return err;
-        }
-        if (bpa && (!bpa->dent && !bpa->dent_bus)) {
-                err = clk_debugfs_register(bpa);
-                if (err)
-                        return err;
-        }
-        if ((!c->dent) && (!c->dent_bus)) {
-                err = clk_debugfs_register_one(c);
-                if (err)
-                        return err;
-        }
-        return 0;
-}
-int __init clk_debugfs_init(void)
-{
-        struct clk *c;
-        struct dentry *d;
-        int err;
-        d = debugfs_create_dir("clock", NULL);
-        if (!d)
-                return -ENOMEM;
-        clk_debugfs_root = d;
-        list_for_each_entry(c, &clk_list, list) {
-                err = clk_debugfs_register(c);
-                if (err)
-                        goto err_out;
-        }
-        return 0;
-err_out:
-        debugfs_remove_recursive(clk_debugfs_root);
-        return err;
-}
-#endif /* defined(CONFIG_DEBUG_FS) */
-unsigned long clk_smp_twd_rate = 500000000;
-unsigned long clk_smp_twd_get_rate(struct clk *clk)
-{
-        return clk_smp_twd_rate;
-}
-static struct clk clk_smp_twd = {
-        .get_rate = clk_smp_twd_get_rate,
-        .name =  "smp_twd",
-};
-static struct clk_lookup clk_smp_twd_lookup = {
-        .dev_id = "smp_twd",
-        .clk = &clk_smp_twd,
-};
-#ifdef CONFIG_CPU_FREQ
-static int clk_twd_cpufreq_transition(struct notifier_block *nb,
-                                      unsigned long state, void *data)
-{
-        struct cpufreq_freqs *f = data;
-        if (state == CPUFREQ_PRECHANGE) {
-                /* Save frequency in simple Hz */
-                clk_smp_twd_rate = (f->new * 1000) / 2;
-        }
-        return NOTIFY_OK;
-}
-static struct notifier_block clk_twd_cpufreq_nb = {
-        .notifier_call = clk_twd_cpufreq_transition,
-};
-int clk_init_smp_twd_cpufreq(void)
-{
-        return cpufreq_register_notifier(&clk_twd_cpufreq_nb,
-                                  CPUFREQ_TRANSITION_NOTIFIER);
-}
-#endif
-int __init clk_init(void)
-{
-        clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
-        clkdev_add(&clk_smp_twd_lookup);
-#ifdef CONFIG_DEBUG_FS
-        clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
-#endif
-        return 0;
-}
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
deleted file mode 100644
index 65d27a13f46d..000000000000
--- a/arch/arm/mach-ux500/clock.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- *  Copyright (C) 2010 ST-Ericsson
- *  Copyright (C) 2009 STMicroelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/**
- * struct clkops - ux500 clock operations
- * @enable:     function to enable the clock
- * @disable:    function to disable the clock
- * @get_rate:   function to get the current clock rate
- *
- * This structure contains function pointers to functions that will be used to
- * control the clock.  All of these functions are optional.  If get_rate is
- * NULL, the rate in the struct clk will be used.
- */
-struct clkops {
-        void (*enable) (struct clk *);
-        void (*disable) (struct clk *);
-        unsigned long (*get_rate) (struct clk *);
-        int (*set_parent)(struct clk *, struct clk *);
-};
-/**
- * struct clk - ux500 clock structure
- * @ops:                pointer to clkops struct used to control this clock
- * @name:               name, for debugging
- * @enabled:            refcount. positive if enabled, zero if disabled
- * @get_rate:           custom callback for getting the clock rate
- * @data:               custom per-clock data for example for the get_rate
- *                      callback
- * @rate:               fixed rate for clocks which don't implement
- *                      ops->getrate
- * @prcmu_cg_off:       address offset of the combined enable/disable register
- *                      (used on u8500v1)
- * @prcmu_cg_bit:       bit in the combined enable/disable register (used on
- *                      u8500v1)
- * @prcmu_cg_mgt:       address of the enable/disable register (used on
- *                      u8500ed)
- * @cluster:            peripheral cluster number
- * @prcc_bus:           bit for the bus clock in the peripheral's CLKRST
- * @prcc_kernel:        bit for the kernel clock in the peripheral's CLKRST.
- *                      -1 if no kernel clock exists.
- * @parent_cluster:     pointer to parent's cluster clk struct
- * @parent_periph:      pointer to parent's peripheral clk struct
- *
- * Peripherals are organised into clusters, and each cluster has an associated
- * bus clock.  Some peripherals also have a parent peripheral clock.
- *
- * In order to enable a clock for a peripheral, we need to enable:
- *      (1) the parent cluster (bus) clock at the PRCMU level
- *      (2) the parent peripheral clock (if any) at the PRCMU level
- *      (3) the peripheral's bus & kernel clock at the PRCC level
- *
- * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each
- * of the cluster and peripheral clocks, and hooking these as the parents of
- * the individual peripheral clocks.
- *
- * (3) is handled by specifying the bits in the PRCC control registers required
- * to enable these clocks and modifying them in the ->enable and
- * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK).
- *
- * This structure describes both the PRCMU-level clocks and PRCC-level clocks.
- * The prcmu_* fields are only used for the PRCMU clocks, and the cluster,
- * prcc, and parent pointers are only used for the PRCC-level clocks.
- */
-struct clk {
-        const struct clkops     *ops;
-        const char              *name;
-        unsigned int            enabled;
-        unsigned long           (*get_rate)(struct clk *);
-        void                    *data;
-        unsigned long           rate;
-        struct list_head        list;
-        /* These three are only for PRCMU clks */
-        unsigned int            prcmu_cg_off;
-        unsigned int            prcmu_cg_bit;
-        unsigned int            prcmu_cg_mgt;
-        /* The rest are only for PRCC clks */
-        int                     cluster;
-        unsigned int            prcc_bus;
-        unsigned int            prcc_kernel;
-        struct clk              *parent_cluster;
-        struct clk              *parent_periph;
-#if defined(CONFIG_DEBUG_FS)
-        struct dentry           *dent;          /* For visible tree hierarchy */
-        struct dentry           *dent_bus;      /* For visible tree hierarchy */
-#endif
-};
-#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg)         \
-struct clk clk_##_name = {                                      \
-                .name           = #_name,                       \
-                .ops            = &clk_prcmu_ops,               \
-                .prcmu_cg_off   = _cg_off,                      \
-                .prcmu_cg_bit   = _cg_bit,                      \
-                .prcmu_cg_mgt   = PRCM_##_reg##_MGT             \
-        }
-#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate)     \
-struct clk clk_##_name = {                                              \
-                .name           = #_name,                               \
-                .ops            = &clk_prcmu_ops,                       \
-                .prcmu_cg_off   = _cg_off,                              \
-                .prcmu_cg_bit   = _cg_bit,                              \
-                .rate           = _rate,                                \
-                .prcmu_cg_mgt   = PRCM_##_reg##_MGT                     \
-        }
-#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk)  \
-struct clk clk_##_name = {                                              \
-                .name           = #_name,                               \
-                .ops            = &clk_prcc_ops,                        \
-                .cluster        = _pclust,                              \
-                .prcc_bus       = _bus_en,                              \
-                .prcc_kernel    = _kernel_en,                           \
-                .parent_cluster = &clk_per##_pclust##clk,               \
-                .parent_periph  = _kernclk                              \
-        }
-#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \
-struct clk clk_##_name = {                                              \
-                .name           = #_name,                               \
-                .ops            = &clk_prcc_ops,                        \
-                .cluster        = _pclust,                              \
-                .prcc_bus       = _bus_en,                              \
-                .prcc_kernel    = _kernel_en,                           \
-                .parent_cluster = &clk_per##_pclust##clk,               \
-                .parent_periph  = _kernclk,                             \
-                .get_rate       = _callback,                            \
-                .data           = (void *) _data                        \
-        }
-#define CLK(_clk, _devname, _conname)                   \
-        {                                               \
-                .clk    = &clk_##_clk,                  \
-                .dev_id = _devname,                     \
-                .con_id = _conname,                     \
-        }
-int __init clk_db8500_ed_fixup(void);
-int __init clk_init(void);
-#ifdef CONFIG_DEBUG_FS
-int clk_debugfs_init(void);
-#else
-static inline int clk_debugfs_init(void) { return 0; }
-#endif
-#ifdef CONFIG_CPU_FREQ
-int clk_init_smp_twd_cpufreq(void);
-#else
-static inline int clk_init_smp_twd_cpufreq(void) { return 0; }
-#endif
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index db3c52d56ca4..bcdfe6b1d453 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -18,13 +18,13 @@
 #include <linux/io.h>
 #include <linux/mfd/abx500/ab8500.h>
-#include <asm/mach/map.h>
 #include <asm/pmu.h>
+#include <asm/mach/map.h>
 #include <plat/gpio-nomadik.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-musb-ux500.h>
 #include <mach/db8500-regs.h>
 #include "devices-db8500.h"
@@ -80,7 +80,7 @@ void __init u8500_map_io(void)
        iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));
-        if (cpu_is_u9540())
+        if (cpu_is_ux540_family())
                iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
        else
                iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
@@ -122,7 +122,7 @@ struct arm_pmu_platdata db8500_pmu_platdata = {
 static struct platform_device db8500_pmu_device = {
        .name                   = "arm-pmu",
-        .id                     = ARM_PMU_DEVICE_CPU,
+        .id                     = -1,
        .num_resources          = ARRAY_SIZE(db8500_pmu_resources),
        .resource               = db8500_pmu_resources,
        .dev.platform_data      = &db8500_pmu_platdata,
@@ -138,10 +138,6 @@ static struct platform_device *platform_devs[] __initdata = {
        &db8500_prcmu_device,
 };
-static struct platform_device *of_platform_devs[] __initdata = {
-        &u8500_dma40_device,
-};
 static resource_size_t __initdata db8500_gpio_base[] = {
        U8500_GPIOBANK0_BASE,
        U8500_GPIOBANK1_BASE,
@@ -235,7 +231,6 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
 struct device * __init u8500_of_init_devices(void)
 {
        struct device *parent;
-        int i;
        parent = db8500_soc_device_init();
@@ -244,8 +239,7 @@ struct device * __init u8500_of_init_devices(void)
        platform_device_register_data(parent,
                "cpufreq-u8500", -1, NULL, 0);
-        for (i = 0; i < ARRAY_SIZE(of_platform_devs); i++)
+        u8500_dma40_device.dev.parent = parent;
-                of_platform_devs[i]->dev.parent = parent;
        /*
         * Devices to be DT:ed:
@@ -253,7 +247,7 @@ struct device * __init u8500_of_init_devices(void)
         *   db8500_pmu_device   = done
         *   db8500_prcmu_device = done
         */
-        platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs));
+        platform_device_register(&u8500_dma40_device);
        return parent;
 }
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index e2360e7c770d..2236cbd03cd7 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -8,7 +8,6 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/clk.h>
 #include <linux/mfd/db8500-prcmu.h>
 #include <linux/clksrc-dbx500-prcmu.h>
 #include <linux/sys_soc.h>
@@ -17,6 +16,7 @@
 #include <linux/stat.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
+#include <linux/platform_data/clk-ux500.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
@@ -25,8 +25,6 @@
 #include <mach/setup.h>
 #include <mach/devices.h>
-#include "clock.h"
 void __iomem *_PRCMU_BASE;
 /*
@@ -51,7 +49,9 @@ void __init ux500_init_irq(void)
        void __iomem *dist_base;
        void __iomem *cpu_base;
-        if (cpu_is_u8500_family()) {
+        gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+        if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
                dist_base = __io_address(U8500_GIC_DIST_BASE);
                cpu_base = __io_address(U8500_GIC_CPU_BASE);
        } else
@@ -70,13 +70,17 @@ void __init ux500_init_irq(void)
         */
        if (cpu_is_u8500_family())
                db8500_prcmu_early_init();
-        clk_init();
+        if (cpu_is_u8500_family())
+                u8500_clk_init();
+        else if (cpu_is_u9540())
+                u9540_clk_init();
+        else if (cpu_is_u8540())
+                u8540_clk_init();
 }
 void __init ux500_init_late(void)
 {
-        clk_debugfs_init();
-        clk_init_smp_twd_cpufreq();
 }
 static const char * __init ux500_get_machine(void)
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index ecdd8386cffb..7fbf0ba336e1 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -13,7 +13,7 @@
 #include <linux/sys_soc.h>
 #include <linux/amba/bus.h>
 #include <linux/platform_data/i2c-nomadik.h>
-#include <mach/crypto-ux500.h>
+#include <linux/platform_data/crypto-ux500.h>
 struct spi_master_cntlr;
diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c
index c76f0f456f04..2f6af259015d 100644
--- a/arch/arm/mach-ux500/hotplug.c
+++ b/arch/arm/mach-ux500/hotplug.c
@@ -15,13 +15,18 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
-extern volatile int pen_release;
+#include <mach/setup.h>
-static inline void platform_do_lowpower(unsigned int cpu)
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __ref ux500_cpu_die(unsigned int cpu)
 {
        flush_cache_all();
-        /* we put the platform to just WFI */
+        /* directly enter low power state, skipping secure registers */
        for (;;) {
                __asm__ __volatile__("dsb\n\t" "wfi\n\t"
                                : : : "memory");
@@ -33,28 +38,3 @@ static inline void platform_do_lowpower(unsigned int cpu)
                }
        }
 }
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void platform_cpu_die(unsigned int cpu)
-{
-        /* directly enter low power state, skipping secure registers */
-        platform_do_lowpower(cpu);
-}
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-ux500/include/mach/crypto-ux500.h b/arch/arm/mach-ux500/include/mach/crypto-ux500.h
deleted file mode 100644
index 5b2d0817e26a..000000000000
--- a/arch/arm/mach-ux500/include/mach/crypto-ux500.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2011
- *
- * Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- */
-#ifndef _CRYPTO_UX500_H
-#define _CRYPTO_UX500_H
-#include <linux/dmaengine.h>
-#include <plat/ste_dma40.h>
-struct hash_platform_data {
-        void *mem_to_engine;
-        bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
-};
-struct cryp_platform_data {
-        struct stedma40_chan_cfg mem_to_engine;
-        struct stedma40_chan_cfg engine_to_mem;
-};
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h
deleted file mode 100644
index c01ef66537f3..000000000000
--- a/arch/arm/mach-ux500/include/mach/gpio.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index c6e2db9e9e51..9c42642ab168 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -41,43 +41,29 @@ static inline bool __attribute_const__ cpu_is_u8500(void)
        return dbx500_partnumber() == 0x8500;
 }
-static inline bool __attribute_const__ cpu_is_u9540(void)
+static inline bool __attribute_const__ cpu_is_u8520(void)
 {
-        return dbx500_partnumber() == 0x9540;
+        return dbx500_partnumber() == 0x8520;
 }
 static inline bool cpu_is_u8500_family(void)
 {
-        return cpu_is_u8500() || cpu_is_u9540();
+        return cpu_is_u8500() || cpu_is_u8520();
-}
-static inline bool __attribute_const__ cpu_is_u5500(void)
-{
-        return dbx500_partnumber() == 0x5500;
-}
-/*
- * 5500 revisions
- */
-static inline bool __attribute_const__ cpu_is_u5500v1(void)
-{
-        return cpu_is_u5500() && (dbx500_revision() & 0xf0) == 0xA0;
 }
-static inline bool __attribute_const__ cpu_is_u5500v2(void)
+static inline bool __attribute_const__ cpu_is_u9540(void)
 {
-        return (dbx500_id.revision & 0xf0) == 0xB0;
+        return dbx500_partnumber() == 0x9540;
 }
-static inline bool __attribute_const__ cpu_is_u5500v20(void)
+static inline bool __attribute_const__ cpu_is_u8540(void)
 {
-        return cpu_is_u5500() && ((dbx500_revision() & 0xf0) == 0xB0);
+        return dbx500_partnumber() == 0x8540;
 }
-static inline bool __attribute_const__ cpu_is_u5500v21(void)
+static inline bool cpu_is_ux540_family(void)
 {
-        return cpu_is_u5500() && (dbx500_revision() == 0xB1);
+        return cpu_is_u9540() || cpu_is_u8540();
 }
 /*
@@ -119,14 +105,14 @@ static inline bool cpu_is_u8500v21(void)
        return cpu_is_u8500() && (dbx500_revision() == 0xB1);
 }
+static inline bool cpu_is_u8500v22(void)
+{
+        return cpu_is_u8500() && (dbx500_revision() == 0xB2);
+}
 static inline bool cpu_is_u8500v20_or_later(void)
 {
-        /*
+        return (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
-         * U9540 has so much in common with U8500 that is is considered a
-         * U8500 variant.
-         */
-        return cpu_is_u9540() ||
-                (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
 }
 static inline bool ux500_is_svp(void)
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h
index 798be19129ef..3cc7142eee02 100644
--- a/arch/arm/mach-ux500/include/mach/msp.h
+++ b/arch/arm/mach-ux500/include/mach/msp.h
@@ -22,8 +22,6 @@ struct msp_i2s_platform_data {
        enum msp_i2s_id id;
        struct stedma40_chan_cfg *msp_i2s_dma_rx;
        struct stedma40_chan_cfg *msp_i2s_dma_tx;
-        int (*msp_i2s_init) (void);
-        int (*msp_i2s_exit) (void);
 };
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index 7914e5eaa9c7..6be4c4d2ab88 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -45,4 +45,7 @@ extern struct sys_timer ux500_timer;
        .type           = MT_MEMORY,            \
 }
+extern struct smp_operations ux500_smp_ops;
+extern void ux500_cpu_die(unsigned int cpu);
 #endif /*  __ASM_ARCH_SETUP_H */
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 34775baadaea..d60ecd1753f0 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -24,7 +24,7 @@
 #include <linux/amba/serial.h>
 #include <mach/hardware.h>
-u32 ux500_uart_base;
+void __iomem *ux500_uart_base;
 static void putc(const char c)
 {
@@ -51,7 +51,7 @@ static void flush(void)
 static inline void arch_decomp_setup(void)
 {
        /* Use machine_is_foo() macro if you need to switch base someday */
-        ux500_uart_base = U8500_UART2_BASE;
+        ux500_uart_base = (void __iomem *)U8500_UART2_BASE;
 }
 #define arch_decomp_wdog() /* nothing to do here */
diff --git a/arch/arm/mach-ux500/include/mach/usb.h b/arch/arm/mach-ux500/include/mach/usb.h
deleted file mode 100644
index 4c1cc50a595a..000000000000
--- a/arch/arm/mach-ux500/include/mach/usb.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2011
- *
- * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
- * License terms: GNU General Public License (GPL) version 2
- */
-#ifndef __ASM_ARCH_USB_H
-#define __ASM_ARCH_USB_H
-#include <linux/dmaengine.h>
-#define UX500_MUSB_DMA_NUM_RX_CHANNELS 8
-#define UX500_MUSB_DMA_NUM_TX_CHANNELS 8
-struct ux500_musb_board_data {
-        void    **dma_rx_param_array;
-        void    **dma_tx_param_array;
-        u32     num_rx_channels;
-        u32     num_tx_channels;
-        bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
-};
-void ux500_add_usb(struct device *parent, resource_size_t base,
-                   int irq, int *dma_rx_cfg, int *dma_tx_cfg);
-#endif
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index da1d5ad5bd45..3db7782f3afb 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -28,12 +28,6 @@
 extern void u8500_secondary_startup(void);
 /*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-volatile int pen_release = -1;
-/*
 * Write pen_release in a way that is guaranteed to be visible to all
 * observers, irrespective of whether they're taking part in coherency
 * or not.  This is necessary for the hotplug code to work reliably.
@@ -48,7 +42,7 @@ static void write_pen_release(int val)
 static void __iomem *scu_base_addr(void)
 {
-        if (cpu_is_u8500_family())
+        if (cpu_is_u8500_family() || cpu_is_ux540_family())
                return __io_address(U8500_SCU_BASE);
        else
                ux500_unknown_soc();
@@ -58,7 +52,7 @@ static void __iomem *scu_base_addr(void)
 static DEFINE_SPINLOCK(boot_lock);
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit ux500_secondary_init(unsigned int cpu)
 {
        /*
         * if any interrupts are already enabled for the primary
@@ -80,7 +74,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
        spin_unlock(&boot_lock);
 }
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        unsigned long timeout;
@@ -118,7 +112,7 @@ static void __init wakeup_secondary(void)
 {
        void __iomem *backupram;
-        if (cpu_is_u8500_family())
+        if (cpu_is_u8500_family() || cpu_is_ux540_family())
                backupram = __io_address(U8500_BACKUPRAM0_BASE);
        else
                ux500_unknown_soc();
@@ -145,7 +139,7 @@ static void __init wakeup_secondary(void)
 * Initialise the CPU possible map early - this describes the CPUs
 * which may be present or become present in the system.
 */
-void __init smp_init_cpus(void)
+static void __init ux500_smp_init_cpus(void)
 {
        void __iomem *scu_base = scu_base_addr();
        unsigned int i, ncores;
@@ -165,9 +159,19 @@ void __init smp_init_cpus(void)
        set_smp_cross_call(gic_raise_softirq);
 }
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
 {
        scu_enable(scu_base_addr());
        wakeup_secondary();
 }
+struct smp_operations ux500_smp_ops __initdata = {
+        .smp_init_cpus          = ux500_smp_init_cpus,
+        .smp_prepare_cpus       = ux500_smp_prepare_cpus,
+        .smp_secondary_init     = ux500_secondary_init,
+        .smp_boot_secondary     = ux500_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = ux500_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 66e7f00884ab..6f39731951b0 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -54,7 +54,7 @@ static void __init ux500_timer_init(void)
        void __iomem *tmp_base;
        struct device_node *np;
-        if (cpu_is_u8500_family()) {
+        if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
                mtu_timer_base = __io_address(U8500_MTU0_BASE);
                prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
        } else {
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index a74af389bc63..145482e74418 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -10,7 +10,7 @@
 #include <plat/ste_dma40.h>
 #include <mach/hardware.h>
-#include <mach/usb.h>
+#include <linux/platform_data/usb-musb-ux500.h>
 #define MUSB_DMA40_RX_CH { \
                .mode = STEDMA40_MODE_LOGICAL, \
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index cd8ea3588f93..5b5c1eeb5b5c 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -37,7 +37,6 @@
 #include <linux/mtd/physmap.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst.h>
 #include <asm/hardware/vic.h>
@@ -169,11 +168,6 @@ static struct map_desc versatile_io_desc[] __initdata = {
                .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
                .length         = VERSATILE_PCI_CFG_BASE_SIZE,
                .type           = MT_DEVICE
-        }, {
-                .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_MEM_BASE0,
-                .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
-                .length         = IO_SPACE_LIMIT,
-                .type           = MT_DEVICE
        },
 #endif
 };
@@ -763,10 +757,6 @@ void __init versatile_init(void)
                struct amba_device *d = amba_devs[i];
                amba_device_register(d, &iomem_resource);
        }
-#ifdef CONFIG_LEDS
-        leds_event = versatile_leds_event;
-#endif
 }
 /*
diff --git a/arch/arm/mach-versatile/include/mach/gpio.h b/arch/arm/mach-versatile/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-versatile/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h
index 408e58da46c6..3e5d425e2a92 100644
--- a/arch/arm/mach-versatile/include/mach/hardware.h
+++ b/arch/arm/mach-versatile/include/mach/hardware.h
@@ -29,7 +29,6 @@
 */
 #define VERSATILE_PCI_VIRT_BASE         (void __iomem *)0xe8000000ul
 #define VERSATILE_PCI_CFG_VIRT_BASE     (void __iomem *)0xe9000000ul
-#define VERSATILE_PCI_VIRT_MEM_BASE0    (void __iomem *)PCIO_BASE
 /* macro to get at MMIO space when running virtually */
 #define IO_ADDRESS(x)           (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h
deleted file mode 100644
index 0406513be7d8..000000000000
--- a/arch/arm/mach-versatile/include/mach/io.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *  arch/arm/mach-versatile/include/mach/io.h
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-#define PCIO_BASE       0xeb000000ul
-#define __io(a)         ((a) + PCIO_BASE)
-#endif
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index e95bf84cc837..2f84f4094f13 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -169,13 +169,6 @@ static struct pci_ops pci_versatile_ops = {
        .write  = versatile_write_config,
 };
-static struct resource io_port = {
-        .name   = "PCI",
-        .start  = 0,
-        .end    = IO_SPACE_LIMIT,
-        .flags  = IORESOURCE_IO,
-};
 static struct resource io_mem = {
        .name   = "PCI I/O space",
        .start  = VERSATILE_PCI_MEM_BASE0,
@@ -207,12 +200,6 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
                       "memory region (%d)\n", ret);
                goto out;
        }
-        ret = request_resource(&ioport_resource, &io_port);
-        if (ret) {
-                printk(KERN_ERR "PCI: unable to allocate I/O "
-                       "port region (%d)\n", ret);
-                goto out;
-        }
        ret = request_resource(&iomem_resource, &non_mem);
        if (ret) {
                printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
@@ -227,11 +214,9 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
        }
        /*
-         * the IO resource for this bus
         * the mem resource for this bus
         * the prefetch mem resource for this bus
         */
-        pci_add_resource_offset(&sys->resources, &io_port, sys->io_offset);
        pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
        pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
@@ -260,9 +245,11 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
                goto out;
        }
+        ret = pci_ioremap_io(0, VERSATILE_PCI_MEM_BASE0);
+        if (ret)
+                goto out;
        if (nr == 0) {
-                sys->mem_offset = 0;
-                sys->io_offset = 0;
                ret = pci_versatile_setup_resources(sys);
                if (ret < 0) {
                        printk("pci_versatile_setup: resources... oops?\n");
@@ -319,7 +306,6 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 void __init pci_versatile_preinit(void)
 {
-        pcibios_min_io = 0x44000000;
        pcibios_min_mem = 0x50000000;
        __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index fc3730f01650..c95296066203 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,38 +1,23 @@
-menu "Versatile Express platform type"
+config ARCH_VEXPRESS
-        depends on ARCH_VEXPRESS
+        bool "ARM Ltd. Versatile Express family" if ARCH_MULTI_V7
+        select ARCH_WANT_OPTIONAL_GPIOLIB
-config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
+        select ARM_AMBA
-        bool "Enable A5 and A9 only errata work-arounds"
-        default y
-        select ARM_ERRATA_720789
-        select ARM_ERRATA_751472
-        select PL310_ERRATA_753970 if CACHE_PL310
-        help
-          Provides common dependencies for Versatile Express platforms
-          based on Cortex-A5 and Cortex-A9 processors. In order to
-          build a working kernel, you must also enable relevant core
-          tile support or Flattened Device Tree based support options.
-config ARCH_VEXPRESS_CA9X4
-        bool "Versatile Express Cortex-A9x4 tile"
-        select ARM_GIC
-        select CPU_V7
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
-config ARCH_VEXPRESS_DT
-        bool "Device Tree support for Versatile Express platforms"
        select ARM_GIC
-        select ARM_PATCH_PHYS_VIRT
+        select ARM_TIMER_SP804
-        select AUTO_ZRELADDR
+        select CLKDEV_LOOKUP
+        select COMMON_CLK
        select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select HAVE_CLK
+        select HAVE_PATA_PLATFORM
        select HAVE_SMP
+        select ICST
        select MIGHT_HAVE_CACHE_L2X0
-        select USE_OF
+        select NO_IOPORT
+        select PLAT_VERSATILE
+        select PLAT_VERSATILE_CLCD
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
        help
-          New Versatile Express platforms require Flattened Device Tree to
-          be passed to the kernel.
          This option enables support for systems using Cortex processor based
          ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
          for example:
@@ -48,7 +33,22 @@ config ARCH_VEXPRESS_DT
          platforms. The traditional (ATAGs) boot method is not usable on
          these boards with this option.
-          If your bootloader supports Flattened Device Tree based booting,
+menu "Versatile Express platform type"
-          say Y here.
+        depends on ARCH_VEXPRESS
+config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
+        bool "Enable A5 and A9 only errata work-arounds"
+        default y
+        select ARM_ERRATA_720789
+        select ARM_ERRATA_751472
+        select PL310_ERRATA_753970 if CACHE_PL310
+        help
+          Provides common dependencies for Versatile Express platforms
+          based on Cortex-A5 and Cortex-A9 processors. In order to
+          build a working kernel, you must also enable relevant core
+          tile support or Flattened Device Tree based support options.
+config ARCH_VEXPRESS_CA9X4
+        bool "Versatile Express Cortex-A9x4 tile"
 endmenu
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 90551b9780ab..42703e8b4d3b 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -1,6 +1,8 @@
 #
 # Makefile for the linux kernel.
 #
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+        -I$(srctree)/arch/arm/plat-versatile/include
 obj-y                                   := v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)       += ct-ca9x4.o
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
deleted file mode 100644
index 318d308dfb93..000000000000
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ /dev/null
@@ -1,10 +0,0 @@
-# Those numbers are used only by the non-DT V2P-CA9 platform
-# The DT-enabled ones require CONFIG_AUTO_ZRELADDR=y
-   zreladdr-y   += 0x60008000
-params_phys-y   := 0x60000100
-initrd_phys-y   := 0x60800000
-dtb-$(CONFIG_ARCH_VEXPRESS_DT)  += vexpress-v2p-ca5s.dtb \
-                                   vexpress-v2p-ca9.dtb \
-                                   vexpress-v2p-ca15-tc1.dtb \
-                                   vexpress-v2p-ca15_a7.dtb
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index a3a4980770bd..f134cd4a85f1 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -5,3 +5,7 @@
 #define V2T_PERIPH 0xf8200000
 void vexpress_dt_smp_map_io(void);
+extern struct smp_operations    vexpress_smp_ops;
+extern void vexpress_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 61c492403b05..4f471fa3e3c5 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -13,7 +13,6 @@
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
-#include <asm/pmu.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
@@ -27,6 +26,7 @@
 #include "core.h"
 #include <mach/motherboard.h>
+#include <mach/irqs.h>
 #include <plat/clcd.h>
@@ -144,7 +144,7 @@ static struct resource pmu_resources[] = {
 static struct platform_device pmu_device = {
        .name           = "arm-pmu",
-        .id             = ARM_PMU_DEVICE_CPU,
+        .id             = -1,
        .num_resources  = ARRAY_SIZE(pmu_resources),
        .resource       = pmu_resources,
 };
diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c
index c504a72b94d6..a141b98d84fe 100644
--- a/arch/arm/mach-vexpress/hotplug.c
+++ b/arch/arm/mach-vexpress/hotplug.c
@@ -16,8 +16,6 @@
 #include <asm/smp_plat.h>
 #include <asm/cp15.h>
-extern volatile int pen_release;
 static inline void cpu_enter_lowpower(void)
 {
        unsigned int v;
@@ -84,17 +82,12 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
        }
 }
-int platform_cpu_kill(unsigned int cpu)
-{
-        return 1;
-}
 /*
 * platform-specific code to shutdown a CPU
 *
 * Called with IRQs disabled
 */
-void platform_cpu_die(unsigned int cpu)
+void __ref vexpress_cpu_die(unsigned int cpu)
 {
        int spurious = 0;
@@ -113,12 +106,3 @@ void platform_cpu_die(unsigned int cpu)
        if (spurious)
                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 }
-int platform_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
diff --git a/arch/arm/mach-vexpress/include/mach/gpio.h b/arch/arm/mach-vexpress/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-vexpress/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-vexpress/include/mach/irqs.h b/arch/arm/mach-vexpress/include/mach/irqs.h
index 4b10ee7657a6..f8f7f782eb55 100644
--- a/arch/arm/mach-vexpress/include/mach/irqs.h
+++ b/arch/arm/mach-vexpress/include/mach/irqs.h
@@ -1,4 +1,6 @@
 #define IRQ_LOCALTIMER          29
 #define IRQ_LOCALWDOG           30
+#ifndef CONFIG_SPARSE_IRQ
 #define NR_IRQS 256
+#endif
diff --git a/arch/arm/mach-vexpress/include/mach/timex.h b/arch/arm/mach-vexpress/include/mach/timex.h
deleted file mode 100644
index 00029bacd43c..000000000000
--- a/arch/arm/mach-vexpress/include/mach/timex.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- *  arch/arm/mach-vexpress/include/mach/timex.h
- *
- *  RealView architecture timex specifications
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
deleted file mode 100644
index 1e472eb0bbdc..000000000000
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- *  arch/arm/mach-vexpress/include/mach/uncompress.h
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define AMBA_UART_DR(base)      (*(volatile unsigned char *)((base) + 0x00))
-#define AMBA_UART_LCRH(base)    (*(volatile unsigned char *)((base) + 0x2c))
-#define AMBA_UART_CR(base)      (*(volatile unsigned char *)((base) + 0x30))
-#define AMBA_UART_FR(base)      (*(volatile unsigned char *)((base) + 0x18))
-#define UART_BASE       0x10009000
-#define UART_BASE_RS1   0x1c090000
-static unsigned long get_uart_base(void)
-{
-#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
-        unsigned long mpcore_periph;
-        /*
-         * Make an educated guess regarding the memory map:
-         * - the original A9 core tile, which has MPCore peripherals
-         *   located at 0x1e000000, should use UART at 0x10009000
-         * - all other (RS1 complaint) tiles use UART mapped
-         *   at 0x1c090000
-         */
-        asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (mpcore_periph));
-        if (mpcore_periph == 0x1e000000)
-                return UART_BASE;
-        else
-                return UART_BASE_RS1;
-#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
-        return UART_BASE;
-#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
-        return UART_BASE_RS1;
-#else
-        return 0;
-#endif
-}
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-        unsigned long base = get_uart_base();
-        if (!base)
-                return;
-        while (AMBA_UART_FR(base) & (1 << 5))
-                barrier();
-        AMBA_UART_DR(base) = c;
-}
-static inline void flush(void)
-{
-        unsigned long base = get_uart_base();
-        if (!base)
-                return;
-        while (AMBA_UART_FR(base) & (1 << 3))
-                barrier();
-}
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 14ba1128ae8d..7db27c8c05cc 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -20,9 +20,9 @@
 #include <mach/motherboard.h>
-#include "core.h"
+#include <plat/platsmp.h>
-extern void versatile_secondary_startup(void);
+#include "core.h"
 #if defined(CONFIG_OF)
@@ -167,7 +167,7 @@ void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
 * Initialise the CPU possible map early - this describes the CPUs
 * which may be present or become present in the system.
 */
-void __init smp_init_cpus(void)
+static void __init vexpress_smp_init_cpus(void)
 {
        if (ct_desc)
                ct_desc->init_cpu_map();
@@ -176,7 +176,7 @@ void __init smp_init_cpus(void)
 }
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init vexpress_smp_prepare_cpus(unsigned int max_cpus)
 {
        /*
         * Initialise the present map, which describes the set of CPUs
@@ -195,3 +195,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
         */
        v2m_flags_set(virt_to_phys(versatile_secondary_startup));
 }
+struct smp_operations __initdata vexpress_smp_ops = {
+        .smp_init_cpus          = vexpress_smp_init_cpus,
+        .smp_prepare_cpus       = vexpress_smp_prepare_cpus,
+        .smp_secondary_init     = versatile_secondary_init,
+        .smp_boot_secondary     = versatile_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = vexpress_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 37608f22ee31..560e0df728f8 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -5,6 +5,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
+#include <linux/smp.h>
 #include <linux/init.h>
 #include <linux/of_address.h>
 #include <linux/of_fdt.h>
@@ -38,6 +39,7 @@
 #include <mach/motherboard.h>
 #include <plat/sched_clock.h>
+#include <plat/platsmp.h>
 #include "core.h"
@@ -530,6 +532,7 @@ static void __init v2m_init(void)
 MACHINE_START(VEXPRESS, "ARM-Versatile Express")
        .atag_offset    = 0x100,
+        .smp            = smp_ops(vexpress_smp_ops),
        .map_io         = v2m_map_io,
        .init_early     = v2m_init_early,
        .init_irq       = v2m_init_irq,
@@ -539,8 +542,6 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
        .restart        = v2m_restart,
 MACHINE_END
-#if defined(CONFIG_ARCH_VEXPRESS_DT)
 static struct map_desc v2m_rs1_io_desc __initdata = {
        .virtual        = V2M_PERIPH,
        .pfn            = __phys_to_pfn(0x1c000000),
@@ -658,11 +659,13 @@ static void __init v2m_dt_init(void)
 const static char *v2m_dt_match[] __initconst = {
        "arm,vexpress",
+        "xen,xenvm",
        NULL,
 };
 DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
        .dt_compat      = v2m_dt_match,
+        .smp            = smp_ops(vexpress_smp_ops),
        .map_io         = v2m_dt_map_io,
        .init_early     = v2m_dt_init_early,
        .init_irq       = v2m_dt_init_irq,
@@ -671,5 +674,3 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
        .handle_irq     = gic_handle_irq,
        .restart        = v2m_restart,
 MACHINE_END
-#endif
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
deleted file mode 100644
index 2c20a341c11a..000000000000
--- a/arch/arm/mach-vt8500/Kconfig
+++ /dev/null
@@ -1,73 +0,0 @@
-if ARCH_VT8500
-config VTWM_VERSION_VT8500
-        bool
-config VTWM_VERSION_WM8505
-        bool
-config MACH_BV07
-        bool "Benign BV07-8500 Mini Netbook"
-        depends on ARCH_VT8500
-        select VTWM_VERSION_VT8500
-        help
-          Add support for the inexpensive 7-inch netbooks sold by many
-          Chinese distributors under various names. Note that there are
-          many hardware implementations in identical exterior, make sure
-          that yours is indeed based on a VIA VT8500 chip.
-config MACH_WM8505_7IN_NETBOOK
-        bool "WM8505 7-inch generic netbook"
-        depends on ARCH_VT8500
-        select VTWM_VERSION_WM8505
-        help
-          Add support for the inexpensive 7-inch netbooks sold by many
-          Chinese distributors under various names. Note that there are
-          many hardware implementations in identical exterior, make sure
-          that yours is indeed based on a WonderMedia WM8505 chip.
-comment "LCD panel size"
-config WMT_PANEL_800X480
-        bool "7-inch with 800x480 resolution"
-        depends on (FB_VT8500 || FB_WM8505)
-        default y
-        help
-          These are found in most of the netbooks in generic cases, as
-          well as in Eken M001 tablets and possibly elsewhere.
-          To select this panel at runtime, say y here and append
-          'panel=800x480' to your kernel command line. Otherwise, the
-          largest one available will be used.
-config WMT_PANEL_800X600
-        bool "8-inch with 800x600 resolution"
-        depends on (FB_VT8500 || FB_WM8505)
-        help
-          These are found in Eken M003 tablets and possibly elsewhere.
-          To select this panel at runtime, say y here and append
-          'panel=800x600' to your kernel command line. Otherwise, the
-          largest one available will be used.
-config WMT_PANEL_1024X576
-        bool "10-inch with 1024x576 resolution"
-        depends on (FB_VT8500 || FB_WM8505)
-        help
-          These are found in CherryPal netbooks and possibly elsewhere.
-          To select this panel at runtime, say y here and append
-          'panel=1024x576' to your kernel command line. Otherwise, the
-          largest one available will be used.
-config WMT_PANEL_1024X600
-        bool "10-inch with 1024x600 resolution"
-        depends on (FB_VT8500 || FB_WM8505)
-        help
-          These are found in Eken M006 tablets and possibly elsewhere.
-          To select this panel at runtime, say y here and append
-          'panel=1024x600' to your kernel command line. Otherwise, the
-          largest one available will be used.
-endif
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index 7ce51767c99c..e035251cda48 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -1,7 +1 @@
-obj-y += devices.o gpio.o irq.o timer.o restart.o
+obj-$(CONFIG_ARCH_VT8500) += irq.o timer.o vt8500.o
-obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o
-obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o
-obj-$(CONFIG_MACH_BV07) += bv07.o
-obj-$(CONFIG_MACH_WM8505_7IN_NETBOOK) += wm8505_7in.o
diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c
deleted file mode 100644
index f9fbeb2d10e9..000000000000
--- a/arch/arm/mach-vt8500/bv07.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/bv07.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/io.h>
-#include <linux/pm.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/restart.h>
-#include "devices.h"
-static void __iomem *pmc_hiber;
-static struct platform_device *devices[] __initdata = {
-        &vt8500_device_uart0,
-        &vt8500_device_lcdc,
-        &vt8500_device_ehci,
-        &vt8500_device_ge_rops,
-        &vt8500_device_pwm,
-        &vt8500_device_pwmbl,
-        &vt8500_device_rtc,
-};
-static void vt8500_power_off(void)
-{
-        local_irq_disable();
-        writew(5, pmc_hiber);
-        asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
-}
-void __init bv07_init(void)
-{
-#ifdef CONFIG_FB_VT8500
-        void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4);
-        if (gpio_mux_reg) {
-                writel(readl(gpio_mux_reg) | 1, gpio_mux_reg);
-                iounmap(gpio_mux_reg);
-        } else {
-                printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n");
-        }
-#endif
-        pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2);
-        if (pmc_hiber)
-                pm_power_off = &vt8500_power_off;
-        else
-                printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-        wmt_setup_restart();
-        vt8500_set_resources();
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-        vt8500_gpio_init();
-}
-MACHINE_START(BV07, "Benign BV07 Mini Netbook")
-        .atag_offset    = 0x100,
-        .restart        = wmt_restart,
-        .reserve        = vt8500_reserve_mem,
-        .map_io         = vt8500_map_io,
-        .init_irq       = vt8500_init_irq,
-        .timer          = &vt8500_timer,
-        .init_machine   = bv07_init,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/include/mach/gpio-tegra.h b/arch/arm/mach-vt8500/common.h
index a978b3cc3a8d..2b2419646e95 100644
--- a/arch/arm/mach-tegra/include/mach/gpio-tegra.h
+++ b/arch/arm/mach-vt8500/common.h
@@ -1,10 +1,6 @@
-/*
+/* linux/arch/arm/mach-vt8500/dt_common.h
- * arch/arm/mach-tegra/include/mach/gpio.h
 *
- * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
- *
- * Author:
- *      Erik Gilling <konkers@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -17,12 +13,16 @@
 *
 */
-#ifndef __MACH_TEGRA_GPIO_TEGRA_H
+#ifndef __ARCH_ARM_MACH_VT8500_DT_COMMON_H
-#define __MACH_TEGRA_GPIO_TEGRA_H
+#define __ARCH_ARM_MACH_VT8500_DT_COMMON_H
+#include <linux/of.h>
-#include <linux/types.h>
+void __init vt8500_timer_init(void);
-#include <mach/irqs.h>
+int __init vt8500_irq_init(struct device_node *node,
+                                struct device_node *parent);
-#define TEGRA_NR_GPIOS          INT_GPIO_NR
+/* defined in drivers/clk/clk-vt8500.c */
+void __init vtwm_clk_init(void __iomem *pmc_base);
 #endif
diff --git a/arch/arm/mach-vt8500/devices-vt8500.c b/arch/arm/mach-vt8500/devices-vt8500.c
deleted file mode 100644
index 19519aeecf37..000000000000
--- a/arch/arm/mach-vt8500/devices-vt8500.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices-vt8500.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/platform_device.h>
-#include <mach/vt8500_regs.h>
-#include <mach/vt8500_irqs.h>
-#include <mach/i8042.h>
-#include "devices.h"
-void __init vt8500_set_resources(void)
-{
-        struct resource tmp[3];
-        tmp[0] = wmt_mmio_res(VT8500_LCDC_BASE, SZ_1K);
-        tmp[1] = wmt_irq_res(IRQ_LCDC);
-        wmt_res_add(&vt8500_device_lcdc, tmp, 2);
-        tmp[0] = wmt_mmio_res(VT8500_UART0_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART0);
-        wmt_res_add(&vt8500_device_uart0, tmp, 2);
-        tmp[0] = wmt_mmio_res(VT8500_UART1_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART1);
-        wmt_res_add(&vt8500_device_uart1, tmp, 2);
-        tmp[0] = wmt_mmio_res(VT8500_UART2_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART2);
-        wmt_res_add(&vt8500_device_uart2, tmp, 2);
-        tmp[0] = wmt_mmio_res(VT8500_UART3_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART3);
-        wmt_res_add(&vt8500_device_uart3, tmp, 2);
-        tmp[0] = wmt_mmio_res(VT8500_EHCI_BASE, SZ_512);
-        tmp[1] = wmt_irq_res(IRQ_EHCI);
-        wmt_res_add(&vt8500_device_ehci, tmp, 2);
-        tmp[0] = wmt_mmio_res(VT8500_GEGEA_BASE, SZ_256);
-        wmt_res_add(&vt8500_device_ge_rops, tmp, 1);
-        tmp[0] = wmt_mmio_res(VT8500_PWM_BASE, 0x44);
-        wmt_res_add(&vt8500_device_pwm, tmp, 1);
-        tmp[0] = wmt_mmio_res(VT8500_RTC_BASE, 0x2c);
-        tmp[1] = wmt_irq_res(IRQ_RTC);
-        tmp[2] = wmt_irq_res(IRQ_RTCSM);
-        wmt_res_add(&vt8500_device_rtc, tmp, 3);
-}
-static void __init vt8500_set_externs(void)
-{
-        /* Non-resource-aware stuff */
-        wmt_ic_base = VT8500_IC_BASE;
-        wmt_gpio_base = VT8500_GPIO_BASE;
-        wmt_pmc_base = VT8500_PMC_BASE;
-        wmt_i8042_base = VT8500_PS2_BASE;
-        wmt_nr_irqs = VT8500_NR_IRQS;
-        wmt_timer_irq = IRQ_PMCOS0;
-        wmt_gpio_ext_irq[0] = IRQ_EXT0;
-        wmt_gpio_ext_irq[1] = IRQ_EXT1;
-        wmt_gpio_ext_irq[2] = IRQ_EXT2;
-        wmt_gpio_ext_irq[3] = IRQ_EXT3;
-        wmt_gpio_ext_irq[4] = IRQ_EXT4;
-        wmt_gpio_ext_irq[5] = IRQ_EXT5;
-        wmt_gpio_ext_irq[6] = IRQ_EXT6;
-        wmt_gpio_ext_irq[7] = IRQ_EXT7;
-        wmt_i8042_kbd_irq = IRQ_PS2KBD;
-        wmt_i8042_aux_irq = IRQ_PS2MOUSE;
-}
-void __init vt8500_map_io(void)
-{
-        iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-        /* Should be done before interrupts and timers are initialized */
-        vt8500_set_externs();
-}
diff --git a/arch/arm/mach-vt8500/devices-wm8505.c b/arch/arm/mach-vt8500/devices-wm8505.c
deleted file mode 100644
index db4594e029f4..000000000000
--- a/arch/arm/mach-vt8500/devices-wm8505.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices-wm8505.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/platform_device.h>
-#include <mach/wm8505_regs.h>
-#include <mach/wm8505_irqs.h>
-#include <mach/i8042.h>
-#include "devices.h"
-void __init wm8505_set_resources(void)
-{
-        struct resource tmp[3];
-        tmp[0] = wmt_mmio_res(WM8505_GOVR_BASE, SZ_512);
-        wmt_res_add(&vt8500_device_wm8505_fb, tmp, 1);
-        tmp[0] = wmt_mmio_res(WM8505_UART0_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART0);
-        wmt_res_add(&vt8500_device_uart0, tmp, 2);
-        tmp[0] = wmt_mmio_res(WM8505_UART1_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART1);
-        wmt_res_add(&vt8500_device_uart1, tmp, 2);
-        tmp[0] = wmt_mmio_res(WM8505_UART2_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART2);
-        wmt_res_add(&vt8500_device_uart2, tmp, 2);
-        tmp[0] = wmt_mmio_res(WM8505_UART3_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART3);
-        wmt_res_add(&vt8500_device_uart3, tmp, 2);
-        tmp[0] = wmt_mmio_res(WM8505_UART4_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART4);
-        wmt_res_add(&vt8500_device_uart4, tmp, 2);
-        tmp[0] = wmt_mmio_res(WM8505_UART5_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART5);
-        wmt_res_add(&vt8500_device_uart5, tmp, 2);
-        tmp[0] = wmt_mmio_res(WM8505_EHCI_BASE, SZ_512);
-        tmp[1] = wmt_irq_res(IRQ_EHCI);
-        wmt_res_add(&vt8500_device_ehci, tmp, 2);
-        tmp[0] = wmt_mmio_res(WM8505_GEGEA_BASE, SZ_256);
-        wmt_res_add(&vt8500_device_ge_rops, tmp, 1);
-        tmp[0] = wmt_mmio_res(WM8505_PWM_BASE, 0x44);
-        wmt_res_add(&vt8500_device_pwm, tmp, 1);
-        tmp[0] = wmt_mmio_res(WM8505_RTC_BASE, 0x2c);
-        tmp[1] = wmt_irq_res(IRQ_RTC);
-        tmp[2] = wmt_irq_res(IRQ_RTCSM);
-        wmt_res_add(&vt8500_device_rtc, tmp, 3);
-}
-static void __init wm8505_set_externs(void)
-{
-        /* Non-resource-aware stuff */
-        wmt_ic_base = WM8505_IC_BASE;
-        wmt_sic_base = WM8505_SIC_BASE;
-        wmt_gpio_base = WM8505_GPIO_BASE;
-        wmt_pmc_base = WM8505_PMC_BASE;
-        wmt_i8042_base = WM8505_PS2_BASE;
-        wmt_nr_irqs = WM8505_NR_IRQS;
-        wmt_timer_irq = IRQ_PMCOS0;
-        wmt_gpio_ext_irq[0] = IRQ_EXT0;
-        wmt_gpio_ext_irq[1] = IRQ_EXT1;
-        wmt_gpio_ext_irq[2] = IRQ_EXT2;
-        wmt_gpio_ext_irq[3] = IRQ_EXT3;
-        wmt_gpio_ext_irq[4] = IRQ_EXT4;
-        wmt_gpio_ext_irq[5] = IRQ_EXT5;
-        wmt_gpio_ext_irq[6] = IRQ_EXT6;
-        wmt_gpio_ext_irq[7] = IRQ_EXT7;
-        wmt_i8042_kbd_irq = IRQ_PS2KBD;
-        wmt_i8042_aux_irq = IRQ_PS2MOUSE;
-}
-void __init wm8505_map_io(void)
-{
-        iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-        /* Should be done before interrupts and timers are initialized */
-        wm8505_set_externs();
-}
diff --git a/arch/arm/mach-vt8500/devices.c b/arch/arm/mach-vt8500/devices.c
deleted file mode 100644
index 1fcdc36b358d..000000000000
--- a/arch/arm/mach-vt8500/devices.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/pwm_backlight.h>
-#include <linux/memblock.h>
-#include <asm/mach/arch.h>
-#include <mach/vt8500fb.h>
-#include <mach/i8042.h>
-#include "devices.h"
-/* These can't use resources currently */
-unsigned long wmt_ic_base __initdata;
-unsigned long wmt_sic_base __initdata;
-unsigned long wmt_gpio_base __initdata;
-unsigned long wmt_pmc_base __initdata;
-unsigned long wmt_i8042_base __initdata;
-int wmt_nr_irqs __initdata;
-int wmt_timer_irq __initdata;
-int wmt_gpio_ext_irq[8] __initdata;
-/* Should remain accessible after init.
- * i8042 driver desperately calls for attention...
- */
-int wmt_i8042_kbd_irq;
-int wmt_i8042_aux_irq;
-static u64 fb_dma_mask = DMA_BIT_MASK(32);
-struct platform_device vt8500_device_lcdc = {
-        .name           = "vt8500-lcd",
-        .id             = 0,
-        .dev            = {
-                .dma_mask       = &fb_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-struct platform_device vt8500_device_wm8505_fb = {
-        .name           = "wm8505-fb",
-        .id             = 0,
-};
-/* Smallest to largest */
-static struct vt8500fb_platform_data panels[] = {
-#ifdef CONFIG_WMT_PANEL_800X480
-{
-        .xres_virtual   = 800,
-        .yres_virtual   = 480 * 2,
-        .mode           = {
-                .name           = "800x480",
-                .xres           = 800,
-                .yres           = 480,
-                .left_margin    = 88,
-                .right_margin   = 40,
-                .upper_margin   = 32,
-                .lower_margin   = 11,
-                .hsync_len      = 0,
-                .vsync_len      = 1,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_800X600
-{
-        .xres_virtual   = 800,
-        .yres_virtual   = 600 * 2,
-        .mode           = {
-                .name           = "800x600",
-                .xres           = 800,
-                .yres           = 600,
-                .left_margin    = 88,
-                .right_margin   = 40,
-                .upper_margin   = 32,
-                .lower_margin   = 11,
-                .hsync_len      = 0,
-                .vsync_len      = 1,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_1024X576
-{
-        .xres_virtual   = 1024,
-        .yres_virtual   = 576 * 2,
-        .mode           = {
-                .name           = "1024x576",
-                .xres           = 1024,
-                .yres           = 576,
-                .left_margin    = 40,
-                .right_margin   = 24,
-                .upper_margin   = 32,
-                .lower_margin   = 11,
-                .hsync_len      = 96,
-                .vsync_len      = 2,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_1024X600
-{
-        .xres_virtual   = 1024,
-        .yres_virtual   = 600 * 2,
-        .mode           = {
-                .name           = "1024x600",
-                .xres           = 1024,
-                .yres           = 600,
-                .left_margin    = 66,
-                .right_margin   = 2,
-                .upper_margin   = 19,
-                .lower_margin   = 1,
-                .hsync_len      = 23,
-                .vsync_len      = 8,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-},
-#endif
-};
-static int current_panel_idx __initdata = ARRAY_SIZE(panels) - 1;
-static int __init panel_setup(char *str)
-{
-        int i;
-        for (i = 0; i < ARRAY_SIZE(panels); i++) {
-                if (strcmp(panels[i].mode.name, str) == 0) {
-                        current_panel_idx = i;
-                        break;
-                }
-        }
-        return 0;
-}
-early_param("panel", panel_setup);
-static inline void preallocate_fb(struct vt8500fb_platform_data *p,
-                                  unsigned long align) {
-        p->video_mem_len = (p->xres_virtual * p->yres_virtual * 4) >>
-                        (p->bpp > 16 ? 0 : (p->bpp > 8 ? 1 :
-                                        (8 / p->bpp) + 1));
-        p->video_mem_phys = (unsigned long)memblock_alloc(p->video_mem_len,
-                                                          align);
-        p->video_mem_virt = phys_to_virt(p->video_mem_phys);
-}
-struct platform_device vt8500_device_uart0 = {
-        .name           = "vt8500_serial",
-        .id             = 0,
-};
-struct platform_device vt8500_device_uart1 = {
-        .name           = "vt8500_serial",
-        .id             = 1,
-};
-struct platform_device vt8500_device_uart2 = {
-        .name           = "vt8500_serial",
-        .id             = 2,
-};
-struct platform_device vt8500_device_uart3 = {
-        .name           = "vt8500_serial",
-        .id             = 3,
-};
-struct platform_device vt8500_device_uart4 = {
-        .name           = "vt8500_serial",
-        .id             = 4,
-};
-struct platform_device vt8500_device_uart5 = {
-        .name           = "vt8500_serial",
-        .id             = 5,
-};
-static u64 ehci_dma_mask = DMA_BIT_MASK(32);
-struct platform_device vt8500_device_ehci = {
-        .name           = "vt8500-ehci",
-        .id             = 0,
-        .dev            = {
-                .dma_mask       = &ehci_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-struct platform_device vt8500_device_ge_rops = {
-        .name           = "wmt_ge_rops",
-        .id             = -1,
-};
-struct platform_device vt8500_device_pwm = {
-        .name           = "vt8500-pwm",
-        .id             = 0,
-};
-static struct platform_pwm_backlight_data vt8500_pwmbl_data = {
-        .pwm_id         = 0,
-        .max_brightness = 128,
-        .dft_brightness = 70,
-        .pwm_period_ns  = 250000, /* revisit when clocks are implemented */
-};
-struct platform_device vt8500_device_pwmbl = {
-        .name           = "pwm-backlight",
-        .id             = 0,
-        .dev            = {
-                .platform_data = &vt8500_pwmbl_data,
-        },
-};
-struct platform_device vt8500_device_rtc = {
-        .name           = "vt8500-rtc",
-        .id             = 0,
-};
-struct map_desc wmt_io_desc[] __initdata = {
-        /* SoC MMIO registers */
-        [0] = {
-                .virtual        = 0xf8000000,
-                .pfn            = __phys_to_pfn(0xd8000000),
-                .length         = 0x00390000, /* max of all chip variants */
-                .type           = MT_DEVICE
-        },
-        /* PCI I/O space, numbers tied to those in <mach/io.h> */
-        [1] = {
-                .virtual        = 0xf0000000,
-                .pfn            = __phys_to_pfn(0xc0000000),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE
-        },
-};
-void __init vt8500_reserve_mem(void)
-{
-#ifdef CONFIG_FB_VT8500
-        panels[current_panel_idx].bpp = 16; /* Always use RGB565 */
-        preallocate_fb(&panels[current_panel_idx], SZ_4M);
-        vt8500_device_lcdc.dev.platform_data = &panels[current_panel_idx];
-#endif
-}
-void __init wm8505_reserve_mem(void)
-{
-#if defined CONFIG_FB_WM8505
-        panels[current_panel_idx].bpp = 32; /* Always use RGB888 */
-        preallocate_fb(&panels[current_panel_idx], 32);
-        vt8500_device_wm8505_fb.dev.platform_data = &panels[current_panel_idx];
-#endif
-}
diff --git a/arch/arm/mach-vt8500/devices.h b/arch/arm/mach-vt8500/devices.h
deleted file mode 100644
index 188d4e17f35c..000000000000
--- a/arch/arm/mach-vt8500/devices.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ARCH_ARM_MACH_VT8500_DEVICES_H
-#define __ARCH_ARM_MACH_VT8500_DEVICES_H
-#include <linux/platform_device.h>
-#include <asm/mach/map.h>
-void __init vt8500_init_irq(void);
-void __init wm8505_init_irq(void);
-void __init vt8500_map_io(void);
-void __init wm8505_map_io(void);
-void __init vt8500_reserve_mem(void);
-void __init wm8505_reserve_mem(void);
-void __init vt8500_gpio_init(void);
-void __init vt8500_set_resources(void);
-void __init wm8505_set_resources(void);
-extern unsigned long wmt_ic_base __initdata;
-extern unsigned long wmt_sic_base __initdata;
-extern unsigned long wmt_gpio_base __initdata;
-extern unsigned long wmt_pmc_base __initdata;
-extern int wmt_nr_irqs __initdata;
-extern int wmt_timer_irq __initdata;
-extern int wmt_gpio_ext_irq[8] __initdata;
-extern struct map_desc wmt_io_desc[2] __initdata;
-static inline struct resource wmt_mmio_res(u32 start, u32 size)
-{
-        struct resource tmp = {
-                .flags = IORESOURCE_MEM,
-                .start = start,
-                .end = start + size - 1,
-        };
-        return tmp;
-}
-static inline struct resource wmt_irq_res(int irq)
-{
-        struct resource tmp = {
-                .flags = IORESOURCE_IRQ,
-                .start = irq,
-                .end = irq,
-        };
-        return tmp;
-}
-static inline void wmt_res_add(struct platform_device *pdev,
-                               const struct resource *res, unsigned int num)
-{
-        if (unlikely(platform_device_add_resources(pdev, res, num)))
-                pr_err("Failed to assign resources\n");
-}
-extern struct sys_timer vt8500_timer;
-extern struct platform_device vt8500_device_uart0;
-extern struct platform_device vt8500_device_uart1;
-extern struct platform_device vt8500_device_uart2;
-extern struct platform_device vt8500_device_uart3;
-extern struct platform_device vt8500_device_uart4;
-extern struct platform_device vt8500_device_uart5;
-extern struct platform_device vt8500_device_lcdc;
-extern struct platform_device vt8500_device_wm8505_fb;
-extern struct platform_device vt8500_device_ehci;
-extern struct platform_device vt8500_device_ge_rops;
-extern struct platform_device vt8500_device_pwm;
-extern struct platform_device vt8500_device_pwmbl;
-extern struct platform_device vt8500_device_rtc;
-#endif
diff --git a/arch/arm/mach-vt8500/gpio.c b/arch/arm/mach-vt8500/gpio.c
deleted file mode 100644
index 2bcc0ec783df..000000000000
--- a/arch/arm/mach-vt8500/gpio.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/* linux/arch/arm/mach-vt8500/gpio.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include "devices.h"
-#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
-#define ENABLE_REGS     0x0
-#define DIRECTION_REGS  0x20
-#define OUTVALUE_REGS   0x40
-#define INVALUE_REGS    0x60
-#define EXT_REGOFF      0x1c
-static void __iomem *regbase;
-struct vt8500_gpio_chip {
-        struct gpio_chip        chip;
-        unsigned int            shift;
-        unsigned int            regoff;
-};
-static int gpio_to_irq_map[8];
-static int vt8500_muxed_gpio_request(struct gpio_chip *chip,
-                                     unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff);
-        val |= (1 << vt8500_chip->shift << offset);
-        writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff);
-        return 0;
-}
-static void vt8500_muxed_gpio_free(struct gpio_chip *chip,
-                                   unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff);
-        val &= ~(1 << vt8500_chip->shift << offset);
-        writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff);
-}
-static int vt8500_muxed_gpio_direction_input(struct gpio_chip *chip,
-                                       unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff);
-        val &= ~(1 << vt8500_chip->shift << offset);
-        writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff);
-        return 0;
-}
-static int vt8500_muxed_gpio_direction_output(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff);
-        val |= (1 << vt8500_chip->shift << offset);
-        writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff);
-        if (value) {
-                val = readl(regbase + OUTVALUE_REGS + vt8500_chip->regoff);
-                val |= (1 << vt8500_chip->shift << offset);
-                writel(val, regbase + OUTVALUE_REGS + vt8500_chip->regoff);
-        }
-        return 0;
-}
-static int vt8500_muxed_gpio_get_value(struct gpio_chip *chip,
-                                       unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        return (readl(regbase + INVALUE_REGS + vt8500_chip->regoff)
-                >> vt8500_chip->shift >> offset) & 1;
-}
-static void vt8500_muxed_gpio_set_value(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + INVALUE_REGS + vt8500_chip->regoff);
-        if (value)
-                val |= (1 << vt8500_chip->shift << offset);
-        else
-                val &= ~(1 << vt8500_chip->shift << offset);
-        writel(val, regbase + INVALUE_REGS + vt8500_chip->regoff);
-}
-#define VT8500_GPIO_BANK(__name, __shift, __off, __base, __num)         \
-{                                                                       \
-        .chip = {                                                       \
-                .label                  = __name,                       \
-                .request                = vt8500_muxed_gpio_request,    \
-                .free                   = vt8500_muxed_gpio_free,       \
-                .direction_input  = vt8500_muxed_gpio_direction_input,  \
-                .direction_output = vt8500_muxed_gpio_direction_output, \
-                .get                    = vt8500_muxed_gpio_get_value,  \
-                .set                    = vt8500_muxed_gpio_set_value,  \
-                .can_sleep              = 0,                            \
-                .base                   = __base,                       \
-                .ngpio                  = __num,                        \
-        },                                                              \
-        .shift          = __shift,                                      \
-        .regoff         = __off,                                        \
-}
-static struct vt8500_gpio_chip vt8500_muxed_gpios[] = {
-        VT8500_GPIO_BANK("uart0",       0,      0x0,    8,      4),
-        VT8500_GPIO_BANK("uart1",       4,      0x0,    12,     4),
-        VT8500_GPIO_BANK("spi0",        8,      0x0,    16,     4),
-        VT8500_GPIO_BANK("spi1",        12,     0x0,    20,     4),
-        VT8500_GPIO_BANK("spi2",        16,     0x0,    24,     4),
-        VT8500_GPIO_BANK("pwmout",      24,     0x0,    28,     2),
-        VT8500_GPIO_BANK("sdmmc",       0,      0x4,    30,     11),
-        VT8500_GPIO_BANK("ms",          16,     0x4,    41,     7),
-        VT8500_GPIO_BANK("i2c0",        24,     0x4,    48,     2),
-        VT8500_GPIO_BANK("i2c1",        26,     0x4,    50,     2),
-        VT8500_GPIO_BANK("mii",         0,      0x8,    52,     20),
-        VT8500_GPIO_BANK("see",         20,     0x8,    72,     4),
-        VT8500_GPIO_BANK("ide",         24,     0x8,    76,     7),
-        VT8500_GPIO_BANK("ccir",        0,      0xc,    83,     19),
-        VT8500_GPIO_BANK("ts",          8,      0x10,   102,    11),
-        VT8500_GPIO_BANK("lcd",         0,      0x14,   113,    23),
-};
-static int vt8500_gpio_direction_input(struct gpio_chip *chip,
-                                       unsigned offset)
-{
-        unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF);
-        val &= ~(1 << offset);
-        writel(val, regbase + DIRECTION_REGS + EXT_REGOFF);
-        return 0;
-}
-static int vt8500_gpio_direction_output(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF);
-        val |= (1 << offset);
-        writel(val, regbase + DIRECTION_REGS + EXT_REGOFF);
-        if (value) {
-                val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF);
-                val |= (1 << offset);
-                writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF);
-        }
-        return 0;
-}
-static int vt8500_gpio_get_value(struct gpio_chip *chip,
-                                       unsigned offset)
-{
-        return (readl(regbase + INVALUE_REGS + EXT_REGOFF) >> offset) & 1;
-}
-static void vt8500_gpio_set_value(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        unsigned val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF);
-        if (value)
-                val |= (1 << offset);
-        else
-                val &= ~(1 << offset);
-        writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF);
-}
-static int vt8500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        if (offset > 7)
-                return -EINVAL;
-        return gpio_to_irq_map[offset];
-}
-static struct gpio_chip vt8500_external_gpios = {
-        .label                  = "extgpio",
-        .direction_input        = vt8500_gpio_direction_input,
-        .direction_output       = vt8500_gpio_direction_output,
-        .get                    = vt8500_gpio_get_value,
-        .set                    = vt8500_gpio_set_value,
-        .to_irq                 = vt8500_gpio_to_irq,
-        .can_sleep              = 0,
-        .base                   = 0,
-        .ngpio                  = 8,
-};
-void __init vt8500_gpio_init(void)
-{
-        int i;
-        for (i = 0; i < 8; i++)
-                gpio_to_irq_map[i] = wmt_gpio_ext_irq[i];
-        regbase = ioremap(wmt_gpio_base, SZ_64K);
-        if (!regbase) {
-                printk(KERN_ERR "Failed to map MMIO registers for GPIO\n");
-                return;
-        }
-        gpiochip_add(&vt8500_external_gpios);
-        for (i = 0; i < ARRAY_SIZE(vt8500_muxed_gpios); i++)
-                gpiochip_add(&vt8500_muxed_gpios[i].chip);
-}
diff --git a/arch/arm/mach-vt8500/include/mach/gpio.h b/arch/arm/mach-vt8500/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-vt8500/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-vt8500/include/mach/restart.h b/arch/arm/mach-vt8500/include/mach/restart.h
index 89f9b787d2a0..738979518acb 100644
--- a/arch/arm/mach-vt8500/include/mach/restart.h
+++ b/arch/arm/mach-vt8500/include/mach/restart.h
@@ -13,5 +13,5 @@
 *
 */
-void wmt_setup_restart(void);
+void vt8500_setup_restart(void);
-void wmt_restart(char mode, const char *cmd);
+void vt8500_restart(char mode, const char *cmd);
diff --git a/arch/arm/mach-vt8500/include/mach/uncompress.h b/arch/arm/mach-vt8500/include/mach/uncompress.h
index bb9e2d23fee3..e6e81fdaf109 100644
--- a/arch/arm/mach-vt8500/include/mach/uncompress.h
+++ b/arch/arm/mach-vt8500/include/mach/uncompress.h
@@ -15,15 +15,15 @@
 *
 */
-#define UART0_PHYS 0xd8200000
+#define UART0_PHYS      0xd8200000
-#include <asm/io.h>
+#define UART0_ADDR(x)   *(volatile unsigned char *)(UART0_PHYS + x)
 static void putc(const char c)
 {
-        while (readb(UART0_PHYS + 0x1c) & 0x2)
+        while (UART0_ADDR(0x1c) & 0x2)
                /* Tx busy, wait and poll */;
-        writeb(c, UART0_PHYS);
+        UART0_ADDR(0) = c;
 }
 static void flush(void)
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h b/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
deleted file mode 100644
index ecfee9124711..000000000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/* VT8500 Interrupt Sources */
-#define IRQ_JPEGENC     0       /* JPEG Encoder */
-#define IRQ_JPEGDEC     1       /* JPEG Decoder */
-                                /* Reserved */
-#define IRQ_PATA        3       /* PATA Controller */
-                                /* Reserved */
-#define IRQ_DMA         5       /* DMA Controller */
-#define IRQ_EXT0        6       /* External Interrupt 0 */
-#define IRQ_EXT1        7       /* External Interrupt 1 */
-#define IRQ_GE          8       /* Graphic Engine */
-#define IRQ_GOV         9       /* Graphic Overlay Engine */
-#define IRQ_ETHER       10      /* Ethernet MAC */
-#define IRQ_MPEGTS      11      /* Transport Stream Interface */
-#define IRQ_LCDC        12      /* LCD Controller */
-#define IRQ_EXT2        13      /* External Interrupt 2 */
-#define IRQ_EXT3        14      /* External Interrupt 3 */
-#define IRQ_EXT4        15      /* External Interrupt 4 */
-#define IRQ_CIPHER      16      /* Cipher */
-#define IRQ_VPP         17      /* Video Post-Processor */
-#define IRQ_I2C1        18      /* I2C 1 */
-#define IRQ_I2C0        19      /* I2C 0 */
-#define IRQ_SDMMC       20      /* SD/MMC Controller */
-#define IRQ_SDMMC_DMA   21      /* SD/MMC Controller DMA */
-#define IRQ_PMC_WU      22      /* Power Management Controller Wakeup */
-                                /* Reserved */
-#define IRQ_SPI0        24      /* SPI 0 */
-#define IRQ_SPI1        25      /* SPI 1 */
-#define IRQ_SPI2        26      /* SPI 2 */
-#define IRQ_LCDDF       27      /* LCD Data Formatter */
-#define IRQ_NAND        28      /* NAND Flash Controller */
-#define IRQ_NAND_DMA    29      /* NAND Flash Controller DMA */
-#define IRQ_MS          30      /* MemoryStick Controller */
-#define IRQ_MS_DMA      31      /* MemoryStick Controller DMA */
-#define IRQ_UART0       32      /* UART 0 */
-#define IRQ_UART1       33      /* UART 1 */
-#define IRQ_I2S         34      /* I2S */
-#define IRQ_PCM         35      /* PCM */
-#define IRQ_PMCOS0      36      /* PMC OS Timer 0 */
-#define IRQ_PMCOS1      37      /* PMC OS Timer 1 */
-#define IRQ_PMCOS2      38      /* PMC OS Timer 2 */
-#define IRQ_PMCOS3      39      /* PMC OS Timer 3 */
-#define IRQ_VPU         40      /* Video Processing Unit */
-#define IRQ_VID         41      /* Video Digital Input Interface */
-#define IRQ_AC97        42      /* AC97 Interface */
-#define IRQ_EHCI        43      /* USB */
-#define IRQ_NOR         44      /* NOR Flash Controller */
-#define IRQ_PS2MOUSE    45      /* PS/2 Mouse */
-#define IRQ_PS2KBD      46      /* PS/2 Keyboard */
-#define IRQ_UART2       47      /* UART 2 */
-#define IRQ_RTC         48      /* RTC Interrupt */
-#define IRQ_RTCSM       49      /* RTC Second/Minute Update Interrupt */
-#define IRQ_UART3       50      /* UART 3 */
-#define IRQ_ADC         51      /* ADC */
-#define IRQ_EXT5        52      /* External Interrupt 5 */
-#define IRQ_EXT6        53      /* External Interrupt 6 */
-#define IRQ_EXT7        54      /* External Interrupt 7 */
-#define IRQ_CIR         55      /* CIR */
-#define IRQ_DMA0        56      /* DMA Channel 0 */
-#define IRQ_DMA1        57      /* DMA Channel 1 */
-#define IRQ_DMA2        58      /* DMA Channel 2 */
-#define IRQ_DMA3        59      /* DMA Channel 3 */
-#define IRQ_DMA4        60      /* DMA Channel 4 */
-#define IRQ_DMA5        61      /* DMA Channel 5 */
-#define IRQ_DMA6        62      /* DMA Channel 6 */
-#define IRQ_DMA7        63      /* DMA Channel 7 */
-#define VT8500_NR_IRQS          64
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h b/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
deleted file mode 100644
index 29c63ecb2383..000000000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vt8500_regs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_VT8500_REGS_H
-#define __ASM_ARM_ARCH_VT8500_REGS_H
-/* VT8500 Registers Map */
-#define VT8500_REGS_START_PHYS  0xd8000000      /* Start of MMIO registers */
-#define VT8500_REGS_START_VIRT  0xf8000000      /* Virtual mapping start */
-#define VT8500_DDR_BASE         0xd8000000      /* 1k   DDR/DDR2 Memory
-                                                        Controller */
-#define VT8500_DMA_BASE         0xd8001000      /* 1k   DMA Controller */
-#define VT8500_SFLASH_BASE      0xd8002000      /* 1k   Serial Flash Memory
-                                                        Controller */
-#define VT8500_ETHER_BASE       0xd8004000      /* 1k   Ethernet MAC 0 */
-#define VT8500_CIPHER_BASE      0xd8006000      /* 4k   Cipher */
-#define VT8500_USB_BASE         0xd8007800      /* 2k   USB OTG */
-# define VT8500_EHCI_BASE       0xd8007900      /*      EHCI */
-# define VT8500_UHCI_BASE       0xd8007b01      /*      UHCI */
-#define VT8500_PATA_BASE        0xd8008000      /* 512  PATA */
-#define VT8500_PS2_BASE         0xd8008800      /* 1k   PS/2 */
-#define VT8500_NAND_BASE        0xd8009000      /* 1k   NAND Controller */
-#define VT8500_NOR_BASE         0xd8009400      /* 1k   NOR Controller */
-#define VT8500_SDMMC_BASE       0xd800a000      /* 1k   SD/MMC Controller */
-#define VT8500_MS_BASE          0xd800b000      /* 1k   MS/MSPRO Controller */
-#define VT8500_LCDC_BASE        0xd800e400      /* 1k   LCD Controller */
-#define VT8500_VPU_BASE         0xd8050000      /* 256  VPU */
-#define VT8500_GOV_BASE         0xd8050300      /* 256  GOV */
-#define VT8500_GEGEA_BASE       0xd8050400      /* 768  GE/GE Alpha Mixing */
-#define VT8500_LCDF_BASE        0xd8050900      /* 256  LCD Formatter */
-#define VT8500_VID_BASE         0xd8050a00      /* 256  VID */
-#define VT8500_VPP_BASE         0xd8050b00      /* 256  VPP */
-#define VT8500_TSBK_BASE        0xd80f4000      /* 4k   TSBK */
-#define VT8500_JPEGDEC_BASE     0xd80fe000      /* 4k   JPEG Decoder */
-#define VT8500_JPEGENC_BASE     0xd80ff000      /* 4k   JPEG Encoder */
-#define VT8500_RTC_BASE         0xd8100000      /* 64k  RTC */
-#define VT8500_GPIO_BASE        0xd8110000      /* 64k  GPIO Configuration */
-#define VT8500_SCC_BASE         0xd8120000      /* 64k  System Configuration*/
-#define VT8500_PMC_BASE         0xd8130000      /* 64k  PMC Configuration */
-#define VT8500_IC_BASE          0xd8140000      /* 64k  Interrupt Controller*/
-#define VT8500_UART0_BASE       0xd8200000      /* 64k  UART 0 */
-#define VT8500_UART2_BASE       0xd8210000      /* 64k  UART 2 */
-#define VT8500_PWM_BASE         0xd8220000      /* 64k  PWM Configuration */
-#define VT8500_SPI0_BASE        0xd8240000      /* 64k  SPI 0 */
-#define VT8500_SPI1_BASE        0xd8250000      /* 64k  SPI 1 */
-#define VT8500_CIR_BASE         0xd8270000      /* 64k  CIR */
-#define VT8500_I2C0_BASE        0xd8280000      /* 64k  I2C 0 */
-#define VT8500_AC97_BASE        0xd8290000      /* 64k  AC97 */
-#define VT8500_SPI2_BASE        0xd82a0000      /* 64k  SPI 2 */
-#define VT8500_UART1_BASE       0xd82b0000      /* 64k  UART 1 */
-#define VT8500_UART3_BASE       0xd82c0000      /* 64k  UART 3 */
-#define VT8500_PCM_BASE         0xd82d0000      /* 64k  PCM */
-#define VT8500_I2C1_BASE        0xd8320000      /* 64k  I2C 1 */
-#define VT8500_I2S_BASE         0xd8330000      /* 64k  I2S */
-#define VT8500_ADC_BASE         0xd8340000      /* 64k  ADC */
-#define VT8500_REGS_END_PHYS    0xd834ffff      /* End of MMIO registers */
-#define VT8500_REGS_LENGTH      (VT8500_REGS_END_PHYS \
-                                - VT8500_REGS_START_PHYS + 1)
-#endif
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500fb.h b/arch/arm/mach-vt8500/include/mach/vt8500fb.h
deleted file mode 100644
index 7f399c370fe0..000000000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500fb.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *  VT8500/WM8505 Frame Buffer platform data definitions
- *
- *  Copyright (C) 2010 Ed Spiridonov <edo.rus@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef _VT8500FB_H
-#define _VT8500FB_H
-#include <linux/fb.h>
-struct vt8500fb_platform_data {
-        struct fb_videomode     mode;
-        u32                     xres_virtual;
-        u32                     yres_virtual;
-        u32                     bpp;
-        unsigned long           video_mem_phys;
-        void                    *video_mem_virt;
-        unsigned long           video_mem_len;
-};
-#endif /* _VT8500FB_H */
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h b/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
deleted file mode 100644
index 6128627ac753..000000000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/* WM8505 Interrupt Sources */
-#define IRQ_UHCI        0       /* UHC FS (UHCI?) */
-#define IRQ_EHCI        1       /* UHC HS */
-#define IRQ_UDCDMA      2       /* UDC DMA */
-                                /* Reserved */
-#define IRQ_PS2MOUSE    4       /* PS/2 Mouse */
-#define IRQ_UDC         5       /* UDC */
-#define IRQ_EXT0        6       /* External Interrupt 0 */
-#define IRQ_EXT1        7       /* External Interrupt 1 */
-#define IRQ_KEYPAD      8       /* Keypad */
-#define IRQ_DMA         9       /* DMA Controller */
-#define IRQ_ETHER       10      /* Ethernet MAC */
-                                /* Reserved */
-                                /* Reserved */
-#define IRQ_EXT2        13      /* External Interrupt 2 */
-#define IRQ_EXT3        14      /* External Interrupt 3 */
-#define IRQ_EXT4        15      /* External Interrupt 4 */
-#define IRQ_APB         16      /* APB Bridge */
-#define IRQ_DMA0        17      /* DMA Channel 0 */
-#define IRQ_I2C1        18      /* I2C 1 */
-#define IRQ_I2C0        19      /* I2C 0 */
-#define IRQ_SDMMC       20      /* SD/MMC Controller */
-#define IRQ_SDMMC_DMA   21      /* SD/MMC Controller DMA */
-#define IRQ_PMC_WU      22      /* Power Management Controller Wakeup */
-#define IRQ_PS2KBD      23      /* PS/2 Keyboard */
-#define IRQ_SPI0        24      /* SPI 0 */
-#define IRQ_SPI1        25      /* SPI 1 */
-#define IRQ_SPI2        26      /* SPI 2 */
-#define IRQ_DMA1        27      /* DMA Channel 1 */
-#define IRQ_NAND        28      /* NAND Flash Controller */
-#define IRQ_NAND_DMA    29      /* NAND Flash Controller DMA */
-#define IRQ_UART5       30      /* UART 5 */
-#define IRQ_UART4       31      /* UART 4 */
-#define IRQ_UART0       32      /* UART 0 */
-#define IRQ_UART1       33      /* UART 1 */
-#define IRQ_DMA2        34      /* DMA Channel 2 */
-#define IRQ_I2S         35      /* I2S */
-#define IRQ_PMCOS0      36      /* PMC OS Timer 0 */
-#define IRQ_PMCOS1      37      /* PMC OS Timer 1 */
-#define IRQ_PMCOS2      38      /* PMC OS Timer 2 */
-#define IRQ_PMCOS3      39      /* PMC OS Timer 3 */
-#define IRQ_DMA3        40      /* DMA Channel 3 */
-#define IRQ_DMA4        41      /* DMA Channel 4 */
-#define IRQ_AC97        42      /* AC97 Interface */
-                                /* Reserved */
-#define IRQ_NOR         44      /* NOR Flash Controller */
-#define IRQ_DMA5        45      /* DMA Channel 5 */
-#define IRQ_DMA6        46      /* DMA Channel 6 */
-#define IRQ_UART2       47      /* UART 2 */
-#define IRQ_RTC         48      /* RTC Interrupt */
-#define IRQ_RTCSM       49      /* RTC Second/Minute Update Interrupt */
-#define IRQ_UART3       50      /* UART 3 */
-#define IRQ_DMA7        51      /* DMA Channel 7 */
-#define IRQ_EXT5        52      /* External Interrupt 5 */
-#define IRQ_EXT6        53      /* External Interrupt 6 */
-#define IRQ_EXT7        54      /* External Interrupt 7 */
-#define IRQ_CIR         55      /* CIR */
-#define IRQ_SIC0        56      /* SIC IRQ0 */
-#define IRQ_SIC1        57      /* SIC IRQ1 */
-#define IRQ_SIC2        58      /* SIC IRQ2 */
-#define IRQ_SIC3        59      /* SIC IRQ3 */
-#define IRQ_SIC4        60      /* SIC IRQ4 */
-#define IRQ_SIC5        61      /* SIC IRQ5 */
-#define IRQ_SIC6        62      /* SIC IRQ6 */
-#define IRQ_SIC7        63      /* SIC IRQ7 */
-                                /* Reserved */
-#define IRQ_JPEGDEC     65      /* JPEG Decoder */
-#define IRQ_SAE         66      /* SAE (?) */
-                                /* Reserved */
-#define IRQ_VPU         79      /* Video Processing Unit */
-#define IRQ_VPP         80      /* Video Post-Processor */
-#define IRQ_VID         81      /* Video Digital Input Interface */
-#define IRQ_SPU         82      /* SPU (?) */
-#define IRQ_PIP         83      /* PIP Error */
-#define IRQ_GE          84      /* Graphic Engine */
-#define IRQ_GOV         85      /* Graphic Overlay Engine */
-#define IRQ_DVO         86      /* Digital Video Output */
-                                /* Reserved */
-#define IRQ_DMA8        92      /* DMA Channel 8 */
-#define IRQ_DMA9        93      /* DMA Channel 9 */
-#define IRQ_DMA10       94      /* DMA Channel 10 */
-#define IRQ_DMA11       95      /* DMA Channel 11 */
-#define IRQ_DMA12       96      /* DMA Channel 12 */
-#define IRQ_DMA13       97      /* DMA Channel 13 */
-#define IRQ_DMA14       98      /* DMA Channel 14 */
-#define IRQ_DMA15       99      /* DMA Channel 15 */
-                                /* Reserved */
-#define IRQ_GOVW        111     /* GOVW (?) */
-#define IRQ_GOVRSDSCD   112     /* GOVR SDSCD (?) */
-#define IRQ_GOVRSDMIF   113     /* GOVR SDMIF (?) */
-#define IRQ_GOVRHDSCD   114     /* GOVR HDSCD (?) */
-#define IRQ_GOVRHDMIF   115     /* GOVR HDMIF (?) */
-#define WM8505_NR_IRQS          116
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h b/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
deleted file mode 100644
index df1550941efb..000000000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/wm8505_regs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_WM8505_REGS_H
-#define __ASM_ARM_ARCH_WM8505_REGS_H
-/* WM8505 Registers Map */
-#define WM8505_REGS_START_PHYS  0xd8000000      /* Start of MMIO registers */
-#define WM8505_REGS_START_VIRT  0xf8000000      /* Virtual mapping start */
-#define WM8505_DDR_BASE         0xd8000400      /* 1k   DDR/DDR2 Memory
-                                                        Controller */
-#define WM8505_DMA_BASE         0xd8001800      /* 1k   DMA Controller */
-#define WM8505_VDMA_BASE        0xd8001c00      /* 1k   VDMA */
-#define WM8505_SFLASH_BASE      0xd8002000      /* 1k   Serial Flash Memory
-                                                        Controller */
-#define WM8505_ETHER_BASE       0xd8004000      /* 1k   Ethernet MAC 0 */
-#define WM8505_CIPHER_BASE      0xd8006000      /* 4k   Cipher */
-#define WM8505_USB_BASE         0xd8007000      /* 2k   USB 2.0 Host */
-# define WM8505_EHCI_BASE       0xd8007100      /*      EHCI */
-# define WM8505_UHCI_BASE       0xd8007301      /*      UHCI */
-#define WM8505_PS2_BASE         0xd8008800      /* 1k   PS/2 */
-#define WM8505_NAND_BASE        0xd8009000      /* 1k   NAND Controller */
-#define WM8505_NOR_BASE         0xd8009400      /* 1k   NOR Controller */
-#define WM8505_SDMMC_BASE       0xd800a000      /* 1k   SD/MMC Controller */
-#define WM8505_VPU_BASE         0xd8050000      /* 256  VPU */
-#define WM8505_GOV_BASE         0xd8050300      /* 256  GOV */
-#define WM8505_GEGEA_BASE       0xd8050400      /* 768  GE/GE Alpha Mixing */
-#define WM8505_GOVR_BASE        0xd8050800      /* 512  GOVR (frambuffer) */
-#define WM8505_VID_BASE         0xd8050a00      /* 256  VID */
-#define WM8505_SCL_BASE         0xd8050d00      /* 256  SCL */
-#define WM8505_VPP_BASE         0xd8050f00      /* 256  VPP */
-#define WM8505_JPEGDEC_BASE     0xd80fe000      /* 4k   JPEG Decoder */
-#define WM8505_RTC_BASE         0xd8100000      /* 64k  RTC */
-#define WM8505_GPIO_BASE        0xd8110000      /* 64k  GPIO Configuration */
-#define WM8505_SCC_BASE         0xd8120000      /* 64k  System Configuration*/
-#define WM8505_PMC_BASE         0xd8130000      /* 64k  PMC Configuration */
-#define WM8505_IC_BASE          0xd8140000      /* 64k  Interrupt Controller*/
-#define WM8505_SIC_BASE         0xd8150000      /* 64k  Secondary IC */
-#define WM8505_UART0_BASE       0xd8200000      /* 64k  UART 0 */
-#define WM8505_UART2_BASE       0xd8210000      /* 64k  UART 2 */
-#define WM8505_PWM_BASE         0xd8220000      /* 64k  PWM Configuration */
-#define WM8505_SPI0_BASE        0xd8240000      /* 64k  SPI 0 */
-#define WM8505_SPI1_BASE        0xd8250000      /* 64k  SPI 1 */
-#define WM8505_KEYPAD_BASE      0xd8260000      /* 64k  Keypad control */
-#define WM8505_CIR_BASE         0xd8270000      /* 64k  CIR */
-#define WM8505_I2C0_BASE        0xd8280000      /* 64k  I2C 0 */
-#define WM8505_AC97_BASE        0xd8290000      /* 64k  AC97 */
-#define WM8505_SPI2_BASE        0xd82a0000      /* 64k  SPI 2 */
-#define WM8505_UART1_BASE       0xd82b0000      /* 64k  UART 1 */
-#define WM8505_UART3_BASE       0xd82c0000      /* 64k  UART 3 */
-#define WM8505_I2C1_BASE        0xd8320000      /* 64k  I2C 1 */
-#define WM8505_I2S_BASE         0xd8330000      /* 64k  I2S */
-#define WM8505_UART4_BASE       0xd8370000      /* 64k  UART 4 */
-#define WM8505_UART5_BASE       0xd8380000      /* 64k  UART 5 */
-#define WM8505_REGS_END_PHYS    0xd838ffff      /* End of MMIO registers */
-#define WM8505_REGS_LENGTH      (WM8505_REGS_END_PHYS \
-                                - WM8505_REGS_START_PHYS + 1)
-#endif
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c
index 642de0408f25..f8f9ab9bc56e 100644
--- a/arch/arm/mach-vt8500/irq.c
+++ b/arch/arm/mach-vt8500/irq.c
@@ -1,6 +1,7 @@
 /*
 *  arch/arm/mach-vt8500/irq.c
 *
+ *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
@@ -18,81 +19,102 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+/*
+ * This file is copied and modified from the original irq.c provided by
+ * Alexey Charkov. Minor changes have been made for Device Tree Support.
+ */
+#include <linux/slab.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 #include <asm/irq.h>
-#include "devices.h"
-#define VT8500_IC_DCTR          0x40            /* Destination control
+#define VT8500_ICPC_IRQ         0x20
-                                                register, 64*u8 */
+#define VT8500_ICPC_FIQ         0x24
-#define VT8500_INT_ENABLE       (1 << 3)
+#define VT8500_ICDC             0x40            /* Destination Control 64*u32 */
-#define VT8500_TRIGGER_HIGH     (0 << 4)
+#define VT8500_ICIS             0x80            /* Interrupt status, 16*u32 */
-#define VT8500_TRIGGER_RISING   (1 << 4)
-#define VT8500_TRIGGER_FALLING  (2 << 4)
+/* ICPC */
+#define ICPC_MASK               0x3F
+#define ICPC_ROTATE             BIT(6)
+/* IC_DCTR */
+#define ICDC_IRQ                0x00
+#define ICDC_FIQ                0x01
+#define ICDC_DSS0               0x02
+#define ICDC_DSS1               0x03
+#define ICDC_DSS2               0x04
+#define ICDC_DSS3               0x05
+#define ICDC_DSS4               0x06
+#define ICDC_DSS5               0x07
+#define VT8500_INT_DISABLE      0
+#define VT8500_INT_ENABLE       BIT(3)
+#define VT8500_TRIGGER_HIGH     0
+#define VT8500_TRIGGER_RISING   BIT(5)
+#define VT8500_TRIGGER_FALLING  BIT(6)
 #define VT8500_EDGE             ( VT8500_TRIGGER_RISING \
                                | VT8500_TRIGGER_FALLING)
-#define VT8500_IC_STATUS        0x80            /* Interrupt status, 2*u32 */
-static void __iomem *ic_regbase;
+static int irq_cnt;
-static void __iomem *sic_regbase;
+struct vt8500_irq_priv {
+        void __iomem *base;
+};
 static void vt8500_irq_mask(struct irq_data *d)
 {
-        void __iomem *base = ic_regbase;
+        struct vt8500_irq_priv *priv =
-        unsigned irq = d->irq;
+                        (struct vt8500_irq_priv *)(d->domain->host_data);
+        void __iomem *base = priv->base;
        u8 edge;
-        if (irq >= 64) {
+        edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
-                base = sic_regbase;
-                irq -= 64;
-        }
-        edge = readb(base + VT8500_IC_DCTR + irq) & VT8500_EDGE;
        if (edge) {
-                void __iomem *stat_reg = base + VT8500_IC_STATUS
+                void __iomem *stat_reg = base + VT8500_ICIS
-                                                + (irq < 32 ? 0 : 4);
+                                                + (d->hwirq < 32 ? 0 : 4);
                unsigned status = readl(stat_reg);
-                status |= (1 << (irq & 0x1f));
+                status |= (1 << (d->hwirq & 0x1f));
                writel(status, stat_reg);
        } else {
-                u8 dctr = readb(base + VT8500_IC_DCTR + irq);
+                u8 dctr = readb(base + VT8500_ICDC + d->hwirq);
                dctr &= ~VT8500_INT_ENABLE;
-                writeb(dctr, base + VT8500_IC_DCTR + irq);
+                writeb(dctr, base + VT8500_ICDC + d->hwirq);
        }
 }
 static void vt8500_irq_unmask(struct irq_data *d)
 {
-        void __iomem *base = ic_regbase;
+        struct vt8500_irq_priv *priv =
-        unsigned irq = d->irq;
+                        (struct vt8500_irq_priv *)(d->domain->host_data);
+        void __iomem *base = priv->base;
        u8 dctr;
-        if (irq >= 64) {
+        dctr = readb(base + VT8500_ICDC + d->hwirq);
-                base = sic_regbase;
-                irq -= 64;
-        }
-        dctr = readb(base + VT8500_IC_DCTR + irq);
        dctr |= VT8500_INT_ENABLE;
-        writeb(dctr, base + VT8500_IC_DCTR + irq);
+        writeb(dctr, base + VT8500_ICDC + d->hwirq);
 }
 static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
-        void __iomem *base = ic_regbase;
+        struct vt8500_irq_priv *priv =
-        unsigned irq = d->irq;
+                        (struct vt8500_irq_priv *)(d->domain->host_data);
-        unsigned orig_irq = irq;
+        void __iomem *base = priv->base;
        u8 dctr;
-        if (irq >= 64) {
+        dctr = readb(base + VT8500_ICDC + d->hwirq);
-                base = sic_regbase;
-                irq -= 64;
-        }
-        dctr = readb(base + VT8500_IC_DCTR + irq);
        dctr &= ~VT8500_EDGE;
        switch (flow_type) {
@@ -100,18 +122,18 @@ static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
                return -EINVAL;
        case IRQF_TRIGGER_HIGH:
                dctr |= VT8500_TRIGGER_HIGH;
-                __irq_set_handler_locked(orig_irq, handle_level_irq);
+                __irq_set_handler_locked(d->irq, handle_level_irq);
                break;
        case IRQF_TRIGGER_FALLING:
                dctr |= VT8500_TRIGGER_FALLING;
-                __irq_set_handler_locked(orig_irq, handle_edge_irq);
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
                break;
        case IRQF_TRIGGER_RISING:
                dctr |= VT8500_TRIGGER_RISING;
-                __irq_set_handler_locked(orig_irq, handle_edge_irq);
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
                break;
        }
-        writeb(dctr, base + VT8500_IC_DCTR + irq);
+        writeb(dctr, base + VT8500_ICDC + d->hwirq);
        return 0;
 }
@@ -124,57 +146,76 @@ static struct irq_chip vt8500_irq_chip = {
        .irq_set_type = vt8500_irq_set_type,
 };
-void __init vt8500_init_irq(void)
+static void __init vt8500_init_irq_hw(void __iomem *base)
 {
        unsigned int i;
-        ic_regbase = ioremap(wmt_ic_base, SZ_64K);
+        /* Enable rotating priority for IRQ */
+        writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
+        writel(0x00, base + VT8500_ICPC_FIQ);
-        if (ic_regbase) {
+        for (i = 0; i < 64; i++) {
-                /* Enable rotating priority for IRQ */
+                /* Disable all interrupts and route them to IRQ */
-                writel((1 << 6), ic_regbase + 0x20);
+                writeb(VT8500_INT_DISABLE | ICDC_IRQ,
-                writel(0, ic_regbase + 0x24);
+                                                base + VT8500_ICDC + i);
+        }
+}
-                for (i = 0; i < wmt_nr_irqs; i++) {
+static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
-                        /* Disable all interrupts and route them to IRQ */
+                                                        irq_hw_number_t hw)
-                        writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
+{
+        irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
+        set_irq_flags(virq, IRQF_VALID);
-                        irq_set_chip_and_handler(i, &vt8500_irq_chip,
+        return 0;
-                                                 handle_level_irq);
-                        set_irq_flags(i, IRQF_VALID);
-                }
-        } else {
-                printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
-        }
 }
-void __init wm8505_init_irq(void)
+static struct irq_domain_ops vt8500_irq_domain_ops = {
+        .map = vt8500_irq_map,
+        .xlate = irq_domain_xlate_onecell,
+};
+int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
 {
-        unsigned int i;
+        struct irq_domain *vt8500_irq_domain;
+        struct vt8500_irq_priv *priv;
+        int irq, i;
+        struct device_node *np = node;
+        priv = kzalloc(sizeof(struct vt8500_irq_priv), GFP_KERNEL);
+        priv->base = of_iomap(np, 0);
+        vt8500_irq_domain = irq_domain_add_legacy(node, 64, irq_cnt, 0,
+                                &vt8500_irq_domain_ops, priv);
+        if (!vt8500_irq_domain)
+                pr_err("%s: Unable to add wmt irq domain!\n", __func__);
+        irq_set_default_host(vt8500_irq_domain);
+        vt8500_init_irq_hw(priv->base);
-        ic_regbase = ioremap(wmt_ic_base, SZ_64K);
+        pr_info("Added IRQ Controller @ %x [virq_base = %d]\n",
-        sic_regbase = ioremap(wmt_sic_base, SZ_64K);
+                                                (u32)(priv->base), irq_cnt);
-        if (ic_regbase && sic_regbase) {
+        /* check if this is a slaved controller */
-                /* Enable rotating priority for IRQ */
+        if (of_irq_count(np) != 0) {
-                writel((1 << 6), ic_regbase + 0x20);
+                /* check that we have the correct number of interrupts */
-                writel(0, ic_regbase + 0x24);
+                if (of_irq_count(np) != 8) {
-                writel((1 << 6), sic_regbase + 0x20);
+                        pr_err("%s: Incorrect IRQ map for slave controller\n",
-                writel(0, sic_regbase + 0x24);
+                                        __func__);
+                        return -EINVAL;
-                for (i = 0; i < wmt_nr_irqs; i++) {
-                        /* Disable all interrupts and route them to IRQ */
-                        if (i < 64)
-                                writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
-                        else
-                                writeb(0x00, sic_regbase + VT8500_IC_DCTR
-                                                                + i - 64);
-                        irq_set_chip_and_handler(i, &vt8500_irq_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(i, IRQF_VALID);
                }
-        } else {
-                printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
+                for (i = 0; i < 8; i++) {
+                        irq = irq_of_parse_and_map(np, i);
+                        enable_irq(irq);
+                }
+                pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
        }
+        irq_cnt += 64;
+        return 0;
 }
diff --git a/arch/arm/mach-vt8500/restart.c b/arch/arm/mach-vt8500/restart.c
deleted file mode 100644
index 497e89a5e130..000000000000
--- a/arch/arm/mach-vt8500/restart.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/arch/arm/mach-vt8500/restart.c
- *
- * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <asm/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#define LEGACY_PMC_BASE         0xD8130000
-#define WMT_PRIZM_PMSR_REG      0x60
-static void __iomem *pmc_base;
-void wmt_setup_restart(void)
-{
-        struct device_node *np;
-        /*
-         * Check if Power Mgmt Controller node is present in device tree. If no
-         * device tree node, use the legacy PMSR value (valid for all current
-         * SoCs).
-         */
-        np = of_find_compatible_node(NULL, NULL, "wmt,prizm-pmc");
-        if (np) {
-                pmc_base = of_iomap(np, 0);
-                if (!pmc_base)
-                        pr_err("%s:of_iomap(pmc) failed\n", __func__);
-                of_node_put(np);
-        } else {
-                pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
-                if (!pmc_base) {
-                        pr_err("%s:ioremap(rstc) failed\n", __func__);
-                        return;
-                }
-        }
-}
-void wmt_restart(char mode, const char *cmd)
-{
-        if (pmc_base)
-                writel(1, pmc_base + WMT_PRIZM_PMSR_REG);
-}
diff --git a/arch/arm/mach-vt8500/timer.c b/arch/arm/mach-vt8500/timer.c
index d5376c592ab6..050e1833f2d0 100644
--- a/arch/arm/mach-vt8500/timer.c
+++ b/arch/arm/mach-vt8500/timer.c
@@ -1,6 +1,7 @@
 /*
- *  arch/arm/mach-vt8500/timer.c
+ *  arch/arm/mach-vt8500/timer_dt.c
 *
+ *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
@@ -18,18 +19,25 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+/*
+ * This file is copied and modified from the original timer.c provided by
+ * Alexey Charkov. Minor changes have been made for Device Tree Support.
+ */
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/delay.h>
 #include <asm/mach/time.h>
-#include "devices.h"
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #define VT8500_TIMER_OFFSET     0x0100
+#define VT8500_TIMER_HZ         3000000
 #define TIMER_MATCH_VAL         0x0000
 #define TIMER_COUNT_VAL         0x0010
 #define TIMER_STATUS_VAL        0x0014
@@ -39,7 +47,6 @@
 #define TIMER_COUNT_R_ACTIVE    (1 << 5)        /* not ready for read */
 #define TIMER_COUNT_W_ACTIVE    (1 << 4)        /* not ready for write */
 #define TIMER_MATCH_W_ACTIVE    (1 << 0)        /* not ready for write */
-#define VT8500_TIMER_HZ         3000000
 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
@@ -55,7 +62,7 @@ static cycle_t vt8500_timer_read(struct clocksource *cs)
        return readl(regbase + TIMER_COUNT_VAL);
 }
-struct clocksource clocksource = {
+static struct clocksource clocksource = {
        .name           = "vt8500_timer",
        .rating         = 200,
        .read           = vt8500_timer_read,
@@ -98,7 +105,7 @@ static void vt8500_timer_set_mode(enum clock_event_mode mode,
        }
 }
-struct clock_event_device clockevent = {
+static struct clock_event_device clockevent = {
        .name           = "vt8500_timer",
        .features       = CLOCK_EVT_FEAT_ONESHOT,
        .rating         = 200,
@@ -115,26 +122,51 @@ static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
        return IRQ_HANDLED;
 }
-struct irqaction irq = {
+static struct irqaction irq = {
        .name    = "vt8500_timer",
        .flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
        .handler = vt8500_timer_interrupt,
        .dev_id  = &clockevent,
 };
-static void __init vt8500_timer_init(void)
+static struct of_device_id vt8500_timer_ids[] = {
+        { .compatible = "via,vt8500-timer" },
+        { }
+};
+void __init vt8500_timer_init(void)
 {
-        regbase = ioremap(wmt_pmc_base + VT8500_TIMER_OFFSET, 0x28);
+        struct device_node *np;
-        if (!regbase)
+        int timer_irq;
-                printk(KERN_ERR "vt8500_timer_init: failed to map MMIO registers\n");
+        np = of_find_matching_node(NULL, vt8500_timer_ids);
+        if (!np) {
+                pr_err("%s: Timer description missing from Device Tree\n",
+                                                                __func__);
+                return;
+        }
+        regbase = of_iomap(np, 0);
+        if (!regbase) {
+                pr_err("%s: Missing iobase description in Device Tree\n",
+                                                                __func__);
+                of_node_put(np);
+                return;
+        }
+        timer_irq = irq_of_parse_and_map(np, 0);
+        if (!timer_irq) {
+                pr_err("%s: Missing irq description in Device Tree\n",
+                                                                __func__);
+                of_node_put(np);
+                return;
+        }
        writel(1, regbase + TIMER_CTRL_VAL);
        writel(0xf, regbase + TIMER_STATUS_VAL);
        writel(~0, regbase + TIMER_MATCH_VAL);
        if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ))
-                printk(KERN_ERR "vt8500_timer_init: clocksource_register failed for %s\n",
+                pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n",
-                                        clocksource.name);
+                                        __func__, clocksource.name);
        clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4);
@@ -144,12 +176,9 @@ static void __init vt8500_timer_init(void)
        clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent);
        clockevent.cpumask = cpumask_of(0);
-        if (setup_irq(wmt_timer_irq, &irq))
+        if (setup_irq(timer_irq, &irq))
-                printk(KERN_ERR "vt8500_timer_init: setup_irq failed for %s\n",
+                pr_err("%s: setup_irq failed for %s\n", __func__,
-                                        clockevent.name);
+                                                        clockevent.name);
        clockevents_register_device(&clockevent);
 }
-struct sys_timer vt8500_timer = {
-        .init = vt8500_timer_init
-};
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
new file mode 100644
index 000000000000..8d3871f110a5
--- /dev/null
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -0,0 +1,198 @@
+/*
+ *  arch/arm/mach-vt8500/vt8500.c
+ *
+ *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/io.h>
+#include <linux/pm.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <mach/restart.h>
+#include "common.h"
+#define LEGACY_GPIO_BASE        0xD8110000
+#define LEGACY_PMC_BASE         0xD8130000
+/* Registers in GPIO Controller */
+#define VT8500_GPIO_MUX_REG     0x200
+/* Registers in Power Management Controller */
+#define VT8500_HCR_REG          0x12
+#define VT8500_PMSR_REG         0x60
+static void __iomem *pmc_base;
+void vt8500_restart(char mode, const char *cmd)
+{
+        if (pmc_base)
+                writel(1, pmc_base + VT8500_PMSR_REG);
+}
+static struct map_desc vt8500_io_desc[] __initdata = {
+        /* SoC MMIO registers */
+        [0] = {
+                .virtual        = 0xf8000000,
+                .pfn            = __phys_to_pfn(0xd8000000),
+                .length         = 0x00390000, /* max of all chip variants */
+                .type           = MT_DEVICE
+        },
+};
+void __init vt8500_map_io(void)
+{
+        iotable_init(vt8500_io_desc, ARRAY_SIZE(vt8500_io_desc));
+}
+static void vt8500_power_off(void)
+{
+        local_irq_disable();
+        writew(5, pmc_base + VT8500_HCR_REG);
+        asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
+}
+void __init vt8500_init(void)
+{
+        struct device_node *np;
+#if defined(CONFIG_FB_VT8500) || defined(CONFIG_FB_WM8505)
+        struct device_node *fb;
+        void __iomem *gpio_base;
+#endif
+#ifdef CONFIG_FB_VT8500
+        fb = of_find_compatible_node(NULL, NULL, "via,vt8500-fb");
+        if (fb) {
+                np = of_find_compatible_node(NULL, NULL, "via,vt8500-gpio");
+                if (np) {
+                        gpio_base = of_iomap(np, 0);
+                        if (!gpio_base)
+                                pr_err("%s: of_iomap(gpio_mux) failed\n",
+                                                                __func__);
+                        of_node_put(np);
+                } else {
+                        gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
+                        if (!gpio_base)
+                                pr_err("%s: ioremap(legacy_gpio_mux) failed\n",
+                                                                __func__);
+                }
+                if (gpio_base) {
+                        writel(readl(gpio_base + VT8500_GPIO_MUX_REG) | 1,
+                                gpio_base + VT8500_GPIO_MUX_REG);
+                        iounmap(gpio_base);
+                } else
+                        pr_err("%s: Could not remap GPIO mux\n", __func__);
+                of_node_put(fb);
+        }
+#endif
+#ifdef CONFIG_FB_WM8505
+        fb = of_find_compatible_node(NULL, NULL, "wm,wm8505-fb");
+        if (fb) {
+                np = of_find_compatible_node(NULL, NULL, "wm,wm8505-gpio");
+                if (!np)
+                        np = of_find_compatible_node(NULL, NULL,
+                                                        "wm,wm8650-gpio");
+                if (np) {
+                        gpio_base = of_iomap(np, 0);
+                        if (!gpio_base)
+                                pr_err("%s: of_iomap(gpio_mux) failed\n",
+                                                                __func__);
+                        of_node_put(np);
+                } else {
+                        gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
+                        if (!gpio_base)
+                                pr_err("%s: ioremap(legacy_gpio_mux) failed\n",
+                                                                __func__);
+                }
+                if (gpio_base) {
+                        writel(readl(gpio_base + VT8500_GPIO_MUX_REG) |
+                                0x80000000, gpio_base + VT8500_GPIO_MUX_REG);
+                        iounmap(gpio_base);
+                } else
+                        pr_err("%s: Could not remap GPIO mux\n", __func__);
+                of_node_put(fb);
+        }
+#endif
+        np = of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
+        if (np) {
+                pmc_base = of_iomap(np, 0);
+                if (!pmc_base)
+                        pr_err("%s:of_iomap(pmc) failed\n", __func__);
+                of_node_put(np);
+        } else {
+                pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
+                if (!pmc_base)
+                        pr_err("%s:ioremap(power_off) failed\n", __func__);
+        }
+        if (pmc_base)
+                pm_power_off = &vt8500_power_off;
+        else
+                pr_err("%s: PMC Hibernation register could not be remapped, not enabling power off!\n", __func__);
+        vtwm_clk_init(pmc_base);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static const struct of_device_id vt8500_irq_match[] __initconst = {
+        { .compatible = "via,vt8500-intc", .data = vt8500_irq_init, },
+        { /* sentinel */ },
+};
+static void __init vt8500_init_irq(void)
+{
+        of_irq_init(vt8500_irq_match);
+};
+static struct sys_timer vt8500_timer = {
+        .init = vt8500_timer_init,
+};
+static const char * const vt8500_dt_compat[] = {
+        "via,vt8500",
+        "wm,wm8650",
+        "wm,wm8505",
+};
+DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
+        .dt_compat      = vt8500_dt_compat,
+        .map_io         = vt8500_map_io,
+        .init_irq       = vt8500_init_irq,
+        .timer          = &vt8500_timer,
+        .init_machine   = vt8500_init,
+        .restart        = vt8500_restart,
+MACHINE_END
diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c
deleted file mode 100644
index db19886caf7c..000000000000
--- a/arch/arm/mach-vt8500/wm8505_7in.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/wm8505_7in.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/io.h>
-#include <linux/pm.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/restart.h>
-#include "devices.h"
-static void __iomem *pmc_hiber;
-static struct platform_device *devices[] __initdata = {
-        &vt8500_device_uart0,
-        &vt8500_device_ehci,
-        &vt8500_device_wm8505_fb,
-        &vt8500_device_ge_rops,
-        &vt8500_device_pwm,
-        &vt8500_device_pwmbl,
-        &vt8500_device_rtc,
-};
-static void vt8500_power_off(void)
-{
-        local_irq_disable();
-        writew(5, pmc_hiber);
-        asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
-}
-void __init wm8505_7in_init(void)
-{
-#ifdef CONFIG_FB_WM8505
-        void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4);
-        if (gpio_mux_reg) {
-                writel(readl(gpio_mux_reg) | 0x80000000, gpio_mux_reg);
-                iounmap(gpio_mux_reg);
-        } else {
-                printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n");
-        }
-#endif
-        pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2);
-        if (pmc_hiber)
-                pm_power_off = &vt8500_power_off;
-        else
-                printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-        wmt_setup_restart();
-        wm8505_set_resources();
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-        vt8500_gpio_init();
-}
-MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook")
-        .atag_offset    = 0x100,
-        .restart        = wmt_restart,
-        .reserve        = wm8505_reserve_mem,
-        .map_io         = wm8505_map_io,
-        .init_irq       = wm8505_init_irq,
-        .timer          = &vt8500_timer,
-        .init_machine   = wm8505_7in_init,
-MACHINE_END
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index 48f5b9fdfb7f..7abdb9645c5b 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -34,11 +34,11 @@
 #include <asm/mach-types.h>
 #include <mach/regs-serial.h>
-#include <mach/nuc900_spi.h>
+#include <linux/platform_data/spi-nuc900.h>
 #include <mach/map.h>
-#include <mach/fb.h>
+#include <linux/platform_data/video-nuc900fb.h>
 #include <mach/regs-ldm.h>
-#include <mach/w90p910_keypad.h>
+#include <linux/platform_data/keypad-w90p910.h>
 #include "cpu.h"
diff --git a/arch/arm/mach-w90x900/include/mach/fb.h b/arch/arm/mach-w90x900/include/mach/fb.h
deleted file mode 100644
index cec5ece765ed..000000000000
--- a/arch/arm/mach-w90x900/include/mach/fb.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* linux/include/asm/arch-nuc900/fb.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * Changelog:
- *
- *   2008/08/26     vincen.zswan modify this file for LCD.
- */
-#ifndef __ASM_ARM_FB_H
-#define __ASM_ARM_FB_H
-/* LCD Controller Hardware Desc */
-struct nuc900fb_hw {
-        unsigned int lcd_dccs;
-        unsigned int lcd_device_ctrl;
-        unsigned int lcd_mpulcd_cmd;
-        unsigned int lcd_int_cs;
-        unsigned int lcd_crtc_size;
-        unsigned int lcd_crtc_dend;
-        unsigned int lcd_crtc_hr;
-        unsigned int lcd_crtc_hsync;
-        unsigned int lcd_crtc_vr;
-        unsigned int lcd_va_baddr0;
-        unsigned int lcd_va_baddr1;
-        unsigned int lcd_va_fbctrl;
-        unsigned int lcd_va_scale;
-        unsigned int lcd_va_test;
-        unsigned int lcd_va_win;
-        unsigned int lcd_va_stuff;
-};
-/* LCD Display Description */
-struct nuc900fb_display {
-        /* LCD Image type */
-        unsigned type;
-        /* LCD Screen Size */
-        unsigned short width;
-        unsigned short height;
-        /* LCD Screen Info */
-        unsigned short xres;
-        unsigned short yres;
-        unsigned short bpp;
-        unsigned long pixclock;
-        unsigned short left_margin;
-        unsigned short right_margin;
-        unsigned short hsync_len;
-        unsigned short upper_margin;
-        unsigned short lower_margin;
-        unsigned short vsync_len;
-        /* hardware special register value */
-        unsigned int dccs;
-        unsigned int devctl;
-        unsigned int fbctrl;
-        unsigned int scale;
-};
-struct nuc900fb_mach_info {
-        struct nuc900fb_display *displays;
-        unsigned num_displays;
-        unsigned default_display;
-        /* GPIO Setting  Info */
-        unsigned gpio_dir;
-        unsigned gpio_dir_mask;
-        unsigned gpio_data;
-        unsigned gpio_data_mask;
-};
-extern void __init nuc900_fb_set_platdata(struct nuc900fb_mach_info *);
-#endif /* __ASM_ARM_FB_H */
diff --git a/arch/arm/mach-w90x900/include/mach/i2c.h b/arch/arm/mach-w90x900/include/mach/i2c.h
deleted file mode 100644
index 9ffb12d06e91..000000000000
--- a/arch/arm/mach-w90x900/include/mach/i2c.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __ASM_ARCH_NUC900_I2C_H
-#define __ASM_ARCH_NUC900_I2C_H
-struct nuc900_platform_i2c {
-        int             bus_num;
-        unsigned long   bus_freq;
-};
-#endif /* __ASM_ARCH_NUC900_I2C_H */
diff --git a/arch/arm/mach-w90x900/include/mach/nuc900_spi.h b/arch/arm/mach-w90x900/include/mach/nuc900_spi.h
deleted file mode 100644
index 2c4e0c128501..000000000000
--- a/arch/arm/mach-w90x900/include/mach/nuc900_spi.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * arch/arm/mach-w90x900/include/mach/nuc900_spi.h
- *
- * Copyright (c) 2009 Nuvoton technology corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation;version 2 of the License.
- *
- */
-#ifndef __ASM_ARCH_SPI_H
-#define __ASM_ARCH_SPI_H
-extern void mfp_set_groupg(struct device *dev, const char *subname);
-struct nuc900_spi_info {
-        unsigned int num_cs;
-        unsigned int lsb;
-        unsigned int txneg;
-        unsigned int rxneg;
-        unsigned int divider;
-        unsigned int sleep;
-        unsigned int txnum;
-        unsigned int txbitlen;
-        int bus_num;
-};
-struct nuc900_spi_chip {
-        unsigned char bits_per_word;
-};
-#endif /* __ASM_ARCH_SPI_H */
diff --git a/arch/arm/mach-w90x900/include/mach/w90p910_keypad.h b/arch/arm/mach-w90x900/include/mach/w90p910_keypad.h
deleted file mode 100644
index 556778e8ddaa..000000000000
--- a/arch/arm/mach-w90x900/include/mach/w90p910_keypad.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __ASM_ARCH_W90P910_KEYPAD_H
-#define __ASM_ARCH_W90P910_KEYPAD_H
-#include <linux/input/matrix_keypad.h>
-extern void mfp_set_groupi(struct device *dev);
-struct w90p910_keypad_platform_data {
-        const struct matrix_keymap_data *keymap_data;
-        unsigned int    prescale;
-        unsigned int    debounce;
-};
-#endif /* __ASM_ARCH_W90P910_KEYPAD_H */
diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c
index 067d8f9166dc..500fe5932ce9 100644
--- a/arch/arm/mach-w90x900/mach-nuc950evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc950evb.c
@@ -20,7 +20,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach-types.h>
 #include <mach/map.h>
-#include <mach/fb.h>
+#include <linux/platform_data/video-nuc900fb.h>
 #include "nuc950.h"
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 101b9681c08c..c9a4963b5c3d 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -624,6 +624,23 @@ config ARM_THUMBEE
          Say Y here if you have a CPU with the ThumbEE extension and code to
          make use of it. Say N for code that can run on CPUs without ThumbEE.
+config ARM_VIRT_EXT
+        bool "Native support for the ARM Virtualization Extensions"
+        depends on MMU && CPU_V7
+        help
+          Enable the kernel to make use of the ARM Virtualization
+          Extensions to install hypervisors without run-time firmware
+          assistance.
+          A compliant bootloader is required in order to make maximum
+          use of this feature.  Refer to Documentation/arm/Booting for
+          details.
+          It is safe to enable this option even if the kernel may not be
+          booted in HYP mode, may not have support for the
+          virtualization extensions, or may be booted with a
+          non-compliant bootloader.
 config SWP_EMULATE
        bool "Emulate SWP/SWPB instructions"
        depends on !CPU_USE_DOMAINS && CPU_V7
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 9107231aacc5..b9f60ebe3bc4 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -699,7 +699,6 @@ do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
        unsigned long instr = *pinstr;
        u16 tinst1 = (instr >> 16) & 0xffff;
        u16 tinst2 = instr & 0xffff;
-        poffset->un = 0;
        switch (tinst1 & 0xffe0) {
        /* A6.3.5 Load/Store multiple */
@@ -854,9 +853,10 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
                break;
        case 0x08000000:        /* ldm or stm, or thumb-2 32bit instruction */
-                if (thumb2_32b)
+                if (thumb2_32b) {
+                        offset.un = 0;
                        handler = do_alignment_t32_to_handler(&instr, regs, &offset);
-                else
+                } else
                        handler = do_alignment_ldmstm;
                break;
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
index 072016371093..e505befe51b5 100644
--- a/arch/arm/mm/cache-fa.S
+++ b/arch/arm/mm/cache-fa.S
@@ -240,6 +240,9 @@ ENTRY(fa_dma_unmap_area)
        mov     pc, lr
 ENDPROC(fa_dma_unmap_area)
+        .globl  fa_flush_kern_cache_louis
+        .equ    fa_flush_kern_cache_louis, fa_flush_kern_cache_all
        __INITDATA
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 2a8e380501e8..8a97e6443c62 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -368,14 +368,18 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
                /* l2x0 controller is disabled */
                writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
-                l2x0_saved_regs.aux_ctrl = aux;
                l2x0_inv_all();
                /* enable L2X0 */
                writel_relaxed(1, l2x0_base + L2X0_CTRL);
        }
+        /* Re-read it in case some bits are reserved. */
+        aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+        /* Save the value for resuming. */
+        l2x0_saved_regs.aux_ctrl = aux;
        outer_cache.inv_range = l2x0_inv_range;
        outer_cache.clean_range = l2x0_clean_range;
        outer_cache.flush_range = l2x0_flush_range;
@@ -554,7 +558,7 @@ static const struct of_device_id l2x0_ids[] __initconst = {
 int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 {
        struct device_node *np;
-        struct l2x0_of_data *data;
+        const struct l2x0_of_data *data;
        struct resource res;
        np = of_find_matching_node(NULL, l2x0_ids);
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 23a7643e9a87..1be0f4e5e6eb 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -15,8 +15,11 @@
 */
 #include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
+#include <asm/cputype.h>
 #include <asm/hardware/cache-tauros2.h>
@@ -144,25 +147,8 @@ static inline void __init write_extra_features(u32 u)
        __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
 }
-static void __init disable_l2_prefetch(void)
-{
-        u32 u;
-        /*
-         * Read the CPU Extra Features register and verify that the
-         * Disable L2 Prefetch bit is set.
-         */
-        u = read_extra_features();
-        if (!(u & 0x01000000)) {
-                printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n");
-                write_extra_features(u | 0x01000000);
-        }
-}
 static inline int __init cpuid_scheme(void)
 {
-        extern int processor_id;
        return !!((processor_id & 0x000f0000) == 0x000f0000);
 }
@@ -189,12 +175,36 @@ static inline void __init write_actlr(u32 actlr)
        __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
 }
-void __init tauros2_init(void)
+static void enable_extra_feature(unsigned int features)
+{
+        u32 u;
+        u = read_extra_features();
+        if (features & CACHE_TAUROS2_PREFETCH_ON)
+                u &= ~0x01000000;
+        else
+                u |= 0x01000000;
+        printk(KERN_INFO "Tauros2: %s L2 prefetch.\n",
+                        (features & CACHE_TAUROS2_PREFETCH_ON)
+                        ? "Enabling" : "Disabling");
+        if (features & CACHE_TAUROS2_LINEFILL_BURST8)
+                u |= 0x00100000;
+        else
+                u &= ~0x00100000;
+        printk(KERN_INFO "Tauros2: %s line fill burt8.\n",
+                        (features & CACHE_TAUROS2_LINEFILL_BURST8)
+                        ? "Enabling" : "Disabling");
+        write_extra_features(u);
+}
+static void __init tauros2_internal_init(unsigned int features)
 {
-        extern int processor_id;
+        char *mode = NULL;
-        char *mode;
-        disable_l2_prefetch();
+        enable_extra_feature(features);
 #ifdef CONFIG_CPU_32v5
        if ((processor_id & 0xff0f0000) == 0x56050000) {
@@ -286,3 +296,34 @@ void __init tauros2_init(void)
        printk(KERN_INFO "Tauros2: L2 cache support initialised "
                         "in %s mode.\n", mode);
 }
+#ifdef CONFIG_OF
+static const struct of_device_id tauros2_ids[] __initconst = {
+        { .compatible = "marvell,tauros2-cache"},
+        {}
+};
+#endif
+void __init tauros2_init(unsigned int features)
+{
+#ifdef CONFIG_OF
+        struct device_node *node;
+        int ret;
+        unsigned int f;
+        node = of_find_matching_node(NULL, tauros2_ids);
+        if (!node) {
+                pr_info("Not found marvell,tauros2-cache, disable it\n");
+                return;
+        }
+        ret = of_property_read_u32(node, "marvell,tauros2-cache-features", &f);
+        if (ret) {
+                pr_info("Not found marvell,tauros-cache-features property, "
+                        "disable extra features\n");
+                features = 0;
+        } else
+                features = f;
+#endif
+        tauros2_internal_init(features);
+}
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index 52e35f32eefb..8a3fadece8d3 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -128,6 +128,9 @@ ENTRY(v3_dma_map_area)
 ENDPROC(v3_dma_unmap_area)
 ENDPROC(v3_dma_map_area)
+        .globl  v3_flush_kern_cache_louis
+        .equ    v3_flush_kern_cache_louis, v3_flush_kern_cache_all
        __INITDATA
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index 022135d2b7e4..43e5d77be677 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -140,6 +140,9 @@ ENTRY(v4_dma_map_area)
 ENDPROC(v4_dma_unmap_area)
 ENDPROC(v4_dma_map_area)
+        .globl  v4_flush_kern_cache_louis
+        .equ    v4_flush_kern_cache_louis, v4_flush_kern_cache_all
        __INITDATA
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 8f1eeae340c8..cd4945321407 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -251,6 +251,9 @@ ENTRY(v4wb_dma_unmap_area)
        mov     pc, lr
 ENDPROC(v4wb_dma_unmap_area)
+        .globl  v4wb_flush_kern_cache_louis
+        .equ    v4wb_flush_kern_cache_louis, v4wb_flush_kern_cache_all
        __INITDATA
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index b34a5f908a82..11e5e5838bc5 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -196,6 +196,9 @@ ENTRY(v4wt_dma_map_area)
 ENDPROC(v4wt_dma_unmap_area)
 ENDPROC(v4wt_dma_map_area)
+        .globl  v4wt_flush_kern_cache_louis
+        .equ    v4wt_flush_kern_cache_louis, v4wt_flush_kern_cache_all
        __INITDATA
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 4b10760c56d6..d8fd4d4bd3d4 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -326,6 +326,9 @@ ENTRY(v6_dma_unmap_area)
        mov     pc, lr
 ENDPROC(v6_dma_unmap_area)
+        .globl  v6_flush_kern_cache_louis
+        .equ    v6_flush_kern_cache_louis, v6_flush_kern_cache_all
        __INITDATA
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 39e3fb3db801..cd956647c21a 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -33,6 +33,24 @@ ENTRY(v7_flush_icache_all)
        mov     pc, lr
 ENDPROC(v7_flush_icache_all)
+ /*
+ *     v7_flush_dcache_louis()
+ *
+ *     Flush the D-cache up to the Level of Unification Inner Shareable
+ *
+ *     Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ */
+ENTRY(v7_flush_dcache_louis)
+        dmb                                     @ ensure ordering with previous memory accesses
+        mrc     p15, 1, r0, c0, c0, 1           @ read clidr, r0 = clidr
+        ands    r3, r0, #0xe00000               @ extract LoUIS from clidr
+        mov     r3, r3, lsr #20                 @ r3 = LoUIS * 2
+        moveq   pc, lr                          @ return if level == 0
+        mov     r10, #0                         @ r10 (starting level) = 0
+        b       flush_levels                    @ start flushing cache levels
+ENDPROC(v7_flush_dcache_louis)
 /*
 *      v7_flush_dcache_all()
 *
@@ -49,7 +67,7 @@ ENTRY(v7_flush_dcache_all)
        mov     r3, r3, lsr #23                 @ left align loc bit field
        beq     finished                        @ if loc is 0, then no need to clean
        mov     r10, #0                         @ start clean at cache level 0
-loop1:
+flush_levels:
        add     r2, r10, r10, lsr #1            @ work out 3x current cache level
        mov     r1, r0, lsr r2                  @ extract cache type bits from clidr
        and     r1, r1, #7                      @ mask of the bits for current cache only
@@ -71,9 +89,9 @@ loop1:
        clz     r5, r4                          @ find bit position of way size increment
        ldr     r7, =0x7fff
        ands    r7, r7, r1, lsr #13             @ extract max number of the index size
-loop2:
+loop1:
        mov     r9, r4                          @ create working copy of max way size
-loop3:
+loop2:
 ARM(   orr     r11, r10, r9, lsl r5    )       @ factor way and cache number into r11
 THUMB( lsl     r6, r9, r5              )
 THUMB( orr     r11, r10, r6            )       @ factor way and cache number into r11
@@ -82,13 +100,13 @@ loop3:
 THUMB( orr     r11, r11, r6            )       @ factor index number into r11
        mcr     p15, 0, r11, c7, c14, 2         @ clean & invalidate by set/way
        subs    r9, r9, #1                      @ decrement the way
-        bge     loop3
-        subs    r7, r7, #1                      @ decrement the index
        bge     loop2
+        subs    r7, r7, #1                      @ decrement the index
+        bge     loop1
 skip:
        add     r10, r10, #2                    @ increment cache number
        cmp     r3, r10
-        bgt     loop1
+        bgt     flush_levels
 finished:
        mov     r10, #0                         @ swith back to cache level 0
        mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
@@ -120,6 +138,24 @@ ENTRY(v7_flush_kern_cache_all)
        mov     pc, lr
 ENDPROC(v7_flush_kern_cache_all)
+ /*
+ *     v7_flush_kern_cache_louis(void)
+ *
+ *     Flush the data cache up to Level of Unification Inner Shareable.
+ *     Invalidate the I-cache to the point of unification.
+ */
+ENTRY(v7_flush_kern_cache_louis)
+ ARM(   stmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
+ THUMB( stmfd   sp!, {r4-r7, r9-r11, lr}        )
+        bl      v7_flush_dcache_louis
+        mov     r0, #0
+        ALT_SMP(mcr     p15, 0, r0, c7, c1, 0)  @ invalidate I-cache inner shareable
+        ALT_UP(mcr      p15, 0, r0, c7, c5, 0)  @ I+BTB cache invalidate
+ ARM(   ldmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
+ THUMB( ldmfd   sp!, {r4-r7, r9-r11, lr}        )
+        mov     pc, lr
+ENDPROC(v7_flush_kern_cache_louis)
 /*
 *      v7_flush_cache_all()
 *
@@ -211,6 +247,9 @@ ENTRY(v7_coherent_user_range)
 * isn't mapped, fail with -EFAULT.
 */
 9001:
+#ifdef CONFIG_ARM_ERRATA_775420
+        dsb
+#endif
        mov     r0, #-EFAULT
        mov     pc, lr
 UNWIND(.fnend          )
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 13f555d62491..477a2d23ddf1 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -73,11 +73,18 @@ static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
             unsigned long offset, size_t size, enum dma_data_direction dir,
             struct dma_attrs *attrs)
 {
-        if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+        if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                __dma_page_cpu_to_dev(page, offset, size, dir);
        return pfn_to_dma(dev, page_to_pfn(page)) + offset;
 }
+static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
+             unsigned long offset, size_t size, enum dma_data_direction dir,
+             struct dma_attrs *attrs)
+{
+        return pfn_to_dma(dev, page_to_pfn(page)) + offset;
+}
 /**
 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
@@ -96,7 +103,7 @@ static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
                size_t size, enum dma_data_direction dir,
                struct dma_attrs *attrs)
 {
-        if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+        if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
                                      handle & ~PAGE_MASK, size, dir);
 }
@@ -106,8 +113,7 @@ static void arm_dma_sync_single_for_cpu(struct device *dev,
 {
        unsigned int offset = handle & (PAGE_SIZE - 1);
        struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
-        if (!arch_is_coherent())
+        __dma_page_dev_to_cpu(page, offset, size, dir);
-                __dma_page_dev_to_cpu(page, offset, size, dir);
 }
 static void arm_dma_sync_single_for_device(struct device *dev,
@@ -115,8 +121,7 @@ static void arm_dma_sync_single_for_device(struct device *dev,
 {
        unsigned int offset = handle & (PAGE_SIZE - 1);
        struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
-        if (!arch_is_coherent())
+        __dma_page_cpu_to_dev(page, offset, size, dir);
-                __dma_page_cpu_to_dev(page, offset, size, dir);
 }
 static int arm_dma_set_mask(struct device *dev, u64 dma_mask);
@@ -138,6 +143,22 @@ struct dma_map_ops arm_dma_ops = {
 };
 EXPORT_SYMBOL(arm_dma_ops);
+static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
+        dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
+static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
+                                  dma_addr_t handle, struct dma_attrs *attrs);
+struct dma_map_ops arm_coherent_dma_ops = {
+        .alloc                  = arm_coherent_dma_alloc,
+        .free                   = arm_coherent_dma_free,
+        .mmap                   = arm_dma_mmap,
+        .get_sgtable            = arm_dma_get_sgtable,
+        .map_page               = arm_coherent_dma_map_page,
+        .map_sg                 = arm_dma_map_sg,
+        .set_dma_mask           = arm_dma_set_mask,
+};
+EXPORT_SYMBOL(arm_coherent_dma_ops);
 static u64 get_coherent_dma_mask(struct device *dev)
 {
        u64 mask = (u64)arm_dma_limit;
@@ -586,7 +607,7 @@ static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
-                         gfp_t gfp, pgprot_t prot, const void *caller)
+                         gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
 {
        u64 mask = get_coherent_dma_mask(dev);
        struct page *page;
@@ -619,7 +640,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
        *handle = DMA_ERROR_CODE;
        size = PAGE_ALIGN(size);
-        if (arch_is_coherent() || nommu())
+        if (is_coherent || nommu())
                addr = __alloc_simple_buffer(dev, size, gfp, &page);
        else if (gfp & GFP_ATOMIC)
                addr = __alloc_from_pool(size, &page);
@@ -647,7 +668,20 @@ void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
        if (dma_alloc_from_coherent(dev, size, handle, &memory))
                return memory;
-        return __dma_alloc(dev, size, handle, gfp, prot,
+        return __dma_alloc(dev, size, handle, gfp, prot, false,
+                           __builtin_return_address(0));
+}
+static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
+        dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
+{
+        pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
+        void *memory;
+        if (dma_alloc_from_coherent(dev, size, handle, &memory))
+                return memory;
+        return __dma_alloc(dev, size, handle, gfp, prot, true,
                           __builtin_return_address(0));
 }
@@ -684,8 +718,9 @@ int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
 /*
 * Free a buffer as defined by the above mapping.
 */
-void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
+static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
-                  dma_addr_t handle, struct dma_attrs *attrs)
+                           dma_addr_t handle, struct dma_attrs *attrs,
+                           bool is_coherent)
 {
        struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
@@ -694,7 +729,7 @@ void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
        size = PAGE_ALIGN(size);
-        if (arch_is_coherent() || nommu()) {
+        if (is_coherent || nommu()) {
                __dma_free_buffer(page, size);
        } else if (__free_from_pool(cpu_addr, size)) {
                return;
@@ -710,6 +745,18 @@ void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
        }
 }
+void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
+                  dma_addr_t handle, struct dma_attrs *attrs)
+{
+        __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
+}
+static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
+                                  dma_addr_t handle, struct dma_attrs *attrs)
+{
+        __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
+}
 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
                 void *cpu_addr, dma_addr_t handle, size_t size,
                 struct dma_attrs *attrs)
@@ -1012,11 +1059,12 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t
                if (!pages[i])
                        goto error;
-                if (order)
+                if (order) {
                        split_page(pages[i], order);
-                j = 1 << order;
+                        j = 1 << order;
-                while (--j)
+                        while (--j)
-                        pages[i + j] = pages[i] + j;
+                                pages[i + j] = pages[i] + j;
+                }
                __dma_clear_buffer(pages[i], PAGE_SIZE << order);
                i += 1 << order;
@@ -1303,7 +1351,8 @@ static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
 */
 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
                          size_t size, dma_addr_t *handle,
-                          enum dma_data_direction dir, struct dma_attrs *attrs)
+                          enum dma_data_direction dir, struct dma_attrs *attrs,
+                          bool is_coherent)
 {
        struct dma_iommu_mapping *mapping = dev->archdata.mapping;
        dma_addr_t iova, iova_base;
@@ -1322,8 +1371,8 @@ static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
                phys_addr_t phys = page_to_phys(sg_page(s));
                unsigned int len = PAGE_ALIGN(s->offset + s->length);
-                if (!arch_is_coherent() &&
+                if (!is_coherent &&
-                    !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+                        !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                        __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
                ret = iommu_map(mapping->domain, iova, phys, len, 0);
@@ -1341,20 +1390,9 @@ fail:
        return ret;
 }
-/**
+static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
- * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
+                     enum dma_data_direction dir, struct dma_attrs *attrs,
- * @dev: valid struct device pointer
+                     bool is_coherent)
- * @sg: list of buffers
- * @nents: number of buffers to map
- * @dir: DMA transfer direction
- *
- * Map a set of buffers described by scatterlist in streaming mode for DMA.
- * The scatter gather list elements are merged together (if possible) and
- * tagged with the appropriate dma address and length. They are obtained via
- * sg_dma_{address,length}.
- */
-int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-                     enum dma_data_direction dir, struct dma_attrs *attrs)
 {
        struct scatterlist *s = sg, *dma = sg, *start = sg;
        int i, count = 0;
@@ -1370,7 +1408,7 @@ int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
                if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
                        if (__map_sg_chunk(dev, start, size, &dma->dma_address,
-                            dir, attrs) < 0)
+                            dir, attrs, is_coherent) < 0)
                                goto bad_mapping;
                        dma->dma_address += offset;
@@ -1383,7 +1421,8 @@ int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
                }
                size += s->length;
        }
-        if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs) < 0)
+        if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
+                is_coherent) < 0)
                goto bad_mapping;
        dma->dma_address += offset;
@@ -1398,17 +1437,44 @@ bad_mapping:
 }
 /**
- * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
+ * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
 * @dev: valid struct device pointer
 * @sg: list of buffers
- * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
+ * @nents: number of buffers to map
- * @dir: DMA transfer direction (same as was passed to dma_map_sg)
+ * @dir: DMA transfer direction
 *
- * Unmap a set of streaming mode DMA translations.  Again, CPU access
+ * Map a set of i/o coherent buffers described by scatterlist in streaming
- * rules concerning calls here are the same as for dma_unmap_single().
+ * mode for DMA. The scatter gather list elements are merged together (if
+ * possible) and tagged with the appropriate dma address and length. They are
+ * obtained via sg_dma_{address,length}.
 */
-void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
+int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
-                        enum dma_data_direction dir, struct dma_attrs *attrs)
+                int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+        return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
+}
+/**
+ * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
+ * @dev: valid struct device pointer
+ * @sg: list of buffers
+ * @nents: number of buffers to map
+ * @dir: DMA transfer direction
+ *
+ * Map a set of buffers described by scatterlist in streaming mode for DMA.
+ * The scatter gather list elements are merged together (if possible) and
+ * tagged with the appropriate dma address and length. They are obtained via
+ * sg_dma_{address,length}.
+ */
+int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
+                int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+        return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
+}
+static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
+                int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
+                bool is_coherent)
 {
        struct scatterlist *s;
        int i;
@@ -1417,7 +1483,7 @@ void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
                if (sg_dma_len(s))
                        __iommu_remove_mapping(dev, sg_dma_address(s),
                                               sg_dma_len(s));
-                if (!arch_is_coherent() &&
+                if (!is_coherent &&
                    !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                        __dma_page_dev_to_cpu(sg_page(s), s->offset,
                                              s->length, dir);
@@ -1425,6 +1491,38 @@ void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
 }
 /**
+ * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
+ * @dev: valid struct device pointer
+ * @sg: list of buffers
+ * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
+ * @dir: DMA transfer direction (same as was passed to dma_map_sg)
+ *
+ * Unmap a set of streaming mode DMA translations.  Again, CPU access
+ * rules concerning calls here are the same as for dma_unmap_single().
+ */
+void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
+                int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+        __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
+}
+/**
+ * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
+ * @dev: valid struct device pointer
+ * @sg: list of buffers
+ * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
+ * @dir: DMA transfer direction (same as was passed to dma_map_sg)
+ *
+ * Unmap a set of streaming mode DMA translations.  Again, CPU access
+ * rules concerning calls here are the same as for dma_unmap_single().
+ */
+void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
+                        enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+        __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
+}
+/**
 * arm_iommu_sync_sg_for_cpu
 * @dev: valid struct device pointer
 * @sg: list of buffers
@@ -1438,8 +1536,7 @@ void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
        int i;
        for_each_sg(sg, s, nents, i)
-                if (!arch_is_coherent())
+                __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
-                        __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
 }
@@ -1457,22 +1554,21 @@ void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
        int i;
        for_each_sg(sg, s, nents, i)
-                if (!arch_is_coherent())
+                __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
-                        __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
 }
 /**
- * arm_iommu_map_page
+ * arm_coherent_iommu_map_page
 * @dev: valid struct device pointer
 * @page: page that buffer resides in
 * @offset: offset into page for start of buffer
 * @size: size of buffer to map
 * @dir: DMA transfer direction
 *
- * IOMMU aware version of arm_dma_map_page()
+ * Coherent IOMMU aware version of arm_dma_map_page()
 */
-static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
+static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
             unsigned long offset, size_t size, enum dma_data_direction dir,
             struct dma_attrs *attrs)
 {
@@ -1480,9 +1576,6 @@ static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
        dma_addr_t dma_addr;
        int ret, len = PAGE_ALIGN(size + offset);
-        if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
-                __dma_page_cpu_to_dev(page, offset, size, dir);
        dma_addr = __alloc_iova(mapping, len);
        if (dma_addr == DMA_ERROR_CODE)
                return dma_addr;
@@ -1498,6 +1591,51 @@ fail:
 }
 /**
+ * arm_iommu_map_page
+ * @dev: valid struct device pointer
+ * @page: page that buffer resides in
+ * @offset: offset into page for start of buffer
+ * @size: size of buffer to map
+ * @dir: DMA transfer direction
+ *
+ * IOMMU aware version of arm_dma_map_page()
+ */
+static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
+             unsigned long offset, size_t size, enum dma_data_direction dir,
+             struct dma_attrs *attrs)
+{
+        if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+                __dma_page_cpu_to_dev(page, offset, size, dir);
+        return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
+}
+/**
+ * arm_coherent_iommu_unmap_page
+ * @dev: valid struct device pointer
+ * @handle: DMA address of buffer
+ * @size: size of buffer (same as passed to dma_map_page)
+ * @dir: DMA transfer direction (same as passed to dma_map_page)
+ *
+ * Coherent IOMMU aware version of arm_dma_unmap_page()
+ */
+static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
+                size_t size, enum dma_data_direction dir,
+                struct dma_attrs *attrs)
+{
+        struct dma_iommu_mapping *mapping = dev->archdata.mapping;
+        dma_addr_t iova = handle & PAGE_MASK;
+        int offset = handle & ~PAGE_MASK;
+        int len = PAGE_ALIGN(size + offset);
+        if (!iova)
+                return;
+        iommu_unmap(mapping->domain, iova, len);
+        __free_iova(mapping, iova, len);
+}
+/**
 * arm_iommu_unmap_page
 * @dev: valid struct device pointer
 * @handle: DMA address of buffer
@@ -1519,7 +1657,7 @@ static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
        if (!iova)
                return;
-        if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+        if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                __dma_page_dev_to_cpu(page, offset, size, dir);
        iommu_unmap(mapping->domain, iova, len);
@@ -1537,8 +1675,7 @@ static void arm_iommu_sync_single_for_cpu(struct device *dev,
        if (!iova)
                return;
-        if (!arch_is_coherent())
+        __dma_page_dev_to_cpu(page, offset, size, dir);
-                __dma_page_dev_to_cpu(page, offset, size, dir);
 }
 static void arm_iommu_sync_single_for_device(struct device *dev,
@@ -1572,6 +1709,19 @@ struct dma_map_ops iommu_ops = {
        .sync_sg_for_device     = arm_iommu_sync_sg_for_device,
 };
+struct dma_map_ops iommu_coherent_ops = {
+        .alloc          = arm_iommu_alloc_attrs,
+        .free           = arm_iommu_free_attrs,
+        .mmap           = arm_iommu_mmap_attrs,
+        .get_sgtable    = arm_iommu_get_sgtable,
+        .map_page       = arm_coherent_iommu_map_page,
+        .unmap_page     = arm_coherent_iommu_unmap_page,
+        .map_sg         = arm_coherent_iommu_map_sg,
+        .unmap_sg       = arm_coherent_iommu_unmap_sg,
+};
 /**
 * arm_iommu_create_mapping
 * @bus: pointer to the bus holding the client device (for IOMMU calls)
@@ -1665,7 +1815,7 @@ int arm_iommu_attach_device(struct device *dev,
        dev->archdata.mapping = mapping;
        set_dma_ops(dev, &iommu_ops);
-        pr_info("Attached IOMMU controller to %s device.\n", dev_name(dev));
+        pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
        return 0;
 }
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 7599e2625c7d..2a5907b5c8d2 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -134,7 +134,6 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
 {
        struct mm_struct *mm = vma->vm_mm;
        struct vm_area_struct *mpnt;
-        struct prio_tree_iter iter;
        unsigned long offset;
        pgoff_t pgoff;
        int aliases = 0;
@@ -147,7 +146,7 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
         * cache coherency.
         */
        flush_dcache_mmap_lock(mapping);
-        vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
+        vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
                /*
                 * If this VMA is not in our MM, we can ignore it.
                 * Note that we intentionally mask out the VMA
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index c3bd83450227..5dbf13f954f6 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -336,6 +336,7 @@ retry:
                        /* Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk
                        * of starvation. */
                        flags &= ~FAULT_FLAG_ALLOW_RETRY;
+                        flags |= FAULT_FLAG_TRIED;
                        goto retry;
                }
        }
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 40ca11ed6e5f..1c8f7f564175 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -196,7 +196,6 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p
 {
        struct mm_struct *mm = current->active_mm;
        struct vm_area_struct *mpnt;
-        struct prio_tree_iter iter;
        pgoff_t pgoff;
        /*
@@ -208,7 +207,7 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p
        pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
        flush_dcache_mmap_lock(mapping);
-        vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
+        vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
                unsigned long offset;
                /*
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9aec41fa80ae..ad722f1208a5 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -324,7 +324,7 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align)
        BUG_ON(!arm_memblock_steal_permitted);
-        phys = memblock_alloc(size, align);
+        phys = memblock_alloc_base(size, align, MEMBLOCK_ALLOC_ANYWHERE);
        memblock_free(phys, size);
        memblock_remove(phys, size);
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 566750fa57d4..5dcc2fd46c46 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -36,6 +36,7 @@
 #include <asm/system_info.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include "mm.h"
 int ioremap_page(unsigned long virt, unsigned long phys,
@@ -247,6 +248,7 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
        if (!area)
                return NULL;
        addr = (unsigned long)area->addr;
+        area->phys_addr = __pfn_to_phys(pfn);
 #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
        if (DOMAIN_IO == 0 &&
@@ -383,3 +385,16 @@ void __arm_iounmap(volatile void __iomem *io_addr)
        arch_iounmap(io_addr);
 }
 EXPORT_SYMBOL(__arm_iounmap);
+#ifdef CONFIG_PCI
+int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr)
+{
+        BUG_ON(offset + SZ_64K > IO_SPACE_LIMIT);
+        return ioremap_page_range(PCI_IO_VIRT_BASE + offset,
+                                  PCI_IO_VIRT_BASE + offset + SZ_64K,
+                                  phys_addr,
+                                  __pgprot(get_mem_type(MT_DEVICE)->prot_pte));
+}
+EXPORT_SYMBOL_GPL(pci_ioremap_io);
+#endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index c2fa21d0103e..941dfb9e9a78 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -31,6 +31,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include "mm.h"
@@ -216,7 +217,7 @@ static struct mem_type mem_types[] = {
                .prot_l1        = PMD_TYPE_TABLE,
                .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
                .domain         = DOMAIN_IO,
-        },      
+        },
        [MT_DEVICE_WC] = {      /* ioremap_wc */
                .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
                .prot_l1        = PMD_TYPE_TABLE,
@@ -422,17 +423,6 @@ static void __init build_mem_type_table(void)
        vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
        /*
-         * Enable CPU-specific coherency if supported.
-         * (Only available on XSC3 at the moment.)
-         */
-        if (arch_is_coherent() && cpu_is_xsc3()) {
-                mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-                mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
-                mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
-                mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
-                mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
-        }
-        /*
         * ARMv6 and above have extended page tables.
         */
        if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
@@ -777,14 +767,27 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
                create_mapping(md);
                vm->addr = (void *)(md->virtual & PAGE_MASK);
                vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
-                vm->phys_addr = __pfn_to_phys(md->pfn); 
+                vm->phys_addr = __pfn_to_phys(md->pfn);
-                vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 
+                vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
                vm->flags |= VM_ARM_MTYPE(md->type);
                vm->caller = iotable_init;
                vm_area_add_early(vm++);
        }
 }
+void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
+                                  void *caller)
+{
+        struct vm_struct *vm;
+        vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
+        vm->addr = (void *)addr;
+        vm->size = size;
+        vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
+        vm->caller = caller;
+        vm_area_add_early(vm);
+}
 #ifndef CONFIG_ARM_LPAE
 /*
@@ -802,14 +805,7 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
 static void __init pmd_empty_section_gap(unsigned long addr)
 {
-        struct vm_struct *vm;
+        vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
-        vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
-        vm->addr = (void *)addr;
-        vm->size = SECTION_SIZE;
-        vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
-        vm->caller = pmd_empty_section_gap;
-        vm_area_add_early(vm);
 }
 static void __init fill_pmd_gaps(void)
@@ -858,6 +854,28 @@ static void __init fill_pmd_gaps(void)
 #define fill_pmd_gaps() do { } while (0)
 #endif
+#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
+static void __init pci_reserve_io(void)
+{
+        struct vm_struct *vm;
+        unsigned long addr;
+        /* we're still single threaded hence no lock needed here */
+        for (vm = vmlist; vm; vm = vm->next) {
+                if (!(vm->flags & VM_ARM_STATIC_MAPPING))
+                        continue;
+                addr = (unsigned long)vm->addr;
+                addr &= ~(SZ_2M - 1);
+                if (addr == PCI_IO_VIRT_BASE)
+                        return;
+        }
+        vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
+}
+#else
+#define pci_reserve_io() do { } while (0)
+#endif
 static void * __initdata vmalloc_min =
        (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
@@ -1141,6 +1159,9 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
                mdesc->map_io();
        fill_pmd_gaps();
+        /* Reserve fixed i/o space in VMALLOC region */
+        pci_reserve_io();
        /*
         * Finally flush the caches and tlb to ensure that we're in a
         * consistent state wrt the writebuffer.  This also ensures that
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 0650bb87c1e3..2bb61e703d6c 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -368,6 +368,9 @@ ENTRY(arm1020_dma_unmap_area)
        mov     pc, lr
 ENDPROC(arm1020_dma_unmap_area)
+        .globl  arm1020_flush_kern_cache_louis
+        .equ    arm1020_flush_kern_cache_louis, arm1020_flush_kern_cache_all
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions arm1020
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 4188478325a6..8f96aa40f510 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -354,6 +354,9 @@ ENTRY(arm1020e_dma_unmap_area)
        mov     pc, lr
 ENDPROC(arm1020e_dma_unmap_area)
+        .globl  arm1020e_flush_kern_cache_louis
+        .equ    arm1020e_flush_kern_cache_louis, arm1020e_flush_kern_cache_all
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions arm1020e
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 33c68824bff0..8ebe4a469a22 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -343,6 +343,9 @@ ENTRY(arm1022_dma_unmap_area)
        mov     pc, lr
 ENDPROC(arm1022_dma_unmap_area)
+        .globl  arm1022_flush_kern_cache_louis
+        .equ    arm1022_flush_kern_cache_louis, arm1022_flush_kern_cache_all
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions arm1022
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index fbc1d5fc24dc..093fc7e520c3 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -337,6 +337,9 @@ ENTRY(arm1026_dma_unmap_area)
        mov     pc, lr
 ENDPROC(arm1026_dma_unmap_area)
+        .globl  arm1026_flush_kern_cache_louis
+        .equ    arm1026_flush_kern_cache_louis, arm1026_flush_kern_cache_all
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions arm1026
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 1a8c138eb897..2c3b9421ab5e 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -319,6 +319,9 @@ ENTRY(arm920_dma_unmap_area)
        mov     pc, lr
 ENDPROC(arm920_dma_unmap_area)
+        .globl  arm920_flush_kern_cache_louis
+        .equ    arm920_flush_kern_cache_louis, arm920_flush_kern_cache_all
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions arm920
 #endif
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 4c44d7e1c3ca..4464c49d7449 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -321,6 +321,9 @@ ENTRY(arm922_dma_unmap_area)
        mov     pc, lr
 ENDPROC(arm922_dma_unmap_area)
+        .globl  arm922_flush_kern_cache_louis
+        .equ    arm922_flush_kern_cache_louis, arm922_flush_kern_cache_all
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions arm922
 #endif
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index ec5b1180994f..281eb9b9c1d6 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -376,6 +376,9 @@ ENTRY(arm925_dma_unmap_area)
        mov     pc, lr
 ENDPROC(arm925_dma_unmap_area)
+        .globl  arm925_flush_kern_cache_louis
+        .equ    arm925_flush_kern_cache_louis, arm925_flush_kern_cache_all
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions arm925
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index c31e62c606c0..f1803f7e2972 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -339,6 +339,9 @@ ENTRY(arm926_dma_unmap_area)
        mov     pc, lr
 ENDPROC(arm926_dma_unmap_area)
+        .globl  arm926_flush_kern_cache_louis
+        .equ    arm926_flush_kern_cache_louis, arm926_flush_kern_cache_all
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions arm926
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index a613a7dd7146..8da189d4a402 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -267,6 +267,9 @@ ENTRY(arm940_dma_unmap_area)
        mov     pc, lr
 ENDPROC(arm940_dma_unmap_area)
+        .globl  arm940_flush_kern_cache_louis
+        .equ    arm940_flush_kern_cache_louis, arm940_flush_kern_cache_all
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions arm940
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 9f4f2999fdd0..f666cf34075a 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -310,6 +310,9 @@ ENTRY(arm946_dma_unmap_area)
        mov     pc, lr
 ENDPROC(arm946_dma_unmap_area)
+        .globl  arm946_flush_kern_cache_louis
+        .equ    arm946_flush_kern_cache_louis, arm946_flush_kern_cache_all
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions arm946
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 23a8e4c7f2bd..4106b09e0c29 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -415,6 +415,9 @@ ENTRY(feroceon_dma_unmap_area)
        mov     pc, lr
 ENDPROC(feroceon_dma_unmap_area)
+        .globl  feroceon_flush_kern_cache_louis
+        .equ    feroceon_flush_kern_cache_louis, feroceon_flush_kern_cache_all
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions feroceon
@@ -431,6 +434,7 @@ ENDPROC(feroceon_dma_unmap_area)
        range_alias flush_icache_all
        range_alias flush_user_cache_all
        range_alias flush_kern_cache_all
+        range_alias flush_kern_cache_louis
        range_alias flush_user_cache_range
        range_alias coherent_kern_range
        range_alias coherent_user_range
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 2d8ff3ad86d3..b29a2265af01 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -299,6 +299,7 @@ ENTRY(\name\()_processor_functions)
 ENTRY(\name\()_cache_fns)
        .long   \name\()_flush_icache_all
        .long   \name\()_flush_kern_cache_all
+        .long   \name\()_flush_kern_cache_louis
        .long   \name\()_flush_user_cache_all
        .long   \name\()_flush_user_cache_range
        .long   \name\()_coherent_kern_range
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index fbb2124a547d..82f9cdc751d6 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -303,6 +303,9 @@ ENTRY(mohawk_dma_unmap_area)
        mov     pc, lr
 ENDPROC(mohawk_dma_unmap_area)
+        .globl  mohawk_flush_kern_cache_louis
+        .equ    mohawk_flush_kern_cache_louis, mohawk_flush_kern_cache_all
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions mohawk
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index c2e2b66f72b5..846d279f3176 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -172,7 +172,7 @@ __v7_ca15mp_setup:
 __v7_setup:
        adr     r12, __v7_setup_stack           @ the local stack
        stmia   r12, {r0-r5, r7, r9, r11, lr}
-        bl      v7_flush_dcache_all
+        bl      v7_flush_dcache_louis
        ldmia   r12, {r0-r5, r7, r9, r11, lr}
        mrc     p15, 0, r0, c0, c0, 0           @ read main ID register
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index b0d57869da2d..eb93d6487f35 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -337,6 +337,9 @@ ENTRY(xsc3_dma_unmap_area)
        mov     pc, lr
 ENDPROC(xsc3_dma_unmap_area)
+        .globl  xsc3_flush_kern_cache_louis
+        .equ    xsc3_flush_kern_cache_louis, xsc3_flush_kern_cache_all
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions xsc3
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 4ffebaa595ee..25510361aa18 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -410,6 +410,9 @@ ENTRY(xscale_dma_unmap_area)
        mov     pc, lr
 ENDPROC(xscale_dma_unmap_area)
+        .globl  xscale_flush_kern_cache_louis
+        .equ    xscale_flush_kern_cache_louis, xscale_flush_kern_cache_all
        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
        define_cache_functions xscale
@@ -439,6 +442,7 @@ ENDPROC(xscale_dma_unmap_area)
        a0_alias flush_icache_all
        a0_alias flush_user_cache_all
        a0_alias flush_kern_cache_all
+        a0_alias flush_kern_cache_louis
        a0_alias flush_user_cache_range
        a0_alias coherent_kern_range
        a0_alias coherent_user_range
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index 8daae9b230ea..362474b5c40d 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -192,30 +192,24 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
        if (nr != 0)
                return 0;
-        res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL);
+        res = kzalloc(sizeof(struct resource), GFP_KERNEL);
        if (!res)
                panic("PCI: unable to alloc resources");
-        res[0].start = IOP3XX_PCI_LOWER_IO_PA;
+        res->start = IOP3XX_PCI_LOWER_MEM_PA;
-        res[0].end   = IOP3XX_PCI_LOWER_IO_PA + IOP3XX_PCI_IO_WINDOW_SIZE - 1;
+        res->end   = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
-        res[0].name  = "IOP3XX PCI I/O Space";
+        res->name  = "IOP3XX PCI Memory Space";
-        res[0].flags = IORESOURCE_IO;
+        res->flags = IORESOURCE_MEM;
-        request_resource(&ioport_resource, &res[0]);
+        request_resource(&iomem_resource, res);
-        res[1].start = IOP3XX_PCI_LOWER_MEM_PA;
-        res[1].end   = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
-        res[1].name  = "IOP3XX PCI Memory Space";
-        res[1].flags = IORESOURCE_MEM;
-        request_resource(&iomem_resource, &res[1]);
        /*
         * Use whatever translation is already setup.
         */
        sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
-        sys->io_offset  = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR;
-        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
+        pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
-        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+        pci_ioremap_io(0, IOP3XX_PCI_LOWER_IO_PA);
        return 1;
 }
@@ -367,7 +361,6 @@ void __init iop3xx_pci_preinit_cond(void)
 void __init iop3xx_pci_preinit(void)
 {
-        pcibios_min_io = 0;
        pcibios_min_mem = 0;
        iop3xx_atu_disable();
diff --git a/arch/arm/plat-iop/pmu.c b/arch/arm/plat-iop/pmu.c
index a2024b8685a1..ad9f9744a82d 100644
--- a/arch/arm/plat-iop/pmu.c
+++ b/arch/arm/plat-iop/pmu.c
@@ -9,7 +9,6 @@
 */
 #include <linux/platform_device.h>
-#include <asm/pmu.h>
 #include <mach/irqs.h>
 static struct resource pmu_resource = {
@@ -26,7 +25,7 @@ static struct resource pmu_resource = {
 static struct platform_device pmu_device = {
        .name           = "arm-pmu",
-        .id             = ARM_PMU_DEVICE_CPU,
+        .id             = -1,
        .resource       = &pmu_resource,
        .num_resources  = 1,
 };
diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/plat-iop/setup.c
index bade586fed0f..5b217f460f18 100644
--- a/arch/arm/plat-iop/setup.c
+++ b/arch/arm/plat-iop/setup.c
@@ -25,11 +25,6 @@ static struct map_desc iop3xx_std_desc[] __initdata = {
                .pfn            = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE),
                .length         = IOP3XX_PERIPHERAL_SIZE,
                .type           = MT_UNCACHED,
-         }, {   /* PCI IO space */
-                .virtual        = IOP3XX_PCI_LOWER_IO_VA,
-                .pfn            = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA),
-                .length         = IOP3XX_PCI_IO_WINDOW_SIZE,
-                .type           = MT_DEVICE,
         },
 };
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 6ac720031150..149237e24850 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,7 +3,7 @@
 #
 # Common support
-obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
+obj-y := time.o devices.o cpu.o system.o irq-common.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
deleted file mode 100644
index 5079787273d2..000000000000
--- a/arch/arm/plat-mxc/clock.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * Based on arch/arm/plat-omap/clock.c
- *
- * Copyright (C) 2004 - 2005 Nokia corporation
- * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-/* #define DEBUG */
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-#include <linux/proc_fs.h>
-#include <linux/semaphore.h>
-#include <linux/string.h>
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#ifndef CONFIG_COMMON_CLK
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-/*-------------------------------------------------------------------------
- * Standard clock functions defined in include/linux/clk.h
- *-------------------------------------------------------------------------*/
-static void __clk_disable(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return;
-        WARN_ON(!clk->usecount);
-        if (!(--clk->usecount)) {
-                if (clk->disable)
-                        clk->disable(clk);
-                __clk_disable(clk->parent);
-                __clk_disable(clk->secondary);
-        }
-}
-static int __clk_enable(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-        if (clk->usecount++ == 0) {
-                __clk_enable(clk->parent);
-                __clk_enable(clk->secondary);
-                if (clk->enable)
-                        clk->enable(clk);
-        }
-        return 0;
-}
-/* This function increments the reference count on the clock and enables the
- * clock if not already enabled. The parent clock tree is recursively enabled
- */
-int clk_enable(struct clk *clk)
-{
-        int ret = 0;
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-        mutex_lock(&clocks_mutex);
-        ret = __clk_enable(clk);
-        mutex_unlock(&clocks_mutex);
-        return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-/* This function decrements the reference count on the clock and disables
- * the clock when reference count is 0. The parent clock tree is
- * recursively disabled
- */
-void clk_disable(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return;
-        mutex_lock(&clocks_mutex);
-        __clk_disable(clk);
-        mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clk_disable);
-/* Retrieve the *current* clock rate. If the clock itself
- * does not provide a special calculation routine, ask
- * its parent and so on, until one is able to return
- * a valid clock rate
- */
-unsigned long clk_get_rate(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return 0UL;
-        if (clk->get_rate)
-                return clk->get_rate(clk);
-        return clk_get_rate(clk->parent);
-}
-EXPORT_SYMBOL(clk_get_rate);
-/* Round the requested clock rate to the nearest supported
- * rate that is less than or equal to the requested rate.
- * This is dependent on the clock's current parent.
- */
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
-                return 0;
-        return clk->round_rate(clk, rate);
-}
-EXPORT_SYMBOL(clk_round_rate);
-/* Set the clock to the requested clock rate. The rate must
- * match a supported rate exactly based on what clk_round_rate returns
- */
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        int ret = -EINVAL;
-        if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
-                return ret;
-        mutex_lock(&clocks_mutex);
-        ret = clk->set_rate(clk, rate);
-        mutex_unlock(&clocks_mutex);
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-/* Set the clock's parent to another clock source */
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        int ret = -EINVAL;
-        struct clk *old;
-        if (clk == NULL || IS_ERR(clk) || parent == NULL ||
-            IS_ERR(parent) || clk->set_parent == NULL)
-                return ret;
-        if (clk->usecount)
-                clk_enable(parent);
-        mutex_lock(&clocks_mutex);
-        ret = clk->set_parent(clk, parent);
-        if (ret == 0) {
-                old = clk->parent;
-                clk->parent = parent;
-        } else {
-                old = parent;
-        }
-        mutex_unlock(&clocks_mutex);
-        if (clk->usecount)
-                clk_disable(old);
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-/* Retrieve the clock's parent clock source */
-struct clk *clk_get_parent(struct clk *clk)
-{
-        struct clk *ret = NULL;
-        if (clk == NULL || IS_ERR(clk))
-                return ret;
-        return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-#else
-/*
- * Lock to protect the clock module (ccm) registers. Used
- * on all i.MXs
- */
-DEFINE_SPINLOCK(imx_ccm_lock);
-#endif /* CONFIG_COMMON_CLK */
-/*
- * Get the resulting clock rate from a PLL register value and the input
- * frequency. PLLs with this register layout can at least be found on
- * MX1, MX21, MX27 and MX31
- *
- *                  mfi + mfn / (mfd + 1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
-{
-        long long ll;
-        int mfn_abs;
-        unsigned int mfi, mfn, mfd, pd;
-        mfi = (reg_val >> 10) & 0xf;
-        mfn = reg_val & 0x3ff;
-        mfd = (reg_val >> 16) & 0x3ff;
-        pd =  (reg_val >> 26) & 0xf;
-        mfi = mfi <= 5 ? 5 : mfi;
-        mfn_abs = mfn;
-        /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
-         * 2's complements number
-         */
-        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
-                mfn_abs = 0x400 - mfn;
-        freq *= 2;
-        freq /= pd + 1;
-        ll = (unsigned long long)freq * mfn_abs;
-        do_div(ll, mfd + 1);
-        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
-                ll = -ll;
-        ll = (freq * mfi) + ll;
-        return ll;
-}
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index 73db34bf588a..b5b6f8083130 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -23,7 +23,6 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <mach/hardware.h>
-#include <mach/clock.h>
 #define CLK32_FREQ      32768
 #define NANOSECOND      (1000 * 1000 * 1000)
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index cb3e3eef55c0..6b46cee2f9cd 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -15,7 +15,11 @@ config IMX_HAVE_PLATFORM_GPIO_KEYS
 config IMX_HAVE_PLATFORM_IMX21_HCD
        bool
-        
+config IMX_HAVE_PLATFORM_IMX27_CODA
+        bool
+        default y if SOC_IMX27
 config IMX_HAVE_PLATFORM_IMX2_WDT
        bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index c11ac8472beb..76f3195475d0 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
 obj-y += platform-gpio-mxc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
 obj-y += platform-imx-dma.o
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
index 2020d84956c3..d390f00bd294 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-uart.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -87,7 +87,7 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
 #ifdef CONFIG_SOC_IMX35
 const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
 #define imx35_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K)
+        imx_imx_uart_1irq_data_entry(MX35, _id, _hwid, SZ_16K)
        imx35_imx_uart_data_entry(0, 1),
        imx35_imx_uart_data_entry(1, 2),
        imx35_imx_uart_data_entry(2, 3),
diff --git a/arch/arm/plat-mxc/devices/platform-imx27-coda.c b/arch/arm/plat-mxc/devices/platform-imx27-coda.c
new file mode 100644
index 000000000000..8b12aacdf396
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx27-coda.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2012 Vista Silicon
+ * Javier Martin <javier.martin@vista-silicon.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+#ifdef CONFIG_SOC_IMX27
+const struct imx_imx27_coda_data imx27_coda_data __initconst = {
+        .iobase = MX27_VPU_BASE_ADDR,
+        .iosize = SZ_512,
+        .irq = MX27_INT_VPU,
+};
+#endif
+struct platform_device *__init imx_add_imx27_coda(
+                const struct imx_imx27_coda_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device_dmamask("coda-imx27", 0, res, 2, NULL,
+                                        0, DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
index 1568f39fba8b..95b75cc70515 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -63,10 +63,6 @@ struct platform_device *__init imx_add_mxc_nand(
        /* AXI has to come first, that's how the mxc_nand driver expect it */
        struct resource res[] = {
                {
-                        .start = data->axibase,
-                        .end = data->axibase + SZ_16K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
                        .start = data->iobase,
                        .end = data->iobase + data->iosize - 1,
                        .flags = IORESOURCE_MEM,
@@ -74,10 +70,13 @@ struct platform_device *__init imx_add_mxc_nand(
                        .start = data->irq,
                        .end = data->irq,
                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = data->axibase,
+                        .end = data->axibase + SZ_16K - 1,
+                        .flags = IORESOURCE_MEM,
                },
        };
        return imx_add_platform_device("mxc_nand", data->id,
-                        res + !data->axibase,
+                        res, ARRAY_SIZE(res) - !data->axibase,
-                        ARRAY_SIZE(res) - !data->axibase,
                        pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
index 5955f5da82ee..3793e475cd95 100644
--- a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
+++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
@@ -8,7 +8,7 @@
 #include <mach/hardware.h>
 #include <mach/devices-common.h>
-#include <mach/esdhc.h>
+#include <linux/platform_data/mmc-esdhc-imx.h>
 #define imx_sdhci_esdhc_imx_data_entry_single(soc, _devid, _id, hwid) \
        {                                                               \
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
deleted file mode 100644
index bd940c795cbb..000000000000
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-#ifndef __ASM_ARCH_MXC_CLOCK_H__
-#define __ASM_ARCH_MXC_CLOCK_H__
-#ifndef __ASSEMBLY__
-#include <linux/list.h>
-#ifndef CONFIG_COMMON_CLK
-struct module;
-struct clk {
-        int id;
-        /* Source clock this clk depends on */
-        struct clk *parent;
-        /* Secondary clock to enable/disable with this clock */
-        struct clk *secondary;
-        /* Reference count of clock enable/disable */
-        __s8 usecount;
-        /* Register bit position for clock's enable/disable control. */
-        u8 enable_shift;
-        /* Register address for clock's enable/disable control. */
-        void __iomem *enable_reg;
-        u32 flags;
-        /* get the current clock rate (always a fresh value) */
-        unsigned long (*get_rate) (struct clk *);
-        /* Function ptr to set the clock to a new rate. The rate must match a
-           supported rate returned from round_rate. Leave blank if clock is not
-           programmable */
-        int (*set_rate) (struct clk *, unsigned long);
-        /* Function ptr to round the requested clock rate to the nearest
-           supported rate that is less than or equal to the requested rate. */
-        unsigned long (*round_rate) (struct clk *, unsigned long);
-        /* Function ptr to enable the clock. Leave blank if clock can not
-           be gated. */
-        int (*enable) (struct clk *);
-        /* Function ptr to disable the clock. Leave blank if clock can not
-           be gated. */
-        void (*disable) (struct clk *);
-        /* Function ptr to set the parent clock of the clock. */
-        int (*set_parent) (struct clk *, struct clk *);
-};
-int clk_register(struct clk *clk);
-void clk_unregister(struct clk *clk);
-#endif /* CONFIG_COMMON_CLK */
-extern spinlock_t imx_ccm_lock;
-unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref);
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 7128e9710417..ead901814c0d 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -52,7 +52,6 @@ extern void imx31_soc_init(void);
 extern void imx35_soc_init(void);
 extern void imx50_soc_init(void);
 extern void imx51_soc_init(void);
-extern void imx53_soc_init(void);
 extern void imx51_init_late(void);
 extern void imx53_init_late(void);
 extern void epit_timer_init(void __iomem *base, int irq);
@@ -137,14 +136,11 @@ extern void imx_src_prepare_restart(void);
 extern void imx_gpc_init(void);
 extern void imx_gpc_pre_suspend(void);
 extern void imx_gpc_post_resume(void);
-extern void imx51_babbage_common_init(void);
-extern void imx53_ard_common_init(void);
-extern void imx53_evk_common_init(void);
-extern void imx53_qsb_common_init(void);
-extern void imx53_smd_common_init(void);
 extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
 extern void imx6q_clock_map_io(void);
+extern void imx_cpu_die(unsigned int cpu);
 #ifdef CONFIG_PM
 extern void imx6q_pm_init(void);
 extern void imx51_pm_init(void);
@@ -161,4 +157,6 @@ extern int mx51_neon_fixup(void);
 static inline int mx51_neon_fixup(void) { return 0; }
 #endif
+extern struct smp_operations imx_smp_ops;
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index a7f5bb1084d7..eaf79d220c9a 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -9,7 +9,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/init.h>
-#include <mach/sdma.h>
+#include <linux/platform_data/dma-imx-sdma.h>
 extern struct device mxc_aips_bus;
 extern struct device mxc_ahb_bus;
@@ -74,7 +74,7 @@ struct platform_device *__init imx_add_fsl_usb2_udc(
 struct platform_device *__init imx_add_gpio_keys(
                const struct gpio_keys_platform_data *pdata);
-#include <mach/mx21-usbhost.h>
+#include <linux/platform_data/usb-mx2.h>
 struct imx_imx21_hcd_data {
        resource_size_t iobase;
        resource_size_t irq;
@@ -83,6 +83,14 @@ struct platform_device *__init imx_add_imx21_hcd(
                const struct imx_imx21_hcd_data *data,
                const struct mx21_usbh_platform_data *pdata);
+struct imx_imx27_coda_data {
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_imx27_coda(
+                const struct imx_imx27_coda_data *data);
 struct imx_imx2_wdt_data {
        int id;
        resource_size_t iobase;
@@ -98,7 +106,7 @@ struct imx_imxdi_rtc_data {
 struct platform_device *__init imx_add_imxdi_rtc(
                const struct imx_imxdi_rtc_data *data);
-#include <mach/imxfb.h>
+#include <linux/platform_data/video-imxfb.h>
 struct imx_imx_fb_data {
        resource_size_t iobase;
        resource_size_t iosize;
@@ -108,7 +116,7 @@ struct platform_device *__init imx_add_imx_fb(
                const struct imx_imx_fb_data *data,
                const struct imx_fb_platform_data *pdata);
-#include <mach/i2c.h>
+#include <linux/platform_data/i2c-imx.h>
 struct imx_imx_i2c_data {
        int id;
        resource_size_t iobase;
@@ -129,7 +137,7 @@ struct platform_device *__init imx_add_imx_keypad(
                const struct imx_imx_keypad_data *data,
                const struct matrix_keymap_data *pdata);
-#include <mach/ssi.h>
+#include <linux/platform_data/asoc-imx-ssi.h>
 struct imx_imx_ssi_data {
        int id;
        resource_size_t iobase;
@@ -144,7 +152,7 @@ struct platform_device *__init imx_add_imx_ssi(
                const struct imx_imx_ssi_data *data,
                const struct imx_ssi_platform_data *pdata);
-#include <mach/imx-uart.h>
+#include <linux/platform_data/serial-imx.h>
 struct imx_imx_uart_3irq_data {
        int id;
        resource_size_t iobase;
@@ -167,7 +175,7 @@ struct platform_device *__init imx_add_imx_uart_1irq(
                const struct imx_imx_uart_1irq_data *data,
                const struct imxuart_platform_data *pdata);
-#include <mach/usb.h>
+#include <linux/platform_data/usb-imx_udc.h>
 struct imx_imx_udc_data {
        resource_size_t iobase;
        resource_size_t iosize;
@@ -183,8 +191,8 @@ struct platform_device *__init imx_add_imx_udc(
                const struct imx_imx_udc_data *data,
                const struct imxusb_platform_data *pdata);
-#include <mach/mx3fb.h>
+#include <linux/platform_data/video-mx3fb.h>
-#include <mach/mx3_camera.h>
+#include <linux/platform_data/camera-mx3.h>
 struct imx_ipu_core_data {
        resource_size_t iobase;
        resource_size_t synirq;
@@ -199,7 +207,7 @@ struct platform_device *__init imx_add_mx3_sdc_fb(
                const struct imx_ipu_core_data *data,
                struct mx3fb_platform_data *pdata);
-#include <mach/mx1_camera.h>
+#include <linux/platform_data/camera-mx1.h>
 struct imx_mx1_camera_data {
        resource_size_t iobase;
        resource_size_t iosize;
@@ -209,7 +217,7 @@ struct platform_device *__init imx_add_mx1_camera(
                const struct imx_mx1_camera_data *data,
                const struct mx1_camera_pdata *pdata);
-#include <mach/mx2_cam.h>
+#include <linux/platform_data/camera-mx2.h>
 struct imx_mx2_camera_data {
        resource_size_t iobasecsi;
        resource_size_t iosizecsi;
@@ -224,7 +232,7 @@ struct platform_device *__init imx_add_mx2_camera(
 struct platform_device *__init imx_add_mx2_emmaprp(
                const struct imx_mx2_camera_data *data);
-#include <mach/mxc_ehci.h>
+#include <linux/platform_data/usb-ehci-mxc.h>
 struct imx_mxc_ehci_data {
        int id;
        resource_size_t iobase;
@@ -234,7 +242,7 @@ struct platform_device *__init imx_add_mxc_ehci(
                const struct imx_mxc_ehci_data *data,
                const struct mxc_usbh_platform_data *pdata);
-#include <mach/mmc.h>
+#include <linux/platform_data/mmc-mxcmmc.h>
 struct imx_mxc_mmc_data {
        int id;
        resource_size_t iobase;
@@ -246,7 +254,7 @@ struct platform_device *__init imx_add_mxc_mmc(
                const struct imx_mxc_mmc_data *data,
                const struct imxmmc_platform_data *pdata);
-#include <mach/mxc_nand.h>
+#include <linux/platform_data/mtd-mxc_nand.h>
 struct imx_mxc_nand_data {
        /*
         * id is traditionally 0, but -1 is more appropriate.  We use -1 for new
@@ -295,7 +303,7 @@ struct imx_mxc_w1_data {
 struct platform_device *__init imx_add_mxc_w1(
                const struct imx_mxc_w1_data *data);
-#include <mach/esdhc.h>
+#include <linux/platform_data/mmc-esdhc-imx.h>
 struct imx_sdhci_esdhc_imx_data {
        const char *devid;
        int id;
@@ -306,7 +314,7 @@ struct platform_device *__init imx_add_sdhci_esdhc_imx(
                const struct imx_sdhci_esdhc_imx_data *data,
                const struct esdhc_platform_data *pdata);
-#include <mach/spi.h>
+#include <linux/platform_data/spi-imx.h>
 struct imx_spi_imx_data {
        const char *devid;
        int id;
diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h
deleted file mode 100644
index 1b9080385b46..000000000000
--- a/arch/arm/plat-mxc/include/mach/dma.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_MXC_DMA_H__
-#define __ASM_ARCH_MXC_DMA_H__
-#include <linux/scatterlist.h>
-#include <linux/device.h>
-#include <linux/dmaengine.h>
-/*
- * This enumerates peripheral types. Used for SDMA.
- */
-enum sdma_peripheral_type {
-        IMX_DMATYPE_SSI,        /* MCU domain SSI */
-        IMX_DMATYPE_SSI_SP,     /* Shared SSI */
-        IMX_DMATYPE_MMC,        /* MMC */
-        IMX_DMATYPE_SDHC,       /* SDHC */
-        IMX_DMATYPE_UART,       /* MCU domain UART */
-        IMX_DMATYPE_UART_SP,    /* Shared UART */
-        IMX_DMATYPE_FIRI,       /* FIRI */
-        IMX_DMATYPE_CSPI,       /* MCU domain CSPI */
-        IMX_DMATYPE_CSPI_SP,    /* Shared CSPI */
-        IMX_DMATYPE_SIM,        /* SIM */
-        IMX_DMATYPE_ATA,        /* ATA */
-        IMX_DMATYPE_CCM,        /* CCM */
-        IMX_DMATYPE_EXT,        /* External peripheral */
-        IMX_DMATYPE_MSHC,       /* Memory Stick Host Controller */
-        IMX_DMATYPE_MSHC_SP,    /* Shared Memory Stick Host Controller */
-        IMX_DMATYPE_DSP,        /* DSP */
-        IMX_DMATYPE_MEMORY,     /* Memory */
-        IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */
-        IMX_DMATYPE_SPDIF,      /* SPDIF */
-        IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */
-        IMX_DMATYPE_ASRC,       /* ASRC */
-        IMX_DMATYPE_ESAI,       /* ESAI */
-};
-enum imx_dma_prio {
-        DMA_PRIO_HIGH = 0,
-        DMA_PRIO_MEDIUM = 1,
-        DMA_PRIO_LOW = 2
-};
-struct imx_dma_data {
-        int dma_request; /* DMA request line */
-        enum sdma_peripheral_type peripheral_type;
-        int priority;
-};
-static inline int imx_dma_is_ipu(struct dma_chan *chan)
-{
-        return !strcmp(dev_name(chan->device->dev), "ipu-core");
-}
-static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
-{
-        return strstr(dev_name(chan->device->dev), "sdma") ||
-                !strcmp(dev_name(chan->device->dev), "imx-dma");
-}
-#endif
diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/arch/arm/plat-mxc/include/mach/esdhc.h
deleted file mode 100644
index aaf97481f413..000000000000
--- a/arch/arm/plat-mxc/include/mach/esdhc.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright 2010 Wolfram Sang <w.sang@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; version 2
- * of the License.
- */
-#ifndef __ASM_ARCH_IMX_ESDHC_H
-#define __ASM_ARCH_IMX_ESDHC_H
-enum wp_types {
-        ESDHC_WP_NONE,          /* no WP, neither controller nor gpio */
-        ESDHC_WP_CONTROLLER,    /* mmc controller internal WP */
-        ESDHC_WP_GPIO,          /* external gpio pin for WP */
-};
-enum cd_types {
-        ESDHC_CD_NONE,          /* no CD, neither controller nor gpio */
-        ESDHC_CD_CONTROLLER,    /* mmc controller internal CD */
-        ESDHC_CD_GPIO,          /* external gpio pin for CD */
-        ESDHC_CD_PERMANENT,     /* no CD, card permanently wired to host */
-};
-/**
- * struct esdhc_platform_data - platform data for esdhc on i.MX
- *
- * ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35.
- *
- * @wp_gpio:    gpio for write_protect
- * @cd_gpio:    gpio for card_detect interrupt
- * @wp_type:    type of write_protect method (see wp_types enum above)
- * @cd_type:    type of card_detect method (see cd_types enum above)
- */
-struct esdhc_platform_data {
-        unsigned int wp_gpio;
-        unsigned int cd_gpio;
-        enum wp_types wp_type;
-        enum cd_types cd_type;
-};
-#endif /* __ASM_ARCH_IMX_ESDHC_H */
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/plat-mxc/include/mach/i2c.h b/arch/arm/plat-mxc/include/mach/i2c.h
deleted file mode 100644
index 8289d915e615..000000000000
--- a/arch/arm/plat-mxc/include/mach/i2c.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * i2c.h - i.MX I2C driver header file
- *
- * Copyright (c) 2008, Darius Augulis <augulis.darius@gmail.com>
- *
- * This file is released under the GPLv2
- */
-#ifndef __ASM_ARCH_I2C_H_
-#define __ASM_ARCH_I2C_H_
-/**
- * struct imxi2c_platform_data - structure of platform data for MXC I2C driver
- * @bitrate:    Bus speed measured in Hz
- *
- **/
-struct imxi2c_platform_data {
-        u32 bitrate;
-};
-#endif /* __ASM_ARCH_I2C_H_ */
diff --git a/arch/arm/plat-mxc/include/mach/imx-uart.h b/arch/arm/plat-mxc/include/mach/imx-uart.h
deleted file mode 100644
index 4adec9b154dd..000000000000
--- a/arch/arm/plat-mxc/include/mach/imx-uart.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#ifndef ASMARM_ARCH_UART_H
-#define ASMARM_ARCH_UART_H
-#define IMXUART_HAVE_RTSCTS (1<<0)
-#define IMXUART_IRDA        (1<<1)
-struct imxuart_platform_data {
-        int (*init)(struct platform_device *pdev);
-        void (*exit)(struct platform_device *pdev);
-        unsigned int flags;
-        void (*irda_enable)(int enable);
-        unsigned int irda_inv_rx:1;
-        unsigned int irda_inv_tx:1;
-        unsigned short transceiver_delay;
-};
-#endif
diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h
deleted file mode 100644
index 9de8f062ad5d..000000000000
--- a/arch/arm/plat-mxc/include/mach/imxfb.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This structure describes the machine which we are running on.
- */
-#ifndef __MACH_IMXFB_H__
-#define __MACH_IMXFB_H__
-#include <linux/fb.h>
-#define PCR_TFT         (1 << 31)
-#define PCR_COLOR       (1 << 30)
-#define PCR_PBSIZ_1     (0 << 28)
-#define PCR_PBSIZ_2     (1 << 28)
-#define PCR_PBSIZ_4     (2 << 28)
-#define PCR_PBSIZ_8     (3 << 28)
-#define PCR_BPIX_1      (0 << 25)
-#define PCR_BPIX_2      (1 << 25)
-#define PCR_BPIX_4      (2 << 25)
-#define PCR_BPIX_8      (3 << 25)
-#define PCR_BPIX_12     (4 << 25)
-#define PCR_BPIX_16     (5 << 25)
-#define PCR_BPIX_18     (6 << 25)
-#define PCR_PIXPOL      (1 << 24)
-#define PCR_FLMPOL      (1 << 23)
-#define PCR_LPPOL       (1 << 22)
-#define PCR_CLKPOL      (1 << 21)
-#define PCR_OEPOL       (1 << 20)
-#define PCR_SCLKIDLE    (1 << 19)
-#define PCR_END_SEL     (1 << 18)
-#define PCR_END_BYTE_SWAP (1 << 17)
-#define PCR_REV_VS      (1 << 16)
-#define PCR_ACD_SEL     (1 << 15)
-#define PCR_ACD(x)      (((x) & 0x7f) << 8)
-#define PCR_SCLK_SEL    (1 << 7)
-#define PCR_SHARP       (1 << 6)
-#define PCR_PCD(x)      ((x) & 0x3f)
-#define PWMR_CLS(x)     (((x) & 0x1ff) << 16)
-#define PWMR_LDMSK      (1 << 15)
-#define PWMR_SCR1       (1 << 10)
-#define PWMR_SCR0       (1 << 9)
-#define PWMR_CC_EN      (1 << 8)
-#define PWMR_PW(x)      ((x) & 0xff)
-#define LSCR1_PS_RISE_DELAY(x)    (((x) & 0x7f) << 26)
-#define LSCR1_CLS_RISE_DELAY(x)   (((x) & 0x3f) << 16)
-#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
-#define LSCR1_GRAY2(x)            (((x) & 0xf) << 4)
-#define LSCR1_GRAY1(x)            (((x) & 0xf))
-#define DMACR_BURST     (1 << 31)
-#define DMACR_HM(x)     (((x) & 0xf) << 16)
-#define DMACR_TM(x)     ((x) & 0xf)
-struct imx_fb_videomode {
-        struct fb_videomode mode;
-        u32 pcr;
-        unsigned char   bpp;
-};
-struct imx_fb_platform_data {
-        struct imx_fb_videomode *mode;
-        int             num_modes;
-        u_int           cmap_greyscale:1,
-                        cmap_inverse:1,
-                        cmap_static:1,
-                        unused:29;
-        u_int           pwmr;
-        u_int           lscr1;
-        u_int           dmacr;
-        u_char * fixed_screen_cpu;
-        dma_addr_t fixed_screen_dma;
-        int (*init)(struct platform_device *);
-        void (*exit)(struct platform_device *);
-        void (*lcd_power)(int);
-        void (*backlight_power)(int);
-};
-void set_imx_fb_info(struct imx_fb_platform_data *);
-#endif /* ifndef __MACH_IMXFB_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index d8b65b51f2a9..f79f78a1c0ed 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -512,12 +512,16 @@ enum iomux_pins {
 #define MX31_PIN_CSPI3_SPI_RDY__CTS3    IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1)
 #define MX31_PIN_CTS1__CTS1             IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_RTS1__RTS1             IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RTS1__SFS              IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_TXD1__TXD1             IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_TXD1__SCK              IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_RXD1__RXD1             IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RXD1__STXDA            IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_DCD_DCE1__DCD_DCE1     IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_RI_DCE1__RI_DCE1       IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_DSR_DCE1__DSR_DCE1     IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_DTR_DCE1__DTR_DCE1     IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DTR_DCE1__SRXDA        IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_CTS2__CTS2             IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_RTS2__RTS2             IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_TXD2__TXD2             IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
@@ -721,6 +725,7 @@ enum iomux_pins {
 #define MX31_PIN_KEY_ROW2_KEY_ROW2      IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_ROW3_KEY_ROW3      IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_ROW4_KEY_ROW4      IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW4_GPIO          IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_KEY_ROW5_KEY_ROW5      IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_ROW6_KEY_ROW6      IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_ROW7_KEY_ROW7      IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
deleted file mode 100644
index 9761e003bde2..000000000000
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ /dev/null
@@ -1,1219 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc..
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#ifndef __MACH_IOMUX_MX53_H__
-#define __MACH_IOMUX_MX53_H__
-#include <mach/iomux-v3.h>
-/* These 2 defines are for pins that may not have a mux register, but could
- * have a pad setting register, and vice-versa. */
-#define __NA_   0x00
-#define MX53_UART_PAD_CTRL              (PAD_CTL_PKE | PAD_CTL_PUE |    \
-                PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define MX53_SDHC_PAD_CTRL      (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-                                PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
-                                PAD_CTL_SRE_FAST)
-#define MX53_PAD_GPIO_19__KPP_COL_5                     IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__GPIO4_5                       IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__CCM_CLKO                      IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__SPDIF_OUT1                    IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2          IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__ECSPI1_RDY                    IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__FEC_TDATA_3                   IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__SRC_INT_BOOT                  IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__KPP_COL_0                    IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__GPIO4_6                      IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC              IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__UART4_TXD_MUX                IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__ECSPI1_SCLK                  IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__FEC_RDATA_3                  IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST               IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__KPP_ROW_0                    IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__GPIO4_7                      IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD              IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX                IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI                  IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__FEC_TX_ER                    IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__KPP_COL_1                    IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__GPIO4_8                      IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS             IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__UART5_TXD_MUX                IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__ECSPI1_MISO                  IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__FEC_RX_CLK                   IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY              IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__KPP_ROW_1                    IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__GPIO4_9                      IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD              IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX                IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__ECSPI1_SS0                   IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__FEC_COL                      IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID              IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__KPP_COL_2                    IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__GPIO4_10                     IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__CAN1_TXCAN                   IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__FEC_MDIO                     IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__ECSPI1_SS1                   IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__FEC_RDATA_2                  IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE             IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__KPP_ROW_2                    IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__GPIO4_11                     IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__CAN1_RXCAN                   IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__FEC_MDC                      IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__ECSPI1_SS2                   IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__FEC_TDATA_2                  IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR              IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__KPP_COL_3                    IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__GPIO4_12                     IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__USBOH3_H2_DP                 IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__SPDIF_IN1                    IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__I2C2_SCL                     IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__ECSPI1_SS3                   IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__FEC_CRS                      IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK             IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__KPP_ROW_3                    IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__GPIO4_13                     IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM                 IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK             IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__I2C2_SDA                     IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT               IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP                 IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0          IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__KPP_COL_4                    IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__GPIO4_14                     IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__CAN2_TXCAN                   IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__IPU_SISG_4                   IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__UART5_RTS                    IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC             IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1          IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__KPP_ROW_4                    IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__GPIO4_15                     IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__CAN2_RXCAN                   IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__IPU_SISG_5                   IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__UART5_CTS                    IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR            IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID            IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK         IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__GPIO4_16                 IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR         IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0  IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0          IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID           IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__GPIO4_17                    IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC             IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1     IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1             IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID              IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2                 IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__GPIO4_18                     IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD              IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2      IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2              IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION           IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                 IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__GPIO4_19                     IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS             IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3      IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3              IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG                IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4                 IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__GPIO4_20                     IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD              IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__ESDHC1_WP                    IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD             IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4              IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT       IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__GPIO4_21                   IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__CSPI_SCLK                  IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0        IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN        IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5            IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY            IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__GPIO4_22                   IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__CSPI_MOSI                  IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1        IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL       \
-                                                        IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6            IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID            IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__GPIO4_23                   IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__CSPI_MISO                  IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2        IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE            IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7            IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE           IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__GPIO4_24                   IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__CSPI_SS0                   IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3        IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR       IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8            IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR            IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__GPIO4_25                   IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__CSPI_SS1                   IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4        IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB         IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9            IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK           IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__GPIO4_26                   IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__CSPI_SS2                   IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5        IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS   IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10           IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0        IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__GPIO4_27                   IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__CSPI_SS3                   IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6        IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE  IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11           IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1        IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__GPIO4_28                   IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__CSPI_RDY                   IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7        IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12           IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID          IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__GPIO4_29                   IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__PWM1_PWMO                  IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B               IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13           IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID             IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__GPIO4_30                   IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__PWM2_PWMO                  IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B               IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14           IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0          IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__GPIO4_31                  IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP          IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3        \
-                                                        IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15          IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1         IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__GPIO5_5                   IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT          IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4        \
-                                                        IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16          IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2         IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__GPIO5_6                   IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK          IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5        \
-                                                        IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17          IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3         IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__GPIO5_7                   IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS          IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0        \
-                                                        IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18          IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4         IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__GPIO5_8                   IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC           IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1        \
-                                                        IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19          IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5         IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__GPIO5_9                   IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1                IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1                IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2        \
-                                                        IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20          IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6         IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__GPIO5_10                  IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI               IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC           IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0          IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3        \
-                                                        IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21          IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7         IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__GPIO5_11                  IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO               IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD           IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1          IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4        \
-                                                        IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22          IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__GPIO5_12                  IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0                IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS          IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS          IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5        \
-                                                        IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23          IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2             IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__GPIO5_13                  IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK               IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD           IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC           IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6        \
-                                                        IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24          IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3             IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__GPIO5_14                  IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK               IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC           IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7        \
-                                                        IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25          IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI              IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__GPIO5_15                  IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI               IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD           IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0   IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26          IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO              IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__GPIO5_16                  IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO               IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS          IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1   IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27          IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK              IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__GPIO5_17                  IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0                IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD           IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2   IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28          IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS              IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK           IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__GPIO5_18                  IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0           IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29          IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC              IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__GPIO5_19                    IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK               IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1             IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30            IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL                  IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN         IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__GPIO5_20                 IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2          IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31         IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK               IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC             IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__GPIO5_21                   IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3            IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32           IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0               IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4                IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__GPIO5_22                    IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__KPP_COL_5                   IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK                 IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP            IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC             IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33            IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1                IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5                IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__GPIO5_23                    IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__KPP_ROW_5                   IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI                 IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT            IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD             IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34            IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2                IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6                IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__GPIO5_24                    IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__KPP_COL_6                   IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO                 IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK            IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS            IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35            IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3                IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7                IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__GPIO5_25                    IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__KPP_ROW_6                   IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0                  IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR            IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD             IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36            IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4                IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8                IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__GPIO5_26                    IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__KPP_COL_7                   IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK                 IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC             IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__I2C1_SDA                    IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37            IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5                IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9                IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__GPIO5_27                    IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__KPP_ROW_7                   IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI                 IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR            IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__I2C1_SCL                    IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38            IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6                IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10              IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__GPIO5_28                   IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX              IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO                IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC            IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4            IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39           IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7               IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11              IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__GPIO5_29                   IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX              IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0                 IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS           IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5            IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40           IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8               IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12              IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__GPIO5_30                   IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX              IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0        IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6            IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41           IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9               IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13              IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__GPIO5_31                   IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX              IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1        IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7            IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42           IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10              IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14              IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__GPIO6_0                    IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX              IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2        IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8            IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43           IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11              IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15              IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__GPIO6_1                    IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX              IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3        IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9            IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44           IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12              IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16              IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__GPIO6_2                    IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__UART4_RTS                  IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4        IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10           IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45           IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13              IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17              IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__GPIO6_3                    IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__UART4_CTS                  IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5        IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11           IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46           IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14              IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18              IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__GPIO6_4                    IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__UART5_RTS                  IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6        IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12           IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47           IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15              IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19              IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__GPIO6_5                    IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__UART5_CTS                  IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7        IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13           IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48           IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK             IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__EMI_WEIM_A_25                 IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__GPIO5_2                       IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__ECSPI2_RDY                    IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__IPU_DI1_PIN12                 IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__CSPI_SS1                      IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS                 IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__USBPHY1_BISTOK                IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2                 IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__GPIO2_30                      IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK               IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS              IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__ECSPI1_SS0                    IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__I2C2_SCL                      IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__EMI_WEIM_D_16                 IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__GPIO3_16                      IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__IPU_DI0_PIN5                  IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK            IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__ECSPI1_SCLK                   IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__I2C2_SDA                      IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__EMI_WEIM_D_17                 IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__GPIO3_17                      IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__IPU_DI0_PIN6                  IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN            IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__ECSPI1_MISO                   IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__I2C3_SCL                      IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__EMI_WEIM_D_18                 IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__GPIO3_18                      IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DI0_PIN7                  IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO            IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__ECSPI1_MOSI                   IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__I2C3_SDA                      IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS                 IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__EMI_WEIM_D_19                 IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__GPIO3_19                      IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__IPU_DI0_PIN8                  IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS             IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__ECSPI1_SS1                    IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__EPIT1_EPITO                   IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__UART1_CTS                     IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC               IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__EMI_WEIM_D_20                 IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__GPIO3_20                      IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__IPU_DI0_PIN16                 IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS              IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__CSPI_SS0                      IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__EPIT2_EPITO                   IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__UART1_RTS                     IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR              IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__EMI_WEIM_D_21                 IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__GPIO3_21                      IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__IPU_DI0_PIN17                 IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK            IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__CSPI_SCLK                     IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__I2C1_SCL                      IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC              IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__EMI_WEIM_D_22                 IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__GPIO3_22                      IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__IPU_DI0_PIN1                  IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN            IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__CSPI_MISO                     IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR             IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__EMI_WEIM_D_23                 IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__GPIO3_23                      IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__UART3_CTS                     IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D23__UART1_DCD                     IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS                 IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI1_PIN2                  IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN              IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI1_PIN14                 IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3                 IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__GPIO2_31                      IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__UART3_RTS                     IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__UART1_RI                      IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3                  IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC                IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16                 IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__EMI_WEIM_D_24                 IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__GPIO3_24                      IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__UART3_TXD_MUX                 IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D24__ECSPI1_SS2                    IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__CSPI_SS2                      IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS              IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__ECSPI2_SS2                    IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__UART1_DTR                     IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__EMI_WEIM_D_25                 IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__GPIO3_25                      IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__UART3_RXD_MUX                 IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D25__ECSPI1_SS3                    IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__CSPI_SS3                      IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC               IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__ECSPI2_SS3                    IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__UART1_DSR                     IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__EMI_WEIM_D_26                 IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__GPIO3_26                      IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__UART2_TXD_MUX                 IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D26__FIRI_RXD                      IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_CSI0_D_1                  IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_DI1_PIN11                 IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_SISG_2                    IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22              IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__EMI_WEIM_D_27                 IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__GPIO3_27                      IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__UART2_RXD_MUX                 IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D27__FIRI_TXD                      IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_CSI0_D_0                  IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_DI1_PIN13                 IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_SISG_3                    IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23              IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__EMI_WEIM_D_28                 IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__GPIO3_28                      IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__UART2_CTS                     IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO            IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__CSPI_MOSI                     IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__I2C1_SDA                      IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_EXT_TRIG                  IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_DI0_PIN13                 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__EMI_WEIM_D_29                 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__GPIO3_29                      IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__UART2_RTS                     IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS             IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__CSPI_SS0                      IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DI1_PIN15                 IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC                IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DI0_PIN14                 IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__EMI_WEIM_D_30                 IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__GPIO3_30                      IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__UART3_CTS                     IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_CSI0_D_3                  IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_DI0_PIN11                 IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21              IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC               IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC               IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__EMI_WEIM_D_31                 IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__GPIO3_31                      IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__UART3_RTS                     IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_CSI0_D_2                  IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_DI0_PIN12                 IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20              IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR              IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR              IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__EMI_WEIM_A_24                 IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__GPIO5_4                       IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19              IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_CSI1_D_19                 IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_SISG_2                    IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__USBPHY2_BVALID                IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__EMI_WEIM_A_23                 IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__GPIO6_6                       IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18              IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_CSI1_D_18                 IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_SISG_3                    IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION            IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__EMI_WEIM_A_22                 IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__GPIO2_16                      IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17              IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__IPU_CSI1_D_17                 IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7                 IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__EMI_WEIM_A_21                 IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__GPIO2_17                      IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16              IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__IPU_CSI1_D_16                 IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6                 IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__EMI_WEIM_A_20                 IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__GPIO2_18                      IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15              IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__IPU_CSI1_D_15                 IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5                 IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__EMI_WEIM_A_19                 IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__GPIO2_19                      IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14              IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__IPU_CSI1_D_14                 IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4                 IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__EMI_WEIM_A_18                 IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__GPIO2_20                      IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13              IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__IPU_CSI1_D_13                 IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3                 IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__EMI_WEIM_A_17                 IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__GPIO2_21                      IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12              IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__IPU_CSI1_D_12                 IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2                 IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__EMI_WEIM_A_16                 IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__GPIO2_22                      IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK              IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK               IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1                 IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0                 IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__GPIO2_23                      IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__ECSPI2_SCLK                   IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5                  IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1                 IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__GPIO2_24                      IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__ECSPI2_MOSI                   IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6                  IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__EMI_WEIM_OE                    IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__GPIO2_25                       IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__ECSPI2_MISO                    IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__IPU_DI1_PIN7                   IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__USBPHY2_IDDIG                  IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__EMI_WEIM_RW                    IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__GPIO2_26                       IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__ECSPI2_SS0                     IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__IPU_DI1_PIN8                   IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT         IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA                  IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__GPIO2_27                      IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__ECSPI2_SS1                    IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17                 IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0                 IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0                 IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__GPIO2_28                      IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11              IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11                 IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY                  IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7                 IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1                 IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__GPIO2_29                      IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10              IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10                 IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6                 IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0            IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__GPIO3_0                       IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9               IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9                  IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5                 IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1            IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__GPIO3_1                       IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8               IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8                  IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4                 IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2            IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__GPIO3_2                       IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7               IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7                  IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3                 IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3            IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__GPIO3_3                       IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6               IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6                  IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2                 IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4            IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__GPIO3_4                       IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5               IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5                  IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7                 IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5            IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__GPIO3_5                       IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4               IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4                  IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6                 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6            IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__GPIO3_6                       IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3               IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3                  IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5                 IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7            IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__GPIO3_7                       IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2               IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2                  IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4                 IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8            IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__GPIO3_8                       IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1               IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1                  IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3                 IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9            IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__GPIO3_9                       IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0               IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0                  IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2                 IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10          IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__GPIO3_10                     IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15                IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN             IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1                IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11          IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__GPIO3_11                     IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2                 IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC               IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12          IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__GPIO3_12                     IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3                 IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC               IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13          IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__GPIO3_13                     IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS                IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK              IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14          IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__GPIO3_14                     IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS                IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK              IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15          IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__GPIO3_15                     IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1                 IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4                 IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B             IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WE_B__GPIO6_12                   IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B             IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RE_B__GPIO6_13                   IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT                IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__GPIO5_0                      IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B             IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX3_P__GPIO6_22                  IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3             IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX2_P__GPIO6_24                  IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2             IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_CLK_P__GPIO6_26                  IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK             IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX1_P__GPIO6_28                  IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1             IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX0_P__GPIO6_30                  IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0             IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX3_P__GPIO7_22                  IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3             IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_CLK_P__GPIO7_24                  IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK             IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX2_P__GPIO7_26                  IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2             IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX1_P__GPIO7_28                  IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1             IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX0_P__GPIO7_30                  IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0             IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_10__GPIO4_0                       IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_10__OSC32k_32K_OUT                IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_11__GPIO4_1                       IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_12__GPIO4_2                       IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_13__GPIO4_3                       IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_14__GPIO4_4                       IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE               IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__GPIO6_7                     IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0           IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE               IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__GPIO6_8                     IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1           IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B             IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__GPIO6_9                    IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2          IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0              IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__GPIO6_10                    IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3           IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0              IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__GPIO6_11                    IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4           IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1              IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__GPIO6_14                    IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__MLB_MLBCLK                  IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5           IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2              IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__GPIO6_15                    IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__IPU_SISG_0                  IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__ESAI1_TX0                   IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE                IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK               IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__MLB_MLBSIG                  IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6           IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3              IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__GPIO6_16                    IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__IPU_SISG_1                  IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__ESAI1_TX1                   IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26               IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__MLB_MLBDAT                  IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7           IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__FEC_MDIO                     IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__GPIO1_22                     IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__ESAI1_SCKR                   IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__FEC_COL                      IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2               IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3      IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49             IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK                IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__GPIO1_23                  IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR                 IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4   IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50          IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__FEC_RX_ER                   IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__GPIO1_24                    IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR                  IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK                  IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3              IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV                  IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__GPIO1_25                   IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT                 IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__FEC_RDATA_1                  IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__GPIO1_26                     IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__ESAI1_FST                    IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__MLB_MLBSIG                   IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1               IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__FEC_RDATA_0                  IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__GPIO1_27                     IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__ESAI1_HCKT                   IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT               IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__FEC_TX_EN                   IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__GPIO1_28                    IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2               IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__FEC_TDATA_1                  IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__GPIO1_29                     IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3                IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__MLB_MLBCLK                   IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK          IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__FEC_TDATA_0                  IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__GPIO1_30                     IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1                IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0            IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__FEC_MDC                       IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__GPIO1_31                      IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0                 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__MLB_MLBDAT                    IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG        IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1             IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__PATA_DIOW                   IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__GPIO6_17                    IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX               IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2           IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__PATA_DMACK                 IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__GPIO6_18                   IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX              IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3          IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__PATA_DMARQ                 IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__GPIO7_0                    IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX              IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0              IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4          IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN         IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1                IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX          IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1          IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5      IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__PATA_INTRQ                 IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__GPIO7_2                    IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__UART2_CTS                  IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN                 IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2              IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6          IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__PATA_DIOR                   IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__GPIO7_3                     IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__UART2_RTS                   IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__CAN1_RXCAN                  IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7           IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B        IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__GPIO7_4                  IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD               IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__UART1_CTS                IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN               IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0        IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__PATA_IORDY                 IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__GPIO7_5                    IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__ESDHC3_CLK                 IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__UART1_RTS                  IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__CAN2_RXCAN                 IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1          IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__PATA_DA_0                   IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__GPIO7_6                     IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__ESDHC3_RST                  IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__OWIRE_LINE                  IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2           IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__PATA_DA_1                   IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__GPIO7_7                     IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__ESDHC4_CMD                  IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__UART3_CTS                   IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3           IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__PATA_DA_2                   IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__GPIO7_8                     IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__ESDHC4_CLK                  IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__UART3_RTS                   IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4           IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__PATA_CS_0                   IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__GPIO7_9                     IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX               IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5           IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__PATA_CS_1                   IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__GPIO7_10                    IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX               IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6           IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__PATA_DATA_0                IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__GPIO2_0                    IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0              IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4                IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0      IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0             IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7          IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__PATA_DATA_1                IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__GPIO2_1                    IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1              IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5                IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1      IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1             IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__PATA_DATA_2                IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__GPIO2_2                    IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2              IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6                IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2      IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2             IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__PATA_DATA_3                IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__GPIO2_3                    IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3              IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7                IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3      IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3             IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__PATA_DATA_4                IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__GPIO2_4                    IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4              IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4                IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4      IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4             IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__PATA_DATA_5                IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__GPIO2_5                    IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5              IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5                IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5      IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5             IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__PATA_DATA_6                IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__GPIO2_6                    IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6              IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6                IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6      IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6             IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__PATA_DATA_7                IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__GPIO2_7                    IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7              IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7                IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7      IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7             IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__PATA_DATA_8                IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__GPIO2_8                    IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4                IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8              IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0                IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8      IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8             IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__PATA_DATA_9                IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__GPIO2_9                    IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5                IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9              IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1                IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9      IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9             IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__PATA_DATA_10              IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__GPIO2_10                  IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6               IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10            IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2               IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10    IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10           IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__PATA_DATA_11              IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__GPIO2_11                  IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7               IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11            IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3               IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11    IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11           IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__PATA_DATA_12              IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__GPIO2_12                  IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4               IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12            IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0               IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12    IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12           IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__PATA_DATA_13              IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__GPIO2_13                  IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5               IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13            IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1               IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13    IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13           IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__PATA_DATA_14              IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__GPIO2_14                  IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6               IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14            IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2               IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14    IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14           IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__PATA_DATA_15              IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__GPIO2_15                  IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7               IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15            IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3               IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15    IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15           IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0                 IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__GPIO1_16                    IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__GPT_CAPIN1                  IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__CSPI_MISO                   IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP                IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1                 IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__GPIO1_17                    IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__GPT_CAPIN2                  IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__CSPI_SS0                    IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP                IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__ESDHC1_CMD                    IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__GPIO1_18                      IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__GPT_CMPOUT1                   IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__CSPI_MOSI                     IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP                  IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2                 IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__GPIO1_19                    IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2                 IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__PWM2_PWMO                   IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B                IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__CSPI_SS1                    IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB        IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP                IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__ESDHC1_CLK                    IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__GPIO1_20                      IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT                IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__GPT_CLKIN                     IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__CSPI_SCLK                     IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0                IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3                 IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__GPIO1_21                    IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3                 IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__PWM1_PWMO                   IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B                IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__CSPI_SS2                    IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB        IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1              IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__ESDHC2_CLK                    IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__GPIO1_10                      IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__KPP_COL_5                     IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS              IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__CSPI_SCLK                     IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__SCC_RANDOM_V                  IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__ESDHC2_CMD                    IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__GPIO1_11                      IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__KPP_ROW_5                     IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC               IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__CSPI_MOSI                     IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__SCC_RANDOM                    IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3                 IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__GPIO1_12                    IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__KPP_COL_6                   IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC             IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__CSPI_SS2                    IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__SJC_DONE                    IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2                 IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__GPIO1_13                    IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__KPP_ROW_6                   IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD             IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__CSPI_SS1                    IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__SJC_FAIL                    IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1                 IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__GPIO1_14                    IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__KPP_COL_7                   IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS            IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__CSPI_SS0                    IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO                IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0                 IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__GPIO1_15                    IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__KPP_ROW_7                   IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD             IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__CSPI_MISO                   IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT               IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CCM_CLKO                       IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__GPIO1_0                        IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__KPP_COL_5                      IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK               IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__EPIT1_EPITO                    IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB                 IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR               IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CSU_TD                         IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__ESAI1_SCKR                     IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__GPIO1_1                        IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__KPP_ROW_5                      IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK               IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__PWM2_PWMO                      IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__WDOG2_WDOG_B                   IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__ESDHC1_CD                      IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__SRC_TESTER_ACK                 IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__ESAI1_FSR                      IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__GPIO1_9                        IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__KPP_COL_6                      IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__CCM_REF_EN_B                   IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__PWM1_PWMO                      IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__WDOG1_WDOG_B                   IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__ESDHC1_WP                      IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__SCC_FAIL_STATE                 IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__ESAI1_HCKR                     IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__GPIO1_3                        IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__I2C3_SCL                       IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN                 IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__CCM_CLKO2                      IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0     IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC                IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__MLB_MLBCLK                     IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__ESAI1_SCKT                     IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__GPIO1_6                        IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__I2C3_SDA                       IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0                  IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB                IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1     IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__ESDHC2_LCTL                    IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__MLB_MLBSIG                     IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__ESAI1_FST                      IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__GPIO1_2                        IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__KPP_ROW_6                      IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1                  IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0            IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2     IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__ESDHC2_WP                      IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__MLB_MLBDAT                     IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__ESAI1_HCKT                     IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__GPIO1_4                        IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__KPP_COL_7                      IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2                  IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1            IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3     IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__ESDHC2_CD                      IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__SCC_SEC_STATE                  IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3                  IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__GPIO1_5                        IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__KPP_ROW_7                      IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CCM_CLKO                       IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2            IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4     IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__I2C3_SCL                       IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CCM_PLL1_BYP                   IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1                  IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__GPIO1_7                        IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__EPIT1_EPITO                    IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__CAN1_TXCAN                     IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__UART2_TXD_MUX                  IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_GPIO_7__FIRI_RXD                       IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__SPDIF_PLOCK                    IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__CCM_PLL2_BYP                   IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0                  IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__GPIO1_8                        IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__EPIT2_EPITO                    IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__CAN1_RXCAN                     IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__UART2_RXD_MUX                  IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL)
-#define MX53_PAD_GPIO_8__FIRI_TXD                       IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__SPDIF_SRCLK                    IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__CCM_PLL3_BYP                   IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2                 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__GPIO7_11                      IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT              IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1          IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__SPDIF_IN1                     IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__I2C3_SDA                      IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__SJC_DE_B                      IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__ESAI1_TX0                     IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__GPIO7_12                      IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0              IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__GPC_PMIC_RDY                  IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG           IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SPDIF_OUT1                    IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__IPU_SNOOP2                    IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SJC_JTAG_ACT                  IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__ESAI1_TX1                     IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__GPIO7_13                      IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1              IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__OWIRE_LINE                    IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG        IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK              IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__ESDHC1_LCTL                   IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST                IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL)
-#endif  /* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h
deleted file mode 100644
index 29115f405af9..000000000000
--- a/arch/arm/plat-mxc/include/mach/mmc.h
+++ /dev/null
@@ -1,39 +0,0 @@
-#ifndef ASMARM_ARCH_MMC_H
-#define ASMARM_ARCH_MMC_H
-#include <linux/mmc/host.h>
-struct device;
-/* board specific SDHC data, optional.
- * If not present, a writable card with 3,3V is assumed.
- */
-struct imxmmc_platform_data {
-        /* Return values for the get_ro callback should be:
-         *   0 for a read/write card
-         *   1 for a read-only card
-         *   -ENOSYS when not supported (equal to NULL callback)
-         *   or a negative errno value when something bad happened
-         */
-        int (*get_ro)(struct device *);
-        /* board specific hook to (de)initialize the SD slot.
-         * The board code can call 'handler' on a card detection
-         * change giving data as argument.
-         */
-        int (*init)(struct device *dev, irq_handler_t handler, void *data);
-        void (*exit)(struct device *dev, void *data);
-        /* available voltages. If not given, assume
-         * MMC_VDD_32_33 | MMC_VDD_33_34
-         */
-        unsigned int ocr_avail;
-        /* adjust slot voltage */
-        void (*setpower)(struct device *, unsigned int vdd);
-        /* enable card detect using DAT3 */
-        int dat3_card_detect;
-};
-#endif
diff --git a/arch/arm/plat-mxc/include/mach/mx1_camera.h b/arch/arm/plat-mxc/include/mach/mx1_camera.h
deleted file mode 100644
index 4fd6c70314b4..000000000000
--- a/arch/arm/plat-mxc/include/mach/mx1_camera.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * mx1_camera.h - i.MX1/i.MXL camera driver header file
- *
- * Copyright (c) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- * Copyright (C) 2009, Darius Augulis <augulis.darius@gmail.com>
- *
- * Based on PXA camera.h file:
- * Copyright (C) 2003, Intel Corporation
- * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_CAMERA_H_
-#define __ASM_ARCH_CAMERA_H_
-#define MX1_CAMERA_DATA_HIGH    1
-#define MX1_CAMERA_PCLK_RISING  2
-#define MX1_CAMERA_VSYNC_HIGH   4
-extern unsigned char mx1_camera_sof_fiq_start, mx1_camera_sof_fiq_end;
-/**
- * struct mx1_camera_pdata - i.MX1/i.MXL camera platform data
- * @mclk_10khz: master clock frequency in 10kHz units
- * @flags:      MX1 camera platform flags
- */
-struct mx1_camera_pdata {
-        unsigned long mclk_10khz;
-        unsigned long flags;
-};
-#endif /* __ASM_ARCH_CAMERA_H_ */
diff --git a/arch/arm/plat-mxc/include/mach/mx21-usbhost.h b/arch/arm/plat-mxc/include/mach/mx21-usbhost.h
deleted file mode 100644
index 22d0b596262c..000000000000
--- a/arch/arm/plat-mxc/include/mach/mx21-usbhost.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- *      Copyright (C) 2009 Martin Fuzzey <mfuzzey@gmail.com>
- *
- *      This program is free software; you can redistribute it and/or modify
- *      it under the terms of the GNU General Public License as published by
- *      the Free Software Foundation; either version 2 of the License, or
- *      (at your option) any later version.
- *
- *      This program is distributed in the hope that it will be useful,
- *      but WITHOUT ANY WARRANTY; without even the implied warranty of
- *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *      GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_MX21_USBH
-#define __ASM_ARCH_MX21_USBH
-enum mx21_usbh_xcvr {
-        /* Values below as used by hardware (HWMODE register) */
-        MX21_USBXCVR_TXDIF_RXDIF = 0,
-        MX21_USBXCVR_TXDIF_RXSE = 1,
-        MX21_USBXCVR_TXSE_RXDIF = 2,
-        MX21_USBXCVR_TXSE_RXSE = 3,
-};
-struct mx21_usbh_platform_data {
-        enum mx21_usbh_xcvr host_xcvr; /* tranceiver mode host 1,2 ports */
-        enum mx21_usbh_xcvr otg_xcvr; /* tranceiver mode otg (as host) port */
-        u16     enable_host1:1,
-                enable_host2:1,
-                enable_otg_host:1, /* enable "OTG" port (as host) */
-                host1_xcverless:1, /* traceiverless host1 port */
-                host1_txenoe:1, /* output enable host1 transmit enable */
-                otg_ext_xcvr:1, /* external tranceiver for OTG port */
-                unused:10;
-};
-#endif /* __ASM_ARCH_MX21_USBH */
diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h
deleted file mode 100644
index 3c080a32dbf5..000000000000
--- a/arch/arm/plat-mxc/include/mach/mx2_cam.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * mx2-cam.h - i.MX27/i.MX25 camera driver header file
- *
- * Copyright (C) 2003, Intel Corporation
- * Copyright (C) 2008, Sascha Hauer <s.hauer@pengutronix.de>
- * Copyright (C) 2010, Baruch Siach <baruch@tkos.co.il>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#ifndef __MACH_MX2_CAM_H_
-#define __MACH_MX2_CAM_H_
-#define MX2_CAMERA_SWAP16               (1 << 0)
-#define MX2_CAMERA_EXT_VSYNC            (1 << 1)
-#define MX2_CAMERA_CCIR                 (1 << 2)
-#define MX2_CAMERA_CCIR_INTERLACE       (1 << 3)
-#define MX2_CAMERA_HSYNC_HIGH           (1 << 4)
-#define MX2_CAMERA_GATED_CLOCK          (1 << 5)
-#define MX2_CAMERA_INV_DATA             (1 << 6)
-#define MX2_CAMERA_PCLK_SAMPLE_RISING   (1 << 7)
-#define MX2_CAMERA_PACK_DIR_MSB         (1 << 8)
-/**
- * struct mx2_camera_platform_data - optional platform data for mx2_camera
- * @flags: any combination of MX2_CAMERA_*
- * @clk: clock rate of the csi block / 2
- */
-struct mx2_camera_platform_data {
-        unsigned long flags;
-        unsigned long clk;
-};
-#endif /* __MACH_MX2_CAM_H_ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index dbced61d9fda..ee9b1f9215df 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -76,7 +76,7 @@
 #define MX31_RTIC_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xec000)
 #define MX31_ROMP_BASE_ADDR             0x60000000
-#define MX31_ROMP_BASE_ADDR_VIRT        0xfc500000
+#define MX31_ROMP_BASE_ADDR_VIRT        IOMEM(0xfc500000)
 #define MX31_ROMP_SIZE                  SZ_1M
 #define MX31_AVIC_BASE_ADDR             0x68000000
@@ -92,11 +92,11 @@
 #define MX31_CS3_BASE_ADDR              0xb2000000
 #define MX31_CS4_BASE_ADDR              0xb4000000
-#define MX31_CS4_BASE_ADDR_VIRT         0xf6000000
+#define MX31_CS4_BASE_ADDR_VIRT         IOMEM(0xf6000000)
 #define MX31_CS4_SIZE                   SZ_32M
 #define MX31_CS5_BASE_ADDR              0xb6000000
-#define MX31_CS5_BASE_ADDR_VIRT         0xf8000000
+#define MX31_CS5_BASE_ADDR_VIRT         IOMEM(0xf8000000)
 #define MX31_CS5_SIZE                   SZ_32M
 #define MX31_X_MEMC_BASE_ADDR           0xb8000000
diff --git a/arch/arm/plat-mxc/include/mach/mx3_camera.h b/arch/arm/plat-mxc/include/mach/mx3_camera.h
deleted file mode 100644
index f226ee3777e1..000000000000
--- a/arch/arm/plat-mxc/include/mach/mx3_camera.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * mx3_camera.h - i.MX3x camera driver header file
- *
- * Copyright (C) 2008, Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef _MX3_CAMERA_H_
-#define _MX3_CAMERA_H_
-#include <linux/device.h>
-#define MX3_CAMERA_CLK_SRC      1
-#define MX3_CAMERA_EXT_VSYNC    2
-#define MX3_CAMERA_DP           4
-#define MX3_CAMERA_PCP          8
-#define MX3_CAMERA_HSP          0x10
-#define MX3_CAMERA_VSP          0x20
-#define MX3_CAMERA_DATAWIDTH_4  0x40
-#define MX3_CAMERA_DATAWIDTH_8  0x80
-#define MX3_CAMERA_DATAWIDTH_10 0x100
-#define MX3_CAMERA_DATAWIDTH_15 0x200
-#define MX3_CAMERA_DATAWIDTH_MASK (MX3_CAMERA_DATAWIDTH_4 | MX3_CAMERA_DATAWIDTH_8 | \
-                                   MX3_CAMERA_DATAWIDTH_10 | MX3_CAMERA_DATAWIDTH_15)
-/**
- * struct mx3_camera_pdata - i.MX3x camera platform data
- * @flags:      MX3_CAMERA_* flags
- * @mclk_10khz: master clock frequency in 10kHz units
- * @dma_dev:    IPU DMA device to match against in channel allocation
- */
-struct mx3_camera_pdata {
-        unsigned long flags;
-        unsigned long mclk_10khz;
-        struct device *dma_dev;
-};
-#endif
diff --git a/arch/arm/plat-mxc/include/mach/mx3fb.h b/arch/arm/plat-mxc/include/mach/mx3fb.h
deleted file mode 100644
index fdbe60001542..000000000000
--- a/arch/arm/plat-mxc/include/mach/mx3fb.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (C) 2008
- * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_MX3FB_H__
-#define __ASM_ARCH_MX3FB_H__
-#include <linux/device.h>
-#include <linux/fb.h>
-/* Proprietary FB_SYNC_ flags */
-#define FB_SYNC_OE_ACT_HIGH     0x80000000
-#define FB_SYNC_CLK_INVERT      0x40000000
-#define FB_SYNC_DATA_INVERT     0x20000000
-#define FB_SYNC_CLK_IDLE_EN     0x10000000
-#define FB_SYNC_SHARP_MODE      0x08000000
-#define FB_SYNC_SWAP_RGB        0x04000000
-#define FB_SYNC_CLK_SEL_EN      0x02000000
-/*
- * Specify the way your display is connected. The IPU can arbitrarily
- * map the internal colors to the external data lines. We only support
- * the following mappings at the moment.
- */
-enum disp_data_mapping {
-        /* blue -> d[0..5], green -> d[6..11], red -> d[12..17] */
-        IPU_DISP_DATA_MAPPING_RGB666,
-        /* blue -> d[0..4], green -> d[5..10], red -> d[11..15] */
-        IPU_DISP_DATA_MAPPING_RGB565,
-        /* blue -> d[0..7], green -> d[8..15], red -> d[16..23] */
-        IPU_DISP_DATA_MAPPING_RGB888,
-};
-/**
- * struct mx3fb_platform_data - mx3fb platform data
- *
- * @dma_dev:    pointer to the dma-device, used for dma-slave connection
- * @mode:       pointer to a platform-provided per mxc_register_fb() videomode
- */
-struct mx3fb_platform_data {
-        struct device                   *dma_dev;
-        const char                      *name;
-        const struct fb_videomode       *mode;
-        int                             num_modes;
-        enum disp_data_mapping          disp_data_fmt;
-};
-#endif
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
deleted file mode 100644
index 7eb9d1329671..000000000000
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ /dev/null
@@ -1,59 +0,0 @@
-#ifndef __INCLUDE_ASM_ARCH_MXC_EHCI_H
-#define __INCLUDE_ASM_ARCH_MXC_EHCI_H
-/* values for portsc field */
-#define MXC_EHCI_PHY_LOW_POWER_SUSPEND  (1 << 23)
-#define MXC_EHCI_FORCE_FS               (1 << 24)
-#define MXC_EHCI_UTMI_8BIT              (0 << 28)
-#define MXC_EHCI_UTMI_16BIT             (1 << 28)
-#define MXC_EHCI_SERIAL                 (1 << 29)
-#define MXC_EHCI_MODE_UTMI              (0 << 30)
-#define MXC_EHCI_MODE_PHILIPS           (1 << 30)
-#define MXC_EHCI_MODE_ULPI              (2 << 30)
-#define MXC_EHCI_MODE_SERIAL            (3 << 30)
-/* values for flags field */
-#define MXC_EHCI_INTERFACE_DIFF_UNI     (0 << 0)
-#define MXC_EHCI_INTERFACE_DIFF_BI      (1 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_UNI   (2 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_BI    (3 << 0)
-#define MXC_EHCI_INTERFACE_MASK         (0xf)
-#define MXC_EHCI_POWER_PINS_ENABLED     (1 << 5)
-#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH    (1 << 6)
-#define MXC_EHCI_OC_PIN_ACTIVE_LOW      (1 << 7)
-#define MXC_EHCI_TTL_ENABLED            (1 << 8)
-#define MXC_EHCI_INTERNAL_PHY           (1 << 9)
-#define MXC_EHCI_IPPUE_DOWN             (1 << 10)
-#define MXC_EHCI_IPPUE_UP               (1 << 11)
-#define MXC_EHCI_WAKEUP_ENABLED         (1 << 12)
-#define MXC_EHCI_ITC_NO_THRESHOLD       (1 << 13)
-#define MXC_USBCTRL_OFFSET              0
-#define MXC_USB_PHY_CTR_FUNC_OFFSET     0x8
-#define MXC_USB_PHY_CTR_FUNC2_OFFSET    0xc
-#define MXC_USBH2CTRL_OFFSET            0x14
-#define MX5_USBOTHER_REGS_OFFSET        0x800
-/* USB_PHY_CTRL_FUNC2*/
-#define MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK               0x3
-#define MX5_USB_UTMI_PHYCTRL1_PLLDIV_SHIFT              0
-struct mxc_usbh_platform_data {
-        int (*init)(struct platform_device *pdev);
-        int (*exit)(struct platform_device *pdev);
-        unsigned int             portsc;
-        struct usb_phy          *otg;
-};
-int mx51_initialize_usb_hw(int port, unsigned int flags);
-int mx25_initialize_usb_hw(int port, unsigned int flags);
-int mx31_initialize_usb_hw(int port, unsigned int flags);
-int mx35_initialize_usb_hw(int port, unsigned int flags);
-int mx27_initialize_usb_hw(int port, unsigned int flags);
-#endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */
diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
deleted file mode 100644
index 6bb96ef1600b..000000000000
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#ifndef __ASM_ARCH_NAND_H
-#define __ASM_ARCH_NAND_H
-#include <linux/mtd/partitions.h>
-struct mxc_nand_platform_data {
-        unsigned int width;     /* data bus width in bytes */
-        unsigned int hw_ecc:1;  /* 0 if suppress hardware ECC */
-        unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
-        struct mtd_partition *parts;    /* partition table */
-        int nr_parts;                   /* size of parts */
-};
-#endif /* __ASM_ARCH_NAND_H */
diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h
deleted file mode 100644
index 3a3942823c20..000000000000
--- a/arch/arm/plat-mxc/include/mach/sdma.h
+++ /dev/null
@@ -1,59 +0,0 @@
-#ifndef __MACH_MXC_SDMA_H__
-#define __MACH_MXC_SDMA_H__
-/**
- * struct sdma_script_start_addrs - SDMA script start pointers
- *
- * start addresses of the different functions in the physical
- * address space of the SDMA engine.
- */
-struct sdma_script_start_addrs {
-        s32 ap_2_ap_addr;
-        s32 ap_2_bp_addr;
-        s32 ap_2_ap_fixed_addr;
-        s32 bp_2_ap_addr;
-        s32 loopback_on_dsp_side_addr;
-        s32 mcu_interrupt_only_addr;
-        s32 firi_2_per_addr;
-        s32 firi_2_mcu_addr;
-        s32 per_2_firi_addr;
-        s32 mcu_2_firi_addr;
-        s32 uart_2_per_addr;
-        s32 uart_2_mcu_addr;
-        s32 per_2_app_addr;
-        s32 mcu_2_app_addr;
-        s32 per_2_per_addr;
-        s32 uartsh_2_per_addr;
-        s32 uartsh_2_mcu_addr;
-        s32 per_2_shp_addr;
-        s32 mcu_2_shp_addr;
-        s32 ata_2_mcu_addr;
-        s32 mcu_2_ata_addr;
-        s32 app_2_per_addr;
-        s32 app_2_mcu_addr;
-        s32 shp_2_per_addr;
-        s32 shp_2_mcu_addr;
-        s32 mshc_2_mcu_addr;
-        s32 mcu_2_mshc_addr;
-        s32 spdif_2_mcu_addr;
-        s32 mcu_2_spdif_addr;
-        s32 asrc_2_mcu_addr;
-        s32 ext_mem_2_ipu_addr;
-        s32 descrambler_addr;
-        s32 dptc_dvfs_addr;
-        s32 utra_addr;
-        s32 ram_code_start_addr;
-};
-/**
- * struct sdma_platform_data - platform specific data for SDMA engine
- *
- * @fw_name             The firmware name
- * @script_addrs        SDMA scripts addresses in SDMA ROM
- */
-struct sdma_platform_data {
-        char *fw_name;
-        struct sdma_script_start_addrs *script_addrs;
-};
-#endif /* __MACH_MXC_SDMA_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/spi.h b/arch/arm/plat-mxc/include/mach/spi.h
deleted file mode 100644
index 08be445e8eb8..000000000000
--- a/arch/arm/plat-mxc/include/mach/spi.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __MACH_SPI_H_
-#define __MACH_SPI_H_
-/*
- * struct spi_imx_master - device.platform_data for SPI controller devices.
- * @chipselect: Array of chipselects for this master. Numbers >= 0 mean gpio
- *              pins, numbers < 0 mean internal CSPI chipselects according
- *              to MXC_SPI_CS(). Normally you want to use gpio based chip
- *              selects as the CSPI module tries to be intelligent about
- *              when to assert the chipselect: The CSPI module deasserts the
- *              chipselect once it runs out of input data. The other problem
- *              is that it is not possible to mix between high active and low
- *              active chipselects on one single bus using the internal
- *              chipselects. Unfortunately Freescale decided to put some
- *              chipselects on dedicated pins which are not usable as gpios,
- *              so we have to support the internal chipselects.
- * @num_chipselect: ARRAY_SIZE(chipselect)
- */
-struct spi_imx_master {
-        int     *chipselect;
-        int     num_chipselect;
-};
-#define MXC_SPI_CS(no)  ((no) - 32)
-#endif /* __MACH_SPI_H_*/
diff --git a/arch/arm/plat-mxc/include/mach/ssi.h b/arch/arm/plat-mxc/include/mach/ssi.h
deleted file mode 100644
index 63f3c2804239..000000000000
--- a/arch/arm/plat-mxc/include/mach/ssi.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef __MACH_SSI_H
-#define __MACH_SSI_H
-struct snd_ac97;
-extern unsigned char imx_ssi_fiq_start, imx_ssi_fiq_end;
-extern unsigned long imx_ssi_fiq_base, imx_ssi_fiq_tx_buffer, imx_ssi_fiq_rx_buffer;
-struct imx_ssi_platform_data {
-        unsigned int flags;
-#define IMX_SSI_DMA            (1 << 0)
-#define IMX_SSI_USE_AC97       (1 << 1)
-#define IMX_SSI_NET            (1 << 2)
-#define IMX_SSI_SYN            (1 << 3)
-#define IMX_SSI_USE_I2S_SLAVE  (1 << 4)
-        void (*ac97_reset) (struct snd_ac97 *ac97);
-        void (*ac97_warm_reset)(struct snd_ac97 *ac97);
-};
-#endif /* __MACH_SSI_H */
diff --git a/arch/arm/plat-mxc/include/mach/usb.h b/arch/arm/plat-mxc/include/mach/usb.h
deleted file mode 100644
index be273371f34a..000000000000
--- a/arch/arm/plat-mxc/include/mach/usb.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- *      Copyright (C) 2008 Darius Augulis <augulis.darius@gmail.com>
- *
- *      This program is free software; you can redistribute it and/or modify
- *      it under the terms of the GNU General Public License as published by
- *      the Free Software Foundation; either version 2 of the License, or
- *      (at your option) any later version.
- *
- *      This program is distributed in the hope that it will be useful,
- *      but WITHOUT ANY WARRANTY; without even the implied warranty of
- *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *      GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_MXC_USB
-#define __ASM_ARCH_MXC_USB
-struct imxusb_platform_data {
-        int (*init)(struct device *);
-        void (*exit)(struct device *);
-};
-#endif /* __ASM_ARCH_MXC_USB */
diff --git a/arch/arm/plat-mxc/ssi-fiq-ksym.c b/arch/arm/plat-mxc/ssi-fiq-ksym.c
index b5fad454da78..792090f9a032 100644
--- a/arch/arm/plat-mxc/ssi-fiq-ksym.c
+++ b/arch/arm/plat-mxc/ssi-fiq-ksym.c
@@ -10,7 +10,7 @@
 #include <linux/module.h>
-#include <mach/ssi.h>
+#include <linux/platform_data/asoc-imx-ssi.h>
 EXPORT_SYMBOL(imx_ssi_fiq_tx_buffer);
 EXPORT_SYMBOL(imx_ssi_fiq_rx_buffer);
diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S
index 8397a2dd19f2..a8b93c5f29b5 100644
--- a/arch/arm/plat-mxc/ssi-fiq.S
+++ b/arch/arm/plat-mxc/ssi-fiq.S
@@ -34,91 +34,98 @@
                .global imx_ssi_fiq_rx_buffer
                .global imx_ssi_fiq_tx_buffer
+/*
+ * imx_ssi_fiq_start is _intentionally_ not marked as a function symbol
+ * using ENDPROC().  imx_ssi_fiq_start and imx_ssi_fiq_end are used to
+ * mark the function body so that it can be copied to the FIQ vector in
+ * the vectors page.  imx_ssi_fiq_start should only be called as the result
+ * of an FIQ: calling it directly will not work.
+ */
 imx_ssi_fiq_start:
-                ldr r12, imx_ssi_fiq_base
+                ldr r12, .L_imx_ssi_fiq_base
                /* TX */
-                ldr r11, imx_ssi_fiq_tx_buffer
+                ldr r13, .L_imx_ssi_fiq_tx_buffer
                /* shall we send? */
-                ldr r13, [r12, #SSI_SIER]
+                ldr r11, [r12, #SSI_SIER]
-                tst r13, #SSI_SIER_TFE0_EN
+                tst r11, #SSI_SIER_TFE0_EN
                beq 1f
                /* TX FIFO empty? */
-                ldr r13, [r12, #SSI_SISR]
+                ldr r11, [r12, #SSI_SISR]
-                tst r13, #SSI_SISR_TFE0
+                tst r11, #SSI_SISR_TFE0
                beq 1f
                mov r10, #0x10000
                sub r10, #1
                and r10, r10, r8        /* r10: current buffer offset */
-                add r11, r11, r10
+                add r13, r13, r10
-                ldrh r13, [r11]
+                ldrh r11, [r13]
-                strh r13, [r12, #SSI_STX0]
+                strh r11, [r12, #SSI_STX0]
-                ldrh r13, [r11, #2]
+                ldrh r11, [r13, #2]
-                strh r13, [r12, #SSI_STX0]
+                strh r11, [r12, #SSI_STX0]
-                ldrh r13, [r11, #4]
+                ldrh r11, [r13, #4]
-                strh r13, [r12, #SSI_STX0]
+                strh r11, [r12, #SSI_STX0]
-                ldrh r13, [r11, #6]
+                ldrh r11, [r13, #6]
-                strh r13, [r12, #SSI_STX0]
+                strh r11, [r12, #SSI_STX0]
                add r10, #8
-                lsr r13, r8, #16        /* r13: buffer size */
+                lsr r11, r8, #16        /* r11: buffer size */
-                cmp r10, r13
+                cmp r10, r11
-                lslgt r8, r13, #16
+                lslgt r8, r11, #16
                addle r8, #8
 1:
                /* RX */
                /* shall we receive? */
-                ldr r13, [r12, #SSI_SIER]
+                ldr r11, [r12, #SSI_SIER]
-                tst r13, #SSI_SIER_RFF0_EN
+                tst r11, #SSI_SIER_RFF0_EN
                beq 1f
                /* RX FIFO full? */
-                ldr r13, [r12, #SSI_SISR]
+                ldr r11, [r12, #SSI_SISR]
-                tst r13, #SSI_SISR_RFF0
+                tst r11, #SSI_SISR_RFF0
                beq 1f
-                ldr r11, imx_ssi_fiq_rx_buffer
+                ldr r13, .L_imx_ssi_fiq_rx_buffer
                mov r10, #0x10000
                sub r10, #1
                and r10, r10, r9        /* r10: current buffer offset */
-                add r11, r11, r10
+                add r13, r13, r10
-                ldr r13, [r12, #SSI_SACNT]
+                ldr r11, [r12, #SSI_SACNT]
-                tst r13, #SSI_SACNT_AC97EN
+                tst r11, #SSI_SACNT_AC97EN
-                ldr r13, [r12, #SSI_SRX0]
+                ldr r11, [r12, #SSI_SRX0]
-                strh r13, [r11]
+                strh r11, [r13]
-                ldr r13, [r12, #SSI_SRX0]
+                ldr r11, [r12, #SSI_SRX0]
-                strh r13, [r11, #2]
+                strh r11, [r13, #2]
                /* dummy read to skip slot 12 */
-                ldrne r13, [r12, #SSI_SRX0]
+                ldrne r11, [r12, #SSI_SRX0]
-                ldr r13, [r12, #SSI_SRX0]
+                ldr r11, [r12, #SSI_SRX0]
-                strh r13, [r11, #4]
+                strh r11, [r13, #4]
-                ldr r13, [r12, #SSI_SRX0]
+                ldr r11, [r12, #SSI_SRX0]
-                strh r13, [r11, #6]
+                strh r11, [r13, #6]
                /* dummy read to skip slot 12 */
-                ldrne r13, [r12, #SSI_SRX0]
+                ldrne r11, [r12, #SSI_SRX0]
                add r10, #8
-                lsr r13, r9, #16        /* r13: buffer size */
+                lsr r11, r9, #16        /* r11: buffer size */
-                cmp r10, r13
+                cmp r10, r11
-                lslgt r9, r13, #16
+                lslgt r9, r11, #16
                addle r9, #8
 1:
@@ -126,11 +133,15 @@ imx_ssi_fiq_start:
                subs    pc, lr, #4
                .align
+.L_imx_ssi_fiq_base:
 imx_ssi_fiq_base:
                .word 0x0
+.L_imx_ssi_fiq_rx_buffer:
 imx_ssi_fiq_rx_buffer:
                .word 0x0
+.L_imx_ssi_fiq_tx_buffer:
 imx_ssi_fiq_tx_buffer:
                .word 0x0
+.L_imx_ssi_fiq_end:
 imx_ssi_fiq_end:
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 1996c3e3b8fe..3da78cfc5a94 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -21,7 +21,6 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/delay.h>
-#include <linux/module.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
@@ -29,9 +28,6 @@
 #include <asm/proc-fns.h>
 #include <asm/mach-types.h>
-void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
-EXPORT_SYMBOL_GPL(imx_ioremap);
 static void __iomem *wdog_base;
 /*
diff --git a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
index 826de74bfdd1..c08a54d9d889 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
@@ -45,6 +45,12 @@
 #define NMK_GPIO_ALT_B  2
 #define NMK_GPIO_ALT_C  (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
+#define NMK_GPIO_ALT_CX_SHIFT 2
+#define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
+#define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
+#define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
+#define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
 /* Pull up/down values */
 enum nmk_gpio_pull {
        NMK_GPIO_PULL_NONE,
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
index 9c949c7c98a7..3b8ec60af351 100644
--- a/arch/arm/plat-nomadik/include/plat/pincfg.h
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -25,6 +25,8 @@
 *      bit 19..20 - SLPM direction
 *      bit 21..22 - SLPM Value (if output)
 *      bit 23..25 - PDIS value (if input)
+ *      bit     26 - Gpio mode
+ *      bit     27 - Sleep mode
 *
 * to facilitate the definition, the following macros are provided
 *
diff --git a/arch/arm/plat-nomadik/include/plat/ske.h b/arch/arm/plat-nomadik/include/plat/ske.h
deleted file mode 100644
index 31382fbc07dc..000000000000
--- a/arch/arm/plat-nomadik/include/plat/ske.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License Terms: GNU General Public License v2
- * Author: Naveen Kumar Gaddipati <naveen.gaddipati@stericsson.com>
- *
- * ux500 Scroll key and Keypad Encoder (SKE) header
- */
-#ifndef __SKE_H
-#define __SKE_H
-#include <linux/input/matrix_keypad.h>
-/* register definitions for SKE peripheral */
-#define SKE_CR          0x00
-#define SKE_VAL0        0x04
-#define SKE_VAL1        0x08
-#define SKE_DBCR        0x0C
-#define SKE_IMSC        0x10
-#define SKE_RIS         0x14
-#define SKE_MIS         0x18
-#define SKE_ICR         0x1C
-/*
- * Keypad module
- */
-/**
- * struct keypad_platform_data - structure for platform specific data
- * @init:       pointer to keypad init function
- * @exit:       pointer to keypad deinitialisation function
- * @keymap_data: matrix scan code table for keycodes
- * @krow:       maximum number of rows
- * @kcol:       maximum number of columns
- * @debounce_ms: platform specific debounce time
- * @no_autorepeat: flag for auto repetition
- * @wakeup_enable: allow waking up the system
- */
-struct ske_keypad_platform_data {
-        int (*init)(void);
-        int (*exit)(void);
-        const struct matrix_keymap_data *keymap_data;
-        u8 krow;
-        u8 kcol;
-        u8 debounce_ms;
-        bool no_autorepeat;
-        bool wakeup_enable;
-};
-#endif  /*__SKE_KPD_H*/
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index dd36eba9506c..c9d1c3603bbf 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -25,6 +25,7 @@ config ARCH_OMAP2PLUS
        bool "TI OMAP2/3/4"
        select CLKDEV_LOOKUP
        select GENERIC_IRQ_CHIP
+        select SPARSE_IRQ
        select OMAP_DM_TIMER
        select USE_OF
        select PROC_DEVICETREE if PROC_FS
@@ -41,13 +42,14 @@ config OMAP_DEBUG_DEVICES
          For debug cards on TI reference boards.
 config OMAP_DEBUG_LEDS
-        bool
+        def_bool y if NEW_LEDS
+        select LEDS_CLASS
        depends on OMAP_DEBUG_DEVICES
-        default y if LEDS_CLASS
 config POWER_AVS_OMAP
        bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2"
        depends on POWER_AVS && (ARCH_OMAP3 || ARCH_OMAP4) && PM
+        select POWER_SUPPLY
        help
          Say Y to enable AVS(Adaptive Voltage Scaling)
          support on OMAP containing the version 1 or
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 961bf859bc0c..dacaee009a4e 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,8 +3,7 @@
 #
 # Common support
-obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
+obj-y := common.o sram.o clock.o dma.o fb.o counter_32k.o
-         fb.o counter_32k.o
 obj-m :=
 obj-n :=
 obj-  :=
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 706b7e29397f..9d7ac20ef8f9 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -312,33 +312,6 @@ void clk_enable_init_clocks(void)
        }
 }
-/**
- * omap_clk_get_by_name - locate OMAP struct clk by its name
- * @name: name of the struct clk to locate
- *
- * Locate an OMAP struct clk by its name.  Assumes that struct clk
- * names are unique.  Returns NULL if not found or a pointer to the
- * struct clk if found.
- */
-struct clk *omap_clk_get_by_name(const char *name)
-{
-        struct clk *c;
-        struct clk *ret = NULL;
-        mutex_lock(&clocks_mutex);
-        list_for_each_entry(c, &clocks, node) {
-                if (!strcmp(c->name, name)) {
-                        ret = c;
-                        break;
-                }
-        }
-        mutex_unlock(&clocks_mutex);
-        return ret;
-}
 int omap_clk_enable_autoidle_all(void)
 {
        struct clk *c;
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 89a3723b3538..111315a69354 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -17,52 +17,12 @@
 #include <linux/dma-mapping.h>
 #include <plat/common.h>
-#include <plat/board.h>
 #include <plat/vram.h>
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 #include <plat/dma.h>
 #include <plat/omap-secure.h>
-#define NO_LENGTH_CHECK 0xffffffff
-struct omap_board_config_kernel *omap_board_config __initdata;
-int omap_board_config_size;
-static const void *__init get_config(u16 tag, size_t len,
-                int skip, size_t *len_out)
-{
-        struct omap_board_config_kernel *kinfo = NULL;
-        int i;
-        /* Try to find the config from the board-specific structures
-         * in the kernel. */
-        for (i = 0; i < omap_board_config_size; i++) {
-                if (omap_board_config[i].tag == tag) {
-                        if (skip == 0) {
-                                kinfo = &omap_board_config[i];
-                                break;
-                        } else {
-                                skip--;
-                        }
-                }
-        }
-        if (kinfo == NULL)
-                return NULL;
-        return kinfo->data;
-}
-const void *__init __omap_get_config(u16 tag, size_t len, int nr)
-{
-        return get_config(tag, len, nr, NULL);
-}
-const void *__init omap_get_var_config(u16 tag, size_t *len)
-{
-        return get_config(tag, NO_LENGTH_CHECK, 0, len);
-}
 void __init omap_reserve(void)
 {
        omap_vram_reserve_sdram_memblock();
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index dbf1e03029a5..87ba8dd0d791 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -22,10 +22,7 @@
 #include <asm/mach/time.h>
 #include <asm/sched_clock.h>
-#include <plat/hardware.h>
 #include <plat/common.h>
-#include <plat/board.h>
 #include <plat/clock.h>
 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
@@ -55,22 +52,29 @@ static u32 notrace omap_32k_read_sched_clock(void)
 * nsecs and adds to a monotonically increasing timespec.
 */
 static struct timespec persistent_ts;
-static cycles_t cycles, last_cycles;
+static cycles_t cycles;
 static unsigned int persistent_mult, persistent_shift;
+static DEFINE_SPINLOCK(read_persistent_clock_lock);
 static void omap_read_persistent_clock(struct timespec *ts)
 {
        unsigned long long nsecs;
-        cycles_t delta;
+        cycles_t last_cycles;
-        struct timespec *tsp = &persistent_ts;
+        unsigned long flags;
+        spin_lock_irqsave(&read_persistent_clock_lock, flags);
        last_cycles = cycles;
        cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
-        delta = cycles - last_cycles;
-        nsecs = clocksource_cyc2ns(delta, persistent_mult, persistent_shift);
+        nsecs = clocksource_cyc2ns(cycles - last_cycles,
+                                        persistent_mult, persistent_shift);
+        timespec_add_ns(&persistent_ts, nsecs);
+        *ts = persistent_ts;
-        timespec_add_ns(tsp, nsecs);
+        spin_unlock_irqrestore(&read_persistent_clock_lock, flags);
-        *ts = *tsp;
 }
 /**
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index caa1f7b6cc21..c7a4c0902b38 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -17,9 +17,6 @@
 #include <mach/hardware.h>
-#include <plat/board.h>
 /* Many OMAP development platforms reuse the same "debug board"; these
 * platforms include H2, H3, H4, and Perseus2.
 */
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 39407cbe34c6..ea29bbe8e5cf 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -1,279 +1,119 @@
 /*
 * linux/arch/arm/plat-omap/debug-leds.c
 *
+ * Copyright 2011 by Bryan Wu <bryan.wu@canonical.com>
 * Copyright 2003 by Texas Instruments Incorporated
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <linux/gpio.h>
+#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/leds.h>
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/slab.h>
 #include <mach/hardware.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <plat/fpga.h>
 /* Many OMAP development platforms reuse the same "debug board"; these
 * platforms include H2, H3, H4, and Perseus2.  There are 16 LEDs on the
 * debug board (all green), accessed through FPGA registers.
- *
- * The "surfer" expansion board and H2 sample board also have two-color
- * green+red LEDs (in parallel), used here for timer and idle indicators
- * in preference to the ones on the debug board, for a "Disco LED" effect.
- *
- * This driver exports either the original ARM LED API, the new generic
- * one, or both.
- */
-static spinlock_t                       lock;
-static struct h2p2_dbg_fpga __iomem     *fpga;
-static u16                              led_state, hw_led_state;
-#ifdef  CONFIG_OMAP_DEBUG_LEDS
-#define new_led_api()   1
-#else
-#define new_led_api()   0
-#endif
-/*-------------------------------------------------------------------------*/
-/* original ARM debug LED API:
- *  - timer and idle leds (some boards use non-FPGA leds here);
- *  - up to 4 generic leds, easily accessed in-kernel (any context)
 */
-#define GPIO_LED_RED            3
+static struct h2p2_dbg_fpga __iomem *fpga;
-#define GPIO_LED_GREEN          OMAP_MPUIO(4)
-#define LED_STATE_ENABLED       0x01
-#define LED_STATE_CLAIMED       0x02
-#define LED_TIMER_ON            0x04
-#define GPIO_IDLE               GPIO_LED_GREEN
-#define GPIO_TIMER              GPIO_LED_RED
-static void h2p2_dbg_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&lock, flags);
-        if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
-                goto done;
-        switch (evt) {
-        case led_start:
-                if (fpga)
-                        led_state |= LED_STATE_ENABLED;
-                break;
-        case led_stop:
-        case led_halted:
-                /* all leds off during suspend or shutdown */
-                if (!(machine_is_omap_perseus2() || machine_is_omap_h4())) {
-                        gpio_set_value(GPIO_TIMER, 0);
-                        gpio_set_value(GPIO_IDLE, 0);
-                }
-                __raw_writew(~0, &fpga->leds);
-                led_state &= ~LED_STATE_ENABLED;
-                goto done;
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                break;
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                led_state ^= LED_TIMER_ON;
-                if (machine_is_omap_perseus2() || machine_is_omap_h4())
-                        hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER;
-                else {
-                        gpio_set_value(GPIO_TIMER,
-                                        led_state & LED_TIMER_ON);
-                        goto done;
-                }
-                break;
-#endif
-#ifdef CONFIG_LEDS_CPU
-        /* LED lit iff busy */
-        case led_idle_start:
-                if (machine_is_omap_perseus2() || machine_is_omap_h4())
-                        hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE;
-                else {
-                        gpio_set_value(GPIO_IDLE, 1);
-                        goto done;
-                }
-                break;
-        case led_idle_end:
+static u16 fpga_led_state;
-                if (machine_is_omap_perseus2() || machine_is_omap_h4())
-                        hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE;
-                else {
-                        gpio_set_value(GPIO_IDLE, 0);
-                        goto done;
-                }
-                break;
-#endif
-        case led_green_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_GREEN;
-                break;
-        case led_green_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_GREEN;
-                break;
-        case led_amber_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_AMBER;
-                break;
-        case led_amber_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_AMBER;
-                break;
-        case led_red_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_RED;
-                break;
-        case led_red_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_RED;
-                break;
-        case led_blue_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_BLUE;
-                break;
-        case led_blue_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_BLUE;
-                break;
-        default:
-                break;
-        }
-        /*
-         *  Actually burn the LEDs
-         */
-        if (led_state & LED_STATE_ENABLED)
-                __raw_writew(~hw_led_state, &fpga->leds);
-done:
-        spin_unlock_irqrestore(&lock, flags);
-}
-/*-------------------------------------------------------------------------*/
-/* "new" LED API
- *  - with syfs access and generic triggering
- *  - not readily accessible to in-kernel drivers
- */
 struct dbg_led {
        struct led_classdev     cdev;
        u16                     mask;
 };
-static struct dbg_led dbg_leds[] = {
+static const struct {
-        /* REVISIT at least H2 uses different timer & cpu leds... */
+        const char *name;
-#ifndef CONFIG_LEDS_TIMER
+        const char *trigger;
-        { .mask = 1 << 0,  .cdev.name =  "d4:green",
+} dbg_leds[] = {
-                .cdev.default_trigger = "heartbeat", },
+        { "dbg:d4", "heartbeat", },
-#endif
+        { "dbg:d5", "cpu0", },
-#ifndef CONFIG_LEDS_CPU
+        { "dbg:d6", "default-on", },
-        { .mask = 1 << 1,  .cdev.name =  "d5:green", },         /* !idle */
+        { "dbg:d7", },
-#endif
+        { "dbg:d8", },
-        { .mask = 1 << 2,  .cdev.name =  "d6:green", },
+        { "dbg:d9", },
-        { .mask = 1 << 3,  .cdev.name =  "d7:green", },
+        { "dbg:d10", },
+        { "dbg:d11", },
-        { .mask = 1 << 4,  .cdev.name =  "d8:green", },
+        { "dbg:d12", },
-        { .mask = 1 << 5,  .cdev.name =  "d9:green", },
+        { "dbg:d13", },
-        { .mask = 1 << 6,  .cdev.name = "d10:green", },
+        { "dbg:d14", },
-        { .mask = 1 << 7,  .cdev.name = "d11:green", },
+        { "dbg:d15", },
+        { "dbg:d16", },
-        { .mask = 1 << 8,  .cdev.name = "d12:green", },
+        { "dbg:d17", },
-        { .mask = 1 << 9,  .cdev.name = "d13:green", },
+        { "dbg:d18", },
-        { .mask = 1 << 10, .cdev.name = "d14:green", },
+        { "dbg:d19", },
-        { .mask = 1 << 11, .cdev.name = "d15:green", },
-#ifndef CONFIG_LEDS
-        { .mask = 1 << 12, .cdev.name = "d16:green", },
-        { .mask = 1 << 13, .cdev.name = "d17:green", },
-        { .mask = 1 << 14, .cdev.name = "d18:green", },
-        { .mask = 1 << 15, .cdev.name = "d19:green", },
-#endif
 };
-static void
+/*
-fpga_led_set(struct led_classdev *cdev, enum led_brightness value)
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static void dbg_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
 {
-        struct dbg_led  *led = container_of(cdev, struct dbg_led, cdev);
+        struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
-        unsigned long   flags;
+        u16 reg;
-        spin_lock_irqsave(&lock, flags);
+        reg = __raw_readw(&fpga->leds);
-        if (value == LED_OFF)
+        if (b != LED_OFF)
-                hw_led_state &= ~led->mask;
+                reg |= led->mask;
        else
-                hw_led_state |= led->mask;
+                reg &= ~led->mask;
-        __raw_writew(~hw_led_state, &fpga->leds);
+        __raw_writew(reg, &fpga->leds);
-        spin_unlock_irqrestore(&lock, flags);
 }
-static void __init newled_init(struct device *dev)
+static enum led_brightness dbg_led_get(struct led_classdev *cdev)
 {
-        unsigned        i;
+        struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
-        struct dbg_led  *led;
+        u16 reg;
-        int             status;
-        for (i = 0, led = dbg_leds; i < ARRAY_SIZE(dbg_leds); i++, led++) {
+        reg = __raw_readw(&fpga->leds);
-                led->cdev.brightness_set = fpga_led_set;
+        return (reg & led->mask) ? LED_FULL : LED_OFF;
-                status = led_classdev_register(dev, &led->cdev);
-                if (status < 0)
-                        break;
-        }
-        return;
 }
+static int fpga_probe(struct platform_device *pdev)
-/*-------------------------------------------------------------------------*/
-static int /* __init */ fpga_probe(struct platform_device *pdev)
 {
        struct resource *iomem;
+        int i;
-        spin_lock_init(&lock);
        iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        if (!iomem)
                return -ENODEV;
        fpga = ioremap(iomem->start, H2P2_DBG_FPGA_SIZE);
-        __raw_writew(~0, &fpga->leds);
+        __raw_writew(0xff, &fpga->leds);
+        for (i = 0; i < ARRAY_SIZE(dbg_leds); i++) {
+                struct dbg_led *led;
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
-#ifdef  CONFIG_LEDS
+                led->cdev.name = dbg_leds[i].name;
-        leds_event = h2p2_dbg_leds_event;
+                led->cdev.brightness_set = dbg_led_set;
-        leds_event(led_start);
+                led->cdev.brightness_get = dbg_led_get;
-#endif
+                led->cdev.default_trigger = dbg_leds[i].trigger;
+                led->mask = BIT(i);
-        if (new_led_api()) {
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
-                newled_init(&pdev->dev);
+                        kfree(led);
+                        break;
+                }
        }
        return 0;
@@ -281,13 +121,15 @@ static int /* __init */ fpga_probe(struct platform_device *pdev)
 static int fpga_suspend_noirq(struct device *dev)
 {
-        __raw_writew(~0, &fpga->leds);
+        fpga_led_state = __raw_readw(&fpga->leds);
+        __raw_writew(0xff, &fpga->leds);
        return 0;
 }
 static int fpga_resume_noirq(struct device *dev)
 {
-        __raw_writew(~hw_led_state, &fpga->leds);
+        __raw_writew(~fpga_led_state, &fpga->leds);
        return 0;
 }
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
deleted file mode 100644
index 1cba9273d2cb..000000000000
--- a/arch/arm/plat-omap/devices.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * linux/arch/arm/plat-omap/devices.c
- *
- * Common platform device setup/initialization for OMAP1 and OMAP2
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/gpio.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/memblock.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/map.h>
-#include <asm/memblock.h>
-#include <plat/tc.h>
-#include <plat/board.h>
-#include <plat/mmc.h>
-#include <plat/menelaus.h>
-#include <plat/omap44xx.h>
-/*-------------------------------------------------------------------------*/
-#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
-#ifdef CONFIG_ARCH_OMAP2
-#define OMAP_RNG_BASE           0x480A0000
-#else
-#define OMAP_RNG_BASE           0xfffe5000
-#endif
-static struct resource rng_resources[] = {
-        {
-                .start          = OMAP_RNG_BASE,
-                .end            = OMAP_RNG_BASE + 0x4f,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-static struct platform_device omap_rng_device = {
-        .name           = "omap_rng",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(rng_resources),
-        .resource       = rng_resources,
-};
-static void omap_init_rng(void)
-{
-        (void) platform_device_register(&omap_rng_device);
-}
-#else
-static inline void omap_init_rng(void) {}
-#endif
-/*
- * This gets called after board-specific INIT_MACHINE, and initializes most
- * on-chip peripherals accessible on this board (except for few like USB):
- *
- *  (a) Does any "standard config" pin muxing needed.  Board-specific
- *      code will have muxed GPIO pins and done "nonstandard" setup;
- *      that code could live in the boot loader.
- *  (b) Populating board-specific platform_data with the data drivers
- *      rely on to handle wiring variations.
- *  (c) Creating platform devices as meaningful on this board and
- *      with this kernel configuration.
- *
- * Claiming GPIOs, and setting their direction and initial values, is the
- * responsibility of the device drivers.  So is responding to probe().
- *
- * Board-specific knowledge like creating devices or pin setup is to be
- * kept out of drivers as much as possible.  In particular, pin setup
- * may be handled by the boot loader, and drivers should expect it will
- * normally have been done by the time they're probed.
- */
-static int __init omap_init_devices(void)
-{
-        /* please keep these calls, and their implementations above,
-         * in alphabetical order so they're easier to sort through.
-         */
-        omap_init_rng();
-        return 0;
-}
-arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7fe626761e53..c76ed8bff838 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -36,9 +36,8 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
-#include <mach/hardware.h>
+#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
 /*
@@ -969,8 +968,7 @@ void omap_stop_dma(int lch)
                        l = p->dma_read(CCR, lch);
                }
                if (i >= 100)
-                        printk(KERN_ERR "DMA drain did not complete on "
+                        pr_err("DMA drain did not complete on lch %d\n", lch);
-                                        "lch %d\n", lch);
                /* Restore OCP_SYSCONFIG */
                p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
        } else {
@@ -1154,8 +1152,7 @@ void omap_dma_link_lch(int lch_head, int lch_queue)
        if ((dma_chan[lch_head].dev_id == -1) ||
            (dma_chan[lch_queue].dev_id == -1)) {
-                printk(KERN_ERR "omap_dma: trying to link "
+                pr_err("omap_dma: trying to link non requested channels\n");
-                       "non requested channels\n");
                dump_stack();
        }
@@ -1181,15 +1178,13 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
        if (dma_chan[lch_head].next_lch != lch_queue ||
            dma_chan[lch_head].next_lch == -1) {
-                printk(KERN_ERR "omap_dma: trying to unlink "
+                pr_err("omap_dma: trying to unlink non linked channels\n");
-                       "non linked channels\n");
                dump_stack();
        }
        if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
            (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
-                printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
+                pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
-                       "before unlinking\n");
                dump_stack();
        }
@@ -1831,16 +1826,15 @@ static int omap1_dma_handle_ch(int ch)
        if ((csr & 0x3f) == 0)
                return 0;
        if (unlikely(dma_chan[ch].dev_id == -1)) {
-                printk(KERN_WARNING "Spurious interrupt from DMA channel "
+                pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
-                       "%d (CSR %04x)\n", ch, csr);
+                        ch, csr);
                return 0;
        }
        if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
-                printk(KERN_WARNING "DMA timeout with device %d\n",
+                pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
-                       dma_chan[ch].dev_id);
        if (unlikely(csr & OMAP_DMA_DROP_IRQ))
-                printk(KERN_WARNING "DMA synchronization event drop occurred "
+                pr_warn("DMA synchronization event drop occurred with device %d\n",
-                       "with device %d\n", dma_chan[ch].dev_id);
+                        dma_chan[ch].dev_id);
        if (likely(csr & OMAP_DMA_BLOCK_IRQ))
                dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
        if (likely(dma_chan[ch].callback != NULL))
@@ -1880,21 +1874,19 @@ static int omap2_dma_handle_ch(int ch)
        if (!status) {
                if (printk_ratelimit())
-                        printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
+                        pr_warn("Spurious DMA IRQ for lch %d\n", ch);
-                                ch);
                p->dma_write(1 << ch, IRQSTATUS_L0, ch);
                return 0;
        }
        if (unlikely(dma_chan[ch].dev_id == -1)) {
                if (printk_ratelimit())
-                        printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
+                        pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
-                                        "channel %d\n", status, ch);
+                                status, ch);
                return 0;
        }
        if (unlikely(status & OMAP_DMA_DROP_IRQ))
-                printk(KERN_INFO
+                pr_info("DMA synchronization event drop occurred with device %d\n",
-                       "DMA synchronization event drop occurred with device "
+                        dma_chan[ch].dev_id);
-                       "%d\n", dma_chan[ch].dev_id);
        if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
                printk(KERN_INFO "DMA transaction error with device %d\n",
                       dma_chan[ch].dev_id);
@@ -2014,8 +2006,9 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
        p = pdev->dev.platform_data;
        if (!p) {
-                dev_err(&pdev->dev, "%s: System DMA initialized without"
+                dev_err(&pdev->dev,
-                        "platform data\n", __func__);
+                        "%s: System DMA initialized without platform data\n",
+                        __func__);
                return -EINVAL;
        }
@@ -2090,8 +2083,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
                }
                ret = setup_irq(dma_irq, &omap24xx_dma_irq);
                if (ret) {
-                        dev_err(&pdev->dev, "set_up failed for IRQ %d"
+                        dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
-                                "for DMA (error %d)\n", dma_irq, ret);
+                                dma_irq, ret);
                        goto exit_dma_lch_fail;
                }
        }
@@ -2099,8 +2092,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
        /* reserve dma channels 0 and 1 in high security devices */
        if (cpu_is_omap34xx() &&
                (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
-                printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
+                pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
-                                "HS ROM code\n");
                dma_chan[0].dev_id = 0;
                dma_chan[1].dev_id = 1;
        }
@@ -2108,8 +2100,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
        return 0;
 exit_dma_irq_fail:
-        dev_err(&pdev->dev, "unable to request IRQ %d"
+        dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
-                        "for DMA (error %d)\n", dma_irq, ret);
+                dma_irq, ret);
        for (irq_rel = 0; irq_rel < ch; irq_rel++) {
                dma_irq = platform_get_irq(pdev, irq_rel);
                free_irq(dma_irq, (void *)(irq_rel + 1));
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index dd6f92c99e56..bcbb9d5dc293 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -33,8 +33,6 @@
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
-#include <plat/board.h>
 #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
 static bool omapfb_lcd_configured;
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index db071bc71c4d..a5683a84c6ee 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -26,19 +26,17 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
-#include <linux/i2c-omap.h>
 #include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <mach/irqs.h>
-#include <plat/mux.h>
 #include <plat/i2c.h>
-#include <plat/omap-pm.h>
 #include <plat/omap_device.h>
 #define OMAP_I2C_SIZE           0x3f
 #define OMAP1_I2C_BASE          0xfffb3800
+#define OMAP1_INT_I2C           (32 + 4)
 static const char name[] = "omap_i2c";
@@ -105,7 +103,7 @@ static inline int omap1_i2c_add_bus(int bus_id)
        res = pdev->resource;
        res[0].start = OMAP1_I2C_BASE;
        res[0].end = res[0].start + OMAP_I2C_SIZE;
-        res[1].start = INT_I2C;
+        res[1].start = OMAP1_INT_I2C;
        pdata = &i2c_pdata[bus_id - 1];
        /* all OMAP1 have IP version 1 register set */
@@ -129,16 +127,6 @@ static inline int omap1_i2c_add_bus(int bus_id)
 #ifdef CONFIG_ARCH_OMAP2PLUS
-/*
- * XXX This function is a temporary compatibility wrapper - only
- * needed until the I2C driver can be converted to call
- * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
- */
-static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
-{
-        omap_pm_set_max_mpu_wakeup_lat(dev, t);
-}
 static inline int omap2_i2c_add_bus(int bus_id)
 {
        int l;
@@ -170,15 +158,6 @@ static inline int omap2_i2c_add_bus(int bus_id)
        dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
        pdata->flags = dev_attr->flags;
-        /*
-         * When waiting for completion of a i2c transfer, we need to
-         * set a wake up latency constraint for the MPU. This is to
-         * ensure quick enough wakeup from idle, when transfer
-         * completes.
-         * Only omap3 has support for constraints
-         */
-        if (cpu_is_omap34xx())
-                pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
        pdev = omap_device_build(name, bus_id, oh, pdata,
                        sizeof(struct omap_i2c_bus_platform_data),
                        NULL, 0, 0);
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
deleted file mode 100644
index e62f20a5c0af..000000000000
--- a/arch/arm/plat-omap/include/plat/board.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/board.h
- *
- *  Information structures for board-specific data
- *
- *  Copyright (C) 2004  Nokia Corporation
- *  Written by Juha Yrjölä <juha.yrjola@nokia.com>
- */
-#ifndef _OMAP_BOARD_H
-#define _OMAP_BOARD_H
-#include <linux/types.h>
-#include <plat/gpio-switch.h>
-/*
- * OMAP35x EVM revision
- * Run time detection of EVM revision is done by reading Ethernet
- * PHY ID -
- *      GEN_1   = 0x01150000
- *      GEN_2   = 0x92200000
- */
-enum {
-        OMAP3EVM_BOARD_GEN_1 = 0,       /* EVM Rev between  A - D */
-        OMAP3EVM_BOARD_GEN_2,           /* EVM Rev >= Rev E */
-};
-/* Different peripheral ids */
-#define OMAP_TAG_CLOCK          0x4f01
-#define OMAP_TAG_GPIO_SWITCH    0x4f06
-#define OMAP_TAG_STI_CONSOLE    0x4f09
-#define OMAP_TAG_CAMERA_SENSOR  0x4f0a
-#define OMAP_TAG_BOOT_REASON    0x4f80
-#define OMAP_TAG_FLASH_PART     0x4f81
-#define OMAP_TAG_VERSION_STR    0x4f82
-struct omap_clock_config {
-        /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
-        u8 system_clock_type;
-};
-struct omap_serial_console_config {
-        u8 console_uart;
-        u32 console_speed;
-};
-struct omap_sti_console_config {
-        unsigned enable:1;
-        u8 channel;
-};
-struct omap_camera_sensor_config {
-        u16 reset_gpio;
-        int (*power_on)(void * data);
-        int (*power_off)(void * data);
-};
-struct omap_lcd_config {
-        char panel_name[16];
-        char ctrl_name[16];
-        s16  nreset_gpio;
-        u8   data_lines;
-};
-struct device;
-struct fb_info;
-struct omap_backlight_config {
-        int default_intensity;
-        int (*set_power)(struct device *dev, int state);
-};
-struct omap_fbmem_config {
-        u32 start;
-        u32 size;
-};
-struct omap_pwm_led_platform_data {
-        const char *name;
-        int intensity_timer;
-        int blink_timer;
-        void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
-};
-struct omap_uart_config {
-        /* Bit field of UARTs present; bit 0 --> UART1 */
-        unsigned int enabled_uarts;
-};
-struct omap_flash_part_config {
-        char part_table[0];
-};
-struct omap_boot_reason_config {
-        char reason_str[12];
-};
-struct omap_version_config {
-        char component[12];
-        char version[12];
-};
-struct omap_board_config_entry {
-        u16 tag;
-        u16 len;
-        u8  data[0];
-};
-struct omap_board_config_kernel {
-        u16 tag;
-        const void *data;
-};
-extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
-#define omap_get_config(tag, type) \
-        ((const type *) __omap_get_config((tag), sizeof(type), 0))
-#define omap_get_nr_config(tag, type, nr) \
-        ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
-extern const void *__init omap_get_var_config(u16 tag, size_t *len);
-extern struct omap_board_config_kernel *omap_board_config;
-extern int omap_board_config_size;
-/* for TI reference platforms sharing the same debug card */
-extern int debug_card_init(u32 addr, unsigned gpio);
-/* OMAP3EVM revision */
-#if defined(CONFIG_MACH_OMAP3EVM)
-u8 get_omap3_evm_rev(void);
-#else
-#define get_omap3_evm_rev() (-EINVAL)
-#endif
-#endif
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 656b9862279e..e2e2d045e428 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -19,6 +19,11 @@ struct module;
 struct clk;
 struct clockdomain;
+/* Temporary, needed during the common clock framework conversion */
+#define __clk_get_name(clk)     (clk->name)
+#define __clk_get_parent(clk)   (clk->parent)
+#define __clk_get_rate(clk)     (clk->rate)
 /**
 * struct clkops - some clock function pointers
 * @enable: fn ptr that enables the current clock in hardware
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index bb5d08a70dbc..67da857783ce 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -30,6 +30,8 @@
 #ifndef __ASM_ARCH_OMAP_CPU_H
 #define __ASM_ARCH_OMAP_CPU_H
+#ifndef __ASSEMBLY__
 #include <linux/bitops.h>
 #include <plat/multi.h>
@@ -493,4 +495,5 @@ OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
 OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
 OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
+#endif  /* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index c5811d4409b0..0a87b052f8f7 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -31,6 +31,8 @@
 /* Move omap4 specific defines to dma-44xx.h */
 #include "dma-44xx.h"
+#define INT_DMA_LCD                     25
 /* DMA channels for omap1 */
 #define OMAP_DMA_NO_DEVICE              0
 #define OMAP_DMA_MCSI1_TX               1
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 19e7fa577bd0..85868e98c11c 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -60,6 +60,7 @@
 #define OMAP_TIMER_ALWON                                0x40000000
 #define OMAP_TIMER_HAS_PWM                              0x20000000
 #define OMAP_TIMER_NEEDS_RESET                          0x10000000
+#define OMAP_TIMER_HAS_DSP_IRQ                          0x08000000
 struct omap_timer_capability_dev_attr {
        u32 timer_capability;
diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h
deleted file mode 100644
index 5927709b1908..000000000000
--- a/arch/arm/plat-omap/include/plat/dsp.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef __OMAP_DSP_H__
-#define __OMAP_DSP_H__
-#include <linux/types.h>
-struct omap_dsp_platform_data {
-        void (*dsp_set_min_opp) (u8 opp_id);
-        u8 (*dsp_get_opp) (void);
-        void (*cpu_set_freq) (unsigned long f);
-        unsigned long (*cpu_get_freq) (void);
-        unsigned long mpu_speed[6];
-        /* functions to write and read PRCM registers */
-        void (*dsp_prm_write)(u32, s16 , u16);
-        u32 (*dsp_prm_read)(s16 , u16);
-        u32 (*dsp_prm_rmw_bits)(u32, u32, s16, s16);
-        void (*dsp_cm_write)(u32, s16 , u16);
-        u32 (*dsp_cm_read)(s16 , u16);
-        u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16);
-        void (*set_bootaddr)(u32);
-        void (*set_bootmode)(u8);
-        phys_addr_t phys_mempool_base;
-        phys_addr_t phys_mempool_size;
-};
-#if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE)
-extern void omap_dsp_reserve_sdram_memblock(void);
-#else
-static inline void omap_dsp_reserve_sdram_memblock(void) { }
-#endif
-#endif
diff --git a/arch/arm/plat-omap/include/plat/gpio-switch.h b/arch/arm/plat-omap/include/plat/gpio-switch.h
deleted file mode 100644
index 10da0e07c0cf..000000000000
--- a/arch/arm/plat-omap/include/plat/gpio-switch.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * GPIO switch definitions
- *
- * Copyright (C) 2006 Nokia Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
-#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
-#include <linux/types.h>
-/* Cover:
- *      high -> closed
- *      low  -> open
- * Connection:
- *      high -> connected
- *      low  -> disconnected
- * Activity:
- *      high -> active
- *      low  -> inactive
- *
- */
-#define OMAP_GPIO_SWITCH_TYPE_COVER             0x0000
-#define OMAP_GPIO_SWITCH_TYPE_CONNECTION        0x0001
-#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY          0x0002
-#define OMAP_GPIO_SWITCH_FLAG_INVERTED          0x0001
-#define OMAP_GPIO_SWITCH_FLAG_OUTPUT            0x0002
-struct omap_gpio_switch {
-        const char *name;
-        s16 gpio;
-        unsigned flags:4;
-        unsigned type:4;
-        /* Time in ms to debounce when transitioning from
-         * inactive state to active state. */
-        u16 debounce_rising;
-        /* Same for transition from active to inactive state. */
-        u16 debounce_falling;
-        /* notify board-specific code about state changes */
-        void (* notify)(void *data, int state);
-        void *notify_data;
-};
-/* Call at init time only */
-extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
-                                        int count);
-#endif
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
deleted file mode 100644
index 50fb7cc000ea..000000000000
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/gpio.h
- *
- * OMAP GPIO handling defines and functions
- *
- * Copyright (C) 2003-2005 Nokia Corporation
- *
- * Written by Juha Yrjölä <juha.yrjola@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#ifndef __ASM_ARCH_OMAP_GPIO_H
-#define __ASM_ARCH_OMAP_GPIO_H
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <mach/irqs.h>
-#define OMAP1_MPUIO_BASE                        0xfffb5000
-/*
- * These are the omap15xx/16xx offsets. The omap7xx offset are
- * OMAP_MPUIO_ / 2 offsets below.
- */
-#define OMAP_MPUIO_INPUT_LATCH          0x00
-#define OMAP_MPUIO_OUTPUT               0x04
-#define OMAP_MPUIO_IO_CNTL              0x08
-#define OMAP_MPUIO_KBR_LATCH            0x10
-#define OMAP_MPUIO_KBC                  0x14
-#define OMAP_MPUIO_GPIO_EVENT_MODE      0x18
-#define OMAP_MPUIO_GPIO_INT_EDGE        0x1c
-#define OMAP_MPUIO_KBD_INT              0x20
-#define OMAP_MPUIO_GPIO_INT             0x24
-#define OMAP_MPUIO_KBD_MASKIT           0x28
-#define OMAP_MPUIO_GPIO_MASKIT          0x2c
-#define OMAP_MPUIO_GPIO_DEBOUNCING      0x30
-#define OMAP_MPUIO_LATCH                0x34
-#define OMAP34XX_NR_GPIOS               6
-/*
- * OMAP1510 GPIO registers
- */
-#define OMAP1510_GPIO_DATA_INPUT        0x00
-#define OMAP1510_GPIO_DATA_OUTPUT       0x04
-#define OMAP1510_GPIO_DIR_CONTROL       0x08
-#define OMAP1510_GPIO_INT_CONTROL       0x0c
-#define OMAP1510_GPIO_INT_MASK          0x10
-#define OMAP1510_GPIO_INT_STATUS        0x14
-#define OMAP1510_GPIO_PIN_CONTROL       0x18
-#define OMAP1510_IH_GPIO_BASE           64
-/*
- * OMAP1610 specific GPIO registers
- */
-#define OMAP1610_GPIO_REVISION          0x0000
-#define OMAP1610_GPIO_SYSCONFIG         0x0010
-#define OMAP1610_GPIO_SYSSTATUS         0x0014
-#define OMAP1610_GPIO_IRQSTATUS1        0x0018
-#define OMAP1610_GPIO_IRQENABLE1        0x001c
-#define OMAP1610_GPIO_WAKEUPENABLE      0x0028
-#define OMAP1610_GPIO_DATAIN            0x002c
-#define OMAP1610_GPIO_DATAOUT           0x0030
-#define OMAP1610_GPIO_DIRECTION         0x0034
-#define OMAP1610_GPIO_EDGE_CTRL1        0x0038
-#define OMAP1610_GPIO_EDGE_CTRL2        0x003c
-#define OMAP1610_GPIO_CLEAR_IRQENABLE1  0x009c
-#define OMAP1610_GPIO_CLEAR_WAKEUPENA   0x00a8
-#define OMAP1610_GPIO_CLEAR_DATAOUT     0x00b0
-#define OMAP1610_GPIO_SET_IRQENABLE1    0x00dc
-#define OMAP1610_GPIO_SET_WAKEUPENA     0x00e8
-#define OMAP1610_GPIO_SET_DATAOUT       0x00f0
-/*
- * OMAP7XX specific GPIO registers
- */
-#define OMAP7XX_GPIO_DATA_INPUT         0x00
-#define OMAP7XX_GPIO_DATA_OUTPUT        0x04
-#define OMAP7XX_GPIO_DIR_CONTROL        0x08
-#define OMAP7XX_GPIO_INT_CONTROL        0x0c
-#define OMAP7XX_GPIO_INT_MASK           0x10
-#define OMAP7XX_GPIO_INT_STATUS         0x14
-/*
- * omap2+ specific GPIO registers
- */
-#define OMAP24XX_GPIO_REVISION          0x0000
-#define OMAP24XX_GPIO_IRQSTATUS1        0x0018
-#define OMAP24XX_GPIO_IRQSTATUS2        0x0028
-#define OMAP24XX_GPIO_IRQENABLE2        0x002c
-#define OMAP24XX_GPIO_IRQENABLE1        0x001c
-#define OMAP24XX_GPIO_WAKE_EN           0x0020
-#define OMAP24XX_GPIO_CTRL              0x0030
-#define OMAP24XX_GPIO_OE                0x0034
-#define OMAP24XX_GPIO_DATAIN            0x0038
-#define OMAP24XX_GPIO_DATAOUT           0x003c
-#define OMAP24XX_GPIO_LEVELDETECT0      0x0040
-#define OMAP24XX_GPIO_LEVELDETECT1      0x0044
-#define OMAP24XX_GPIO_RISINGDETECT      0x0048
-#define OMAP24XX_GPIO_FALLINGDETECT     0x004c
-#define OMAP24XX_GPIO_DEBOUNCE_EN       0x0050
-#define OMAP24XX_GPIO_DEBOUNCE_VAL      0x0054
-#define OMAP24XX_GPIO_CLEARIRQENABLE1   0x0060
-#define OMAP24XX_GPIO_SETIRQENABLE1     0x0064
-#define OMAP24XX_GPIO_CLEARWKUENA       0x0080
-#define OMAP24XX_GPIO_SETWKUENA         0x0084
-#define OMAP24XX_GPIO_CLEARDATAOUT      0x0090
-#define OMAP24XX_GPIO_SETDATAOUT        0x0094
-#define OMAP4_GPIO_REVISION             0x0000
-#define OMAP4_GPIO_EOI                  0x0020
-#define OMAP4_GPIO_IRQSTATUSRAW0        0x0024
-#define OMAP4_GPIO_IRQSTATUSRAW1        0x0028
-#define OMAP4_GPIO_IRQSTATUS0           0x002c
-#define OMAP4_GPIO_IRQSTATUS1           0x0030
-#define OMAP4_GPIO_IRQSTATUSSET0        0x0034
-#define OMAP4_GPIO_IRQSTATUSSET1        0x0038
-#define OMAP4_GPIO_IRQSTATUSCLR0        0x003c
-#define OMAP4_GPIO_IRQSTATUSCLR1        0x0040
-#define OMAP4_GPIO_IRQWAKEN0            0x0044
-#define OMAP4_GPIO_IRQWAKEN1            0x0048
-#define OMAP4_GPIO_IRQENABLE1           0x011c
-#define OMAP4_GPIO_WAKE_EN              0x0120
-#define OMAP4_GPIO_IRQSTATUS2           0x0128
-#define OMAP4_GPIO_IRQENABLE2           0x012c
-#define OMAP4_GPIO_CTRL                 0x0130
-#define OMAP4_GPIO_OE                   0x0134
-#define OMAP4_GPIO_DATAIN               0x0138
-#define OMAP4_GPIO_DATAOUT              0x013c
-#define OMAP4_GPIO_LEVELDETECT0         0x0140
-#define OMAP4_GPIO_LEVELDETECT1         0x0144
-#define OMAP4_GPIO_RISINGDETECT         0x0148
-#define OMAP4_GPIO_FALLINGDETECT        0x014c
-#define OMAP4_GPIO_DEBOUNCENABLE        0x0150
-#define OMAP4_GPIO_DEBOUNCINGTIME       0x0154
-#define OMAP4_GPIO_CLEARIRQENABLE1      0x0160
-#define OMAP4_GPIO_SETIRQENABLE1        0x0164
-#define OMAP4_GPIO_CLEARWKUENA          0x0180
-#define OMAP4_GPIO_SETWKUENA            0x0184
-#define OMAP4_GPIO_CLEARDATAOUT         0x0190
-#define OMAP4_GPIO_SETDATAOUT           0x0194
-#define OMAP_MPUIO(nr)          (OMAP_MAX_GPIO_LINES + (nr))
-#define OMAP_GPIO_IS_MPUIO(nr)  ((nr) >= OMAP_MAX_GPIO_LINES)
-struct omap_gpio_dev_attr {
-        int bank_width;         /* GPIO bank width */
-        bool dbck_flag;         /* dbck required or not - True for OMAP3&4 */
-};
-struct omap_gpio_reg_offs {
-        u16 revision;
-        u16 direction;
-        u16 datain;
-        u16 dataout;
-        u16 set_dataout;
-        u16 clr_dataout;
-        u16 irqstatus;
-        u16 irqstatus2;
-        u16 irqstatus_raw0;
-        u16 irqstatus_raw1;
-        u16 irqenable;
-        u16 irqenable2;
-        u16 set_irqenable;
-        u16 clr_irqenable;
-        u16 debounce;
-        u16 debounce_en;
-        u16 ctrl;
-        u16 wkup_en;
-        u16 leveldetect0;
-        u16 leveldetect1;
-        u16 risingdetect;
-        u16 fallingdetect;
-        u16 irqctrl;
-        u16 edgectrl1;
-        u16 edgectrl2;
-        u16 pinctrl;
-        bool irqenable_inv;
-};
-struct omap_gpio_platform_data {
-        int bank_type;
-        int bank_width;         /* GPIO bank width */
-        int bank_stride;        /* Only needed for omap1 MPUIO */
-        bool dbck_flag;         /* dbck required or not - True for OMAP3&4 */
-        bool loses_context;     /* whether the bank would ever lose context */
-        bool is_mpuio;          /* whether the bank is of type MPUIO */
-        u32 non_wakeup_gpios;
-        struct omap_gpio_reg_offs *regs;
-        /* Return context loss count due to PM states changing */
-        int (*get_context_loss_count)(struct device *dev);
-};
-extern void omap2_gpio_prepare_for_idle(int off_mode);
-extern void omap2_gpio_resume_after_idle(void);
-extern void omap_set_gpio_debounce(int gpio, int enable);
-extern void omap_set_gpio_debounce_time(int gpio, int enable);
-/*-------------------------------------------------------------------------*/
-/*
- * Wrappers for "new style" GPIO calls, using the new infrastructure
- * which lets us plug in FPGA, I2C, and other implementations.
- *
- * The original OMAP-specific calls should eventually be removed.
- */
-#include <linux/errno.h>
-#include <asm-generic/gpio.h>
-#endif
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index f37764a36072..2e6e2597178c 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -133,6 +133,25 @@ struct gpmc_timings {
        u16 wr_data_mux_bus;    /* WRDATAONADMUXBUS */
 };
+struct gpmc_nand_regs {
+        void __iomem    *gpmc_status;
+        void __iomem    *gpmc_nand_command;
+        void __iomem    *gpmc_nand_address;
+        void __iomem    *gpmc_nand_data;
+        void __iomem    *gpmc_prefetch_config1;
+        void __iomem    *gpmc_prefetch_config2;
+        void __iomem    *gpmc_prefetch_control;
+        void __iomem    *gpmc_prefetch_status;
+        void __iomem    *gpmc_ecc_config;
+        void __iomem    *gpmc_ecc_control;
+        void __iomem    *gpmc_ecc_size_config;
+        void __iomem    *gpmc_ecc1_result;
+        void __iomem    *gpmc_bch_result0;
+};
+extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
+extern int gpmc_get_client_irq(unsigned irq_config);
 extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
 extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
deleted file mode 100644
index ddbde38e1e33..000000000000
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/hardware.h
- *
- * Hardware definitions for TI OMAP processors and boards
- *
- * NOTE: Please put device driver specific defines into a separate header
- *       file for each driver.
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
- *
- * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
- *                          and Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_ARCH_OMAP_HARDWARE_H
-#define __ASM_ARCH_OMAP_HARDWARE_H
-#include <asm/sizes.h>
-#ifndef __ASSEMBLER__
-#include <asm/types.h>
-#include <plat/cpu.h>
-#endif
-#include <plat/serial.h>
-/*
- * ---------------------------------------------------------------------------
- * Common definitions for all OMAP processors
- * NOTE: Put all processor or board specific parts to the special header
- *       files.
- * ---------------------------------------------------------------------------
- */
-/*
- * ----------------------------------------------------------------------------
- * Timers
- * ----------------------------------------------------------------------------
- */
-#define OMAP_MPU_TIMER1_BASE    (0xfffec500)
-#define OMAP_MPU_TIMER2_BASE    (0xfffec600)
-#define OMAP_MPU_TIMER3_BASE    (0xfffec700)
-#define MPU_TIMER_FREE          (1 << 6)
-#define MPU_TIMER_CLOCK_ENABLE  (1 << 5)
-#define MPU_TIMER_AR            (1 << 1)
-#define MPU_TIMER_ST            (1 << 0)
-/*
- * ----------------------------------------------------------------------------
- * Clocks
- * ----------------------------------------------------------------------------
- */
-#define CLKGEN_REG_BASE         (0xfffece00)
-#define ARM_CKCTL               (CLKGEN_REG_BASE + 0x0)
-#define ARM_IDLECT1             (CLKGEN_REG_BASE + 0x4)
-#define ARM_IDLECT2             (CLKGEN_REG_BASE + 0x8)
-#define ARM_EWUPCT              (CLKGEN_REG_BASE + 0xC)
-#define ARM_RSTCT1              (CLKGEN_REG_BASE + 0x10)
-#define ARM_RSTCT2              (CLKGEN_REG_BASE + 0x14)
-#define ARM_SYSST               (CLKGEN_REG_BASE + 0x18)
-#define ARM_IDLECT3             (CLKGEN_REG_BASE + 0x24)
-#define CK_RATEF                1
-#define CK_IDLEF                2
-#define CK_ENABLEF              4
-#define CK_SELECTF              8
-#define SETARM_IDLE_SHIFT
-/* DPLL control registers */
-#define DPLL_CTL                (0xfffecf00)
-/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
-#define DSP_CONFIG_REG_BASE     IOMEM(0xe1008000)
-#define DSP_CKCTL               (DSP_CONFIG_REG_BASE + 0x0)
-#define DSP_IDLECT1             (DSP_CONFIG_REG_BASE + 0x4)
-#define DSP_IDLECT2             (DSP_CONFIG_REG_BASE + 0x8)
-#define DSP_RSTCT2              (DSP_CONFIG_REG_BASE + 0x14)
-/*
- * ---------------------------------------------------------------------------
- * UPLD
- * ---------------------------------------------------------------------------
- */
-#define ULPD_REG_BASE           (0xfffe0800)
-#define ULPD_IT_STATUS          (ULPD_REG_BASE + 0x14)
-#define ULPD_SETUP_ANALOG_CELL_3        (ULPD_REG_BASE + 0x24)
-#define ULPD_CLOCK_CTRL         (ULPD_REG_BASE + 0x30)
-#       define DIS_USB_PVCI_CLK         (1 << 5)        /* no USB/FAC synch */
-#       define USB_MCLK_EN              (1 << 4)        /* enable W4_USB_CLKO */
-#define ULPD_SOFT_REQ           (ULPD_REG_BASE + 0x34)
-#       define SOFT_UDC_REQ             (1 << 4)
-#       define SOFT_USB_CLK_REQ         (1 << 3)
-#       define SOFT_DPLL_REQ            (1 << 0)
-#define ULPD_DPLL_CTRL          (ULPD_REG_BASE + 0x3c)
-#define ULPD_STATUS_REQ         (ULPD_REG_BASE + 0x40)
-#define ULPD_APLL_CTRL          (ULPD_REG_BASE + 0x4c)
-#define ULPD_POWER_CTRL         (ULPD_REG_BASE + 0x50)
-#define ULPD_SOFT_DISABLE_REQ_REG       (ULPD_REG_BASE + 0x68)
-#       define DIS_MMC2_DPLL_REQ        (1 << 11)
-#       define DIS_MMC1_DPLL_REQ        (1 << 10)
-#       define DIS_UART3_DPLL_REQ       (1 << 9)
-#       define DIS_UART2_DPLL_REQ       (1 << 8)
-#       define DIS_UART1_DPLL_REQ       (1 << 7)
-#       define DIS_USB_HOST_DPLL_REQ    (1 << 6)
-#define ULPD_SDW_CLK_DIV_CTRL_SEL       (ULPD_REG_BASE + 0x74)
-#define ULPD_CAM_CLK_CTRL       (ULPD_REG_BASE + 0x7c)
-/*
- * ---------------------------------------------------------------------------
- * Watchdog timer
- * ---------------------------------------------------------------------------
- */
-/* Watchdog timer within the OMAP3.2 gigacell */
-#define OMAP_MPU_WATCHDOG_BASE  (0xfffec800)
-#define OMAP_WDT_TIMER          (OMAP_MPU_WATCHDOG_BASE + 0x0)
-#define OMAP_WDT_LOAD_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
-#define OMAP_WDT_READ_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
-#define OMAP_WDT_TIMER_MODE     (OMAP_MPU_WATCHDOG_BASE + 0x8)
-/*
- * ---------------------------------------------------------------------------
- * Interrupts
- * ---------------------------------------------------------------------------
- */
-#ifdef CONFIG_ARCH_OMAP1
-/*
- * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
- * or something similar.. -- PFM.
- */
-#define OMAP_IH1_BASE           0xfffecb00
-#define OMAP_IH2_BASE           0xfffe0000
-#define OMAP_IH1_ITR            (OMAP_IH1_BASE + 0x00)
-#define OMAP_IH1_MIR            (OMAP_IH1_BASE + 0x04)
-#define OMAP_IH1_SIR_IRQ        (OMAP_IH1_BASE + 0x10)
-#define OMAP_IH1_SIR_FIQ        (OMAP_IH1_BASE + 0x14)
-#define OMAP_IH1_CONTROL        (OMAP_IH1_BASE + 0x18)
-#define OMAP_IH1_ILR0           (OMAP_IH1_BASE + 0x1c)
-#define OMAP_IH1_ISR            (OMAP_IH1_BASE + 0x9c)
-#define OMAP_IH2_ITR            (OMAP_IH2_BASE + 0x00)
-#define OMAP_IH2_MIR            (OMAP_IH2_BASE + 0x04)
-#define OMAP_IH2_SIR_IRQ        (OMAP_IH2_BASE + 0x10)
-#define OMAP_IH2_SIR_FIQ        (OMAP_IH2_BASE + 0x14)
-#define OMAP_IH2_CONTROL        (OMAP_IH2_BASE + 0x18)
-#define OMAP_IH2_ILR0           (OMAP_IH2_BASE + 0x1c)
-#define OMAP_IH2_ISR            (OMAP_IH2_BASE + 0x9c)
-#define IRQ_ITR_REG_OFFSET      0x00
-#define IRQ_MIR_REG_OFFSET      0x04
-#define IRQ_SIR_IRQ_REG_OFFSET  0x10
-#define IRQ_SIR_FIQ_REG_OFFSET  0x14
-#define IRQ_CONTROL_REG_OFFSET  0x18
-#define IRQ_ISR_REG_OFFSET      0x9c
-#define IRQ_ILR0_REG_OFFSET     0x1c
-#define IRQ_GMR_REG_OFFSET      0xa0
-#endif
-/*
- * ----------------------------------------------------------------------------
- * System control registers
- * ----------------------------------------------------------------------------
- */
-#define MOD_CONF_CTRL_0         0xfffe1080
-#define MOD_CONF_CTRL_1         0xfffe1110
-/*
- * ----------------------------------------------------------------------------
- * Pin multiplexing registers
- * ----------------------------------------------------------------------------
- */
-#define FUNC_MUX_CTRL_0         0xfffe1000
-#define FUNC_MUX_CTRL_1         0xfffe1004
-#define FUNC_MUX_CTRL_2         0xfffe1008
-#define COMP_MODE_CTRL_0        0xfffe100c
-#define FUNC_MUX_CTRL_3         0xfffe1010
-#define FUNC_MUX_CTRL_4         0xfffe1014
-#define FUNC_MUX_CTRL_5         0xfffe1018
-#define FUNC_MUX_CTRL_6         0xfffe101C
-#define FUNC_MUX_CTRL_7         0xfffe1020
-#define FUNC_MUX_CTRL_8         0xfffe1024
-#define FUNC_MUX_CTRL_9         0xfffe1028
-#define FUNC_MUX_CTRL_A         0xfffe102C
-#define FUNC_MUX_CTRL_B         0xfffe1030
-#define FUNC_MUX_CTRL_C         0xfffe1034
-#define FUNC_MUX_CTRL_D         0xfffe1038
-#define PULL_DWN_CTRL_0         0xfffe1040
-#define PULL_DWN_CTRL_1         0xfffe1044
-#define PULL_DWN_CTRL_2         0xfffe1048
-#define PULL_DWN_CTRL_3         0xfffe104c
-#define PULL_DWN_CTRL_4         0xfffe10ac
-/* OMAP-1610 specific multiplexing registers */
-#define FUNC_MUX_CTRL_E         0xfffe1090
-#define FUNC_MUX_CTRL_F         0xfffe1094
-#define FUNC_MUX_CTRL_10        0xfffe1098
-#define FUNC_MUX_CTRL_11        0xfffe109c
-#define FUNC_MUX_CTRL_12        0xfffe10a0
-#define PU_PD_SEL_0             0xfffe10b4
-#define PU_PD_SEL_1             0xfffe10b8
-#define PU_PD_SEL_2             0xfffe10bc
-#define PU_PD_SEL_3             0xfffe10c0
-#define PU_PD_SEL_4             0xfffe10c4
-/* Timer32K for 1610 and 1710*/
-#define OMAP_TIMER32K_BASE      0xFFFBC400
-/*
- * ---------------------------------------------------------------------------
- * TIPB bus interface
- * ---------------------------------------------------------------------------
- */
-#define TIPB_PUBLIC_CNTL_BASE           0xfffed300
-#define MPU_PUBLIC_TIPB_CNTL            (TIPB_PUBLIC_CNTL_BASE + 0x8)
-#define TIPB_PRIVATE_CNTL_BASE          0xfffeca00
-#define MPU_PRIVATE_TIPB_CNTL           (TIPB_PRIVATE_CNTL_BASE + 0x8)
-/*
- * ----------------------------------------------------------------------------
- * MPUI interface
- * ----------------------------------------------------------------------------
- */
-#define MPUI_BASE                       (0xfffec900)
-#define MPUI_CTRL                       (MPUI_BASE + 0x0)
-#define MPUI_DEBUG_ADDR                 (MPUI_BASE + 0x4)
-#define MPUI_DEBUG_DATA                 (MPUI_BASE + 0x8)
-#define MPUI_DEBUG_FLAG                 (MPUI_BASE + 0xc)
-#define MPUI_STATUS_REG                 (MPUI_BASE + 0x10)
-#define MPUI_DSP_STATUS                 (MPUI_BASE + 0x14)
-#define MPUI_DSP_BOOT_CONFIG            (MPUI_BASE + 0x18)
-#define MPUI_DSP_API_CONFIG             (MPUI_BASE + 0x1c)
-/*
- * ----------------------------------------------------------------------------
- * LED Pulse Generator
- * ----------------------------------------------------------------------------
- */
-#define OMAP_LPG1_BASE                  0xfffbd000
-#define OMAP_LPG2_BASE                  0xfffbd800
-#define OMAP_LPG1_LCR                   (OMAP_LPG1_BASE + 0x00)
-#define OMAP_LPG1_PMR                   (OMAP_LPG1_BASE + 0x04)
-#define OMAP_LPG2_LCR                   (OMAP_LPG2_BASE + 0x00)
-#define OMAP_LPG2_PMR                   (OMAP_LPG2_BASE + 0x04)
-/*
- * ----------------------------------------------------------------------------
- * Pulse-Width Light
- * ----------------------------------------------------------------------------
- */
-#define OMAP_PWL_BASE                   0xfffb5800
-#define OMAP_PWL_ENABLE                 (OMAP_PWL_BASE + 0x00)
-#define OMAP_PWL_CLK_ENABLE             (OMAP_PWL_BASE + 0x04)
-/*
- * ---------------------------------------------------------------------------
- * Processor specific defines
- * ---------------------------------------------------------------------------
- */
-#include <plat/omap7xx.h>
-#include <plat/omap1510.h>
-#include <plat/omap16xx.h>
-#include <plat/omap24xx.h>
-#include <plat/omap34xx.h>
-#include <plat/omap44xx.h>
-#include <plat/ti81xx.h>
-#include <plat/am33xx.h>
-#include <plat/omap54xx.h>
-#endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 88be3e628b33..68b5f0362f35 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -103,6 +103,19 @@ struct iommu_functions {
        ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len);
 };
+/**
+ * struct omap_mmu_dev_attr - OMAP mmu device attributes for omap_hwmod
+ * @da_start:           device address where the va space starts.
+ * @da_end:             device address where the va space ends.
+ * @nr_tlb_entries:     number of entries supported by the translation
+ *                      look-aside buffer (TLB).
+ */
+struct omap_mmu_dev_attr {
+        u32 da_start;
+        u32 da_end;
+        int nr_tlb_entries;
+};
 struct iommu_platform_data {
        const char *name;
        const char *clk_name;
@@ -126,6 +139,7 @@ struct omap_iommu_arch_data {
        struct omap_iommu *iommu_dev;
 };
+#ifdef CONFIG_IOMMU_API
 /**
 * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
 * @dev: iommu client device
@@ -136,6 +150,7 @@ static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
        return arch_data->iommu_dev;
 }
+#endif
 /* IOMMU errors */
 #define OMAP_IOMMU_ERR_TLB_MISS         (1 << 0)
diff --git a/arch/arm/plat-omap/include/plat/irqs-44xx.h b/arch/arm/plat-omap/include/plat/irqs-44xx.h
deleted file mode 100644
index 518322c80116..000000000000
--- a/arch/arm/plat-omap/include/plat/irqs-44xx.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * OMAP4 Interrupt lines definitions
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Santosh Shilimkar (santosh.shilimkar@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
-#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
-/* OMAP44XX IRQs numbers definitions */
-#define OMAP44XX_IRQ_LOCALTIMER                 29
-#define OMAP44XX_IRQ_LOCALWDT                   30
-#define OMAP44XX_IRQ_GIC_START                  32
-#define OMAP44XX_IRQ_PL310                      (0 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CTI0                       (1 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CTI1                       (2 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ELM                        (4 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SYS_1N                     (7 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SECURITY_EVENTS            (8 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_L3_DBG                     (9 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_L3_APP                     (10 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_PRCM                       (11 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_0                     (12 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_1                     (13 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_2                     (14 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_3                     (15 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP4                     (16 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP1                     (17 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_MCU                     (18 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_CORE                    (19 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPMC                       (20 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GFX                        (21 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP2                     (22 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP3                     (23 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ISS_5                      (24 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DISPC                  (25 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MAIL_U0                    (26 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_C2C_SSCM_0                 (27 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_TESLA_MMU                  (28 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO1                      (29 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO2                      (30 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO3                      (31 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO4                      (32 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO5                      (33 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO6                      (34 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_USIM                       (35 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_WDT3                       (36 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT1                       (37 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT2                       (38 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT3                       (39 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT4                       (40 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT5                       (41 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT6                       (42 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT7                       (43 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT8                       (44 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT9                       (45 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT10                      (46 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT11                      (47 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI4                       (48 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SHA1_S                     (49 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FPKA_SINTREQUEST_S         (50 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SHA1_P                     (51 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_RNG                        (52 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DSI1                   (53 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C1                       (56 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C2                       (57 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HDQ                        (58 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC5                       (59 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C3                       (61 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C4                       (62 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES2_S                     (63 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES2_P                     (64 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI1                       (65 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI2                       (66 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_P1                     (67 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_P2                     (68 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FDIF_3                     (69 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART4                      (70 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_DMA                    (71 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART1                      (72 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART2                      (73 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART3                      (74 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_PBIAS                      (75 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_OHCI                       (76 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EHCI                       (77 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_TLL                        (78 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES1_S                     (79 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_WDT2                       (80 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DES_S                      (81 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DES_P                      (82 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC1                       (83 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DSI2                   (84 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES1_P                     (85 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC2                       (86 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MPU_ICR                    (87 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_C2C_SSCM_1                 (88 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FSUSB                      (89 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FSUSB_SMI                  (90 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI3                       (91 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HS_USB_MC_N                (92 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HS_USB_DMA_N               (93 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC3                       (94 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT12                      (95 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC4                       (96 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SLIMBUS1                   (97 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SLIMBUS2                   (98 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ABE                        (99 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DUCATI_MMU                 (100 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_HDMI                   (101 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_IVA                     (102 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1     (103 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0     (104 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0      (107 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCASP1_AR                  (108 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCASP1_AX                  (109 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EMIF4_1                    (110 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EMIF4_2                    (111 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCPDM                      (112 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DMM                        (113 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DMIC                       (114 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_0                     (115 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_1                     (116 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_2                     (117 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_3                     (118 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SYS_2N                     (119 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_KBD_CTL                    (120 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UNIPRO1                    (124 + OMAP44XX_IRQ_GIC_START)
-#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
deleted file mode 100644
index 37bbbbb981b2..000000000000
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/irqs.h
- *
- *  Copyright (C) Greg Lonnon 2001
- *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
- *       are different.
- */
-#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
-#define __ASM_ARCH_OMAP15XX_IRQS_H
-/* All OMAP4 specific defines are moved to irqs-44xx.h */
-#include "irqs-44xx.h"
-/*
- * IRQ numbers for interrupt handler 1
- *
- * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
- *
- */
-#define INT_CAMERA              1
-#define INT_FIQ                 3
-#define INT_RTDX                6
-#define INT_DSP_MMU_ABORT       7
-#define INT_HOST                8
-#define INT_ABORT               9
-#define INT_BRIDGE_PRIV         13
-#define INT_GPIO_BANK1          14
-#define INT_UART3               15
-#define INT_TIMER3              16
-#define INT_DMA_CH0_6           19
-#define INT_DMA_CH1_7           20
-#define INT_DMA_CH2_8           21
-#define INT_DMA_CH3             22
-#define INT_DMA_CH4             23
-#define INT_DMA_CH5             24
-#define INT_DMA_LCD             25
-#define INT_TIMER1              26
-#define INT_WD_TIMER            27
-#define INT_BRIDGE_PUB          28
-#define INT_TIMER2              30
-#define INT_LCD_CTRL            31
-/*
- * OMAP-1510 specific IRQ numbers for interrupt handler 1
- */
-#define INT_1510_IH2_IRQ        0
-#define INT_1510_RES2           2
-#define INT_1510_SPI_TX         4
-#define INT_1510_SPI_RX         5
-#define INT_1510_DSP_MAILBOX1   10
-#define INT_1510_DSP_MAILBOX2   11
-#define INT_1510_RES12          12
-#define INT_1510_LB_MMU         17
-#define INT_1510_RES18          18
-#define INT_1510_LOCAL_BUS      29
-/*
- * OMAP-1610 specific IRQ numbers for interrupt handler 1
- */
-#define INT_1610_IH2_IRQ        INT_1510_IH2_IRQ
-#define INT_1610_IH2_FIQ        2
-#define INT_1610_McBSP2_TX      4
-#define INT_1610_McBSP2_RX      5
-#define INT_1610_DSP_MAILBOX1   10
-#define INT_1610_DSP_MAILBOX2   11
-#define INT_1610_LCD_LINE       12
-#define INT_1610_GPTIMER1       17
-#define INT_1610_GPTIMER2       18
-#define INT_1610_SSR_FIFO_0     29
-/*
- * OMAP-7xx specific IRQ numbers for interrupt handler 1
- */
-#define INT_7XX_IH2_FIQ         0
-#define INT_7XX_IH2_IRQ         1
-#define INT_7XX_USB_NON_ISO     2
-#define INT_7XX_USB_ISO         3
-#define INT_7XX_ICR             4
-#define INT_7XX_EAC             5
-#define INT_7XX_GPIO_BANK1      6
-#define INT_7XX_GPIO_BANK2      7
-#define INT_7XX_GPIO_BANK3      8
-#define INT_7XX_McBSP2TX        10
-#define INT_7XX_McBSP2RX        11
-#define INT_7XX_McBSP2RX_OVF    12
-#define INT_7XX_LCD_LINE        14
-#define INT_7XX_GSM_PROTECT     15
-#define INT_7XX_TIMER3          16
-#define INT_7XX_GPIO_BANK5      17
-#define INT_7XX_GPIO_BANK6      18
-#define INT_7XX_SPGIO_WR        29
-/*
- * IRQ numbers for interrupt handler 2
- *
- * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
- */
-#define IH2_BASE                32
-#define INT_KEYBOARD            (1 + IH2_BASE)
-#define INT_uWireTX             (2 + IH2_BASE)
-#define INT_uWireRX             (3 + IH2_BASE)
-#define INT_I2C                 (4 + IH2_BASE)
-#define INT_MPUIO               (5 + IH2_BASE)
-#define INT_USB_HHC_1           (6 + IH2_BASE)
-#define INT_McBSP3TX            (10 + IH2_BASE)
-#define INT_McBSP3RX            (11 + IH2_BASE)
-#define INT_McBSP1TX            (12 + IH2_BASE)
-#define INT_McBSP1RX            (13 + IH2_BASE)
-#define INT_UART1               (14 + IH2_BASE)
-#define INT_UART2               (15 + IH2_BASE)
-#define INT_BT_MCSI1TX          (16 + IH2_BASE)
-#define INT_BT_MCSI1RX          (17 + IH2_BASE)
-#define INT_SOSSI_MATCH         (19 + IH2_BASE)
-#define INT_USB_W2FC            (20 + IH2_BASE)
-#define INT_1WIRE               (21 + IH2_BASE)
-#define INT_OS_TIMER            (22 + IH2_BASE)
-#define INT_MMC                 (23 + IH2_BASE)
-#define INT_GAUGE_32K           (24 + IH2_BASE)
-#define INT_RTC_TIMER           (25 + IH2_BASE)
-#define INT_RTC_ALARM           (26 + IH2_BASE)
-#define INT_MEM_STICK           (27 + IH2_BASE)
-/*
- * OMAP-1510 specific IRQ numbers for interrupt handler 2
- */
-#define INT_1510_DSP_MMU        (28 + IH2_BASE)
-#define INT_1510_COM_SPI_RO     (31 + IH2_BASE)
-/*
- * OMAP-1610 specific IRQ numbers for interrupt handler 2
- */
-#define INT_1610_FAC            (0 + IH2_BASE)
-#define INT_1610_USB_HHC_2      (7 + IH2_BASE)
-#define INT_1610_USB_OTG        (8 + IH2_BASE)
-#define INT_1610_SoSSI          (9 + IH2_BASE)
-#define INT_1610_SoSSI_MATCH    (19 + IH2_BASE)
-#define INT_1610_DSP_MMU        (28 + IH2_BASE)
-#define INT_1610_McBSP2RX_OF    (31 + IH2_BASE)
-#define INT_1610_STI            (32 + IH2_BASE)
-#define INT_1610_STI_WAKEUP     (33 + IH2_BASE)
-#define INT_1610_GPTIMER3       (34 + IH2_BASE)
-#define INT_1610_GPTIMER4       (35 + IH2_BASE)
-#define INT_1610_GPTIMER5       (36 + IH2_BASE)
-#define INT_1610_GPTIMER6       (37 + IH2_BASE)
-#define INT_1610_GPTIMER7       (38 + IH2_BASE)
-#define INT_1610_GPTIMER8       (39 + IH2_BASE)
-#define INT_1610_GPIO_BANK2     (40 + IH2_BASE)
-#define INT_1610_GPIO_BANK3     (41 + IH2_BASE)
-#define INT_1610_MMC2           (42 + IH2_BASE)
-#define INT_1610_CF             (43 + IH2_BASE)
-#define INT_1610_WAKE_UP_REQ    (46 + IH2_BASE)
-#define INT_1610_GPIO_BANK4     (48 + IH2_BASE)
-#define INT_1610_SPI            (49 + IH2_BASE)
-#define INT_1610_DMA_CH6        (53 + IH2_BASE)
-#define INT_1610_DMA_CH7        (54 + IH2_BASE)
-#define INT_1610_DMA_CH8        (55 + IH2_BASE)
-#define INT_1610_DMA_CH9        (56 + IH2_BASE)
-#define INT_1610_DMA_CH10       (57 + IH2_BASE)
-#define INT_1610_DMA_CH11       (58 + IH2_BASE)
-#define INT_1610_DMA_CH12       (59 + IH2_BASE)
-#define INT_1610_DMA_CH13       (60 + IH2_BASE)
-#define INT_1610_DMA_CH14       (61 + IH2_BASE)
-#define INT_1610_DMA_CH15       (62 + IH2_BASE)
-#define INT_1610_NAND           (63 + IH2_BASE)
-#define INT_1610_SHA1MD5        (91 + IH2_BASE)
-/*
- * OMAP-7xx specific IRQ numbers for interrupt handler 2
- */
-#define INT_7XX_HW_ERRORS       (0 + IH2_BASE)
-#define INT_7XX_NFIQ_PWR_FAIL   (1 + IH2_BASE)
-#define INT_7XX_CFCD            (2 + IH2_BASE)
-#define INT_7XX_CFIREQ          (3 + IH2_BASE)
-#define INT_7XX_I2C             (4 + IH2_BASE)
-#define INT_7XX_PCC             (5 + IH2_BASE)
-#define INT_7XX_MPU_EXT_NIRQ    (6 + IH2_BASE)
-#define INT_7XX_SPI_100K_1      (7 + IH2_BASE)
-#define INT_7XX_SYREN_SPI       (8 + IH2_BASE)
-#define INT_7XX_VLYNQ           (9 + IH2_BASE)
-#define INT_7XX_GPIO_BANK4      (10 + IH2_BASE)
-#define INT_7XX_McBSP1TX        (11 + IH2_BASE)
-#define INT_7XX_McBSP1RX        (12 + IH2_BASE)
-#define INT_7XX_McBSP1RX_OF     (13 + IH2_BASE)
-#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
-#define INT_7XX_UART_MODEM_1    (15 + IH2_BASE)
-#define INT_7XX_MCSI            (16 + IH2_BASE)
-#define INT_7XX_uWireTX         (17 + IH2_BASE)
-#define INT_7XX_uWireRX         (18 + IH2_BASE)
-#define INT_7XX_SMC_CD          (19 + IH2_BASE)
-#define INT_7XX_SMC_IREQ        (20 + IH2_BASE)
-#define INT_7XX_HDQ_1WIRE       (21 + IH2_BASE)
-#define INT_7XX_TIMER32K        (22 + IH2_BASE)
-#define INT_7XX_MMC_SDIO        (23 + IH2_BASE)
-#define INT_7XX_UPLD            (24 + IH2_BASE)
-#define INT_7XX_USB_HHC_1       (27 + IH2_BASE)
-#define INT_7XX_USB_HHC_2       (28 + IH2_BASE)
-#define INT_7XX_USB_GENI        (29 + IH2_BASE)
-#define INT_7XX_USB_OTG         (30 + IH2_BASE)
-#define INT_7XX_CAMERA_IF       (31 + IH2_BASE)
-#define INT_7XX_RNG             (32 + IH2_BASE)
-#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
-#define INT_7XX_DBB_RF_EN       (34 + IH2_BASE)
-#define INT_7XX_MPUIO_KEYPAD    (35 + IH2_BASE)
-#define INT_7XX_SHA1_MD5        (36 + IH2_BASE)
-#define INT_7XX_SPI_100K_2      (37 + IH2_BASE)
-#define INT_7XX_RNG_IDLE        (38 + IH2_BASE)
-#define INT_7XX_MPUIO           (39 + IH2_BASE)
-#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
-#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
-#define INT_7XX_LLPC_OE_RISING  (42 + IH2_BASE)
-#define INT_7XX_LLPC_VSYNC      (43 + IH2_BASE)
-#define INT_7XX_WAKE_UP_REQ     (46 + IH2_BASE)
-#define INT_7XX_DMA_CH6         (53 + IH2_BASE)
-#define INT_7XX_DMA_CH7         (54 + IH2_BASE)
-#define INT_7XX_DMA_CH8         (55 + IH2_BASE)
-#define INT_7XX_DMA_CH9         (56 + IH2_BASE)
-#define INT_7XX_DMA_CH10        (57 + IH2_BASE)
-#define INT_7XX_DMA_CH11        (58 + IH2_BASE)
-#define INT_7XX_DMA_CH12        (59 + IH2_BASE)
-#define INT_7XX_DMA_CH13        (60 + IH2_BASE)
-#define INT_7XX_DMA_CH14        (61 + IH2_BASE)
-#define INT_7XX_DMA_CH15        (62 + IH2_BASE)
-#define INT_7XX_NAND            (63 + IH2_BASE)
-#define INT_24XX_SYS_NIRQ       7
-#define INT_24XX_SDMA_IRQ0      12
-#define INT_24XX_SDMA_IRQ1      13
-#define INT_24XX_SDMA_IRQ2      14
-#define INT_24XX_SDMA_IRQ3      15
-#define INT_24XX_CAM_IRQ        24
-#define INT_24XX_DSS_IRQ        25
-#define INT_24XX_MAIL_U0_MPU    26
-#define INT_24XX_DSP_UMA        27
-#define INT_24XX_DSP_MMU        28
-#define INT_24XX_GPIO_BANK1     29
-#define INT_24XX_GPIO_BANK2     30
-#define INT_24XX_GPIO_BANK3     31
-#define INT_24XX_GPIO_BANK4     32
-#define INT_24XX_GPIO_BANK5     33
-#define INT_24XX_MAIL_U3_MPU    34
-#define INT_24XX_GPTIMER1       37
-#define INT_24XX_GPTIMER2       38
-#define INT_24XX_GPTIMER3       39
-#define INT_24XX_GPTIMER4       40
-#define INT_24XX_GPTIMER5       41
-#define INT_24XX_GPTIMER6       42
-#define INT_24XX_GPTIMER7       43
-#define INT_24XX_GPTIMER8       44
-#define INT_24XX_GPTIMER9       45
-#define INT_24XX_GPTIMER10      46
-#define INT_24XX_GPTIMER11      47
-#define INT_24XX_GPTIMER12      48
-#define INT_24XX_SHA1MD5        51
-#define INT_24XX_MCBSP4_IRQ_TX  54
-#define INT_24XX_MCBSP4_IRQ_RX  55
-#define INT_24XX_I2C1_IRQ       56
-#define INT_24XX_I2C2_IRQ       57
-#define INT_24XX_HDQ_IRQ        58
-#define INT_24XX_MCBSP1_IRQ_TX  59
-#define INT_24XX_MCBSP1_IRQ_RX  60
-#define INT_24XX_MCBSP2_IRQ_TX  62
-#define INT_24XX_MCBSP2_IRQ_RX  63
-#define INT_24XX_SPI1_IRQ       65
-#define INT_24XX_SPI2_IRQ       66
-#define INT_24XX_UART1_IRQ      72
-#define INT_24XX_UART2_IRQ      73
-#define INT_24XX_UART3_IRQ      74
-#define INT_24XX_USB_IRQ_GEN    75
-#define INT_24XX_USB_IRQ_NISO   76
-#define INT_24XX_USB_IRQ_ISO    77
-#define INT_24XX_USB_IRQ_HGEN   78
-#define INT_24XX_USB_IRQ_HSOF   79
-#define INT_24XX_USB_IRQ_OTG    80
-#define INT_24XX_MCBSP5_IRQ_TX  81
-#define INT_24XX_MCBSP5_IRQ_RX  82
-#define INT_24XX_MMC_IRQ        83
-#define INT_24XX_MMC2_IRQ       86
-#define INT_24XX_MCBSP3_IRQ_TX  89
-#define INT_24XX_MCBSP3_IRQ_RX  90
-#define INT_24XX_SPI3_IRQ       91
-#define INT_243X_MCBSP2_IRQ     16
-#define INT_243X_MCBSP3_IRQ     17
-#define INT_243X_MCBSP4_IRQ     18
-#define INT_243X_MCBSP5_IRQ     19
-#define INT_243X_MCBSP1_IRQ     64
-#define INT_243X_HS_USB_MC      92
-#define INT_243X_HS_USB_DMA     93
-#define INT_243X_CARKIT_IRQ     94
-#define INT_34XX_BENCH_MPU_EMUL 3
-#define INT_34XX_ST_MCBSP2_IRQ  4
-#define INT_34XX_ST_MCBSP3_IRQ  5
-#define INT_34XX_SSM_ABORT_IRQ  6
-#define INT_34XX_SYS_NIRQ       7
-#define INT_34XX_D2D_FW_IRQ     8
-#define INT_34XX_L3_DBG_IRQ     9
-#define INT_34XX_L3_APP_IRQ     10
-#define INT_34XX_PRCM_MPU_IRQ   11
-#define INT_34XX_MCBSP1_IRQ     16
-#define INT_34XX_MCBSP2_IRQ     17
-#define INT_34XX_GPMC_IRQ       20
-#define INT_34XX_MCBSP3_IRQ     22
-#define INT_34XX_MCBSP4_IRQ     23
-#define INT_34XX_CAM_IRQ        24
-#define INT_34XX_MCBSP5_IRQ     27
-#define INT_34XX_GPIO_BANK1     29
-#define INT_34XX_GPIO_BANK2     30
-#define INT_34XX_GPIO_BANK3     31
-#define INT_34XX_GPIO_BANK4     32
-#define INT_34XX_GPIO_BANK5     33
-#define INT_34XX_GPIO_BANK6     34
-#define INT_34XX_USIM_IRQ       35
-#define INT_34XX_WDT3_IRQ       36
-#define INT_34XX_SPI4_IRQ       48
-#define INT_34XX_SHA1MD52_IRQ   49
-#define INT_34XX_FPKA_READY_IRQ 50
-#define INT_34XX_SHA1MD51_IRQ   51
-#define INT_34XX_RNG_IRQ        52
-#define INT_34XX_I2C3_IRQ       61
-#define INT_34XX_FPKA_ERROR_IRQ 64
-#define INT_34XX_PBIAS_IRQ      75
-#define INT_34XX_OHCI_IRQ       76
-#define INT_34XX_EHCI_IRQ       77
-#define INT_34XX_TLL_IRQ        78
-#define INT_34XX_PARTHASH_IRQ   79
-#define INT_34XX_MMC3_IRQ       94
-#define INT_34XX_GPT12_IRQ      95
-#define INT_36XX_UART4_IRQ      80
-#define INT_35XX_HECC0_IRQ              24
-#define INT_35XX_HECC1_IRQ              28
-#define INT_35XX_EMAC_C0_RXTHRESH_IRQ   67
-#define INT_35XX_EMAC_C0_RX_PULSE_IRQ   68
-#define INT_35XX_EMAC_C0_TX_PULSE_IRQ   69
-#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70
-#define INT_35XX_USBOTG_IRQ             71
-#define INT_35XX_UART4_IRQ              84
-#define INT_35XX_CCDC_VD0_IRQ           88
-#define INT_35XX_CCDC_VD1_IRQ           92
-#define INT_35XX_CCDC_VD2_IRQ           93
-/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
- * 16 MPUIO lines */
-#define OMAP_MAX_GPIO_LINES     192
-#define IH_GPIO_BASE            (128 + IH2_BASE)
-#define IH_MPUIO_BASE           (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
-#define OMAP_IRQ_END            (IH_MPUIO_BASE + 16)
-/* External FPGA handles interrupts on Innovator boards */
-#define OMAP_FPGA_IRQ_BASE      (OMAP_IRQ_END)
-#ifdef  CONFIG_MACH_OMAP_INNOVATOR
-#define OMAP_FPGA_NR_IRQS       24
-#else
-#define OMAP_FPGA_NR_IRQS       0
-#endif
-#define OMAP_FPGA_IRQ_END       (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
-/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
-#define TWL4030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
-#ifdef  CONFIG_TWL4030_CORE
-#define TWL4030_BASE_NR_IRQS    8
-#define TWL4030_PWR_NR_IRQS     8
-#else
-#define TWL4030_BASE_NR_IRQS    0
-#define TWL4030_PWR_NR_IRQS     0
-#endif
-#define TWL4030_IRQ_END         (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
-#define TWL4030_PWR_IRQ_BASE    TWL4030_IRQ_END
-#define TWL4030_PWR_IRQ_END     (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
-/* External TWL4030 gpio interrupts are optional */
-#define TWL4030_GPIO_IRQ_BASE   TWL4030_PWR_IRQ_END
-#ifdef  CONFIG_GPIO_TWL4030
-#define TWL4030_GPIO_NR_IRQS    18
-#else
-#define TWL4030_GPIO_NR_IRQS    0
-#endif
-#define TWL4030_GPIO_IRQ_END    (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
-#define TWL6030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
-#ifdef CONFIG_TWL4030_CORE
-#define TWL6030_BASE_NR_IRQS    20
-#else
-#define TWL6030_BASE_NR_IRQS    0
-#endif
-#define TWL6030_IRQ_END         (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
-#define TWL6040_CODEC_IRQ_BASE  TWL6030_IRQ_END
-#ifdef CONFIG_TWL6040_CODEC
-#define TWL6040_CODEC_NR_IRQS   6
-#else
-#define TWL6040_CODEC_NR_IRQS   0
-#endif
-#define TWL6040_CODEC_IRQ_END   (TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS)
-/* Total number of interrupts depends on the enabled blocks above */
-#if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END)
-#define TWL_IRQ_END             TWL4030_GPIO_IRQ_END
-#else
-#define TWL_IRQ_END             TWL6040_CODEC_IRQ_END
-#endif
-/* GPMC related */
-#define OMAP_GPMC_IRQ_BASE      (TWL_IRQ_END)
-#define OMAP_GPMC_NR_IRQS       8
-#define OMAP_GPMC_IRQ_END       (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
-/* PRCM IRQ handler */
-#ifdef CONFIG_ARCH_OMAP2PLUS
-#define OMAP_PRCM_IRQ_BASE      (OMAP_GPMC_IRQ_END)
-#define OMAP_PRCM_NR_IRQS       64
-#define OMAP_PRCM_IRQ_END       (OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
-#else
-#define OMAP_PRCM_IRQ_END       OMAP_GPMC_IRQ_END
-#endif
-#define NR_IRQS                 OMAP_PRCM_IRQ_END
-#define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
-#define INTCPS_NR_MIR_REGS      3
-#define INTCPS_NR_IRQS          96
-#include <mach/hardware.h>
-#ifdef CONFIG_FIQ
-#define FIQ_START               1024
-#endif
-#endif
diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
deleted file mode 100644
index a6b21eddb212..000000000000
--- a/arch/arm/plat-omap/include/plat/keypad.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/keypad.h
- *
- *  Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_ARCH_KEYPAD_H
-#define ASMARM_ARCH_KEYPAD_H
-#ifndef CONFIG_ARCH_OMAP1
-#warning Please update the board to use matrix-keypad driver
-#define omap_readw(reg)         0
-#define omap_writew(val, reg)   do {} while (0)
-#endif
-#include <linux/input/matrix_keypad.h>
-struct omap_kp_platform_data {
-        int rows;
-        int cols;
-        const struct matrix_keymap_data *keymap_data;
-        bool rep;
-        unsigned long delay;
-        bool dbounce;
-        /* specific to OMAP242x*/
-        unsigned int *row_gpios;
-        unsigned int *col_gpios;
-};
-/* Group (0..3) -- when multiple keys are pressed, only the
- * keys pressed in the same group are considered as pressed. This is
- * in order to workaround certain crappy HW designs that produce ghost
- * keypresses. Two free bits, not used by neither row/col nor keynum,
- * must be available for use as group bits. The below GROUP_SHIFT
- * macro definition is based on some prior knowledge of the
- * matrix_keypad defined KEY() macro internals.
- */
-#define GROUP_SHIFT     14
-#define GROUP_0         (0 << GROUP_SHIFT)
-#define GROUP_1         (1 << GROUP_SHIFT)
-#define GROUP_2         (2 << GROUP_SHIFT)
-#define GROUP_3         (3 << GROUP_SHIFT)
-#define GROUP_MASK      GROUP_3
-#if KEY_MAX & GROUP_MASK
-#error Group bits in conflict with keynum bits
-#endif
-#endif
diff --git a/arch/arm/plat-omap/include/plat/lcd_mipid.h b/arch/arm/plat-omap/include/plat/lcd_mipid.h
deleted file mode 100644
index 8e52c6572281..000000000000
--- a/arch/arm/plat-omap/include/plat/lcd_mipid.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef __LCD_MIPID_H
-#define __LCD_MIPID_H
-enum mipid_test_num {
-        MIPID_TEST_RGB_LINES,
-};
-enum mipid_test_result {
-        MIPID_TEST_SUCCESS,
-        MIPID_TEST_INVALID,
-        MIPID_TEST_FAILED,
-};
-#ifdef __KERNEL__
-struct mipid_platform_data {
-        int     nreset_gpio;
-        int     data_lines;
-        void    (*shutdown)(struct mipid_platform_data *pdata);
-        void    (*set_bklight_level)(struct mipid_platform_data *pdata,
-                                     int level);
-        int     (*get_bklight_level)(struct mipid_platform_data *pdata);
-        int     (*get_bklight_max)(struct mipid_platform_data *pdata);
-};
-#endif
-#endif
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
deleted file mode 100644
index 18814127809a..000000000000
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/mcbsp.h
- *
- * Defines for Multi-Channel Buffered Serial Port
- *
- * Copyright (C) 2002 RidgeRun, Inc.
- * Author: Steve Johnson
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#ifndef __ASM_ARCH_OMAP_MCBSP_H
-#define __ASM_ARCH_OMAP_MCBSP_H
-#include <linux/spinlock.h>
-#include <linux/clk.h>
-#define MCBSP_CONFIG_TYPE2      0x2
-#define MCBSP_CONFIG_TYPE3      0x3
-#define MCBSP_CONFIG_TYPE4      0x4
-/* Platform specific configuration */
-struct omap_mcbsp_ops {
-        void (*request)(unsigned int);
-        void (*free)(unsigned int);
-};
-struct omap_mcbsp_platform_data {
-        struct omap_mcbsp_ops *ops;
-        u16 buffer_size;
-        u8 reg_size;
-        u8 reg_step;
-        /* McBSP platform and instance specific features */
-        bool has_wakeup; /* Wakeup capability */
-        bool has_ccr; /* Transceiver has configuration control registers */
-        int (*enable_st_clock)(unsigned int, bool);
-        int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src);
-        int (*mux_signal)(struct device *dev, const char *signal, const char *src);
-};
-/**
- * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
- * @sidetone: name of the sidetone device
- */
-struct omap_mcbsp_dev_attr {
-        const char *sidetone;
-};
-#endif
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
deleted file mode 100644
index a357eb26bd25..000000000000
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef _OMAP2_MCSPI_H
-#define _OMAP2_MCSPI_H
-#define OMAP2_MCSPI_REV 0
-#define OMAP3_MCSPI_REV 1
-#define OMAP4_MCSPI_REV 2
-#define OMAP4_MCSPI_REG_OFFSET 0x100
-struct omap2_mcspi_platform_config {
-        unsigned short  num_cs;
-        unsigned int regs_offset;
-};
-struct omap2_mcspi_dev_attr {
-        unsigned short num_chipselect;
-};
-struct omap2_mcspi_device_config {
-        unsigned turbo_mode:1;
-};
-#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index eb3e4d555343..8b4e4f2da2f5 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -15,7 +15,6 @@
 #include <linux/device.h>
 #include <linux/mmc/host.h>
-#include <plat/board.h>
 #include <plat/omap_hwmod.h>
 #define OMAP15XX_NR_MMC         1
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
deleted file mode 100644
index 67fc5060183e..000000000000
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/nand.h
- *
- * Copyright (C) 2006 Micron Technology Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <plat/gpmc.h>
-#include <linux/mtd/partitions.h>
-enum nand_io {
-        NAND_OMAP_PREFETCH_POLLED = 0,  /* prefetch polled mode, default */
-        NAND_OMAP_POLLED,               /* polled mode, without prefetch */
-        NAND_OMAP_PREFETCH_DMA,         /* prefetch enabled sDMA mode */
-        NAND_OMAP_PREFETCH_IRQ          /* prefetch enabled irq mode */
-};
-struct omap_nand_platform_data {
-        int                     cs;
-        struct mtd_partition    *parts;
-        struct gpmc_timings     *gpmc_t;
-        int                     nr_parts;
-        bool                    dev_ready;
-        int                     gpmc_irq;
-        enum nand_io            xfer_type;
-        unsigned long           phys_base;
-        int                     devsize;
-        enum omap_ecc           ecc_opt;
-};
-/* minimum size for IO mapping */
-#define NAND_IO_SIZE    4
-#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-extern int gpmc_nand_init(struct omap_nand_platform_data *d);
-#else
-static inline int gpmc_nand_init(struct omap_nand_platform_data *d)
-{
-        return 0;
-}
-#endif
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 1a52725ffcf2..f4a4cd014795 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -18,11 +18,9 @@
 #define __OMAP_SERIAL_H__
 #include <linux/serial_core.h>
-#include <linux/platform_device.h>
+#include <linux/device.h>
 #include <linux/pm_qos.h>
-#include <plat/mux.h>
 #define DRIVER_NAME     "omap_uart"
 /*
@@ -42,10 +40,10 @@
 #define OMAP_UART_WER_MOD_WKUP  0X7F
 /* Enable XON/XOFF flow control on output */
-#define OMAP_UART_SW_TX         0x04
+#define OMAP_UART_SW_TX         0x8
 /* Enable XON/XOFF flow control on input */
-#define OMAP_UART_SW_RX         0x04
+#define OMAP_UART_SW_RX         0x2
 #define OMAP_UART_SYSC_RESET    0X07
 #define OMAP_UART_TCR_TRIG      0X0F
@@ -54,7 +52,7 @@
 #define OMAP_UART_DMA_CH_FREE   -1
-#define OMAP_MAX_HSUART_PORTS   4
+#define OMAP_MAX_HSUART_PORTS   6
 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
@@ -69,11 +67,14 @@ struct omap_uart_port_info {
        unsigned int            dma_rx_timeout;
        unsigned int            autosuspend_timeout;
        unsigned int            dma_rx_poll_rate;
+        int                     DTR_gpio;
+        int                     DTR_inverted;
+        int                     DTR_present;
        int (*get_context_loss_count)(struct device *);
-        void (*set_forceidle)(struct platform_device *);
+        void (*set_forceidle)(struct device *);
-        void (*set_noidle)(struct platform_device *);
+        void (*set_noidle)(struct device *);
-        void (*enable_wakeup)(struct platform_device *, bool);
+        void (*enable_wakeup)(struct device *, bool);
 };
 struct uart_omap_dma {
@@ -102,39 +103,4 @@ struct uart_omap_dma {
        unsigned int            rx_timeout;
 };
-struct uart_omap_port {
-        struct uart_port        port;
-        struct uart_omap_dma    uart_dma;
-        struct platform_device  *pdev;
-        unsigned char           ier;
-        unsigned char           lcr;
-        unsigned char           mcr;
-        unsigned char           fcr;
-        unsigned char           efr;
-        unsigned char           dll;
-        unsigned char           dlh;
-        unsigned char           mdr1;
-        unsigned char           scr;
-        int                     use_dma;
-        /*
-         * Some bits in registers are cleared on a read, so they must
-         * be saved whenever the register is read but the bits will not
-         * be immediately processed.
-         */
-        unsigned int            lsr_break_flag;
-        unsigned char           msr_saved_flags;
-        char                    name[20];
-        unsigned long           port_activity;
-        u32                     context_loss_cnt;
-        u32                     errata;
-        u8                      wakeups_enabled;
-        struct pm_qos_request   pm_qos_request;
-        u32                     latency;
-        u32                     calc_latency;
-        struct work_struct      qos_work;
-};
 #endif /* __OMAP_SERIAL_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 4327b2c90c3d..106f50665804 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -60,6 +60,7 @@ extern struct dev_pm_domain omap_device_pm_domain;
 * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
 * @_state: one of OMAP_DEVICE_STATE_* (see above)
 * @flags: device flags
+ * @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h>
 *
 * Integrates omap_hwmod data into Linux platform_device.
 *
@@ -73,6 +74,7 @@ struct omap_device {
        struct omap_device_pm_latency   *pm_lats;
        u32                             dev_wakeup_lat;
        u32                             _dev_wakeup_lat_limit;
+        unsigned long                   _driver_status;
        u8                              pm_lats_cnt;
        s8                              pm_lat_level;
        u8                              hwmods_cnt;
@@ -118,6 +120,10 @@ int omap_device_get_context_loss_count(struct platform_device *pdev);
 /* Other */
+int omap_device_assert_hardreset(struct platform_device *pdev,
+                                 const char *name);
+int omap_device_deassert_hardreset(struct platform_device *pdev,
+                                 const char *name);
 int omap_device_idle_hwmods(struct omap_device *od);
 int omap_device_enable_hwmods(struct omap_device *od);
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 6132972aff37..b3349f7b1a2c 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -2,7 +2,7 @@
 * omap_hwmod macros, structures
 *
 * Copyright (C) 2009-2011 Nokia Corporation
- * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2012 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -384,21 +384,38 @@ struct omap_hwmod_omap2_prcm {
        u8 idlest_stdby_bit;
 };
+/*
+ * Possible values for struct omap_hwmod_omap4_prcm.flags
+ *
+ * HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT: Some IP blocks don't have a PRCM
+ *     module-level context loss register associated with them; this
+ *     flag bit should be set in those cases
+ */
+#define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT         (1 << 0)
 /**
 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
 * @clkctrl_reg: PRCM address of the clock control register
 * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
+ * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register
 * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM
 * @submodule_wkdep_bit: bit shift of the WKDEP range
+ * @flags: PRCM register capabilities for this IP block
+ *
+ * If @lostcontext_mask is not defined, context loss check code uses
+ * whole register without masking. @lostcontext_mask should only be
+ * defined in cases where @context_offs register is shared by two or
+ * more hwmods.
 */
 struct omap_hwmod_omap4_prcm {
        u16             clkctrl_offs;
        u16             rstctrl_offs;
        u16             rstst_offs;
        u16             context_offs;
+        u32             lostcontext_mask;
        u8              submodule_wkdep_bit;
        u8              modulemode;
+        u8              flags;
 };
@@ -591,9 +608,7 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
 int __init omap_hwmod_setup_one(const char *name);
 int omap_hwmod_enable(struct omap_hwmod *oh);
-int _omap_hwmod_enable(struct omap_hwmod *oh);
 int omap_hwmod_idle(struct omap_hwmod *oh);
-int _omap_hwmod_idle(struct omap_hwmod *oh);
 int omap_hwmod_shutdown(struct omap_hwmod *oh);
 int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
@@ -615,6 +630,7 @@ int omap_hwmod_softreset(struct omap_hwmod *oh);
 int omap_hwmod_count_resources(struct omap_hwmod *oh);
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
+int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res);
 int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
                                   const char *name, struct resource *res);
@@ -626,11 +642,6 @@ int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
 int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
                                 struct omap_hwmod *init_oh);
-int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
-int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
-int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
-int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
 int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
 int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
@@ -658,6 +669,7 @@ extern int omap2420_hwmod_init(void);
 extern int omap2430_hwmod_init(void);
 extern int omap3xxx_hwmod_init(void);
 extern int omap44xx_hwmod_init(void);
+extern int am33xx_hwmod_init(void);
 extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
deleted file mode 100644
index 2858667d2e4f..000000000000
--- a/arch/arm/plat-omap/include/plat/onenand.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/onenand.h
- *
- * Copyright (C) 2006 Nokia Corporation
- * Author: Juha Yrjola
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#define ONENAND_SYNC_READ       (1 << 0)
-#define ONENAND_SYNC_READWRITE  (1 << 1)
-struct onenand_freq_info {
-        u16                     maf_id;
-        u16                     dev_id;
-        u16                     ver_id;
-};
-struct omap_onenand_platform_data {
-        int                     cs;
-        int                     gpio_irq;
-        struct mtd_partition    *parts;
-        int                     nr_parts;
-        int                     (*onenand_setup)(void __iomem *, int *freq_ptr);
-        int             (*get_freq)(const struct onenand_freq_info *freq_info,
-                                    bool *clk_dep);
-        int                     dma_channel;
-        u8                      flags;
-        u8                      regulator_can_sleep;
-        u8                      skip_initial_unlocking;
-};
-#define ONENAND_MAX_PARTITIONS 8
-#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
-        defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
-extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
-#else
-#define board_onenand_data      NULL
-static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
-{
-}
-#endif
diff --git a/arch/arm/plat-omap/include/plat/param.h b/arch/arm/plat-omap/include/plat/param.h
deleted file mode 100644
index 1eb4dc326979..000000000000
--- a/arch/arm/plat-omap/include/plat/param.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/param.h
- *
- */
-#ifdef CONFIG_OMAP_32K_TIMER_HZ
-#define HZ      CONFIG_OMAP_32K_TIMER_HZ
-#endif
diff --git a/arch/arm/plat-omap/include/plat/remoteproc.h b/arch/arm/plat-omap/include/plat/remoteproc.h
deleted file mode 100644
index b10eac89e2e9..000000000000
--- a/arch/arm/plat-omap/include/plat/remoteproc.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Remote Processor - omap-specific bits
- *
- * Copyright (C) 2011 Texas Instruments, Inc.
- * Copyright (C) 2011 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef _PLAT_REMOTEPROC_H
-#define _PLAT_REMOTEPROC_H
-struct rproc_ops;
-struct platform_device;
-/*
- * struct omap_rproc_pdata - omap remoteproc's platform data
- * @name: the remoteproc's name
- * @oh_name: omap hwmod device
- * @oh_name_opt: optional, secondary omap hwmod device
- * @firmware: name of firmware file to load
- * @mbox_name: name of omap mailbox device to use with this rproc
- * @ops: start/stop rproc handlers
- * @device_enable: omap-specific handler for enabling a device
- * @device_shutdown: omap-specific handler for shutting down a device
- */
-struct omap_rproc_pdata {
-        const char *name;
-        const char *oh_name;
-        const char *oh_name_opt;
-        const char *firmware;
-        const char *mbox_name;
-        const struct rproc_ops *ops;
-        int (*device_enable) (struct platform_device *pdev);
-        int (*device_shutdown) (struct platform_device *pdev);
-};
-#if defined(CONFIG_OMAP_REMOTEPROC) || defined(CONFIG_OMAP_REMOTEPROC_MODULE)
-void __init omap_rproc_reserve_cma(void);
-#else
-void __init omap_rproc_reserve_cma(void)
-{
-}
-#endif
-#endif /* _PLAT_REMOTEPROC_H */
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 548a4c8d63df..87ee140fefaa 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -4,8 +4,8 @@
 #define __ASM_ARCH_OMAP_USB_H
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #include <linux/usb/musb.h>
-#include <plat/board.h>
 #define OMAP3_HS_USB_PORTS      3
@@ -64,6 +64,10 @@ struct usbhs_omap_platform_data {
        struct ehci_hcd_omap_platform_data      *ehci_data;
        struct ohci_hcd_omap_platform_data      *ohci_data;
 };
+struct usbtll_omap_platform_data {
+        enum usbhs_omap_port_mode               port_mode[OMAP3_HS_USB_PORTS];
+};
 /*-------------------------------------------------------------------------*/
 struct omap_musb_board_data {
@@ -82,6 +86,8 @@ enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
 extern void usb_musb_init(struct omap_musb_board_data *board_data);
 extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
+extern int omap_tll_enable(void);
+extern int omap_tll_disable(void);
 extern int omap4430_phy_power(struct device *dev, int ID, int on);
 extern int omap4430_phy_set_clk(struct device *dev, int on);
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
deleted file mode 100644
index 5be4d5def427..000000000000
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * OMAP Voltage Management Routines
- *
- * Copyright (C) 2011, Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ARCH_ARM_OMAP_VOLTAGE_H
-#define __ARCH_ARM_OMAP_VOLTAGE_H
-/**
- * struct omap_volt_data - Omap voltage specific data.
- * @voltage_nominal:    The possible voltage value in uV
- * @sr_efuse_offs:      The offset of the efuse register(from system
- *                      control module base address) from where to read
- *                      the n-target value for the smartreflex module.
- * @sr_errminlimit:     Error min limit value for smartreflex. This value
- *                      differs at differnet opp and thus is linked
- *                      with voltage.
- * @vp_errorgain:       Error gain value for the voltage processor. This
- *                      field also differs according to the voltage/opp.
- */
-struct omap_volt_data {
-        u32     volt_nominal;
-        u32     sr_efuse_offs;
-        u8      sr_errminlimit;
-        u8      vp_errgain;
-};
-struct voltagedomain;
-struct voltagedomain *voltdm_lookup(const char *name);
-int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
-unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
-struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
-                unsigned long volt);
-#endif
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 5e13c3884aa4..42377ef9ea3d 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -310,7 +310,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
                omap_mbox_disable_irq(mbox, IRQ_RX);
                free_irq(mbox->irq, mbox);
                tasklet_kill(&mbox->txq->tasklet);
-                flush_work_sync(&mbox->rxq->work);
+                flush_work(&mbox->rxq->work);
                mbox_queue_free(mbox->txq);
                mbox_queue_free(mbox->rxq);
        }
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
deleted file mode 100644
index cff8712122bb..000000000000
--- a/arch/arm/plat-omap/mux.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * linux/arch/arm/plat-omap/mux.c
- *
- * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
- *
- * Copyright (C) 2003 - 2008 Nokia Corporation
- *
- * Written by Tony Lindgren
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-#include <asm/system.h>
-#include <plat/cpu.h>
-#include <plat/mux.h>
-#ifdef CONFIG_OMAP_MUX
-static struct omap_mux_cfg *mux_cfg;
-int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
-{
-        if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
-                        || !arch_mux_cfg->cfg_reg) {
-                printk(KERN_ERR "Invalid pin table\n");
-                return -EINVAL;
-        }
-        mux_cfg = arch_mux_cfg;
-        return 0;
-}
-/*
- * Sets the Omap MUX and PULL_DWN registers based on the table
- */
-int __init_or_module omap_cfg_reg(const unsigned long index)
-{
-        struct pin_config *reg;
-        if (!cpu_class_is_omap1()) {
-                printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
-                                index);
-                WARN_ON(1);
-                return -EINVAL;
-        }
-        if (mux_cfg == NULL) {
-                printk(KERN_ERR "Pin mux table not initialized\n");
-                return -ENODEV;
-        }
-        if (index >= mux_cfg->size) {
-                printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
-                       index, mux_cfg->size);
-                dump_stack();
-                return -ENODEV;
-        }
-        reg = (struct pin_config *)&mux_cfg->pins[index];
-        if (!mux_cfg->cfg_reg)
-                return -ENODEV;
-        return mux_cfg->cfg_reg(reg);
-}
-EXPORT_SYMBOL(omap_cfg_reg);
-#else
-#define omap_mux_init() do {} while(0)
-#define omap_cfg_reg(x) do {} while(0)
-#endif  /* CONFIG_OMAP_MUX */
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index 5a97b4d98d41..9722f418ae1f 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -38,14 +38,14 @@ int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
        if (!dev || t < -1) {
                WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
                return -EINVAL;
-        };
+        }
        if (t == -1)
-                pr_debug("OMAP PM: remove max MPU wakeup latency constraint: "
+                pr_debug("OMAP PM: remove max MPU wakeup latency constraint: dev %s\n",
-                         "dev %s\n", dev_name(dev));
+                         dev_name(dev));
        else
-                pr_debug("OMAP PM: add max MPU wakeup latency constraint: "
+                pr_debug("OMAP PM: add max MPU wakeup latency constraint: dev %s, t = %ld usec\n",
-                         "dev %s, t = %ld usec\n", dev_name(dev), t);
+                         dev_name(dev), t);
        /*
         * For current Linux, this needs to map the MPU to a
@@ -67,14 +67,13 @@ int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
            agent_id != OCP_TARGET_AGENT)) {
                WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
                return -EINVAL;
-        };
+        }
        if (r == 0)
-                pr_debug("OMAP PM: remove min bus tput constraint: "
+                pr_debug("OMAP PM: remove min bus tput constraint: dev %s for agent_id %d\n",
-                         "dev %s for agent_id %d\n", dev_name(dev), agent_id);
+                         dev_name(dev), agent_id);
        else
-                pr_debug("OMAP PM: add min bus tput constraint: "
+                pr_debug("OMAP PM: add min bus tput constraint: dev %s for agent_id %d: rate %ld KiB\n",
-                         "dev %s for agent_id %d: rate %ld KiB\n",
                         dev_name(dev), agent_id, r);
        /*
@@ -94,14 +93,14 @@ int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
        if (!req_dev || !dev || t < -1) {
                WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
                return -EINVAL;
-        };
+        }
        if (t == -1)
-                pr_debug("OMAP PM: remove max device latency constraint: "
+                pr_debug("OMAP PM: remove max device latency constraint: dev %s\n",
-                         "dev %s\n", dev_name(dev));
+                         dev_name(dev));
        else
-                pr_debug("OMAP PM: add max device latency constraint: "
+                pr_debug("OMAP PM: add max device latency constraint: dev %s, t = %ld usec\n",
-                         "dev %s, t = %ld usec\n", dev_name(dev), t);
+                         dev_name(dev), t);
        /*
         * For current Linux, this needs to map the device to a
@@ -124,14 +123,14 @@ int omap_pm_set_max_sdma_lat(struct device *dev, long t)
        if (!dev || t < -1) {
                WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
                return -EINVAL;
-        };
+        }
        if (t == -1)
-                pr_debug("OMAP PM: remove max DMA latency constraint: "
+                pr_debug("OMAP PM: remove max DMA latency constraint: dev %s\n",
-                         "dev %s\n", dev_name(dev));
+                         dev_name(dev));
        else
-                pr_debug("OMAP PM: add max DMA latency constraint: "
+                pr_debug("OMAP PM: add max DMA latency constraint: dev %s, t = %ld usec\n",
-                         "dev %s, t = %ld usec\n", dev_name(dev), t);
+                         dev_name(dev), t);
        /*
         * For current Linux PM QOS params, this code should scan the
@@ -156,11 +155,11 @@ int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
        }
        if (r == 0)
-                pr_debug("OMAP PM: remove min clk rate constraint: "
+                pr_debug("OMAP PM: remove min clk rate constraint: dev %s\n",
-                         "dev %s\n", dev_name(dev));
+                         dev_name(dev));
        else
-                pr_debug("OMAP PM: add min clk rate constraint: "
+                pr_debug("OMAP PM: add min clk rate constraint: dev %s, rate = %ld Hz\n",
-                         "dev %s, rate = %ld Hz\n", dev_name(dev), r);
+                         dev_name(dev), r);
        /*
         * Code in a real implementation should keep track of these
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240bb82c..7a7d1f2a65e9 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -1,4 +1,3 @@
 /*
 * omap_device implementation
 *
@@ -153,21 +152,19 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
                act_lat = timespec_to_ns(&c);
                dev_dbg(&od->pdev->dev,
-                        "omap_device: pm_lat %d: activate: elapsed time "
+                        "omap_device: pm_lat %d: activate: elapsed time %llu nsec\n",
-                        "%llu nsec\n", od->pm_lat_level, act_lat);
+                        od->pm_lat_level, act_lat);
                if (act_lat > odpl->activate_lat) {
                        odpl->activate_lat_worst = act_lat;
                        if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
                                odpl->activate_lat = act_lat;
                                dev_dbg(&od->pdev->dev,
-                                        "new worst case activate latency "
+                                        "new worst case activate latency %d: %llu\n",
-                                        "%d: %llu\n",
                                        od->pm_lat_level, act_lat);
                        } else
                                dev_warn(&od->pdev->dev,
-                                         "activate latency %d "
+                                         "activate latency %d higher than expected. (%llu > %d)\n",
-                                         "higher than exptected. (%llu > %d)\n",
                                         od->pm_lat_level, act_lat,
                                         odpl->activate_lat);
                }
@@ -220,21 +217,19 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
                deact_lat = timespec_to_ns(&c);
                dev_dbg(&od->pdev->dev,
-                        "omap_device: pm_lat %d: deactivate: elapsed time "
+                        "omap_device: pm_lat %d: deactivate: elapsed time %llu nsec\n",
-                        "%llu nsec\n", od->pm_lat_level, deact_lat);
+                        od->pm_lat_level, deact_lat);
                if (deact_lat > odpl->deactivate_lat) {
                        odpl->deactivate_lat_worst = deact_lat;
                        if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
                                odpl->deactivate_lat = deact_lat;
                                dev_dbg(&od->pdev->dev,
-                                        "new worst case deactivate latency "
+                                        "new worst case deactivate latency %d: %llu\n",
-                                        "%d: %llu\n",
                                        od->pm_lat_level, deact_lat);
                        } else
                                dev_warn(&od->pdev->dev,
-                                         "deactivate latency %d "
+                                         "deactivate latency %d higher than expected. (%llu > %d)\n",
-                                         "higher than exptected. (%llu > %d)\n",
                                         od->pm_lat_level, deact_lat,
                                         odpl->deactivate_lat);
                }
@@ -266,10 +261,10 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
                return;
        }
-        r = omap_clk_get_by_name(clk_name);
+        r = clk_get(NULL, clk_name);
        if (IS_ERR(r)) {
                dev_err(&od->pdev->dev,
-                        "omap_clk_get_by_name for %s failed\n", clk_name);
+                        "clk_get for %s failed\n", clk_name);
                return;
        }
@@ -370,6 +365,14 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
                goto odbfd_exit1;
        }
+        /* Fix up missing resource names */
+        for (i = 0; i < pdev->num_resources; i++) {
+                struct resource *r = &pdev->resource[i];
+                if (r->name == NULL)
+                        r->name = dev_name(&pdev->dev);
+        }
        if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
                omap_device_disable_idle_on_suspend(pdev);
@@ -385,17 +388,21 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
                                      unsigned long event, void *dev)
 {
        struct platform_device *pdev = to_platform_device(dev);
+        struct omap_device *od;
        switch (event) {
-        case BUS_NOTIFY_ADD_DEVICE:
-                if (pdev->dev.of_node)
-                        omap_device_build_from_dt(pdev);
-                break;
        case BUS_NOTIFY_DEL_DEVICE:
                if (pdev->archdata.od)
                        omap_device_delete(pdev->archdata.od);
                break;
+        case BUS_NOTIFY_ADD_DEVICE:
+                if (pdev->dev.of_node)
+                        omap_device_build_from_dt(pdev);
+                /* fall through */
+        default:
+                od = to_omap_device(pdev);
+                if (od)
+                        od->_driver_status = event;
        }
        return NOTIFY_DONE;
@@ -449,8 +456,8 @@ static int omap_device_count_resources(struct omap_device *od)
        for (i = 0; i < od->hwmods_cnt; i++)
                c += omap_hwmod_count_resources(od->hwmods[i]);
-        pr_debug("omap_device: %s: counted %d total resources across %d "
+        pr_debug("omap_device: %s: counted %d total resources across %d hwmods\n",
-                 "hwmods\n", od->pdev->name, c, od->hwmods_cnt);
+                 od->pdev->name, c, od->hwmods_cnt);
        return c;
 }
@@ -486,6 +493,33 @@ static int omap_device_fill_resources(struct omap_device *od,
 }
 /**
+ * _od_fill_dma_resources - fill in array of struct resource with dma resources
+ * @od: struct omap_device *
+ * @res: pointer to an array of struct resource to be filled in
+ *
+ * Populate one or more empty struct resource pointed to by @res with
+ * the dma resource data for this omap_device @od.  Used by
+ * omap_device_alloc() after calling omap_device_count_resources().
+ *
+ * Ideally this function would not be needed at all.  If we have
+ * mechanism to get dma resources from DT.
+ *
+ * Returns 0.
+ */
+static int _od_fill_dma_resources(struct omap_device *od,
+                                      struct resource *res)
+{
+        int i, r;
+        for (i = 0; i < od->hwmods_cnt; i++) {
+                r = omap_hwmod_fill_dma_resources(od->hwmods[i], res);
+                res += r;
+        }
+        return 0;
+}
+/**
 * omap_device_alloc - allocate an omap_device
 * @pdev: platform_device that will be included in this omap_device
 * @oh: ptr to the single omap_hwmod that backs this omap_device
@@ -524,24 +558,44 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
        od->hwmods = hwmods;
        od->pdev = pdev;
+        res_count = omap_device_count_resources(od);
        /*
-         * HACK: Ideally the resources from DT should match, and hwmod
+         * DT Boot:
-         * should just add the missing ones. Since the name is not
+         *   OF framework will construct the resource structure (currently
-         * properly populated by DT, stick to hwmod resources only.
+         *   does for MEM & IRQ resource) and we should respect/use these
+         *   resources, killing hwmod dependency.
+         *   If pdev->num_resources > 0, we assume that MEM & IRQ resources
+         *   have been allocated by OF layer already (through DTB).
+         *
+         * Non-DT Boot:
+         *   Here, pdev->num_resources = 0, and we should get all the
+         *   resources from hwmod.
+         *
+         * TODO: Once DMA resource is available from OF layer, we should
+         *   kill filling any resources from hwmod.
         */
-        if (pdev->num_resources && pdev->resource)
+        if (res_count > pdev->num_resources) {
-                dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
+                /* Allocate resources memory to account for new resources */
-                        __func__, pdev->num_resources);
-        res_count = omap_device_count_resources(od);
-        if (res_count > 0) {
-                dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n",
-                        __func__, res_count);
                res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
                if (!res)
                        goto oda_exit3;
-                omap_device_fill_resources(od, res);
+                /*
+                 * If pdev->num_resources > 0, then assume that,
+                 * MEM and IRQ resources will only come from DT and only
+                 * fill DMA resource from hwmod layer.
+                 */
+                if (pdev->num_resources && pdev->resource) {
+                        dev_dbg(&pdev->dev, "%s(): resources already allocated %d\n",
+                                __func__, res_count);
+                        memcpy(res, pdev->resource,
+                               sizeof(struct resource) * pdev->num_resources);
+                        _od_fill_dma_resources(od, &res[pdev->num_resources]);
+                } else {
+                        dev_dbg(&pdev->dev, "%s(): using resources from hwmod %d\n",
+                                __func__, res_count);
+                        omap_device_fill_resources(od, res);
+                }
                ret = platform_device_add_resources(pdev, res, res_count);
                kfree(res);
@@ -671,7 +725,7 @@ struct platform_device __init *omap_device_build_ss(const char *pdev_name, int p
                dev_set_name(&pdev->dev, "%s", pdev->name);
        od = omap_device_alloc(pdev, ohs, oh_cnt, pm_lats, pm_lats_cnt);
-        if (!od)
+        if (IS_ERR(od))
                goto odbs_exit1;
        ret = platform_device_add_data(pdev, pdata, pdata_len);
@@ -752,6 +806,10 @@ static int _od_suspend_noirq(struct device *dev)
        struct omap_device *od = to_omap_device(pdev);
        int ret;
+        /* Don't attempt late suspend on a driver that is not bound */
+        if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER)
+                return 0;
        ret = pm_generic_suspend_noirq(dev);
        if (!ret && !pm_runtime_status_suspended(dev)) {
@@ -925,6 +983,61 @@ int omap_device_shutdown(struct platform_device *pdev)
 }
 /**
+ * omap_device_assert_hardreset - set a device's hardreset line
+ * @pdev: struct platform_device * to reset
+ * @name: const char * name of the reset line
+ *
+ * Set the hardreset line identified by @name on the IP blocks
+ * associated with the hwmods backing the platform_device @pdev.  All
+ * of the hwmods associated with @pdev must have the same hardreset
+ * line linked to them for this to work.  Passes along the return value
+ * of omap_hwmod_assert_hardreset() in the event of any failure, or
+ * returns 0 upon success.
+ */
+int omap_device_assert_hardreset(struct platform_device *pdev, const char *name)
+{
+        struct omap_device *od = to_omap_device(pdev);
+        int ret = 0;
+        int i;
+        for (i = 0; i < od->hwmods_cnt; i++) {
+                ret = omap_hwmod_assert_hardreset(od->hwmods[i], name);
+                if (ret)
+                        break;
+        }
+        return ret;
+}
+/**
+ * omap_device_deassert_hardreset - release a device's hardreset line
+ * @pdev: struct platform_device * to reset
+ * @name: const char * name of the reset line
+ *
+ * Release the hardreset line identified by @name on the IP blocks
+ * associated with the hwmods backing the platform_device @pdev.  All
+ * of the hwmods associated with @pdev must have the same hardreset
+ * line linked to them for this to work.  Passes along the return
+ * value of omap_hwmod_deassert_hardreset() in the event of any
+ * failure, or returns 0 upon success.
+ */
+int omap_device_deassert_hardreset(struct platform_device *pdev,
+                                   const char *name)
+{
+        struct omap_device *od = to_omap_device(pdev);
+        int ret = 0;
+        int i;
+        for (i = 0; i < od->hwmods_cnt; i++) {
+                ret = omap_hwmod_deassert_hardreset(od->hwmods[i], name);
+                if (ret)
+                        break;
+        }
+        return ret;
+}
+/**
 * omap_device_align_pm_lat - activate/deactivate device to match wakeup lat lim
 * @od: struct omap_device *
 *
@@ -1125,3 +1238,41 @@ static int __init omap_device_init(void)
        return 0;
 }
 core_initcall(omap_device_init);
+/**
+ * omap_device_late_idle - idle devices without drivers
+ * @dev: struct device * associated with omap_device
+ * @data: unused
+ *
+ * Check the driver bound status of this device, and idle it
+ * if there is no driver attached.
+ */
+static int __init omap_device_late_idle(struct device *dev, void *data)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct omap_device *od = to_omap_device(pdev);
+        if (!od)
+                return 0;
+        /*
+         * If omap_device state is enabled, but has no driver bound,
+         * idle it.
+         */
+        if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) {
+                if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
+                        dev_warn(dev, "%s: enabled but no driver.  Idling\n",
+                                 __func__);
+                        omap_device_idle(pdev);
+                }
+        }
+        return 0;
+}
+static int __init omap_device_late_init(void)
+{
+        bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
+        return 0;
+}
+late_initcall(omap_device_late_init);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 024f3b08db29..28acb383e7df 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -26,7 +26,6 @@
 #include <asm/mach/map.h>
 #include <plat/sram.h>
-#include <plat/board.h>
 #include <plat/cpu.h>
 #include "sram.h"
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index c20ce0f5ce33..a82cecb84948 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -1,10 +1,10 @@
 #
 # Makefile for the linux kernel.
 #
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
-obj-y   := irq.o pcie.o time.o common.o mpp.o addr-map.o
+obj-y                             += addr-map.o
-obj-m   :=
-obj-n   :=
-obj-    :=
-obj-$(CONFIG_GENERIC_GPIO) += gpio.o
+orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += $(orion-gpio-y)
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
index 367ca89ac403..a7b8060c293a 100644
--- a/arch/arm/plat-orion/addr-map.c
+++ b/arch/arm/plat-orion/addr-map.c
@@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
 static void __init __iomem *
 orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
 {
-        return (void __iomem *)(cfg->bridge_virt_base + (win << 4));
+        return cfg->bridge_virt_base + (win << 4);
 }
 /*
@@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
 * Setup MBUS dram target info.
 */
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-                                        const u32 ddr_window_cpu_base)
+                                        const void __iomem *ddr_window_cpu_base)
 {
-        void __iomem *addr;
        int i;
        int cs;
        orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
-        addr = (void __iomem *)ddr_window_cpu_base;
        for (i = 0, cs = 0; i < 4; i++) {
-                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
+                u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
-                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
+                u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
                /*
                 * Chip select enabled?
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index b8b747a9d360..b8a688cad4c2 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -19,8 +19,8 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/mv643xx_i2c.h>
 #include <net/dsa.h>
-#include <plat/mv_xor.h>
+#include <linux/platform_data/dma-mv_xor.h>
-#include <plat/ehci-orion.h>
+#include <linux/platform_data/usb-ehci-orion.h>
 #include <mach/bridge-regs.h>
 /* Create a clkdev entry for a given device/clk */
@@ -86,13 +86,13 @@ static void __init uart_complete(
        struct platform_device *orion_uart,
        struct plat_serial8250_port *data,
        struct resource *resources,
-        unsigned int membase,
+        void __iomem *membase,
        resource_size_t mapbase,
        unsigned int irq,
        struct clk *clk)
 {
        data->mapbase = mapbase;
-        data->membase = (void __iomem *)membase;
+        data->membase = membase;
        data->irq = irq;
        data->uartclk = uart_get_clk_rate(clk);
        orion_uart->dev.platform_data = data;
@@ -120,7 +120,7 @@ static struct platform_device orion_uart0 = {
        .id                     = PLAT8250_DEV_PLATFORM,
 };
-void __init orion_uart0_init(unsigned int membase,
+void __init orion_uart0_init(void __iomem *membase,
                             resource_size_t mapbase,
                             unsigned int irq,
                             struct clk *clk)
@@ -148,7 +148,7 @@ static struct platform_device orion_uart1 = {
        .id                     = PLAT8250_DEV_PLATFORM1,
 };
-void __init orion_uart1_init(unsigned int membase,
+void __init orion_uart1_init(void __iomem *membase,
                             resource_size_t mapbase,
                             unsigned int irq,
                             struct clk *clk)
@@ -176,7 +176,7 @@ static struct platform_device orion_uart2 = {
        .id                     = PLAT8250_DEV_PLATFORM2,
 };
-void __init orion_uart2_init(unsigned int membase,
+void __init orion_uart2_init(void __iomem *membase,
                             resource_size_t mapbase,
                             unsigned int irq,
                             struct clk *clk)
@@ -204,7 +204,7 @@ static struct platform_device orion_uart3 = {
        .id                     = 3,
 };
-void __init orion_uart3_init(unsigned int membase,
+void __init orion_uart3_init(void __iomem *membase,
                             resource_size_t mapbase,
                             unsigned int irq,
                             struct clk *clk)
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index dfda74fae6f2..c29ee7ea200b 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -23,7 +23,7 @@
 #include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
-#include <plat/gpio.h>
+#include <plat/orion-gpio.h>
 /*
 * GPIO unit register offsets.
diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
index fd556f77562c..ec63e4a627d0 100644
--- a/arch/arm/plat-orion/include/plat/addr-map.h
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
 struct orion_addr_map_cfg {
        const int num_wins;     /* Total number of windows */
        const int remappable_wins;
-        const u32 bridge_virt_base;
+        void __iomem *bridge_virt_base;
        /* If NULL, the default cpu_win_can_remap will be used, using
           the value in remappable_wins */
@@ -49,5 +49,5 @@ void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
                                const u8 attr, const int remap);
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-                                        const u32 ddr_window_cpu_base);
+                                        const void __iomem *ddr_window_cpu_base);
 #endif
diff --git a/arch/arm/plat-orion/include/plat/audio.h b/arch/arm/plat-orion/include/plat/audio.h
deleted file mode 100644
index d6a55bd2e578..000000000000
--- a/arch/arm/plat-orion/include/plat/audio.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __PLAT_AUDIO_H
-#define __PLAT_AUDIO_H
-struct kirkwood_asoc_platform_data {
-        int burst;
-};
-#endif
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index ae2377ef63e5..6bbc3fe5f58e 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -13,22 +13,22 @@
 struct dsa_platform_data;
-void __init orion_uart0_init(unsigned int membase,
+void __init orion_uart0_init(void __iomem *membase,
                             resource_size_t mapbase,
                             unsigned int irq,
                             struct clk *clk);
-void __init orion_uart1_init(unsigned int membase,
+void __init orion_uart1_init(void __iomem *membase,
                             resource_size_t mapbase,
                             unsigned int irq,
                             struct clk *clk);
-void __init orion_uart2_init(unsigned int membase,
+void __init orion_uart2_init(void __iomem *membase,
                             resource_size_t mapbase,
                             unsigned int irq,
                             struct clk *clk);
-void __init orion_uart3_init(unsigned int membase,
+void __init orion_uart3_init(void __iomem *membase,
                             resource_size_t mapbase,
                             unsigned int irq,
                             struct clk *clk);
diff --git a/arch/arm/plat-orion/include/plat/ehci-orion.h b/arch/arm/plat-orion/include/plat/ehci-orion.h
deleted file mode 100644
index 6fc78e430420..000000000000
--- a/arch/arm/plat-orion/include/plat/ehci-orion.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/plat-orion/include/plat/ehci-orion.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __PLAT_EHCI_ORION_H
-#define __PLAT_EHCI_ORION_H
-#include <linux/mbus.h>
-enum orion_ehci_phy_ver {
-        EHCI_PHY_ORION,
-        EHCI_PHY_DD,
-        EHCI_PHY_KW,
-        EHCI_PHY_NA,
-};
-struct orion_ehci_data {
-        enum orion_ehci_phy_ver phy_version;
-};
-#endif
diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h
index 723adce99f41..254552fee889 100644
--- a/arch/arm/plat-orion/include/plat/mpp.h
+++ b/arch/arm/plat-orion/include/plat/mpp.h
@@ -29,6 +29,6 @@
 #define MPP_OUTPUT_MASK         GENERIC_MPP(0, 0x0, 0, 1)
 void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
-                           unsigned int mpp_max, unsigned int dev_bus);
+                           unsigned int mpp_max, void __iomem *dev_bus);
 #endif
diff --git a/arch/arm/plat-orion/include/plat/mv_xor.h b/arch/arm/plat-orion/include/plat/mv_xor.h
deleted file mode 100644
index 2ba1f7d76eef..000000000000
--- a/arch/arm/plat-orion/include/plat/mv_xor.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/plat-orion/include/plat/mv_xor.h
- *
- * Marvell XOR platform device data definition file.
- */
-#ifndef __PLAT_MV_XOR_H
-#define __PLAT_MV_XOR_H
-#include <linux/dmaengine.h>
-#include <linux/mbus.h>
-#define MV_XOR_SHARED_NAME      "mv_xor_shared"
-#define MV_XOR_NAME             "mv_xor"
-struct mv_xor_platform_data {
-        struct platform_device          *shared;
-        int                             hw_id;
-        dma_cap_mask_t                  cap_mask;
-        size_t                          pool_size;
-};
-#endif
diff --git a/arch/arm/plat-orion/include/plat/mvsdio.h b/arch/arm/plat-orion/include/plat/mvsdio.h
deleted file mode 100644
index 1190efedcb94..000000000000
--- a/arch/arm/plat-orion/include/plat/mvsdio.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/plat-orion/include/plat/mvsdio.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_MVSDIO_H
-#define __MACH_MVSDIO_H
-#include <linux/mbus.h>
-struct mvsdio_platform_data {
-        unsigned int clock;
-        int gpio_card_detect;
-        int gpio_write_protect;
-};
-#endif
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/orion-gpio.h
index 81c6fc8a7b28..614dcac9dc52 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/orion-gpio.h
@@ -1,5 +1,5 @@
 /*
- * arch/arm/plat-orion/include/plat/gpio.h
+ * arch/arm/plat-orion/include/plat/orion-gpio.h
 *
 * Marvell Orion SoC GPIO handling.
 *
diff --git a/arch/arm/plat-orion/include/plat/orion_nand.h b/arch/arm/plat-orion/include/plat/orion_nand.h
deleted file mode 100644
index 9f3c180834d1..000000000000
--- a/arch/arm/plat-orion/include/plat/orion_nand.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/plat-orion/include/plat/orion_nand.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __PLAT_ORION_NAND_H
-#define __PLAT_ORION_NAND_H
-/*
- * Device bus NAND private data
- */
-struct orion_nand_data {
-        struct mtd_partition *parts;
-        int (*dev_ready)(struct mtd_info *mtd);
-        u32 nr_parts;
-        u8 ale;         /* address line number connected to ALE */
-        u8 cle;         /* address line number connected to CLE */
-        u8 width;       /* buswidth */
-        u8 chip_delay;
-};
-#endif
diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
index 4d5f1f6e18df..07527e417c62 100644
--- a/arch/arm/plat-orion/include/plat/time.h
+++ b/arch/arm/plat-orion/include/plat/time.h
@@ -11,9 +11,9 @@
 #ifndef __PLAT_TIME_H
 #define __PLAT_TIME_H
-void orion_time_set_base(u32 timer_base);
+void orion_time_set_base(void __iomem *timer_base);
-void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask,
+void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask,
                     unsigned int irq, unsigned int tclk);
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index d751964def4c..1867944415ca 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -16,7 +16,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <plat/irq.h>
-#include <plat/gpio.h>
+#include <plat/orion-gpio.h>
 void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
 {
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
index 3b1e17bd3d17..e686fe76a96b 100644
--- a/arch/arm/plat-orion/mpp.c
+++ b/arch/arm/plat-orion/mpp.c
@@ -14,18 +14,19 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <mach/hardware.h>
+#include <plat/orion-gpio.h>
 #include <plat/mpp.h>
 /* Address of the ith MPP control register */
-static __init unsigned long mpp_ctrl_addr(unsigned int i,
+static __init void __iomem *mpp_ctrl_addr(unsigned int i,
-                                          unsigned long dev_bus)
+                                          void __iomem *dev_bus)
 {
        return dev_bus + (i) * 4;
 }
 void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
-                           unsigned int mpp_max, unsigned int dev_bus)
+                           unsigned int mpp_max, void __iomem *dev_bus)
 {
        unsigned int mpp_nr_regs = (1 + mpp_max/8);
        u32 mpp_ctrl[mpp_nr_regs];
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 1ed8d1397fcf..0f4fa863dd55 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -180,13 +180,13 @@ static struct irqaction orion_timer_irq = {
 };
 void __init
-orion_time_set_base(u32 _timer_base)
+orion_time_set_base(void __iomem *_timer_base)
 {
-        timer_base = (void __iomem *)_timer_base;
+        timer_base = _timer_base;
 }
 void __init
-orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
+orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
                unsigned int irq, unsigned int tclk)
 {
        u32 u;
@@ -194,7 +194,7 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
        /*
         * Set SoC-specific data.
         */
-        bridge_base = (void __iomem *)_bridge_base;
+        bridge_base = _bridge_base;
        bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
        ticks_per_jiffy = (tclk + HZ/2) / HZ;
diff --git a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
deleted file mode 100644
index 5ce8d5e6ea51..000000000000
--- a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
+++ /dev/null
@@ -1,73 +0,0 @@
-#ifndef __ASM_ARCH_PXA27x_KEYPAD_H
-#define __ASM_ARCH_PXA27x_KEYPAD_H
-#include <linux/input.h>
-#include <linux/input/matrix_keypad.h>
-#define MAX_MATRIX_KEY_ROWS     (8)
-#define MAX_MATRIX_KEY_COLS     (8)
-#define MATRIX_ROW_SHIFT        (3)
-#define MAX_DIRECT_KEY_NUM      (8)
-/* pxa3xx keypad platform specific parameters
- *
- * NOTE:
- * 1. direct_key_num indicates the number of keys in the direct keypad
- *    _plus_ the number of rotary-encoder sensor inputs,  this can be
- *    left as 0 if only rotary encoders are enabled,  the driver will
- *    automatically calculate this
- *
- * 2. direct_key_map is the key code map for the direct keys, if rotary
- *    encoder(s) are enabled, direct key 0/1(2/3) will be ignored
- *
- * 3. rotary can be either interpreted as a relative input event (e.g.
- *    REL_WHEEL/REL_HWHEEL) or specific keys (e.g. UP/DOWN/LEFT/RIGHT)
- *
- * 4. matrix key and direct key will use the same debounce_interval by
- *    default, which should be sufficient in most cases
- *
- * pxa168 keypad platform specific parameter
- *
- * NOTE:
- * clear_wakeup_event callback is a workaround required to clear the
- * keypad interrupt. The keypad wake must be cleared in addition to
- * reading the MI/DI bits in the KPC register.
- */
-struct pxa27x_keypad_platform_data {
-        /* code map for the matrix keys */
-        unsigned int    matrix_key_rows;
-        unsigned int    matrix_key_cols;
-        unsigned int    *matrix_key_map;
-        int             matrix_key_map_size;
-        /* direct keys */
-        int             direct_key_num;
-        unsigned int    direct_key_map[MAX_DIRECT_KEY_NUM];
-        /* the key output may be low active */
-        int             direct_key_low_active;
-        /* give board a chance to choose the start direct key */
-        unsigned int    direct_key_mask;
-        /* rotary encoders 0 */
-        int             enable_rotary0;
-        int             rotary0_rel_code;
-        int             rotary0_up_key;
-        int             rotary0_down_key;
-        /* rotary encoders 1 */
-        int             enable_rotary1;
-        int             rotary1_rel_code;
-        int             rotary1_up_key;
-        int             rotary1_down_key;
-        /* key debounce interval */
-        unsigned int    debounce_interval;
-        /* clear wakeup event requirement for pxa168 */
-        void            (*clear_wakeup_event)(void);
-};
-extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
-#endif /* __ASM_ARCH_PXA27x_KEYPAD_H */
diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
deleted file mode 100644
index c42f39f20195..000000000000
--- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
+++ /dev/null
@@ -1,79 +0,0 @@
-#ifndef __ASM_ARCH_PXA3XX_NAND_H
-#define __ASM_ARCH_PXA3XX_NAND_H
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-struct pxa3xx_nand_timing {
-        unsigned int    tCH;  /* Enable signal hold time */
-        unsigned int    tCS;  /* Enable signal setup time */
-        unsigned int    tWH;  /* ND_nWE high duration */
-        unsigned int    tWP;  /* ND_nWE pulse time */
-        unsigned int    tRH;  /* ND_nRE high duration */
-        unsigned int    tRP;  /* ND_nRE pulse width */
-        unsigned int    tR;   /* ND_nWE high to ND_nRE low for read */
-        unsigned int    tWHR; /* ND_nWE high to ND_nRE low for status read */
-        unsigned int    tAR;  /* ND_ALE low to ND_nRE low delay */
-};
-struct pxa3xx_nand_cmdset {
-        uint16_t        read1;
-        uint16_t        read2;
-        uint16_t        program;
-        uint16_t        read_status;
-        uint16_t        read_id;
-        uint16_t        erase;
-        uint16_t        reset;
-        uint16_t        lock;
-        uint16_t        unlock;
-        uint16_t        lock_status;
-};
-struct pxa3xx_nand_flash {
-        char            *name;
-        uint32_t        chip_id;
-        unsigned int    page_per_block; /* Pages per block (PG_PER_BLK) */
-        unsigned int    page_size;      /* Page size in bytes (PAGE_SZ) */
-        unsigned int    flash_width;    /* Width of Flash memory (DWIDTH_M) */
-        unsigned int    dfc_width;      /* Width of flash controller(DWIDTH_C) */
-        unsigned int    num_blocks;     /* Number of physical blocks in Flash */
-        struct pxa3xx_nand_timing *timing;      /* NAND Flash timing */
-};
-/*
- * Current pxa3xx_nand controller has two chip select which
- * both be workable.
- *
- * Notice should be taken that:
- * When you want to use this feature, you should not enable the
- * keep configuration feature, for two chip select could be
- * attached with different nand chip. The different page size
- * and timing requirement make the keep configuration impossible.
- */
-/* The max num of chip select current support */
-#define NUM_CHIP_SELECT         (2)
-struct pxa3xx_nand_platform_data {
-        /* the data flash bus is shared between the Static Memory
-         * Controller and the Data Flash Controller,  the arbiter
-         * controls the ownership of the bus
-         */
-        int     enable_arbiter;
-        /* allow platform code to keep OBM/bootloader defined NFC config */
-        int     keep_config;
-        /* indicate how many chip selects will be used */
-        int     num_cs;
-        const struct mtd_partition              *parts[NUM_CHIP_SELECT];
-        unsigned int                            nr_parts[NUM_CHIP_SELECT];
-        const struct pxa3xx_nand_flash *        flash;
-        size_t                                  num_flash;
-};
-extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
-#endif /* __ASM_ARCH_PXA3XX_NAND_H */
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index d1116e2dfbea..012bbd0b8d81 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -119,7 +119,7 @@ void clk_disable(struct clk *clk)
 unsigned long clk_get_rate(struct clk *clk)
 {
-        if (IS_ERR(clk))
+        if (IS_ERR_OR_NULL(clk))
                return 0;
        if (clk->rate != 0)
@@ -136,7 +136,7 @@ unsigned long clk_get_rate(struct clk *clk)
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
-        if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
+        if (!IS_ERR_OR_NULL(clk) && clk->ops && clk->ops->round_rate)
                return (clk->ops->round_rate)(clk, rate);
        return rate;
@@ -147,7 +147,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
        unsigned long flags;
        int ret;
-        if (IS_ERR(clk))
+        if (IS_ERR_OR_NULL(clk))
                return -EINVAL;
        /* We do not default just do a clk->rate = rate as
@@ -177,7 +177,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
        unsigned long flags;
        int ret = 0;
-        if (IS_ERR(clk))
+        if (IS_ERR_OR_NULL(clk) || IS_ERR_OR_NULL(parent))
                return -EINVAL;
        spin_lock_irqsave(&clocks_lock, flags);
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index fc49f3dabd76..03f654d55eff 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -35,7 +35,6 @@
 #include <media/s5p_hdmi.h>
 #include <asm/irq.h>
-#include <asm/pmu.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -48,24 +47,25 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/adc.h>
-#include <plat/ata.h>
+#include <linux/platform_data/ata-samsung_cf.h>
-#include <plat/ehci.h>
+#include <linux/platform_data/usb-ehci-s5p.h>
 #include <plat/fb.h>
 #include <plat/fb-s3c2410.h>
-#include <plat/hwmon.h>
+#include <plat/hdmi.h>
-#include <plat/iic.h>
+#include <linux/platform_data/hwmon-s3c.h>
+#include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/keypad.h>
-#include <plat/mci.h>
+#include <linux/platform_data/mmc-s3cmci.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <plat/sdhci.h>
-#include <plat/ts.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/udc.h>
+#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <plat/usb-control.h>
+#include <linux/platform_data/usb-ohci-s3c2410.h>
 #include <plat/usb-phy.h>
 #include <plat/regs-iic.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-spi.h>
-#include <plat/s3c64xx-spi.h>
+#include <linux/platform_data/spi-s3c64xx.h>
 static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
@@ -763,7 +763,7 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
                               &s5p_device_i2c_hdmiphy);
 }
-struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
+static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
 void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
                                  struct i2c_board_info *mhl_info, int mhl_bus)
@@ -1132,7 +1132,7 @@ static struct resource s5p_pmu_resource[] = {
 static struct platform_device s5p_device_pmu = {
        .name           = "arm-pmu",
-        .id             = ARM_PMU_DEVICE_CPU,
+        .id             = -1,
        .num_resources  = ARRAY_SIZE(s5p_pmu_resource),
        .resource       = s5p_pmu_resource,
 };
@@ -1591,6 +1591,8 @@ struct platform_device s3c64xx_device_spi1 = {
 void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
                                                int num_cs)
 {
+        struct s3c64xx_spi_info pd;
        /* Reject invalid configuration */
        if (!num_cs || src_clk_nr < 0) {
                pr_err("%s: Invalid SPI configuration\n", __func__);
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index c38d75489240..d088afa034e8 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -91,7 +91,8 @@ static int samsung_dmadev_prepare(unsigned ch,
                break;
        case DMA_CYCLIC:
                desc = dmaengine_prep_dma_cyclic(chan, param->buf,
-                        param->len, param->period, param->direction);
+                        param->len, param->period, param->direction,
+                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
                break;
        default:
                dev_err(&chan->dev->device, "unsupported format\n");
diff --git a/arch/arm/plat-samsung/include/plat/ata.h b/arch/arm/plat-samsung/include/plat/ata.h
deleted file mode 100644
index 2a3855a8372a..000000000000
--- a/arch/arm/plat-samsung/include/plat/ata.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/ata.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Samsung CF-ATA platform_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_PLAT_ATA_H
-#define __ASM_PLAT_ATA_H __FILE__
-/**
- * struct s3c_ide_platdata - S3C IDE driver platform data.
- * @setup_gpio: Setup the external GPIO pins to the right state for data
- * transfer in true-ide mode.
- */
-struct s3c_ide_platdata {
-        void (*setup_gpio)(void);
-};
-/*
- * s3c_ide_set_platdata() - Setup the platform specifc data for IDE driver.
- * @pdata: Platform data for IDE driver.
- */
-extern void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata);
-/* architecture-specific IDE configuration */
-extern void s3c64xx_ide_setup_gpio(void);
-extern void s5pc100_ide_setup_gpio(void);
-extern void s5pv210_ide_setup_gpio(void);
-#endif /*__ASM_PLAT_ATA_H */
diff --git a/arch/arm/plat-samsung/include/plat/audio-simtec.h b/arch/arm/plat-samsung/include/plat/audio-simtec.h
deleted file mode 100644
index 376af5286a3e..000000000000
--- a/arch/arm/plat-samsung/include/plat/audio-simtec.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/audio-simtec.h
- *
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Simtec Audio support.
-*/
-/**
- * struct s3c24xx_audio_simtec_pdata - platform data for simtec audio
- * @use_mpllin: Select codec clock from MPLLin
- * @output_cdclk: Need to output CDCLK to the codec
- * @have_mic: Set if we have a MIC socket
- * @have_lout: Set if we have a LineOut socket
- * @amp_gpio: GPIO pin to enable the AMP
- * @amp_gain: Option GPIO to control AMP gain
- */
-struct s3c24xx_audio_simtec_pdata {
-        unsigned int    use_mpllin:1;
-        unsigned int    output_cdclk:1;
-        unsigned int    have_mic:1;
-        unsigned int    have_lout:1;
-        int             amp_gpio;
-        int             amp_gain[2];
-        void    (*startup)(void);
-};
diff --git a/arch/arm/plat-samsung/include/plat/audio.h b/arch/arm/plat-samsung/include/plat/audio.h
deleted file mode 100644
index aa9875f77c40..000000000000
--- a/arch/arm/plat-samsung/include/plat/audio.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/audio.h
- *
- * Copyright (c) 2009 Samsung Electronics Co. Ltd
- * Author: Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/* The machine init code calls s3c*_ac97_setup_gpio with
- * one of these defines in order to select appropriate bank
- * of GPIO for AC97 pins
- */
-#define S3C64XX_AC97_GPD  0
-#define S3C64XX_AC97_GPE  1
-extern void s3c64xx_ac97_setup_gpio(int);
-/*
- * The machine init code calls s5p*_spdif_setup_gpio with
- * one of these defines in order to select appropriate bank
- * of GPIO for S/PDIF pins
- */
-#define S5PC100_SPDIF_GPD  0
-#define S5PC100_SPDIF_GPG3 1
-extern void s5pc100_spdif_setup_gpio(int);
-struct samsung_i2s {
-/* If the Primary DAI has 5.1 Channels */
-#define QUIRK_PRI_6CHAN         (1 << 0)
-/* If the I2S block has a Stereo Overlay Channel */
-#define QUIRK_SEC_DAI           (1 << 1)
-/*
- * If the I2S block has no internal prescalar or MUX (I2SMOD[10] bit)
- * The Machine driver must provide suitably set clock to the I2S block.
- */
-#define QUIRK_NO_MUXPSR         (1 << 2)
-#define QUIRK_NEED_RSTCLR       (1 << 3)
-        /* Quirks of the I2S controller */
-        u32 quirks;
-        /*
-         * Array of clock names that can be used to generate I2S signals.
-         * Also corresponds to clocks of I2SMOD[10]
-         */
-        const char **src_clk;
-        dma_addr_t idma_addr;
-};
-/**
- * struct s3c_audio_pdata - common platform data for audio device drivers
- * @cfg_gpio: Callback function to setup mux'ed pins in I2S/PCM/AC97 mode
- */
-struct s3c_audio_pdata {
-        int (*cfg_gpio)(struct platform_device *);
-        union {
-                struct samsung_i2s i2s;
-        } type;
-};
diff --git a/arch/arm/plat-samsung/include/plat/ehci.h b/arch/arm/plat-samsung/include/plat/ehci.h
deleted file mode 100644
index 5f28cae18582..000000000000
--- a/arch/arm/plat-samsung/include/plat/ehci.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co.Ltd
- * Author: Joonyoung Shim <jy0922.shim@samsung.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef __PLAT_SAMSUNG_EHCI_H
-#define __PLAT_SAMSUNG_EHCI_H __FILE__
-struct s5p_ehci_platdata {
-        int (*phy_init)(struct platform_device *pdev, int type);
-        int (*phy_exit)(struct platform_device *pdev, int type);
-};
-extern void s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd);
-#endif /* __PLAT_SAMSUNG_EHCI_H */
diff --git a/arch/arm/plat-samsung/include/plat/gpio-fns.h b/arch/arm/plat-samsung/include/plat/gpio-fns.h
index bab139201761..d1ecef0e38e0 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-fns.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-fns.h
@@ -1,98 +1 @@
-/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
- *
- * Copyright (c) 2003-2009 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - hardware
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __MACH_GPIO_FNS_H
-#define __MACH_GPIO_FNS_H __FILE__
-/* These functions are in the to-be-removed category and it is strongly
- * encouraged not to use these in new code. They will be marked deprecated
- * very soon.
- *
- * Most of the functionality can be either replaced by the gpiocfg calls
- * for the s3c platform or by the generic GPIOlib API.
- *
- * As of 2.6.35-rc, these will be removed, with the few drivers using them
- * either replaced or given a wrapper until the calls can be removed.
-*/
 #include <plat/gpio-cfg.h>
-static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
-{
-        /* 1:1 mapping between cfgpin and setcfg calls at the moment */
-        s3c_gpio_cfgpin(pin, cfg);
-}
-/* external functions for GPIO support
- *
- * These allow various different clients to access the same GPIO
- * registers without conflicting. If your driver only owns the entire
- * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
-*/
-extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
-/* s3c2410_gpio_getirq
- *
- * turn the given pin number into the corresponding IRQ number
- *
- * returns:
- *      < 0 = no interrupt for this pin
- *      >=0 = interrupt number for the pin
-*/
-extern int s3c2410_gpio_getirq(unsigned int pin);
-/* s3c2410_gpio_irqfilter
- *
- * set the irq filtering on the given pin
- *
- * on = 0 => disable filtering
- *      1 => enable filtering
- *
- * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
- *          width of filter (0 through 63)
- *
- *
-*/
-extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
-                                  unsigned int config);
-/* s3c2410_gpio_pullup
- *
- * This call should be replaced with s3c_gpio_setpull().
- *
- * As a note, there is currently no distinction between pull-up and pull-down
- * in the s3c24xx series devices with only an on/off configuration.
- */
-/* s3c2410_gpio_pullup
- *
- * configure the pull-up control on the given pin
- *
- * to = 1 => disable the pull-up
- *      0 => enable the pull-up
- *
- * eg;
- *
- *   s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
- *   s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
-*/
-extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
-extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
-extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
-#endif /* __MACH_GPIO_FNS_H */
diff --git a/arch/arm/plat-samsung/include/plat/hwmon.h b/arch/arm/plat-samsung/include/plat/hwmon.h
deleted file mode 100644
index c167e4429bc7..000000000000
--- a/arch/arm/plat-samsung/include/plat/hwmon.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* linux/arch/arm/plat-s3c/include/plat/hwmon.h
- *
- * Copyright 2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C - HWMon interface for ADC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_ADC_HWMON_H
-#define __ASM_ARCH_ADC_HWMON_H __FILE__
-/**
- * s3c_hwmon_chcfg - channel configuration
- * @name: The name to give this channel.
- * @mult: Multiply the ADC value read by this.
- * @div: Divide the value from the ADC by this.
- *
- * The value read from the ADC is converted to a value that
- * hwmon expects (mV) by result = (value_read * @mult) / @div.
- */
-struct s3c_hwmon_chcfg {
-        const char      *name;
-        unsigned int    mult;
-        unsigned int    div;
-};
-/**
- * s3c_hwmon_pdata - HWMON platform data
- * @in: One configuration for each possible channel used.
- */
-struct s3c_hwmon_pdata {
-        struct s3c_hwmon_chcfg  *in[8];
-};
-/**
- * s3c_hwmon_set_platdata - Set platform data for S3C HWMON device
- * @pd: Platform data to register to device.
- *
- * Register the given platform data for use with the S3C HWMON device.
- * The call will copy the platform data, so the board definitions can
- * make the structure itself __initdata.
- */
-extern void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd);
-#endif /* __ASM_ARCH_ADC_HWMON_H */
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h
deleted file mode 100644
index 51d52e767a19..000000000000
--- a/arch/arm/plat-samsung/include/plat/iic.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* arch/arm/plat-s3c/include/plat/iic.h
- *
- * Copyright 2004-2009 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C - I2C Controller platform_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_IIC_H
-#define __ASM_ARCH_IIC_H __FILE__
-#define S3C_IICFLG_FILTER       (1<<0)  /* enable s3c2440 filter */
-/**
- *      struct s3c2410_platform_i2c - Platform data for s3c I2C.
- *      @bus_num: The bus number to use (if possible).
- *      @flags: Any flags for the I2C bus (E.g. S3C_IICFLK_FILTER).
- *      @slave_addr: The I2C address for the slave device (if enabled).
- *      @frequency: The desired frequency in Hz of the bus.  This is
- *                  guaranteed to not be exceeded.  If the caller does
- *                  not care, use zero and the driver will select a
- *                  useful default.
- *      @sda_delay: The delay (in ns) applied to SDA edges.
- *      @cfg_gpio: A callback to configure the pins for I2C operation.
- */
-struct s3c2410_platform_i2c {
-        int             bus_num;
-        unsigned int    flags;
-        unsigned int    slave_addr;
-        unsigned long   frequency;
-        unsigned int    sda_delay;
-        void    (*cfg_gpio)(struct platform_device *dev);
-};
-/**
- * s3c_i2c0_set_platdata - set platform data for i2c0 device
- * @i2c: The platform data to set, or NULL for default data.
- *
- * Register the given platform data for use with the i2c0 device. This
- * call copies the platform data, so the caller can use __initdata for
- * their copy.
- *
- * This call will set cfg_gpio if is null to the default platform
- * implementation.
- *
- * Any user of s3c_device_i2c0 should call this, even if it is with
- * NULL to ensure that the device is given the default platform data
- * as the driver will no longer carry defaults.
- */
-extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
-extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
-extern void s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *i2c);
-extern void s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *i2c);
-extern void s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *i2c);
-extern void s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *i2c);
-extern void s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *i2c);
-extern void s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *i2c);
-extern void s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *i2c);
-/* defined by architecture to configure gpio */
-extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
-extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
-extern void s3c_i2c2_cfg_gpio(struct platform_device *dev);
-extern void s3c_i2c3_cfg_gpio(struct platform_device *dev);
-extern void s3c_i2c4_cfg_gpio(struct platform_device *dev);
-extern void s3c_i2c5_cfg_gpio(struct platform_device *dev);
-extern void s3c_i2c6_cfg_gpio(struct platform_device *dev);
-extern void s3c_i2c7_cfg_gpio(struct platform_device *dev);
-extern struct s3c2410_platform_i2c default_i2c_data;
-#endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/mci.h b/arch/arm/plat-samsung/include/plat/mci.h
deleted file mode 100644
index c42d31711944..000000000000
--- a/arch/arm/plat-samsung/include/plat/mci.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#ifndef _ARCH_MCI_H
-#define _ARCH_MCI_H
-/**
- * struct s3c24xx_mci_pdata - sd/mmc controller platform data
- * @no_wprotect: Set this to indicate there is no write-protect switch.
- * @no_detect: Set this if there is no detect switch.
- * @wprotect_invert: Invert the default sense of the write protect switch.
- * @detect_invert: Invert the default sense of the write protect switch.
- * @use_dma: Set to allow the use of DMA.
- * @gpio_detect: GPIO number for the card detect line.
- * @gpio_wprotect: GPIO number for the write protect line.
- * @ocr_avail: The mask of the available power states, non-zero to use.
- * @set_power: Callback to control the power mode.
- *
- * The @gpio_detect is used for card detection when @no_wprotect is unset,
- * and the default sense is that 0 returned from gpio_get_value() means
- * that a card is inserted. If @detect_invert is set, then the value from
- * gpio_get_value() is inverted, which makes 1 mean card inserted.
- *
- * The driver will use @gpio_wprotect to signal whether the card is write
- * protected if @no_wprotect is not set. A 0 returned from gpio_get_value()
- * means the card is read/write, and 1 means read-only. The @wprotect_invert
- * will invert the value returned from gpio_get_value().
- *
- * Card power is set by @ocr_availa, using MCC_VDD_ constants if it is set
- * to a non-zero value, otherwise the default of 3.2-3.4V is used.
- */
-struct s3c24xx_mci_pdata {
-        unsigned int    no_wprotect:1;
-        unsigned int    no_detect:1;
-        unsigned int    wprotect_invert:1;
-        unsigned int    detect_invert:1;        /* set => detect active high */
-        unsigned int    use_dma:1;
-        unsigned int    gpio_detect;
-        unsigned int    gpio_wprotect;
-        unsigned long   ocr_avail;
-        void            (*set_power)(unsigned char power_mode,
-                                     unsigned short vdd);
-};
-/**
- * s3c24xx_mci_set_platdata - set platform data for mmc/sdi device
- * @pdata: The platform data
- *
- * Copy the platform data supplied by @pdata so that this can be marked
- * __initdata.
- */
-extern void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata);
-#endif /* _ARCH_NCI_H */
diff --git a/arch/arm/plat-samsung/include/plat/mipi_csis.h b/arch/arm/plat-samsung/include/plat/mipi_csis.h
deleted file mode 100644
index c45b1e8d4c2e..000000000000
--- a/arch/arm/plat-samsung/include/plat/mipi_csis.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
- *
- * S5P series MIPI CSI slave device support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __PLAT_SAMSUNG_MIPI_CSIS_H_
-#define __PLAT_SAMSUNG_MIPI_CSIS_H_ __FILE__
-struct platform_device;
-/**
- * struct s5p_platform_mipi_csis - platform data for S5P MIPI-CSIS driver
- * @clk_rate: bus clock frequency
- * @lanes: number of data lanes used
- * @alignment: data alignment in bits
- * @hs_settle: HS-RX settle time
- * @fixed_phy_vdd: false to enable external D-PHY regulator management in the
- *                 driver or true in case this regulator has no enable function
- * @phy_enable: pointer to a callback controlling D-PHY enable/reset
- */
-struct s5p_platform_mipi_csis {
-        unsigned long clk_rate;
-        u8 lanes;
-        u8 alignment;
-        u8 hs_settle;
-        bool fixed_phy_vdd;
-        int (*phy_enable)(struct platform_device *pdev, bool on);
-};
-/**
- * s5p_csis_phy_enable - global MIPI-CSI receiver D-PHY control
- * @pdev: MIPI-CSIS platform device
- * @on: true to enable D-PHY and deassert its reset
- *      false to disable D-PHY
- */
-int s5p_csis_phy_enable(struct platform_device *pdev, bool on);
-#endif /* __PLAT_SAMSUNG_MIPI_CSIS_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/nand.h b/arch/arm/plat-samsung/include/plat/nand.h
deleted file mode 100644
index b64115fa93a4..000000000000
--- a/arch/arm/plat-samsung/include/plat/nand.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/nand.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - NAND device controller platform_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-/**
- * struct s3c2410_nand_set - define a set of one or more nand chips
- * @disable_ecc:        Entirely disable ECC - Dangerous
- * @flash_bbt:          Openmoko u-boot can create a Bad Block Table
- *                      Setting this flag will allow the kernel to
- *                      look for it at boot time and also skip the NAND
- *                      scan.
- * @options:            Default value to set into 'struct nand_chip' options.
- * @nr_chips:           Number of chips in this set
- * @nr_partitions:      Number of partitions pointed to by @partitions
- * @name:               Name of set (optional)
- * @nr_map:             Map for low-layer logical to physical chip numbers (option)
- * @partitions:         The mtd partition list
- *
- * define a set of one or more nand chips registered with an unique mtd. Also
- * allows to pass flag to the underlying NAND layer. 'disable_ecc' will trigger
- * a warning at boot time.
- */
-struct s3c2410_nand_set {
-        unsigned int            disable_ecc:1;
-        unsigned int            flash_bbt:1;
-        unsigned int            options;
-        int                     nr_chips;
-        int                     nr_partitions;
-        char                    *name;
-        int                     *nr_map;
-        struct mtd_partition    *partitions;
-        struct nand_ecclayout   *ecc_layout;
-};
-struct s3c2410_platform_nand {
-        /* timing information for controller, all times in nanoseconds */
-        int     tacls;  /* time for active CLE/ALE to nWE/nOE */
-        int     twrph0; /* active time for nWE/nOE */
-        int     twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
-        unsigned int    ignore_unset_ecc:1;
-        int                     nr_sets;
-        struct s3c2410_nand_set *sets;
-        void                    (*select_chip)(struct s3c2410_nand_set *,
-                                               int chip);
-};
-/**
- * s3c_nand_set_platdata() - register NAND platform data.
- * @nand: The NAND platform data to register with s3c_device_nand.
- *
- * This function copies the given NAND platform data, @nand and registers
- * it with the s3c_device_nand. This allows @nand to be __initdata.
-*/
-extern void s3c_nand_set_platdata(struct s3c2410_platform_nand *nand);
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
deleted file mode 100644
index 4c3647f80057..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/regs-fb-v4.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C64XX - new-style framebuffer register definitions
- *
- * This is the register set for the new style framebuffer interface
- * found from the S3C2443 onwards and specifically the S3C64XX series
- * S3C6400 and S3C6410.
- *
- * The file contains the cpu specific items which change between whichever
- * architecture is selected. See <plat/regs-fb.h> for the core definitions
- * that are the same.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-/* include the core definitions here, in case we really do need to
- * override them at a later date.
-*/
-#include <plat/regs-fb.h>
-#define S3C_FB_MAX_WIN (5)  /* number of hardware windows available. */
-#define VIDCON1_FSTATUS_EVEN    (1 << 15)
-/* Video timing controls */
-#define VIDTCON0                                (0x10)
-#define VIDTCON1                                (0x14)
-#define VIDTCON2                                (0x18)
-/* Window position controls */
-#define WINCON(_win)                            (0x20 + ((_win) * 4))
-/* OSD1 and OSD4 do not have register D */
-#define VIDOSD_BASE                             (0x40)
-#define VIDINTCON0                              (0x130)
-/* WINCONx */
-#define WINCONx_CSCWIDTH_MASK                   (0x3 << 26)
-#define WINCONx_CSCWIDTH_SHIFT                  (26)
-#define WINCONx_CSCWIDTH_WIDE                   (0x0 << 26)
-#define WINCONx_CSCWIDTH_NARROW                 (0x3 << 26)
-#define WINCONx_ENLOCAL                         (1 << 22)
-#define WINCONx_BUFSTATUS                       (1 << 21)
-#define WINCONx_BUFSEL                          (1 << 20)
-#define WINCONx_BUFAUTOEN                       (1 << 19)
-#define WINCONx_YCbCr                           (1 << 13)
-#define WINCON1_LOCALSEL_CAMIF                  (1 << 23)
-#define WINCON2_LOCALSEL_CAMIF                  (1 << 23)
-#define WINCON2_BLD_PIX                         (1 << 6)
-#define WINCON2_ALPHA_SEL                       (1 << 1)
-#define WINCON2_BPPMODE_MASK                    (0xf << 2)
-#define WINCON2_BPPMODE_SHIFT                   (2)
-#define WINCON2_BPPMODE_1BPP                    (0x0 << 2)
-#define WINCON2_BPPMODE_2BPP                    (0x1 << 2)
-#define WINCON2_BPPMODE_4BPP                    (0x2 << 2)
-#define WINCON2_BPPMODE_8BPP_1232               (0x4 << 2)
-#define WINCON2_BPPMODE_16BPP_565               (0x5 << 2)
-#define WINCON2_BPPMODE_16BPP_A1555             (0x6 << 2)
-#define WINCON2_BPPMODE_16BPP_I1555             (0x7 << 2)
-#define WINCON2_BPPMODE_18BPP_666               (0x8 << 2)
-#define WINCON2_BPPMODE_18BPP_A1665             (0x9 << 2)
-#define WINCON2_BPPMODE_19BPP_A1666             (0xa << 2)
-#define WINCON2_BPPMODE_24BPP_888               (0xb << 2)
-#define WINCON2_BPPMODE_24BPP_A1887             (0xc << 2)
-#define WINCON2_BPPMODE_25BPP_A1888             (0xd << 2)
-#define WINCON2_BPPMODE_28BPP_A4888             (0xd << 2)
-#define WINCON3_BLD_PIX                         (1 << 6)
-#define WINCON3_ALPHA_SEL                       (1 << 1)
-#define WINCON3_BPPMODE_MASK                    (0xf << 2)
-#define WINCON3_BPPMODE_SHIFT                   (2)
-#define WINCON3_BPPMODE_1BPP                    (0x0 << 2)
-#define WINCON3_BPPMODE_2BPP                    (0x1 << 2)
-#define WINCON3_BPPMODE_4BPP                    (0x2 << 2)
-#define WINCON3_BPPMODE_16BPP_565               (0x5 << 2)
-#define WINCON3_BPPMODE_16BPP_A1555             (0x6 << 2)
-#define WINCON3_BPPMODE_16BPP_I1555             (0x7 << 2)
-#define WINCON3_BPPMODE_18BPP_666               (0x8 << 2)
-#define WINCON3_BPPMODE_18BPP_A1665             (0x9 << 2)
-#define WINCON3_BPPMODE_19BPP_A1666             (0xa << 2)
-#define WINCON3_BPPMODE_24BPP_888               (0xb << 2)
-#define WINCON3_BPPMODE_24BPP_A1887             (0xc << 2)
-#define WINCON3_BPPMODE_25BPP_A1888             (0xd << 2)
-#define WINCON3_BPPMODE_28BPP_A4888             (0xd << 2)
-#define VIDINTCON0_FIFIOSEL_WINDOW2             (0x10 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW3             (0x20 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW4             (0x40 << 5)
-#define DITHMODE                                (0x170)
-#define WINxMAP(_win)                           (0x180 + ((_win) * 4))
-#define DITHMODE_R_POS_MASK                     (0x3 << 5)
-#define DITHMODE_R_POS_SHIFT                    (5)
-#define DITHMODE_R_POS_8BIT                     (0x0 << 5)
-#define DITHMODE_R_POS_6BIT                     (0x1 << 5)
-#define DITHMODE_R_POS_5BIT                     (0x2 << 5)
-#define DITHMODE_G_POS_MASK                     (0x3 << 3)
-#define DITHMODE_G_POS_SHIFT                    (3)
-#define DITHMODE_G_POS_8BIT                     (0x0 << 3)
-#define DITHMODE_G_POS_6BIT                     (0x1 << 3)
-#define DITHMODE_G_POS_5BIT                     (0x2 << 3)
-#define DITHMODE_B_POS_MASK                     (0x3 << 1)
-#define DITHMODE_B_POS_SHIFT                    (1)
-#define DITHMODE_B_POS_8BIT                     (0x0 << 1)
-#define DITHMODE_B_POS_6BIT                     (0x1 << 1)
-#define DITHMODE_B_POS_5BIT                     (0x2 << 1)
-#define DITHMODE_DITH_EN                        (1 << 0)
-#define WPALCON                                 (0x1A0)
-/* Palette control */
-/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
- * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
-#define WPALCON_W4PAL_16BPP_A555                (1 << 8)
-#define WPALCON_W3PAL_16BPP_A555                (1 << 7)
-#define WPALCON_W2PAL_16BPP_A555                (1 << 6)
-/* Notes on per-window bpp settings
- *
- * Value        Win0     Win1     Win2     Win3     Win 4
- * 0000         1(P)     1(P)     1(P)     1(P)     1(P)
- * 0001         2(P)     2(P)     2(P)     2(P)     2(P)
- * 0010         4(P)     4(P)     4(P)     4(P)     -none-
- * 0011         8(P)     8(P)     -none-   -none-   -none-
- * 0100         -none-   8(A232)  8(A232)  -none-   -none-
- * 0101         16(565)  16(565)  16(565)  16(565)   16(565)
- * 0110         -none-   16(A555) 16(A555) 16(A555)  16(A555)
- * 0111         16(I555) 16(I565) 16(I555) 16(I555)  16(I555)
- * 1000         18(666)  18(666)  18(666)  18(666)   18(666)
- * 1001         -none-   18(A665) 18(A665) 18(A665)  16(A665)
- * 1010         -none-   19(A666) 19(A666) 19(A666)  19(A666)
- * 1011         24(888)  24(888)  24(888)  24(888)   24(888)
- * 1100         -none-   24(A887) 24(A887) 24(A887)  24(A887)
- * 1101         -none-   25(A888) 25(A888) 25(A888)  25(A888)
- * 1110         -none-   -none-   -none-   -none-    -none-
- * 1111         -none-   -none-   -none-   -none-    -none-
-*/
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
deleted file mode 100644
index 9a78012d6f43..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ /dev/null
@@ -1,403 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/regs-fb.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C Platform - new-style framebuffer register definitions
- *
- * This is the register set for the new style framebuffer interface
- * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
- * S3C64XX series such as the S3C6400 and S3C6410.
- *
- * The file does not contain the cpu specific items which are based on
- * whichever architecture is selected, it only contains the core of the
- * register set. See <mach/regs-fb.h> to get the specifics.
- *
- * Note, we changed to using regs-fb.h as it avoids any clashes with
- * the original regs-lcd.h so out of the way of regs-lcd.h as well as
- * indicating the newer block is much more than just an LCD interface.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-/* Please do not include this file directly, use <mach/regs-fb.h> to
- * ensure all the localised SoC support is included as necessary.
-*/
-/* VIDCON0 */
-#define VIDCON0                                 (0x00)
-#define VIDCON0_INTERLACE                       (1 << 29)
-#define VIDCON0_VIDOUT_MASK                     (0x3 << 26)
-#define VIDCON0_VIDOUT_SHIFT                    (26)
-#define VIDCON0_VIDOUT_RGB                      (0x0 << 26)
-#define VIDCON0_VIDOUT_TV                       (0x1 << 26)
-#define VIDCON0_VIDOUT_I80_LDI0                 (0x2 << 26)
-#define VIDCON0_VIDOUT_I80_LDI1                 (0x3 << 26)
-#define VIDCON0_L1_DATA_MASK                    (0x7 << 23)
-#define VIDCON0_L1_DATA_SHIFT                   (23)
-#define VIDCON0_L1_DATA_16BPP                   (0x0 << 23)
-#define VIDCON0_L1_DATA_18BPP16                 (0x1 << 23)
-#define VIDCON0_L1_DATA_18BPP9                  (0x2 << 23)
-#define VIDCON0_L1_DATA_24BPP                   (0x3 << 23)
-#define VIDCON0_L1_DATA_18BPP                   (0x4 << 23)
-#define VIDCON0_L1_DATA_16BPP8                  (0x5 << 23)
-#define VIDCON0_L0_DATA_MASK                    (0x7 << 20)
-#define VIDCON0_L0_DATA_SHIFT                   (20)
-#define VIDCON0_L0_DATA_16BPP                   (0x0 << 20)
-#define VIDCON0_L0_DATA_18BPP16                 (0x1 << 20)
-#define VIDCON0_L0_DATA_18BPP9                  (0x2 << 20)
-#define VIDCON0_L0_DATA_24BPP                   (0x3 << 20)
-#define VIDCON0_L0_DATA_18BPP                   (0x4 << 20)
-#define VIDCON0_L0_DATA_16BPP8                  (0x5 << 20)
-#define VIDCON0_PNRMODE_MASK                    (0x3 << 17)
-#define VIDCON0_PNRMODE_SHIFT                   (17)
-#define VIDCON0_PNRMODE_RGB                     (0x0 << 17)
-#define VIDCON0_PNRMODE_BGR                     (0x1 << 17)
-#define VIDCON0_PNRMODE_SERIAL_RGB              (0x2 << 17)
-#define VIDCON0_PNRMODE_SERIAL_BGR              (0x3 << 17)
-#define VIDCON0_CLKVALUP                        (1 << 16)
-#define VIDCON0_CLKVAL_F_MASK                   (0xff << 6)
-#define VIDCON0_CLKVAL_F_SHIFT                  (6)
-#define VIDCON0_CLKVAL_F_LIMIT                  (0xff)
-#define VIDCON0_CLKVAL_F(_x)                    ((_x) << 6)
-#define VIDCON0_VLCKFREE                        (1 << 5)
-#define VIDCON0_CLKDIR                          (1 << 4)
-#define VIDCON0_CLKSEL_MASK                     (0x3 << 2)
-#define VIDCON0_CLKSEL_SHIFT                    (2)
-#define VIDCON0_CLKSEL_HCLK                     (0x0 << 2)
-#define VIDCON0_CLKSEL_LCD                      (0x1 << 2)
-#define VIDCON0_CLKSEL_27M                      (0x3 << 2)
-#define VIDCON0_ENVID                           (1 << 1)
-#define VIDCON0_ENVID_F                         (1 << 0)
-#define VIDCON1                                 (0x04)
-#define VIDCON1_LINECNT_MASK                    (0x7ff << 16)
-#define VIDCON1_LINECNT_SHIFT                   (16)
-#define VIDCON1_LINECNT_GET(_v)                 (((_v) >> 16) & 0x7ff)
-#define VIDCON1_VSTATUS_MASK                    (0x3 << 13)
-#define VIDCON1_VSTATUS_SHIFT                   (13)
-#define VIDCON1_VSTATUS_VSYNC                   (0x0 << 13)
-#define VIDCON1_VSTATUS_BACKPORCH               (0x1 << 13)
-#define VIDCON1_VSTATUS_ACTIVE                  (0x2 << 13)
-#define VIDCON1_VSTATUS_FRONTPORCH              (0x0 << 13)
-#define VIDCON1_VCLK_MASK                       (0x3 << 9)
-#define VIDCON1_VCLK_HOLD                       (0x0 << 9)
-#define VIDCON1_VCLK_RUN                        (0x1 << 9)
-#define VIDCON1_INV_VCLK                        (1 << 7)
-#define VIDCON1_INV_HSYNC                       (1 << 6)
-#define VIDCON1_INV_VSYNC                       (1 << 5)
-#define VIDCON1_INV_VDEN                        (1 << 4)
-/* VIDCON2 */
-#define VIDCON2                                 (0x08)
-#define VIDCON2_EN601                           (1 << 23)
-#define VIDCON2_TVFMTSEL_SW                     (1 << 14)
-#define VIDCON2_TVFMTSEL1_MASK                  (0x3 << 12)
-#define VIDCON2_TVFMTSEL1_SHIFT                 (12)
-#define VIDCON2_TVFMTSEL1_RGB                   (0x0 << 12)
-#define VIDCON2_TVFMTSEL1_YUV422                (0x1 << 12)
-#define VIDCON2_TVFMTSEL1_YUV444                (0x2 << 12)
-#define VIDCON2_ORGYCbCr                        (1 << 8)
-#define VIDCON2_YUVORDCrCb                      (1 << 7)
-/* PRTCON (S3C6410, S5PC100)
- * Might not be present in the S3C6410 documentation,
- * but tests prove it's there almost for sure; shouldn't hurt in any case.
- */
-#define PRTCON                                  (0x0c)
-#define PRTCON_PROTECT                          (1 << 11)
-/* VIDTCON0 */
-#define VIDTCON0_VBPDE_MASK                     (0xff << 24)
-#define VIDTCON0_VBPDE_SHIFT                    (24)
-#define VIDTCON0_VBPDE_LIMIT                    (0xff)
-#define VIDTCON0_VBPDE(_x)                      ((_x) << 24)
-#define VIDTCON0_VBPD_MASK                      (0xff << 16)
-#define VIDTCON0_VBPD_SHIFT                     (16)
-#define VIDTCON0_VBPD_LIMIT                     (0xff)
-#define VIDTCON0_VBPD(_x)                       ((_x) << 16)
-#define VIDTCON0_VFPD_MASK                      (0xff << 8)
-#define VIDTCON0_VFPD_SHIFT                     (8)
-#define VIDTCON0_VFPD_LIMIT                     (0xff)
-#define VIDTCON0_VFPD(_x)                       ((_x) << 8)
-#define VIDTCON0_VSPW_MASK                      (0xff << 0)
-#define VIDTCON0_VSPW_SHIFT                     (0)
-#define VIDTCON0_VSPW_LIMIT                     (0xff)
-#define VIDTCON0_VSPW(_x)                       ((_x) << 0)
-/* VIDTCON1 */
-#define VIDTCON1_VFPDE_MASK                     (0xff << 24)
-#define VIDTCON1_VFPDE_SHIFT                    (24)
-#define VIDTCON1_VFPDE_LIMIT                    (0xff)
-#define VIDTCON1_VFPDE(_x)                      ((_x) << 24)
-#define VIDTCON1_HBPD_MASK                      (0xff << 16)
-#define VIDTCON1_HBPD_SHIFT                     (16)
-#define VIDTCON1_HBPD_LIMIT                     (0xff)
-#define VIDTCON1_HBPD(_x)                       ((_x) << 16)
-#define VIDTCON1_HFPD_MASK                      (0xff << 8)
-#define VIDTCON1_HFPD_SHIFT                     (8)
-#define VIDTCON1_HFPD_LIMIT                     (0xff)
-#define VIDTCON1_HFPD(_x)                       ((_x) << 8)
-#define VIDTCON1_HSPW_MASK                      (0xff << 0)
-#define VIDTCON1_HSPW_SHIFT                     (0)
-#define VIDTCON1_HSPW_LIMIT                     (0xff)
-#define VIDTCON1_HSPW(_x)                       ((_x) << 0)
-#define VIDTCON2                                (0x18)
-#define VIDTCON2_LINEVAL_E(_x)                  ((((_x) & 0x800) >> 11) << 23)
-#define VIDTCON2_LINEVAL_MASK                   (0x7ff << 11)
-#define VIDTCON2_LINEVAL_SHIFT                  (11)
-#define VIDTCON2_LINEVAL_LIMIT                  (0x7ff)
-#define VIDTCON2_LINEVAL(_x)                    (((_x) & 0x7ff) << 11)
-#define VIDTCON2_HOZVAL_E(_x)                   ((((_x) & 0x800) >> 11) << 22)
-#define VIDTCON2_HOZVAL_MASK                    (0x7ff << 0)
-#define VIDTCON2_HOZVAL_SHIFT                   (0)
-#define VIDTCON2_HOZVAL_LIMIT                   (0x7ff)
-#define VIDTCON2_HOZVAL(_x)                     (((_x) & 0x7ff) << 0)
-/* WINCONx */
-#define WINCONx_BITSWP                          (1 << 18)
-#define WINCONx_BYTSWP                          (1 << 17)
-#define WINCONx_HAWSWP                          (1 << 16)
-#define WINCONx_WSWP                            (1 << 15)
-#define WINCONx_BURSTLEN_MASK                   (0x3 << 9)
-#define WINCONx_BURSTLEN_SHIFT                  (9)
-#define WINCONx_BURSTLEN_16WORD                 (0x0 << 9)
-#define WINCONx_BURSTLEN_8WORD                  (0x1 << 9)
-#define WINCONx_BURSTLEN_4WORD                  (0x2 << 9)
-#define WINCONx_ENWIN                           (1 << 0)
-#define WINCON0_BPPMODE_MASK                    (0xf << 2)
-#define WINCON0_BPPMODE_SHIFT                   (2)
-#define WINCON0_BPPMODE_1BPP                    (0x0 << 2)
-#define WINCON0_BPPMODE_2BPP                    (0x1 << 2)
-#define WINCON0_BPPMODE_4BPP                    (0x2 << 2)
-#define WINCON0_BPPMODE_8BPP_PALETTE            (0x3 << 2)
-#define WINCON0_BPPMODE_16BPP_565               (0x5 << 2)
-#define WINCON0_BPPMODE_16BPP_1555              (0x7 << 2)
-#define WINCON0_BPPMODE_18BPP_666               (0x8 << 2)
-#define WINCON0_BPPMODE_24BPP_888               (0xb << 2)
-#define WINCON1_BLD_PIX                         (1 << 6)
-#define WINCON1_ALPHA_SEL                       (1 << 1)
-#define WINCON1_BPPMODE_MASK                    (0xf << 2)
-#define WINCON1_BPPMODE_SHIFT                   (2)
-#define WINCON1_BPPMODE_1BPP                    (0x0 << 2)
-#define WINCON1_BPPMODE_2BPP                    (0x1 << 2)
-#define WINCON1_BPPMODE_4BPP                    (0x2 << 2)
-#define WINCON1_BPPMODE_8BPP_PALETTE            (0x3 << 2)
-#define WINCON1_BPPMODE_8BPP_1232               (0x4 << 2)
-#define WINCON1_BPPMODE_16BPP_565               (0x5 << 2)
-#define WINCON1_BPPMODE_16BPP_A1555             (0x6 << 2)
-#define WINCON1_BPPMODE_16BPP_I1555             (0x7 << 2)
-#define WINCON1_BPPMODE_18BPP_666               (0x8 << 2)
-#define WINCON1_BPPMODE_18BPP_A1665             (0x9 << 2)
-#define WINCON1_BPPMODE_19BPP_A1666             (0xa << 2)
-#define WINCON1_BPPMODE_24BPP_888               (0xb << 2)
-#define WINCON1_BPPMODE_24BPP_A1887             (0xc << 2)
-#define WINCON1_BPPMODE_25BPP_A1888             (0xd << 2)
-#define WINCON1_BPPMODE_28BPP_A4888             (0xd << 2)
-/* S5PV210 */
-#define SHADOWCON                               (0x34)
-#define SHADOWCON_WINx_PROTECT(_win)            (1 << (10 + (_win)))
-/* DMA channels (all windows) */
-#define SHADOWCON_CHx_ENABLE(_win)              (1 << (_win))
-/* Local input channels (windows 0-2) */
-#define SHADOWCON_CHx_LOCAL_ENABLE(_win)        (1 << (5 + (_win)))
-#define VIDOSDxA_TOPLEFT_X_E(_x)                ((((_x) & 0x800) >> 11) << 23)
-#define VIDOSDxA_TOPLEFT_X_MASK                 (0x7ff << 11)
-#define VIDOSDxA_TOPLEFT_X_SHIFT                (11)
-#define VIDOSDxA_TOPLEFT_X_LIMIT                (0x7ff)
-#define VIDOSDxA_TOPLEFT_X(_x)                  (((_x) & 0x7ff) << 11)
-#define VIDOSDxA_TOPLEFT_Y_E(_x)                ((((_x) & 0x800) >> 11) << 22)
-#define VIDOSDxA_TOPLEFT_Y_MASK                 (0x7ff << 0)
-#define VIDOSDxA_TOPLEFT_Y_SHIFT                (0)
-#define VIDOSDxA_TOPLEFT_Y_LIMIT                (0x7ff)
-#define VIDOSDxA_TOPLEFT_Y(_x)                  (((_x) & 0x7ff) << 0)
-#define VIDOSDxB_BOTRIGHT_X_E(_x)               ((((_x) & 0x800) >> 11) << 23)
-#define VIDOSDxB_BOTRIGHT_X_MASK                (0x7ff << 11)
-#define VIDOSDxB_BOTRIGHT_X_SHIFT               (11)
-#define VIDOSDxB_BOTRIGHT_X_LIMIT               (0x7ff)
-#define VIDOSDxB_BOTRIGHT_X(_x)                 (((_x) & 0x7ff) << 11)
-#define VIDOSDxB_BOTRIGHT_Y_E(_x)               ((((_x) & 0x800) >> 11) << 22)
-#define VIDOSDxB_BOTRIGHT_Y_MASK                (0x7ff << 0)
-#define VIDOSDxB_BOTRIGHT_Y_SHIFT               (0)
-#define VIDOSDxB_BOTRIGHT_Y_LIMIT               (0x7ff)
-#define VIDOSDxB_BOTRIGHT_Y(_x)                 (((_x) & 0x7ff) << 0)
-/* For VIDOSD[1..4]C */
-#define VIDISD14C_ALPHA0_R(_x)                  ((_x) << 20)
-#define VIDISD14C_ALPHA0_G_MASK                 (0xf << 16)
-#define VIDISD14C_ALPHA0_G_SHIFT                (16)
-#define VIDISD14C_ALPHA0_G_LIMIT                (0xf)
-#define VIDISD14C_ALPHA0_G(_x)                  ((_x) << 16)
-#define VIDISD14C_ALPHA0_B_MASK                 (0xf << 12)
-#define VIDISD14C_ALPHA0_B_SHIFT                (12)
-#define VIDISD14C_ALPHA0_B_LIMIT                (0xf)
-#define VIDISD14C_ALPHA0_B(_x)                  ((_x) << 12)
-#define VIDISD14C_ALPHA1_R_MASK                 (0xf << 8)
-#define VIDISD14C_ALPHA1_R_SHIFT                (8)
-#define VIDISD14C_ALPHA1_R_LIMIT                (0xf)
-#define VIDISD14C_ALPHA1_R(_x)                  ((_x) << 8)
-#define VIDISD14C_ALPHA1_G_MASK                 (0xf << 4)
-#define VIDISD14C_ALPHA1_G_SHIFT                (4)
-#define VIDISD14C_ALPHA1_G_LIMIT                (0xf)
-#define VIDISD14C_ALPHA1_G(_x)                  ((_x) << 4)
-#define VIDISD14C_ALPHA1_B_MASK                 (0xf << 0)
-#define VIDISD14C_ALPHA1_B_SHIFT                (0)
-#define VIDISD14C_ALPHA1_B_LIMIT                (0xf)
-#define VIDISD14C_ALPHA1_B(_x)                  ((_x) << 0)
-/* Video buffer addresses */
-#define VIDW_BUF_START(_buff)                   (0xA0 + ((_buff) * 8))
-#define VIDW_BUF_START1(_buff)                  (0xA4 + ((_buff) * 8))
-#define VIDW_BUF_END(_buff)                     (0xD0 + ((_buff) * 8))
-#define VIDW_BUF_END1(_buff)                    (0xD4 + ((_buff) * 8))
-#define VIDW_BUF_SIZE(_buff)                    (0x100 + ((_buff) * 4))
-#define VIDW_BUF_SIZE_OFFSET_E(_x)              ((((_x) & 0x2000) >> 13) << 27)
-#define VIDW_BUF_SIZE_OFFSET_MASK               (0x1fff << 13)
-#define VIDW_BUF_SIZE_OFFSET_SHIFT              (13)
-#define VIDW_BUF_SIZE_OFFSET_LIMIT              (0x1fff)
-#define VIDW_BUF_SIZE_OFFSET(_x)                (((_x) & 0x1fff) << 13)
-#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x)           ((((_x) & 0x2000) >> 13) << 26)
-#define VIDW_BUF_SIZE_PAGEWIDTH_MASK            (0x1fff << 0)
-#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT           (0)
-#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT           (0x1fff)
-#define VIDW_BUF_SIZE_PAGEWIDTH(_x)             (((_x) & 0x1fff) << 0)
-/* Interrupt controls and status */
-#define VIDINTCON0_FIFOINTERVAL_MASK            (0x3f << 20)
-#define VIDINTCON0_FIFOINTERVAL_SHIFT           (20)
-#define VIDINTCON0_FIFOINTERVAL_LIMIT           (0x3f)
-#define VIDINTCON0_FIFOINTERVAL(_x)             ((_x) << 20)
-#define VIDINTCON0_INT_SYSMAINCON               (1 << 19)
-#define VIDINTCON0_INT_SYSSUBCON                (1 << 18)
-#define VIDINTCON0_INT_I80IFDONE                (1 << 17)
-#define VIDINTCON0_FRAMESEL0_MASK               (0x3 << 15)
-#define VIDINTCON0_FRAMESEL0_SHIFT              (15)
-#define VIDINTCON0_FRAMESEL0_BACKPORCH          (0x0 << 15)
-#define VIDINTCON0_FRAMESEL0_VSYNC              (0x1 << 15)
-#define VIDINTCON0_FRAMESEL0_ACTIVE             (0x2 << 15)
-#define VIDINTCON0_FRAMESEL0_FRONTPORCH         (0x3 << 15)
-#define VIDINTCON0_FRAMESEL1                    (1 << 13)
-#define VIDINTCON0_FRAMESEL1_MASK               (0x3 << 13)
-#define VIDINTCON0_FRAMESEL1_NONE               (0x0 << 13)
-#define VIDINTCON0_FRAMESEL1_BACKPORCH          (0x1 << 13)
-#define VIDINTCON0_FRAMESEL1_VSYNC              (0x2 << 13)
-#define VIDINTCON0_FRAMESEL1_FRONTPORCH         (0x3 << 13)
-#define VIDINTCON0_INT_FRAME                    (1 << 12)
-#define VIDINTCON0_FIFIOSEL_MASK                (0x7f << 5)
-#define VIDINTCON0_FIFIOSEL_SHIFT               (5)
-#define VIDINTCON0_FIFIOSEL_WINDOW0             (0x1 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW1             (0x2 << 5)
-#define VIDINTCON0_FIFOLEVEL_MASK               (0x7 << 2)
-#define VIDINTCON0_FIFOLEVEL_SHIFT              (2)
-#define VIDINTCON0_FIFOLEVEL_TO25PC             (0x0 << 2)
-#define VIDINTCON0_FIFOLEVEL_TO50PC             (0x1 << 2)
-#define VIDINTCON0_FIFOLEVEL_TO75PC             (0x2 << 2)
-#define VIDINTCON0_FIFOLEVEL_EMPTY              (0x3 << 2)
-#define VIDINTCON0_FIFOLEVEL_FULL               (0x4 << 2)
-#define VIDINTCON0_INT_FIFO_MASK                (0x3 << 0)
-#define VIDINTCON0_INT_FIFO_SHIFT               (0)
-#define VIDINTCON0_INT_ENABLE                   (1 << 0)
-#define VIDINTCON1                              (0x134)
-#define VIDINTCON1_INT_I180                     (1 << 2)
-#define VIDINTCON1_INT_FRAME                    (1 << 1)
-#define VIDINTCON1_INT_FIFO                     (1 << 0)
-/* Window colour-key control registers */
-#define WKEYCON                                 (0x140) /* 6410,V210 */
-#define WKEYCON0                                (0x00)
-#define WKEYCON1                                (0x04)
-#define WxKEYCON0_KEYBL_EN                      (1 << 26)
-#define WxKEYCON0_KEYEN_F                       (1 << 25)
-#define WxKEYCON0_DIRCON                        (1 << 24)
-#define WxKEYCON0_COMPKEY_MASK                  (0xffffff << 0)
-#define WxKEYCON0_COMPKEY_SHIFT                 (0)
-#define WxKEYCON0_COMPKEY_LIMIT                 (0xffffff)
-#define WxKEYCON0_COMPKEY(_x)                   ((_x) << 0)
-#define WxKEYCON1_COLVAL_MASK                   (0xffffff << 0)
-#define WxKEYCON1_COLVAL_SHIFT                  (0)
-#define WxKEYCON1_COLVAL_LIMIT                  (0xffffff)
-#define WxKEYCON1_COLVAL(_x)                    ((_x) << 0)
-/* Window blanking (MAP) */
-#define WINxMAP_MAP                             (1 << 24)
-#define WINxMAP_MAP_COLOUR_MASK                 (0xffffff << 0)
-#define WINxMAP_MAP_COLOUR_SHIFT                (0)
-#define WINxMAP_MAP_COLOUR_LIMIT                (0xffffff)
-#define WINxMAP_MAP_COLOUR(_x)                  ((_x) << 0)
-#define WPALCON_PAL_UPDATE                      (1 << 9)
-#define WPALCON_W1PAL_MASK                      (0x7 << 3)
-#define WPALCON_W1PAL_SHIFT                     (3)
-#define WPALCON_W1PAL_25BPP_A888                (0x0 << 3)
-#define WPALCON_W1PAL_24BPP                     (0x1 << 3)
-#define WPALCON_W1PAL_19BPP_A666                (0x2 << 3)
-#define WPALCON_W1PAL_18BPP_A665                (0x3 << 3)
-#define WPALCON_W1PAL_18BPP                     (0x4 << 3)
-#define WPALCON_W1PAL_16BPP_A555                (0x5 << 3)
-#define WPALCON_W1PAL_16BPP_565                 (0x6 << 3)
-#define WPALCON_W0PAL_MASK                      (0x7 << 0)
-#define WPALCON_W0PAL_SHIFT                     (0)
-#define WPALCON_W0PAL_25BPP_A888                (0x0 << 0)
-#define WPALCON_W0PAL_24BPP                     (0x1 << 0)
-#define WPALCON_W0PAL_19BPP_A666                (0x2 << 0)
-#define WPALCON_W0PAL_18BPP_A665                (0x3 << 0)
-#define WPALCON_W0PAL_18BPP                     (0x4 << 0)
-#define WPALCON_W0PAL_16BPP_A555                (0x5 << 0)
-#define WPALCON_W0PAL_16BPP_565                 (0x6 << 0)
-/* Blending equation control */
-#define BLENDCON                                (0x260)
-#define BLENDCON_NEW_MASK                       (1 << 0)
-#define BLENDCON_NEW_8BIT_ALPHA_VALUE           (1 << 0)
-#define BLENDCON_NEW_4BIT_ALPHA_VALUE           (0 << 0)
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
deleted file mode 100644
index ceba18d23a5a..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
- *
- * Copyright (C) 2009 Samsung Electronics Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __S3C64XX_PLAT_SPI_H
-#define __S3C64XX_PLAT_SPI_H
-struct platform_device;
-/**
- * struct s3c64xx_spi_csinfo - ChipSelect description
- * @fb_delay: Slave specific feedback delay.
- *            Refer to FB_CLK_SEL register definition in SPI chapter.
- * @line: Custom 'identity' of the CS line.
- *
- * This is per SPI-Slave Chipselect information.
- * Allocate and initialize one in machine init code and make the
- * spi_board_info.controller_data point to it.
- */
-struct s3c64xx_spi_csinfo {
-        u8 fb_delay;
-        unsigned line;
-};
-/**
- * struct s3c64xx_spi_info - SPI Controller defining structure
- * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
- * @num_cs: Number of CS this controller emulates.
- * @cfg_gpio: Configure pins for this SPI controller.
- */
-struct s3c64xx_spi_info {
-        int src_clk_nr;
-        int num_cs;
-        int (*cfg_gpio)(void);
-};
-/**
- * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
- *                              initialization code.
- * @cfg_gpio: Pointer to gpio setup function.
- * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
- * @num_cs: Number of elements in the 'cs' array.
- *
- * Call this from machine init code for each SPI Controller that
- * has some chips attached to it.
- */
-extern void s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
-                                                int num_cs);
-extern void s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
-                                                int num_cs);
-extern void s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
-                                                int num_cs);
-/* defined by architecture to configure gpio */
-extern int s3c64xx_spi0_cfg_gpio(void);
-extern int s3c64xx_spi1_cfg_gpio(void);
-extern int s3c64xx_spi2_cfg_gpio(void);
-extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
-extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
-extern struct s3c64xx_spi_info s3c64xx_spi2_pdata;
-#endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/arm/plat-samsung/include/plat/ts.h b/arch/arm/plat-samsung/include/plat/ts.h
deleted file mode 100644
index 26fdb22e0fc2..000000000000
--- a/arch/arm/plat-samsung/include/plat/ts.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/ts.h
- *
- * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARM_TS_H
-#define __ASM_ARM_TS_H
-struct s3c2410_ts_mach_info {
-       int             delay;
-       int             presc;
-       int             oversampling_shift;
-        void    (*cfg_gpio)(struct platform_device *dev);
-};
-extern void s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *);
-/* defined by architecture to configure gpio */
-extern void s3c24xx_ts_cfg_gpio(struct platform_device *dev);
-#endif /* __ASM_ARM_TS_H */
diff --git a/arch/arm/plat-samsung/include/plat/udc.h b/arch/arm/plat-samsung/include/plat/udc.h
deleted file mode 100644
index de8e2288a509..000000000000
--- a/arch/arm/plat-samsung/include/plat/udc.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/udc.h
- *
- * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *
- *  Changelog:
- *      14-Mar-2005     RTP     Created file
- *      02-Aug-2005     RTP     File rename
- *      07-Sep-2005     BJD     Minor cleanups, changed cmd to enum
- *      18-Jan-2007     HMW     Add per-platform vbus_draw function
-*/
-#ifndef __ASM_ARM_ARCH_UDC_H
-#define __ASM_ARM_ARCH_UDC_H
-enum s3c2410_udc_cmd_e {
-        S3C2410_UDC_P_ENABLE    = 1,    /* Pull-up enable        */
-        S3C2410_UDC_P_DISABLE   = 2,    /* Pull-up disable       */
-        S3C2410_UDC_P_RESET     = 3,    /* UDC reset, in case of */
-};
-struct s3c2410_udc_mach_info {
-        void    (*udc_command)(enum s3c2410_udc_cmd_e);
-        void    (*vbus_draw)(unsigned int ma);
-        unsigned int pullup_pin;
-        unsigned int pullup_pin_inverted;
-        unsigned int vbus_pin;
-        unsigned char vbus_pin_inverted;
-};
-extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
-struct s3c24xx_hsudc_platdata;
-extern void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd);
-#endif /* __ASM_ARM_ARCH_UDC_H */
diff --git a/arch/arm/plat-samsung/include/plat/usb-control.h b/arch/arm/plat-samsung/include/plat/usb-control.h
deleted file mode 100644
index 7fa1fbefc3f2..000000000000
--- a/arch/arm/plat-samsung/include/plat/usb-control.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/usb-control.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C - USB host port information
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_USBCONTROL_H
-#define __ASM_ARCH_USBCONTROL_H
-#define S3C_HCDFLG_USED (1)
-struct s3c2410_hcd_port {
-        unsigned char   flags;
-        unsigned char   power;
-        unsigned char   oc_status;
-        unsigned char   oc_changed;
-};
-struct s3c2410_hcd_info {
-        struct usb_hcd          *hcd;
-        struct s3c2410_hcd_port port[2];
-        void            (*power_control)(int port, int to);
-        void            (*enable_oc)(struct s3c2410_hcd_info *, int on);
-        void            (*report_oc)(struct s3c2410_hcd_info *, int ports);
-};
-static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports)
-{
-        if (info->report_oc != NULL) {
-                (info->report_oc)(info, ports);
-        }
-}
-extern void s3c_ohci_set_platdata(struct s3c2410_hcd_info *info);
-#endif /*__ASM_ARCH_USBCONTROL_H */
diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c
index f9431fe5b06e..23557d30e44c 100644
--- a/arch/arm/plat-samsung/s5p-irq-gpioint.c
+++ b/arch/arm/plat-samsung/s5p-irq-gpioint.c
@@ -24,7 +24,7 @@
 #include <asm/mach/irq.h>
-#define GPIO_BASE(chip)         (((unsigned long)(chip)->base) & 0xFFFFF000u)
+#define GPIO_BASE(chip)         ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
 #define CON_OFFSET              0x700
 #define MASK_OFFSET             0x900
@@ -153,7 +153,7 @@ static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
        bank->chips[group - bank->start] = chip;
        gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
-                                    (void __iomem *)GPIO_BASE(chip),
+                                    GPIO_BASE(chip),
                                    handle_level_irq);
        if (!gc)
                return -ENOMEM;
diff --git a/arch/arm/plat-samsung/setup-mipiphy.c b/arch/arm/plat-samsung/setup-mipiphy.c
index 683c466c0e6a..147459327601 100644
--- a/arch/arm/plat-samsung/setup-mipiphy.c
+++ b/arch/arm/plat-samsung/setup-mipiphy.c
@@ -14,24 +14,18 @@
 #include <linux/spinlock.h>
 #include <mach/regs-clock.h>
-static int __s5p_mipi_phy_control(struct platform_device *pdev,
+static int __s5p_mipi_phy_control(int id, bool on, u32 reset)
-                                  bool on, u32 reset)
 {
        static DEFINE_SPINLOCK(lock);
        void __iomem *addr;
        unsigned long flags;
-        int pid;
        u32 cfg;
-        if (!pdev)
+        id = max(0, id);
+        if (id > 1)
                return -EINVAL;
-        pid = (pdev->id == -1) ? 0 : pdev->id;
+        addr = S5P_MIPI_DPHY_CONTROL(id);
-        if (pid != 0 && pid != 1)
-                return -EINVAL;
-        addr = S5P_MIPI_DPHY_CONTROL(pid);
        spin_lock_irqsave(&lock, flags);
@@ -52,12 +46,12 @@ static int __s5p_mipi_phy_control(struct platform_device *pdev,
        return 0;
 }
-int s5p_csis_phy_enable(struct platform_device *pdev, bool on)
+int s5p_csis_phy_enable(int id, bool on)
 {
-        return __s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_SRESETN);
+        return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN);
 }
 int s5p_dsim_phy_enable(struct platform_device *pdev, bool on)
 {
-        return __s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_MRESETN);
+        return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN);
 }
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
index 4dcb11c3d894..60552e22f22e 100644
--- a/arch/arm/plat-samsung/time.c
+++ b/arch/arm/plat-samsung/time.c
@@ -28,7 +28,6 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
diff --git a/arch/arm/plat-spear/include/plat/gpio.h b/arch/arm/plat-spear/include/plat/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/plat-spear/include/plat/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/plat-spear/include/plat/keyboard.h b/arch/arm/plat-spear/include/plat/keyboard.h
deleted file mode 100644
index 9248e3a7e333..000000000000
--- a/arch/arm/plat-spear/include/plat/keyboard.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright (C) 2010 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __PLAT_KEYBOARD_H
-#define __PLAT_KEYBOARD_H
-#include <linux/bitops.h>
-#include <linux/input.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/types.h>
-#define DECLARE_9x9_KEYMAP(_name) \
-int _name[] = { \
-        KEY(0, 0, KEY_ESC), \
-        KEY(0, 1, KEY_1), \
-        KEY(0, 2, KEY_2), \
-        KEY(0, 3, KEY_3), \
-        KEY(0, 4, KEY_4), \
-        KEY(0, 5, KEY_5), \
-        KEY(0, 6, KEY_6), \
-        KEY(0, 7, KEY_7), \
-        KEY(0, 8, KEY_8), \
-        KEY(1, 0, KEY_9), \
-        KEY(1, 1, KEY_MINUS), \
-        KEY(1, 2, KEY_EQUAL), \
-        KEY(1, 3, KEY_BACKSPACE), \
-        KEY(1, 4, KEY_TAB), \
-        KEY(1, 5, KEY_Q), \
-        KEY(1, 6, KEY_W), \
-        KEY(1, 7, KEY_E), \
-        KEY(1, 8, KEY_R), \
-        KEY(2, 0, KEY_T), \
-        KEY(2, 1, KEY_Y), \
-        KEY(2, 2, KEY_U), \
-        KEY(2, 3, KEY_I), \
-        KEY(2, 4, KEY_O), \
-        KEY(2, 5, KEY_P), \
-        KEY(2, 6, KEY_LEFTBRACE), \
-        KEY(2, 7, KEY_RIGHTBRACE), \
-        KEY(2, 8, KEY_ENTER), \
-        KEY(3, 0, KEY_LEFTCTRL), \
-        KEY(3, 1, KEY_A), \
-        KEY(3, 2, KEY_S), \
-        KEY(3, 3, KEY_D), \
-        KEY(3, 4, KEY_F), \
-        KEY(3, 5, KEY_G), \
-        KEY(3, 6, KEY_H), \
-        KEY(3, 7, KEY_J), \
-        KEY(3, 8, KEY_K), \
-        KEY(4, 0, KEY_L), \
-        KEY(4, 1, KEY_SEMICOLON), \
-        KEY(4, 2, KEY_APOSTROPHE), \
-        KEY(4, 3, KEY_GRAVE), \
-        KEY(4, 4, KEY_LEFTSHIFT), \
-        KEY(4, 5, KEY_BACKSLASH), \
-        KEY(4, 6, KEY_Z), \
-        KEY(4, 7, KEY_X), \
-        KEY(4, 8, KEY_C), \
-        KEY(5, 0, KEY_V), \
-        KEY(5, 1, KEY_B), \
-        KEY(5, 2, KEY_N), \
-        KEY(5, 3, KEY_M), \
-        KEY(5, 4, KEY_COMMA), \
-        KEY(5, 5, KEY_DOT), \
-        KEY(5, 6, KEY_SLASH), \
-        KEY(5, 7, KEY_RIGHTSHIFT), \
-        KEY(5, 8, KEY_KPASTERISK), \
-        KEY(6, 0, KEY_LEFTALT), \
-        KEY(6, 1, KEY_SPACE), \
-        KEY(6, 2, KEY_CAPSLOCK), \
-        KEY(6, 3, KEY_F1), \
-        KEY(6, 4, KEY_F2), \
-        KEY(6, 5, KEY_F3), \
-        KEY(6, 6, KEY_F4), \
-        KEY(6, 7, KEY_F5), \
-        KEY(6, 8, KEY_F6), \
-        KEY(7, 0, KEY_F7), \
-        KEY(7, 1, KEY_F8), \
-        KEY(7, 2, KEY_F9), \
-        KEY(7, 3, KEY_F10), \
-        KEY(7, 4, KEY_NUMLOCK), \
-        KEY(7, 5, KEY_SCROLLLOCK), \
-        KEY(7, 6, KEY_KP7), \
-        KEY(7, 7, KEY_KP8), \
-        KEY(7, 8, KEY_KP9), \
-        KEY(8, 0, KEY_KPMINUS), \
-        KEY(8, 1, KEY_KP4), \
-        KEY(8, 2, KEY_KP5), \
-        KEY(8, 3, KEY_KP6), \
-        KEY(8, 4, KEY_KPPLUS), \
-        KEY(8, 5, KEY_KP1), \
-        KEY(8, 6, KEY_KP2), \
-        KEY(8, 7, KEY_KP3), \
-        KEY(8, 8, KEY_KP0), \
-}
-#define DECLARE_6x6_KEYMAP(_name) \
-int _name[] = { \
-        KEY(0, 0, KEY_RESERVED), \
-        KEY(0, 1, KEY_1), \
-        KEY(0, 2, KEY_2), \
-        KEY(0, 3, KEY_3), \
-        KEY(0, 4, KEY_4), \
-        KEY(0, 5, KEY_5), \
-        KEY(1, 0, KEY_Q), \
-        KEY(1, 1, KEY_W), \
-        KEY(1, 2, KEY_E), \
-        KEY(1, 3, KEY_R), \
-        KEY(1, 4, KEY_T), \
-        KEY(1, 5, KEY_Y), \
-        KEY(2, 0, KEY_D), \
-        KEY(2, 1, KEY_F), \
-        KEY(2, 2, KEY_G), \
-        KEY(2, 3, KEY_H), \
-        KEY(2, 4, KEY_J), \
-        KEY(2, 5, KEY_K), \
-        KEY(3, 0, KEY_B), \
-        KEY(3, 1, KEY_N), \
-        KEY(3, 2, KEY_M), \
-        KEY(3, 3, KEY_COMMA), \
-        KEY(3, 4, KEY_DOT), \
-        KEY(3, 5, KEY_SLASH), \
-        KEY(4, 0, KEY_F6), \
-        KEY(4, 1, KEY_F7), \
-        KEY(4, 2, KEY_F8), \
-        KEY(4, 3, KEY_F9), \
-        KEY(4, 4, KEY_F10), \
-        KEY(4, 5, KEY_NUMLOCK), \
-        KEY(5, 0, KEY_KP2), \
-        KEY(5, 1, KEY_KP3), \
-        KEY(5, 2, KEY_KP0), \
-        KEY(5, 3, KEY_KPDOT), \
-        KEY(5, 4, KEY_RO), \
-        KEY(5, 5, KEY_ZENKAKUHANKAKU), \
-}
-#define KEYPAD_9x9     0
-#define KEYPAD_6x6     1
-#define KEYPAD_2x2     2
-/**
- * struct kbd_platform_data - spear keyboard platform data
- * keymap: pointer to keymap data (table and size)
- * rep: enables key autorepeat
- * mode: choose keyboard support(9x9, 6x6, 2x2)
- * suspended_rate: rate at which keyboard would operate in suspended mode
- *
- * This structure is supposed to be used by platform code to supply
- * keymaps to drivers that implement keyboards.
- */
-struct kbd_platform_data {
-        const struct matrix_keymap_data *keymap;
-        bool rep;
-        unsigned int mode;
-        unsigned int suspended_rate;
-};
-#endif /* __PLAT_KEYBOARD_H */
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index 8d5c10a5084d..2a4ae8a6a081 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -16,8 +16,10 @@ config PLAT_VERSATILE_FPGA_IRQ_NR
       depends on PLAT_VERSATILE_FPGA_IRQ
 config PLAT_VERSATILE_LEDS
-        def_bool y if LEDS_CLASS
+        def_bool y if NEW_LEDS
        depends on ARCH_REALVIEW || ARCH_VERSATILE
+        select LEDS_CLASS
+        select LEDS_TRIGGER
 config PLAT_VERSATILE_SCHED_CLOCK
        def_bool y
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 272769a8a7d6..74cfd94cbf80 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,3 +1,5 @@
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
 obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c
index 6e70d03824a1..091ae1030045 100644
--- a/arch/arm/plat-versatile/fpga-irq.c
+++ b/arch/arm/plat-versatile/fpga-irq.c
@@ -5,6 +5,8 @@
 #include <linux/io.h>
 #include <linux/irqdomain.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
@@ -14,11 +16,17 @@
 #define IRQ_RAW_STATUS          0x04
 #define IRQ_ENABLE_SET          0x08
 #define IRQ_ENABLE_CLEAR        0x0c
+#define INT_SOFT_SET            0x10
+#define INT_SOFT_CLEAR          0x14
+#define FIQ_STATUS              0x20
+#define FIQ_RAW_STATUS          0x24
+#define FIQ_ENABLE              0x28
+#define FIQ_ENABLE_SET          0x28
+#define FIQ_ENABLE_CLEAR        0x2C
 /**
 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
 * @base: memory offset in virtual memory
- * @irq_start: first IRQ number handled by this instance
 * @chip: chip container for this instance
 * @domain: IRQ domain for this instance
 * @valid: mask for valid IRQs on this controller
@@ -26,7 +34,6 @@
 */
 struct fpga_irq_data {
        void __iomem *base;
-        unsigned int irq_start;
        struct irq_chip chip;
        u32 valid;
        struct irq_domain *domain;
@@ -125,34 +132,79 @@ static struct irq_domain_ops fpga_irqdomain_ops = {
        .xlate = irq_domain_xlate_onetwocell,
 };
-void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
+static __init struct fpga_irq_data *
-                          int parent_irq, u32 valid, struct device_node *node)
+fpga_irq_prep_struct(void __iomem *base, const char *name, u32 valid) {
-{
        struct fpga_irq_data *f;
        if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
                printk(KERN_ERR "%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__);
-                return;
+                return NULL;
        }
        f = &fpga_irq_devices[fpga_irq_id];
        f->base = base;
-        f->irq_start = irq_start;
        f->chip.name = name;
        f->chip.irq_ack = fpga_irq_mask;
        f->chip.irq_mask = fpga_irq_mask;
        f->chip.irq_unmask = fpga_irq_unmask;
        f->valid = valid;
+        fpga_irq_id++;
+        return f;
+}
+void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
+                          int parent_irq, u32 valid, struct device_node *node)
+{
+        struct fpga_irq_data *f;
+        f = fpga_irq_prep_struct(base, name, valid);
+        if (!f)
+                return;
        if (parent_irq != -1) {
                irq_set_handler_data(parent_irq, f);
                irq_set_chained_handler(parent_irq, fpga_irq_handle);
        }
-        f->domain = irq_domain_add_legacy(node, fls(valid), f->irq_start, 0,
+        f->domain = irq_domain_add_legacy(node, fls(valid), irq_start, 0,
                                          &fpga_irqdomain_ops, f);
        pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
                fpga_irq_id, name, base, f->used_irqs);
+}
-        fpga_irq_id++;
+#ifdef CONFIG_OF
+int __init fpga_irq_of_init(struct device_node *node,
+                            struct device_node *parent)
+{
+        struct fpga_irq_data *f;
+        void __iomem *base;
+        u32 clear_mask;
+        u32 valid_mask;
+        if (WARN_ON(!node))
+                return -ENODEV;
+        base = of_iomap(node, 0);
+        WARN(!base, "unable to map fpga irq registers\n");
+        if (of_property_read_u32(node, "clear-mask", &clear_mask))
+                clear_mask = 0;
+        if (of_property_read_u32(node, "valid-mask", &valid_mask))
+                valid_mask = 0;
+        f = fpga_irq_prep_struct(base, node->name, valid_mask);
+        if (!f)
+                return -ENOMEM;
+        writel(clear_mask, base + IRQ_ENABLE_CLEAR);
+        writel(clear_mask, base + FIQ_ENABLE_CLEAR);
+        f->domain = irq_domain_add_linear(node, fls(valid_mask), &fpga_irqdomain_ops, f);
+        f->used_irqs = hweight32(valid_mask);
+        pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
+                fpga_irq_id, node->name, base, f->used_irqs);
+        return 0;
 }
+#endif
diff --git a/arch/arm/plat-versatile/include/plat/fpga-irq.h b/arch/arm/plat-versatile/include/plat/fpga-irq.h
index 91bcfb67551d..1fac9651d3ca 100644
--- a/arch/arm/plat-versatile/include/plat/fpga-irq.h
+++ b/arch/arm/plat-versatile/include/plat/fpga-irq.h
@@ -7,5 +7,7 @@ struct pt_regs;
 void fpga_handle_irq(struct pt_regs *regs);
 void fpga_irq_init(void __iomem *, const char *, int, int, u32,
                struct device_node *node);
+int fpga_irq_of_init(struct device_node *node,
+                     struct device_node *parent);
 #endif
diff --git a/arch/arm/plat-versatile/include/plat/platsmp.h b/arch/arm/plat-versatile/include/plat/platsmp.h
new file mode 100644
index 000000000000..50fb830192e0
--- /dev/null
+++ b/arch/arm/plat-versatile/include/plat/platsmp.h
@@ -0,0 +1,14 @@
+/*
+ *  linux/arch/arm/plat-versatile/include/plat/platsmp.h
+ *
+ *  Copyright (C) 2011 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+extern void versatile_secondary_startup(void);
+extern void versatile_secondary_init(unsigned int cpu);
+extern int  versatile_boot_secondary(unsigned int cpu, struct task_struct *idle);
diff --git a/arch/arm/plat-versatile/leds.c b/arch/arm/plat-versatile/leds.c
index 3169fa555ea6..d2490d00b46c 100644
--- a/arch/arm/plat-versatile/leds.c
+++ b/arch/arm/plat-versatile/leds.c
@@ -37,10 +37,10 @@ static const struct {
 } versatile_leds[] = {
        { "versatile:0", "heartbeat", },
        { "versatile:1", "mmc0", },
-        { "versatile:2", },
+        { "versatile:2", "cpu0" },
-        { "versatile:3", },
+        { "versatile:3", "cpu1" },
-        { "versatile:4", },
+        { "versatile:4", "cpu2" },
-        { "versatile:5", },
+        { "versatile:5", "cpu3" },
        { "versatile:6", },
        { "versatile:7", },
 };
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index d7c5c171f5aa..04ca4937d8ca 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -20,12 +20,6 @@
 #include <asm/hardware/gic.h>
 /*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-volatile int __cpuinitdata pen_release = -1;
-/*
 * Write pen_release in a way that is guaranteed to be visible to all
 * observers, irrespective of whether they're taking part in coherency
 * or not.  This is necessary for the hotplug code to work reliably.
@@ -40,7 +34,7 @@ static void __cpuinit write_pen_release(int val)
 static DEFINE_SPINLOCK(boot_lock);
-void __cpuinit platform_secondary_init(unsigned int cpu)
+void __cpuinit versatile_secondary_init(unsigned int cpu)
 {
        /*
         * if any interrupts are already enabled for the primary
@@ -62,7 +56,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
        spin_unlock(&boot_lock);
 }
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        unsigned long timeout;
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 2997e56ce0dd..831e1fdfdb2f 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -66,7 +66,6 @@ iq80321			ARCH_IQ80321		IQ80321			169
 ks8695                  ARCH_KS8695             KS8695                  180
 karo                    ARCH_KARO               KARO                    190
 smdk2410                ARCH_SMDK2410           SMDK2410                193
-ceiva                   ARCH_CEIVA              CEIVA                   200
 voiceblue               MACH_VOICEBLUE          VOICEBLUE               218
 h5400                   ARCH_H5400              H5400                   220
 omap_innovator          MACH_OMAP_INNOVATOR     OMAP_INNOVATOR          234
@@ -158,7 +157,6 @@ edb9315a		MACH_EDB9315A		EDB9315A		772
 stargate2               MACH_STARGATE2          STARGATE2               774
 intelmote2              MACH_INTELMOTE2         INTELMOTE2              775
 trizeps4                MACH_TRIZEPS4           TRIZEPS4                776
-pnx4008                 MACH_PNX4008            PNX4008                 782
 cpuat91                 MACH_CPUAT91            CPUAT91                 787
 iq81340sc               MACH_IQ81340SC          IQ81340SC               799
 iq81340mc               MACH_IQ81340MC          IQ81340MC               801
diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
new file mode 100644
index 000000000000..43841033afd3
--- /dev/null
+++ b/arch/arm/xen/Makefile
@@ -0,0 +1 @@
+obj-y           := enlighten.o hypercall.o grant-table.o
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
new file mode 100644
index 000000000000..59bcb96ac369
--- /dev/null
+++ b/arch/arm/xen/enlighten.c
@@ -0,0 +1,168 @@
+#include <xen/xen.h>
+#include <xen/events.h>
+#include <xen/grant_table.h>
+#include <xen/hvm.h>
+#include <xen/interface/xen.h>
+#include <xen/interface/memory.h>
+#include <xen/interface/hvm/params.h>
+#include <xen/features.h>
+#include <xen/platform_pci.h>
+#include <xen/xenbus.h>
+#include <asm/xen/hypervisor.h>
+#include <asm/xen/hypercall.h>
+#include <linux/interrupt.h>
+#include <linux/irqreturn.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+struct start_info _xen_start_info;
+struct start_info *xen_start_info = &_xen_start_info;
+EXPORT_SYMBOL_GPL(xen_start_info);
+enum xen_domain_type xen_domain_type = XEN_NATIVE;
+EXPORT_SYMBOL_GPL(xen_domain_type);
+struct shared_info xen_dummy_shared_info;
+struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info;
+DEFINE_PER_CPU(struct vcpu_info *, xen_vcpu);
+/* TODO: to be removed */
+__read_mostly int xen_have_vector_callback;
+EXPORT_SYMBOL_GPL(xen_have_vector_callback);
+int xen_platform_pci_unplug = XEN_UNPLUG_ALL;
+EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
+static __read_mostly int xen_events_irq = -1;
+int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
+                               unsigned long addr,
+                               unsigned long mfn, int nr,
+                               pgprot_t prot, unsigned domid)
+{
+        return -ENOSYS;
+}
+EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
+/*
+ * see Documentation/devicetree/bindings/arm/xen.txt for the
+ * documentation of the Xen Device Tree format.
+ */
+#define GRANT_TABLE_PHYSADDR 0
+static int __init xen_guest_init(void)
+{
+        struct xen_add_to_physmap xatp;
+        static struct shared_info *shared_info_page = 0;
+        struct device_node *node;
+        int len;
+        const char *s = NULL;
+        const char *version = NULL;
+        const char *xen_prefix = "xen,xen-";
+        struct resource res;
+        node = of_find_compatible_node(NULL, NULL, "xen,xen");
+        if (!node) {
+                pr_debug("No Xen support\n");
+                return 0;
+        }
+        s = of_get_property(node, "compatible", &len);
+        if (strlen(xen_prefix) + 3  < len &&
+                        !strncmp(xen_prefix, s, strlen(xen_prefix)))
+                version = s + strlen(xen_prefix);
+        if (version == NULL) {
+                pr_debug("Xen version not found\n");
+                return 0;
+        }
+        if (of_address_to_resource(node, GRANT_TABLE_PHYSADDR, &res))
+                return 0;
+        xen_hvm_resume_frames = res.start >> PAGE_SHIFT;
+        xen_events_irq = irq_of_parse_and_map(node, 0);
+        pr_info("Xen %s support found, events_irq=%d gnttab_frame_pfn=%lx\n",
+                        version, xen_events_irq, xen_hvm_resume_frames);
+        xen_domain_type = XEN_HVM_DOMAIN;
+        xen_setup_features();
+        if (xen_feature(XENFEAT_dom0))
+                xen_start_info->flags |= SIF_INITDOMAIN|SIF_PRIVILEGED;
+        else
+                xen_start_info->flags &= ~(SIF_INITDOMAIN|SIF_PRIVILEGED);
+        if (!shared_info_page)
+                shared_info_page = (struct shared_info *)
+                        get_zeroed_page(GFP_KERNEL);
+        if (!shared_info_page) {
+                pr_err("not enough memory\n");
+                return -ENOMEM;
+        }
+        xatp.domid = DOMID_SELF;
+        xatp.idx = 0;
+        xatp.space = XENMAPSPACE_shared_info;
+        xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
+        if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
+                BUG();
+        HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
+        /* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
+         * page, we use it in the event channel upcall and in some pvclock
+         * related functions. We don't need the vcpu_info placement
+         * optimizations because we don't use any pv_mmu or pv_irq op on
+         * HVM.
+         * The shared info contains exactly 1 CPU (the boot CPU). The guest
+         * is required to use VCPUOP_register_vcpu_info to place vcpu info
+         * for secondary CPUs as they are brought up. */
+        per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
+        gnttab_init();
+        if (!xen_initial_domain())
+                xenbus_probe(NULL);
+        return 0;
+}
+core_initcall(xen_guest_init);
+static irqreturn_t xen_arm_callback(int irq, void *arg)
+{
+        xen_hvm_evtchn_do_upcall();
+        return IRQ_HANDLED;
+}
+static int __init xen_init_events(void)
+{
+        if (!xen_domain() || xen_events_irq < 0)
+                return -ENODEV;
+        xen_init_IRQ();
+        if (request_percpu_irq(xen_events_irq, xen_arm_callback,
+                        "events", xen_vcpu)) {
+                pr_err("Error requesting IRQ %d\n", xen_events_irq);
+                return -EINVAL;
+        }
+        enable_percpu_irq(xen_events_irq, 0);
+        return 0;
+}
+postcore_initcall(xen_init_events);
+/* XXX: only until balloon is properly working */
+int alloc_xenballooned_pages(int nr_pages, struct page **pages, bool highmem)
+{
+        *pages = alloc_pages(highmem ? GFP_HIGHUSER : GFP_KERNEL,
+                        get_order(nr_pages));
+        if (*pages == NULL)
+                return -ENOMEM;
+        return 0;
+}
+EXPORT_SYMBOL_GPL(alloc_xenballooned_pages);
+void free_xenballooned_pages(int nr_pages, struct page **pages)
+{
+        kfree(*pages);
+        *pages = NULL;
+}
+EXPORT_SYMBOL_GPL(free_xenballooned_pages);
diff --git a/arch/arm/xen/grant-table.c b/arch/arm/xen/grant-table.c
new file mode 100644
index 000000000000..dbd1330c0196
--- /dev/null
+++ b/arch/arm/xen/grant-table.c
@@ -0,0 +1,53 @@
+/******************************************************************************
+ * grant_table.c
+ * ARM specific part
+ *
+ * Granting foreign access to our memory reservation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#include <xen/interface/xen.h>
+#include <xen/page.h>
+#include <xen/grant_table.h>
+int arch_gnttab_map_shared(unsigned long *frames, unsigned long nr_gframes,
+                           unsigned long max_nr_gframes,
+                           void **__shared)
+{
+        return -ENOSYS;
+}
+void arch_gnttab_unmap(void *shared, unsigned long nr_gframes)
+{
+        return;
+}
+int arch_gnttab_map_status(uint64_t *frames, unsigned long nr_gframes,
+                           unsigned long max_nr_gframes,
+                           grant_status_t **__shared)
+{
+        return -ENOSYS;
+}
diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S
new file mode 100644
index 000000000000..074f5ed101b9
--- /dev/null
+++ b/arch/arm/xen/hypercall.S
@@ -0,0 +1,106 @@
+/******************************************************************************
+ * hypercall.S
+ *
+ * Xen hypercall wrappers
+ *
+ * Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+/*
+ * The Xen hypercall calling convention is very similar to the ARM
+ * procedure calling convention: the first paramter is passed in r0, the
+ * second in r1, the third in r2 and the fourth in r3. Considering that
+ * Xen hypercalls have 5 arguments at most, the fifth paramter is passed
+ * in r4, differently from the procedure calling convention of using the
+ * stack for that case.
+ *
+ * The hypercall number is passed in r12.
+ *
+ * The return value is in r0.
+ *
+ * The hvc ISS is required to be 0xEA1, that is the Xen specific ARM
+ * hypercall tag.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <xen/interface/xen.h>
+/* HVC 0xEA1 */
+#ifdef CONFIG_THUMB2_KERNEL
+#define xen_hvc .word 0xf7e08ea1
+#else
+#define xen_hvc .word 0xe140ea71
+#endif
+#define HYPERCALL_SIMPLE(hypercall)             \
+ENTRY(HYPERVISOR_##hypercall)                   \
+        mov r12, #__HYPERVISOR_##hypercall;     \
+        xen_hvc;                                                        \
+        mov pc, lr;                                                     \
+ENDPROC(HYPERVISOR_##hypercall)
+#define HYPERCALL0 HYPERCALL_SIMPLE
+#define HYPERCALL1 HYPERCALL_SIMPLE
+#define HYPERCALL2 HYPERCALL_SIMPLE
+#define HYPERCALL3 HYPERCALL_SIMPLE
+#define HYPERCALL4 HYPERCALL_SIMPLE
+#define HYPERCALL5(hypercall)                   \
+ENTRY(HYPERVISOR_##hypercall)                   \
+        stmdb sp!, {r4}                                         \
+        ldr r4, [sp, #4]                                        \
+        mov r12, #__HYPERVISOR_##hypercall;     \
+        xen_hvc                                                         \
+        ldm sp!, {r4}                                           \
+        mov pc, lr                                                      \
+ENDPROC(HYPERVISOR_##hypercall)
+                .text
+HYPERCALL2(xen_version);
+HYPERCALL3(console_io);
+HYPERCALL3(grant_table_op);
+HYPERCALL2(sched_op);
+HYPERCALL2(event_channel_op);
+HYPERCALL2(hvm_op);
+HYPERCALL2(memory_op);
+HYPERCALL2(physdev_op);
+ENTRY(privcmd_call)
+        stmdb sp!, {r4}
+        mov r12, r0
+        mov r0, r1
+        mov r1, r2
+        mov r2, r3
+        ldr r3, [sp, #8]
+        ldr r4, [sp, #4]
+        xen_hvc
+        ldm sp!, {r4}
+        mov pc, lr
+ENDPROC(privcmd_call);