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-rw-r--r--arch/arm/boot/dts/am437x-sk-evm.dts4
-rw-r--r--arch/arm/boot/dts/am57xx-beagle-x15.dts11
-rw-r--r--arch/arm/boot/dts/armada-375.dtsi2
-rw-r--r--arch/arm/boot/dts/armada-38x.dtsi2
-rw-r--r--arch/arm/boot/dts/armada-39x.dtsi2
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts4
-rw-r--r--arch/arm/boot/dts/dove-cubox.dts1
-rw-r--r--arch/arm/boot/dts/dra7.dtsi10
-rw-r--r--arch/arm/boot/dts/exynos4412-odroid-common.dtsi3
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts1
-rw-r--r--arch/arm/boot/dts/exynos5420-peach-pit.dts1
-rw-r--r--arch/arm/boot/dts/exynos5420-trip-points.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi1
-rw-r--r--arch/arm/boot/dts/exynos5440-trip-points.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5800-peach-pi.dts1
-rw-r--r--arch/arm/boot/dts/imx23-olinuxino.dts4
-rw-r--r--arch/arm/boot/dts/imx25.dtsi1
-rw-r--r--arch/arm/boot/dts/imx28.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi1
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts4
-rw-r--r--arch/arm/boot/dts/omap3.dtsi2
-rw-r--r--arch/arm/boot/dts/omap5.dtsi2
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts2
-rw-r--r--arch/arm/boot/dts/ste-dbx5x0.dtsi17
-rw-r--r--arch/arm/boot/dts/ste-href.dtsi15
-rw-r--r--arch/arm/boot/dts/ste-snowball.dts13
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi8
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts1
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca9.dts11
-rw-r--r--arch/arm/configs/multi_v7_defconfig3
-rw-r--r--arch/arm/configs/omap2plus_defconfig2
-rw-r--r--arch/arm/include/asm/dma-iommu.h2
-rw-r--r--arch/arm/include/asm/xen/page.h1
-rw-r--r--arch/arm/kernel/perf_event_cpu.c9
-rw-r--r--arch/arm/mach-exynos/common.h2
-rw-r--r--arch/arm/mach-exynos/exynos.c27
-rw-r--r--arch/arm/mach-exynos/platsmp.c39
-rw-r--r--arch/arm/mach-exynos/pm_domains.c4
-rw-r--r--arch/arm/mach-exynos/suspend.c7
-rw-r--r--arch/arm/mach-gemini/common.h4
-rw-r--r--arch/arm/mach-gemini/reset.c4
-rw-r--r--arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c68
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_43xx_data.c70
-rw-r--r--arch/arm/mach-omap2/prcm43xx.h3
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h1
-rw-r--r--arch/arm/mach-omap2/prm-regbits-44xx.h1
-rw-r--r--arch/arm/mach-omap2/prminst44xx.c20
-rw-r--r--arch/arm/mach-omap2/timer.c13
-rw-r--r--arch/arm/mach-omap2/vc.c12
-rw-r--r--arch/arm/mach-omap2/vc.h2
-rw-r--r--arch/arm/mach-omap2/vc3xxx_data.c1
-rw-r--r--arch/arm/mach-omap2/vc44xx_data.c1
-rw-r--r--arch/arm/mach-pxa/Kconfig9
-rw-r--r--arch/arm/mach-pxa/Makefile1
-rw-r--r--arch/arm/mach-pxa/include/mach/lubbock.h7
-rw-r--r--arch/arm/mach-pxa/include/mach/mainstone.h6
-rw-r--r--arch/arm/mach-pxa/lubbock.c108
-rw-r--r--arch/arm/mach-pxa/mainstone.c115
-rw-r--r--arch/arm/mach-pxa/pxa_cplds_irqs.c200
-rw-r--r--arch/arm/mach-rockchip/pm.c7
-rw-r--r--arch/arm/mach-rockchip/pm.h4
-rw-r--r--arch/arm/mach-rockchip/rockchip.c19
-rw-r--r--arch/arm/mm/dma-mapping.c13
-rw-r--r--arch/arm/mm/proc-arm1020.S2
-rw-r--r--arch/arm/mm/proc-arm1020e.S2
-rw-r--r--arch/arm/mm/proc-arm925.S3
-rw-r--r--arch/arm/mm/proc-feroceon.S1
-rw-r--r--arch/arm/net/bpf_jit_32.c42
-rw-r--r--arch/arm/xen/mm.c15
71 files changed, 621 insertions, 363 deletions
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 8ae29c955c11..c17097d2c167 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -49,7 +49,7 @@
49 pinctrl-0 = <&matrix_keypad_pins>; 49 pinctrl-0 = <&matrix_keypad_pins>;
50 50
51 debounce-delay-ms = <5>; 51 debounce-delay-ms = <5>;
52 col-scan-delay-us = <1500>; 52 col-scan-delay-us = <5>;
53 53
54 row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ 54 row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */
55 &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ 55 &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */
@@ -473,7 +473,7 @@
473 interrupt-parent = <&gpio0>; 473 interrupt-parent = <&gpio0>;
474 interrupts = <31 0>; 474 interrupts = <31 0>;
475 475
476 wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 476 reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
477 477
478 touchscreen-size-x = <480>; 478 touchscreen-size-x = <480>;
479 touchscreen-size-y = <272>; 479 touchscreen-size-y = <272>;
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 15f198e4864d..7128fad991ac 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -18,6 +18,7 @@
18 aliases { 18 aliases {
19 rtc0 = &mcp_rtc; 19 rtc0 = &mcp_rtc;
20 rtc1 = &tps659038_rtc; 20 rtc1 = &tps659038_rtc;
21 rtc2 = &rtc;
21 }; 22 };
22 23
23 memory { 24 memory {
@@ -83,7 +84,7 @@
83 gpio_fan: gpio_fan { 84 gpio_fan: gpio_fan {
84 /* Based on 5v 500mA AFB02505HHB */ 85 /* Based on 5v 500mA AFB02505HHB */
85 compatible = "gpio-fan"; 86 compatible = "gpio-fan";
86 gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>; 87 gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>;
87 gpio-fan,speed-map = <0 0>, 88 gpio-fan,speed-map = <0 0>,
88 <13000 1>; 89 <13000 1>;
89 #cooling-cells = <2>; 90 #cooling-cells = <2>;
@@ -130,8 +131,8 @@
130 131
131 uart3_pins_default: uart3_pins_default { 132 uart3_pins_default: uart3_pins_default {
132 pinctrl-single,pins = < 133 pinctrl-single,pins = <
133 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */ 134 0x3f8 (PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */
134 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */ 135 0x3fc (PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */
135 >; 136 >;
136 }; 137 };
137 138
@@ -455,7 +456,7 @@
455 mcp_rtc: rtc@6f { 456 mcp_rtc: rtc@6f {
456 compatible = "microchip,mcp7941x"; 457 compatible = "microchip,mcp7941x";
457 reg = <0x6f>; 458 reg = <0x6f>;
458 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */ 459 interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; /* IRQ_SYS_1N */
459 460
460 pinctrl-names = "default"; 461 pinctrl-names = "default";
461 pinctrl-0 = <&mcp79410_pins_default>; 462 pinctrl-0 = <&mcp79410_pins_default>;
@@ -478,7 +479,7 @@
478&uart3 { 479&uart3 {
479 status = "okay"; 480 status = "okay";
480 interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 481 interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
481 <&dra7_pmx_core 0x248>; 482 <&dra7_pmx_core 0x3f8>;
482 483
483 pinctrl-names = "default"; 484 pinctrl-names = "default";
484 pinctrl-0 = <&uart3_pins_default>; 485 pinctrl-0 = <&uart3_pins_default>;
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index c675257f2377..f076ff856d8b 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -69,7 +69,7 @@
69 mainpll: mainpll { 69 mainpll: mainpll {
70 compatible = "fixed-clock"; 70 compatible = "fixed-clock";
71 #clock-cells = <0>; 71 #clock-cells = <0>;
72 clock-frequency = <2000000000>; 72 clock-frequency = <1000000000>;
73 }; 73 };
74 /* 25 MHz reference crystal */ 74 /* 25 MHz reference crystal */
75 refclk: oscillator { 75 refclk: oscillator {
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index ed2dd8ba4080..218a2acd36e5 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -585,7 +585,7 @@
585 mainpll: mainpll { 585 mainpll: mainpll {
586 compatible = "fixed-clock"; 586 compatible = "fixed-clock";
587 #clock-cells = <0>; 587 #clock-cells = <0>;
588 clock-frequency = <2000000000>; 588 clock-frequency = <1000000000>;
589 }; 589 };
590 590
591 /* 25 MHz reference crystal */ 591 /* 25 MHz reference crystal */
diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
index 0e85fc15ceda..ecd1318109ba 100644
--- a/arch/arm/boot/dts/armada-39x.dtsi
+++ b/arch/arm/boot/dts/armada-39x.dtsi
@@ -502,7 +502,7 @@
502 mainpll: mainpll { 502 mainpll: mainpll {
503 compatible = "fixed-clock"; 503 compatible = "fixed-clock";
504 #clock-cells = <0>; 504 #clock-cells = <0>;
505 clock-frequency = <2000000000>; 505 clock-frequency = <1000000000>;
506 }; 506 };
507 }; 507 };
508}; 508};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index e3b08fb959e5..990e8a2100f0 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -105,6 +105,10 @@
105 }; 105 };
106 106
107 internal-regs { 107 internal-regs {
108 rtc@10300 {
109 /* No crystal connected to the internal RTC */
110 status = "disabled";
111 };
108 serial@12000 { 112 serial@12000 {
109 status = "okay"; 113 status = "okay";
110 }; 114 };
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index aae7efc09b0b..e6fa251e17b9 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -87,6 +87,7 @@
87 87
88 /* connect xtal input to 25MHz reference */ 88 /* connect xtal input to 25MHz reference */
89 clocks = <&ref25>; 89 clocks = <&ref25>;
90 clock-names = "xtal";
90 91
91 /* connect xtal input as source of pll0 and pll1 */ 92 /* connect xtal input as source of pll0 and pll1 */
92 silabs,pll-source = <0 0>, <1 0>; 93 silabs,pll-source = <0 0>, <1 0>;
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5332b57b4950..f03a091cd076 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -911,7 +911,7 @@
911 ti,clock-cycles = <16>; 911 ti,clock-cycles = <16>;
912 912
913 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 913 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
914 <0x4ae06014 0x4>, <0x4a003b20 0x8>, 914 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
915 <0x4ae0c158 0x4>; 915 <0x4ae0c158 0x4>;
916 reg-names = "setup-address", "control-address", 916 reg-names = "setup-address", "control-address",
917 "int-address", "efuse-address", 917 "int-address", "efuse-address",
@@ -944,7 +944,7 @@
944 ti,clock-cycles = <16>; 944 ti,clock-cycles = <16>;
945 945
946 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 946 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
947 <0x4ae06010 0x4>, <0x4a0025cc 0x8>, 947 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
948 <0x4a002470 0x4>; 948 <0x4a002470 0x4>;
949 reg-names = "setup-address", "control-address", 949 reg-names = "setup-address", "control-address",
950 "int-address", "efuse-address", 950 "int-address", "efuse-address",
@@ -977,7 +977,7 @@
977 ti,clock-cycles = <16>; 977 ti,clock-cycles = <16>;
978 978
979 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 979 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
980 <0x4ae06010 0x4>, <0x4a0025e0 0x8>, 980 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
981 <0x4a00246c 0x4>; 981 <0x4a00246c 0x4>;
982 reg-names = "setup-address", "control-address", 982 reg-names = "setup-address", "control-address",
983 "int-address", "efuse-address", 983 "int-address", "efuse-address",
@@ -1010,7 +1010,7 @@
1010 ti,clock-cycles = <16>; 1010 ti,clock-cycles = <16>;
1011 1011
1012 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 1012 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1013 <0x4ae06010 0x4>, <0x4a003b08 0x8>, 1013 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1014 <0x4ae0c154 0x4>; 1014 <0x4ae0c154 0x4>;
1015 reg-names = "setup-address", "control-address", 1015 reg-names = "setup-address", "control-address",
1016 "int-address", "efuse-address", 1016 "int-address", "efuse-address",
@@ -1203,7 +1203,7 @@
1203 status = "disabled"; 1203 status = "disabled";
1204 }; 1204 };
1205 1205
1206 rtc@48838000 { 1206 rtc: rtc@48838000 {
1207 compatible = "ti,am3352-rtc"; 1207 compatible = "ti,am3352-rtc";
1208 reg = <0x48838000 0x100>; 1208 reg = <0x48838000 0x100>;
1209 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1209 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 8de12af7c276..d6b49e5b32e9 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -9,6 +9,7 @@
9 9
10#include <dt-bindings/sound/samsung-i2s.h> 10#include <dt-bindings/sound/samsung-i2s.h>
11#include <dt-bindings/input/input.h> 11#include <dt-bindings/input/input.h>
12#include <dt-bindings/clock/maxim,max77686.h>
12#include "exynos4412.dtsi" 13#include "exynos4412.dtsi"
13 14
14/ { 15/ {
@@ -105,6 +106,8 @@
105 106
106 rtc@10070000 { 107 rtc@10070000 {
107 status = "okay"; 108 status = "okay";
109 clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
110 clock-names = "rtc", "rtc_src";
108 }; 111 };
109 112
110 g2d@10800000 { 113 g2d@10800000 {
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 2657e842e5a5..1eca97ee4bd6 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -567,6 +567,7 @@
567 num-slots = <1>; 567 num-slots = <1>;
568 broken-cd; 568 broken-cd;
569 cap-sdio-irq; 569 cap-sdio-irq;
570 keep-power-in-suspend;
570 card-detect-delay = <200>; 571 card-detect-delay = <200>;
571 samsung,dw-mshc-ciu-div = <3>; 572 samsung,dw-mshc-ciu-div = <3>;
572 samsung,dw-mshc-sdr-timing = <2 3>; 573 samsung,dw-mshc-sdr-timing = <2 3>;
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 0788d08fb43e..146e71118a72 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -711,6 +711,7 @@
711 num-slots = <1>; 711 num-slots = <1>;
712 broken-cd; 712 broken-cd;
713 cap-sdio-irq; 713 cap-sdio-irq;
714 keep-power-in-suspend;
714 card-detect-delay = <200>; 715 card-detect-delay = <200>;
715 clock-frequency = <400000000>; 716 clock-frequency = <400000000>;
716 samsung,dw-mshc-ciu-div = <1>; 717 samsung,dw-mshc-ciu-div = <1>;
diff --git a/arch/arm/boot/dts/exynos5420-trip-points.dtsi b/arch/arm/boot/dts/exynos5420-trip-points.dtsi
index 5d31fc140823..2180a0152c9b 100644
--- a/arch/arm/boot/dts/exynos5420-trip-points.dtsi
+++ b/arch/arm/boot/dts/exynos5420-trip-points.dtsi
@@ -28,7 +28,7 @@ trips {
28 type = "active"; 28 type = "active";
29 }; 29 };
30 cpu-crit-0 { 30 cpu-crit-0 {
31 temperature = <1200000>; /* millicelsius */ 31 temperature = <120000>; /* millicelsius */
32 hysteresis = <0>; /* millicelsius */ 32 hysteresis = <0>; /* millicelsius */
33 type = "critical"; 33 type = "critical";
34 }; 34 };
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index f67b23f303c3..45317538bbae 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -536,6 +536,7 @@
536 clock-names = "dp"; 536 clock-names = "dp";
537 phys = <&dp_phy>; 537 phys = <&dp_phy>;
538 phy-names = "dp"; 538 phy-names = "dp";
539 power-domains = <&disp_pd>;
539 }; 540 };
540 541
541 mipi_phy: video-phy@10040714 { 542 mipi_phy: video-phy@10040714 {
diff --git a/arch/arm/boot/dts/exynos5440-trip-points.dtsi b/arch/arm/boot/dts/exynos5440-trip-points.dtsi
index 48adfa8f4300..356e963edf11 100644
--- a/arch/arm/boot/dts/exynos5440-trip-points.dtsi
+++ b/arch/arm/boot/dts/exynos5440-trip-points.dtsi
@@ -18,7 +18,7 @@ trips {
18 type = "active"; 18 type = "active";
19 }; 19 };
20 cpu-crit-0 { 20 cpu-crit-0 {
21 temperature = <1050000>; /* millicelsius */ 21 temperature = <105000>; /* millicelsius */
22 hysteresis = <0>; /* millicelsius */ 22 hysteresis = <0>; /* millicelsius */
23 type = "critical"; 23 type = "critical";
24 }; 24 };
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 412f41d62686..02eb8b15374f 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -674,6 +674,7 @@
674 num-slots = <1>; 674 num-slots = <1>;
675 broken-cd; 675 broken-cd;
676 cap-sdio-irq; 676 cap-sdio-irq;
677 keep-power-in-suspend;
677 card-detect-delay = <200>; 678 card-detect-delay = <200>;
678 clock-frequency = <400000000>; 679 clock-frequency = <400000000>;
679 samsung,dw-mshc-ciu-div = <1>; 680 samsung,dw-mshc-ciu-div = <1>;
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index 7e6eef2488e8..82045398bf1f 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -12,6 +12,7 @@
12 */ 12 */
13 13
14/dts-v1/; 14/dts-v1/;
15#include <dt-bindings/gpio/gpio.h>
15#include "imx23.dtsi" 16#include "imx23.dtsi"
16 17
17/ { 18/ {
@@ -93,6 +94,7 @@
93 94
94 ahb@80080000 { 95 ahb@80080000 {
95 usb0: usb@80080000 { 96 usb0: usb@80080000 {
97 dr_mode = "host";
96 vbus-supply = <&reg_usb0_vbus>; 98 vbus-supply = <&reg_usb0_vbus>;
97 status = "okay"; 99 status = "okay";
98 }; 100 };
@@ -122,7 +124,7 @@
122 124
123 user { 125 user {
124 label = "green"; 126 label = "green";
125 gpios = <&gpio2 1 1>; 127 gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
126 }; 128 };
127 }; 129 };
128}; 130};
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index e4d3aecc4ed2..677f81d9dcd5 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -428,6 +428,7 @@
428 428
429 pwm4: pwm@53fc8000 { 429 pwm4: pwm@53fc8000 {
430 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; 430 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
431 #pwm-cells = <2>;
431 reg = <0x53fc8000 0x4000>; 432 reg = <0x53fc8000 0x4000>;
432 clocks = <&clks 108>, <&clks 52>; 433 clocks = <&clks 108>, <&clks 52>;
433 clock-names = "ipg", "per"; 434 clock-names = "ipg", "per";
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 25e25f82fbae..4e073e854742 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -913,7 +913,7 @@
913 80 81 68 69 913 80 81 68 69
914 70 71 72 73 914 70 71 72 73
915 74 75 76 77>; 915 74 75 76 77>;
916 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty", 916 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
917 "saif0", "saif1", "i2c0", "i2c1", 917 "saif0", "saif1", "i2c0", "i2c1",
918 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", 918 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
919 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; 919 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 19cc269a08d4..1ce6133b67f5 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -31,6 +31,7 @@
31 regulator-min-microvolt = <5000000>; 31 regulator-min-microvolt = <5000000>;
32 regulator-max-microvolt = <5000000>; 32 regulator-max-microvolt = <5000000>;
33 gpio = <&gpio4 15 0>; 33 gpio = <&gpio4 15 0>;
34 enable-active-high;
34 }; 35 };
35 36
36 reg_usb_h1_vbus: regulator@1 { 37 reg_usb_h1_vbus: regulator@1 {
@@ -40,6 +41,7 @@
40 regulator-min-microvolt = <5000000>; 41 regulator-min-microvolt = <5000000>;
41 regulator-max-microvolt = <5000000>; 42 regulator-max-microvolt = <5000000>;
42 gpio = <&gpio1 0 0>; 43 gpio = <&gpio1 0 0>;
44 enable-active-high;
43 }; 45 };
44 }; 46 };
45 47
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 46b2fed7c319..3b24b12651b2 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -185,7 +185,6 @@
185&i2c3 { 185&i2c3 {
186 pinctrl-names = "default"; 186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_i2c3>; 187 pinctrl-0 = <&pinctrl_i2c3>;
188 pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
189 status = "okay"; 188 status = "okay";
190 189
191 max7310_a: gpio@30 { 190 max7310_a: gpio@30 {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index a29315833ecd..5c16145920ea 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -498,6 +498,8 @@
498 DRVDD-supply = <&vmmc2>; 498 DRVDD-supply = <&vmmc2>;
499 IOVDD-supply = <&vio>; 499 IOVDD-supply = <&vio>;
500 DVDD-supply = <&vio>; 500 DVDD-supply = <&vio>;
501
502 ai3x-micbias-vg = <1>;
501 }; 503 };
502 504
503 tlv320aic3x_aux: tlv320aic3x@19 { 505 tlv320aic3x_aux: tlv320aic3x@19 {
@@ -509,6 +511,8 @@
509 DRVDD-supply = <&vmmc2>; 511 DRVDD-supply = <&vmmc2>;
510 IOVDD-supply = <&vio>; 512 IOVDD-supply = <&vio>;
511 DVDD-supply = <&vio>; 513 DVDD-supply = <&vio>;
514
515 ai3x-micbias-vg = <2>;
512 }; 516 };
513 517
514 tsl2563: tsl2563@29 { 518 tsl2563: tsl2563@29 {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index d18a90f5eca3..69a40cfc1f29 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -456,6 +456,7 @@
456 }; 456 };
457 457
458 mmu_isp: mmu@480bd400 { 458 mmu_isp: mmu@480bd400 {
459 #iommu-cells = <0>;
459 compatible = "ti,omap2-iommu"; 460 compatible = "ti,omap2-iommu";
460 reg = <0x480bd400 0x80>; 461 reg = <0x480bd400 0x80>;
461 interrupts = <24>; 462 interrupts = <24>;
@@ -464,6 +465,7 @@
464 }; 465 };
465 466
466 mmu_iva: mmu@5d000000 { 467 mmu_iva: mmu@5d000000 {
468 #iommu-cells = <0>;
467 compatible = "ti,omap2-iommu"; 469 compatible = "ti,omap2-iommu";
468 reg = <0x5d000000 0x80>; 470 reg = <0x5d000000 0x80>;
469 interrupts = <28>; 471 interrupts = <28>;
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index efe5f737f39b..7d24ae0306b5 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -128,7 +128,7 @@
128 * hierarchy. 128 * hierarchy.
129 */ 129 */
130 ocp { 130 ocp {
131 compatible = "ti,omap4-l3-noc", "simple-bus"; 131 compatible = "ti,omap5-l3-noc", "simple-bus";
132 #address-cells = <1>; 132 #address-cells = <1>;
133 #size-cells = <1>; 133 #size-cells = <1>;
134 ranges; 134 ranges;
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 74c3212f1f11..824ddab9c3ad 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -545,7 +545,7 @@
545 compatible = "adi,adv7511w"; 545 compatible = "adi,adv7511w";
546 reg = <0x39>; 546 reg = <0x39>;
547 interrupt-parent = <&gpio3>; 547 interrupt-parent = <&gpio3>;
548 interrupts = <29 IRQ_TYPE_EDGE_FALLING>; 548 interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
549 549
550 adi,input-depth = <8>; 550 adi,input-depth = <8>;
551 adi,input-colorspace = "rgb"; 551 adi,input-colorspace = "rgb";
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index bfd3f1c734b8..2201cd5da3bb 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -1017,23 +1017,6 @@
1017 status = "disabled"; 1017 status = "disabled";
1018 }; 1018 };
1019 1019
1020 vmmci: regulator-gpio {
1021 compatible = "regulator-gpio";
1022
1023 regulator-min-microvolt = <1800000>;
1024 regulator-max-microvolt = <2900000>;
1025 regulator-name = "mmci-reg";
1026 regulator-type = "voltage";
1027
1028 startup-delay-us = <100>;
1029 enable-active-high;
1030
1031 states = <1800000 0x1
1032 2900000 0x0>;
1033
1034 status = "disabled";
1035 };
1036
1037 mcde@a0350000 { 1020 mcde@a0350000 {
1038 compatible = "stericsson,mcde"; 1021 compatible = "stericsson,mcde";
1039 reg = <0xa0350000 0x1000>, /* MCDE */ 1022 reg = <0xa0350000 0x1000>, /* MCDE */
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index bf8f0eddc2c0..744c1e3a744d 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -111,6 +111,21 @@
111 pinctrl-1 = <&i2c3_sleep_mode>; 111 pinctrl-1 = <&i2c3_sleep_mode>;
112 }; 112 };
113 113
114 vmmci: regulator-gpio {
115 compatible = "regulator-gpio";
116
117 regulator-min-microvolt = <1800000>;
118 regulator-max-microvolt = <2900000>;
119 regulator-name = "mmci-reg";
120 regulator-type = "voltage";
121
122 startup-delay-us = <100>;
123 enable-active-high;
124
125 states = <1800000 0x1
126 2900000 0x0>;
127 };
128
114 // External Micro SD slot 129 // External Micro SD slot
115 sdi0_per1@80126000 { 130 sdi0_per1@80126000 {
116 arm,primecell-periphid = <0x10480180>; 131 arm,primecell-periphid = <0x10480180>;
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 206826a855c0..1bc84ebdccaa 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -146,8 +146,21 @@
146 }; 146 };
147 147
148 vmmci: regulator-gpio { 148 vmmci: regulator-gpio {
149 compatible = "regulator-gpio";
150
149 gpios = <&gpio7 4 0x4>; 151 gpios = <&gpio7 4 0x4>;
150 enable-gpio = <&gpio6 25 0x4>; 152 enable-gpio = <&gpio6 25 0x4>;
153
154 regulator-min-microvolt = <1800000>;
155 regulator-max-microvolt = <2900000>;
156 regulator-name = "mmci-reg";
157 regulator-type = "voltage";
158
159 startup-delay-us = <100>;
160 enable-active-high;
161
162 states = <1800000 0x1
163 2900000 0x0>;
151 }; 164 };
152 165
153 // External Micro SD slot 166 // External Micro SD slot
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index cf01c818b8ea..13cc7ca5e031 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -826,7 +826,7 @@
826 <&tegra_car TEGRA124_CLK_PLL_U>, 826 <&tegra_car TEGRA124_CLK_PLL_U>,
827 <&tegra_car TEGRA124_CLK_USBD>; 827 <&tegra_car TEGRA124_CLK_USBD>;
828 clock-names = "reg", "pll_u", "utmi-pads"; 828 clock-names = "reg", "pll_u", "utmi-pads";
829 resets = <&tegra_car 59>, <&tegra_car 22>; 829 resets = <&tegra_car 22>, <&tegra_car 22>;
830 reset-names = "usb", "utmi-pads"; 830 reset-names = "usb", "utmi-pads";
831 nvidia,hssync-start-delay = <0>; 831 nvidia,hssync-start-delay = <0>;
832 nvidia,idle-wait-delay = <17>; 832 nvidia,idle-wait-delay = <17>;
@@ -838,6 +838,7 @@
838 nvidia,hssquelch-level = <2>; 838 nvidia,hssquelch-level = <2>;
839 nvidia,hsdiscon-level = <5>; 839 nvidia,hsdiscon-level = <5>;
840 nvidia,xcvr-hsslew = <12>; 840 nvidia,xcvr-hsslew = <12>;
841 nvidia,has-utmi-pad-registers;
841 status = "disabled"; 842 status = "disabled";
842 }; 843 };
843 844
@@ -862,7 +863,7 @@
862 <&tegra_car TEGRA124_CLK_PLL_U>, 863 <&tegra_car TEGRA124_CLK_PLL_U>,
863 <&tegra_car TEGRA124_CLK_USBD>; 864 <&tegra_car TEGRA124_CLK_USBD>;
864 clock-names = "reg", "pll_u", "utmi-pads"; 865 clock-names = "reg", "pll_u", "utmi-pads";
865 resets = <&tegra_car 22>, <&tegra_car 22>; 866 resets = <&tegra_car 58>, <&tegra_car 22>;
866 reset-names = "usb", "utmi-pads"; 867 reset-names = "usb", "utmi-pads";
867 nvidia,hssync-start-delay = <0>; 868 nvidia,hssync-start-delay = <0>;
868 nvidia,idle-wait-delay = <17>; 869 nvidia,idle-wait-delay = <17>;
@@ -874,7 +875,6 @@
874 nvidia,hssquelch-level = <2>; 875 nvidia,hssquelch-level = <2>;
875 nvidia,hsdiscon-level = <5>; 876 nvidia,hsdiscon-level = <5>;
876 nvidia,xcvr-hsslew = <12>; 877 nvidia,xcvr-hsslew = <12>;
877 nvidia,has-utmi-pad-registers;
878 status = "disabled"; 878 status = "disabled";
879 }; 879 };
880 880
@@ -899,7 +899,7 @@
899 <&tegra_car TEGRA124_CLK_PLL_U>, 899 <&tegra_car TEGRA124_CLK_PLL_U>,
900 <&tegra_car TEGRA124_CLK_USBD>; 900 <&tegra_car TEGRA124_CLK_USBD>;
901 clock-names = "reg", "pll_u", "utmi-pads"; 901 clock-names = "reg", "pll_u", "utmi-pads";
902 resets = <&tegra_car 58>, <&tegra_car 22>; 902 resets = <&tegra_car 59>, <&tegra_car 22>;
903 reset-names = "usb", "utmi-pads"; 903 reset-names = "usb", "utmi-pads";
904 nvidia,hssync-start-delay = <0>; 904 nvidia,hssync-start-delay = <0>;
905 nvidia,idle-wait-delay = <17>; 905 nvidia,idle-wait-delay = <17>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 7a2aeacd62c0..107395c32d82 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -191,6 +191,7 @@
191 compatible = "arm,cortex-a15-pmu"; 191 compatible = "arm,cortex-a15-pmu";
192 interrupts = <0 68 4>, 192 interrupts = <0 68 4>,
193 <0 69 4>; 193 <0 69 4>;
194 interrupt-affinity = <&cpu0>, <&cpu1>;
194 }; 195 };
195 196
196 oscclk6a: oscclk6a { 197 oscclk6a: oscclk6a {
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 23662b5a5e9d..d949facba376 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -33,28 +33,28 @@
33 #address-cells = <1>; 33 #address-cells = <1>;
34 #size-cells = <0>; 34 #size-cells = <0>;
35 35
36 cpu@0 { 36 A9_0: cpu@0 {
37 device_type = "cpu"; 37 device_type = "cpu";
38 compatible = "arm,cortex-a9"; 38 compatible = "arm,cortex-a9";
39 reg = <0>; 39 reg = <0>;
40 next-level-cache = <&L2>; 40 next-level-cache = <&L2>;
41 }; 41 };
42 42
43 cpu@1 { 43 A9_1: cpu@1 {
44 device_type = "cpu"; 44 device_type = "cpu";
45 compatible = "arm,cortex-a9"; 45 compatible = "arm,cortex-a9";
46 reg = <1>; 46 reg = <1>;
47 next-level-cache = <&L2>; 47 next-level-cache = <&L2>;
48 }; 48 };
49 49
50 cpu@2 { 50 A9_2: cpu@2 {
51 device_type = "cpu"; 51 device_type = "cpu";
52 compatible = "arm,cortex-a9"; 52 compatible = "arm,cortex-a9";
53 reg = <2>; 53 reg = <2>;
54 next-level-cache = <&L2>; 54 next-level-cache = <&L2>;
55 }; 55 };
56 56
57 cpu@3 { 57 A9_3: cpu@3 {
58 device_type = "cpu"; 58 device_type = "cpu";
59 compatible = "arm,cortex-a9"; 59 compatible = "arm,cortex-a9";
60 reg = <3>; 60 reg = <3>;
@@ -170,6 +170,7 @@
170 compatible = "arm,pl310-cache"; 170 compatible = "arm,pl310-cache";
171 reg = <0x1e00a000 0x1000>; 171 reg = <0x1e00a000 0x1000>;
172 interrupts = <0 43 4>; 172 interrupts = <0 43 4>;
173 cache-unified;
173 cache-level = <2>; 174 cache-level = <2>;
174 arm,data-latency = <1 1 1>; 175 arm,data-latency = <1 1 1>;
175 arm,tag-latency = <1 1 1>; 176 arm,tag-latency = <1 1 1>;
@@ -181,6 +182,8 @@
181 <0 61 4>, 182 <0 61 4>,
182 <0 62 4>, 183 <0 62 4>,
183 <0 63 4>; 184 <0 63 4>;
185 interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
186
184 }; 187 };
185 188
186 dcc { 189 dcc {
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index ab86655c1f4b..0ca4a3eaf65d 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -39,11 +39,14 @@ CONFIG_ARCH_HIP04=y
39CONFIG_ARCH_KEYSTONE=y 39CONFIG_ARCH_KEYSTONE=y
40CONFIG_ARCH_MESON=y 40CONFIG_ARCH_MESON=y
41CONFIG_ARCH_MXC=y 41CONFIG_ARCH_MXC=y
42CONFIG_SOC_IMX50=y
42CONFIG_SOC_IMX51=y 43CONFIG_SOC_IMX51=y
43CONFIG_SOC_IMX53=y 44CONFIG_SOC_IMX53=y
44CONFIG_SOC_IMX6Q=y 45CONFIG_SOC_IMX6Q=y
45CONFIG_SOC_IMX6SL=y 46CONFIG_SOC_IMX6SL=y
47CONFIG_SOC_IMX6SX=y
46CONFIG_SOC_VF610=y 48CONFIG_SOC_VF610=y
49CONFIG_SOC_LS1021A=y
47CONFIG_ARCH_OMAP3=y 50CONFIG_ARCH_OMAP3=y
48CONFIG_ARCH_OMAP4=y 51CONFIG_ARCH_OMAP4=y
49CONFIG_SOC_OMAP5=y 52CONFIG_SOC_OMAP5=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 9ff7b54b2a83..3743ca221d40 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -393,7 +393,7 @@ CONFIG_TI_EDMA=y
393CONFIG_DMA_OMAP=y 393CONFIG_DMA_OMAP=y
394# CONFIG_IOMMU_SUPPORT is not set 394# CONFIG_IOMMU_SUPPORT is not set
395CONFIG_EXTCON=m 395CONFIG_EXTCON=m
396CONFIG_EXTCON_GPIO=m 396CONFIG_EXTCON_USB_GPIO=m
397CONFIG_EXTCON_PALMAS=m 397CONFIG_EXTCON_PALMAS=m
398CONFIG_TI_EMIF=m 398CONFIG_TI_EMIF=m
399CONFIG_PWM=y 399CONFIG_PWM=y
diff --git a/arch/arm/include/asm/dma-iommu.h b/arch/arm/include/asm/dma-iommu.h
index 8e3fcb924db6..2ef282f96651 100644
--- a/arch/arm/include/asm/dma-iommu.h
+++ b/arch/arm/include/asm/dma-iommu.h
@@ -25,7 +25,7 @@ struct dma_iommu_mapping {
25}; 25};
26 26
27struct dma_iommu_mapping * 27struct dma_iommu_mapping *
28arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size); 28arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size);
29 29
30void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping); 30void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping);
31 31
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index 2f7e6ff67d51..0b579b2f4e0e 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -110,5 +110,6 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
110bool xen_arch_need_swiotlb(struct device *dev, 110bool xen_arch_need_swiotlb(struct device *dev,
111 unsigned long pfn, 111 unsigned long pfn,
112 unsigned long mfn); 112 unsigned long mfn);
113unsigned long xen_get_swiotlb_free_pages(unsigned int order);
113 114
114#endif /* _ASM_ARM_XEN_PAGE_H */ 115#endif /* _ASM_ARM_XEN_PAGE_H */
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index 91c7ba182dcd..213919ba326f 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -303,12 +303,17 @@ static int probe_current_pmu(struct arm_pmu *pmu)
303 303
304static int of_pmu_irq_cfg(struct platform_device *pdev) 304static int of_pmu_irq_cfg(struct platform_device *pdev)
305{ 305{
306 int i; 306 int i, irq;
307 int *irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL); 307 int *irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL);
308 308
309 if (!irqs) 309 if (!irqs)
310 return -ENOMEM; 310 return -ENOMEM;
311 311
312 /* Don't bother with PPIs; they're already affine */
313 irq = platform_get_irq(pdev, 0);
314 if (irq >= 0 && irq_is_percpu(irq))
315 return 0;
316
312 for (i = 0; i < pdev->num_resources; ++i) { 317 for (i = 0; i < pdev->num_resources; ++i) {
313 struct device_node *dn; 318 struct device_node *dn;
314 int cpu; 319 int cpu;
@@ -317,7 +322,7 @@ static int of_pmu_irq_cfg(struct platform_device *pdev)
317 i); 322 i);
318 if (!dn) { 323 if (!dn) {
319 pr_warn("Failed to parse %s/interrupt-affinity[%d]\n", 324 pr_warn("Failed to parse %s/interrupt-affinity[%d]\n",
320 of_node_full_name(dn), i); 325 of_node_full_name(pdev->dev.of_node), i);
321 break; 326 break;
322 } 327 }
323 328
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index acd5b560b728..5f5cd562c593 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -159,6 +159,8 @@ extern void exynos_enter_aftr(void);
159 159
160extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data; 160extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
161 161
162extern void exynos_set_delayed_reset_assertion(bool enable);
163
162extern void s5p_init_cpu(void __iomem *cpuid_addr); 164extern void s5p_init_cpu(void __iomem *cpuid_addr);
163extern unsigned int samsung_rev(void); 165extern unsigned int samsung_rev(void);
164extern void __iomem *cpu_boot_reg_base(void); 166extern void __iomem *cpu_boot_reg_base(void);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index bcde0dd668df..5917a30eee33 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -167,6 +167,33 @@ static void __init exynos_init_io(void)
167} 167}
168 168
169/* 169/*
170 * Set or clear the USE_DELAYED_RESET_ASSERTION option. Used by smp code
171 * and suspend.
172 *
173 * This is necessary only on Exynos4 SoCs. When system is running
174 * USE_DELAYED_RESET_ASSERTION should be set so the ARM CLK clock down
175 * feature could properly detect global idle state when secondary CPU is
176 * powered down.
177 *
178 * However this should not be set when such system is going into suspend.
179 */
180void exynos_set_delayed_reset_assertion(bool enable)
181{
182 if (of_machine_is_compatible("samsung,exynos4")) {
183 unsigned int tmp, core_id;
184
185 for (core_id = 0; core_id < num_possible_cpus(); core_id++) {
186 tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));
187 if (enable)
188 tmp |= S5P_USE_DELAYED_RESET_ASSERTION;
189 else
190 tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION);
191 pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));
192 }
193 }
194}
195
196/*
170 * Apparently, these SoCs are not able to wake-up from suspend using 197 * Apparently, these SoCs are not able to wake-up from suspend using
171 * the PMU. Too bad. Should they suddenly become capable of such a 198 * the PMU. Too bad. Should they suddenly become capable of such a
172 * feat, the matches below should be moved to suspend.c. 199 * feat, the matches below should be moved to suspend.c.
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index ebd135bb0995..a825bca2a2b6 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -34,30 +34,6 @@
34 34
35extern void exynos4_secondary_startup(void); 35extern void exynos4_secondary_startup(void);
36 36
37/*
38 * Set or clear the USE_DELAYED_RESET_ASSERTION option, set on Exynos4 SoCs
39 * during hot-(un)plugging CPUx.
40 *
41 * The feature can be cleared safely during first boot of secondary CPU.
42 *
43 * Exynos4 SoCs require setting USE_DELAYED_RESET_ASSERTION during powering
44 * down a CPU so the CPU idle clock down feature could properly detect global
45 * idle state when CPUx is off.
46 */
47static void exynos_set_delayed_reset_assertion(u32 core_id, bool enable)
48{
49 if (soc_is_exynos4()) {
50 unsigned int tmp;
51
52 tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));
53 if (enable)
54 tmp |= S5P_USE_DELAYED_RESET_ASSERTION;
55 else
56 tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION);
57 pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));
58 }
59}
60
61#ifdef CONFIG_HOTPLUG_CPU 37#ifdef CONFIG_HOTPLUG_CPU
62static inline void cpu_leave_lowpower(u32 core_id) 38static inline void cpu_leave_lowpower(u32 core_id)
63{ 39{
@@ -73,8 +49,6 @@ static inline void cpu_leave_lowpower(u32 core_id)
73 : "=&r" (v) 49 : "=&r" (v)
74 : "Ir" (CR_C), "Ir" (0x40) 50 : "Ir" (CR_C), "Ir" (0x40)
75 : "cc"); 51 : "cc");
76
77 exynos_set_delayed_reset_assertion(core_id, false);
78} 52}
79 53
80static inline void platform_do_lowpower(unsigned int cpu, int *spurious) 54static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
@@ -87,14 +61,6 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
87 /* Turn the CPU off on next WFI instruction. */ 61 /* Turn the CPU off on next WFI instruction. */
88 exynos_cpu_power_down(core_id); 62 exynos_cpu_power_down(core_id);
89 63
90 /*
91 * Exynos4 SoCs require setting
92 * USE_DELAYED_RESET_ASSERTION so the CPU idle
93 * clock down feature could properly detect
94 * global idle state when CPUx is off.
95 */
96 exynos_set_delayed_reset_assertion(core_id, true);
97
98 wfi(); 64 wfi();
99 65
100 if (pen_release == core_id) { 66 if (pen_release == core_id) {
@@ -371,9 +337,6 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
371 udelay(10); 337 udelay(10);
372 } 338 }
373 339
374 /* No harm if this is called during first boot of secondary CPU */
375 exynos_set_delayed_reset_assertion(core_id, false);
376
377 /* 340 /*
378 * now the secondary core is starting up let it run its 341 * now the secondary core is starting up let it run its
379 * calibrations, then wait for it to finish 342 * calibrations, then wait for it to finish
@@ -420,6 +383,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
420 383
421 exynos_sysram_init(); 384 exynos_sysram_init();
422 385
386 exynos_set_delayed_reset_assertion(true);
387
423 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 388 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
424 scu_enable(scu_base_addr()); 389 scu_enable(scu_base_addr());
425 390
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index cbe56b35aea0..a9686535f9ed 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -188,7 +188,7 @@ no_clk:
188 args.np = np; 188 args.np = np;
189 args.args_count = 0; 189 args.args_count = 0;
190 child_domain = of_genpd_get_from_provider(&args); 190 child_domain = of_genpd_get_from_provider(&args);
191 if (!child_domain) 191 if (IS_ERR(child_domain))
192 continue; 192 continue;
193 193
194 if (of_parse_phandle_with_args(np, "power-domains", 194 if (of_parse_phandle_with_args(np, "power-domains",
@@ -196,7 +196,7 @@ no_clk:
196 continue; 196 continue;
197 197
198 parent_domain = of_genpd_get_from_provider(&args); 198 parent_domain = of_genpd_get_from_provider(&args);
199 if (!parent_domain) 199 if (IS_ERR(parent_domain))
200 continue; 200 continue;
201 201
202 if (pm_genpd_add_subdomain(parent_domain, child_domain)) 202 if (pm_genpd_add_subdomain(parent_domain, child_domain))
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 3e6aea7f83af..c0b6dccbf7bd 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -342,6 +342,8 @@ static void exynos_pm_enter_sleep_mode(void)
342 342
343static void exynos_pm_prepare(void) 343static void exynos_pm_prepare(void)
344{ 344{
345 exynos_set_delayed_reset_assertion(false);
346
345 /* Set wake-up mask registers */ 347 /* Set wake-up mask registers */
346 exynos_pm_set_wakeup_mask(); 348 exynos_pm_set_wakeup_mask();
347 349
@@ -482,6 +484,7 @@ early_wakeup:
482 484
483 /* Clear SLEEP mode set in INFORM1 */ 485 /* Clear SLEEP mode set in INFORM1 */
484 pmu_raw_writel(0x0, S5P_INFORM1); 486 pmu_raw_writel(0x0, S5P_INFORM1);
487 exynos_set_delayed_reset_assertion(true);
485} 488}
486 489
487static void exynos3250_pm_resume(void) 490static void exynos3250_pm_resume(void)
@@ -723,8 +726,10 @@ void __init exynos_pm_init(void)
723 return; 726 return;
724 } 727 }
725 728
726 if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) 729 if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
727 pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); 730 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
731 return;
732 }
728 733
729 pm_data = (const struct exynos_pm_data *) match->data; 734 pm_data = (const struct exynos_pm_data *) match->data;
730 735
diff --git a/arch/arm/mach-gemini/common.h b/arch/arm/mach-gemini/common.h
index 38a45260a7c8..dd883698ff7e 100644
--- a/arch/arm/mach-gemini/common.h
+++ b/arch/arm/mach-gemini/common.h
@@ -12,6 +12,8 @@
12#ifndef __GEMINI_COMMON_H__ 12#ifndef __GEMINI_COMMON_H__
13#define __GEMINI_COMMON_H__ 13#define __GEMINI_COMMON_H__
14 14
15#include <linux/reboot.h>
16
15struct mtd_partition; 17struct mtd_partition;
16 18
17extern void gemini_map_io(void); 19extern void gemini_map_io(void);
@@ -26,6 +28,6 @@ extern int platform_register_pflash(unsigned int size,
26 struct mtd_partition *parts, 28 struct mtd_partition *parts,
27 unsigned int nr_parts); 29 unsigned int nr_parts);
28 30
29extern void gemini_restart(char mode, const char *cmd); 31extern void gemini_restart(enum reboot_mode mode, const char *cmd);
30 32
31#endif /* __GEMINI_COMMON_H__ */ 33#endif /* __GEMINI_COMMON_H__ */
diff --git a/arch/arm/mach-gemini/reset.c b/arch/arm/mach-gemini/reset.c
index b26659759e27..21a6d6d4f9c4 100644
--- a/arch/arm/mach-gemini/reset.c
+++ b/arch/arm/mach-gemini/reset.c
@@ -14,7 +14,9 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/global_reg.h> 15#include <mach/global_reg.h>
16 16
17void gemini_restart(char mode, const char *cmd) 17#include "common.h"
18
19void gemini_restart(enum reboot_mode mode, const char *cmd)
18{ 20{
19 __raw_writel(RESET_GLOBAL | RESET_CPU1, 21 __raw_writel(RESET_GLOBAL | RESET_CPU1,
20 IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET); 22 IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET);
diff --git a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
index fb8d4a2ad48c..a5edd7d60266 100644
--- a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
+++ b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> 2 * Copyright (C) 2010 Pengutronix, Wolfram Sang <kernel@pengutronix.de>
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it under 4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the 5 * the terms of the GNU General Public License version 2 as published by the
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 355b08936871..752969ff9de0 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -171,6 +171,12 @@
171 */ 171 */
172#define LINKS_PER_OCP_IF 2 172#define LINKS_PER_OCP_IF 2
173 173
174/*
175 * Address offset (in bytes) between the reset control and the reset
176 * status registers: 4 bytes on OMAP4
177 */
178#define OMAP4_RST_CTRL_ST_OFFSET 4
179
174/** 180/**
175 * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations 181 * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
176 * @enable_module: function to enable a module (via MODULEMODE) 182 * @enable_module: function to enable a module (via MODULEMODE)
@@ -3016,10 +3022,12 @@ static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
3016 if (ohri->st_shift) 3022 if (ohri->st_shift)
3017 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", 3023 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
3018 oh->name, ohri->name); 3024 oh->name, ohri->name);
3019 return omap_prm_deassert_hardreset(ohri->rst_shift, 0, 3025 return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift,
3020 oh->clkdm->pwrdm.ptr->prcm_partition, 3026 oh->clkdm->pwrdm.ptr->prcm_partition,
3021 oh->clkdm->pwrdm.ptr->prcm_offs, 3027 oh->clkdm->pwrdm.ptr->prcm_offs,
3022 oh->prcm.omap4.rstctrl_offs, 0); 3028 oh->prcm.omap4.rstctrl_offs,
3029 oh->prcm.omap4.rstctrl_offs +
3030 OMAP4_RST_CTRL_ST_OFFSET);
3023} 3031}
3024 3032
3025/** 3033/**
@@ -3048,27 +3056,6 @@ static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
3048} 3056}
3049 3057
3050/** 3058/**
3051 * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args
3052 * @oh: struct omap_hwmod * to assert hardreset
3053 * @ohri: hardreset line data
3054 *
3055 * Call am33xx_prminst_assert_hardreset() with parameters extracted
3056 * from the hwmod @oh and the hardreset line data @ohri. Only
3057 * intended for use as an soc_ops function pointer. Passes along the
3058 * return value from am33xx_prminst_assert_hardreset(). XXX This
3059 * function is scheduled for removal when the PRM code is moved into
3060 * drivers/.
3061 */
3062static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
3063 struct omap_hwmod_rst_info *ohri)
3064
3065{
3066 return omap_prm_assert_hardreset(ohri->rst_shift, 0,
3067 oh->clkdm->pwrdm.ptr->prcm_offs,
3068 oh->prcm.omap4.rstctrl_offs);
3069}
3070
3071/**
3072 * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args 3059 * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args
3073 * @oh: struct omap_hwmod * to deassert hardreset 3060 * @oh: struct omap_hwmod * to deassert hardreset
3074 * @ohri: hardreset line data 3061 * @ohri: hardreset line data
@@ -3083,32 +3070,13 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
3083static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, 3070static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
3084 struct omap_hwmod_rst_info *ohri) 3071 struct omap_hwmod_rst_info *ohri)
3085{ 3072{
3086 return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0, 3073 return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift,
3074 oh->clkdm->pwrdm.ptr->prcm_partition,
3087 oh->clkdm->pwrdm.ptr->prcm_offs, 3075 oh->clkdm->pwrdm.ptr->prcm_offs,
3088 oh->prcm.omap4.rstctrl_offs, 3076 oh->prcm.omap4.rstctrl_offs,
3089 oh->prcm.omap4.rstst_offs); 3077 oh->prcm.omap4.rstst_offs);
3090} 3078}
3091 3079
3092/**
3093 * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args
3094 * @oh: struct omap_hwmod * to test hardreset
3095 * @ohri: hardreset line data
3096 *
3097 * Call am33xx_prminst_is_hardreset_asserted() with parameters
3098 * extracted from the hwmod @oh and the hardreset line data @ohri.
3099 * Only intended for use as an soc_ops function pointer. Passes along
3100 * the return value from am33xx_prminst_is_hardreset_asserted(). XXX
3101 * This function is scheduled for removal when the PRM code is moved
3102 * into drivers/.
3103 */
3104static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh,
3105 struct omap_hwmod_rst_info *ohri)
3106{
3107 return omap_prm_is_hardreset_asserted(ohri->rst_shift, 0,
3108 oh->clkdm->pwrdm.ptr->prcm_offs,
3109 oh->prcm.omap4.rstctrl_offs);
3110}
3111
3112/* Public functions */ 3080/* Public functions */
3113 3081
3114u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) 3082u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
@@ -3908,21 +3876,13 @@ void __init omap_hwmod_init(void)
3908 soc_ops.init_clkdm = _init_clkdm; 3876 soc_ops.init_clkdm = _init_clkdm;
3909 soc_ops.update_context_lost = _omap4_update_context_lost; 3877 soc_ops.update_context_lost = _omap4_update_context_lost;
3910 soc_ops.get_context_lost = _omap4_get_context_lost; 3878 soc_ops.get_context_lost = _omap4_get_context_lost;
3911 } else if (soc_is_am43xx()) { 3879 } else if (cpu_is_ti816x() || soc_is_am33xx() || soc_is_am43xx()) {
3912 soc_ops.enable_module = _omap4_enable_module; 3880 soc_ops.enable_module = _omap4_enable_module;
3913 soc_ops.disable_module = _omap4_disable_module; 3881 soc_ops.disable_module = _omap4_disable_module;
3914 soc_ops.wait_target_ready = _omap4_wait_target_ready; 3882 soc_ops.wait_target_ready = _omap4_wait_target_ready;
3915 soc_ops.assert_hardreset = _omap4_assert_hardreset; 3883 soc_ops.assert_hardreset = _omap4_assert_hardreset;
3916 soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
3917 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
3918 soc_ops.init_clkdm = _init_clkdm;
3919 } else if (cpu_is_ti816x() || soc_is_am33xx()) {
3920 soc_ops.enable_module = _omap4_enable_module;
3921 soc_ops.disable_module = _omap4_disable_module;
3922 soc_ops.wait_target_ready = _omap4_wait_target_ready;
3923 soc_ops.assert_hardreset = _am33xx_assert_hardreset;
3924 soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; 3884 soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
3925 soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted; 3885 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
3926 soc_ops.init_clkdm = _init_clkdm; 3886 soc_ops.init_clkdm = _init_clkdm;
3927 } else { 3887 } else {
3928 WARN(1, "omap_hwmod: unknown SoC type\n"); 3888 WARN(1, "omap_hwmod: unknown SoC type\n");
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index e2223148ba4d..17e8004fc20f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -544,6 +544,44 @@ static struct omap_hwmod am43xx_hdq1w_hwmod = {
544 }, 544 },
545}; 545};
546 546
547static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
548 .rev_offs = 0x0,
549 .sysc_offs = 0x104,
550 .sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
551 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
552 MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
553 .sysc_fields = &omap_hwmod_sysc_type2,
554};
555
556static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
557 .name = "vpfe",
558 .sysc = &am43xx_vpfe_sysc,
559};
560
561static struct omap_hwmod am43xx_vpfe0_hwmod = {
562 .name = "vpfe0",
563 .class = &am43xx_vpfe_hwmod_class,
564 .clkdm_name = "l3s_clkdm",
565 .prcm = {
566 .omap4 = {
567 .modulemode = MODULEMODE_SWCTRL,
568 .clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
569 },
570 },
571};
572
573static struct omap_hwmod am43xx_vpfe1_hwmod = {
574 .name = "vpfe1",
575 .class = &am43xx_vpfe_hwmod_class,
576 .clkdm_name = "l3s_clkdm",
577 .prcm = {
578 .omap4 = {
579 .modulemode = MODULEMODE_SWCTRL,
580 .clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
581 },
582 },
583};
584
547/* Interfaces */ 585/* Interfaces */
548static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { 586static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
549 .master = &am33xx_l3_main_hwmod, 587 .master = &am33xx_l3_main_hwmod,
@@ -825,6 +863,34 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
825 .user = OCP_USER_MPU | OCP_USER_SDMA, 863 .user = OCP_USER_MPU | OCP_USER_SDMA,
826}; 864};
827 865
866static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
867 .master = &am43xx_vpfe0_hwmod,
868 .slave = &am33xx_l3_main_hwmod,
869 .clk = "l3_gclk",
870 .user = OCP_USER_MPU | OCP_USER_SDMA,
871};
872
873static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
874 .master = &am43xx_vpfe1_hwmod,
875 .slave = &am33xx_l3_main_hwmod,
876 .clk = "l3_gclk",
877 .user = OCP_USER_MPU | OCP_USER_SDMA,
878};
879
880static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = {
881 .master = &am33xx_l4_ls_hwmod,
882 .slave = &am43xx_vpfe0_hwmod,
883 .clk = "l4ls_gclk",
884 .user = OCP_USER_MPU | OCP_USER_SDMA,
885};
886
887static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
888 .master = &am33xx_l4_ls_hwmod,
889 .slave = &am43xx_vpfe1_hwmod,
890 .clk = "l4ls_gclk",
891 .user = OCP_USER_MPU | OCP_USER_SDMA,
892};
893
828static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { 894static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
829 &am33xx_l4_wkup__synctimer, 895 &am33xx_l4_wkup__synctimer,
830 &am43xx_l4_ls__timer8, 896 &am43xx_l4_ls__timer8,
@@ -925,6 +991,10 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
925 &am43xx_l4_ls__dss_dispc, 991 &am43xx_l4_ls__dss_dispc,
926 &am43xx_l4_ls__dss_rfbi, 992 &am43xx_l4_ls__dss_rfbi,
927 &am43xx_l4_ls__hdq1w, 993 &am43xx_l4_ls__hdq1w,
994 &am43xx_l3__vpfe0,
995 &am43xx_l3__vpfe1,
996 &am43xx_l4_ls__vpfe0,
997 &am43xx_l4_ls__vpfe1,
928 NULL, 998 NULL,
929}; 999};
930 1000
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index 48df3b55057e..d0261996db6d 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -144,5 +144,6 @@
144#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 144#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0
145#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20 145#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20
146#define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0 146#define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0
147 147#define AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET 0x0068
148#define AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET 0x0070
148#endif 149#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index cbefbd7cfdb5..661d753df584 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -112,6 +112,7 @@
112#define OMAP3430_VC_CMD_ONLP_SHIFT 16 112#define OMAP3430_VC_CMD_ONLP_SHIFT 16
113#define OMAP3430_VC_CMD_RET_SHIFT 8 113#define OMAP3430_VC_CMD_RET_SHIFT 8
114#define OMAP3430_VC_CMD_OFF_SHIFT 0 114#define OMAP3430_VC_CMD_OFF_SHIFT 0
115#define OMAP3430_SREN_MASK (1 << 4)
115#define OMAP3430_HSEN_MASK (1 << 3) 116#define OMAP3430_HSEN_MASK (1 << 3)
116#define OMAP3430_MCODE_MASK (0x7 << 0) 117#define OMAP3430_MCODE_MASK (0x7 << 0)
117#define OMAP3430_VALID_MASK (1 << 24) 118#define OMAP3430_VALID_MASK (1 << 24)
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index b1c7a33e00e7..e794828dee55 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -35,6 +35,7 @@
35#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 35#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1
36#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) 36#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16)
37#define OMAP4430_HSMCODE_MASK (0x7 << 0) 37#define OMAP4430_HSMCODE_MASK (0x7 << 0)
38#define OMAP4430_SRMODEEN_MASK (1 << 4)
38#define OMAP4430_HSMODEEN_MASK (1 << 3) 39#define OMAP4430_HSMODEEN_MASK (1 << 3)
39#define OMAP4430_HSSCLL_SHIFT 24 40#define OMAP4430_HSSCLL_SHIFT 24
40#define OMAP4430_ICEPICK_RST_SHIFT 9 41#define OMAP4430_ICEPICK_RST_SHIFT 9
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index c4859c4d3646..d0b15dbafa2e 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -87,12 +87,6 @@ u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
87 return v; 87 return v;
88} 88}
89 89
90/*
91 * Address offset (in bytes) between the reset control and the reset
92 * status registers: 4 bytes on OMAP4
93 */
94#define OMAP4_RST_CTRL_ST_OFFSET 4
95
96/** 90/**
97 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of 91 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
98 * submodules contained in the hwmod module 92 * submodules contained in the hwmod module
@@ -141,11 +135,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
141 * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and 135 * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
142 * wait 136 * wait
143 * @shift: register bit shift corresponding to the reset line to deassert 137 * @shift: register bit shift corresponding to the reset line to deassert
144 * @st_shift: status bit offset, not used for OMAP4+ 138 * @st_shift: status bit offset corresponding to the reset line
145 * @part: PRM partition 139 * @part: PRM partition
146 * @inst: PRM instance offset 140 * @inst: PRM instance offset
147 * @rstctrl_offs: reset register offset 141 * @rstctrl_offs: reset register offset
148 * @st_offs: reset status register offset, not used for OMAP4+ 142 * @rstst_offs: reset status register offset
149 * 143 *
150 * Some IPs like dsp, ipu or iva contain processors that require an HW 144 * Some IPs like dsp, ipu or iva contain processors that require an HW
151 * reset line to be asserted / deasserted in order to fully enable the 145 * reset line to be asserted / deasserted in order to fully enable the
@@ -157,11 +151,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
157 * of reset, or -EBUSY if the submodule did not exit reset promptly. 151 * of reset, or -EBUSY if the submodule did not exit reset promptly.
158 */ 152 */
159int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst, 153int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
160 u16 rstctrl_offs, u16 st_offs) 154 u16 rstctrl_offs, u16 rstst_offs)
161{ 155{
162 int c; 156 int c;
163 u32 mask = 1 << shift; 157 u32 mask = 1 << shift;
164 u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET; 158 u32 st_mask = 1 << st_shift;
165 159
166 /* Check the current status to avoid de-asserting the line twice */ 160 /* Check the current status to avoid de-asserting the line twice */
167 if (omap4_prminst_is_hardreset_asserted(shift, part, inst, 161 if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
@@ -169,13 +163,13 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
169 return -EEXIST; 163 return -EEXIST;
170 164
171 /* Clear the reset status by writing 1 to the status bit */ 165 /* Clear the reset status by writing 1 to the status bit */
172 omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst, 166 omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst,
173 rstst_offs); 167 rstst_offs);
174 /* de-assert the reset control line */ 168 /* de-assert the reset control line */
175 omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs); 169 omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
176 /* wait the status to be set */ 170 /* wait the status to be set */
177 omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst, 171 omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part,
178 rstst_offs), 172 inst, rstst_offs),
179 MAX_MODULE_HARDRESET_WAIT, c); 173 MAX_MODULE_HARDRESET_WAIT, c);
180 174
181 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; 175 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index cef67af9e9b8..cac46d852da1 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -298,14 +298,11 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
298 if (IS_ERR(src)) 298 if (IS_ERR(src))
299 return PTR_ERR(src); 299 return PTR_ERR(src);
300 300
301 if (clk_get_parent(timer->fclk) != src) { 301 r = clk_set_parent(timer->fclk, src);
302 r = clk_set_parent(timer->fclk, src); 302 if (r < 0) {
303 if (r < 0) { 303 pr_warn("%s: %s cannot set source\n", __func__, oh->name);
304 pr_warn("%s: %s cannot set source\n", __func__, 304 clk_put(src);
305 oh->name); 305 return r;
306 clk_put(src);
307 return r;
308 }
309 } 306 }
310 307
311 clk_put(src); 308 clk_put(src);
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index be9ef834fa81..076fd20d7e5a 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -316,7 +316,8 @@ static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm)
316 * idle. And we can also scale voltages to zero for off-idle. 316 * idle. And we can also scale voltages to zero for off-idle.
317 * Note that no actual voltage scaling during off-idle will 317 * Note that no actual voltage scaling during off-idle will
318 * happen unless the board specific twl4030 PMIC scripts are 318 * happen unless the board specific twl4030 PMIC scripts are
319 * loaded. 319 * loaded. See also omap_vc_i2c_init for comments regarding
320 * erratum i531.
320 */ 321 */
321 val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); 322 val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
322 if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) { 323 if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) {
@@ -704,9 +705,16 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
704 return; 705 return;
705 } 706 }
706 707
708 /*
709 * Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around
710 * erratum i531 "Extra Power Consumed When Repeated Start Operation
711 * Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)".
712 * Otherwise I2C4 eventually leads into about 23mW extra power being
713 * consumed even during off idle using VMODE.
714 */
707 i2c_high_speed = voltdm->pmic->i2c_high_speed; 715 i2c_high_speed = voltdm->pmic->i2c_high_speed;
708 if (i2c_high_speed) 716 if (i2c_high_speed)
709 voltdm->rmw(vc->common->i2c_cfg_hsen_mask, 717 voltdm->rmw(vc->common->i2c_cfg_clear_mask,
710 vc->common->i2c_cfg_hsen_mask, 718 vc->common->i2c_cfg_hsen_mask,
711 vc->common->i2c_cfg_reg); 719 vc->common->i2c_cfg_reg);
712 720
diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
index cdbdd78e755e..89b83b7ff3ec 100644
--- a/arch/arm/mach-omap2/vc.h
+++ b/arch/arm/mach-omap2/vc.h
@@ -34,6 +34,7 @@ struct voltagedomain;
34 * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register 34 * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
35 * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register 35 * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
36 * @i2c_cfg_reg: I2C configuration register offset 36 * @i2c_cfg_reg: I2C configuration register offset
37 * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
37 * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register 38 * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
38 * @i2c_mcode_mask: MCODE field mask for I2C config register 39 * @i2c_mcode_mask: MCODE field mask for I2C config register
39 * 40 *
@@ -52,6 +53,7 @@ struct omap_vc_common {
52 u8 cmd_ret_shift; 53 u8 cmd_ret_shift;
53 u8 cmd_off_shift; 54 u8 cmd_off_shift;
54 u8 i2c_cfg_reg; 55 u8 i2c_cfg_reg;
56 u8 i2c_cfg_clear_mask;
55 u8 i2c_cfg_hsen_mask; 57 u8 i2c_cfg_hsen_mask;
56 u8 i2c_mcode_mask; 58 u8 i2c_mcode_mask;
57}; 59};
diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
index 75bc4aa22b3a..71d74c9172c1 100644
--- a/arch/arm/mach-omap2/vc3xxx_data.c
+++ b/arch/arm/mach-omap2/vc3xxx_data.c
@@ -40,6 +40,7 @@ static struct omap_vc_common omap3_vc_common = {
40 .cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT, 40 .cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT,
41 .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT, 41 .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT,
42 .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT, 42 .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT,
43 .i2c_cfg_clear_mask = OMAP3430_SREN_MASK | OMAP3430_HSEN_MASK,
43 .i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK, 44 .i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK,
44 .i2c_cfg_reg = OMAP3_PRM_VC_I2C_CFG_OFFSET, 45 .i2c_cfg_reg = OMAP3_PRM_VC_I2C_CFG_OFFSET,
45 .i2c_mcode_mask = OMAP3430_MCODE_MASK, 46 .i2c_mcode_mask = OMAP3430_MCODE_MASK,
diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
index 085e5d6a04fd..2abd5fa8a697 100644
--- a/arch/arm/mach-omap2/vc44xx_data.c
+++ b/arch/arm/mach-omap2/vc44xx_data.c
@@ -42,6 +42,7 @@ static const struct omap_vc_common omap4_vc_common = {
42 .cmd_ret_shift = OMAP4430_RET_SHIFT, 42 .cmd_ret_shift = OMAP4430_RET_SHIFT,
43 .cmd_off_shift = OMAP4430_OFF_SHIFT, 43 .cmd_off_shift = OMAP4430_OFF_SHIFT,
44 .i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET, 44 .i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET,
45 .i2c_cfg_clear_mask = OMAP4430_SRMODEEN_MASK | OMAP4430_HSMODEEN_MASK,
45 .i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK, 46 .i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK,
46 .i2c_mcode_mask = OMAP4430_HSMCODE_MASK, 47 .i2c_mcode_mask = OMAP4430_HSMCODE_MASK,
47}; 48};
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 8896e71586f5..f09683687963 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -691,4 +691,13 @@ config SHARPSL_PM_MAX1111
691config PXA310_ULPI 691config PXA310_ULPI
692 bool 692 bool
693 693
694config PXA_SYSTEMS_CPLDS
695 tristate "Motherboard cplds"
696 default ARCH_LUBBOCK || MACH_MAINSTONE
697 help
698 This driver supports the Lubbock and Mainstone multifunction chip
699 found on the pxa25x development platform system (Lubbock) and pxa27x
700 development platform system (Mainstone). This IO board supports the
701 interrupts handling, ethernet controller, flash chips, etc ...
702
694endif 703endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index eb0bf7678a99..4087d334ecdf 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -90,4 +90,5 @@ obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR) += raumfeld.o
90obj-$(CONFIG_MACH_RAUMFELD_SPEAKER) += raumfeld.o 90obj-$(CONFIG_MACH_RAUMFELD_SPEAKER) += raumfeld.o
91obj-$(CONFIG_MACH_ZIPIT2) += z2.o 91obj-$(CONFIG_MACH_ZIPIT2) += z2.o
92 92
93obj-$(CONFIG_PXA_SYSTEMS_CPLDS) += pxa_cplds_irqs.o
93obj-$(CONFIG_TOSA_BT) += tosa-bt.o 94obj-$(CONFIG_TOSA_BT) += tosa-bt.o
diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h
index 958cd6af9384..1eecf794acd2 100644
--- a/arch/arm/mach-pxa/include/mach/lubbock.h
+++ b/arch/arm/mach-pxa/include/mach/lubbock.h
@@ -37,7 +37,9 @@
37#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100) 37#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100)
38 38
39/* Board specific IRQs */ 39/* Board specific IRQs */
40#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x)) 40#define LUBBOCK_NR_IRQS IRQ_BOARD_START
41
42#define LUBBOCK_IRQ(x) (LUBBOCK_NR_IRQS + (x))
41#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) 43#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0)
42#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) 44#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1)
43#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ 45#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */
@@ -47,8 +49,7 @@
47#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ 49#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */
48#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) 50#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
49 51
50#define LUBBOCK_SA1111_IRQ_BASE (IRQ_BOARD_START + 16) 52#define LUBBOCK_SA1111_IRQ_BASE (LUBBOCK_NR_IRQS + 32)
51#define LUBBOCK_NR_IRQS (IRQ_BOARD_START + 16 + 55)
52 53
53#ifndef __ASSEMBLY__ 54#ifndef __ASSEMBLY__
54extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set); 55extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
diff --git a/arch/arm/mach-pxa/include/mach/mainstone.h b/arch/arm/mach-pxa/include/mach/mainstone.h
index 1bfc4e822a41..e82a7d31104e 100644
--- a/arch/arm/mach-pxa/include/mach/mainstone.h
+++ b/arch/arm/mach-pxa/include/mach/mainstone.h
@@ -120,7 +120,9 @@
120#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */ 120#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */
121 121
122/* board specific IRQs */ 122/* board specific IRQs */
123#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x)) 123#define MAINSTONE_NR_IRQS IRQ_BOARD_START
124
125#define MAINSTONE_IRQ(x) (MAINSTONE_NR_IRQS + (x))
124#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) 126#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0)
125#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) 127#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1)
126#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) 128#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2)
@@ -136,6 +138,4 @@
136#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) 138#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
137#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) 139#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15)
138 140
139#define MAINSTONE_NR_IRQS (IRQ_BOARD_START + 16)
140
141#endif 141#endif
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index d8a1be619f21..4ac9ab80d24b 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -12,6 +12,7 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14#include <linux/gpio.h> 14#include <linux/gpio.h>
15#include <linux/gpio/machine.h>
15#include <linux/module.h> 16#include <linux/module.h>
16#include <linux/kernel.h> 17#include <linux/kernel.h>
17#include <linux/init.h> 18#include <linux/init.h>
@@ -123,84 +124,6 @@ void lubbock_set_misc_wr(unsigned int mask, unsigned int set)
123} 124}
124EXPORT_SYMBOL(lubbock_set_misc_wr); 125EXPORT_SYMBOL(lubbock_set_misc_wr);
125 126
126static unsigned long lubbock_irq_enabled;
127
128static void lubbock_mask_irq(struct irq_data *d)
129{
130 int lubbock_irq = (d->irq - LUBBOCK_IRQ(0));
131 LUB_IRQ_MASK_EN = (lubbock_irq_enabled &= ~(1 << lubbock_irq));
132}
133
134static void lubbock_unmask_irq(struct irq_data *d)
135{
136 int lubbock_irq = (d->irq - LUBBOCK_IRQ(0));
137 /* the irq can be acknowledged only if deasserted, so it's done here */
138 LUB_IRQ_SET_CLR &= ~(1 << lubbock_irq);
139 LUB_IRQ_MASK_EN = (lubbock_irq_enabled |= (1 << lubbock_irq));
140}
141
142static struct irq_chip lubbock_irq_chip = {
143 .name = "FPGA",
144 .irq_ack = lubbock_mask_irq,
145 .irq_mask = lubbock_mask_irq,
146 .irq_unmask = lubbock_unmask_irq,
147};
148
149static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc)
150{
151 unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
152 do {
153 /* clear our parent irq */
154 desc->irq_data.chip->irq_ack(&desc->irq_data);
155 if (likely(pending)) {
156 irq = LUBBOCK_IRQ(0) + __ffs(pending);
157 generic_handle_irq(irq);
158 }
159 pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
160 } while (pending);
161}
162
163static void __init lubbock_init_irq(void)
164{
165 int irq;
166
167 pxa25x_init_irq();
168
169 /* setup extra lubbock irqs */
170 for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
171 irq_set_chip_and_handler(irq, &lubbock_irq_chip,
172 handle_level_irq);
173 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
174 }
175
176 irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lubbock_irq_handler);
177 irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
178}
179
180#ifdef CONFIG_PM
181
182static void lubbock_irq_resume(void)
183{
184 LUB_IRQ_MASK_EN = lubbock_irq_enabled;
185}
186
187static struct syscore_ops lubbock_irq_syscore_ops = {
188 .resume = lubbock_irq_resume,
189};
190
191static int __init lubbock_irq_device_init(void)
192{
193 if (machine_is_lubbock()) {
194 register_syscore_ops(&lubbock_irq_syscore_ops);
195 return 0;
196 }
197 return -ENODEV;
198}
199
200device_initcall(lubbock_irq_device_init);
201
202#endif
203
204static int lubbock_udc_is_connected(void) 127static int lubbock_udc_is_connected(void)
205{ 128{
206 return (LUB_MISC_RD & (1 << 9)) == 0; 129 return (LUB_MISC_RD & (1 << 9)) == 0;
@@ -383,11 +306,38 @@ static struct platform_device lubbock_flash_device[2] = {
383 }, 306 },
384}; 307};
385 308
309static struct resource lubbock_cplds_resources[] = {
310 [0] = {
311 .start = LUBBOCK_FPGA_PHYS + 0xc0,
312 .end = LUBBOCK_FPGA_PHYS + 0xe0 - 1,
313 .flags = IORESOURCE_MEM,
314 },
315 [1] = {
316 .start = PXA_GPIO_TO_IRQ(0),
317 .end = PXA_GPIO_TO_IRQ(0),
318 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
319 },
320 [2] = {
321 .start = LUBBOCK_IRQ(0),
322 .end = LUBBOCK_IRQ(6),
323 .flags = IORESOURCE_IRQ,
324 },
325};
326
327static struct platform_device lubbock_cplds_device = {
328 .name = "pxa_cplds_irqs",
329 .id = -1,
330 .resource = &lubbock_cplds_resources[0],
331 .num_resources = 3,
332};
333
334
386static struct platform_device *devices[] __initdata = { 335static struct platform_device *devices[] __initdata = {
387 &sa1111_device, 336 &sa1111_device,
388 &smc91x_device, 337 &smc91x_device,
389 &lubbock_flash_device[0], 338 &lubbock_flash_device[0],
390 &lubbock_flash_device[1], 339 &lubbock_flash_device[1],
340 &lubbock_cplds_device,
391}; 341};
392 342
393static struct pxafb_mode_info sharp_lm8v31_mode = { 343static struct pxafb_mode_info sharp_lm8v31_mode = {
@@ -648,7 +598,7 @@ MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
648 /* Maintainer: MontaVista Software Inc. */ 598 /* Maintainer: MontaVista Software Inc. */
649 .map_io = lubbock_map_io, 599 .map_io = lubbock_map_io,
650 .nr_irqs = LUBBOCK_NR_IRQS, 600 .nr_irqs = LUBBOCK_NR_IRQS,
651 .init_irq = lubbock_init_irq, 601 .init_irq = pxa25x_init_irq,
652 .handle_irq = pxa25x_handle_irq, 602 .handle_irq = pxa25x_handle_irq,
653 .init_time = pxa_timer_init, 603 .init_time = pxa_timer_init,
654 .init_machine = lubbock_init, 604 .init_machine = lubbock_init,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 78b84c0dfc79..2c0658cf6be2 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -13,6 +13,7 @@
13 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
14 */ 14 */
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/gpio/machine.h>
16#include <linux/init.h> 17#include <linux/init.h>
17#include <linux/platform_device.h> 18#include <linux/platform_device.h>
18#include <linux/syscore_ops.h> 19#include <linux/syscore_ops.h>
@@ -122,92 +123,6 @@ static unsigned long mainstone_pin_config[] = {
122 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, 123 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
123}; 124};
124 125
125static unsigned long mainstone_irq_enabled;
126
127static void mainstone_mask_irq(struct irq_data *d)
128{
129 int mainstone_irq = (d->irq - MAINSTONE_IRQ(0));
130 MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
131}
132
133static void mainstone_unmask_irq(struct irq_data *d)
134{
135 int mainstone_irq = (d->irq - MAINSTONE_IRQ(0));
136 /* the irq can be acknowledged only if deasserted, so it's done here */
137 MST_INTSETCLR &= ~(1 << mainstone_irq);
138 MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
139}
140
141static struct irq_chip mainstone_irq_chip = {
142 .name = "FPGA",
143 .irq_ack = mainstone_mask_irq,
144 .irq_mask = mainstone_mask_irq,
145 .irq_unmask = mainstone_unmask_irq,
146};
147
148static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
149{
150 unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
151 do {
152 /* clear useless edge notification */
153 desc->irq_data.chip->irq_ack(&desc->irq_data);
154 if (likely(pending)) {
155 irq = MAINSTONE_IRQ(0) + __ffs(pending);
156 generic_handle_irq(irq);
157 }
158 pending = MST_INTSETCLR & mainstone_irq_enabled;
159 } while (pending);
160}
161
162static void __init mainstone_init_irq(void)
163{
164 int irq;
165
166 pxa27x_init_irq();
167
168 /* setup extra Mainstone irqs */
169 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
170 irq_set_chip_and_handler(irq, &mainstone_irq_chip,
171 handle_level_irq);
172 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
173 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
174 else
175 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
176 }
177 set_irq_flags(MAINSTONE_IRQ(8), 0);
178 set_irq_flags(MAINSTONE_IRQ(12), 0);
179
180 MST_INTMSKENA = 0;
181 MST_INTSETCLR = 0;
182
183 irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), mainstone_irq_handler);
184 irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
185}
186
187#ifdef CONFIG_PM
188
189static void mainstone_irq_resume(void)
190{
191 MST_INTMSKENA = mainstone_irq_enabled;
192}
193
194static struct syscore_ops mainstone_irq_syscore_ops = {
195 .resume = mainstone_irq_resume,
196};
197
198static int __init mainstone_irq_device_init(void)
199{
200 if (machine_is_mainstone())
201 register_syscore_ops(&mainstone_irq_syscore_ops);
202
203 return 0;
204}
205
206device_initcall(mainstone_irq_device_init);
207
208#endif
209
210
211static struct resource smc91x_resources[] = { 126static struct resource smc91x_resources[] = {
212 [0] = { 127 [0] = {
213 .start = (MST_ETH_PHYS + 0x300), 128 .start = (MST_ETH_PHYS + 0x300),
@@ -487,11 +402,37 @@ static struct platform_device mst_gpio_keys_device = {
487 }, 402 },
488}; 403};
489 404
405static struct resource mst_cplds_resources[] = {
406 [0] = {
407 .start = MST_FPGA_PHYS + 0xc0,
408 .end = MST_FPGA_PHYS + 0xe0 - 1,
409 .flags = IORESOURCE_MEM,
410 },
411 [1] = {
412 .start = PXA_GPIO_TO_IRQ(0),
413 .end = PXA_GPIO_TO_IRQ(0),
414 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
415 },
416 [2] = {
417 .start = MAINSTONE_IRQ(0),
418 .end = MAINSTONE_IRQ(15),
419 .flags = IORESOURCE_IRQ,
420 },
421};
422
423static struct platform_device mst_cplds_device = {
424 .name = "pxa_cplds_irqs",
425 .id = -1,
426 .resource = &mst_cplds_resources[0],
427 .num_resources = 3,
428};
429
490static struct platform_device *platform_devices[] __initdata = { 430static struct platform_device *platform_devices[] __initdata = {
491 &smc91x_device, 431 &smc91x_device,
492 &mst_flash_device[0], 432 &mst_flash_device[0],
493 &mst_flash_device[1], 433 &mst_flash_device[1],
494 &mst_gpio_keys_device, 434 &mst_gpio_keys_device,
435 &mst_cplds_device,
495}; 436};
496 437
497static struct pxaohci_platform_data mainstone_ohci_platform_data = { 438static struct pxaohci_platform_data mainstone_ohci_platform_data = {
@@ -718,7 +659,7 @@ MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
718 .atag_offset = 0x100, /* BLOB boot parameter setting */ 659 .atag_offset = 0x100, /* BLOB boot parameter setting */
719 .map_io = mainstone_map_io, 660 .map_io = mainstone_map_io,
720 .nr_irqs = MAINSTONE_NR_IRQS, 661 .nr_irqs = MAINSTONE_NR_IRQS,
721 .init_irq = mainstone_init_irq, 662 .init_irq = pxa27x_init_irq,
722 .handle_irq = pxa27x_handle_irq, 663 .handle_irq = pxa27x_handle_irq,
723 .init_time = pxa_timer_init, 664 .init_time = pxa_timer_init,
724 .init_machine = mainstone_init, 665 .init_machine = mainstone_init,
diff --git a/arch/arm/mach-pxa/pxa_cplds_irqs.c b/arch/arm/mach-pxa/pxa_cplds_irqs.c
new file mode 100644
index 000000000000..f1aeb54fabe3
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa_cplds_irqs.c
@@ -0,0 +1,200 @@
1/*
2 * Intel Reference Systems cplds
3 *
4 * Copyright (C) 2014 Robert Jarzmik
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * Cplds motherboard driver, supporting lubbock and mainstone SoC board.
12 */
13
14#include <linux/bitops.h>
15#include <linux/gpio.h>
16#include <linux/gpio/consumer.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
21#include <linux/mfd/core.h>
22#include <linux/module.h>
23#include <linux/of_platform.h>
24
25#define FPGA_IRQ_MASK_EN 0x0
26#define FPGA_IRQ_SET_CLR 0x10
27
28#define CPLDS_NB_IRQ 32
29
30struct cplds {
31 void __iomem *base;
32 int irq;
33 unsigned int irq_mask;
34 struct gpio_desc *gpio0;
35 struct irq_domain *irqdomain;
36};
37
38static irqreturn_t cplds_irq_handler(int in_irq, void *d)
39{
40 struct cplds *fpga = d;
41 unsigned long pending;
42 unsigned int bit;
43
44 pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask;
45 for_each_set_bit(bit, &pending, CPLDS_NB_IRQ)
46 generic_handle_irq(irq_find_mapping(fpga->irqdomain, bit));
47
48 return IRQ_HANDLED;
49}
50
51static void cplds_irq_mask_ack(struct irq_data *d)
52{
53 struct cplds *fpga = irq_data_get_irq_chip_data(d);
54 unsigned int cplds_irq = irqd_to_hwirq(d);
55 unsigned int set, bit = BIT(cplds_irq);
56
57 fpga->irq_mask &= ~bit;
58 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
59 set = readl(fpga->base + FPGA_IRQ_SET_CLR);
60 writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR);
61}
62
63static void cplds_irq_unmask(struct irq_data *d)
64{
65 struct cplds *fpga = irq_data_get_irq_chip_data(d);
66 unsigned int cplds_irq = irqd_to_hwirq(d);
67 unsigned int bit = BIT(cplds_irq);
68
69 fpga->irq_mask |= bit;
70 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
71}
72
73static struct irq_chip cplds_irq_chip = {
74 .name = "pxa_cplds",
75 .irq_mask_ack = cplds_irq_mask_ack,
76 .irq_unmask = cplds_irq_unmask,
77 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
78};
79
80static int cplds_irq_domain_map(struct irq_domain *d, unsigned int irq,
81 irq_hw_number_t hwirq)
82{
83 struct cplds *fpga = d->host_data;
84
85 irq_set_chip_and_handler(irq, &cplds_irq_chip, handle_level_irq);
86 irq_set_chip_data(irq, fpga);
87
88 return 0;
89}
90
91static const struct irq_domain_ops cplds_irq_domain_ops = {
92 .xlate = irq_domain_xlate_twocell,
93 .map = cplds_irq_domain_map,
94};
95
96static int cplds_resume(struct platform_device *pdev)
97{
98 struct cplds *fpga = platform_get_drvdata(pdev);
99
100 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
101
102 return 0;
103}
104
105static int cplds_probe(struct platform_device *pdev)
106{
107 struct resource *res;
108 struct cplds *fpga;
109 int ret;
110 unsigned int base_irq = 0;
111 unsigned long irqflags = 0;
112
113 fpga = devm_kzalloc(&pdev->dev, sizeof(*fpga), GFP_KERNEL);
114 if (!fpga)
115 return -ENOMEM;
116
117 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
118 if (res) {
119 fpga->irq = (unsigned int)res->start;
120 irqflags = res->flags;
121 }
122 if (!fpga->irq)
123 return -ENODEV;
124
125 base_irq = platform_get_irq(pdev, 1);
126 if (base_irq < 0)
127 base_irq = 0;
128
129 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
130 fpga->base = devm_ioremap_resource(&pdev->dev, res);
131 if (IS_ERR(fpga->base))
132 return PTR_ERR(fpga->base);
133
134 platform_set_drvdata(pdev, fpga);
135
136 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
137 writel(0, fpga->base + FPGA_IRQ_SET_CLR);
138
139 ret = devm_request_irq(&pdev->dev, fpga->irq, cplds_irq_handler,
140 irqflags, dev_name(&pdev->dev), fpga);
141 if (ret == -ENOSYS)
142 return -EPROBE_DEFER;
143
144 if (ret) {
145 dev_err(&pdev->dev, "couldn't request main irq%d: %d\n",
146 fpga->irq, ret);
147 return ret;
148 }
149
150 irq_set_irq_wake(fpga->irq, 1);
151 fpga->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
152 CPLDS_NB_IRQ,
153 &cplds_irq_domain_ops, fpga);
154 if (!fpga->irqdomain)
155 return -ENODEV;
156
157 if (base_irq) {
158 ret = irq_create_strict_mappings(fpga->irqdomain, base_irq, 0,
159 CPLDS_NB_IRQ);
160 if (ret) {
161 dev_err(&pdev->dev, "couldn't create the irq mapping %d..%d\n",
162 base_irq, base_irq + CPLDS_NB_IRQ);
163 return ret;
164 }
165 }
166
167 return 0;
168}
169
170static int cplds_remove(struct platform_device *pdev)
171{
172 struct cplds *fpga = platform_get_drvdata(pdev);
173
174 irq_set_chip_and_handler(fpga->irq, NULL, NULL);
175
176 return 0;
177}
178
179static const struct of_device_id cplds_id_table[] = {
180 { .compatible = "intel,lubbock-cplds-irqs", },
181 { .compatible = "intel,mainstone-cplds-irqs", },
182 { }
183};
184MODULE_DEVICE_TABLE(of, cplds_id_table);
185
186static struct platform_driver cplds_driver = {
187 .driver = {
188 .name = "pxa_cplds_irqs",
189 .of_match_table = of_match_ptr(cplds_id_table),
190 },
191 .probe = cplds_probe,
192 .remove = cplds_remove,
193 .resume = cplds_resume,
194};
195
196module_platform_driver(cplds_driver);
197
198MODULE_DESCRIPTION("PXA Cplds interrupts driver");
199MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
200MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index b07d88602073..b0dcbe28f78c 100644
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -83,6 +83,13 @@ static void rk3288_slp_mode_set(int level)
83 SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN 83 SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN
84 | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE); 84 | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);
85 85
86 /*
87 * The dapswjdp can not auto reset before resume, that cause it may
88 * access some illegal address during resume. Let's disable it before
89 * suspend, and the MASKROM will enable it back.
90 */
91 regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE);
92
86 /* booting address of resuming system is from this register value */ 93 /* booting address of resuming system is from this register value */
87 regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR, 94 regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
88 rk3288_bootram_phy); 95 rk3288_bootram_phy);
diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h
index 03ff31d8282d..3e8d39c0c3d5 100644
--- a/arch/arm/mach-rockchip/pm.h
+++ b/arch/arm/mach-rockchip/pm.h
@@ -55,6 +55,10 @@ static inline void rockchip_suspend_init(void)
55#define SGRF_FAST_BOOT_EN BIT(8) 55#define SGRF_FAST_BOOT_EN BIT(8)
56#define SGRF_FAST_BOOT_EN_WRITE BIT(24) 56#define SGRF_FAST_BOOT_EN_WRITE BIT(24)
57 57
58#define RK3288_SGRF_CPU_CON0 (0x40)
59#define SGRF_DAPDEVICEEN BIT(0)
60#define SGRF_DAPDEVICEEN_WRITE BIT(16)
61
58#define RK3288_CRU_MODE_CON 0x50 62#define RK3288_CRU_MODE_CON 0x50
59#define RK3288_CRU_SEL0_CON 0x60 63#define RK3288_CRU_SEL0_CON 0x60
60#define RK3288_CRU_SEL1_CON 0x64 64#define RK3288_CRU_SEL1_CON 0x64
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index d360ec044b66..b6cf3b449428 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -30,11 +30,30 @@
30#include "pm.h" 30#include "pm.h"
31 31
32#define RK3288_GRF_SOC_CON0 0x244 32#define RK3288_GRF_SOC_CON0 0x244
33#define RK3288_TIMER6_7_PHYS 0xff810000
33 34
34static void __init rockchip_timer_init(void) 35static void __init rockchip_timer_init(void)
35{ 36{
36 if (of_machine_is_compatible("rockchip,rk3288")) { 37 if (of_machine_is_compatible("rockchip,rk3288")) {
37 struct regmap *grf; 38 struct regmap *grf;
39 void __iomem *reg_base;
40
41 /*
42 * Most/all uboot versions for rk3288 don't enable timer7
43 * which is needed for the architected timer to work.
44 * So make sure it is running during early boot.
45 */
46 reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
47 if (reg_base) {
48 writel(0, reg_base + 0x30);
49 writel(0xffffffff, reg_base + 0x20);
50 writel(0xffffffff, reg_base + 0x24);
51 writel(1, reg_base + 0x30);
52 dsb();
53 iounmap(reg_base);
54 } else {
55 pr_err("rockchip: could not map timer7 registers\n");
56 }
38 57
39 /* 58 /*
40 * Disable auto jtag/sdmmc switching that causes issues 59 * Disable auto jtag/sdmmc switching that causes issues
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 09c5fe3d30c2..7e7583ddd607 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1878,7 +1878,7 @@ struct dma_map_ops iommu_coherent_ops = {
1878 * arm_iommu_attach_device function. 1878 * arm_iommu_attach_device function.
1879 */ 1879 */
1880struct dma_iommu_mapping * 1880struct dma_iommu_mapping *
1881arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size) 1881arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size)
1882{ 1882{
1883 unsigned int bits = size >> PAGE_SHIFT; 1883 unsigned int bits = size >> PAGE_SHIFT;
1884 unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long); 1884 unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
@@ -1886,6 +1886,10 @@ arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size)
1886 int extensions = 1; 1886 int extensions = 1;
1887 int err = -ENOMEM; 1887 int err = -ENOMEM;
1888 1888
1889 /* currently only 32-bit DMA address space is supported */
1890 if (size > DMA_BIT_MASK(32) + 1)
1891 return ERR_PTR(-ERANGE);
1892
1889 if (!bitmap_size) 1893 if (!bitmap_size)
1890 return ERR_PTR(-EINVAL); 1894 return ERR_PTR(-EINVAL);
1891 1895
@@ -2057,13 +2061,6 @@ static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2057 if (!iommu) 2061 if (!iommu)
2058 return false; 2062 return false;
2059 2063
2060 /*
2061 * currently arm_iommu_create_mapping() takes a max of size_t
2062 * for size param. So check this limit for now.
2063 */
2064 if (size > SIZE_MAX)
2065 return false;
2066
2067 mapping = arm_iommu_create_mapping(dev->bus, dma_base, size); 2064 mapping = arm_iommu_create_mapping(dev->bus, dma_base, size);
2068 if (IS_ERR(mapping)) { 2065 if (IS_ERR(mapping)) {
2069 pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n", 2066 pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n",
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index aa0519eed698..774ef1323554 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -22,8 +22,6 @@
22 * 22 *
23 * These are the low level assembler for performing cache and TLB 23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020. 24 * functions on the arm1020.
25 *
26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
27 */ 25 */
28#include <linux/linkage.h> 26#include <linux/linkage.h>
29#include <linux/init.h> 27#include <linux/init.h>
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index bff4c7f70fd6..ae3c27b71594 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -22,8 +22,6 @@
22 * 22 *
23 * These are the low level assembler for performing cache and TLB 23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020e. 24 * functions on the arm1020e.
25 *
26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
27 */ 25 */
28#include <linux/linkage.h> 26#include <linux/linkage.h>
29#include <linux/init.h> 27#include <linux/init.h>
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index ede8c54ab4aa..32a47cc19076 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -441,9 +441,6 @@ ENTRY(cpu_arm925_set_pte_ext)
441 .type __arm925_setup, #function 441 .type __arm925_setup, #function
442__arm925_setup: 442__arm925_setup:
443 mov r0, #0 443 mov r0, #0
444#if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
445 orr r0,r0,#1 << 7
446#endif
447 444
448 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */ 445 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */
449 orr r0,r0,#1 << 1 @ transparent mode on 446 orr r0,r0,#1 << 1 @ transparent mode on
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index e494d6d6acbe..92e08bf37aad 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -602,7 +602,6 @@ __\name\()_proc_info:
602 PMD_SECT_AP_WRITE | \ 602 PMD_SECT_AP_WRITE | \
603 PMD_SECT_AP_READ 603 PMD_SECT_AP_READ
604 initfn __feroceon_setup, __\name\()_proc_info 604 initfn __feroceon_setup, __\name\()_proc_info
605 .long __feroceon_setup
606 .long cpu_arch_name 605 .long cpu_arch_name
607 .long cpu_elf_name 606 .long cpu_elf_name
608 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 607 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index e1268f905026..e0e23582c8b4 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -54,6 +54,7 @@
54#define SEEN_DATA (1 << (BPF_MEMWORDS + 3)) 54#define SEEN_DATA (1 << (BPF_MEMWORDS + 3))
55 55
56#define FLAG_NEED_X_RESET (1 << 0) 56#define FLAG_NEED_X_RESET (1 << 0)
57#define FLAG_IMM_OVERFLOW (1 << 1)
57 58
58struct jit_ctx { 59struct jit_ctx {
59 const struct bpf_prog *skf; 60 const struct bpf_prog *skf;
@@ -293,6 +294,15 @@ static u16 imm_offset(u32 k, struct jit_ctx *ctx)
293 /* PC in ARM mode == address of the instruction + 8 */ 294 /* PC in ARM mode == address of the instruction + 8 */
294 imm = offset - (8 + ctx->idx * 4); 295 imm = offset - (8 + ctx->idx * 4);
295 296
297 if (imm & ~0xfff) {
298 /*
299 * literal pool is too far, signal it into flags. we
300 * can only detect it on the second pass unfortunately.
301 */
302 ctx->flags |= FLAG_IMM_OVERFLOW;
303 return 0;
304 }
305
296 return imm; 306 return imm;
297} 307}
298 308
@@ -449,10 +459,21 @@ static inline void emit_udiv(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx)
449 return; 459 return;
450 } 460 }
451#endif 461#endif
452 if (rm != ARM_R0) 462
453 emit(ARM_MOV_R(ARM_R0, rm), ctx); 463 /*
464 * For BPF_ALU | BPF_DIV | BPF_K instructions, rm is ARM_R4
465 * (r_A) and rn is ARM_R0 (r_scratch) so load rn first into
466 * ARM_R1 to avoid accidentally overwriting ARM_R0 with rm
467 * before using it as a source for ARM_R1.
468 *
469 * For BPF_ALU | BPF_DIV | BPF_X rm is ARM_R4 (r_A) and rn is
470 * ARM_R5 (r_X) so there is no particular register overlap
471 * issues.
472 */
454 if (rn != ARM_R1) 473 if (rn != ARM_R1)
455 emit(ARM_MOV_R(ARM_R1, rn), ctx); 474 emit(ARM_MOV_R(ARM_R1, rn), ctx);
475 if (rm != ARM_R0)
476 emit(ARM_MOV_R(ARM_R0, rm), ctx);
456 477
457 ctx->seen |= SEEN_CALL; 478 ctx->seen |= SEEN_CALL;
458 emit_mov_i(ARM_R3, (u32)jit_udiv, ctx); 479 emit_mov_i(ARM_R3, (u32)jit_udiv, ctx);
@@ -855,6 +876,14 @@ b_epilogue:
855 default: 876 default:
856 return -1; 877 return -1;
857 } 878 }
879
880 if (ctx->flags & FLAG_IMM_OVERFLOW)
881 /*
882 * this instruction generated an overflow when
883 * trying to access the literal pool, so
884 * delegate this filter to the kernel interpreter.
885 */
886 return -1;
858 } 887 }
859 888
860 /* compute offsets only during the first pass */ 889 /* compute offsets only during the first pass */
@@ -917,7 +946,14 @@ void bpf_jit_compile(struct bpf_prog *fp)
917 ctx.idx = 0; 946 ctx.idx = 0;
918 947
919 build_prologue(&ctx); 948 build_prologue(&ctx);
920 build_body(&ctx); 949 if (build_body(&ctx) < 0) {
950#if __LINUX_ARM_ARCH__ < 7
951 if (ctx.imm_count)
952 kfree(ctx.imms);
953#endif
954 bpf_jit_binary_free(header);
955 goto out;
956 }
921 build_epilogue(&ctx); 957 build_epilogue(&ctx);
922 958
923 flush_icache_range((u32)ctx.target, (u32)(ctx.target + ctx.idx)); 959 flush_icache_range((u32)ctx.target, (u32)(ctx.target + ctx.idx));
diff --git a/arch/arm/xen/mm.c b/arch/arm/xen/mm.c
index 793551d15f1d..498325074a06 100644
--- a/arch/arm/xen/mm.c
+++ b/arch/arm/xen/mm.c
@@ -4,6 +4,7 @@
4#include <linux/gfp.h> 4#include <linux/gfp.h>
5#include <linux/highmem.h> 5#include <linux/highmem.h>
6#include <linux/export.h> 6#include <linux/export.h>
7#include <linux/memblock.h>
7#include <linux/of_address.h> 8#include <linux/of_address.h>
8#include <linux/slab.h> 9#include <linux/slab.h>
9#include <linux/types.h> 10#include <linux/types.h>
@@ -21,6 +22,20 @@
21#include <asm/xen/hypercall.h> 22#include <asm/xen/hypercall.h>
22#include <asm/xen/interface.h> 23#include <asm/xen/interface.h>
23 24
25unsigned long xen_get_swiotlb_free_pages(unsigned int order)
26{
27 struct memblock_region *reg;
28 gfp_t flags = __GFP_NOWARN;
29
30 for_each_memblock(memory, reg) {
31 if (reg->base < (phys_addr_t)0xffffffff) {
32 flags |= __GFP_DMA;
33 break;
34 }
35 }
36 return __get_free_pages(flags, order);
37}
38
24enum dma_cache_op { 39enum dma_cache_op {
25 DMA_UNMAP, 40 DMA_UNMAP,
26 DMA_MAP, 41 DMA_MAP,
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-05 02:38:20 -0500