213 files changed, 4527 insertions, 1156 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5cdee4bc181d..09ebf0ba64fa 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -328,7 +328,7 @@ config ARCH_CLPS711X
 
 config ARCH_CNS3XXX
         bool "Cavium Networks CNS3XXX family"
-        select CPU_V6
+        select CPU_V6K
         select GENERIC_CLOCKEVENTS
         select ARM_GIC
         select MIGHT_HAVE_PCI
@@ -396,6 +396,7 @@ config ARCH_MXC
         select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
         select CLKSRC_MMIO
+        select GENERIC_IRQ_CHIP
         select HAVE_SCHED_CLOCK
         help
           Support for Freescale MXC/iMX-based family of processors
@@ -603,7 +604,6 @@ config ARCH_TEGRA
         select GENERIC_GPIO
         select HAVE_CLK
         select HAVE_SCHED_CLOCK
-        select ARCH_HAS_BARRIERS if CACHE_L2X0
         select ARCH_HAS_CPUFREQ
         help
           This enables support for NVIDIA Tegra based systems (Tegra APX,
@@ -630,6 +630,8 @@ config ARCH_PXA
         select TICK_ONESHOT
         select PLAT_PXA
         select SPARSE_IRQ
+        select AUTO_ZRELADDR
+        select MULTI_IRQ_HANDLER
         help
           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 
@@ -768,6 +770,7 @@ config ARCH_S5PV210
         bool "Samsung S5PV210/S5PC110"
         select CPU_V7
         select ARCH_SPARSEMEM_ENABLE
+        select ARCH_HAS_HOLES_MEMORYMODEL
         select GENERIC_GPIO
         select HAVE_CLK
         select CLKDEV_LOOKUP
@@ -786,6 +789,7 @@ config ARCH_EXYNOS4
         bool "Samsung EXYNOS4"
         select CPU_V7
         select ARCH_SPARSEMEM_ENABLE
+        select ARCH_HAS_HOLES_MEMORYMODEL
         select GENERIC_GPIO
         select HAVE_CLK
         select CLKDEV_LOOKUP
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 7bdd91766d65..3227ca952a12 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -38,12 +38,6 @@ static DEFINE_SPINLOCK(irq_controller_lock);
 /* Address of GIC 0 CPU interface */
 void __iomem *gic_cpu_base_addr __read_mostly;
 
-struct gic_chip_data {
-        unsigned int irq_offset;
-        void __iomem *dist_base;
-        void __iomem *cpu_base;
-};
-
 /*
  * Supported arch specific GIC irq extension.
  * Default make them NULL.
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 5a6ff7c605df..db2cb7d180dc 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -22,6 +22,8 @@ CONFIG_BLK_DEV_INTEGRITY=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_MXS=y
+CONFIG_MACH_MX23EVK=y
+CONFIG_MACH_MX28EVK=y
 CONFIG_MACH_STMP378X_DEVB=y
 CONFIG_MACH_TX28=y
 # CONFIG_ARM_THUMB is not set
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index a5cce242a775..97d31a4663da 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -11,12 +11,12 @@ CONFIG_ARCH_U8500=y
 CONFIG_UX500_SOC_DB5500=y
 CONFIG_UX500_SOC_DB8500=y
 CONFIG_MACH_U8500=y
+CONFIG_MACH_SNOWBALL=y
 CONFIG_MACH_U5500=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
-CONFIG_HOTPLUG_CPU=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8"
@@ -25,8 +25,13 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_NETFILTER=y
 CONFIG_PHONET=y
-CONFIG_PHONET_PIPECTRLR=y
 # CONFIG_WIRELESS is not set
 CONFIG_CAIF=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
@@ -35,6 +40,13 @@ CONFIG_BLK_DEV_RAM_SIZE=65536
 CONFIG_MISC_DEVICES=y
 CONFIG_AB8500_PWM=y
 CONFIG_SENSORS_BH1780=y
+CONFIG_NETDEVICES=y
+CONFIG_SMSC_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMSC911X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
@@ -49,9 +61,9 @@ CONFIG_INPUT_MISC=y
 CONFIG_INPUT_AB8500_PONKEY=y
 # CONFIG_SERIO is not set
 CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_NOMADIK=y
 CONFIG_I2C=y
@@ -64,14 +76,19 @@ CONFIG_GPIO_TC3589X=y
 CONFIG_MFD_STMPE=y
 CONFIG_MFD_TC3589X=y
 CONFIG_AB8500_CORE=y
-CONFIG_REGULATOR=y
 CONFIG_REGULATOR_AB8500=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_MUSB_PIO_ONLY=y
+CONFIG_USB_GADGET=y
+CONFIG_AB8500_USB=y
 CONFIG_MMC=y
+CONFIG_MMC_CLKGATE=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_LM3530=y
 CONFIG_LEDS_LP5521=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AB8500=y
@@ -79,7 +96,6 @@ CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
 CONFIG_STE_DMA40=y
 CONFIG_STAGING=y
-# CONFIG_STAGING_EXCLUDE_BUILD is not set
 CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
@@ -91,6 +107,8 @@ CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_CONFIGFS_FS=m
 # CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_MAGIC_SYSRQ=y
@@ -99,7 +117,5 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 0691f9dcc500..435d3f86c708 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -41,6 +41,12 @@ void gic_secondary_init(unsigned int);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
 void gic_enable_ppi(unsigned int);
+
+struct gic_chip_data {
+        unsigned int irq_offset;
+        void __iomem *dist_base;
+        void __iomem *cpu_base;
+};
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 2721a5814cb9..5a526afb5f18 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -23,6 +23,7 @@ struct pt_regs;
 extern void migrate_irqs(void);
 
 extern void asm_do_IRQ(unsigned int, struct pt_regs *);
+void handle_IRQ(unsigned int, struct pt_regs *);
 void init_IRQ(void);
 
 #endif
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 0f928a131af8..de3dcab8610b 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -67,12 +67,12 @@ int arch_show_interrupts(struct seq_file *p, int prec)
 }
 
 /*
- * do_IRQ handles all hardware IRQ's.  Decoded IRQs should not
- * come via this function.  Instead, they should provide their
- * own 'handler'
+ * handle_IRQ handles all hardware IRQ's.  Decoded IRQs should
+ * not come via this function.  Instead, they should provide their
+ * own 'handler'.  Used by platform code implementing C-based 1st
+ * level decoding.
  */
-asmlinkage void __exception_irq_entry
-asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
+void handle_IRQ(unsigned int irq, struct pt_regs *regs)
 {
         struct pt_regs *old_regs = set_irq_regs(regs);
 
@@ -97,6 +97,15 @@ asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
         set_irq_regs(old_regs);
 }
 
+/*
+ * asm_do_IRQ is the interface to be used from assembly code.
+ */
+asmlinkage void __exception_irq_entry
+asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
+{
+        handle_IRQ(irq, regs);
+}
+
 void set_irq_flags(unsigned int irq, unsigned int iflags)
 {
         unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 85e6390795ac..3e7d1496cb47 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -169,6 +169,8 @@ static struct platform_device *cns3420_pdevs[] __initdata = {
 
 static void __init cns3420_init(void)
 {
+        cns3xxx_l2x0_init();
+
         platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
 
         cns3xxx_ahci_init();
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index da30078a80c1..941a308e1253 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -16,6 +16,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
 #include <mach/cns3xxx.h>
 #include "core.h"
 
@@ -244,3 +245,45 @@ static void __init cns3xxx_timer_init(void)
 struct sys_timer cns3xxx_timer = {
         .init = cns3xxx_timer_init,
 };
+
+#ifdef CONFIG_CACHE_L2X0
+
+void __init cns3xxx_l2x0_init(void)
+{
+        void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
+        u32 val;
+
+        if (WARN_ON(!base))
+                return;
+
+        /*
+         * Tag RAM Control register
+         *
+         * bit[10:8]    - 1 cycle of write accesses latency
+         * bit[6:4]     - 1 cycle of read accesses latency
+         * bit[3:0]     - 1 cycle of setup latency
+         *
+         * 1 cycle of latency for setup, read and write accesses
+         */
+        val = readl(base + L2X0_TAG_LATENCY_CTRL);
+        val &= 0xfffff888;
+        writel(val, base + L2X0_TAG_LATENCY_CTRL);
+
+        /*
+         * Data RAM Control register
+         *
+         * bit[10:8]    - 1 cycles of write accesses latency
+         * bit[6:4]     - 1 cycles of read accesses latency
+         * bit[3:0]     - 1 cycle of setup latency
+         *
+         * 1 cycle of latency for setup, read and write accesses
+         */
+        val = readl(base + L2X0_DATA_LATENCY_CTRL);
+        val &= 0xfffff888;
+        writel(val, base + L2X0_DATA_LATENCY_CTRL);
+
+        /* 32 KiB, 8-way, parity disable */
+        l2x0_init(base, 0x00540000, 0xfe000fff);
+}
+
+#endif /* CONFIG_CACHE_L2X0 */
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index ffeb3a8b73ba..fcd225343c61 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -13,6 +13,12 @@
 
 extern struct sys_timer cns3xxx_timer;
 
+#ifdef CONFIG_CACHE_L2X0
+void __init cns3xxx_l2x0_init(void);
+#else
+static inline void cns3xxx_l2x0_init(void) {}
+#endif /* CONFIG_CACHE_L2X0 */
+
 void __init cns3xxx_map_io(void);
 void __init cns3xxx_init_irq(void);
 void cns3xxx_power_off(void);
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 29671ef07152..bd5394537c88 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -1117,6 +1117,8 @@ static __init int da850_evm_init_cpufreq(void)
 static __init int da850_evm_init_cpufreq(void) { return 0; }
 #endif
 
+#define DA850EVM_SATA_REFCLKPN_RATE     (100 * 1000 * 1000)
+
 static __init void da850_evm_init(void)
 {
         int ret;
@@ -1237,6 +1239,11 @@ static __init void da850_evm_init(void)
         if (ret)
                 pr_warning("da850_evm_init: spi 1 registration failed: %d\n",
                                 ret);
+
+        ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE);
+        if (ret)
+                pr_warning("da850_evm_init: sata registration failed: %d\n",
+                                ret);
 }
 
 #ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index ae653194b645..00861139101d 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -44,7 +44,7 @@ static void __clk_enable(struct clk *clk)
                 __clk_enable(clk->parent);
         if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
                 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
-                                PSC_STATE_ENABLE);
+                                true, clk->flags);
 }
 
 static void __clk_disable(struct clk *clk)
@@ -54,8 +54,7 @@ static void __clk_disable(struct clk *clk)
         if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
             (clk->flags & CLK_PSC))
                 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
-                                (clk->flags & PSC_SWRSTDISABLE) ?
-                                PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
+                                false, clk->flags);
         if (clk->parent)
                 __clk_disable(clk->parent);
 }
@@ -239,8 +238,7 @@ static int __init clk_disable_unused(void)
                 pr_debug("Clocks: disable unused %s\n", ck->name);
 
                 davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
-                                (ck->flags & PSC_SWRSTDISABLE) ?
-                                PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
+                                false, ck->flags);
         }
         spin_unlock_irq(&clockfw_lock);
 
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 50b2482e0ba2..a705f367a84d 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -111,6 +111,7 @@ struct clk {
 #define CLK_PLL                 BIT(4) /* PLL-derived clock */
 #define PRE_PLL                 BIT(5) /* source is before PLL mult/div */
 #define PSC_SWRSTDISABLE        BIT(6) /* Disable state is SwRstDisable */
+#define PSC_FORCE               BIT(7) /* Force module state transtition */
 
 #define CLK(dev, con, ck)       \
         {                       \
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 133aac405853..935dbed5c541 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -58,6 +58,7 @@ static struct pll_data pll0_data = {
 static struct clk ref_clk = {
         .name           = "ref_clk",
         .rate           = DA850_REF_FREQ,
+        .set_rate       = davinci_simple_set_rate,
 };
 
 static struct clk pll0_clk = {
@@ -373,6 +374,14 @@ static struct clk spi1_clk = {
         .flags          = DA850_CLK_ASYNC3,
 };
 
+static struct clk sata_clk = {
+        .name           = "sata",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA850_LPSC1_SATA,
+        .gpsc           = 1,
+        .flags          = PSC_FORCE,
+};
+
 static struct clk_lookup da850_clks[] = {
         CLK(NULL,               "ref",          &ref_clk),
         CLK(NULL,               "pll0",         &pll0_clk),
@@ -419,6 +428,7 @@ static struct clk_lookup da850_clks[] = {
         CLK(NULL,               "usb20",        &usb20_clk),
         CLK("spi_davinci.0",    NULL,           &spi0_clk),
         CLK("spi_davinci.1",    NULL,           &spi1_clk),
+        CLK("ahci",             NULL,           &sata_clk),
         CLK(NULL,               NULL,           NULL),
 };
 
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index fc4e98ea7543..2f7e719636f1 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -14,6 +14,8 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/serial_8250.h>
+#include <linux/ahci_platform.h>
+#include <linux/clk.h>
 
 #include <mach/cputype.h>
 #include <mach/common.h>
@@ -33,6 +35,7 @@
 #define DA8XX_SPI0_BASE                 0x01c41000
 #define DA830_SPI1_BASE                 0x01e12000
 #define DA8XX_LCD_CNTRL_BASE            0x01e13000
+#define DA850_SATA_BASE                 0x01e18000
 #define DA850_MMCSD1_BASE               0x01e1b000
 #define DA8XX_EMAC_CPPI_PORT_BASE       0x01e20000
 #define DA8XX_EMAC_CPGMACSS_BASE        0x01e22000
@@ -842,3 +845,126 @@ int __init da8xx_register_spi(int instance, struct spi_board_info *info,
 
         return platform_device_register(&da8xx_spi_device[instance]);
 }
+
+#ifdef CONFIG_ARCH_DAVINCI_DA850
+
+static struct resource da850_sata_resources[] = {
+        {
+                .start  = DA850_SATA_BASE,
+                .end    = DA850_SATA_BASE + 0x1fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_DA850_SATAINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+/* SATA PHY Control Register offset from AHCI base */
+#define SATA_P0PHYCR_REG        0x178
+
+#define SATA_PHY_MPY(x)         ((x) << 0)
+#define SATA_PHY_LOS(x)         ((x) << 6)
+#define SATA_PHY_RXCDR(x)       ((x) << 10)
+#define SATA_PHY_RXEQ(x)        ((x) << 13)
+#define SATA_PHY_TXSWING(x)     ((x) << 19)
+#define SATA_PHY_ENPLL(x)       ((x) << 31)
+
+static struct clk *da850_sata_clk;
+static unsigned long da850_sata_refclkpn;
+
+/* Supported DA850 SATA crystal frequencies */
+#define KHZ_TO_HZ(freq) ((freq) * 1000)
+static unsigned long da850_sata_xtal[] = {
+        KHZ_TO_HZ(300000),
+        KHZ_TO_HZ(250000),
+        0,                      /* Reserved */
+        KHZ_TO_HZ(187500),
+        KHZ_TO_HZ(150000),
+        KHZ_TO_HZ(125000),
+        KHZ_TO_HZ(120000),
+        KHZ_TO_HZ(100000),
+        KHZ_TO_HZ(75000),
+        KHZ_TO_HZ(60000),
+};
+
+static int da850_sata_init(struct device *dev, void __iomem *addr)
+{
+        int i, ret;
+        unsigned int val;
+
+        da850_sata_clk = clk_get(dev, NULL);
+        if (IS_ERR(da850_sata_clk))
+                return PTR_ERR(da850_sata_clk);
+
+        ret = clk_enable(da850_sata_clk);
+        if (ret)
+                goto err0;
+
+        /* Enable SATA clock receiver */
+        val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
+        val &= ~BIT(0);
+        __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
+
+        /* Get the multiplier needed for 1.5GHz PLL output */
+        for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++)
+                if (da850_sata_xtal[i] == da850_sata_refclkpn)
+                        break;
+
+        if (i == ARRAY_SIZE(da850_sata_xtal)) {
+                ret = -EINVAL;
+                goto err1;
+        }
+
+        val = SATA_PHY_MPY(i + 1) |
+                SATA_PHY_LOS(1) |
+                SATA_PHY_RXCDR(4) |
+                SATA_PHY_RXEQ(1) |
+                SATA_PHY_TXSWING(3) |
+                SATA_PHY_ENPLL(1);
+
+        __raw_writel(val, addr + SATA_P0PHYCR_REG);
+
+        return 0;
+
+err1:
+        clk_disable(da850_sata_clk);
+err0:
+        clk_put(da850_sata_clk);
+        return ret;
+}
+
+static void da850_sata_exit(struct device *dev)
+{
+        clk_disable(da850_sata_clk);
+        clk_put(da850_sata_clk);
+}
+
+static struct ahci_platform_data da850_sata_pdata = {
+        .init   = da850_sata_init,
+        .exit   = da850_sata_exit,
+};
+
+static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device da850_sata_device = {
+        .name   = "ahci",
+        .id     = -1,
+        .dev    = {
+                .platform_data          = &da850_sata_pdata,
+                .dma_mask               = &da850_sata_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(da850_sata_resources),
+        .resource       = da850_sata_resources,
+};
+
+int __init da850_register_sata(unsigned long refclkpn)
+{
+        da850_sata_refclkpn = refclkpn;
+        if (!da850_sata_refclkpn)
+                return -EINVAL;
+
+        return platform_device_register(&da850_sata_device);
+}
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index ad64da713fc8..eaca7d8b9d68 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -57,6 +57,7 @@ extern unsigned int da850_max_speed;
 #define DA8XX_SYSCFG1_BASE      (IO_PHYS + 0x22C000)
 #define DA8XX_SYSCFG1_VIRT(x)   (da8xx_syscfg1_base + (x))
 #define DA8XX_DEEPSLEEP_REG     0x8
+#define DA8XX_PWRDN_REG         0x18
 
 #define DA8XX_PSC0_BASE         0x01c10000
 #define DA8XX_PLL0_BASE         0x01c11000
@@ -89,6 +90,7 @@ int da850_register_cpufreq(char *async_clk);
 int da8xx_register_cpuidle(void);
 void __iomem * __init da8xx_get_mem_ctlr(void);
 int da850_register_pm(struct platform_device *pdev);
+int __init da850_register_sata(unsigned long refclkpn);
 
 extern struct platform_device da8xx_serial_device;
 extern struct emac_platform_data da8xx_emac_pdata;
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 1110fdd77ba4..47fd0bc3d3e7 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -244,12 +244,13 @@
 #define PSC_STATE_ENABLE        3
 
 #define MDSTAT_STATE_MASK       0x1f
+#define MDCTL_FORCE             BIT(31)
 
 #ifndef __ASSEMBLER__
 
 extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
 extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
-                unsigned int id, u32 next_state);
+                unsigned int id, bool enable, u32 flags);
 
 #endif
 
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index a41580400701..1fb6bdff38c1 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -25,6 +25,8 @@
 #include <mach/cputype.h>
 #include <mach/psc.h>
 
+#include "clock.h"
+
 /* Return nonzero iff the domain's clock is active */
 int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
 {
@@ -48,11 +50,12 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
 
 /* Enable or disable a PSC domain */
 void davinci_psc_config(unsigned int domain, unsigned int ctlr,
-                unsigned int id, u32 next_state)
+                unsigned int id, bool enable, u32 flags)
 {
         u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
         void __iomem *psc_base;
         struct davinci_soc_info *soc_info = &davinci_soc_info;
+        u32 next_state = PSC_STATE_ENABLE;
 
         if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
                 pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
@@ -62,9 +65,18 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
 
         psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
 
+        if (!enable) {
+                if (flags & PSC_SWRSTDISABLE)
+                        next_state = PSC_STATE_SWRSTDISABLE;
+                else
+                        next_state = PSC_STATE_DISABLE;
+        }
+
         mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
         mdctl &= ~MDSTAT_STATE_MASK;
         mdctl |= next_state;
+        if (flags & PSC_FORCE)
+                mdctl |= MDCTL_FORCE;
         __raw_writel(mdctl, psc_base + MDCTL + 4 * id);
 
         pdstat = __raw_readl(psc_base + PDSTAT);
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index ae433a052df6..0c77ab99fa16 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -16,7 +16,8 @@ config CPU_EXYNOS4210
           Enable EXYNOS4210 CPU support
 
 config EXYNOS4_MCT
-        bool "Kernel timer support by MCT"
+        bool
+        default y
         help
           Use MCT (Multi Core Timer) as kernel timers
 
@@ -25,6 +26,11 @@ config EXYNOS4_DEV_AHCI
         help
           Compile in platform device definitions for AHCI
 
+config EXYNOS4_SETUP_FIMD0
+        bool
+        help
+          Common setup code for FIMD0.
+
 config EXYNOS4_DEV_PD
         bool
         help
@@ -35,6 +41,11 @@ config EXYNOS4_DEV_SYSMMU
         help
           Common setup code for SYSTEM MMU in EXYNOS4
 
+config EXYNOS4_DEV_DWMCI
+        bool
+        help
+          Compile in platform device definitions for DWMCI
+
 config EXYNOS4_SETUP_I2C1
         bool
         help
@@ -103,6 +114,7 @@ menu "EXYNOS4 Machines"
 config MACH_SMDKC210
         bool "SMDKC210"
         select CPU_EXYNOS4210
+        select S5P_DEV_FIMD0
         select S3C_DEV_RTC
         select S3C_DEV_WDT
         select S3C_DEV_I2C1
@@ -114,6 +126,7 @@ config MACH_SMDKC210
         select SAMSUNG_DEV_BACKLIGHT
         select EXYNOS4_DEV_PD
         select EXYNOS4_DEV_SYSMMU
+        select EXYNOS4_SETUP_FIMD0
         select EXYNOS4_SETUP_I2C1
         select EXYNOS4_SETUP_SDHCI
         help
@@ -122,6 +135,7 @@ config MACH_SMDKC210
 config MACH_SMDKV310
         bool "SMDKV310"
         select CPU_EXYNOS4210
+        select S5P_DEV_FIMD0
         select S3C_DEV_RTC
         select S3C_DEV_WDT
         select S3C_DEV_I2C1
@@ -130,10 +144,12 @@ config MACH_SMDKV310
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
         select SAMSUNG_DEV_BACKLIGHT
+        select EXYNOS4_DEV_AHCI
         select SAMSUNG_DEV_KEYPAD
         select EXYNOS4_DEV_PD
         select SAMSUNG_DEV_PWM
         select EXYNOS4_DEV_SYSMMU
+        select EXYNOS4_SETUP_FIMD0
         select EXYNOS4_SETUP_I2C1
         select EXYNOS4_SETUP_KEYPAD
         select EXYNOS4_SETUP_SDHCI
@@ -157,13 +173,22 @@ config MACH_ARMLEX4210
 config MACH_UNIVERSAL_C210
         bool "Mobile UNIVERSAL_C210 Board"
         select CPU_EXYNOS4210
+        select S5P_GPIO_INT
+        select S5P_DEV_FIMC0
+        select S5P_DEV_FIMC1
+        select S5P_DEV_FIMC2
+        select S5P_DEV_FIMC3
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
         select S3C_DEV_I2C1
+        select S3C_DEV_I2C3
         select S3C_DEV_I2C5
+        select S5P_DEV_MFC
         select S5P_DEV_ONENAND
+        select EXYNOS4_DEV_PD
         select EXYNOS4_SETUP_I2C1
+        select EXYNOS4_SETUP_I2C3
         select EXYNOS4_SETUP_I2C5
         select EXYNOS4_SETUP_SDHCI
         help
@@ -180,13 +205,16 @@ config MACH_NURI
         select S3C_DEV_I2C1
         select S3C_DEV_I2C3
         select S3C_DEV_I2C5
+        select S5P_DEV_MFC
         select S5P_DEV_USB_EHCI
+        select EXYNOS4_DEV_PD
         select EXYNOS4_SETUP_I2C1
         select EXYNOS4_SETUP_I2C3
         select EXYNOS4_SETUP_I2C5
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
         select SAMSUNG_DEV_PWM
+        select SAMSUNG_DEV_ADC
         help
           Machine support for Samsung Mobile NURI Board.
 
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 1366995d8c2c..b7fe1d7b0b1f 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -13,18 +13,13 @@ obj-				:=
 # Core support for EXYNOS4 system
 
 obj-$(CONFIG_CPU_EXYNOS4210)    += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_EXYNOS4210)    += setup-i2c0.o irq-eint.o dma.o
+obj-$(CONFIG_CPU_EXYNOS4210)    += setup-i2c0.o irq-eint.o dma.o pmu.o
 obj-$(CONFIG_PM)                += pm.o sleep.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 
-ifeq ($(CONFIG_EXYNOS4_MCT),y)
-obj-y                           += mct.o
-else
-obj-y                           += time.o
-obj-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
-endif
+obj-$(CONFIG_EXYNOS4_MCT)       += mct.o
 
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 
@@ -42,8 +37,10 @@ obj-y					+= dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)          += dev-ahci.o
 obj-$(CONFIG_EXYNOS4_DEV_PD)            += dev-pd.o
 obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)        += dev-sysmmu.o
+obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
 
 obj-$(CONFIG_EXYNOS4_SETUP_FIMC)        += setup-fimc.o
+obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)       += setup-fimd0.o
 obj-$(CONFIG_EXYNOS4_SETUP_I2C1)        += setup-i2c1.o
 obj-$(CONFIG_EXYNOS4_SETUP_I2C2)        += setup-i2c2.o
 obj-$(CONFIG_EXYNOS4_SETUP_I2C3)        += setup-i2c3.o
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 66494f28bbef..851dea018578 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -528,6 +528,11 @@ static struct clk init_clocks_off[] = {
                 .enable         = exynos4_clk_ip_image_ctrl,
                 .ctrlbit        = (1 << 0),
         }, {
+                .name           = "mfc",
+                .devname        = "s5p-mfc",
+                .enable         = exynos4_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
                 .name           = "i2c",
                 .devname        = "s3c2440-i2c.0",
                 .parent         = &clk_aclk_100.clk,
@@ -731,6 +736,52 @@ static struct clksrc_sources clkset_mout_g2d = {
         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
 };
 
+static struct clk *clkset_mout_mfc0_list[] = {
+        [0] = &clk_mout_mpll.clk,
+        [1] = &clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources clkset_mout_mfc0 = {
+        .sources        = clkset_mout_mfc0_list,
+        .nr_sources     = ARRAY_SIZE(clkset_mout_mfc0_list),
+};
+
+static struct clksrc_clk clk_mout_mfc0 = {
+        .clk    = {
+                .name           = "mout_mfc0",
+        },
+        .sources        = &clkset_mout_mfc0,
+        .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
+};
+
+static struct clk *clkset_mout_mfc1_list[] = {
+        [0] = &clk_mout_epll.clk,
+        [1] = &clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources clkset_mout_mfc1 = {
+        .sources        = clkset_mout_mfc1_list,
+        .nr_sources     = ARRAY_SIZE(clkset_mout_mfc1_list),
+};
+
+static struct clksrc_clk clk_mout_mfc1 = {
+        .clk    = {
+                .name           = "mout_mfc1",
+        },
+        .sources        = &clkset_mout_mfc1,
+        .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
+};
+
+static struct clk *clkset_mout_mfc_list[] = {
+        [0] = &clk_mout_mfc0.clk,
+        [1] = &clk_mout_mfc1.clk,
+};
+
+static struct clksrc_sources clkset_mout_mfc = {
+        .sources        = clkset_mout_mfc_list,
+        .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
+};
+
 static struct clksrc_clk clk_dout_mmc0 = {
         .clk            = {
                 .name           = "dout_mmc0",
@@ -974,6 +1025,14 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
         }, {
                 .clk            = {
+                        .name           = "sclk_mfc",
+                        .devname        = "s5p-mfc",
+                },
+                .sources = &clkset_mout_mfc,
+                .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
+                .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
                         .name           = "sclk_mmc",
                         .devname        = "s3c-sdhci.0",
                         .parent         = &clk_dout_mmc0.clk,
@@ -1049,6 +1108,8 @@ static struct clksrc_clk *sysclks[] = {
         &clk_dout_mmc2,
         &clk_dout_mmc3,
         &clk_dout_mmc4,
+        &clk_mout_mfc0,
+        &clk_mout_mfc1,
 };
 
 static int xtal_rate;
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index bfd621460abf..2d8a40c9e6e5 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -16,12 +16,16 @@
 
 #include <asm/proc-fns.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
 
 #include <plat/cpu.h>
 #include <plat/clock.h>
+#include <plat/devs.h>
 #include <plat/exynos4.h>
+#include <plat/adc-core.h>
 #include <plat/sdhci.h>
 #include <plat/devs.h>
+#include <plat/fb-core.h>
 #include <plat/fimc-core.h>
 #include <plat/iic-core.h>
 
@@ -103,7 +107,17 @@ static struct map_desc exynos4_iodesc[] __initdata = {
                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
-        }
+        }, {
+                .virtual        = (unsigned long)S5P_VA_GIC_CPU,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_GIC_DIST,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        },
 };
 
 static void exynos4_idle(void)
@@ -129,6 +143,8 @@ void __init exynos4_map_io(void)
         exynos4_default_sdhci2();
         exynos4_default_sdhci3();
 
+        s3c_adc_setname("samsung-adc-v3");
+
         s3c_fimc_setname(0, "exynos4-fimc");
         s3c_fimc_setname(1, "exynos4-fimc");
         s3c_fimc_setname(2, "exynos4-fimc");
@@ -138,6 +154,8 @@ void __init exynos4_map_io(void)
         s3c_i2c0_setname("s3c2440-i2c");
         s3c_i2c1_setname("s3c2440-i2c");
         s3c_i2c2_setname("s3c2440-i2c");
+
+        s5p_fb_setname(0, "exynos4-fb");
 }
 
 void __init exynos4_init_clocks(int xtal)
@@ -150,22 +168,23 @@ void __init exynos4_init_clocks(int xtal)
         exynos4_setup_clocks();
 }
 
+static void exynos4_gic_irq_eoi(struct irq_data *d)
+{
+        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+
+        gic_data->cpu_base = S5P_VA_GIC_CPU +
+                            (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+}
+
 void __init exynos4_init_irq(void)
 {
         int irq;
 
-        gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+        gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+        gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
 
         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 
-                /*
-                 * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
-                 * connected to the interrupt combiner. These irqs
-                 * should be initialized to support cascade interrupt.
-                 */
-                if ((irq >= 40) && !(irq == 51) && !(irq == 53))
-                        continue;
-
                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
                                 COMBINER_IRQ(irq, 0));
                 combiner_cascade_irq(irq, IRQ_SPI(irq));
diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c
index 983069a53239..5a9f9c2e53bf 100644
--- a/arch/arm/mach-exynos4/dev-audio.c
+++ b/arch/arm/mach-exynos4/dev-audio.c
@@ -21,6 +21,7 @@
 #include <mach/map.h>
 #include <mach/dma.h>
 #include <mach/irqs.h>
+#include <mach/regs-audss.h>
 
 static const char *rclksrc[] = {
         [0] = "busclk",
@@ -55,6 +56,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
                         .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
                                          | QUIRK_NEED_RSTCLR,
                         .src_clk = rclksrc,
+                        .idma_addr = EXYNOS4_AUDSS_INT_MEM,
                 },
         },
 };
diff --git a/arch/arm/mach-exynos4/dev-dwmci.c b/arch/arm/mach-exynos4/dev-dwmci.c
new file mode 100644
index 000000000000..b025db4bf602
--- /dev/null
+++ b/arch/arm/mach-exynos4/dev-dwmci.c
@@ -0,0 +1,82 @@
+/*
+ * linux/arch/arm/mach-exynos4/dev-dwmci.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Platform device for Synopsys DesignWare Mobile Storage IP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/mmc/dw_mmc.h>
+
+#include <plat/devs.h>
+
+#include <mach/map.h>
+
+static int exynos4_dwmci_get_bus_wd(u32 slot_id)
+{
+        return 4;
+}
+
+static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
+{
+        return 0;
+}
+
+static struct resource exynos4_dwmci_resource[] = {
+        [0] = {
+                .start  = EXYNOS4_PA_DWMCI,
+                .end    = EXYNOS4_PA_DWMCI + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_DWMCI,
+                .end    = IRQ_DWMCI,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct dw_mci_board exynos4_dwci_pdata = {
+        .num_slots                      = 1,
+        .quirks                         = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
+        .bus_hz                         = 80 * 1000 * 1000,
+        .detect_delay_ms        = 200,
+        .init                           = exynos4_dwmci_init,
+        .get_bus_wd                     = exynos4_dwmci_get_bus_wd,
+};
+
+static u64 exynos4_dwmci_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device exynos4_device_dwmci = {
+        .name           = "dw_mmc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(exynos4_dwmci_resource),
+        .resource       = exynos4_dwmci_resource,
+        .dev            = {
+                .dma_mask               = &exynos4_dwmci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data  = &exynos4_dwci_pdata,
+        },
+};
+
+void __init exynos4_dwmci_set_platdata(struct dw_mci_board *pd)
+{
+        struct dw_mci_board *npd;
+
+        npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
+                        &exynos4_device_dwmci);
+
+        if (!npd->init)
+                npd->init = exynos4_dwmci_init;
+        if (!npd->get_bus_wd)
+                npd->get_bus_wd = exynos4_dwmci_get_bus_wd;
+}
diff --git a/arch/arm/mach-exynos4/hotplug.c b/arch/arm/mach-exynos4/hotplug.c
index 2b5909e2ccd3..7490789784c9 100644
--- a/arch/arm/mach-exynos4/hotplug.c
+++ b/arch/arm/mach-exynos4/hotplug.c
@@ -13,9 +13,12 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
+#include <linux/io.h>
 
 #include <asm/cacheflush.h>
 
+#include <mach/regs-pmu.h>
+
 extern volatile int pen_release;
 
 static inline void cpu_enter_lowpower(void)
@@ -58,12 +61,12 @@ static inline void cpu_leave_lowpower(void)
 
 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
-        /*
-         * there is no power-control hardware on this platform, so all
-         * we can do is put the core into WFI; this is safe as the calling
-         * code will have already disabled interrupts
-         */
         for (;;) {
+
+                /* make cpu1 to be turned off at next WFI command */
+                if (cpu == 1)
+                        __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+
                 /*
                  * here's the WFI
                  */
diff --git a/arch/arm/mach-exynos4/include/mach/dwmci.h b/arch/arm/mach-exynos4/include/mach/dwmci.h
new file mode 100644
index 000000000000..7ce657459cc0
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/dwmci.h
@@ -0,0 +1,20 @@
+/* linux/arch/arm/mach-exynos4/include/mach/dwmci.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Synopsys DesignWare Mobile Storage for EXYNOS4210
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_DWMCI_H
+#define __ASM_ARM_ARCH_DWMCI_H __FILE__
+
+#include <linux/mmc/dw_mmc.h>
+
+extern void exynos4_dwmci_set_platdata(struct dw_mci_board *pd);
+
+#endif /* __ASM_ARM_ARCH_DWMCI_H */
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index d8f38c2e5654..d7a1e281ce7a 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -10,6 +10,7 @@
 */
 
 #include <mach/hardware.h>
+#include <mach/map.h>
 #include <asm/hardware/gic.h>
 
                 .macro  disable_fiq
@@ -18,6 +19,10 @@
                 .macro  get_irqnr_preamble, base, tmp
                 ldr     \base, =gic_cpu_base_addr
                 ldr     \base, [\base]
+                mrc     p15, 0, \tmp, c0, c0, 5
+                and     \tmp, \tmp, #3
+                cmp     \tmp, #1
+                addeq   \base, \base, #EXYNOS4_GIC_BANK_OFFSET
                 .endm
 
                 .macro  arch_ret_to_user, tmp1, tmp2
@@ -75,10 +80,4 @@
                 /* As above, this assumes that irqstat and base are preserved.. */
 
                 .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
                 .endm
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index 5d037301d21a..934d2a493982 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -19,40 +19,105 @@
 
 #define IRQ_PPI(x)              S5P_IRQ(x+16)
 
-#define IRQ_LOCALTIMER          IRQ_PPI(13)
-
 /* SPI: Shared Peripheral Interrupt */
 
 #define IRQ_SPI(x)              S5P_IRQ(x+32)
 
-#define IRQ_MCT1                IRQ_SPI(35)
-
-#define IRQ_EINT0               IRQ_SPI(40)
-#define IRQ_EINT1               IRQ_SPI(41)
-#define IRQ_EINT2               IRQ_SPI(42)
-#define IRQ_EINT3               IRQ_SPI(43)
-#define IRQ_USB_HSOTG           IRQ_SPI(44)
-#define IRQ_USB_HOST            IRQ_SPI(45)
-#define IRQ_MODEM_IF            IRQ_SPI(46)
-#define IRQ_ROTATOR             IRQ_SPI(47)
-#define IRQ_JPEG                IRQ_SPI(48)
-#define IRQ_2D                  IRQ_SPI(49)
-#define IRQ_PCIE                IRQ_SPI(50)
-#define IRQ_MCT0                IRQ_SPI(51)
-#define IRQ_MFC                 IRQ_SPI(52)
-#define IRQ_AUDIO_SS            IRQ_SPI(54)
-#define IRQ_AC97                IRQ_SPI(55)
-#define IRQ_SPDIF               IRQ_SPI(56)
-#define IRQ_KEYPAD              IRQ_SPI(57)
-#define IRQ_INTFEEDCTRL_SSS     IRQ_SPI(58)
-#define IRQ_SLIMBUS             IRQ_SPI(59)
-#define IRQ_PMU                 IRQ_SPI(60)
-#define IRQ_TSI                 IRQ_SPI(61)
-#define IRQ_SATA                IRQ_SPI(62)
-#define IRQ_GPS                 IRQ_SPI(63)
+#define IRQ_EINT0               IRQ_SPI(16)
+#define IRQ_EINT1               IRQ_SPI(17)
+#define IRQ_EINT2               IRQ_SPI(18)
+#define IRQ_EINT3               IRQ_SPI(19)
+#define IRQ_EINT4               IRQ_SPI(20)
+#define IRQ_EINT5               IRQ_SPI(21)
+#define IRQ_EINT6               IRQ_SPI(22)
+#define IRQ_EINT7               IRQ_SPI(23)
+#define IRQ_EINT8               IRQ_SPI(24)
+#define IRQ_EINT9               IRQ_SPI(25)
+#define IRQ_EINT10              IRQ_SPI(26)
+#define IRQ_EINT11              IRQ_SPI(27)
+#define IRQ_EINT12              IRQ_SPI(28)
+#define IRQ_EINT13              IRQ_SPI(29)
+#define IRQ_EINT14              IRQ_SPI(30)
+#define IRQ_EINT15              IRQ_SPI(31)
+#define IRQ_EINT16_31           IRQ_SPI(32)
+
+#define IRQ_PDMA0               IRQ_SPI(35)
+#define IRQ_PDMA1               IRQ_SPI(36)
+#define IRQ_TIMER0_VIC          IRQ_SPI(37)
+#define IRQ_TIMER1_VIC          IRQ_SPI(38)
+#define IRQ_TIMER2_VIC          IRQ_SPI(39)
+#define IRQ_TIMER3_VIC          IRQ_SPI(40)
+#define IRQ_TIMER4_VIC          IRQ_SPI(41)
+#define IRQ_MCT_L0              IRQ_SPI(42)
+#define IRQ_WDT                 IRQ_SPI(43)
+#define IRQ_RTC_ALARM           IRQ_SPI(44)
+#define IRQ_RTC_TIC             IRQ_SPI(45)
+#define IRQ_GPIO_XB             IRQ_SPI(46)
+#define IRQ_GPIO_XA             IRQ_SPI(47)
+#define IRQ_MCT_L1              IRQ_SPI(48)
+
+#define IRQ_UART0               IRQ_SPI(52)
+#define IRQ_UART1               IRQ_SPI(53)
+#define IRQ_UART2               IRQ_SPI(54)
+#define IRQ_UART3               IRQ_SPI(55)
+#define IRQ_UART4               IRQ_SPI(56)
+#define IRQ_MCT_G0              IRQ_SPI(57)
+#define IRQ_IIC                 IRQ_SPI(58)
+#define IRQ_IIC1                IRQ_SPI(59)
+#define IRQ_IIC2                IRQ_SPI(60)
+#define IRQ_IIC3                IRQ_SPI(61)
+#define IRQ_IIC4                IRQ_SPI(62)
+#define IRQ_IIC5                IRQ_SPI(63)
+#define IRQ_IIC6                IRQ_SPI(64)
+#define IRQ_IIC7                IRQ_SPI(65)
+
+#define IRQ_USB_HOST            IRQ_SPI(70)
+#define IRQ_USB_HSOTG           IRQ_SPI(71)
+#define IRQ_MODEM_IF            IRQ_SPI(72)
+#define IRQ_HSMMC0              IRQ_SPI(73)
+#define IRQ_HSMMC1              IRQ_SPI(74)
+#define IRQ_HSMMC2              IRQ_SPI(75)
+#define IRQ_HSMMC3              IRQ_SPI(76)
+#define IRQ_DWMCI               IRQ_SPI(77)
+
+#define IRQ_MIPICSI0            IRQ_SPI(78)
+
+#define IRQ_MIPICSI1            IRQ_SPI(80)
+
+#define IRQ_ONENAND_AUDI        IRQ_SPI(82)
+#define IRQ_ROTATOR             IRQ_SPI(83)
+#define IRQ_FIMC0               IRQ_SPI(84)
+#define IRQ_FIMC1               IRQ_SPI(85)
+#define IRQ_FIMC2               IRQ_SPI(86)
+#define IRQ_FIMC3               IRQ_SPI(87)
+#define IRQ_JPEG                IRQ_SPI(88)
+#define IRQ_2D                  IRQ_SPI(89)
+#define IRQ_PCIE                IRQ_SPI(90)
+
+#define IRQ_MFC                 IRQ_SPI(94)
+
+#define IRQ_AUDIO_SS            IRQ_SPI(96)
+#define IRQ_I2S0                IRQ_SPI(97)
+#define IRQ_I2S1                IRQ_SPI(98)
+#define IRQ_I2S2                IRQ_SPI(99)
+#define IRQ_AC97                IRQ_SPI(100)
+
+#define IRQ_SPDIF               IRQ_SPI(104)
+#define IRQ_ADC0                IRQ_SPI(105)
+#define IRQ_PEN0                IRQ_SPI(106)
+#define IRQ_ADC1                IRQ_SPI(107)
+#define IRQ_PEN1                IRQ_SPI(108)
+#define IRQ_KEYPAD              IRQ_SPI(109)
+#define IRQ_PMU                 IRQ_SPI(110)
+#define IRQ_GPS                 IRQ_SPI(111)
+#define IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
+#define IRQ_SLIMBUS             IRQ_SPI(113)
+
+#define IRQ_TSI                 IRQ_SPI(115)
+#define IRQ_SATA                IRQ_SPI(116)
 
 #define MAX_IRQ_IN_COMBINER     8
-#define COMBINER_GROUP(x)       ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64))
+#define COMBINER_GROUP(x)       ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
 #define COMBINER_IRQ(x, y)      (COMBINER_GROUP(x) + y)
 
 #define IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(4, 0)
@@ -73,75 +138,14 @@
 #define IRQ_SYSMMU_MFC_M1_0     COMBINER_IRQ(5, 6)
 #define IRQ_SYSMMU_PCIE_0       COMBINER_IRQ(5, 7)
 
-#define IRQ_PDMA0               COMBINER_IRQ(21, 0)
-#define IRQ_PDMA1               COMBINER_IRQ(21, 1)
-
-#define IRQ_TIMER0_VIC          COMBINER_IRQ(22, 0)
-#define IRQ_TIMER1_VIC          COMBINER_IRQ(22, 1)
-#define IRQ_TIMER2_VIC          COMBINER_IRQ(22, 2)
-#define IRQ_TIMER3_VIC          COMBINER_IRQ(22, 3)
-#define IRQ_TIMER4_VIC          COMBINER_IRQ(22, 4)
-
-#define IRQ_RTC_ALARM           COMBINER_IRQ(23, 0)
-#define IRQ_RTC_TIC             COMBINER_IRQ(23, 1)
-
-#define IRQ_GPIO_XB             COMBINER_IRQ(24, 0)
-#define IRQ_GPIO_XA             COMBINER_IRQ(24, 1)
-
-#define IRQ_UART0               COMBINER_IRQ(26, 0)
-#define IRQ_UART1               COMBINER_IRQ(26, 1)
-#define IRQ_UART2               COMBINER_IRQ(26, 2)
-#define IRQ_UART3               COMBINER_IRQ(26, 3)
-#define IRQ_UART4               COMBINER_IRQ(26, 4)
-
-#define IRQ_IIC                 COMBINER_IRQ(27, 0)
-#define IRQ_IIC1                COMBINER_IRQ(27, 1)
-#define IRQ_IIC2                COMBINER_IRQ(27, 2)
-#define IRQ_IIC3                COMBINER_IRQ(27, 3)
-#define IRQ_IIC4                COMBINER_IRQ(27, 4)
-#define IRQ_IIC5                COMBINER_IRQ(27, 5)
-#define IRQ_IIC6                COMBINER_IRQ(27, 6)
-#define IRQ_IIC7                COMBINER_IRQ(27, 7)
-
-#define IRQ_HSMMC0              COMBINER_IRQ(29, 0)
-#define IRQ_HSMMC1              COMBINER_IRQ(29, 1)
-#define IRQ_HSMMC2              COMBINER_IRQ(29, 2)
-#define IRQ_HSMMC3              COMBINER_IRQ(29, 3)
-
-#define IRQ_MIPI_CSIS0          COMBINER_IRQ(30, 0)
-#define IRQ_MIPI_CSIS1          COMBINER_IRQ(30, 1)
-
-#define IRQ_FIMC0               COMBINER_IRQ(32, 0)
-#define IRQ_FIMC1               COMBINER_IRQ(32, 1)
-#define IRQ_FIMC2               COMBINER_IRQ(33, 0)
-#define IRQ_FIMC3               COMBINER_IRQ(33, 1)
-
-#define IRQ_ONENAND_AUDI        COMBINER_IRQ(34, 0)
-
-#define IRQ_MCT_L1              COMBINER_IRQ(35, 3)
-
-#define IRQ_EINT4               COMBINER_IRQ(37, 0)
-#define IRQ_EINT5               COMBINER_IRQ(37, 1)
-#define IRQ_EINT6               COMBINER_IRQ(37, 2)
-#define IRQ_EINT7               COMBINER_IRQ(37, 3)
-#define IRQ_EINT8               COMBINER_IRQ(38, 0)
-
-#define IRQ_EINT9               COMBINER_IRQ(38, 1)
-#define IRQ_EINT10              COMBINER_IRQ(38, 2)
-#define IRQ_EINT11              COMBINER_IRQ(38, 3)
-#define IRQ_EINT12              COMBINER_IRQ(38, 4)
-#define IRQ_EINT13              COMBINER_IRQ(38, 5)
-#define IRQ_EINT14              COMBINER_IRQ(38, 6)
-#define IRQ_EINT15              COMBINER_IRQ(38, 7)
-
-#define IRQ_EINT16_31           COMBINER_IRQ(39, 0)
-
-#define IRQ_MCT_L0              COMBINER_IRQ(51, 0)
+#define IRQ_FIMD0_FIFO          COMBINER_IRQ(11, 0)
+#define IRQ_FIMD0_VSYNC         COMBINER_IRQ(11, 1)
+#define IRQ_FIMD0_SYSTEM        COMBINER_IRQ(11, 2)
 
-#define IRQ_WDT                 COMBINER_IRQ(53, 0)
-#define IRQ_MCT_G0              COMBINER_IRQ(53, 4)
+#define MAX_COMBINER_NR         16
 
-#define MAX_COMBINER_NR         54
+#define IRQ_ADC                 IRQ_ADC0
+#define IRQ_TC                  IRQ_PEN0
 
 #define S5P_IRQ_EINT_BASE       COMBINER_IRQ(MAX_COMBINER_NR, 0)
 
@@ -155,6 +159,6 @@
 #define IRQ_GPIO_END            (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
 
 /* Set the default NR_IRQS */
-#define NR_IRQS                 (IRQ_GPIO_END)
+#define NR_IRQS                 (IRQ_GPIO_END + 64)
 
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index 0009e77a05fc..d32296dc65e2 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -57,12 +57,14 @@
 
 #define EXYNOS4_PA_DMC0                 0x10400000
 
-#define EXYNOS4_PA_COMBINER             0x10448000
+#define EXYNOS4_PA_COMBINER             0x10440000
+
+#define EXYNOS4_PA_GIC_CPU              0x10480000
+#define EXYNOS4_PA_GIC_DIST             0x10490000
+#define EXYNOS4_GIC_BANK_OFFSET         0x8000
 
 #define EXYNOS4_PA_COREPERI             0x10500000
-#define EXYNOS4_PA_GIC_CPU              0x10500100
 #define EXYNOS4_PA_TWD                  0x10500600
-#define EXYNOS4_PA_GIC_DIST             0x10501000
 #define EXYNOS4_PA_L2CC                 0x10502000
 
 #define EXYNOS4_PA_MDMA                 0x10810000
@@ -93,7 +95,10 @@
 #define EXYNOS4_PA_MIPI_CSIS0           0x11880000
 #define EXYNOS4_PA_MIPI_CSIS1           0x11890000
 
+#define EXYNOS4_PA_FIMD0                0x11C00000
+
 #define EXYNOS4_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
+#define EXYNOS4_PA_DWMCI                0x12550000
 
 #define EXYNOS4_PA_SATA                 0x12560000
 #define EXYNOS4_PA_SATAPHY              0x125D0000
@@ -103,11 +108,15 @@
 
 #define EXYNOS4_PA_EHCI                 0x12580000
 #define EXYNOS4_PA_HSPHY                0x125B0000
+#define EXYNOS4_PA_MFC                  0x13400000
 
 #define EXYNOS4_PA_UART                 0x13800000
 
 #define EXYNOS4_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
 
+#define EXYNOS4_PA_ADC                  0x13910000
+#define EXYNOS4_PA_ADC1                 0x13911000
+
 #define EXYNOS4_PA_AC97                 0x139A0000
 
 #define EXYNOS4_PA_SPDIF                0x139B0000
@@ -130,6 +139,8 @@
 #define S3C_PA_IIC5                     EXYNOS4_PA_IIC(5)
 #define S3C_PA_IIC6                     EXYNOS4_PA_IIC(6)
 #define S3C_PA_IIC7                     EXYNOS4_PA_IIC(7)
+#define SAMSUNG_PA_ADC                  EXYNOS4_PA_ADC
+#define SAMSUNG_PA_ADC1                 EXYNOS4_PA_ADC1
 #define S3C_PA_RTC                      EXYNOS4_PA_RTC
 #define S3C_PA_WDT                      EXYNOS4_PA_WATCHDOG
 
@@ -140,10 +151,12 @@
 #define S5P_PA_FIMC3                    EXYNOS4_PA_FIMC3
 #define S5P_PA_MIPI_CSIS0               EXYNOS4_PA_MIPI_CSIS0
 #define S5P_PA_MIPI_CSIS1               EXYNOS4_PA_MIPI_CSIS1
+#define S5P_PA_FIMD0                    EXYNOS4_PA_FIMD0
 #define S5P_PA_ONENAND                  EXYNOS4_PA_ONENAND
 #define S5P_PA_ONENAND_DMA              EXYNOS4_PA_ONENAND_DMA
 #define S5P_PA_SDRAM                    EXYNOS4_PA_SDRAM
 #define S5P_PA_SROMC                    EXYNOS4_PA_SROMC
+#define S5P_PA_MFC                      EXYNOS4_PA_MFC
 #define S5P_PA_SYSCON                   EXYNOS4_PA_SYSCON
 #define S5P_PA_TIMER                    EXYNOS4_PA_TIMER
 #define S5P_PA_EHCI                     EXYNOS4_PA_EHCI
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h
index f26e46bc06ca..1df3b81f96e8 100644
--- a/arch/arm/mach-exynos4/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos4/include/mach/pm-core.h
@@ -47,3 +47,13 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
 {
         /* nothing here yet */
 }
+
+static inline void s3c_pm_restored_gpios(void)
+{
+        /* nothing here yet */
+}
+
+static inline void s3c_pm_saved_gpios(void)
+{
+        /* nothing here yet */
+}
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h
new file mode 100644
index 000000000000..a952904b010e
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/pmu.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * EXYNOS4210 - PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_PMU_H
+#define __ASM_ARCH_PMU_H __FILE__
+
+enum sys_powerdown {
+        SYS_AFTR,
+        SYS_LPA,
+        SYS_SLEEP,
+        NUM_SYS_POWERDOWN,
+};
+
+extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
+
+#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-audss.h b/arch/arm/mach-exynos4/include/mach/regs-audss.h
new file mode 100644
index 000000000000..ca5a8b64218a
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-audss.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-exynos4/include/mach/regs-audss.h
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ *              http://www.samsung.com
+ *
+ * Exynos4 Audio SubSystem clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_AUDSS_H
+#define __PLAT_REGS_AUDSS_H __FILE__
+
+#define EXYNOS4_AUDSS_INT_MEM   (0x03000000)
+
+#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index 6e311c1157f5..d493fdb422ff 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -25,6 +25,9 @@
 #define S5P_CLKDIV_STAT_RIGHTBUS        S5P_CLKREG(0x08600)
 #define S5P_CLKGATE_IP_RIGHTBUS         S5P_CLKREG(0x08800)
 
+#define S5P_EPLL_LOCK                   S5P_CLKREG(0x0C010)
+#define S5P_VPLL_LOCK                   S5P_CLKREG(0x0C020)
+
 #define S5P_EPLL_CON0                   S5P_CLKREG(0x0C110)
 #define S5P_EPLL_CON1                   S5P_CLKREG(0x0C114)
 #define S5P_VPLL_CON0                   S5P_CLKREG(0x0C120)
@@ -33,7 +36,9 @@
 #define S5P_CLKSRC_TOP0                 S5P_CLKREG(0x0C210)
 #define S5P_CLKSRC_TOP1                 S5P_CLKREG(0x0C214)
 #define S5P_CLKSRC_CAM                  S5P_CLKREG(0x0C220)
+#define S5P_CLKSRC_TV                   S5P_CLKREG(0x0C224)
 #define S5P_CLKSRC_MFC                  S5P_CLKREG(0x0C228)
+#define S5P_CLKSRC_G3D                  S5P_CLKREG(0x0C22C)
 #define S5P_CLKSRC_IMAGE                S5P_CLKREG(0x0C230)
 #define S5P_CLKSRC_LCD0                 S5P_CLKREG(0x0C234)
 #define S5P_CLKSRC_LCD1                 S5P_CLKREG(0x0C238)
@@ -61,6 +66,7 @@
 #define S5P_CLKDIV_PERIL3               S5P_CLKREG(0x0C55C)
 #define S5P_CLKDIV_PERIL4               S5P_CLKREG(0x0C560)
 #define S5P_CLKDIV_PERIL5               S5P_CLKREG(0x0C564)
+#define S5P_CLKDIV2_RATIO               S5P_CLKREG(0x0C580)
 
 #define S5P_CLKSRC_MASK_TOP             S5P_CLKREG(0x0C310)
 #define S5P_CLKSRC_MASK_CAM             S5P_CLKREG(0x0C320)
@@ -120,6 +126,12 @@
 #define S5P_APLL_VAL_1000               ((250 << 16) | (6 << 8) | 1)
 #define S5P_APLL_VAL_800                ((200 << 16) | (6 << 8) | 1)
 
+#define S5P_EPLLCON0_ENABLE_SHIFT       (31)
+#define S5P_EPLLCON0_LOCKED_SHIFT       (29)
+
+#define S5P_VPLLCON0_ENABLE_SHIFT       (31)
+#define S5P_VPLLCON0_LOCKED_SHIFT       (29)
+
 #define S5P_CLKSRC_CPU_MUXCORE_SHIFT    (16)
 #define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
 
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index a9643371f8e7..fa49bbb8e7b0 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -158,6 +158,7 @@
 #define S5P_PMU_GPS_CONF                        S5P_PMUREG(0x3CE0)
 
 #define S5P_PMU_SATA_PHY_CONTROL_EN             0x1
+#define S5P_CORE_LOCAL_PWR_EN                   0x3
 #define S5P_INT_LOCAL_PWR_EN                    0x7
 
 #define S5P_CHECK_SLEEP                         0x00000BAD
diff --git a/arch/arm/mach-exynos4/localtimer.c b/arch/arm/mach-exynos4/localtimer.c
deleted file mode 100644
index 6bf3d0ab9627..000000000000
--- a/arch/arm/mach-exynos4/localtimer.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* linux/arch/arm/mach-exynos4/localtimer.c
- *
- * Cloned from linux/arch/arm/mach-realview/localtimer.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/clockchips.h>
-
-#include <asm/irq.h>
-#include <asm/localtimer.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        evt->irq = IRQ_LOCALTIMER;
-        twd_timer_setup(evt);
-        return 0;
-}
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
index 642702bb5b12..43be71b799cb 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -13,10 +13,15 @@
 #include <linux/input.h>
 #include <linux/i2c.h>
 #include <linux/i2c/atmel_mxt_ts.h>
+#include <linux/i2c-gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/gpio.h>
+#include <linux/power/max8903_charger.h>
+#include <linux/power/max17042_battery.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
+#include <linux/mfd/max8997.h>
+#include <linux/mfd/max8997-private.h>
 #include <linux/mmc/host.h>
 #include <linux/fb.h>
 #include <linux/pwm_backlight.h>
@@ -26,6 +31,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
+#include <plat/adc.h>
 #include <plat/regs-serial.h>
 #include <plat/exynos4.h>
 #include <plat/cpu.h>
@@ -35,6 +41,8 @@
 #include <plat/clock.h>
 #include <plat/gpio-cfg.h>
 #include <plat/iic.h>
+#include <plat/mfc.h>
+#include <plat/pd.h>
 
 #include <mach/map.h>
 
@@ -54,6 +62,7 @@
 
 enum fixed_regulator_id {
         FIXED_REG_ID_MMC = 0,
+        FIXED_REG_ID_MAX8903,
 };
 
 static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
@@ -344,10 +353,730 @@ static void __init nuri_tsp_init(void)
         s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
 }
 
+static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
+        REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
+        REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
+        REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
+        REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
+        REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo8_[] = {
+        REGULATOR_SUPPLY("vusb_d", NULL), /* Used by CPU */
+        REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo11_[] = {
+        REGULATOR_SUPPLY("vcc", "platform-lcd"), /* U804 LVDS */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
+        REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
+        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
+        REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
+};
+static struct regulator_consumer_supply __initdata max8997_ldo15_[] = {
+        REGULATOR_SUPPLY("avdd", "3-004a"), /* Touch Screen */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo16_[] = {
+        REGULATOR_SUPPLY("d_sensor", "0-001f"), /* HDC803 */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo18_[] = {
+        REGULATOR_SUPPLY("vdd", "3-004a"), /* Touch Screen */
+};
+static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
+        REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
+        REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
+        REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
+};
+static struct regulator_consumer_supply __initdata max8997_buck4_[] = {
+        REGULATOR_SUPPLY("core", "0-001f"), /* HDC803 */
+};
+static struct regulator_consumer_supply __initdata max8997_buck6_[] = {
+        REGULATOR_SUPPLY("dig_28", "0-001f"), /* pin "7" of HDC803 */
+};
+static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = {
+        REGULATOR_SUPPLY("usb_vbus", NULL), /* CPU's USB OTG */
+};
+static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = {
+        REGULATOR_SUPPLY("usb_vbus", "modemctl"), /* VBUS of Modem */
+};
+
+static struct regulator_consumer_supply __initdata max8997_charger_[] = {
+        REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
+};
+static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = {
+        REGULATOR_SUPPLY("vinchg_stop", NULL), /* for jack interrupt handlers */
+};
+
+static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = {
+        REGULATOR_SUPPLY("gps_clk", "bcm4751"),
+        REGULATOR_SUPPLY("bt_clk", "bcm4330-b1"),
+        REGULATOR_SUPPLY("wifi_clk", "bcm433-b1"),
+};
+
+static struct regulator_init_data __initdata max8997_ldo1_data = {
+        .constraints    = {
+                .name           = "VADC_3.3V_C210",
+                .min_uV         = 3300000,
+                .max_uV         = 3300000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .apply_uV       = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo1_),
+        .consumer_supplies      = max8997_ldo1_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo2_data = {
+        .constraints    = {
+                .name           = "VALIVE_1.1V_C210",
+                .min_uV         = 1100000,
+                .max_uV         = 1100000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .enabled        = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_ldo3_data = {
+        .constraints    = {
+                .name           = "VUSB_1.1V_C210",
+                .min_uV         = 1100000,
+                .max_uV         = 1100000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .apply_uV       = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo3_),
+        .consumer_supplies      = max8997_ldo3_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo4_data = {
+        .constraints    = {
+                .name           = "VMIPI_1.8V",
+                .min_uV         = 1800000,
+                .max_uV         = 1800000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .apply_uV       = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo4_),
+        .consumer_supplies      = max8997_ldo4_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo5_data = {
+        .constraints    = {
+                .name           = "VHSIC_1.2V_C210",
+                .min_uV         = 1200000,
+                .max_uV         = 1200000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .apply_uV       = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo5_),
+        .consumer_supplies      = max8997_ldo5_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo6_data = {
+        .constraints    = {
+                .name           = "VCC_1.8V_PDA",
+                .min_uV         = 1800000,
+                .max_uV         = 1800000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .enabled        = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_ldo7_data = {
+        .constraints    = {
+                .name           = "CAM_ISP_1.8V",
+                .min_uV         = 1800000,
+                .max_uV         = 1800000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .apply_uV       = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo7_),
+        .consumer_supplies      = max8997_ldo7_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo8_data = {
+        .constraints    = {
+                .name           = "VUSB/VDAC_3.3V_C210",
+                .min_uV         = 3300000,
+                .max_uV         = 3300000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .apply_uV       = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo8_),
+        .consumer_supplies      = max8997_ldo8_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo9_data = {
+        .constraints    = {
+                .name           = "VCC_2.8V_PDA",
+                .min_uV         = 2800000,
+                .max_uV         = 2800000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .enabled        = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_ldo10_data = {
+        .constraints    = {
+                .name           = "VPLL_1.1V_C210",
+                .min_uV         = 1100000,
+                .max_uV         = 1100000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_ldo11_data = {
+        .constraints    = {
+                .name           = "LVDS_VDD3.3V",
+                .min_uV         = 3300000,
+                .max_uV         = 3300000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .apply_uV       = 1,
+                .boot_on        = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo11_),
+        .consumer_supplies      = max8997_ldo11_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo12_data = {
+        .constraints    = {
+                .name           = "VT_CAM_1.8V",
+                .min_uV         = 1800000,
+                .max_uV         = 1800000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .apply_uV       = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo12_),
+        .consumer_supplies      = max8997_ldo12_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo13_data = {
+        .constraints    = {
+                .name           = "VTF_2.8V",
+                .min_uV         = 2800000,
+                .max_uV         = 2800000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .apply_uV       = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo13_),
+        .consumer_supplies      = max8997_ldo13_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo14_data = {
+        .constraints    = {
+                .name           = "VCC_3.0V_MOTOR",
+                .min_uV         = 3000000,
+                .max_uV         = 3000000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .apply_uV       = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo14_),
+        .consumer_supplies      = max8997_ldo14_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo15_data = {
+        .constraints    = {
+                .name           = "VTOUCH_ADVV2.8V",
+                .min_uV         = 2800000,
+                .max_uV         = 2800000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo15_),
+        .consumer_supplies      = max8997_ldo15_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo16_data = {
+        .constraints    = {
+                .name           = "CAM_SENSOR_IO_1.8V",
+                .min_uV         = 1800000,
+                .max_uV         = 1800000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .apply_uV       = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo16_),
+        .consumer_supplies      = max8997_ldo16_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo18_data = {
+        .constraints    = {
+                .name           = "VTOUCH_VDD2.8V",
+                .min_uV         = 2800000,
+                .max_uV         = 2800000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .apply_uV       = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo18_),
+        .consumer_supplies      = max8997_ldo18_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo21_data = {
+        .constraints    = {
+                .name           = "VDDQ_M1M2_1.2V",
+                .min_uV         = 1200000,
+                .max_uV         = 1200000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_buck1_data = {
+        .constraints    = {
+                .name           = "VARM_1.2V_C210",
+                .min_uV         = 900000,
+                .max_uV         = 1350000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .always_on      = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies = ARRAY_SIZE(max8997_buck1_),
+        .consumer_supplies = max8997_buck1_,
+};
+
+static struct regulator_init_data __initdata max8997_buck2_data = {
+        .constraints    = {
+                .name           = "VINT_1.1V_C210",
+                .min_uV         = 900000,
+                .max_uV         = 1100000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .always_on      = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies = ARRAY_SIZE(max8997_buck2_),
+        .consumer_supplies = max8997_buck2_,
+};
+
+static struct regulator_init_data __initdata max8997_buck3_data = {
+        .constraints    = {
+                .name           = "VG3D_1.1V_C210",
+                .min_uV         = 900000,
+                .max_uV         = 1100000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies = ARRAY_SIZE(max8997_buck3_),
+        .consumer_supplies = max8997_buck3_,
+};
+
+static struct regulator_init_data __initdata max8997_buck4_data = {
+        .constraints    = {
+                .name           = "CAM_ISP_CORE_1.2V",
+                .min_uV         = 1200000,
+                .max_uV         = 1200000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies = ARRAY_SIZE(max8997_buck4_),
+        .consumer_supplies = max8997_buck4_,
+};
+
+static struct regulator_init_data __initdata max8997_buck5_data = {
+        .constraints    = {
+                .name           = "VMEM_1.2V_C210",
+                .min_uV         = 1200000,
+                .max_uV         = 1200000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .enabled        = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_buck6_data = {
+        .constraints    = {
+                .name           = "CAM_AF_2.8V",
+                .min_uV         = 2800000,
+                .max_uV         = 2800000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies = ARRAY_SIZE(max8997_buck6_),
+        .consumer_supplies = max8997_buck6_,
+};
+
+static struct regulator_init_data __initdata max8997_buck7_data = {
+        .constraints    = {
+                .name           = "VCC_SUB_2.0V",
+                .min_uV         = 2000000,
+                .max_uV         = 2000000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .enabled        = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_32khz_ap_data = {
+        .constraints    = {
+                .name           = "32KHz AP",
+                .always_on      = 1,
+                .state_mem      = {
+                        .enabled        = 1,
+                },
+        },
+        .num_consumer_supplies = ARRAY_SIZE(max8997_32khz_ap_),
+        .consumer_supplies = max8997_32khz_ap_,
+};
+
+static struct regulator_init_data __initdata max8997_32khz_cp_data = {
+        .constraints    = {
+                .name           = "32KHz CP",
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_vichg_data = {
+        .constraints    = {
+                .name           = "VICHG",
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_esafeout1_data = {
+        .constraints    = {
+                .name           = "SAFEOUT1",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_esafeout1_),
+        .consumer_supplies      = max8997_esafeout1_,
+};
+
+static struct regulator_init_data __initdata max8997_esafeout2_data = {
+        .constraints    = {
+                .name           = "SAFEOUT2",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_esafeout2_),
+        .consumer_supplies      = max8997_esafeout2_,
+};
+
+static struct regulator_init_data __initdata max8997_charger_cv_data = {
+        .constraints    = {
+                .name           = "CHARGER_CV",
+                .min_uV         = 4200000,
+                .max_uV         = 4200000,
+                .apply_uV       = 1,
+        },
+};
+
+static struct regulator_init_data __initdata max8997_charger_data = {
+        .constraints    = {
+                .name           = "CHARGER",
+                .min_uA         = 200000,
+                .max_uA         = 950000,
+                .boot_on        = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS |
+                                REGULATOR_CHANGE_CURRENT,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_charger_),
+        .consumer_supplies      = max8997_charger_,
+};
+
+static struct regulator_init_data __initdata max8997_charger_topoff_data = {
+        .constraints    = {
+                .name           = "CHARGER TOPOFF",
+                .min_uA         = 50000,
+                .max_uA         = 200000,
+                .valid_ops_mask = REGULATOR_CHANGE_CURRENT,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(max8997_chg_toff_),
+        .consumer_supplies      = max8997_chg_toff_,
+};
+
+static struct max8997_regulator_data __initdata nuri_max8997_regulators[] = {
+        { MAX8997_LDO1, &max8997_ldo1_data },
+        { MAX8997_LDO2, &max8997_ldo2_data },
+        { MAX8997_LDO3, &max8997_ldo3_data },
+        { MAX8997_LDO4, &max8997_ldo4_data },
+        { MAX8997_LDO5, &max8997_ldo5_data },
+        { MAX8997_LDO6, &max8997_ldo6_data },
+        { MAX8997_LDO7, &max8997_ldo7_data },
+        { MAX8997_LDO8, &max8997_ldo8_data },
+        { MAX8997_LDO9, &max8997_ldo9_data },
+        { MAX8997_LDO10, &max8997_ldo10_data },
+        { MAX8997_LDO11, &max8997_ldo11_data },
+        { MAX8997_LDO12, &max8997_ldo12_data },
+        { MAX8997_LDO13, &max8997_ldo13_data },
+        { MAX8997_LDO14, &max8997_ldo14_data },
+        { MAX8997_LDO15, &max8997_ldo15_data },
+        { MAX8997_LDO16, &max8997_ldo16_data },
+
+        { MAX8997_LDO18, &max8997_ldo18_data },
+        { MAX8997_LDO21, &max8997_ldo21_data },
+
+        { MAX8997_BUCK1, &max8997_buck1_data },
+        { MAX8997_BUCK2, &max8997_buck2_data },
+        { MAX8997_BUCK3, &max8997_buck3_data },
+        { MAX8997_BUCK4, &max8997_buck4_data },
+        { MAX8997_BUCK5, &max8997_buck5_data },
+        { MAX8997_BUCK6, &max8997_buck6_data },
+        { MAX8997_BUCK7, &max8997_buck7_data },
+
+        { MAX8997_EN32KHZ_AP, &max8997_32khz_ap_data },
+        { MAX8997_EN32KHZ_CP, &max8997_32khz_cp_data },
+
+        { MAX8997_ENVICHG, &max8997_vichg_data },
+        { MAX8997_ESAFEOUT1, &max8997_esafeout1_data },
+        { MAX8997_ESAFEOUT2, &max8997_esafeout2_data },
+        { MAX8997_CHARGER_CV, &max8997_charger_cv_data },
+        { MAX8997_CHARGER, &max8997_charger_data },
+        { MAX8997_CHARGER_TOPOFF, &max8997_charger_topoff_data },
+};
+
+static struct max8997_platform_data __initdata nuri_max8997_pdata = {
+        .wakeup                 = 1,
+
+        .num_regulators         = ARRAY_SIZE(nuri_max8997_regulators),
+        .regulators             = nuri_max8997_regulators,
+
+        .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
+        .buck2_gpiodvs = true,
+
+        .buck1_voltage[0] = 1350000, /* 1.35V */
+        .buck1_voltage[1] = 1300000, /* 1.3V */
+        .buck1_voltage[2] = 1250000, /* 1.25V */
+        .buck1_voltage[3] = 1200000, /* 1.2V */
+        .buck1_voltage[4] = 1150000, /* 1.15V */
+        .buck1_voltage[5] = 1100000, /* 1.1V */
+        .buck1_voltage[6] = 1000000, /* 1.0V */
+        .buck1_voltage[7] = 950000, /* 0.95V */
+
+        .buck2_voltage[0] = 1100000, /* 1.1V */
+        .buck2_voltage[1] = 1000000, /* 1.0V */
+        .buck2_voltage[2] = 950000, /* 0.95V */
+        .buck2_voltage[3] = 900000, /* 0.9V */
+        .buck2_voltage[4] = 1100000, /* 1.1V */
+        .buck2_voltage[5] = 1000000, /* 1.0V */
+        .buck2_voltage[6] = 950000, /* 0.95V */
+        .buck2_voltage[7] = 900000, /* 0.9V */
+
+        .buck5_voltage[0] = 1200000, /* 1.2V */
+        .buck5_voltage[1] = 1200000, /* 1.2V */
+        .buck5_voltage[2] = 1200000, /* 1.2V */
+        .buck5_voltage[3] = 1200000, /* 1.2V */
+        .buck5_voltage[4] = 1200000, /* 1.2V */
+        .buck5_voltage[5] = 1200000, /* 1.2V */
+        .buck5_voltage[6] = 1200000, /* 1.2V */
+        .buck5_voltage[7] = 1200000, /* 1.2V */
+};
+
 /* GPIO I2C 5 (PMIC) */
+enum { I2C5_MAX8997 };
 static struct i2c_board_info i2c5_devs[] __initdata = {
-        /* max8997, To be updated */
+        [I2C5_MAX8997] = {
+                I2C_BOARD_INFO("max8997", 0xCC >> 1),
+                .platform_data  = &nuri_max8997_pdata,
+        },
+};
+
+static struct max17042_platform_data nuri_battery_platform_data = {
+};
+
+/* GPIO I2C 9 (Fuel Gauge) */
+static struct i2c_gpio_platform_data i2c9_gpio_data = {
+        .sda_pin                = EXYNOS4_GPY4(0),      /* XM0ADDR_8 */
+        .scl_pin                = EXYNOS4_GPY4(1),      /* XM0ADDR_9 */
+};
+static struct platform_device i2c9_gpio = {
+        .name                   = "i2c-gpio",
+        .id                     = 9,
+        .dev                    = {
+                .platform_data  = &i2c9_gpio_data,
+        },
 };
+enum { I2C9_MAX17042};
+static struct i2c_board_info i2c9_devs[] __initdata = {
+        [I2C9_MAX17042] = {
+                I2C_BOARD_INFO("max17042", 0x36),
+                .platform_data = &nuri_battery_platform_data,
+        },
+};
+
+/* MAX8903 Secondary Charger */
+static struct regulator_consumer_supply supplies_max8903[] = {
+        REGULATOR_SUPPLY("vinchg2", "charger-manager.0"),
+};
+
+static struct regulator_init_data max8903_charger_en_data = {
+        .constraints = {
+                .name           = "VOUT_CHARGER",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .boot_on        = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(supplies_max8903),
+        .consumer_supplies = supplies_max8903,
+};
+
+static struct fixed_voltage_config max8903_charger_en = {
+        .supply_name = "VOUT_CHARGER",
+        .microvolts = 5000000, /* Assume 5VDC */
+        .gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */
+        .enable_high = 0, /* Enable = Low */
+        .enabled_at_boot = 1,
+        .init_data = &max8903_charger_en_data,
+};
+
+static struct platform_device max8903_fixed_reg_dev = {
+        .name = "reg-fixed-voltage",
+        .id = FIXED_REG_ID_MAX8903,
+        .dev = { .platform_data = &max8903_charger_en },
+};
+
+static struct max8903_pdata nuri_max8903 = {
+        /*
+         * cen: don't control with the driver, let it be
+         * controlled by regulator above
+         */
+        .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */
+        /* uok, usus: not connected */
+        .chg = EXYNOS4_GPE2(0), /* TA_nCHG */
+        /* flt: vcc_1.8V_pda */
+        .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
+
+        .dc_valid = true,
+        .usb_valid = false, /* USB is not wired to MAX8903 */
+};
+
+static struct platform_device nuri_max8903_device = {
+        .name                   = "max8903-charger",
+        .dev                    = {
+                .platform_data  = &nuri_max8903,
+        },
+};
+
+static struct device *nuri_cm_devices[] = {
+        &s3c_device_i2c5.dev,
+        &s3c_device_adc.dev,
+        NULL, /* Reserved for UART */
+        NULL,
+};
+
+static void __init nuri_power_init(void)
+{
+        int gpio;
+        int irq_base = IRQ_GPIO_END + 1;
+        int ta_en = 0;
+
+        nuri_max8997_pdata.irq_base = irq_base;
+        irq_base += MAX8997_IRQ_NR;
+
+        gpio = EXYNOS4_GPX0(7);
+        gpio_request(gpio, "AP_PMIC_IRQ");
+        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+        gpio = EXYNOS4_GPX2(3);
+        gpio_request(gpio, "FUEL_ALERT");
+        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+        gpio = nuri_max8903.dok;
+        gpio_request(gpio, "TA_nCONNECTED");
+        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        ta_en = gpio_get_value(gpio) ? 0 : 1;
+
+        gpio = nuri_max8903.chg;
+        gpio_request(gpio, "TA_nCHG");
+        gpio_direction_input(gpio);
+
+        gpio = nuri_max8903.dcm;
+        gpio_request(gpio, "CURR_ADJ");
+        gpio_direction_output(gpio, ta_en);
+}
 
 /* USB EHCI */
 static struct s5p_ehci_platdata nuri_ehci_pdata;
@@ -361,6 +1090,7 @@ static void __init nuri_ehci_init(void)
 
 static struct platform_device *nuri_devices[] __initdata = {
         /* Samsung Platform Devices */
+        &s3c_device_i2c5, /* PMIC should initialize first */
         &emmc_fixed_voltage,
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc2,
@@ -369,11 +1099,20 @@ static struct platform_device *nuri_devices[] __initdata = {
         &s3c_device_timer[0],
         &s5p_device_ehci,
         &s3c_device_i2c3,
+        &i2c9_gpio,
+        &s3c_device_adc,
+        &s3c_device_rtc,
+        &s5p_device_mfc,
+        &s5p_device_mfc_l,
+        &s5p_device_mfc_r,
+        &exynos4_device_pd[PD_MFC],
 
         /* NURI Devices */
         &nuri_gpio_keys,
         &nuri_lcd_device,
         &nuri_backlight_device,
+        &max8903_fixed_reg_dev,
+        &nuri_max8903_device,
 };
 
 static void __init nuri_map_io(void)
@@ -383,21 +1122,32 @@ static void __init nuri_map_io(void)
         s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
 }
 
+static void __init nuri_reserve(void)
+{
+        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
 static void __init nuri_machine_init(void)
 {
         nuri_sdhci_init();
         nuri_tsp_init();
+        nuri_power_init();
 
         i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
         s3c_i2c3_set_platdata(&i2c3_data);
         i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
+        s3c_i2c5_set_platdata(NULL);
+        i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7));
         i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
+        i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
+        i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
 
         nuri_ehci_init();
         clk_xusbxti.rate = 24000000;
 
         /* Last */
         platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
+        s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
 }
 
 MACHINE_START(NURI, "NURI")
@@ -407,4 +1157,5 @@ MACHINE_START(NURI, "NURI")
         .map_io         = nuri_map_io,
         .init_machine   = nuri_machine_init,
         .timer          = &exynos4_timer,
+        .reserve        = &nuri_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
index f606ea75bf43..a7c65e05c1eb 100644
--- a/arch/arm/mach-exynos4/mach-smdkc210.c
+++ b/arch/arm/mach-exynos4/mach-smdkc210.c
@@ -9,7 +9,9 @@
 */
 
 #include <linux/serial_core.h>
+#include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/lcd.h>
 #include <linux/mmc/host.h>
 #include <linux/platform_device.h>
 #include <linux/smsc911x.h>
@@ -20,11 +22,15 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
+#include <video/platform_lcd.h>
+
 #include <plat/regs-serial.h>
 #include <plat/regs-srom.h>
+#include <plat/regs-fb-v4.h>
 #include <plat/exynos4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
+#include <plat/fb.h>
 #include <plat/sdhci.h>
 #include <plat/iic.h>
 #include <plat/pd.h>
@@ -114,6 +120,67 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+                gpio_free(EXYNOS4_GPD0(1));
+#endif
+                /* fire nRESET on power up */
+                gpio_request(EXYNOS4_GPX0(6), "GPX0");
+
+                gpio_direction_output(EXYNOS4_GPX0(6), 1);
+                mdelay(100);
+
+                gpio_set_value(EXYNOS4_GPX0(6), 0);
+                mdelay(10);
+
+                gpio_set_value(EXYNOS4_GPX0(6), 1);
+                mdelay(10);
+
+                gpio_free(EXYNOS4_GPX0(6));
+        } else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+                gpio_free(EXYNOS4_GPD0(1));
+#endif
+        }
+}
+
+static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
+        .set_power              = lcd_lte480wv_set_power,
+};
+
+static struct platform_device smdkc210_lcd_lte480wv = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s5p_device_fimd0.dev,
+        .dev.platform_data      = &smdkc210_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win0 = {
+        .win_mode = {
+                .left_margin    = 13,
+                .right_margin   = 8,
+                .upper_margin   = 7,
+                .lower_margin   = 5,
+                .hsync_len      = 3,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp                = 32,
+        .default_bpp            = 24,
+};
+
+static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
+        .win[0]         = &smdkc210_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
+
 static struct resource smdkc210_smsc911x_resources[] = {
         [0] = {
                 .start  = EXYNOS4_PA_SROM_BANK(1),
@@ -168,6 +235,8 @@ static struct platform_device *smdkc210_devices[] __initdata = {
         &exynos4_device_pd[PD_GPS],
         &exynos4_device_sysmmu,
         &samsung_asoc_dma,
+        &s5p_device_fimd0,
+        &smdkc210_lcd_lte480wv,
         &smdkc210_smsc911x,
 };
 
@@ -225,6 +294,7 @@ static void __init smdkc210_machine_init(void)
         s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
 
         samsung_bl_set(&smdkc210_bl_gpio_info, &smdkc210_bl_data);
+        s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
 
         platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
 }
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index df1107828abd..ea4149556860 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -184,9 +184,12 @@ static struct platform_device *smdkv310_devices[] __initdata = {
         &exynos4_device_pd[PD_CAM],
         &exynos4_device_pd[PD_TV],
         &exynos4_device_pd[PD_GPS],
+        &exynos4_device_spdif,
         &exynos4_device_sysmmu,
         &samsung_asoc_dma,
+        &samsung_asoc_idma,
         &smdkv310_smsc911x,
+        &exynos4_device_ahci,
 };
 
 static void __init smdkv310_smsc911x_init(void)
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
index 97d329fff2cf..0e280d12301e 100644
--- a/arch/arm/mach-exynos4/mach-universal_c210.c
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -18,6 +18,9 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/max8952.h>
 #include <linux/mmc/host.h>
+#include <linux/i2c-gpio.h>
+#include <linux/i2c/mcs.h>
+#include <linux/i2c/atmel_mxt_ts.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -27,7 +30,10 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+#include <plat/mfc.h>
 #include <plat/sdhci.h>
+#include <plat/pd.h>
 
 #include <mach/map.h>
 
@@ -477,6 +483,96 @@ static struct i2c_board_info i2c5_devs[] __initdata = {
         },
 };
 
+/* I2C3 (TSP) */
+static struct mxt_platform_data qt602240_platform_data = {
+        .x_line         = 19,
+        .y_line         = 11,
+        .x_size         = 800,
+        .y_size         = 480,
+        .blen           = 0x11,
+        .threshold      = 0x28,
+        .voltage        = 2800000,              /* 2.8V */
+        .orient         = MXT_DIAGONAL,
+};
+
+static struct i2c_board_info i2c3_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("qt602240_ts", 0x4a),
+                .platform_data = &qt602240_platform_data,
+        },
+};
+
+static void __init universal_tsp_init(void)
+{
+        int gpio;
+
+        /* TSP_LDO_ON: XMDMADDR_11 */
+        gpio = EXYNOS4_GPE2(3);
+        gpio_request(gpio, "TSP_LDO_ON");
+        gpio_direction_output(gpio, 1);
+        gpio_export(gpio, 0);
+
+        /* TSP_INT: XMDMADDR_7 */
+        gpio = EXYNOS4_GPE1(7);
+        gpio_request(gpio, "TSP_INT");
+
+        s5p_register_gpio_interrupt(gpio);
+        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+        i2c3_devs[0].irq = gpio_to_irq(gpio);
+}
+
+
+/* GPIO I2C 12 (3 Touchkey) */
+static uint32_t touchkey_keymap[] = {
+        /* MCS_KEY_MAP(value, keycode) */
+        MCS_KEY_MAP(0, KEY_MENU),               /* KEY_SEND */
+        MCS_KEY_MAP(1, KEY_BACK),               /* KEY_END */
+};
+
+static struct mcs_platform_data touchkey_data = {
+        .keymap         = touchkey_keymap,
+        .keymap_size    = ARRAY_SIZE(touchkey_keymap),
+        .key_maxval     = 2,
+};
+
+/* GPIO I2C 3_TOUCH 2.8V */
+#define I2C_GPIO_BUS_12         12
+static struct i2c_gpio_platform_data i2c_gpio12_data = {
+        .sda_pin        = EXYNOS4_GPE4(0),      /* XMDMDATA_8 */
+        .scl_pin        = EXYNOS4_GPE4(1),      /* XMDMDATA_9 */
+};
+
+static struct platform_device i2c_gpio12 = {
+        .name           = "i2c-gpio",
+        .id             = I2C_GPIO_BUS_12,
+        .dev            = {
+                .platform_data  = &i2c_gpio12_data,
+        },
+};
+
+static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
+                .platform_data = &touchkey_data,
+        },
+};
+
+static void __init universal_touchkey_init(void)
+{
+        int gpio;
+
+        gpio = EXYNOS4_GPE3(7);                 /* XMDMDATA_7 */
+        gpio_request(gpio, "3_TOUCH_INT");
+        s5p_register_gpio_interrupt(gpio);
+        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+        i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
+
+        gpio = EXYNOS4_GPE3(3);                 /* XMDMDATA_3 */
+        gpio_request(gpio, "3_TOUCH_EN");
+        gpio_direction_output(gpio, 1);
+}
+
 /* GPIO KEYS */
 static struct gpio_keys_button universal_gpio_keys_tables[] = {
         {
@@ -608,15 +704,25 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
 
 static struct platform_device *universal_devices[] __initdata = {
         /* Samsung Platform Devices */
+        &s5p_device_fimc0,
+        &s5p_device_fimc1,
+        &s5p_device_fimc2,
+        &s5p_device_fimc3,
         &mmc0_fixed_voltage,
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc2,
         &s3c_device_hsmmc3,
+        &s3c_device_i2c3,
         &s3c_device_i2c5,
 
         /* Universal Devices */
+        &i2c_gpio12,
         &universal_gpio_keys,
         &s5p_device_onenand,
+        &s5p_device_mfc,
+        &s5p_device_mfc_l,
+        &s5p_device_mfc_r,
+        &exynos4_device_pd[PD_MFC],
 };
 
 static void __init universal_map_io(void)
@@ -626,6 +732,11 @@ static void __init universal_map_io(void)
         s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
 }
 
+static void __init universal_reserve(void)
+{
+        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
 static void __init universal_machine_init(void)
 {
         universal_sdhci_init();
@@ -633,11 +744,20 @@ static void __init universal_machine_init(void)
         i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
         i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
 
+        universal_tsp_init();
+        s3c_i2c3_set_platdata(NULL);
+        i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
+
         s3c_i2c5_set_platdata(NULL);
         i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
 
+        universal_touchkey_init();
+        i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
+                        ARRAY_SIZE(i2c_gpio12_devs));
+
         /* Last */
         platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
+        s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
 }
 
 MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
@@ -647,4 +767,5 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
         .map_io         = universal_map_io,
         .init_machine   = universal_machine_init,
         .timer          = &exynos4_timer,
+        .reserve        = &universal_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index 14ac10b7ec02..1ae059b7ad7b 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -383,8 +383,8 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
                 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
         } else {
                 mct_tick1_event_irq.dev_id = &mct_tick[cpu];
-                irq_set_affinity(IRQ_MCT1, cpumask_of(1));
                 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
+                irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
         }
 }
 
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index b68d5bdf04cf..7c2282c6ba81 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -28,9 +28,12 @@
 
 #include <mach/hardware.h>
 #include <mach/regs-clock.h>
+#include <mach/regs-pmu.h>
 
 extern void exynos4_secondary_startup(void);
 
+#define CPU1_BOOT_REG S5P_VA_SYSRAM
+
 /*
  * control for which core is the next to come out of the secondary
  * boot "holding pen"
@@ -58,6 +61,31 @@ static void __iomem *scu_base_addr(void)
 
 static DEFINE_SPINLOCK(boot_lock);
 
+static void __cpuinit exynos4_gic_secondary_init(void)
+{
+        void __iomem *dist_base = S5P_VA_GIC_DIST +
+                                 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+        void __iomem *cpu_base = S5P_VA_GIC_CPU +
+                                (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+        int i;
+
+        /*
+         * Deal with the banked PPI and SGI interrupts - disable all
+         * PPI interrupts, ensure all SGI interrupts are enabled.
+         */
+        __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
+        __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
+
+        /*
+         * Set priority on PPI and SGI interrupts
+         */
+        for (i = 0; i < 32; i += 4)
+                __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
+
+        __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
+        __raw_writel(1, cpu_base + GIC_CPU_CTRL);
+}
+
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
         /*
@@ -65,7 +93,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
          * core (e.g. timer irq), then they will not have been enabled
          * for us: do so
          */
-        gic_secondary_init(0);
+        exynos4_gic_secondary_init();
 
         /*
          * let the primary processor know we're out of the
@@ -100,16 +128,41 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          */
         write_pen_release(cpu);
 
+        if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
+                __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                             S5P_ARM_CORE1_CONFIGURATION);
+
+                timeout = 10;
+
+                /* wait max 10 ms until cpu1 is on */
+                while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+                        & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
+                        if (timeout-- == 0)
+                                break;
+
+                        mdelay(1);
+                }
+
+                if (timeout == 0) {
+                        printk(KERN_ERR "cpu1 power enable failed");
+                        spin_unlock(&boot_lock);
+                        return -ETIMEDOUT;
+                }
+        }
         /*
          * Send the secondary CPU a soft interrupt, thereby causing
          * the boot monitor to read the system wide flags register,
          * and branch to the address found there.
          */
-        gic_raise_softirq(cpumask_of(cpu), 1);
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
                 smp_rmb();
+
+                __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+                        CPU1_BOOT_REG);
+                gic_raise_softirq(cpumask_of(cpu), 1);
+
                 if (pen_release == -1)
                         break;
 
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 533c28f758ca..bc6ca9482de1 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -18,92 +18,23 @@
 #include <linux/suspend.h>
 #include <linux/syscore_ops.h>
 #include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include <plat/pll.h>
+#include <plat/regs-srom.h>
 
 #include <mach/regs-irq.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-pmu.h>
 #include <mach/pm-core.h>
-
-static struct sleep_save exynos4_sleep[] = {
-        { .reg = S5P_ARM_CORE0_LOWPWR                   , .val = 0x2, },
-        { .reg = S5P_DIS_IRQ_CORE0                      , .val = 0x0, },
-        { .reg = S5P_DIS_IRQ_CENTRAL0                   , .val = 0x0, },
-        { .reg = S5P_ARM_CORE1_LOWPWR                   , .val = 0x2, },
-        { .reg = S5P_DIS_IRQ_CORE1                      , .val = 0x0, },
-        { .reg = S5P_DIS_IRQ_CENTRAL1                   , .val = 0x0, },
-        { .reg = S5P_ARM_COMMON_LOWPWR                  , .val = 0x2, },
-        { .reg = S5P_L2_0_LOWPWR                        , .val = 0x3, },
-        { .reg = S5P_L2_1_LOWPWR                        , .val = 0x3, },
-        { .reg = S5P_CMU_ACLKSTOP_LOWPWR                , .val = 0x0, },
-        { .reg = S5P_CMU_SCLKSTOP_LOWPWR                , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_LOWPWR                   , .val = 0x0, },
-        { .reg = S5P_APLL_SYSCLK_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_MPLL_SYSCLK_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_VPLL_SYSCLK_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_EPLL_SYSCLK_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR       , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR             , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_TV_LOWPWR              , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR             , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR             , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR            , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR            , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR             , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_CAM_LOWPWR               , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_TV_LOWPWR                , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_MFC_LOWPWR               , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_G3D_LOWPWR               , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_LCD0_LOWPWR              , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_LCD1_LOWPWR              , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_MAUDIO_LOWPWR            , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_GPS_LOWPWR               , .val = 0x0, },
-        { .reg = S5P_TOP_BUS_LOWPWR                     , .val = 0x0, },
-        { .reg = S5P_TOP_RETENTION_LOWPWR               , .val = 0x1, },
-        { .reg = S5P_TOP_PWR_LOWPWR                     , .val = 0x3, },
-        { .reg = S5P_LOGIC_RESET_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_ONENAND_MEM_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_MODIMIF_MEM_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_G2D_ACP_MEM_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_USBOTG_MEM_LOWPWR                  , .val = 0x0, },
-        { .reg = S5P_HSMMC_MEM_LOWPWR                   , .val = 0x0, },
-        { .reg = S5P_CSSYS_MEM_LOWPWR                   , .val = 0x0, },
-        { .reg = S5P_SECSS_MEM_LOWPWR                   , .val = 0x0, },
-        { .reg = S5P_PCIE_MEM_LOWPWR                    , .val = 0x0, },
-        { .reg = S5P_SATA_MEM_LOWPWR                    , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_DRAM_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR        , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_GPIO_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_UART_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_MMCA_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_MMCB_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_EBIA_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_EBIB_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR     , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR       , .val = 0x0, },
-        { .reg = S5P_XUSBXTI_LOWPWR                     , .val = 0x0, },
-        { .reg = S5P_XXTI_LOWPWR                        , .val = 0x0, },
-        { .reg = S5P_EXT_REGULATOR_LOWPWR               , .val = 0x0, },
-        { .reg = S5P_GPIO_MODE_LOWPWR                   , .val = 0x0, },
-        { .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR            , .val = 0x0, },
-        { .reg = S5P_CAM_LOWPWR                         , .val = 0x0, },
-        { .reg = S5P_TV_LOWPWR                          , .val = 0x0, },
-        { .reg = S5P_MFC_LOWPWR                         , .val = 0x0, },
-        { .reg = S5P_G3D_LOWPWR                         , .val = 0x0, },
-        { .reg = S5P_LCD0_LOWPWR                        , .val = 0x0, },
-        { .reg = S5P_LCD1_LOWPWR                        , .val = 0x0, },
-        { .reg = S5P_MAUDIO_LOWPWR                      , .val = 0x0, },
-        { .reg = S5P_GPS_LOWPWR                         , .val = 0x0, },
-        { .reg = S5P_GPS_ALIVE_LOWPWR                   , .val = 0x0, },
-};
+#include <mach/pmu.h>
 
 static struct sleep_save exynos4_set_clksrc[] = {
         { .reg = S5P_CLKSRC_MASK_TOP                    , .val = 0x00000001, },
@@ -118,20 +49,28 @@ static struct sleep_save exynos4_set_clksrc[] = {
         { .reg = S5P_CLKSRC_MASK_DMC                    , .val = 0x00010000, },
 };
 
+static struct sleep_save exynos4_epll_save[] = {
+        SAVE_ITEM(S5P_EPLL_CON0),
+        SAVE_ITEM(S5P_EPLL_CON1),
+};
+
+static struct sleep_save exynos4_vpll_save[] = {
+        SAVE_ITEM(S5P_VPLL_CON0),
+        SAVE_ITEM(S5P_VPLL_CON1),
+};
+
 static struct sleep_save exynos4_core_save[] = {
         /* CMU side */
         SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
         SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
         SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
         SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
-        SAVE_ITEM(S5P_EPLL_CON0),
-        SAVE_ITEM(S5P_EPLL_CON1),
-        SAVE_ITEM(S5P_VPLL_CON0),
-        SAVE_ITEM(S5P_VPLL_CON1),
         SAVE_ITEM(S5P_CLKSRC_TOP0),
         SAVE_ITEM(S5P_CLKSRC_TOP1),
         SAVE_ITEM(S5P_CLKSRC_CAM),
+        SAVE_ITEM(S5P_CLKSRC_TV),
         SAVE_ITEM(S5P_CLKSRC_MFC),
+        SAVE_ITEM(S5P_CLKSRC_G3D),
         SAVE_ITEM(S5P_CLKSRC_IMAGE),
         SAVE_ITEM(S5P_CLKSRC_LCD0),
         SAVE_ITEM(S5P_CLKSRC_LCD1),
@@ -158,6 +97,7 @@ static struct sleep_save exynos4_core_save[] = {
         SAVE_ITEM(S5P_CLKDIV_PERIL4),
         SAVE_ITEM(S5P_CLKDIV_PERIL5),
         SAVE_ITEM(S5P_CLKDIV_TOP),
+        SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
         SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
         SAVE_ITEM(S5P_CLKSRC_MASK_TV),
         SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
@@ -166,6 +106,7 @@ static struct sleep_save exynos4_core_save[] = {
         SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
         SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
         SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
+        SAVE_ITEM(S5P_CLKDIV2_RATIO),
         SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
         SAVE_ITEM(S5P_CLKGATE_IP_CAM),
         SAVE_ITEM(S5P_CLKGATE_IP_TV),
@@ -186,8 +127,10 @@ static struct sleep_save exynos4_core_save[] = {
         SAVE_ITEM(S5P_CLKGATE_IP_DMC),
         SAVE_ITEM(S5P_CLKSRC_CPU),
         SAVE_ITEM(S5P_CLKDIV_CPU),
+        SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
         SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
         SAVE_ITEM(S5P_CLKGATE_IP_CPU),
+
         /* GIC side */
         SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
         SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
@@ -270,6 +213,13 @@ static struct sleep_save exynos4_core_save[] = {
         SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
         SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
         SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
+
+        /* SROM side */
+        SAVE_ITEM(S5P_SROM_BW),
+        SAVE_ITEM(S5P_SROM_BC0),
+        SAVE_ITEM(S5P_SROM_BC1),
+        SAVE_ITEM(S5P_SROM_BC2),
+        SAVE_ITEM(S5P_SROM_BC3),
 };
 
 static struct sleep_save exynos4_l2cc_save[] = {
@@ -280,37 +230,11 @@ static struct sleep_save exynos4_l2cc_save[] = {
         SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
 };
 
+/* For Cortex-A9 Diagnostic and Power control register */
+static unsigned int save_arm_register[2];
+
 static int exynos4_cpu_suspend(unsigned long arg)
 {
-        unsigned long tmp;
-        unsigned long mask = 0xFFFFFFFF;
-
-        /* Setting Central Sequence Register for power down mode */
-
-        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
-        tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
-        __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-
-        /* Setting Central Sequence option Register */
-
-        tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
-        tmp &= ~(S5P_USE_MASK);
-        tmp |= S5P_USE_STANDBY_WFI0;
-        __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
-
-        /* Clear all interrupt pending to avoid early wakeup */
-
-        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
-        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
-        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
-
-        /* Disable all interrupt */
-
-        __raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
-        __raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
-        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
-        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
-
         outer_flush_all();
 
         /* issue the standby signal into the pm unit. */
@@ -326,12 +250,14 @@ static void exynos4_pm_prepare(void)
 
         s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
         s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+        s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
+        s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
 
         tmp = __raw_readl(S5P_INFORM1);
 
         /* Set value of power down register for sleep mode */
 
-        s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep));
+        exynos4_sys_powerdown_conf(SYS_SLEEP);
         __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 
         /* ensure at least INFORM0 has the resume address */
@@ -373,12 +299,80 @@ void exynos4_scu_enable(void __iomem *scu_base)
         flush_cache_all();
 }
 
+static unsigned long pll_base_rate;
+
+static void exynos4_restore_pll(void)
+{
+        unsigned long pll_con, locktime, lockcnt;
+        unsigned long pll_in_rate;
+        unsigned int p_div, epll_wait = 0, vpll_wait = 0;
+
+        if (pll_base_rate == 0)
+                return;
+
+        pll_in_rate = pll_base_rate;
+
+        /* EPLL */
+        pll_con = exynos4_epll_save[0].val;
+
+        if (pll_con & (1 << 31)) {
+                pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
+                p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
+
+                pll_in_rate /= 1000000;
+
+                locktime = (3000 / pll_in_rate) * p_div;
+                lockcnt = locktime * 10000 / (10000 / pll_in_rate);
+
+                __raw_writel(lockcnt, S5P_EPLL_LOCK);
+
+                s3c_pm_do_restore_core(exynos4_epll_save,
+                                        ARRAY_SIZE(exynos4_epll_save));
+                epll_wait = 1;
+        }
+
+        pll_in_rate = pll_base_rate;
+
+        /* VPLL */
+        pll_con = exynos4_vpll_save[0].val;
+
+        if (pll_con & (1 << 31)) {
+                pll_in_rate /= 1000000;
+                /* 750us */
+                locktime = 750;
+                lockcnt = locktime * 10000 / (10000 / pll_in_rate);
+
+                __raw_writel(lockcnt, S5P_VPLL_LOCK);
+
+                s3c_pm_do_restore_core(exynos4_vpll_save,
+                                        ARRAY_SIZE(exynos4_vpll_save));
+                vpll_wait = 1;
+        }
+
+        /* Wait PLL locking */
+
+        do {
+                if (epll_wait) {
+                        pll_con = __raw_readl(S5P_EPLL_CON0);
+                        if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
+                                epll_wait = 0;
+                }
+
+                if (vpll_wait) {
+                        pll_con = __raw_readl(S5P_VPLL_CON0);
+                        if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
+                                vpll_wait = 0;
+                }
+        } while (epll_wait || vpll_wait);
+}
+
 static struct sysdev_driver exynos4_pm_driver = {
         .add            = exynos4_pm_add,
 };
 
 static __init int exynos4_pm_drvinit(void)
 {
+        struct clk *pll_base;
         unsigned int tmp;
 
         s3c_pm_init();
@@ -389,12 +383,69 @@ static __init int exynos4_pm_drvinit(void)
         tmp |= ((0xFF << 8) | (0x1F << 1));
         __raw_writel(tmp, S5P_WAKEUP_MASK);
 
+        pll_base = clk_get(NULL, "xtal");
+
+        if (!IS_ERR(pll_base)) {
+                pll_base_rate = clk_get_rate(pll_base);
+                clk_put(pll_base);
+        }
+
         return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
 }
 arch_initcall(exynos4_pm_drvinit);
 
+static int exynos4_pm_suspend(void)
+{
+        unsigned long tmp;
+
+        /* Setting Central Sequence Register for power down mode */
+
+        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+        tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
+        __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+        /* Save Power control register */
+        asm ("mrc p15, 0, %0, c15, c0, 0"
+             : "=r" (tmp) : : "cc");
+        save_arm_register[0] = tmp;
+
+        /* Save Diagnostic register */
+        asm ("mrc p15, 0, %0, c15, c0, 1"
+             : "=r" (tmp) : : "cc");
+        save_arm_register[1] = tmp;
+
+        return 0;
+}
+
 static void exynos4_pm_resume(void)
 {
+        unsigned long tmp;
+
+        /*
+         * If PMU failed while entering sleep mode, WFI will be
+         * ignored by PMU and then exiting cpu_do_idle().
+         * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+         * in this situation.
+         */
+        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+        if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
+                tmp |= S5P_CENTRAL_LOWPWR_CFG;
+                __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+                /* No need to perform below restore code */
+                goto early_wakeup;
+        }
+        /* Restore Power control register */
+        tmp = save_arm_register[0];
+        asm volatile ("mcr p15, 0, %0, c15, c0, 0"
+                      : : "r" (tmp)
+                      : "cc");
+
+        /* Restore Diagnostic register */
+        tmp = save_arm_register[1];
+        asm volatile ("mcr p15, 0, %0, c15, c0, 1"
+                      : : "r" (tmp)
+                      : "cc");
+
         /* For release retention */
 
         __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
@@ -407,6 +458,8 @@ static void exynos4_pm_resume(void)
 
         s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
 
+        exynos4_restore_pll();
+
         exynos4_scu_enable(S5P_VA_SCU);
 
 #ifdef CONFIG_CACHE_L2X0
@@ -415,9 +468,13 @@ static void exynos4_pm_resume(void)
         /* enable L2X0*/
         writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
 #endif
+
+early_wakeup:
+        return;
 }
 
 static struct syscore_ops exynos4_pm_syscore_ops = {
+        .suspend        = exynos4_pm_suspend,
         .resume         = exynos4_pm_resume,
 };
 
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c
new file mode 100644
index 000000000000..7ea9eb2a20d2
--- /dev/null
+++ b/arch/arm/mach-exynos4/pmu.c
@@ -0,0 +1,175 @@
+/* linux/arch/arm/mach-exynos4/pmu.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * EXYNOS4210 - CPU PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include <mach/regs-clock.h>
+#include <mach/pmu.h>
+
+static void __iomem *sys_powerdown_reg[] = {
+        S5P_ARM_CORE0_LOWPWR,
+        S5P_DIS_IRQ_CORE0,
+        S5P_DIS_IRQ_CENTRAL0,
+        S5P_ARM_CORE1_LOWPWR,
+        S5P_DIS_IRQ_CORE1,
+        S5P_DIS_IRQ_CENTRAL1,
+        S5P_ARM_COMMON_LOWPWR,
+        S5P_L2_0_LOWPWR,
+        S5P_L2_1_LOWPWR,
+        S5P_CMU_ACLKSTOP_LOWPWR,
+        S5P_CMU_SCLKSTOP_LOWPWR,
+        S5P_CMU_RESET_LOWPWR,
+        S5P_APLL_SYSCLK_LOWPWR,
+        S5P_MPLL_SYSCLK_LOWPWR,
+        S5P_VPLL_SYSCLK_LOWPWR,
+        S5P_EPLL_SYSCLK_LOWPWR,
+        S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
+        S5P_CMU_RESET_GPSALIVE_LOWPWR,
+        S5P_CMU_CLKSTOP_CAM_LOWPWR,
+        S5P_CMU_CLKSTOP_TV_LOWPWR,
+        S5P_CMU_CLKSTOP_MFC_LOWPWR,
+        S5P_CMU_CLKSTOP_G3D_LOWPWR,
+        S5P_CMU_CLKSTOP_LCD0_LOWPWR,
+        S5P_CMU_CLKSTOP_LCD1_LOWPWR,
+        S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
+        S5P_CMU_CLKSTOP_GPS_LOWPWR,
+        S5P_CMU_RESET_CAM_LOWPWR,
+        S5P_CMU_RESET_TV_LOWPWR,
+        S5P_CMU_RESET_MFC_LOWPWR,
+        S5P_CMU_RESET_G3D_LOWPWR,
+        S5P_CMU_RESET_LCD0_LOWPWR,
+        S5P_CMU_RESET_LCD1_LOWPWR,
+        S5P_CMU_RESET_MAUDIO_LOWPWR,
+        S5P_CMU_RESET_GPS_LOWPWR,
+        S5P_TOP_BUS_LOWPWR,
+        S5P_TOP_RETENTION_LOWPWR,
+        S5P_TOP_PWR_LOWPWR,
+        S5P_LOGIC_RESET_LOWPWR,
+        S5P_ONENAND_MEM_LOWPWR,
+        S5P_MODIMIF_MEM_LOWPWR,
+        S5P_G2D_ACP_MEM_LOWPWR,
+        S5P_USBOTG_MEM_LOWPWR,
+        S5P_HSMMC_MEM_LOWPWR,
+        S5P_CSSYS_MEM_LOWPWR,
+        S5P_SECSS_MEM_LOWPWR,
+        S5P_PCIE_MEM_LOWPWR,
+        S5P_SATA_MEM_LOWPWR,
+        S5P_PAD_RETENTION_DRAM_LOWPWR,
+        S5P_PAD_RETENTION_MAUDIO_LOWPWR,
+        S5P_PAD_RETENTION_GPIO_LOWPWR,
+        S5P_PAD_RETENTION_UART_LOWPWR,
+        S5P_PAD_RETENTION_MMCA_LOWPWR,
+        S5P_PAD_RETENTION_MMCB_LOWPWR,
+        S5P_PAD_RETENTION_EBIA_LOWPWR,
+        S5P_PAD_RETENTION_EBIB_LOWPWR,
+        S5P_PAD_RETENTION_ISOLATION_LOWPWR,
+        S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
+        S5P_XUSBXTI_LOWPWR,
+        S5P_XXTI_LOWPWR,
+        S5P_EXT_REGULATOR_LOWPWR,
+        S5P_GPIO_MODE_LOWPWR,
+        S5P_GPIO_MODE_MAUDIO_LOWPWR,
+        S5P_CAM_LOWPWR,
+        S5P_TV_LOWPWR,
+        S5P_MFC_LOWPWR,
+        S5P_G3D_LOWPWR,
+        S5P_LCD0_LOWPWR,
+        S5P_LCD1_LOWPWR,
+        S5P_MAUDIO_LOWPWR,
+        S5P_GPS_LOWPWR,
+        S5P_GPS_ALIVE_LOWPWR,
+};
+
+static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
+        /* { AFTR, LPA, SLEEP }*/
+        { 0, 0, 2 },    /* ARM_CORE0 */
+        { 0, 0, 0 },    /* ARM_DIS_IRQ_CORE0 */
+        { 0, 0, 0 },    /* ARM_DIS_IRQ_CENTRAL0 */
+        { 0, 0, 2 },    /* ARM_CORE1 */
+        { 0, 0, 0 },    /* ARM_DIS_IRQ_CORE1 */
+        { 0, 0, 0 },    /* ARM_DIS_IRQ_CENTRAL1 */
+        { 0, 0, 2 },    /* ARM_COMMON */
+        { 2, 2, 3 },    /* ARM_CPU_L2_0 */
+        { 2, 2, 3 },    /* ARM_CPU_L2_1 */
+        { 1, 0, 0 },    /* CMU_ACLKSTOP */
+        { 1, 0, 0 },    /* CMU_SCLKSTOP */
+        { 1, 1, 0 },    /* CMU_RESET */
+        { 1, 0, 0 },    /* APLL_SYSCLK */
+        { 1, 0, 0 },    /* MPLL_SYSCLK */
+        { 1, 0, 0 },    /* VPLL_SYSCLK */
+        { 1, 1, 0 },    /* EPLL_SYSCLK */
+        { 1, 1, 0 },    /* CMU_CLKSTOP_GPS_ALIVE */
+        { 1, 1, 0 },    /* CMU_RESET_GPS_ALIVE */
+        { 1, 1, 0 },    /* CMU_CLKSTOP_CAM */
+        { 1, 1, 0 },    /* CMU_CLKSTOP_TV */
+        { 1, 1, 0 },    /* CMU_CLKSTOP_MFC */
+        { 1, 1, 0 },    /* CMU_CLKSTOP_G3D */
+        { 1, 1, 0 },    /* CMU_CLKSTOP_LCD0 */
+        { 1, 1, 0 },    /* CMU_CLKSTOP_LCD1 */
+        { 1, 1, 0 },    /* CMU_CLKSTOP_MAUDIO */
+        { 1, 1, 0 },    /* CMU_CLKSTOP_GPS */
+        { 1, 1, 0 },    /* CMU_RESET_CAM */
+        { 1, 1, 0 },    /* CMU_RESET_TV */
+        { 1, 1, 0 },    /* CMU_RESET_MFC */
+        { 1, 1, 0 },    /* CMU_RESET_G3D */
+        { 1, 1, 0 },    /* CMU_RESET_LCD0 */
+        { 1, 1, 0 },    /* CMU_RESET_LCD1 */
+        { 1, 1, 0 },    /* CMU_RESET_MAUDIO */
+        { 1, 1, 0 },    /* CMU_RESET_GPS */
+        { 3, 0, 0 },    /* TOP_BUS */
+        { 1, 0, 1 },    /* TOP_RETENTION */
+        { 3, 0, 3 },    /* TOP_PWR */
+        { 1, 1, 0 },    /* LOGIC_RESET */
+        { 3, 0, 0 },    /* ONENAND_MEM */
+        { 3, 0, 0 },    /* MODIMIF_MEM */
+        { 3, 0, 0 },    /* G2D_ACP_MEM */
+        { 3, 0, 0 },    /* USBOTG_MEM */
+        { 3, 0, 0 },    /* HSMMC_MEM */
+        { 3, 0, 0 },    /* CSSYS_MEM */
+        { 3, 0, 0 },    /* SECSS_MEM */
+        { 3, 0, 0 },    /* PCIE_MEM */
+        { 3, 0, 0 },    /* SATA_MEM */
+        { 1, 0, 0 },    /* PAD_RETENTION_DRAM */
+        { 1, 1, 0 },    /* PAD_RETENTION_MAUDIO */
+        { 1, 0, 0 },    /* PAD_RETENTION_GPIO */
+        { 1, 0, 0 },    /* PAD_RETENTION_UART */
+        { 1, 0, 0 },    /* PAD_RETENTION_MMCA */
+        { 1, 0, 0 },    /* PAD_RETENTION_MMCB */
+        { 1, 0, 0 },    /* PAD_RETENTION_EBIA */
+        { 1, 0, 0 },    /* PAD_RETENTION_EBIB */
+        { 1, 0, 0 },    /* PAD_RETENTION_ISOLATION */
+        { 1, 0, 0 },    /* PAD_RETENTION_ALV_SEL */
+        { 1, 1, 0 },    /* XUSBXTI */
+        { 1, 1, 0 },    /* XXTI */
+        { 1, 1, 0 },    /* EXT_REGULATOR */
+        { 1, 0, 0 },    /* GPIO_MODE */
+        { 1, 1, 0 },    /* GPIO_MODE_MAUDIO */
+        { 7, 0, 0 },    /* CAM */
+        { 7, 0, 0 },    /* TV */
+        { 7, 0, 0 },    /* MFC */
+        { 7, 0, 0 },    /* G3D */
+        { 7, 0, 0 },    /* LCD0 */
+        { 7, 0, 0 },    /* LCD1 */
+        { 7, 7, 0 },    /* MAUDIO */
+        { 7, 0, 0 },    /* GPS */
+        { 7, 0, 0 },    /* GPS_ALIVE */
+};
+
+void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
+{
+        unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
+
+        for (; count > 0; count--)
+                __raw_writel(sys_powerdown_val[count - 1][mode],
+                                sys_powerdown_reg[count - 1]);
+}
diff --git a/arch/arm/mach-exynos4/setup-fimd0.c b/arch/arm/mach-exynos4/setup-fimd0.c
new file mode 100644
index 000000000000..07a6dbeecdd0
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-fimd0.c
@@ -0,0 +1,43 @@
+/* linux/arch/arm/mach-exynos4/setup-fimd0.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Base Exynos4 FIMD 0 configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/fb.h>
+#include <linux/gpio.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/regs-fb-v4.h>
+
+#include <mach/map.h>
+
+void exynos4_fimd0_gpio_setup_24bpp(void)
+{
+        unsigned int reg;
+
+        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
+        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
+        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
+        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
+
+        /*
+         * Set DISPLAY_CONTROL register for Display path selection.
+         *
+         * DISPLAY_CONTROL[1:0]
+         * ---------------------
+         *  00 | MIE
+         *  01 | MDINE
+         *  10 | FIMD : selected
+         *  11 | FIMD
+         */
+        reg = __raw_readl(S3C_VA_SYS + 0x0210);
+        reg |= (1 << 1);
+        __raw_writel(reg, S3C_VA_SYS + 0x0210);
+}
diff --git a/arch/arm/mach-exynos4/time.c b/arch/arm/mach-exynos4/time.c
deleted file mode 100644
index ebb8f38d5405..000000000000
--- a/arch/arm/mach-exynos4/time.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/* linux/arch/arm/mach-exynos4/time.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 (and compatible) HRT support
- * PWM 2/4 is used for this feature
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/platform_device.h>
-
-#include <asm/smp_twd.h>
-
-#include <mach/map.h>
-#include <plat/regs-timer.h>
-#include <asm/mach/time.h>
-
-static unsigned long clock_count_per_tick;
-
-static struct clk *tin2;
-static struct clk *tin4;
-static struct clk *tdiv2;
-static struct clk *tdiv4;
-static struct clk *timerclk;
-
-static void exynos4_pwm_stop(unsigned int pwm_id)
-{
-        unsigned long tcon;
-
-        tcon = __raw_readl(S3C2410_TCON);
-
-        switch (pwm_id) {
-        case 2:
-                tcon &= ~S3C2410_TCON_T2START;
-                break;
-        case 4:
-                tcon &= ~S3C2410_TCON_T4START;
-                break;
-        default:
-                break;
-        }
-        __raw_writel(tcon, S3C2410_TCON);
-}
-
-static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt)
-{
-        unsigned long tcon;
-
-        tcon = __raw_readl(S3C2410_TCON);
-
-        /* timers reload after counting zero, so reduce the count by 1 */
-        tcnt--;
-
-        /* ensure timer is stopped... */
-        switch (pwm_id) {
-        case 2:
-                tcon &= ~(0xf<<12);
-                tcon |= S3C2410_TCON_T2MANUALUPD;
-
-                __raw_writel(tcnt, S3C2410_TCNTB(2));
-                __raw_writel(tcnt, S3C2410_TCMPB(2));
-                __raw_writel(tcon, S3C2410_TCON);
-
-                break;
-        case 4:
-                tcon &= ~(7<<20);
-                tcon |= S3C2410_TCON_T4MANUALUPD;
-
-                __raw_writel(tcnt, S3C2410_TCNTB(4));
-                __raw_writel(tcnt, S3C2410_TCMPB(4));
-                __raw_writel(tcon, S3C2410_TCON);
-
-                break;
-        default:
-                break;
-        }
-}
-
-static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic)
-{
-        unsigned long tcon;
-
-        tcon  = __raw_readl(S3C2410_TCON);
-
-        switch (pwm_id) {
-        case 2:
-                tcon |= S3C2410_TCON_T2START;
-                tcon &= ~S3C2410_TCON_T2MANUALUPD;
-
-                if (periodic)
-                        tcon |= S3C2410_TCON_T2RELOAD;
-                else
-                        tcon &= ~S3C2410_TCON_T2RELOAD;
-                break;
-        case 4:
-                tcon |= S3C2410_TCON_T4START;
-                tcon &= ~S3C2410_TCON_T4MANUALUPD;
-
-                if (periodic)
-                        tcon |= S3C2410_TCON_T4RELOAD;
-                else
-                        tcon &= ~S3C2410_TCON_T4RELOAD;
-                break;
-        default:
-                break;
-        }
-        __raw_writel(tcon, S3C2410_TCON);
-}
-
-static int exynos4_pwm_set_next_event(unsigned long cycles,
-                                        struct clock_event_device *evt)
-{
-        exynos4_pwm_init(2, cycles);
-        exynos4_pwm_start(2, 0);
-        return 0;
-}
-
-static void exynos4_pwm_set_mode(enum clock_event_mode mode,
-                                struct clock_event_device *evt)
-{
-        exynos4_pwm_stop(2);
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                exynos4_pwm_init(2, clock_count_per_tick);
-                exynos4_pwm_start(2, 1);
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                break;
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
-}
-
-static struct clock_event_device pwm_event_device = {
-        .name           = "pwm_timer2",
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .rating         = 200,
-        .shift          = 32,
-        .set_next_event = exynos4_pwm_set_next_event,
-        .set_mode       = exynos4_pwm_set_mode,
-};
-
-irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = &pwm_event_device;
-
-        evt->event_handler(evt);
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction exynos4_clock_event_irq = {
-        .name           = "pwm_timer2_irq",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = exynos4_clock_event_isr,
-};
-
-static void __init exynos4_clockevent_init(void)
-{
-        unsigned long pclk;
-        unsigned long clock_rate;
-        struct clk *tscaler;
-
-        pclk = clk_get_rate(timerclk);
-
-        /* configure clock tick */
-
-        tscaler = clk_get_parent(tdiv2);
-
-        clk_set_rate(tscaler, pclk / 2);
-        clk_set_rate(tdiv2, pclk / 2);
-        clk_set_parent(tin2, tdiv2);
-
-        clock_rate = clk_get_rate(tin2);
-
-        clock_count_per_tick = clock_rate / HZ;
-
-        pwm_event_device.mult =
-                div_sc(clock_rate, NSEC_PER_SEC, pwm_event_device.shift);
-        pwm_event_device.max_delta_ns =
-                clockevent_delta2ns(-1, &pwm_event_device);
-        pwm_event_device.min_delta_ns =
-                clockevent_delta2ns(1, &pwm_event_device);
-
-        pwm_event_device.cpumask = cpumask_of(0);
-        clockevents_register_device(&pwm_event_device);
-
-        setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq);
-}
-
-static cycle_t exynos4_pwm4_read(struct clocksource *cs)
-{
-        return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
-}
-
-#ifdef CONFIG_PM
-static void exynos4_pwm4_resume(struct clocksource *cs)
-{
-        unsigned long pclk;
-
-        pclk = clk_get_rate(timerclk);
-
-        clk_set_rate(tdiv4, pclk / 2);
-        clk_set_parent(tin4, tdiv4);
-
-        exynos4_pwm_init(4, ~0);
-        exynos4_pwm_start(4, 1);
-}
-#endif
-
-struct clocksource pwm_clocksource = {
-        .name           = "pwm_timer4",
-        .rating         = 250,
-        .read           = exynos4_pwm4_read,
-        .mask           = CLOCKSOURCE_MASK(32),
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS ,
-#ifdef CONFIG_PM
-        .resume         = exynos4_pwm4_resume,
-#endif
-};
-
-static void __init exynos4_clocksource_init(void)
-{
-        unsigned long pclk;
-        unsigned long clock_rate;
-
-        pclk = clk_get_rate(timerclk);
-
-        clk_set_rate(tdiv4, pclk / 2);
-        clk_set_parent(tin4, tdiv4);
-
-        clock_rate = clk_get_rate(tin4);
-
-        exynos4_pwm_init(4, ~0);
-        exynos4_pwm_start(4, 1);
-
-        if (clocksource_register_hz(&pwm_clocksource, clock_rate))
-                panic("%s: can't register clocksource\n", pwm_clocksource.name);
-}
-
-static void __init exynos4_timer_resources(void)
-{
-        struct platform_device tmpdev;
-
-        tmpdev.dev.bus = &platform_bus_type;
-
-        timerclk = clk_get(NULL, "timers");
-        if (IS_ERR(timerclk))
-                panic("failed to get timers clock for system timer");
-
-        clk_enable(timerclk);
-
-        tmpdev.id = 2;
-        tin2 = clk_get(&tmpdev.dev, "pwm-tin");
-        if (IS_ERR(tin2))
-                panic("failed to get pwm-tin2 clock for system timer");
-
-        tdiv2 = clk_get(&tmpdev.dev, "pwm-tdiv");
-        if (IS_ERR(tdiv2))
-                panic("failed to get pwm-tdiv2 clock for system timer");
-        clk_enable(tin2);
-
-        tmpdev.id = 4;
-        tin4 = clk_get(&tmpdev.dev, "pwm-tin");
-        if (IS_ERR(tin4))
-                panic("failed to get pwm-tin4 clock for system timer");
-
-        tdiv4 = clk_get(&tmpdev.dev, "pwm-tdiv");
-        if (IS_ERR(tdiv4))
-                panic("failed to get pwm-tdiv4 clock for system timer");
-
-        clk_enable(tin4);
-}
-
-static void __init exynos4_timer_init(void)
-{
-#ifdef CONFIG_LOCAL_TIMERS
-        twd_base = S5P_VA_TWD;
-#endif
-
-        exynos4_timer_resources();
-        exynos4_clockevent_init();
-        exynos4_clocksource_init();
-}
-
-struct sys_timer exynos4_timer = {
-        .init           = exynos4_timer_init,
-};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e8dd22fa7d61..0519dd7f034b 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -278,6 +278,7 @@ config MACH_MX27_3DS
         select SOC_IMX27
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_UART
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index b31d4129e10e..6fa6934ab150 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -29,6 +29,7 @@
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
 #include <linux/regulator/machine.h>
+#include <linux/spi/l4f00242t03.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -47,7 +48,10 @@
 #define SPI2_SS0                IMX_GPIO_NR(4, 21)
 #define EXPIO_PARENT_INT        gpio_to_irq(IMX_GPIO_NR(3, 28))
 #define PMIC_INT                IMX_GPIO_NR(3, 14)
+#define SPI1_SS0                IMX_GPIO_NR(4, 28)
 #define SD1_CD                  IMX_GPIO_NR(2, 26)
+#define LCD_RESET               IMX_GPIO_NR(1, 3)
+#define LCD_ENABLE              IMX_GPIO_NR(1, 31)
 
 static const int mx27pdk_pins[] __initconst = {
         /* UART1 */
@@ -96,6 +100,12 @@ static const int mx27pdk_pins[] __initconst = {
         PE2_PF_USBOTG_DIR,
         PE24_PF_USBOTG_CLK,
         PE25_PF_USBOTG_DATA7,
+        /* CSPI1 */
+        PD31_PF_CSPI1_MOSI,
+        PD30_PF_CSPI1_MISO,
+        PD29_PF_CSPI1_SCLK,
+        PD25_PF_CSPI1_RDY,
+        SPI1_SS0 | GPIO_GPIO | GPIO_OUT,
         /* CSPI2 */
         PD22_PF_CSPI2_SCLK,
         PD23_PF_CSPI2_MISO,
@@ -106,6 +116,31 @@ static const int mx27pdk_pins[] __initconst = {
         PD18_PF_I2C_CLK,
         /* PMIC INT */
         PMIC_INT | GPIO_GPIO | GPIO_IN,
+        /* LCD */
+        PA5_PF_LSCLK,
+        PA6_PF_LD0,
+        PA7_PF_LD1,
+        PA8_PF_LD2,
+        PA9_PF_LD3,
+        PA10_PF_LD4,
+        PA11_PF_LD5,
+        PA12_PF_LD6,
+        PA13_PF_LD7,
+        PA14_PF_LD8,
+        PA15_PF_LD9,
+        PA16_PF_LD10,
+        PA17_PF_LD11,
+        PA18_PF_LD12,
+        PA19_PF_LD13,
+        PA20_PF_LD14,
+        PA21_PF_LD15,
+        PA22_PF_LD16,
+        PA23_PF_LD17,
+        PA28_PF_HSYNC,
+        PA29_PF_VSYNC,
+        PA30_PF_CONTRAST,
+        LCD_ENABLE | GPIO_GPIO | GPIO_OUT,
+        LCD_RESET | GPIO_GPIO | GPIO_OUT,
 };
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -258,10 +293,18 @@ static struct mc13xxx_platform_data mc13783_pdata = {
                 .num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
 
         },
-        .flags  = MC13783_USE_REGULATOR,
+        .flags  = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN |
+        MC13783_USE_RTC,
 };
 
 /* SPI */
+static int spi1_chipselect[] = {SPI1_SS0};
+
+static const struct spi_imx_master spi1_pdata __initconst = {
+        .chipselect     = spi1_chipselect,
+        .num_chipselect = ARRAY_SIZE(spi1_chipselect),
+};
+
 static int spi2_chipselect[] = {SPI2_SS0};
 
 static const struct spi_imx_master spi2_pdata __initconst = {
@@ -269,6 +312,46 @@ static const struct spi_imx_master spi2_pdata __initconst = {
         .num_chipselect = ARRAY_SIZE(spi2_chipselect),
 };
 
+static struct imx_fb_videomode mx27_3ds_modes[] = {
+        {       /* 480x640 @ 60 Hz */
+                .mode = {
+                        .name           = "Epson-VGA",
+                        .refresh        = 60,
+                        .xres           = 480,
+                        .yres           = 640,
+                        .pixclock       = 41701,
+                        .left_margin    = 20,
+                        .right_margin   = 41,
+                        .upper_margin   = 10,
+                        .lower_margin   = 5,
+                        .hsync_len      = 20,
+                        .vsync_len      = 10,
+                        .sync           = FB_SYNC_OE_ACT_HIGH |
+                                                FB_SYNC_CLK_INVERT,
+                        .vmode          = FB_VMODE_NONINTERLACED,
+                        .flag           = 0,
+                },
+                .bpp            = 16,
+                .pcr            = 0xFAC08B82,
+        },
+};
+
+static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = {
+        .mode = mx27_3ds_modes,
+        .num_modes = ARRAY_SIZE(mx27_3ds_modes),
+        .pwmr           = 0x00A903FF,
+        .lscr1          = 0x00120300,
+        .dmacr          = 0x00020010,
+};
+
+/* LCD */
+static struct l4f00242t03_pdata mx27_3ds_lcd_pdata = {
+        .reset_gpio             = LCD_RESET,
+        .data_enable_gpio       = LCD_ENABLE,
+        .core_supply            = "lcd_2v8",
+        .io_supply              = "vdd_lcdio",
+};
+
 static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
         {
                 .modalias       = "mc13783",
@@ -278,6 +361,12 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
                 .platform_data  = &mc13783_pdata,
                 .irq = gpio_to_irq(PMIC_INT),
                 .mode = SPI_CS_HIGH,
+        }, {
+                .modalias       = "l4f00242t03",
+                .max_speed_hz   = 5000000,
+                .bus_num        = 0,
+                .chip_select    = 0, /* SS0 */
+                .platform_data  = &mx27_3ds_lcd_pdata,
         },
 };
 
@@ -311,12 +400,14 @@ static void __init mx27pdk_init(void)
                 imx27_add_fsl_usb2_udc(&otg_device_pdata);
 
         imx27_add_spi_imx1(&spi2_pdata);
+        imx27_add_spi_imx0(&spi1_pdata);
         spi_register_board_info(mx27_3ds_spi_devs,
                                                 ARRAY_SIZE(mx27_3ds_spi_devs));
 
         if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
         imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
+        imx27_add_imx_fb(&mx27_3ds_fb_data);
 }
 
 static void __init mx27pdk_timer_init(void)
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 6d7d518686a5..3f05dfebacc9 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -22,6 +22,7 @@
 #include <linux/init.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
+#include <mach/devices-common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
 #include <mach/irqs.h>
@@ -82,4 +83,6 @@ void __init imx21_soc_init(void)
         mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
         mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
         mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
+
+        imx_add_imx_dma();
 }
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 9a1591c2508d..8bf029164652 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -24,6 +24,7 @@
 #include <asm/mach/map.h>
 
 #include <mach/common.h>
+#include <mach/devices-common.h>
 #include <mach/hardware.h>
 #include <mach/mx25.h>
 #include <mach/iomux-v3.h>
@@ -61,6 +62,28 @@ void __init mx25_init_irq(void)
         mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
 }
 
+static struct sdma_script_start_addrs imx25_sdma_script __initdata = {
+        .ap_2_ap_addr = 729,
+        .uart_2_mcu_addr = 904,
+        .per_2_app_addr = 1255,
+        .mcu_2_app_addr = 834,
+        .uartsh_2_mcu_addr = 1120,
+        .per_2_shp_addr = 1329,
+        .mcu_2_shp_addr = 1048,
+        .ata_2_mcu_addr = 1560,
+        .mcu_2_ata_addr = 1479,
+        .app_2_per_addr = 1189,
+        .app_2_mcu_addr = 770,
+        .shp_2_per_addr = 1407,
+        .shp_2_mcu_addr = 979,
+};
+
+static struct sdma_platform_data imx25_sdma_pdata __initdata = {
+        .sdma_version = 2,
+        .fw_name = "sdma-imx25.bin",
+        .script_addrs = &imx25_sdma_script,
+};
+
 void __init imx25_soc_init(void)
 {
         /* i.mx25 has the i.mx31 type gpio */
@@ -68,4 +91,6 @@ void __init imx25_soc_init(void)
         mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
         mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
         mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
+
+        imx_add_imx_sdma(MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
 }
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 133b30003ddb..96dd1f5ea7bd 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -22,6 +22,7 @@
 #include <linux/init.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
+#include <mach/devices-common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
 #include <mach/irqs.h>
@@ -83,4 +84,6 @@ void __init imx27_soc_init(void)
         mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
         mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
         mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
+
+        imx_add_imx_dma();
 }
diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c
index 6d103c01b8b9..61bff38cb955 100644
--- a/arch/arm/mach-imx/mm-imx31.c
+++ b/arch/arm/mach-imx/mm-imx31.c
@@ -24,6 +24,7 @@
 #include <asm/mach/map.h>
 
 #include <mach/common.h>
+#include <mach/devices-common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-v3.h>
 #include <mach/irqs.h>
@@ -57,9 +58,35 @@ void __init mx31_init_irq(void)
         mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
 }
 
+static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
+        .per_2_per_addr = 1677,
+};
+
+static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
+        .ap_2_ap_addr = 423,
+        .ap_2_bp_addr = 829,
+        .bp_2_ap_addr = 1029,
+};
+
+static struct sdma_platform_data imx31_sdma_pdata __initdata = {
+        .sdma_version = 1,
+        .fw_name = "sdma-imx31-to2.bin",
+        .script_addrs = &imx31_to2_sdma_script,
+};
+
 void __init imx31_soc_init(void)
 {
+        int to_version = mx31_revision() >> 4;
+
         mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
         mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
         mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
+
+        if (to_version == 1) {
+                strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
+                        strlen(imx31_sdma_pdata.fw_name));
+                imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
+        }
+
+        imx_add_imx_sdma(MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
 }
diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c
index bb068bc8dab7..98769ae34377 100644
--- a/arch/arm/mach-imx/mm-imx35.c
+++ b/arch/arm/mach-imx/mm-imx35.c
@@ -25,6 +25,7 @@
 #include <asm/hardware/cache-l2x0.h>
 
 #include <mach/common.h>
+#include <mach/devices-common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-v3.h>
 #include <mach/irqs.h>
@@ -54,10 +55,56 @@ void __init mx35_init_irq(void)
         mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
 }
 
+static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
+        .ap_2_ap_addr = 642,
+        .uart_2_mcu_addr = 817,
+        .mcu_2_app_addr = 747,
+        .uartsh_2_mcu_addr = 1183,
+        .per_2_shp_addr = 1033,
+        .mcu_2_shp_addr = 961,
+        .ata_2_mcu_addr = 1333,
+        .mcu_2_ata_addr = 1252,
+        .app_2_mcu_addr = 683,
+        .shp_2_per_addr = 1111,
+        .shp_2_mcu_addr = 892,
+};
+
+static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
+        .ap_2_ap_addr = 729,
+        .uart_2_mcu_addr = 904,
+        .per_2_app_addr = 1597,
+        .mcu_2_app_addr = 834,
+        .uartsh_2_mcu_addr = 1270,
+        .per_2_shp_addr = 1120,
+        .mcu_2_shp_addr = 1048,
+        .ata_2_mcu_addr = 1429,
+        .mcu_2_ata_addr = 1339,
+        .app_2_per_addr = 1531,
+        .app_2_mcu_addr = 770,
+        .shp_2_per_addr = 1198,
+        .shp_2_mcu_addr = 979,
+};
+
+static struct sdma_platform_data imx35_sdma_pdata __initdata = {
+        .sdma_version = 2,
+        .fw_name = "sdma-imx35-to2.bin",
+        .script_addrs = &imx35_to2_sdma_script,
+};
+
 void __init imx35_soc_init(void)
 {
+        int to_version = mx35_revision() >> 4;
+
         /* i.mx35 has the i.mx31 type gpio */
         mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
         mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
         mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
+
+        if (to_version == 1) {
+                strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
+                        strlen(imx35_sdma_pdata.fw_name));
+                imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
+        }
+
+        imx_add_imx_sdma(MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
 }
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index da0e6498110a..1e027514096d 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -1077,7 +1077,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
         _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
         _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
-        _REGISTER_CLOCK("lpc32xx-ts", NULL, clk_tsc)
+        _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
         _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
         _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
         _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index ee24dc28e93e..205b2dbb565b 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -95,6 +95,48 @@ struct platform_device lpc32xx_i2c2_device = {
         },
 };
 
+/* TSC (Touch Screen Controller) */
+
+static struct resource lpc32xx_tsc_resources[] = {
+        {
+                .start = LPC32XX_ADC_BASE,
+                .end = LPC32XX_ADC_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = IRQ_LPC32XX_TS_IRQ,
+                .end = IRQ_LPC32XX_TS_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device lpc32xx_tsc_device = {
+        .name =  "ts-lpc32xx",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(lpc32xx_tsc_resources),
+        .resource = lpc32xx_tsc_resources,
+};
+
+/* RTC */
+
+static struct resource lpc32xx_rtc_resources[] = {
+        {
+                .start = LPC32XX_RTC_BASE,
+                .end = LPC32XX_RTC_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },{
+                .start = IRQ_LPC32XX_RTC,
+                .end = IRQ_LPC32XX_RTC,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device lpc32xx_rtc_device = {
+        .name =  "rtc-lpc32xx",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(lpc32xx_rtc_resources),
+        .resource = lpc32xx_rtc_resources,
+};
+
 /*
  * Returns the unique ID for the device
  */
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index f82211fd80c1..5583f52662bd 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -28,6 +28,8 @@ extern struct platform_device lpc32xx_watchdog_device;
 extern struct platform_device lpc32xx_i2c0_device;
 extern struct platform_device lpc32xx_i2c1_device;
 extern struct platform_device lpc32xx_i2c2_device;
+extern struct platform_device lpc32xx_tsc_device;
+extern struct platform_device lpc32xx_rtc_device;
 
 /*
  * Other arch specific structures and functions
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 67793a690272..56ef5f6c8116 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -77,6 +77,13 @@ config MACH_TETON_BGA
           Say 'Y' here if you want to support the Marvell PXA168-based
           Teton BGA Development Board.
 
+config MACH_SHEEVAD
+        bool "Marvell's PXA168 GuruPlug Display (gplugD) Board"
+        select CPU_PXA168
+        help
+          Say 'Y' here if you want to support the Marvell PXA168-based
+          GuruPlug Display (gplugD) Board
+
 endmenu
 
 config CPU_PXA168
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 5c68382141af..b0ac942327aa 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_MACH_BROWNSTONE)	+= brownstone.o
 obj-$(CONFIG_MACH_FLINT)        += flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
 obj-$(CONFIG_MACH_TETON_BGA)    += teton_bga.o
+obj-$(CONFIG_MACH_SHEEVAD)      += gplugd.o
diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c
index 886e05648f08..7c6f95f29142 100644
--- a/arch/arm/mach-mmp/clock.c
+++ b/arch/arm/mach-mmp/clock.c
@@ -88,3 +88,18 @@ unsigned long clk_get_rate(struct clk *clk)
         return rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long flags;
+        int ret = -EINVAL;
+
+        if (clk->ops->setrate) {
+                spin_lock_irqsave(&clocks_lock, flags);
+                ret = clk->ops->setrate(clk, rate);
+                spin_unlock_irqrestore(&clocks_lock, flags);
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
index 9b027d7491f5..3143e994e672 100644
--- a/arch/arm/mach-mmp/clock.h
+++ b/arch/arm/mach-mmp/clock.h
@@ -12,6 +12,7 @@ struct clkops {
         void                    (*enable)(struct clk *);
         void                    (*disable)(struct clk *);
         unsigned long           (*getrate)(struct clk *);
+        int                     (*setrate)(struct clk *, unsigned long);
 };
 
 struct clk {
diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
new file mode 100644
index 000000000000..c070c24255f4
--- /dev/null
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -0,0 +1,189 @@
+/*
+ *  linux/arch/arm/mach-mmp/gplugd.c
+ *
+ *  Support for the Marvell PXA168-based GuruPlug Display (gplugD) Platform.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/gpio.h>
+#include <mach/pxa168.h>
+#include <mach/mfp-pxa168.h>
+#include <mach/mfp-gplugd.h>
+
+#include "common.h"
+
+static unsigned long gplugd_pin_config[] __initdata = {
+        /* UART3 */
+        GPIO8_UART3_SOUT,
+        GPIO9_UART3_SIN,
+        GPI1O_UART3_CTS,
+        GPI11_UART3_RTS,
+
+        /* MMC2 */
+        GPIO28_MMC2_CMD,
+        GPIO29_MMC2_CLK,
+        GPIO30_MMC2_DAT0,
+        GPIO31_MMC2_DAT1,
+        GPIO32_MMC2_DAT2,
+        GPIO33_MMC2_DAT3,
+
+        /* LCD & HDMI clock selection GPIO: 0: 74.176MHz, 1: 74.25 MHz */
+        GPIO35_GPIO,
+        GPIO36_GPIO, /* CEC Interrupt */
+
+        /* MMC1 */
+        GPIO43_MMC1_CLK,
+        GPIO49_MMC1_CMD,
+        GPIO41_MMC1_DAT0,
+        GPIO40_MMC1_DAT1,
+        GPIO52_MMC1_DAT2,
+        GPIO51_MMC1_DAT3,
+        GPIO53_MMC1_CD,
+
+        /* LCD */
+        GPIO56_LCD_FCLK_RD,
+        GPIO57_LCD_LCLK_A0,
+        GPIO58_LCD_PCLK_WR,
+        GPIO59_LCD_DENA_BIAS,
+        GPIO60_LCD_DD0,
+        GPIO61_LCD_DD1,
+        GPIO62_LCD_DD2,
+        GPIO63_LCD_DD3,
+        GPIO64_LCD_DD4,
+        GPIO65_LCD_DD5,
+        GPIO66_LCD_DD6,
+        GPIO67_LCD_DD7,
+        GPIO68_LCD_DD8,
+        GPIO69_LCD_DD9,
+        GPIO70_LCD_DD10,
+        GPIO71_LCD_DD11,
+        GPIO72_LCD_DD12,
+        GPIO73_LCD_DD13,
+        GPIO74_LCD_DD14,
+        GPIO75_LCD_DD15,
+        GPIO76_LCD_DD16,
+        GPIO77_LCD_DD17,
+        GPIO78_LCD_DD18,
+        GPIO79_LCD_DD19,
+        GPIO80_LCD_DD20,
+        GPIO81_LCD_DD21,
+        GPIO82_LCD_DD22,
+        GPIO83_LCD_DD23,
+
+        /* GPIO */
+        GPIO84_GPIO,
+        GPIO85_GPIO,
+
+        /* Fast-Ethernet*/
+        GPIO86_TX_CLK,
+        GPIO87_TX_EN,
+        GPIO88_TX_DQ3,
+        GPIO89_TX_DQ2,
+        GPIO90_TX_DQ1,
+        GPIO91_TX_DQ0,
+        GPIO92_MII_CRS,
+        GPIO93_MII_COL,
+        GPIO94_RX_CLK,
+        GPIO95_RX_ER,
+        GPIO96_RX_DQ3,
+        GPIO97_RX_DQ2,
+        GPIO98_RX_DQ1,
+        GPIO99_RX_DQ0,
+        GPIO100_MII_MDC,
+        GPIO101_MII_MDIO,
+        GPIO103_RX_DV,
+        GPIO104_GPIO,     /* Reset PHY */
+
+        /* RTC interrupt */
+        GPIO102_GPIO,
+
+        /* I2C */
+        GPIO105_CI2C_SDA,
+        GPIO106_CI2C_SCL,
+
+        /* Select JTAG */
+        GPIO109_GPIO,
+
+        /* I2S */
+        GPIO114_I2S_FRM,
+        GPIO115_I2S_BCLK,
+        GPIO116_I2S_TXD
+};
+
+static struct i2c_board_info gplugd_i2c_board_info[] = {
+        {
+                .type = "isl1208",
+                .addr = 0x6F,
+        }
+};
+
+/* Bring PHY out of reset by setting GPIO 104 */
+static int gplugd_eth_init(void)
+{
+        if (unlikely(gpio_request(104, "ETH_RESET_N"))) {
+                printk(KERN_ERR "Can't get hold of GPIO 104 to bring Ethernet "
+                                "PHY out of reset\n");
+                return -EIO;
+        }
+
+        gpio_direction_output(104, 1);
+        gpio_free(104);
+        return 0;
+}
+
+struct pxa168_eth_platform_data gplugd_eth_platform_data = {
+        .port_number = 0,
+        .phy_addr    = 0,
+        .speed       = 0, /* Autonagotiation */
+        .init        = gplugd_eth_init,
+};
+
+static void __init select_disp_freq(void)
+{
+        /* set GPIO 35 & clear GPIO 85 to set LCD External Clock to 74.25 MHz */
+        if (unlikely(gpio_request(35, "DISP_FREQ_SEL"))) {
+                printk(KERN_ERR "Can't get hold of GPIO 35 to select display "
+                                "frequency\n");
+        } else {
+                gpio_direction_output(35, 1);
+                gpio_free(104);
+        }
+
+        if (unlikely(gpio_request(85, "DISP_FREQ_SEL_2"))) {
+                printk(KERN_ERR "Can't get hold of GPIO 85 to select display "
+                                "frequency\n");
+        } else {
+                gpio_direction_output(85, 0);
+                gpio_free(104);
+        }
+}
+
+static void __init gplugd_init(void)
+{
+        mfp_config(ARRAY_AND_SIZE(gplugd_pin_config));
+
+        select_disp_freq();
+
+        /* on-chip devices */
+        pxa168_add_uart(3);
+        pxa168_add_ssp(0);
+        pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info));
+
+        pxa168_add_eth(&gplugd_eth_platform_data);
+}
+
+MACHINE_START(SHEEVAD, "PXA168-based GuruPlug Display (gplugD) Platform")
+        .map_io         = mmp_map_io,
+        .nr_irqs        = IRQ_BOARD_START,
+        .init_irq       = pxa168_init_irq,
+        .timer          = &pxa168_timer,
+        .init_machine   = gplugd_init,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/include/mach/mfp-gplugd.h b/arch/arm/mach-mmp/include/mach/mfp-gplugd.h
new file mode 100644
index 000000000000..b8cf38d85600
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/mfp-gplugd.h
@@ -0,0 +1,52 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/mfp-gplugd.h
+ *
+ *   MFP definitions used in gplugD
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_MFP_GPLUGD_H
+#define __MACH_MFP_GPLUGD_H
+
+#include <plat/mfp.h>
+#include <mach/mfp.h>
+
+/* UART3 */
+#define GPIO8_UART3_SOUT       MFP_CFG(GPIO8, AF2)
+#define GPIO9_UART3_SIN        MFP_CFG(GPIO9, AF2)
+#define GPI1O_UART3_CTS        MFP_CFG(GPIO10, AF2)
+#define GPI11_UART3_RTS        MFP_CFG(GPIO11, AF2)
+
+/* MMC2 */
+#define GPIO28_MMC2_CMD         MFP_CFG_DRV(GPIO28, AF6, FAST)
+#define GPIO29_MMC2_CLK         MFP_CFG_DRV(GPIO29, AF6, FAST)
+#define GPIO30_MMC2_DAT0        MFP_CFG_DRV(GPIO30, AF6, FAST)
+#define GPIO31_MMC2_DAT1        MFP_CFG_DRV(GPIO31, AF6, FAST)
+#define GPIO32_MMC2_DAT2        MFP_CFG_DRV(GPIO32, AF6, FAST)
+#define GPIO33_MMC2_DAT3        MFP_CFG_DRV(GPIO33, AF6, FAST)
+
+/* I2S */
+#undef GPIO114_I2S_FRM
+#undef GPIO115_I2S_BCLK
+
+#define GPIO114_I2S_FRM         MFP_CFG_DRV(GPIO114, AF1, FAST)
+#define GPIO115_I2S_BCLK        MFP_CFG_DRV(GPIO115, AF1, FAST)
+#define GPIO116_I2S_TXD         MFP_CFG_DRV(GPIO116, AF1, FAST)
+
+/* MMC4 */
+#define GPIO125_MMC4_DAT3       MFP_CFG_DRV(GPIO125, AF7, FAST)
+#define GPIO126_MMC4_DAT2       MFP_CFG_DRV(GPIO126, AF7, FAST)
+#define GPIO127_MMC4_DAT1       MFP_CFG_DRV(GPIO127, AF7, FAST)
+#define GPIO0_2_MMC4_DAT0       MFP_CFG_DRV(GPIO0_2, AF7, FAST)
+#define GPIO1_2_MMC4_CMD        MFP_CFG_DRV(GPIO1_2, AF7, FAST)
+#define GPIO2_2_MMC4_CLK        MFP_CFG_DRV(GPIO2_2, AF7, FAST)
+
+/* OTG GPIO */
+#define GPIO_USB_OTG_PEN        18
+#define GPIO_USB_OIDIR          20
+
+/* Other GPIOs are 35, 84, 85 */
+#endif /* __MACH_MFP_GPLUGD_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
index 713be155a44d..8c782328b21c 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
@@ -305,4 +305,23 @@
 #define GPIO112_KP_MKOUT6       MFP_CFG(GPIO112, AF7)
 #define GPIO121_KP_MKIN4        MFP_CFG(GPIO121, AF7)
 
+/* Fast Ethernet */
+#define GPIO86_TX_CLK           MFP_CFG(GPIO86, AF5)
+#define GPIO87_TX_EN            MFP_CFG(GPIO87, AF5)
+#define GPIO88_TX_DQ3           MFP_CFG(GPIO88, AF5)
+#define GPIO89_TX_DQ2           MFP_CFG(GPIO89, AF5)
+#define GPIO90_TX_DQ1           MFP_CFG(GPIO90, AF5)
+#define GPIO91_TX_DQ0           MFP_CFG(GPIO91, AF5)
+#define GPIO92_MII_CRS          MFP_CFG(GPIO92, AF5)
+#define GPIO93_MII_COL          MFP_CFG(GPIO93, AF5)
+#define GPIO94_RX_CLK           MFP_CFG(GPIO94, AF5)
+#define GPIO95_RX_ER            MFP_CFG(GPIO95, AF5)
+#define GPIO96_RX_DQ3           MFP_CFG(GPIO96, AF5)
+#define GPIO97_RX_DQ2           MFP_CFG(GPIO97, AF5)
+#define GPIO98_RX_DQ1           MFP_CFG(GPIO98, AF5)
+#define GPIO99_RX_DQ0           MFP_CFG(GPIO99, AF5)
+#define GPIO100_MII_MDC         MFP_CFG(GPIO100, AF5)
+#define GPIO101_MII_MDIO        MFP_CFG(GPIO101, AF5)
+#define GPIO103_RX_DV           MFP_CFG(GPIO103, AF5)
+
 #endif /* __ASM_MACH_MFP_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index a52b3d2f325c..7f005843a707 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -14,9 +14,11 @@ extern void pxa168_clear_keypad_wakeup(void);
 #include <video/pxa168fb.h>
 #include <plat/pxa27x_keypad.h>
 #include <mach/cputype.h>
+#include <linux/pxa168_eth.h>
 
 extern struct pxa_device_desc pxa168_device_uart1;
 extern struct pxa_device_desc pxa168_device_uart2;
+extern struct pxa_device_desc pxa168_device_uart3;
 extern struct pxa_device_desc pxa168_device_twsi0;
 extern struct pxa_device_desc pxa168_device_twsi1;
 extern struct pxa_device_desc pxa168_device_pwm1;
@@ -31,6 +33,7 @@ extern struct pxa_device_desc pxa168_device_ssp5;
 extern struct pxa_device_desc pxa168_device_nand;
 extern struct pxa_device_desc pxa168_device_fb;
 extern struct pxa_device_desc pxa168_device_keypad;
+extern struct pxa_device_desc pxa168_device_eth;
 
 static inline int pxa168_add_uart(int id)
 {
@@ -39,6 +42,7 @@ static inline int pxa168_add_uart(int id)
         switch (id) {
         case 1: d = &pxa168_device_uart1; break;
         case 2: d = &pxa168_device_uart2; break;
+        case 3: d = &pxa168_device_uart3; break;
         }
 
         if (d == NULL)
@@ -117,4 +121,8 @@ static inline int pxa168_add_keypad(struct pxa27x_keypad_platform_data *data)
         return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data));
 }
 
+static inline int pxa168_add_eth(struct pxa168_eth_platform_data *data)
+{
+        return pxa_register_device(&pxa168_device_eth, data, sizeof(*data));
+}
 #endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index f7011ef70bf5..8447ac63e28f 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -29,6 +29,7 @@
 #define APMU_BUS        APMU_REG(0x06c)
 #define APMU_SDH2       APMU_REG(0x0e8)
 #define APMU_SDH3       APMU_REG(0x0ec)
+#define APMU_ETH        APMU_REG(0x0fc)
 
 #define APMU_FNCLK_EN   (1 << 4)
 #define APMU_AXICLK_EN  (1 << 3)
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index ab9f999106c7..0156f535dae7 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -66,6 +66,7 @@ void __init pxa168_init_irq(void)
 /* APB peripheral clocks */
 static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
 static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
+static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
 static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
 static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
 static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
@@ -81,11 +82,13 @@ static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
 
 static APMU_CLK(nand, NAND, 0x19b, 156000000);
 static APMU_CLK(lcd, LCD, 0x7f, 312000000);
+static APMU_CLK(eth, ETH, 0x09, 0);
 
 /* device and clock bindings */
 static struct clk_lookup pxa168_clkregs[] = {
         INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
         INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+        INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
         INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
         INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
         INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
@@ -100,6 +103,7 @@ static struct clk_lookup pxa168_clkregs[] = {
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
         INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
         INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
+        INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
 };
 
 static int __init pxa168_init(void)
@@ -149,6 +153,7 @@ void pxa168_clear_keypad_wakeup(void)
 /* on-chip devices */
 PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
 PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
+PXA168_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4026000, 0x30, 23, 24);
 PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
 PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
 PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10);
@@ -163,3 +168,4 @@ PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59);
 PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
 PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
 PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
+PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff);
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index e411039ea59e..6bd37a27e5fc 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -15,6 +15,8 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/onenand.h>
 #include <linux/interrupt.h>
+#include <linux/i2c/pca953x.h>
+#include <linux/gpio.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -25,7 +27,17 @@
 
 #include "common.h"
 
-#define TTCDKB_NR_IRQS          (IRQ_BOARD_START + 24)
+#define TTCDKB_GPIO_EXT0(x)     (NR_BUILTIN_GPIO + ((x < 0) ? 0 :       \
+                                ((x < 16) ? x : 15)))
+#define TTCDKB_GPIO_EXT1(x)     (NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 :  \
+                                ((x < 16) ? x : 15)))
+
+/*
+ * 16 board interrupts -- MAX7312 GPIO expander
+ * 16 board interrupts -- PCA9575 GPIO expander
+ * 24 board interrupts -- 88PM860x PMIC
+ */
+#define TTCDKB_NR_IRQS          (IRQ_BOARD_START + 16 + 16 + 24)
 
 static unsigned long ttc_dkb_pin_config[] __initdata = {
         /* UART2 */
@@ -113,6 +125,22 @@ static struct platform_device *ttc_dkb_devices[] = {
         &ttc_dkb_device_onenand,
 };
 
+static struct pca953x_platform_data max7312_data[] = {
+        {
+                .gpio_base      = TTCDKB_GPIO_EXT0(0),
+                .irq_base       = IRQ_BOARD_START,
+        },
+};
+
+static struct i2c_board_info ttc_dkb_i2c_info[] = {
+        {
+                .type           = "max7312",
+                .addr           = 0x23,
+                .irq            = IRQ_GPIO(80),
+                .platform_data  = &max7312_data,
+        },
+};
+
 static void __init ttc_dkb_init(void)
 {
         mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
@@ -121,6 +149,7 @@ static void __init ttc_dkb_init(void)
         pxa910_add_uart(1);
 
         /* off-chip devices */
+        pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
         platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
 }
 
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index f25e9d7bf0f5..b4e7c58bbb38 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -180,6 +180,7 @@ config MACH_MX53_EVK
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select IMX_HAVE_PLATFORM_SPI_IMX
+        select LEDS_GPIO_REGISTER
         help
           Include support for MX53 EVK platform. This includes specific
           configurations for the board and its peripherals.
@@ -203,10 +204,23 @@ config MACH_MX53_LOCO
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select IMX_HAVE_PLATFORM_GPIO_KEYS
+        select LEDS_GPIO_REGISTER
         help
           Include support for MX53 LOCO platform. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_MX53_ARD
+        bool "Support MX53 ARD platforms"
+        select SOC_IMX53
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        select IMX_HAVE_PLATFORM_GPIO_KEYS
+        help
+          Include support for MX53 ARD platform. This includes specific
+          configurations for the board and its peripherals.
+
 endif # ARCH_MX53_SUPPORTED
 
 endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 0b9338cec516..383e7cd3fbcb 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -6,12 +6,14 @@
 obj-y   := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o
 obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
 
+obj-$(CONFIG_PM) += pm-imx5.o
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpu_op-mx51.o
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
 obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
 obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
 obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o
 obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o
+obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index e54e4bf61cfd..15c600026aee 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -41,6 +41,10 @@
 #define BABBAGE_POWER_KEY       IMX_GPIO_NR(2, 21)
 #define BABBAGE_ECSPI1_CS0      IMX_GPIO_NR(4, 24)
 #define BABBAGE_ECSPI1_CS1      IMX_GPIO_NR(4, 25)
+#define BABBAGE_SD1_CD          IMX_GPIO_NR(1, 0)
+#define BABBAGE_SD1_WP          IMX_GPIO_NR(1, 1)
+#define BABBAGE_SD2_CD          IMX_GPIO_NR(1, 6)
+#define BABBAGE_SD2_WP          IMX_GPIO_NR(1, 5)
 
 /* USB_CTRL_1 */
 #define MX51_USB_CTRL_1_OFFSET                  0x10
@@ -142,6 +146,8 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
         MX51_PAD_SD1_DATA1__SD1_DATA1,
         MX51_PAD_SD1_DATA2__SD1_DATA2,
         MX51_PAD_SD1_DATA3__SD1_DATA3,
+        MX51_PAD_GPIO1_0__GPIO1_0,
+        MX51_PAD_GPIO1_1__GPIO1_1,
 
         /* SD 2 */
         MX51_PAD_SD2_CMD__SD2_CMD,
@@ -150,6 +156,8 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
         MX51_PAD_SD2_DATA1__SD2_DATA1,
         MX51_PAD_SD2_DATA2__SD2_DATA2,
         MX51_PAD_SD2_DATA3__SD2_DATA3,
+        MX51_PAD_GPIO1_6__GPIO1_6,
+        MX51_PAD_GPIO1_5__GPIO1_5,
 
         /* eCSPI1 */
         MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
@@ -331,6 +339,16 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
         .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
 };
 
+static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
+        .cd_gpio = BABBAGE_SD1_CD,
+        .wp_gpio = BABBAGE_SD1_WP,
+};
+
+static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
+        .cd_gpio = BABBAGE_SD2_CD,
+        .wp_gpio = BABBAGE_SD2_WP,
+};
+
 /*
  * Board specific initialization.
  */
@@ -376,8 +394,8 @@ static void __init mx51_babbage_init(void)
         mxc_iomux_v3_setup_pad(usbh1stp);
         babbage_usbhub_reset();
 
-        imx51_add_sdhci_esdhc_imx(0, NULL);
-        imx51_add_sdhci_esdhc_imx(1, NULL);
+        imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
+        imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
 
         spi_register_board_info(mx51_babbage_spi_board_info,
                 ARRAY_SIZE(mx51_babbage_spi_board_info));
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c
new file mode 100644
index 000000000000..76a67c4a2a0b
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx53_ard.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx53.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "crm_regs.h"
+#include "devices-imx53.h"
+
+#define ARD_ETHERNET_INT_B      IMX_GPIO_NR(2, 31)
+#define ARD_SD1_CD              IMX_GPIO_NR(1, 1)
+#define ARD_SD1_WP              IMX_GPIO_NR(1, 9)
+#define ARD_I2CPORTEXP_B        IMX_GPIO_NR(2, 3)
+#define ARD_VOLUMEDOWN          IMX_GPIO_NR(4, 0)
+#define ARD_HOME                        IMX_GPIO_NR(5, 10)
+#define ARD_BACK                        IMX_GPIO_NR(5, 11)
+#define ARD_PROG                        IMX_GPIO_NR(5, 12)
+#define ARD_VOLUMEUP            IMX_GPIO_NR(5, 13)
+
+static iomux_v3_cfg_t mx53_ard_pads[] = {
+        /* UART1 */
+        MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
+        MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
+        /* WEIM for CS1 */
+        MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
+        MX53_PAD_EIM_D16__EMI_WEIM_D_16,
+        MX53_PAD_EIM_D17__EMI_WEIM_D_17,
+        MX53_PAD_EIM_D18__EMI_WEIM_D_18,
+        MX53_PAD_EIM_D19__EMI_WEIM_D_19,
+        MX53_PAD_EIM_D20__EMI_WEIM_D_20,
+        MX53_PAD_EIM_D21__EMI_WEIM_D_21,
+        MX53_PAD_EIM_D22__EMI_WEIM_D_22,
+        MX53_PAD_EIM_D23__EMI_WEIM_D_23,
+        MX53_PAD_EIM_D24__EMI_WEIM_D_24,
+        MX53_PAD_EIM_D25__EMI_WEIM_D_25,
+        MX53_PAD_EIM_D26__EMI_WEIM_D_26,
+        MX53_PAD_EIM_D27__EMI_WEIM_D_27,
+        MX53_PAD_EIM_D28__EMI_WEIM_D_28,
+        MX53_PAD_EIM_D29__EMI_WEIM_D_29,
+        MX53_PAD_EIM_D30__EMI_WEIM_D_30,
+        MX53_PAD_EIM_D31__EMI_WEIM_D_31,
+        MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
+        MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
+        MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
+        MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
+        MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
+        MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
+        MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
+        MX53_PAD_EIM_OE__EMI_WEIM_OE,
+        MX53_PAD_EIM_RW__EMI_WEIM_RW,
+        MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
+        /* SDHC1 */
+        MX53_PAD_SD1_CMD__ESDHC1_CMD,
+        MX53_PAD_SD1_CLK__ESDHC1_CLK,
+        MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
+        MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
+        MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
+        MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+        MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
+        MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
+        MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
+        MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
+        MX53_PAD_GPIO_1__GPIO1_1,
+        MX53_PAD_GPIO_9__GPIO1_9,
+        /* I2C2 */
+        MX53_PAD_EIM_EB2__I2C2_SCL,
+        MX53_PAD_KEY_ROW3__I2C2_SDA,
+        /* I2C3 */
+        MX53_PAD_GPIO_3__I2C3_SCL,
+        MX53_PAD_GPIO_16__I2C3_SDA,
+        /* GPIO */
+        MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */
+        MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */
+        MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */
+        MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */
+        MX53_PAD_GPIO_10__GPIO4_0,              /* vol down */
+};
+
+#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)    \
+{                                                       \
+        .gpio           = gpio_num,                             \
+        .type           = EV_KEY,                               \
+        .code           = ev_code,                              \
+        .active_low     = act_low,                              \
+        .desc           = "btn " descr,                 \
+        .wakeup         = wake,                                 \
+}
+
+static struct gpio_keys_button ard_buttons[] = {
+        GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
+        GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
+        GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
+        GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
+        GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
+};
+
+static const struct gpio_keys_platform_data ard_button_data __initconst = {
+        .buttons        = ard_buttons,
+        .nbuttons       = ARRAY_SIZE(ard_buttons),
+};
+
+static struct resource ard_smsc911x_resources[] = {
+        {
+                .start = MX53_CS1_64MB_BASE_ADDR,
+                .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start =  gpio_to_irq(ARD_ETHERNET_INT_B),
+                .end =  gpio_to_irq(ARD_ETHERNET_INT_B),
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct smsc911x_platform_config ard_smsc911x_config = {
+        .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+        .flags = SMSC911X_USE_32BIT,
+};
+
+static struct platform_device ard_smsc_lan9220_device = {
+        .name = "smsc911x",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(ard_smsc911x_resources),
+        .resource = ard_smsc911x_resources,
+        .dev = {
+                .platform_data = &ard_smsc911x_config,
+        },
+};
+
+static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
+        .cd_gpio = ARD_SD1_CD,
+        .wp_gpio = ARD_SD1_WP,
+};
+
+static struct imxi2c_platform_data mx53_ard_i2c2_data = {
+        .bitrate = 50000,
+};
+
+static struct imxi2c_platform_data mx53_ard_i2c3_data = {
+        .bitrate = 400000,
+};
+
+static void __init mx53_ard_io_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
+                                ARRAY_SIZE(mx53_ard_pads));
+
+        gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
+        gpio_direction_input(ARD_ETHERNET_INT_B);
+
+        gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
+        gpio_direction_output(ARD_I2CPORTEXP_B, 1);
+}
+
+/* Config CS1 settings for ethernet controller */
+static int weim_cs_config(void)
+{
+        u32 reg;
+        void __iomem *weim_base, *iomuxc_base;
+
+        weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
+        if (!weim_base)
+                return -ENOMEM;
+
+        iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
+        if (!iomuxc_base)
+                return -ENOMEM;
+
+        /* CS1 timings for LAN9220 */
+        writel(0x20001, (weim_base + 0x18));
+        writel(0x0, (weim_base + 0x1C));
+        writel(0x16000202, (weim_base + 0x20));
+        writel(0x00000002, (weim_base + 0x24));
+        writel(0x16002082, (weim_base + 0x28));
+        writel(0x00000000, (weim_base + 0x2C));
+        writel(0x00000000, (weim_base + 0x90));
+
+        /* specify 64 MB on CS1 and CS0 on GPR1 */
+        reg = readl(iomuxc_base + 0x4);
+        reg &= ~0x3F;
+        reg |= 0x1B;
+        writel(reg, (iomuxc_base + 0x4));
+
+        iounmap(iomuxc_base);
+        iounmap(weim_base);
+
+        return 0;
+}
+
+static struct platform_device *devices[] __initdata = {
+        &ard_smsc_lan9220_device,
+};
+
+static void __init mx53_ard_board_init(void)
+{
+        imx53_soc_init();
+        imx53_add_imx_uart(0, NULL);
+
+        mx53_ard_io_init();
+        weim_cs_config();
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+
+        imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
+        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
+        imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
+        imx_add_gpio_keys(&ard_button_data);
+}
+
+static void __init mx53_ard_timer_init(void)
+{
+        mx53_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mx53_ard_timer = {
+        .init   = mx53_ard_timer_init,
+};
+
+MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
+        .map_io = mx53_map_io,
+        .init_early = imx53_init_early,
+        .init_irq = mx53_init_irq,
+        .timer = &mx53_ard_timer,
+        .init_machine = mx53_ard_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 0d9218a6e2d2..1b417b06b736 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -35,6 +35,7 @@
 #define MX53_EVK_FEC_PHY_RST    IMX_GPIO_NR(7, 6)
 #define EVK_ECSPI1_CS0          IMX_GPIO_NR(2, 30)
 #define EVK_ECSPI1_CS1          IMX_GPIO_NR(3, 19)
+#define MX53EVK_LED             IMX_GPIO_NR(7, 7)
 
 #include "crm_regs.h"
 #include "devices-imx53.h"
@@ -58,12 +59,27 @@ static iomux_v3_cfg_t mx53_evk_pads[] = {
         /* ecspi chip select lines */
         MX53_PAD_EIM_EB2__GPIO2_30,
         MX53_PAD_EIM_D19__GPIO3_19,
+        /* LED */
+        MX53_PAD_PATA_DA_1__GPIO7_7,
 };
 
 static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
+static const struct gpio_led mx53evk_leds[] __initconst = {
+        {
+                .name                   = "green",
+                .default_trigger        = "heartbeat",
+                .gpio                   = MX53EVK_LED,
+        },
+};
+
+static const struct gpio_led_platform_data mx53evk_leds_data __initconst = {
+        .leds           = mx53evk_leds,
+        .num_leds       = ARRAY_SIZE(mx53evk_leds),
+};
+
 static inline void mx53_evk_init_uart(void)
 {
         imx53_add_imx_uart(0, NULL);
@@ -135,6 +151,7 @@ static void __init mx53_evk_board_init(void)
                 ARRAY_SIZE(mx53_evk_spi_board_info));
         imx53_add_ecspi(0, &mx53_evk_spi_data);
         imx53_add_imx2_wdt(0, NULL);
+        gpio_led_register_device(-1, &mx53evk_leds_data);
 }
 
 static void __init mx53_evk_timer_init(void)
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 359c3e248add..54be525e2bd7 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -38,6 +38,10 @@
 #define MX53_LOCO_UI1                   IMX_GPIO_NR(2, 14)
 #define MX53_LOCO_UI2                   IMX_GPIO_NR(2, 15)
 #define LOCO_FEC_PHY_RST                IMX_GPIO_NR(7, 6)
+#define LOCO_LED                        IMX_GPIO_NR(7, 7)
+#define LOCO_SD3_CD                     IMX_GPIO_NR(3, 11)
+#define LOCO_SD3_WP                     IMX_GPIO_NR(3, 12)
+#define LOCO_SD1_CD                     IMX_GPIO_NR(3, 13)
 
 static iomux_v3_cfg_t mx53_loco_pads[] = {
         /* FEC */
@@ -70,6 +74,8 @@ static iomux_v3_cfg_t mx53_loco_pads[] = {
         MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
         MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
         MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+        /* SD1_CD */
+        MX53_PAD_EIM_DA13__GPIO3_13,
         /* SD3 */
         MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
         MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
@@ -163,7 +169,7 @@ static iomux_v3_cfg_t mx53_loco_pads[] = {
         MX53_PAD_GPIO_7__SPDIF_PLOCK,
         MX53_PAD_GPIO_17__SPDIF_OUT1,
         /* GPIO */
-        MX53_PAD_PATA_DA_1__GPIO7_7,
+        MX53_PAD_PATA_DA_1__GPIO7_7,            /* LED */
         MX53_PAD_PATA_DA_2__GPIO7_8,
         MX53_PAD_PATA_DATA5__GPIO2_5,
         MX53_PAD_PATA_DATA6__GPIO2_6,
@@ -202,6 +208,15 @@ static const struct gpio_keys_platform_data loco_button_data __initconst = {
         .nbuttons       = ARRAY_SIZE(loco_buttons),
 };
 
+static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
+        .cd_gpio = LOCO_SD1_CD,
+};
+
+static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
+        .cd_gpio = LOCO_SD3_CD,
+        .wp_gpio = LOCO_SD3_WP,
+};
+
 static inline void mx53_loco_fec_reset(void)
 {
         int ret;
@@ -225,6 +240,19 @@ static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
         .bitrate = 100000,
 };
 
+static const struct gpio_led mx53loco_leds[] __initconst = {
+        {
+                .name                   = "green",
+                .default_trigger        = "heartbeat",
+                .gpio                   = LOCO_LED,
+        },
+};
+
+static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
+        .leds           = mx53loco_leds,
+        .num_leds       = ARRAY_SIZE(mx53loco_leds),
+};
+
 static void __init mx53_loco_board_init(void)
 {
         imx53_soc_init();
@@ -237,9 +265,10 @@ static void __init mx53_loco_board_init(void)
         imx53_add_imx2_wdt(0, NULL);
         imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
         imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
-        imx53_add_sdhci_esdhc_imx(0, NULL);
-        imx53_add_sdhci_esdhc_imx(2, NULL);
+        imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
+        imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
         imx_add_gpio_keys(&loco_button_data);
+        gpio_led_register_device(-1, &mx53loco_leds_data);
 }
 
 static void __init mx53_loco_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 0adeea17d123..23cd809fa8b8 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1254,12 +1254,20 @@ DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
 DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
         NULL,  NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(uart4_ipg_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG4_OFFSET,
+        NULL,  NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(uart5_ipg_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG6_OFFSET,
+        NULL,  NULL, &ipg_clk, &spba_clk);
 DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
         NULL,  NULL, &uart_root_clk, &uart1_ipg_clk);
 DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
         NULL,  NULL, &uart_root_clk, &uart2_ipg_clk);
 DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
         NULL,  NULL, &uart_root_clk, &uart3_ipg_clk);
+DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG5_OFFSET,
+        NULL,  NULL, &uart_root_clk, &uart4_ipg_clk);
+DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG7_OFFSET,
+        NULL,  NULL, &uart_root_clk, &uart5_ipg_clk);
 
 /* GPT */
 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
@@ -1279,6 +1287,8 @@ DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
         NULL, NULL, &ipg_perclk, NULL);
 DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
         NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(i2c3_mx53_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
+        NULL, NULL, &ipg_perclk, NULL);
 
 /* FEC */
 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
@@ -1463,11 +1473,14 @@ static struct clk_lookup mx53_lookups[] = {
         _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
         _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+        _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
+        _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_mx53_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk)
@@ -1479,6 +1492,11 @@ static struct clk_lookup mx53_lookups[] = {
         _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
+        _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+        _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
+        _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
 };
 
 static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index 87c0c58f27a7..5e11ba7daee2 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -114,6 +114,8 @@
 #define MXC_CCM_CCGR4           (MX51_CCM_BASE + 0x78)
 #define MXC_CCM_CCGR5           (MX51_CCM_BASE + 0x7C)
 #define MXC_CCM_CCGR6           (MX51_CCM_BASE + 0x80)
+#define MXC_CCM_CCGR7           (MX51_CCM_BASE + 0x84)
+
 #define MXC_CCM_CMEOR           (MX51_CCM_BASE + 0x84)
 
 /* Define the bits in register CCR */
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 48f4c8cc42f5..c27fe8bb4762 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -32,3 +32,11 @@ extern const struct imx_spi_imx_data imx53_ecspi_data[];
 extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
 #define imx53_add_imx2_wdt(id, pdata)   \
         imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
+
+extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
+#define imx53_add_imx_ssi(id, pdata)    \
+        imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
+
+extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
+#define imx53_add_imx_keypad(pdata)     \
+        imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index 665843d6c2b2..ef8aec9319b6 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -18,6 +18,7 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
+#include <mach/devices-common.h>
 #include <mach/iomux-v3.h>
 
 /*
@@ -100,6 +101,45 @@ void __init mx53_init_irq(void)
         tzic_init_irq(tzic_virt);
 }
 
+static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
+        .ap_2_ap_addr = 642,
+        .uart_2_mcu_addr = 817,
+        .mcu_2_app_addr = 747,
+        .mcu_2_shp_addr = 961,
+        .ata_2_mcu_addr = 1473,
+        .mcu_2_ata_addr = 1392,
+        .app_2_per_addr = 1033,
+        .app_2_mcu_addr = 683,
+        .shp_2_per_addr = 1251,
+        .shp_2_mcu_addr = 892,
+};
+
+static struct sdma_platform_data imx51_sdma_pdata __initdata = {
+        .sdma_version = 2,
+        .fw_name = "sdma-imx51.bin",
+        .script_addrs = &imx51_sdma_script,
+};
+
+static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
+        .ap_2_ap_addr = 642,
+        .app_2_mcu_addr = 683,
+        .mcu_2_app_addr = 747,
+        .uart_2_mcu_addr = 817,
+        .shp_2_mcu_addr = 891,
+        .mcu_2_shp_addr = 960,
+        .uartsh_2_mcu_addr = 1032,
+        .spdif_2_mcu_addr = 1100,
+        .mcu_2_spdif_addr = 1134,
+        .firi_2_mcu_addr = 1193,
+        .mcu_2_firi_addr = 1290,
+};
+
+static struct sdma_platform_data imx53_sdma_pdata __initdata = {
+        .sdma_version = 2,
+        .fw_name = "sdma-imx53.bin",
+        .script_addrs = &imx53_sdma_script,
+};
+
 void __init imx51_soc_init(void)
 {
         /* i.mx51 has the i.mx31 type gpio */
@@ -107,6 +147,8 @@ void __init imx51_soc_init(void)
         mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
         mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
         mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);
+
+        imx_add_imx_sdma(MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
 }
 
 void __init imx53_soc_init(void)
@@ -119,4 +161,6 @@ void __init imx53_soc_init(void)
         mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
         mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
         mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
+
+        imx_add_imx_sdma(MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
 }
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c
new file mode 100644
index 000000000000..e4529af0da72
--- /dev/null
+++ b/arch/arm/mach-mx5/pm-imx5.c
@@ -0,0 +1,73 @@
+/*
+ *  Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/suspend.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <mach/system.h>
+#include "crm_regs.h"
+
+static struct clk *gpc_dvfs_clk;
+
+static int mx5_suspend_enter(suspend_state_t state)
+{
+        clk_enable(gpc_dvfs_clk);
+        switch (state) {
+        case PM_SUSPEND_MEM:
+                mx5_cpu_lp_set(STOP_POWER_OFF);
+                break;
+        case PM_SUSPEND_STANDBY:
+                mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        if (state == PM_SUSPEND_MEM) {
+                local_flush_tlb_all();
+                flush_cache_all();
+
+                /*clear the EMPGC0/1 bits */
+                __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
+                __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
+        }
+        cpu_do_idle();
+        clk_disable(gpc_dvfs_clk);
+
+        return 0;
+}
+
+static int mx5_pm_valid(suspend_state_t state)
+{
+        return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
+}
+
+static const struct platform_suspend_ops mx5_suspend_ops = {
+        .valid = mx5_pm_valid,
+        .enter = mx5_suspend_enter,
+};
+
+static int __init mx5_pm_init(void)
+{
+        if (gpc_dvfs_clk == NULL)
+                gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
+
+        if (!IS_ERR(gpc_dvfs_clk)) {
+                if (cpu_is_mx51())
+                        suspend_set_ops(&mx5_suspend_ops);
+        } else
+                return -EPERM;
+
+        return 0;
+}
+device_initcall(mx5_pm_init);
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 162b0b0bc356..4cd0231ee539 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -41,6 +41,7 @@ config MACH_MX23EVK
 config MACH_MX28EVK
         bool "Support MX28EVK Platform"
         select SOC_IMX28
+        select LEDS_GPIO_REGISTER
         select MXS_HAVE_AMBA_DUART
         select MXS_HAVE_PLATFORM_AUART
         select MXS_HAVE_PLATFORM_FEC
@@ -60,6 +61,7 @@ config MODULE_TX28
         select MXS_HAVE_PLATFORM_AUART
         select MXS_HAVE_PLATFORM_FEC
         select MXS_HAVE_PLATFORM_MXS_I2C
+        select MXS_HAVE_PLATFORM_MXS_MMC
         select MXS_HAVE_PLATFORM_MXS_PWM
 
 config MACH_TX28
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index 56767a5cce0e..eaaf6ff28990 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -15,6 +15,7 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <linux/leds.h>
 #include <linux/irq.h>
 #include <linux/clk.h>
 
@@ -29,6 +30,7 @@
 
 #define MX28EVK_FLEXCAN_SWITCH  MXS_GPIO_NR(2, 13)
 #define MX28EVK_FEC_PHY_POWER   MXS_GPIO_NR(2, 15)
+#define MX28EVK_GPIO_LED        MXS_GPIO_NR(3, 5)
 #define MX28EVK_BL_ENABLE       MXS_GPIO_NR(3, 18)
 #define MX28EVK_LCD_ENABLE      MXS_GPIO_NR(3, 30)
 #define MX28EVK_FEC_PHY_RESET   MXS_GPIO_NR(4, 13)
@@ -178,6 +180,23 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = {
         /* slot power enable */
         MX28_PAD_PWM4__GPIO_3_29 |
                 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
+        /* led */
+        MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL,
+};
+
+/* led */
+static const struct gpio_led mx28evk_leds[] __initconst = {
+        {
+                .name = "GPIO-LED",
+                .default_trigger = "heartbeat",
+                .gpio = MX28EVK_GPIO_LED,
+        },
+};
+
+static const struct gpio_led_platform_data mx28evk_led_data __initconst = {
+        .leds = mx28evk_leds,
+        .num_leds = ARRAY_SIZE(mx28evk_leds),
 };
 
 /* fec */
@@ -385,6 +404,8 @@ static void __init mx28evk_init(void)
         if (ret)
                 pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret);
         mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
+
+        gpio_led_register_device(0, &mx28evk_led_data);
 }
 
 static void __init mx28evk_timer_init(void)
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
index 6766a12cca7f..515a423f82cd 100644
--- a/arch/arm/mach-mxs/mach-tx28.c
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -139,6 +139,11 @@ static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = {
         },
 };
 
+static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
+       .wp_gpio = -EINVAL,
+       .flags = SLOTF_4_BIT_CAPABLE,
+};
+
 static void __init tx28_stk5v3_init(void)
 {
         mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
@@ -155,6 +160,7 @@ static void __init tx28_stk5v3_init(void)
         mx28_add_mxs_i2c(0);
         i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo,
                         ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo));
+        mx28_add_mxs_mmc(0, &tx28_mmc0_pdata);
 }
 
 static void __init tx28_timer_init(void)
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 810a982a66f8..ef3e8b1e06c1 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -825,6 +825,7 @@ MACHINE_START(BALLOON3, "Balloon3")
         .map_io         = balloon3_map_io,
         .nr_irqs        = BALLOON3_NR_IRQS,
         .init_irq       = balloon3_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = balloon3_init,
         .boot_params    = PLAT_PHYS_OFFSET + 0x100,
diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c
index 4284513f396a..648b0ab2bf77 100644
--- a/arch/arm/mach-pxa/capc7117.c
+++ b/arch/arm/mach-pxa/capc7117.c
@@ -151,6 +151,7 @@ MACHINE_START(CAPC7117,
         .boot_params = 0xa0000100,
         .map_io = pxa3xx_map_io,
         .init_irq = pxa3xx_init_irq,
+        .handle_irq = pxa3xx_handle_irq,
         .timer = &pxa_timer,
         .init_machine = capc7117_init
 MACHINE_END
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index d5152220ce94..4d466102a027 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -53,6 +53,21 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
 
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long flags;
+        int ret = -EINVAL;
+
+        if (clk->ops->setrate) {
+                spin_lock_irqsave(&clocks_lock, flags);
+                ret = clk->ops->setrate(clk, rate);
+                spin_unlock_irqrestore(&clocks_lock, flags);
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
 void clk_dummy_enable(struct clk *clk)
 {
 }
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index 1f2fb9c43f06..3a258b1bf1aa 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -5,6 +5,7 @@ struct clkops {
         void                    (*enable)(struct clk *);
         void                    (*disable)(struct clk *);
         unsigned long           (*getrate)(struct clk *);
+        int                     (*setrate)(struct clk *, unsigned long);
 };
 
 struct clk {
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index bc55d07566ca..13cf518bbbf8 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -21,7 +21,8 @@
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 
-#include <mach/pxa2xx-regs.h>
+#include <mach/pxa25x.h>
+#include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
 #include <mach/smemc.h>
@@ -516,6 +517,8 @@ MACHINE_START(ARMCORE, "Compulab CM-X2XX")
         .map_io         = cmx2xx_map_io,
         .nr_irqs        = CMX2XX_NR_IRQS,
         .init_irq       = cmx2xx_init_irq,
+        /* NOTE: pxa25x_handle_irq() works on PXA27x w/o camera support */
+        .handle_irq     = pxa25x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = cmx2xx_init,
 #ifdef CONFIG_PCI
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index b199596f9c3d..b6a51340270b 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -855,6 +855,7 @@ MACHINE_START(CM_X300, "CM-X300 module")
         .boot_params    = 0xa0000100,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
+        .handle_irq     = pxa3xx_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = cm_x300_init,
         .fixup          = cm_x300_fixup,
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
index 7545a48ed88b..870920934ecf 100644
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -310,6 +310,7 @@ MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
         .init_machine   = colibri_pxa270_init,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
 MACHINE_END
 
@@ -318,6 +319,7 @@ MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC")
         .init_machine   = colibri_pxa270_income_init,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
 MACHINE_END
 
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index 66dd81cbc8a0..60a6781e7a8e 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -187,6 +187,7 @@ MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
         .init_machine   = colibri_pxa300_init,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
+        .handle_irq     = pxa3xx_handle_irq,
         .timer          = &pxa_timer,
 MACHINE_END
 
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index ff9ff5f4fc47..d2c6631915d4 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -23,8 +23,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 
-#include <mach/pxa3xx-regs.h>
-#include <mach/mfp-pxa320.h>
+#include <mach/pxa320.h>
 #include <mach/colibri.h>
 #include <mach/pxafb.h>
 #include <mach/ohci.h>
@@ -258,6 +257,7 @@ MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
         .init_machine   = colibri_pxa320_init,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
+        .handle_irq     = pxa3xx_handle_irq,
         .timer          = &pxa_timer,
 MACHINE_END
 
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 3a5507e31919..185a37cad254 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -722,6 +722,7 @@ MACHINE_START(CORGI, "SHARP Corgi")
         .fixup          = fixup_corgi,
         .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .init_machine   = corgi_init,
         .timer          = &pxa_timer,
 MACHINE_END
@@ -732,6 +733,7 @@ MACHINE_START(SHEPHERD, "SHARP Shepherd")
         .fixup          = fixup_corgi,
         .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .init_machine   = corgi_init,
         .timer          = &pxa_timer,
 MACHINE_END
@@ -742,6 +744,7 @@ MACHINE_START(HUSKY, "SHARP Husky")
         .fixup          = fixup_corgi,
         .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .init_machine   = corgi_init,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index 0481c29a70e8..fe812eafb1f1 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -22,10 +22,9 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/csb726.h>
-#include <mach/mfp-pxa27x.h>
+#include <mach/pxa27x.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
-#include <mach/pxa2xx-regs.h>
 #include <mach/audio.h>
 #include <mach/smemc.h>
 
@@ -276,6 +275,7 @@ MACHINE_START(CSB726, "Cogent CSB726")
         .boot_params    = 0xa0000100,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq       = pxa27x_handle_irq,
         .init_machine   = csb726_init,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index f8a6e9d79a3a..2e37ea52b372 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -1302,6 +1302,7 @@ MACHINE_START(EM_X270, "Compulab EM-X270")
         .boot_params    = 0xa0000100,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = em_x270_init,
 MACHINE_END
@@ -1310,6 +1311,7 @@ MACHINE_START(EXEDA, "Compulab eXeda")
         .boot_params    = 0xa0000100,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = em_x270_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 2e3970fdde0b..b4599ec9d619 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -193,6 +193,7 @@ MACHINE_START(E330, "Toshiba e330")
         .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e330_init,
         .timer          = &pxa_timer,
@@ -242,6 +243,7 @@ MACHINE_START(E350, "Toshiba e350")
         .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e350_init,
         .timer          = &pxa_timer,
@@ -364,6 +366,7 @@ MACHINE_START(E400, "Toshiba e400")
         .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e400_init,
         .timer          = &pxa_timer,
@@ -552,6 +555,7 @@ MACHINE_START(E740, "Toshiba e740")
         .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e740_init,
         .timer          = &pxa_timer,
@@ -743,6 +747,7 @@ MACHINE_START(E750, "Toshiba e750")
         .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e750_init,
         .timer          = &pxa_timer,
@@ -947,6 +952,7 @@ MACHINE_START(E800, "Toshiba e800")
         .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e800_init,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index d88aed8fbe15..b73eadb9f5dc 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -801,6 +801,7 @@ MACHINE_START(EZX_A780, "Motorola EZX A780")
         .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq       = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = a780_init,
 MACHINE_END
@@ -866,6 +867,7 @@ MACHINE_START(EZX_E680, "Motorola EZX E680")
         .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq       = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = e680_init,
 MACHINE_END
@@ -931,6 +933,7 @@ MACHINE_START(EZX_A1200, "Motorola EZX A1200")
         .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq       = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = a1200_init,
 MACHINE_END
@@ -1121,6 +1124,7 @@ MACHINE_START(EZX_A910, "Motorola EZX A910")
         .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq       = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = a910_init,
 MACHINE_END
@@ -1186,6 +1190,7 @@ MACHINE_START(EZX_E6, "Motorola EZX E6")
         .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq       = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = e6_init,
 MACHINE_END
@@ -1225,6 +1230,7 @@ MACHINE_START(EZX_E2, "Motorola EZX E2")
         .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq       = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = e2_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index e6c9344a95ae..92a2e85ab02c 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -13,21 +13,8 @@ struct irq_data;
 struct sys_timer;
 
 extern struct sys_timer pxa_timer;
-extern void __init pxa_init_irq(int irq_nr,
-                                int (*set_wake)(struct irq_data *,
-                                                unsigned int));
-extern void __init pxa25x_init_irq(void);
-#ifdef CONFIG_CPU_PXA26x
-extern void __init pxa26x_init_irq(void);
-#endif
-extern void __init pxa27x_init_irq(void);
-extern void __init pxa3xx_init_irq(void);
-extern void __init pxa95x_init_irq(void);
 
 extern void __init pxa_map_io(void);
-extern void __init pxa25x_map_io(void);
-extern void __init pxa27x_map_io(void);
-extern void __init pxa3xx_map_io(void);
 
 extern unsigned int get_clk_frequency_khz(int info);
 
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index d65e4bde9b91..deaa111c91f9 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -236,6 +236,7 @@ MACHINE_START(GUMSTIX, "Gumstix")
         .boot_params    = 0xa0000100, /* match u-boot bi_boot_params */
         .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = gumstix_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
index 657db469de1f..0a235128914d 100644
--- a/arch/arm/mach-pxa/h5000.c
+++ b/arch/arm/mach-pxa/h5000.c
@@ -28,6 +28,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/irq.h>
 
 #include <mach/pxa25x.h>
 #include <mach/h5000.h>
@@ -205,6 +206,7 @@ MACHINE_START(H5400, "HP iPAQ H5000")
         .boot_params = 0xa0000100,
         .map_io = pxa25x_map_io,
         .init_irq = pxa25x_init_irq,
+        .handle_irq = pxa25x_handle_irq,
         .timer = &pxa_timer,
         .init_machine = h5000_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c
index e8603eba54bd..a997d0ab2872 100644
--- a/arch/arm/mach-pxa/himalaya.c
+++ b/arch/arm/mach-pxa/himalaya.c
@@ -24,8 +24,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/mfp-pxa25x.h>
-#include <mach/hardware.h>
+#include <mach/pxa25x.h>
 
 #include "generic.h"
 
@@ -162,6 +161,7 @@ MACHINE_START(HIMALAYA, "HTC Himalaya")
         .boot_params = 0xa0000100,
         .map_io = pxa25x_map_io,
         .init_irq = pxa25x_init_irq,
+        .handle_irq = pxa25x_handle_irq,
         .init_machine = himalaya_init,
         .timer = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 99960a1814e0..c748a473a2ff 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -842,6 +842,7 @@ MACHINE_START(H4700, "HP iPAQ HX4700")
         .map_io       = pxa27x_map_io,
         .nr_irqs      = HX4700_NR_IRQS,
         .init_irq     = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .init_machine = hx4700_init,
         .timer        = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
index 6cedc81da3bc..d427429f1f34 100644
--- a/arch/arm/mach-pxa/icontrol.c
+++ b/arch/arm/mach-pxa/icontrol.c
@@ -194,6 +194,7 @@ MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
         .boot_params    = 0xa0000100,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
+        .handle_irq     = pxa3xx_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = icontrol_init
 MACHINE_END
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index f7fb64f11a7d..ddf20e5c376e 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -196,6 +196,7 @@ MACHINE_START(PXA_IDP, "Vibren PXA255 IDP")
         /* Maintainer: Vibren Technologies */
         .map_io         = idp_map_io,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = idp_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index 038402404e39..7cc5a781e99e 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -104,4 +104,16 @@
 
 #define NR_IRQS                 (IRQ_BOARD_START)
 
+#ifndef __ASSEMBLY__
+struct irq_data;
+struct pt_regs;
+
+void pxa_mask_irq(struct irq_data *);
+void pxa_unmask_irq(struct irq_data *);
+void icip_handle_irq(struct pt_regs *);
+void ichp_handle_irq(struct pt_regs *);
+
+void pxa_init_irq(int irq_nr, int (*set_wake)(struct irq_data *, unsigned int));
+#endif
+
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa25x.h b/arch/arm/mach-pxa/include/mach/pxa25x.h
index 508c3ba1f4d0..3ac0baac7350 100644
--- a/arch/arm/mach-pxa/include/mach/pxa25x.h
+++ b/arch/arm/mach-pxa/include/mach/pxa25x.h
@@ -4,5 +4,14 @@
 #include <mach/hardware.h>
 #include <mach/pxa2xx-regs.h>
 #include <mach/mfp-pxa25x.h>
+#include <mach/irqs.h>
+
+extern void __init pxa25x_map_io(void);
+extern void __init pxa25x_init_irq(void);
+#ifdef CONFIG_CPU_PXA26x
+extern void __init pxa26x_init_irq(void);
+#endif
+
+#define pxa25x_handle_irq       icip_handle_irq
 
 #endif /* __MACH_PXA25x_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h
index 0b702693f458..b9b1bdc4bacc 100644
--- a/arch/arm/mach-pxa/include/mach/pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/pxa27x.h
@@ -4,6 +4,7 @@
 #include <mach/hardware.h>
 #include <mach/pxa2xx-regs.h>
 #include <mach/mfp-pxa27x.h>
+#include <mach/irqs.h>
 
 #define ARB_CNTRL       __REG(0x48000048)  /* Arbiter Control Register */
 
@@ -17,6 +18,10 @@
 #define ARB_CORE_PARK           (1<<24)    /* Be parked with core when idle */
 #define ARB_LOCK_FLAG           (1<<23)    /* Only Locking masters gain access to the bus */
 
+extern void __init pxa27x_map_io(void);
+extern void __init pxa27x_init_irq(void);
 extern int __init pxa27x_set_pwrmode(unsigned int mode);
 
+#define pxa27x_handle_irq       ichp_handle_irq
+
 #endif /* __MACH_PXA27x_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa300.h b/arch/arm/mach-pxa/include/mach/pxa300.h
index 2f33076c9e48..733b6412c3df 100644
--- a/arch/arm/mach-pxa/include/mach/pxa300.h
+++ b/arch/arm/mach-pxa/include/mach/pxa300.h
@@ -1,8 +1,7 @@
 #ifndef __MACH_PXA300_H
 #define __MACH_PXA300_H
 
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
+#include <mach/pxa3xx.h>
 #include <mach/mfp-pxa300.h>
 
 #endif /* __MACH_PXA300_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa320.h b/arch/arm/mach-pxa/include/mach/pxa320.h
index cab78e903273..b6204e470d89 100644
--- a/arch/arm/mach-pxa/include/mach/pxa320.h
+++ b/arch/arm/mach-pxa/include/mach/pxa320.h
@@ -1,8 +1,7 @@
 #ifndef __MACH_PXA320_H
 #define __MACH_PXA320_H
 
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
+#include <mach/pxa3xx.h>
 #include <mach/mfp-pxa320.h>
 
 #endif /* __MACH_PXA320_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx.h b/arch/arm/mach-pxa/include/mach/pxa3xx.h
new file mode 100644
index 000000000000..cd3e57f42688
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx.h
@@ -0,0 +1,14 @@
+#ifndef __MACH_PXA3XX_H 
+#define __MACH_PXA3XX_H
+
+#include <mach/hardware.h>
+#include <mach/pxa3xx-regs.h>
+#include <mach/irqs.h>
+
+extern void __init pxa3xx_map_io(void);
+extern void __init pxa3xx_init_irq(void);
+extern void __init pxa95x_init_irq(void);
+
+#define pxa3xx_handle_irq       ichp_handle_irq
+
+#endif /* __MACH_PXA3XX_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa930.h b/arch/arm/mach-pxa/include/mach/pxa930.h
index d45f76a9b54d..190363b98d01 100644
--- a/arch/arm/mach-pxa/include/mach/pxa930.h
+++ b/arch/arm/mach-pxa/include/mach/pxa930.h
@@ -1,8 +1,7 @@
 #ifndef __MACH_PXA930_H
 #define __MACH_PXA930_H
 
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
+#include <mach/pxa3xx.h>
 #include <mach/mfp-pxa930.h>
 
 #endif /* __MACH_PXA930_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h
deleted file mode 100644
index 662288eb6f95..000000000000
--- a/arch/arm/mach-pxa/include/mach/regs-intc.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __ASM_MACH_REGS_INTC_H
-#define __ASM_MACH_REGS_INTC_H
-
-#include <mach/hardware.h>
-
-/*
- * Interrupt Controller
- */
-
-#define ICIP            __REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
-#define ICMR            __REG(0x40D00004)  /* Interrupt Controller Mask Register */
-#define ICLR            __REG(0x40D00008)  /* Interrupt Controller Level Register */
-#define ICFP            __REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
-#define ICPR            __REG(0x40D00010)  /* Interrupt Controller Pending Register */
-#define ICCR            __REG(0x40D00014)  /* Interrupt Controller Control Register */
-#define ICHP            __REG(0x40D00018)  /* Interrupt Controller Highest Priority Register */
-
-#define ICIP2           __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2           __REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
-#define ICLR2           __REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
-#define ICFP2           __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2           __REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
-
-#define ICIP3           __REG(0x40D00130)  /* Interrupt Controller IRQ Pending Register 3 */
-#define ICMR3           __REG(0x40D00134)  /* Interrupt Controller Mask Register 3 */
-#define ICLR3           __REG(0x40D00138)  /* Interrupt Controller Level Register 3 */
-#define ICFP3           __REG(0x40D0013C)  /* Interrupt Controller FIQ Pending Register 3 */
-#define ICPR3           __REG(0x40D00140)  /* Interrupt Controller Pending Register 3 */
-
-#endif /* __ASM_MACH_REGS_INTC_H */
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 32ed551bf9c5..b09e848eb6c6 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -37,6 +37,8 @@
 #define IPR(i)                  (((i) < 32) ? (0x01c + ((i) << 2)) :            \
                                 ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) :      \
                                       (0x144 + (((i) - 64) << 2)))
+#define ICHP_VAL_IRQ            (1 << 31)
+#define ICHP_IRQ(i)             (((i) >> 16) & 0x7fff)
 #define IPR_VALID               (1 << 31)
 #define IRQ_BIT(n)              (((n) - PXA_IRQ(0)) & 0x1f)
 
@@ -64,7 +66,7 @@ static inline void __iomem *irq_base(int i)
         return (void __iomem *)io_p2v(phys_base[i]);
 }
 
-static void pxa_mask_irq(struct irq_data *d)
+void pxa_mask_irq(struct irq_data *d)
 {
         void __iomem *base = irq_data_get_irq_chip_data(d);
         uint32_t icmr = __raw_readl(base + ICMR);
@@ -73,7 +75,7 @@ static void pxa_mask_irq(struct irq_data *d)
         __raw_writel(icmr, base + ICMR);
 }
 
-static void pxa_unmask_irq(struct irq_data *d)
+void pxa_unmask_irq(struct irq_data *d)
 {
         void __iomem *base = irq_data_get_irq_chip_data(d);
         uint32_t icmr = __raw_readl(base + ICMR);
@@ -127,6 +129,36 @@ static struct irq_chip pxa_low_gpio_chip = {
         .irq_set_type   = pxa_set_low_gpio_type,
 };
 
+asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
+{
+        uint32_t icip, icmr, mask;
+
+        do {
+                icip = __raw_readl(IRQ_BASE + ICIP);
+                icmr = __raw_readl(IRQ_BASE + ICMR);
+                mask = icip & icmr;
+
+                if (mask == 0)
+                        break;
+
+                handle_IRQ(PXA_IRQ(fls(mask) - 1), regs);
+        } while (1);
+}
+
+asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
+{
+        uint32_t ichp;
+
+        do {
+                __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp));
+
+                if ((ichp & ICHP_VAL_IRQ) == 0)
+                        break;
+
+                handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs);
+        } while (1);
+}
+
 static void __init pxa_init_low_gpio_irq(set_wake_t fn)
 {
         int irq;
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index e5e326d2cdc9..8f97e15e86e5 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -441,6 +441,7 @@ MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleto
         .map_io         = pxa3xx_map_io,
         .nr_irqs        = LITTLETON_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
+        .handle_irq     = pxa3xx_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = littleton_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 6cf8180bf5bd..c171d6ebee49 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -503,6 +503,7 @@ MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
         .map_io         = lpd270_map_io,
         .nr_irqs        = LPD270_NR_IRQS,
         .init_irq       = lpd270_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = lpd270_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index e10ddb827147..a8c696bfc132 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -553,6 +553,7 @@ MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
         .map_io         = lubbock_map_io,
         .nr_irqs        = LUBBOCK_NR_IRQS,
         .init_irq       = lubbock_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = lubbock_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 0e42798942f7..5fe5bcd7c0a1 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -757,6 +757,7 @@ MACHINE_START(MAGICIAN, "HTC Magician")
         .map_io = pxa27x_map_io,
         .nr_irqs = MAGICIAN_NR_IRQS,
         .init_irq = pxa27x_init_irq,
+        .handle_irq = pxa27x_handle_irq,
         .init_machine = magician_init,
         .timer = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 3479e2b3b511..4622eb78ef25 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -620,6 +620,7 @@ MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
         .map_io         = mainstone_map_io,
         .nr_irqs        = MAINSTONE_NR_IRQS,
         .init_irq       = mainstone_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = mainstone_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index aa67637ae41d..64810f908e5b 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -754,6 +754,7 @@ MACHINE_START(MIOA701, "MIO A701")
         .boot_params    = 0xa0000100,
         .map_io         = &pxa27x_map_io,
         .init_irq       = &pxa27x_init_irq,
+        .handle_irq     = &pxa27x_handle_irq,
         .init_machine   = mioa701_machine_init,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
index 59cce78aebd1..fb408861dbcf 100644
--- a/arch/arm/mach-pxa/mp900.c
+++ b/arch/arm/mach-pxa/mp900.c
@@ -96,6 +96,7 @@ MACHINE_START(NEC_MP900, "MobilePro900/C")
         .timer          = &pxa_timer,
         .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .init_machine   = mp900c_init,
 MACHINE_END
 
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 4061ecddee70..6b77365ed938 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -345,6 +345,7 @@ MACHINE_START(PALMLD, "Palm LifeDrive")
         .boot_params    = 0xa0000100,
         .map_io         = palmld_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = palmld_init
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index df4d7d009fbb..9bd3e47486fb 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -206,6 +206,7 @@ MACHINE_START(PALMT5, "Palm Tungsten|T5")
         .map_io         = pxa27x_map_io,
         .reserve        = palmt5_reserve,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = palmt5_init
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index fb06bd047272..6ad4a6c7bc96 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -31,14 +31,13 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
+#include <mach/pxa25x.h>
 #include <mach/audio.h>
 #include <mach/palmtc.h>
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
-#include <mach/mfp-pxa25x.h>
 #include <mach/irda.h>
 #include <mach/udc.h>
-#include <mach/pxa2xx-regs.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -541,6 +540,7 @@ MACHINE_START(PALMTC, "Palm Tungsten|C")
         .boot_params    = 0xa0000100,
         .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = palmtc_init
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 726f5b98dcd3..664232f3e62c 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -31,11 +31,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
+#include <mach/pxa25x.h>
 #include <mach/audio.h>
 #include <mach/palmte2.h>
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
-#include <mach/mfp-pxa25x.h>
 #include <mach/irda.h>
 #include <mach/udc.h>
 #include <mach/palmasoc.h>
@@ -359,6 +359,7 @@ MACHINE_START(PALMTE2, "Palm Tungsten|E2")
         .boot_params    = 0xa0000100,
         .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = palmte2_init
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index 20d1b18b1733..bb27d4b688d8 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -444,6 +444,7 @@ MACHINE_START(TREO680, "Palm Treo 680")
         .map_io         = pxa27x_map_io,
         .reserve        = treo_reserve,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq       = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = treo680_init,
 MACHINE_END
@@ -453,6 +454,7 @@ MACHINE_START(CENTRO, "Palm Centro 685")
         .map_io         = pxa27x_map_io,
         .reserve        = treo_reserve,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq       = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = centro_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 595f002066cc..fc4285589c1f 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -367,6 +367,7 @@ MACHINE_START(PALMTX, "Palm T|X")
         .boot_params    = 0xa0000100,
         .map_io         = palmtx_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = palmtx_init
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 5a5329bc33f1..e61c1cc05519 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -402,6 +402,7 @@ MACHINE_START(PALMZ72, "Palm Zire72")
         .boot_params    = 0xa0000100,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = palmz72_init
 MACHINE_END
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index 1fc8a66407ae..ffa65dfb8c6f 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -262,6 +262,7 @@ MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270")
         .map_io         = pcm027_map_io,
         .nr_irqs        = PCM027_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = pcm027_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 16d14fd79b4b..a113ea9ab4ab 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -468,6 +468,7 @@ MACHINE_START(POODLE, "SHARP Poodle")
         .map_io         = pxa25x_map_io,
         .nr_irqs        = POODLE_NR_IRQS,       /* 4 for LoCoMo */
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = poodle_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index ef1c56a67afc..b5cd9e5aba31 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -32,7 +32,6 @@
 #include <mach/ohci.h>
 #include <mach/pm.h>
 #include <mach/dma.h>
-#include <mach/regs-intc.h>
 #include <mach/smemc.h>
 
 #include "generic.h"
@@ -338,13 +337,13 @@ static void pxa_ack_ext_wakeup(struct irq_data *d)
 
 static void pxa_mask_ext_wakeup(struct irq_data *d)
 {
-        ICMR2 &= ~(1 << ((d->irq - PXA_IRQ(0)) & 0x1f));
+        pxa_mask_irq(d);
         PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
 }
 
 static void pxa_unmask_ext_wakeup(struct irq_data *d)
 {
-        ICMR2 |= 1 << ((d->irq - PXA_IRQ(0)) & 0x1f);
+        pxa_unmask_irq(d);
         PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
 }
 
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
index ecc82a330fad..0ee166b61f81 100644
--- a/arch/arm/mach-pxa/pxa95x.c
+++ b/arch/arm/mach-pxa/pxa95x.c
@@ -27,7 +27,6 @@
 #include <mach/reset.h>
 #include <mach/pm.h>
 #include <mach/dma.h>
-#include <mach/regs-intc.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 2f37d43f51b6..bbcd90562ebe 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -46,10 +46,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
-#include <mach/mfp-pxa3xx.h>
-#include <mach/mfp-pxa300.h>
+#include <mach/pxa300.h>
 #include <mach/ohci.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
@@ -1093,6 +1090,7 @@ MACHINE_START(RAUMFELD_RC, "Raumfeld Controller")
         .init_machine   = raumfeld_controller_init,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
+        .handle_irq     = pxa3xx_handle_irq,
         .timer          = &pxa_timer,
 MACHINE_END
 #endif
@@ -1103,6 +1101,7 @@ MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector")
         .init_machine   = raumfeld_connector_init,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
+        .handle_irq     = pxa3xx_handle_irq,
         .timer          = &pxa_timer,
 MACHINE_END
 #endif
@@ -1113,6 +1112,7 @@ MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker")
         .init_machine   = raumfeld_speaker_init,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
+        .handle_irq     = pxa3xx_handle_irq,
         .timer          = &pxa_timer,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index fee97a935122..df4356e8acae 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -599,6 +599,7 @@ MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
         .boot_params    = 0xa0000100,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
+        .handle_irq       = pxa3xx_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = saar_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c
index e53a3334c944..ebd6379c4969 100644
--- a/arch/arm/mach-pxa/saarb.c
+++ b/arch/arm/mach-pxa/saarb.c
@@ -107,6 +107,7 @@ MACHINE_START(SAARB, "PXA955 Handheld Platform (aka SAARB)")
         .map_io         = pxa3xx_map_io,
         .nr_irqs        = SAARB_NR_IRQS,
         .init_irq       = pxa95x_init_irq,
+        .handle_irq     = pxa3xx_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = saarb_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 01c576963e94..438c7b5e451f 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -984,6 +984,7 @@ MACHINE_START(SPITZ, "SHARP Spitz")
         .fixup          = spitz_fixup,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .init_machine   = spitz_init,
         .timer          = &pxa_timer,
 MACHINE_END
@@ -994,6 +995,7 @@ MACHINE_START(BORZOI, "SHARP Borzoi")
         .fixup          = spitz_fixup,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .init_machine   = spitz_init,
         .timer          = &pxa_timer,
 MACHINE_END
@@ -1004,6 +1006,7 @@ MACHINE_START(AKITA, "SHARP Akita")
         .fixup          = spitz_fixup,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .init_machine   = spitz_init,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index cb5611daf5fe..3f8d0af9e2f7 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -1001,6 +1001,7 @@ static void __init stargate2_init(void)
 MACHINE_START(INTELMOTE2, "IMOTE 2")
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = imote2_init,
         .boot_params    = 0xA0000100,
@@ -1012,6 +1013,7 @@ MACHINE_START(STARGATE2, "Stargate 2")
         .map_io = pxa27x_map_io,
         .nr_irqs = STARGATE_NR_IRQS,
         .init_irq = pxa27x_init_irq,
+        .handle_irq = pxa27x_handle_irq,
         .timer = &pxa_timer,
         .init_machine = stargate2_init,
         .boot_params = 0xA0000100,
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 53d4a472b699..32fb58e01b10 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -492,6 +492,7 @@ MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)")
         .boot_params    = 0xa0000100,
         .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
+        .handle_irq       = pxa3xx_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = tavorevb_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c
index 79f4422f12f4..fd5a8eae0a87 100644
--- a/arch/arm/mach-pxa/tavorevb3.c
+++ b/arch/arm/mach-pxa/tavorevb3.c
@@ -129,6 +129,7 @@ MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)")
         .map_io         = pxa3xx_map_io,
         .nr_irqs        = TAVOREVB3_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
+        .handle_irq       = pxa3xx_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = evb3_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 5fa145778e7d..9f69a2682693 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -974,6 +974,7 @@ MACHINE_START(TOSA, "SHARP Tosa")
         .map_io         = pxa25x_map_io,
         .nr_irqs        = TOSA_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq       = pxa25x_handle_irq,
         .init_machine   = tosa_init,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 687417a93698..c0417508f39d 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -558,6 +558,7 @@ MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
         .init_machine   = trizeps4_init,
         .map_io         = trizeps4_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
 MACHINE_END
 
@@ -567,5 +568,6 @@ MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module")
         .init_machine   = trizeps4_init,
         .map_io         = trizeps4_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 903218eab56d..d4a3dc74e84a 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -995,6 +995,7 @@ MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC")
         .boot_params    = 0xa0000100,
         .map_io         = viper_map_io,
         .init_irq       = viper_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = viper_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index 67bd41488bf8..5f8490ab07cb 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -719,6 +719,7 @@ MACHINE_START(VPAC270, "Voipac PXA270")
         .boot_params    = 0xa0000100,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = vpac270_init
 MACHINE_END
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c
index f55f8f2e0db3..acc600f5e72f 100644
--- a/arch/arm/mach-pxa/xcep.c
+++ b/arch/arm/mach-pxa/xcep.c
@@ -28,8 +28,7 @@
 #include <asm/mach/map.h>
 
 #include <mach/hardware.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa25x.h>
+#include <mach/pxa25x.h>
 #include <mach/smemc.h>
 
 #include "generic.h"
@@ -185,6 +184,7 @@ MACHINE_START(XCEP, "Iskratel XCEP")
         .init_machine   = xcep_init,
         .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
+        .handle_irq     = pxa25x_handle_irq,
         .timer          = &pxa_timer,
 MACHINE_END
 
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index fbe9e02e2f9f..6c9275a20c91 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -40,6 +40,7 @@
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <plat/pxa27x_keypad.h>
+#include <mach/pm.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -677,6 +678,20 @@ static void __init z2_pmic_init(void)
 static inline void z2_pmic_init(void) {}
 #endif
 
+#ifdef CONFIG_PM
+static void z2_power_off(void)
+{
+        /* We're using deep sleep as poweroff, so clear PSPR to ensure that
+         * bootloader will jump to its entry point in resume handler
+         */
+        PSPR = 0x0;
+        local_irq_disable();
+        pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET);
+}
+#else
+#define z2_power_off   NULL
+#endif
+
 /******************************************************************************
  * Machine init
  ******************************************************************************/
@@ -698,12 +713,15 @@ static void __init z2_init(void)
         z2_leds_init();
         z2_keys_init();
         z2_pmic_init();
+
+        pm_power_off = z2_power_off;
 }
 
 MACHINE_START(ZIPIT2, "Zipit Z2")
         .boot_params    = 0xa0000100,
         .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = z2_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 9b99cc164de5..99c49bcd9f70 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -35,14 +35,13 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <mach/pxa2xx-regs.h>
+#include <mach/pxa27x.h>
 #include <mach/regs-uart.h>
 #include <mach/ohci.h>
 #include <mach/mmc.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/udc.h>
 #include <mach/pxafb.h>
-#include <mach/mfp-pxa27x.h>
 #include <mach/pm.h>
 #include <mach/audio.h>
 #include <mach/arcom-pcmcia.h>
@@ -909,6 +908,7 @@ MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
         .map_io         = zeus_map_io,
         .nr_irqs        = ZEUS_NR_IRQS,
         .init_irq       = zeus_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = zeus_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 5821185f77ab..15ec66b3471a 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -24,7 +24,7 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/hardware.h>
+#include <mach/pxa3xx.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
 #include <mach/zylonite.h>
@@ -426,6 +426,7 @@ MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
         .map_io         = pxa3xx_map_io,
         .nr_irqs        = ZYLONITE_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
+        .handle_irq     = pxa3xx_handle_irq,
         .timer          = &pxa_timer,
         .init_machine   = zylonite_init,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2410/include/mach/pm-core.h b/arch/arm/mach-s3c2410/include/mach/pm-core.h
index 70a83b209e25..45eea5210c87 100644
--- a/arch/arm/mach-s3c2410/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c2410/include/mach/pm-core.h
@@ -62,3 +62,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
                                            struct pm_uart_save *save)
 {
 }
+
+static inline void s3c_pm_restored_gpios(void) { }
+static inline void s3c_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
index ddb63a1863ab..c026f67a80de 100644
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -217,6 +217,7 @@
 /* Compatibility */
 
 #define IRQ_ONENAND     IRQ_ONENAND0
+#define IRQ_I2S0        IRQ_S3C6410_IIS
 
 #endif /* __ASM_MACH_S3C64XX_IRQS_H */
 
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
index 1e9f20f0bb7b..38659bebe4b1 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
@@ -53,7 +53,7 @@ static inline void s3c_pm_arch_show_resume_irqs(void)
  * the IRQ wake controls depending on the CPU we are running on */
 
 #define s3c_irqwake_eintallow   ((1 << 28) - 1)
-#define s3c_irqwake_intallow    (0)
+#define s3c_irqwake_intallow    (~0)
 
 static inline void s3c_pm_arch_update_uart(void __iomem *regs,
                                            struct pm_uart_save *save)
@@ -96,3 +96,20 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
                 save->ucon = new_ucon;
         }
 }
+
+static inline void s3c_pm_restored_gpios(void)
+{
+        /* ensure sleep mode has been cleared from the system */
+
+        __raw_writel(0, S3C64XX_SLPEN);
+}
+
+static inline void s3c_pm_saved_gpios(void)
+{
+        /* turn on the sleep mode and keep it there, as it seems that during
+         * suspend the xCON registers get re-set and thus you can end up with
+         * problems between going to sleep and resuming.
+         */
+
+        __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
+}
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c
index 97660c8141ae..75d9a0e49193 100644
--- a/arch/arm/mach-s3c64xx/irq.c
+++ b/arch/arm/mach-s3c64xx/irq.c
@@ -48,14 +48,22 @@ static struct s3c_uart_irq uart_irqs[] = {
         },
 };
 
+/* setup the sources the vic should advertise resume for, even though it
+ * is not doing the wake (set_irq_wake needs to be valid) */
+#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
+#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
+                         1 << (IRQ_PENDN - IRQ_VIC1_BASE) |     \
+                         1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |    \
+                         1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |    \
+                         1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
 
 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
 {
         printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
 
         /* initialise the pair of VICs */
-        vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0);
-        vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0);
+        vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
+        vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
 
         /* add the timer sub-irqs */
         s3c_init_vic_timer_irq(5, IRQ_TIMER0);
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index ae6bf6feba89..5f6afdf067ed 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -13,7 +13,7 @@ obj-				:=
 # Core support for S5P64X0 system
 
 obj-$(CONFIG_ARCH_S5P64X0)      += cpu.o init.o clock.o dma.o gpiolib.o
-obj-$(CONFIG_ARCH_S5P64X0)      += setup-i2c0.o
+obj-$(CONFIG_ARCH_S5P64X0)      += setup-i2c0.o irq-eint.o
 obj-$(CONFIG_CPU_S5P6440)       += clock-s5p6440.o
 obj-$(CONFIG_CPU_S5P6450)       += clock-s5p6450.o
 
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 513abffc7604..5837a36ece8d 100644
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -85,6 +85,8 @@
 #define IRQ_S3CUART_RX4         IRQ_S5P_UART_RX4
 #define IRQ_S3CUART_RX5         IRQ_S5P_UART_RX5
 
+#define IRQ_I2S0                IRQ_I2SV40
+
 /* S5P6450 EINT feature will be added */
 
 /*
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 0953ef6b1c77..6ce254729f3b 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -34,4 +34,14 @@
 #define S5P6450_GPQ_BASE                (S5P_VA_GPIO + 0x0180)
 #define S5P6450_GPS_BASE                (S5P_VA_GPIO + 0x0300)
 
+/* External interrupt control registers for group0 */
+
+#define EINT0CON0_OFFSET                (0x900)
+#define EINT0MASK_OFFSET                (0x920)
+#define EINT0PEND_OFFSET                (0x924)
+
+#define S5P64X0_EINT0CON0               (S5P_VA_GPIO + EINT0CON0_OFFSET)
+#define S5P64X0_EINT0MASK               (S5P_VA_GPIO + EINT0MASK_OFFSET)
+#define S5P64X0_EINT0PEND               (S5P_VA_GPIO + EINT0PEND_OFFSET)
+
 #endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c
new file mode 100644
index 000000000000..69ed4545112b
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/irq-eint.c
@@ -0,0 +1,152 @@
+/* arch/arm/mach-s5p64x0/irq-eint.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *              http://www.samsung.com/
+ *
+ * Based on linux/arch/arm/mach-s3c64xx/irq-eint.c
+ *
+ * S5P64X0 - Interrupt handling for External Interrupts.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <plat/regs-irqtype.h>
+#include <plat/gpio-cfg.h>
+
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+
+#define eint_offset(irq)        ((irq) - IRQ_EINT(0))
+
+static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
+{
+        int offs = eint_offset(data->irq);
+        int shift;
+        u32 ctrl, mask;
+        u32 newvalue = 0;
+
+        if (offs > 15)
+                return -EINVAL;
+
+        switch (type) {
+        case IRQ_TYPE_NONE:
+                printk(KERN_WARNING "No edge setting!\n");
+                break;
+        case IRQ_TYPE_EDGE_RISING:
+                newvalue = S3C2410_EXTINT_RISEEDGE;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                newvalue = S3C2410_EXTINT_FALLEDGE;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                newvalue = S3C2410_EXTINT_BOTHEDGE;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                newvalue = S3C2410_EXTINT_LOWLEV;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                newvalue = S3C2410_EXTINT_HILEV;
+                break;
+        default:
+                printk(KERN_ERR "No such irq type %d", type);
+                return -EINVAL;
+        }
+
+        shift = (offs / 2) * 4;
+        mask = 0x7 << shift;
+
+        ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
+        ctrl |= newvalue << shift;
+        __raw_writel(ctrl, S5P64X0_EINT0CON0);
+
+        /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
+        if (0x50000 == (__raw_readl(S5P64X0_SYS_ID) & 0xFF000))
+                s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
+        else
+                s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
+
+        return 0;
+}
+
+/*
+ * s5p64x0_irq_demux_eint
+ *
+ * This function demuxes the IRQ from the group0 external interrupts,
+ * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
+ * the specific handlers s5p64x0_irq_demux_eintX_Y.
+ */
+static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
+{
+        u32 status = __raw_readl(S5P64X0_EINT0PEND);
+        u32 mask = __raw_readl(S5P64X0_EINT0MASK);
+        unsigned int irq;
+
+        status &= ~mask;
+        status >>= start;
+        status &= (1 << (end - start + 1)) - 1;
+
+        for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
+                if (status & 1)
+                        generic_handle_irq(irq);
+                status >>= 1;
+        }
+}
+
+static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
+{
+        s5p64x0_irq_demux_eint(0, 3);
+}
+
+static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
+{
+        s5p64x0_irq_demux_eint(4, 11);
+}
+
+static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
+                                        struct irq_desc *desc)
+{
+        s5p64x0_irq_demux_eint(12, 15);
+}
+
+static int s5p64x0_alloc_gc(void)
+{
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+
+        gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
+                                    S5P_VA_GPIO, handle_level_irq);
+        if (!gc) {
+                printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
+                        "external interrupts failed\n", __func__);
+                return -EINVAL;
+        }
+
+        ct = gc->chip_types;
+        ct->chip.irq_ack = irq_gc_ack;
+        ct->chip.irq_mask = irq_gc_mask_set_bit;
+        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
+        ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
+        ct->regs.ack = EINT0PEND_OFFSET;
+        ct->regs.mask = EINT0MASK_OFFSET;
+        irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+        return 0;
+}
+
+static int __init s5p64x0_init_irq_eint(void)
+{
+        int ret = s5p64x0_alloc_gc();
+        irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
+        irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
+        irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
+
+        return ret;
+}
+arch_initcall(s5p64x0_init_irq_eint);
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 79bb3a0314ef..69dd87cd8e22 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -90,6 +90,7 @@ config MACH_GONI
         select S3C_DEV_HSMMC2
         select S3C_DEV_I2C1
         select S3C_DEV_I2C2
+        select S5P_DEV_MFC
         select S3C_DEV_USB_HSOTG
         select S5P_DEV_ONENAND
         select SAMSUNG_DEV_KEYPAD
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index ae72f87eab15..52a8e607bcc2 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -324,6 +324,12 @@ static struct clk init_clocks_off[] = {
                 .enable         = s5pv210_clk_ip0_ctrl,
                 .ctrlbit        = (1 << 26),
         }, {
+                .name           = "mfc",
+                .devname        = "s5p-mfc",
+                .parent         = &clk_pclk_psys.clk,
+                .enable         = s5pv210_clk_ip0_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
                 .name           = "otg",
                 .parent         = &clk_hclk_psys.clk,
                 .enable         = s5pv210_clk_ip1_ctrl,
@@ -879,6 +885,7 @@ static struct clksrc_clk clksrcs[] = {
         }, {
                 .clk            = {
                         .name           = "sclk_mfc",
+                        .devname        = "s5p-mfc",
                         .enable         = s5pv210_clk_ip0_ctrl,
                         .ctrlbit        = (1 << 16),
                 },
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 61e6c24b90ac..79907ec78d43 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -126,7 +126,7 @@ void __init s5pv210_map_io(void)
         s5pv210_default_sdhci2();
         s5pv210_default_sdhci3();
 
-        s3c_adc_setname("s3c64xx-adc");
+        s3c_adc_setname("samsung-adc-v3");
 
         s3c_cfcon_setname("s5pv210-pata");
 
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
index 8d58f1926241..63f5d82004b5 100644
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ b/arch/arm/mach-s5pv210/dev-audio.c
@@ -18,6 +18,7 @@
 #include <mach/map.h>
 #include <mach/dma.h>
 #include <mach/irqs.h>
+#include <mach/regs-audss.h>
 
 static const char *rclksrc[] = {
         [0] = "busclk",
@@ -52,6 +53,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
                         .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
                                          | QUIRK_NEED_RSTCLR,
                         .src_clk = rclksrc,
+                        .idma_addr = S5PV210_AUDSS_INT_MEM,
                 },
         },
 };
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 1dd58836fd4f..aac343c180b2 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -59,6 +59,8 @@
 
 #define S5PV210_PA_CFCON                0xE8200000
 
+#define S5PV210_PA_MFC                  0xF1700000
+
 #define S5PV210_PA_HSMMC(x)             (0xEB000000 + ((x) * 0x100000))
 
 #define S5PV210_PA_HSOTG                0xEC000000
@@ -107,6 +109,7 @@
 #define S5P_PA_FIMC1                    S5PV210_PA_FIMC1
 #define S5P_PA_FIMC2                    S5PV210_PA_FIMC2
 #define S5P_PA_MIPI_CSIS0               S5PV210_PA_MIPI_CSIS
+#define S5P_PA_MFC                      S5PV210_PA_MFC
 #define S5P_PA_ONENAND                  S5PC110_PA_ONENAND
 #define S5P_PA_ONENAND_DMA              S5PC110_PA_ONENAND_DMA
 #define S5P_PA_SDRAM                    S5PV210_PA_SDRAM
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
index e8d394f8b057..3e22109e1b7b 100644
--- a/arch/arm/mach-s5pv210/include/mach/pm-core.h
+++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h
@@ -41,3 +41,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
 {
         /* nothing here yet */
 }
+
+static inline void s3c_pm_restored_gpios(void) { }
+static inline void s3c_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-audss.h b/arch/arm/mach-s5pv210/include/mach/regs-audss.h
new file mode 100644
index 000000000000..eacc1f790807
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/regs-audss.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-s5pv210/include/mach/regs-audss.h
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ *              http://www.samsung.com
+ *
+ * S5PV210 Audio SubSystem clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_AUDSS_H
+#define __PLAT_REGS_AUDSS_H __FILE__
+
+#define S5PV210_AUDSS_INT_MEM   (0xC0000000)
+
+#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index e0c4d06b9db6..85c2d51a0956 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -46,6 +46,7 @@
 #include <plat/sdhci.h>
 #include <plat/clock.h>
 #include <plat/s5p-time.h>
+#include <plat/mfc.h>
 #include <plat/regs-fb-v4.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
@@ -808,6 +809,9 @@ static struct platform_device *goni_devices[] __initdata = {
         &goni_i2c_gpio5,
         &mmc2_fixed_voltage,
         &goni_device_gpiokeys,
+        &s5p_device_mfc,
+        &s5p_device_mfc_l,
+        &s5p_device_mfc_r,
         &s3c_device_i2c0,
         &s5p_device_fimc0,
         &s5p_device_fimc1,
@@ -841,6 +845,11 @@ static void __init goni_map_io(void)
         s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 }
 
+static void __init goni_reserve(void)
+{
+        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
 static void __init goni_machine_init(void)
 {
         /* Radio: call before I2C 1 registeration */
@@ -893,4 +902,5 @@ MACHINE_START(GONI, "GONI")
         .map_io         = goni_map_io,
         .init_machine   = goni_machine_init,
         .timer          = &s5p_timer,
+        .reserve        = &goni_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index ef20f922249d..5e011fc6720d 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -229,6 +229,7 @@ static struct platform_device *smdkv210_devices[] __initdata = {
         &s5pv210_device_iis0,
         &s5pv210_device_spdif,
         &samsung_asoc_dma,
+        &samsung_asoc_idma,
         &samsung_device_keypad,
         &smdkv210_dm9000,
         &smdkv210_lcd_lte480wv,
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 30e18bc60647..846cd7d69e3e 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -25,7 +25,6 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/i2c.h>
-#include <linux/i2c-tegra.h>
 
 #include <sound/wm8903.h>
 
@@ -83,22 +82,6 @@ static struct platform_device harmony_audio_device = {
         },
 };
 
-static struct tegra_i2c_platform_data harmony_i2c1_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-
-static struct tegra_i2c_platform_data harmony_i2c2_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-
-static struct tegra_i2c_platform_data harmony_i2c3_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-
-static struct tegra_i2c_platform_data harmony_dvc_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-
 static struct wm8903_platform_data harmony_wm8903_pdata = {
         .irq_active_low = 0,
         .micdet_cfg = 0,
@@ -121,11 +104,6 @@ static struct i2c_board_info __initdata wm8903_board_info = {
 
 static void __init harmony_i2c_init(void)
 {
-        tegra_i2c_device1.dev.platform_data = &harmony_i2c1_platform_data;
-        tegra_i2c_device2.dev.platform_data = &harmony_i2c2_platform_data;
-        tegra_i2c_device3.dev.platform_data = &harmony_i2c3_platform_data;
-        tegra_i2c_device4.dev.platform_data = &harmony_dvc_platform_data;
-
         platform_device_register(&tegra_i2c_device1);
         platform_device_register(&tegra_i2c_device2);
         platform_device_register(&tegra_i2c_device3);
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index 2643d1bd568b..bdd2627dd87b 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -141,12 +141,10 @@ static struct tegra_pingroup_config paz00_pinmux[] = {
 };
 
 static struct tegra_gpio_table gpio_table[] = {
-        { .gpio = TEGRA_GPIO_SD1_CD,    .enable = true  },
-        { .gpio = TEGRA_GPIO_SD1_WP,    .enable = true  },
-        { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true  },
-        { .gpio = TEGRA_GPIO_SD4_CD,    .enable = true  },
-        { .gpio = TEGRA_GPIO_SD4_WP,    .enable = true  },
-        { .gpio = TEGRA_GPIO_SD4_POWER, .enable = true  },
+        { .gpio = TEGRA_GPIO_SD1_CD,    .enable = true },
+        { .gpio = TEGRA_GPIO_SD1_WP,    .enable = true },
+        { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true },
+        { .gpio = TEGRA_ULPI_RST,       .enable = true },
 };
 
 void paz00_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 57e50a823eec..ea2f79c9879b 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -25,6 +25,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/pda_power.h>
 #include <linux/io.h>
+#include <linux/i2c.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -34,6 +35,7 @@
 #include <mach/iomap.h>
 #include <mach/irqs.h>
 #include <mach/sdhci.h>
+#include <mach/gpio.h>
 
 #include "board.h"
 #include "board-paz00.h"
@@ -66,10 +68,22 @@ static struct platform_device debug_uart = {
 static struct platform_device *paz00_devices[] __initdata = {
         &debug_uart,
         &tegra_sdhci_device1,
-        &tegra_sdhci_device2,
         &tegra_sdhci_device4,
 };
 
+static void paz00_i2c_init(void)
+{
+        platform_device_register(&tegra_i2c_device1);
+        platform_device_register(&tegra_i2c_device2);
+        platform_device_register(&tegra_i2c_device4);
+}
+
+static void paz00_usb_init(void)
+{
+        platform_device_register(&tegra_ehci2_device);
+        platform_device_register(&tegra_ehci3_device);
+}
+
 static void __init tegra_paz00_fixup(struct machine_desc *desc,
         struct tag *tags, char **cmdline, struct meminfo *mi)
 {
@@ -84,23 +98,16 @@ static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
         { NULL,         NULL,           0,              0},
 };
 
-
 static struct tegra_sdhci_platform_data sdhci_pdata1 = {
         .cd_gpio        = TEGRA_GPIO_SD1_CD,
         .wp_gpio        = TEGRA_GPIO_SD1_WP,
         .power_gpio     = TEGRA_GPIO_SD1_POWER,
 };
 
-static struct tegra_sdhci_platform_data sdhci_pdata2 = {
+static struct tegra_sdhci_platform_data sdhci_pdata4 = {
         .cd_gpio        = -1,
         .wp_gpio        = -1,
         .power_gpio     = -1,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
-        .cd_gpio        = TEGRA_GPIO_SD4_CD,
-        .wp_gpio        = TEGRA_GPIO_SD4_WP,
-        .power_gpio     = TEGRA_GPIO_SD4_POWER,
         .is_8bit        = 1,
 };
 
@@ -111,13 +118,15 @@ static void __init tegra_paz00_init(void)
         paz00_pinmux_init();
 
         tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
-        tegra_sdhci_device2.dev.platform_data = &sdhci_pdata2;
         tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
 
         platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices));
+
+        paz00_i2c_init();
+        paz00_usb_init();
 }
 
-MACHINE_START(PAZ00, "paz00")
+MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
         .boot_params    = 0x00000100,
         .fixup          = tegra_paz00_fixup,
         .map_io         = tegra_map_common_io,
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index da193ca76d3b..d4ff39ddaeb3 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -17,12 +17,10 @@
 #ifndef _MACH_TEGRA_BOARD_PAZ00_H
 #define _MACH_TEGRA_BOARD_PAZ00_H
 
-#define TEGRA_GPIO_SD1_CD               TEGRA_GPIO_PV5
-#define TEGRA_GPIO_SD1_WP               TEGRA_GPIO_PH1
-#define TEGRA_GPIO_SD1_POWER            TEGRA_GPIO_PT3
-#define TEGRA_GPIO_SD4_CD               TEGRA_GPIO_PH2
-#define TEGRA_GPIO_SD4_WP               TEGRA_GPIO_PH3
-#define TEGRA_GPIO_SD4_POWER            TEGRA_GPIO_PI6
+#define TEGRA_GPIO_SD1_CD               TEGRA_GPIO_PV5
+#define TEGRA_GPIO_SD1_WP               TEGRA_GPIO_PH1
+#define TEGRA_GPIO_SD1_POWER            TEGRA_GPIO_PT3
+#define TEGRA_ULPI_RST                  TEGRA_GPIO_PV0
 
 void paz00_pinmux_init(void);
 
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index 10fbbdc8699a..56cbabf6aa68 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -19,7 +19,6 @@
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 #include <linux/i2c.h>
-#include <linux/i2c-tegra.h>
 #include <linux/delay.h>
 #include <linux/input.h>
 #include <linux/io.h>
@@ -66,22 +65,6 @@ static __initdata struct tegra_clk_init_table seaboard_clk_init_table[] = {
         { NULL,         NULL,           0,              0},
 };
 
-static struct tegra_i2c_platform_data seaboard_i2c1_platform_data = {
-        .bus_clk_rate   = 400000.
-};
-
-static struct tegra_i2c_platform_data seaboard_i2c2_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-
-static struct tegra_i2c_platform_data seaboard_i2c3_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-
-static struct tegra_i2c_platform_data seaboard_dvc_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-
 static struct gpio_keys_button seaboard_gpio_keys_buttons[] = {
         {
                 .code           = SW_LID,
@@ -137,9 +120,9 @@ static struct tegra_sdhci_platform_data sdhci_pdata4 = {
 static struct platform_device *seaboard_devices[] __initdata = {
         &debug_uart,
         &tegra_pmu_device,
-        &tegra_sdhci_device1,
-        &tegra_sdhci_device3,
         &tegra_sdhci_device4,
+        &tegra_sdhci_device3,
+        &tegra_sdhci_device1,
         &seaboard_gpio_keys_device,
 };
 
@@ -161,11 +144,6 @@ static void __init seaboard_i2c_init(void)
 
         i2c_register_board_info(3, &adt7461_device, 1);
 
-        tegra_i2c_device1.dev.platform_data = &seaboard_i2c1_platform_data;
-        tegra_i2c_device2.dev.platform_data = &seaboard_i2c2_platform_data;
-        tegra_i2c_device3.dev.platform_data = &seaboard_i2c3_platform_data;
-        tegra_i2c_device4.dev.platform_data = &seaboard_dvc_platform_data;
-
         platform_device_register(&tegra_i2c_device1);
         platform_device_register(&tegra_i2c_device2);
         platform_device_register(&tegra_i2c_device3);
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index d9dc5d297edd..47c596cdbf32 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -29,7 +29,7 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
         {TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_OSC,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
@@ -126,7 +126,7 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
         {TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_UAD,   TEGRA_MUX_IRDA,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
@@ -145,6 +145,9 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
 static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */
         { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */
+
+        { .gpio = TRIMSLICE_GPIO_USB1_MODE, .enable = true }, /* USB1 mode */
+        { .gpio = TRIMSLICE_GPIO_USB2_RST,  .enable = true }, /* USB2 PHY rst */
 };
 
 void __init trimslice_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index cda4cfd78e84..89a6d2adc1de 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -23,6 +23,8 @@
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 #include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -30,6 +32,7 @@
 
 #include <mach/iomap.h>
 #include <mach/sdhci.h>
+#include <mach/gpio.h>
 
 #include "board.h"
 #include "clock.h"
@@ -71,12 +74,58 @@ static struct tegra_sdhci_platform_data sdhci_pdata4 = {
         .power_gpio     = -1,
 };
 
+static struct platform_device trimslice_audio_device = {
+        .name   = "tegra-snd-trimslice",
+        .id     = 0,
+};
+
 static struct platform_device *trimslice_devices[] __initdata = {
         &debug_uart,
         &tegra_sdhci_device1,
         &tegra_sdhci_device4,
+        &tegra_i2s_device1,
+        &tegra_das_device,
+        &tegra_pcm_device,
+        &trimslice_audio_device,
 };
 
+static struct i2c_board_info trimslice_i2c3_board_info[] = {
+        {
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        },
+        {
+                I2C_BOARD_INFO("em3027", 0x56),
+        },
+};
+
+static void trimslice_i2c_init(void)
+{
+        platform_device_register(&tegra_i2c_device1);
+        platform_device_register(&tegra_i2c_device2);
+        platform_device_register(&tegra_i2c_device3);
+
+        i2c_register_board_info(2, trimslice_i2c3_board_info,
+                                ARRAY_SIZE(trimslice_i2c3_board_info));
+}
+
+static void trimslice_usb_init(void)
+{
+        int err;
+
+        platform_device_register(&tegra_ehci3_device);
+
+        platform_device_register(&tegra_ehci2_device);
+
+        err = gpio_request_one(TRIMSLICE_GPIO_USB1_MODE, GPIOF_OUT_INIT_HIGH,
+                               "usb1mode");
+        if (err) {
+                pr_err("TrimSlice: failed to obtain USB1 mode gpio: %d\n", err);
+                return;
+        }
+
+        platform_device_register(&tegra_ehci1_device);
+}
+
 static void __init tegra_trimslice_fixup(struct machine_desc *desc,
         struct tag *tags, char **cmdline, struct meminfo *mi)
 {
@@ -90,6 +139,10 @@ static void __init tegra_trimslice_fixup(struct machine_desc *desc,
 static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = {
         /* name         parent          rate            enabled */
         { "uarta",      "pll_p",        216000000,      true },
+        { "pll_a",      "pll_p_out1",   56448000,       true },
+        { "pll_a_out0", "pll_a",        11289600,       true },
+        { "cdev1",      NULL,           0,              true },
+        { "i2s1",       "pll_a_out0",   11289600,       false},
         { NULL,         NULL,           0,              0},
 };
 
@@ -112,6 +165,9 @@ static void __init tegra_trimslice_init(void)
         tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
 
         platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices));
+
+        trimslice_i2c_init();
+        trimslice_usb_init();
 }
 
 MACHINE_START(TRIMSLICE, "trimslice")
diff --git a/arch/arm/mach-tegra/board-trimslice.h b/arch/arm/mach-tegra/board-trimslice.h
index e8ef6291c6f1..7a7dee86b4da 100644
--- a/arch/arm/mach-tegra/board-trimslice.h
+++ b/arch/arm/mach-tegra/board-trimslice.h
@@ -20,6 +20,9 @@
 #define TRIMSLICE_GPIO_SD4_CD   TEGRA_GPIO_PP1  /* mmc4 cd */
 #define TRIMSLICE_GPIO_SD4_WP   TEGRA_GPIO_PP2  /* mmc4 wp */
 
+#define TRIMSLICE_GPIO_USB1_MODE        TEGRA_GPIO_PV2 /* USB1 mode */
+#define TRIMSLICE_GPIO_USB2_RST         TEGRA_GPIO_PV0 /* USB2 PHY reset */
+
 void trimslice_pinmux_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 1528f9daef1f..57e35d20c24c 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -22,10 +22,14 @@
 #include <linux/dma-mapping.h>
 #include <linux/fsl_devices.h>
 #include <linux/serial_8250.h>
+#include <linux/i2c-tegra.h>
+#include <linux/platform_data/tegra_usb.h>
 #include <asm/pmu.h>
 #include <mach/irqs.h>
 #include <mach/iomap.h>
 #include <mach/dma.h>
+#include <mach/usb_phy.h>
+#include "gpio-names.h"
 
 static struct resource i2c_resource1[] = {
         [0] = {
@@ -79,13 +83,29 @@ static struct resource i2c_resource4[] = {
         },
 };
 
+static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
+        .bus_clk_rate   = 400000,
+};
+
+static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
+        .bus_clk_rate   = 400000,
+};
+
+static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
+        .bus_clk_rate   = 400000,
+};
+
+static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
+        .bus_clk_rate   = 400000,
+};
+
 struct platform_device tegra_i2c_device1 = {
         .name           = "tegra-i2c",
         .id             = 0,
         .resource       = i2c_resource1,
         .num_resources  = ARRAY_SIZE(i2c_resource1),
         .dev = {
-                .platform_data = 0,
+                .platform_data = &tegra_i2c1_platform_data,
         },
 };
 
@@ -95,7 +115,7 @@ struct platform_device tegra_i2c_device2 = {
         .resource       = i2c_resource2,
         .num_resources  = ARRAY_SIZE(i2c_resource2),
         .dev = {
-                .platform_data = 0,
+                .platform_data = &tegra_i2c2_platform_data,
         },
 };
 
@@ -105,7 +125,7 @@ struct platform_device tegra_i2c_device3 = {
         .resource       = i2c_resource3,
         .num_resources  = ARRAY_SIZE(i2c_resource3),
         .dev = {
-                .platform_data = 0,
+                .platform_data = &tegra_i2c3_platform_data,
         },
 };
 
@@ -115,7 +135,7 @@ struct platform_device tegra_i2c_device4 = {
         .resource       = i2c_resource4,
         .num_resources  = ARRAY_SIZE(i2c_resource4),
         .dev = {
-                .platform_data = 0,
+                .platform_data = &tegra_dvc_platform_data,
         },
 };
 
@@ -334,6 +354,28 @@ static struct resource tegra_usb3_resources[] = {
         },
 };
 
+static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
+        /* All existing boards use GPIO PV0 for phy reset */
+        .reset_gpio = TEGRA_GPIO_PV0,
+        .clk = "cdev2",
+};
+
+static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
+        .operating_mode = TEGRA_USB_OTG,
+        .power_down_on_bus_suspend = 1,
+};
+
+static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
+        .phy_config = &tegra_ehci2_ulpi_phy_config,
+        .operating_mode = TEGRA_USB_HOST,
+        .power_down_on_bus_suspend = 1,
+};
+
+static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
+        .operating_mode = TEGRA_USB_HOST,
+        .power_down_on_bus_suspend = 1,
+};
+
 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
 
 struct platform_device tegra_ehci1_device = {
@@ -342,6 +384,7 @@ struct platform_device tegra_ehci1_device = {
         .dev    = {
                 .dma_mask       = &tegra_ehci_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &tegra_ehci1_pdata,
         },
         .resource = tegra_usb1_resources,
         .num_resources = ARRAY_SIZE(tegra_usb1_resources),
@@ -353,6 +396,7 @@ struct platform_device tegra_ehci2_device = {
         .dev    = {
                 .dma_mask       = &tegra_ehci_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &tegra_ehci2_pdata,
         },
         .resource = tegra_usb2_resources,
         .num_resources = ARRAY_SIZE(tegra_usb2_resources),
@@ -364,6 +408,7 @@ struct platform_device tegra_ehci3_device = {
         .dev    = {
                 .dma_mask       = &tegra_ehci_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &tegra_ehci3_pdata,
         },
         .resource = tegra_usb3_resources,
         .num_resources = ARRAY_SIZE(tegra_usb3_resources),
diff --git a/arch/arm/mach-tegra/include/mach/barriers.h b/arch/arm/mach-tegra/include/mach/barriers.h
deleted file mode 100644
index 425b42e91ef6..000000000000
--- a/arch/arm/mach-tegra/include/mach/barriers.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * arch/arm/mach-realview/include/mach/barriers.h
- *
- * Copyright (C) 2010 ARM Ltd.
- * Written by Catalin Marinas <catalin.marinas@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __MACH_BARRIERS_H
-#define __MACH_BARRIERS_H
-
-#include <asm/outercache.h>
-
-#define rmb()           dsb()
-#define wmb()           do { dsb(); outer_sync(); } while (0)
-#define mb()            wmb()
-
-#endif  /* __MACH_BARRIERS_H */
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 32ca6267b9ff..0886cbccddee 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -121,7 +121,7 @@ void __init smp_init_cpus(void)
         }
 
         for (i = 0; i < ncores; i++)
-                cpu_set(i, cpu_possible_map);
+                set_cpu_possible(i, true);
 
         set_smp_cross_call(gic_raise_softirq);
 }
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index bb618075fab6..0fe9b3ee2947 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -2182,8 +2182,8 @@ struct clk tegra_list_clks[] = {
         PERIPH_CLK("tvo",       "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
         PERIPH_CLK("hdmi",      "hdmi",                 NULL,   51,     0x18c,  600000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
         PERIPH_CLK("tvdac",     "tvdac",                NULL,   53,     0x194,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("disp1",     "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("disp2",     "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* scales with voltage and process_id */
+        PERIPH_CLK("disp1",     "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_plld_pllc_clkm,     MUX), /* scales with voltage and process_id */
+        PERIPH_CLK("disp2",     "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_plld_pllc_clkm,     MUX), /* scales with voltage and process_id */
         PERIPH_CLK("usbd",      "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
         PERIPH_CLK("usb2",      "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
         PERIPH_CLK("usb3",      "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index 5767208f1c1d..7b597e2b19e2 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -40,8 +40,8 @@ struct pl022_config_chip dummy_chip_info = {
         .hierarchy = SSP_MASTER,
         /* 0 = drive TX even as slave, 1 = do not drive TX as slave */
         .slave_tx_disable = 0,
-        .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
-        .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
+        .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
+        .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
         .ctrl_len = SSP_BITS_12,
         .wait_state = SSP_MWIRE_WAIT_ZERO,
         .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 18d7fa0603c2..5f51bdeef0ef 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -27,9 +27,6 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
-/* Be able to sleep for atleast 4 seconds (usually more) */
-#define APPTIMER_MIN_RANGE 4
-
 /*
  * APP side special timer registers
  * This timer contains four timers which can fire an interrupt each.
@@ -309,11 +306,11 @@ static int u300_set_next_event(unsigned long cycles,
 
 /* Use general purpose timer 1 as clock event */
 static struct clock_event_device clockevent_u300_1mhz = {
-        .name           = "GPT1",
-        .rating         = 300, /* Reasonably fast and accurate clock event */
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .set_next_event = u300_set_next_event,
-        .set_mode       = u300_set_mode,
+        .name           = "GPT1",
+        .rating         = 300, /* Reasonably fast and accurate clock event */
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .set_next_event = u300_set_next_event,
+        .set_mode       = u300_set_mode,
 };
 
 /* Clock event timer interrupt handler */
@@ -328,9 +325,9 @@ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
 }
 
 static struct irqaction u300_timer_irq = {
-        .name           = "U300 Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = u300_timer_interrupt,
+        .name           = "U300 Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = u300_timer_interrupt,
 };
 
 /*
@@ -413,16 +410,10 @@ static void __init u300_timer_init(void)
                         "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
                 pr_err("timer: failed to initialize U300 clock source\n");
 
-        clockevents_calc_mult_shift(&clockevent_u300_1mhz,
-                                    rate, APPTIMER_MIN_RANGE);
-        /* 32bit counter, so 32bits delta is max */
-        clockevent_u300_1mhz.max_delta_ns =
-                clockevent_delta2ns(0xffffffff, &clockevent_u300_1mhz);
-        /* This timer is slow enough to set for 1 cycle == 1 MHz */
-        clockevent_u300_1mhz.min_delta_ns =
-                clockevent_delta2ns(1, &clockevent_u300_1mhz);
-        clockevent_u300_1mhz.cpumask = cpumask_of(0);
-        clockevents_register_device(&clockevent_u300_1mhz);
+        /* Configure and register the clockevent */
+        clockevents_config_and_register(&clockevent_u300_1mhz, rate,
+                                        1, 0xffffffff);
+
         /*
          * TODO: init and register the rest of the timers too, they can be
          * used by hrtimers!
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index f8b9392ee347..4210cb434dbc 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -20,7 +20,7 @@ config UX500_SOC_DB8500
 
 endmenu
 
-menu "Ux500 target platform"
+menu "Ux500 target platform (boards)"
 
 config MACH_U8500
         bool "U8500 Development platform"
@@ -29,6 +29,19 @@ config MACH_U8500
         help
           Include support for the mop500 development platform.
 
+config MACH_HREFV60
+       bool "U85000 Development platform, HREFv60 version"
+       depends on UX500_SOC_DB8500
+       help
+         Include support for the HREFv60 new development platform.
+
+config MACH_SNOWBALL
+        bool "U8500 Snowball platform"
+        depends on UX500_SOC_DB8500
+        select MACH_U8500
+        help
+          Include support for the snowball development platform.
+
 config MACH_U5500
         bool "U5500 Development platform"
         depends on UX500_SOC_DB5500
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 70cdbd60596a..f26fd76f72b4 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -236,6 +236,46 @@ static pin_cfg_t mop500_pins_hrefv60[] = {
 
 };
 
+static pin_cfg_t snowball_pins[] = {
+        /* SSP0, to AB8500 */
+        GPIO143_SSP0_CLK,
+        GPIO144_SSP0_FRM,
+        GPIO145_SSP0_RXD        | PIN_PULL_DOWN,
+        GPIO146_SSP0_TXD,
+
+        /* MMC0: MicroSD card */
+        GPIO21_MC0_DAT31DIR     | PIN_OUTPUT_HIGH,
+
+        /* MMC2: LAN */
+        GPIO86_SM_ADQ0,
+        GPIO87_SM_ADQ1,
+        GPIO88_SM_ADQ2,
+        GPIO89_SM_ADQ3,
+        GPIO90_SM_ADQ4,
+        GPIO91_SM_ADQ5,
+        GPIO92_SM_ADQ6,
+        GPIO93_SM_ADQ7,
+
+        GPIO94_SM_ADVn,
+        GPIO95_SM_CS0n,
+        GPIO96_SM_OEn,
+        GPIO97_SM_WEn,
+
+        GPIO128_SM_CKO,
+        GPIO130_SM_FBCLK,
+        GPIO131_SM_ADQ8,
+        GPIO132_SM_ADQ9,
+        GPIO133_SM_ADQ10,
+        GPIO134_SM_ADQ11,
+        GPIO135_SM_ADQ12,
+        GPIO136_SM_ADQ13,
+        GPIO137_SM_ADQ14,
+        GPIO138_SM_ADQ15,
+
+        /* RSTn_LAN */
+        GPIO141_GPIO            | PIN_OUTPUT_HIGH,
+};
+
 void __init mop500_pins_init(void)
 {
         nmk_config_pins(mop500_pins_common,
@@ -243,6 +283,9 @@ void __init mop500_pins_init(void)
         if (machine_is_hrefv60())
                 nmk_config_pins(mop500_pins_hrefv60,
                                 ARRAY_SIZE(mop500_pins_hrefv60));
+        else if (machine_is_snowball())
+                nmk_config_pins(snowball_pins,
+                                ARRAY_SIZE(snowball_pins));
         else
                 nmk_config_pins(mop500_pins_default,
                                 ARRAY_SIZE(mop500_pins_default));
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 0f2e522f387d..2735d03996cf 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -272,7 +272,14 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .max_uV = 2900000,
                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
                                           REGULATOR_CHANGE_STATUS,
-                        .boot_on = 1, /* must be on for display */
+                        .boot_on = 1, /* display is on at boot */
+                        /*
+                         * This voltage cannot be disabled right now because
+                         * it is somehow affecting the external MMC
+                         * functionality, though that typically will use
+                         * AUX3.
+                         */
+                        .always_on = 1,
                 },
                 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers),
                 .consumer_supplies = ab8500_vaux1_consumers,
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 7c6cb4fa47a9..d0cb9e5eb87c 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -32,13 +32,32 @@
 #define MCI_DATA31DIREN         (1 << 5)
 #define MCI_FBCLKEN             (1 << 7)
 
+/* GPIO pins used by the sdi0 level shifter */
+static int sdi0_en = -1;
+static int sdi0_vsel = -1;
+
 static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
                                    unsigned char power_mode)
 {
-        if (power_mode == MMC_POWER_UP)
-                gpio_set_value_cansleep(GPIO_SDMMC_EN, 1);
-        else if (power_mode == MMC_POWER_OFF)
-                gpio_set_value_cansleep(GPIO_SDMMC_EN, 0);
+        switch (power_mode) {
+        case MMC_POWER_UP:
+        case MMC_POWER_ON:
+                /*
+                 * Level shifter voltage should depend on vdd to when deciding
+                 * on either 1.8V or 2.9V. Once the decision has been made the
+                 * level shifter must be disabled and re-enabled with a changed
+                 * select signal in order to switch the voltage. Since there is
+                 * no framework support yet for indicating 1.8V in vdd, use the
+                 * default 2.9V.
+                 */
+                gpio_direction_output(sdi0_vsel, 0);
+                gpio_direction_output(sdi0_en, 1);
+                break;
+        case MMC_POWER_OFF:
+                gpio_direction_output(sdi0_vsel, 0);
+                gpio_direction_output(sdi0_en, 0);
+                break;
+        }
 
         return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN |
                MCI_DATA2DIREN | MCI_DATA31DIREN;
@@ -67,8 +86,10 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
 static struct mmci_platform_data mop500_sdi0_data = {
         .vdd_handler    = mop500_sdi0_vdd_handler,
         .ocr_mask       = MMC_VDD_29_30,
-        .f_max          = 100000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA,
+        .f_max          = 50000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_SD_HIGHSPEED |
+                                MMC_CAP_MMC_HIGHSPEED,
         .gpio_wp        = -1,
 #ifdef CONFIG_STE_DMA40
         .dma_filter     = stedma40_filter,
@@ -77,10 +98,6 @@ static struct mmci_platform_data mop500_sdi0_data = {
 #endif
 };
 
-/* GPIO pins used by the sdi0 level shifter */
-static int sdi0_en = -1;
-static int sdi0_vsel = -1;
-
 static void sdi0_configure(void)
 {
         int ret;
@@ -140,7 +157,7 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
 
 static struct mmci_platform_data mop500_sdi2_data = {
         .ocr_mask       = MMC_VDD_165_195,
-        .f_max          = 100000000,
+        .f_max          = 50000000,
         .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
         .gpio_cd        = -1,
         .gpio_wp        = -1,
@@ -177,7 +194,7 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
 
 static struct mmci_platform_data mop500_sdi4_data = {
         .ocr_mask       = MMC_VDD_29_30,
-        .f_max          = 100000000,
+        .f_max          = 50000000,
         .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
                           MMC_CAP_MMC_HIGHSPEED,
         .gpio_cd        = -1,
@@ -199,17 +216,27 @@ void __init mop500_sdi_init(void)
         /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
         if (!cpu_is_u8500v10())
                 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
-        db8500_add_sdi2(&mop500_sdi2_data, periphid);
+        /* sdi2 on snowball is in ATL_B mode for FSMC (LAN) */
+        if (!machine_is_snowball())
+                db8500_add_sdi2(&mop500_sdi2_data, periphid);
 
         /* On-board eMMC */
         db8500_add_sdi4(&mop500_sdi4_data, periphid);
 
-        if (machine_is_hrefv60()) {
-                mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
-                sdi0_en = HREFV60_SDMMC_EN_GPIO;
-                sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
+        if (machine_is_hrefv60() || machine_is_snowball()) {
+                if (machine_is_hrefv60()) {
+                        mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
+                        sdi0_en = HREFV60_SDMMC_EN_GPIO;
+                        sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
+                } else if (machine_is_snowball()) {
+                        mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
+                        mop500_sdi0_data.cd_invert = true;
+                        sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
+                        sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
+                }
                 sdi0_configure();
         }
+
         /*
          * On boards with the TC35892 GPIO expander, sdi0 will finally
          * be added when the TC35892 initializes and calls
diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c
index 69cce41f602a..5af36aa56c08 100644
--- a/arch/arm/mach-ux500/board-mop500-uib.c
+++ b/arch/arm/mach-ux500/board-mop500-uib.c
@@ -25,7 +25,7 @@ struct uib {
         void (*init)(void);
 };
 
-static struct __initdata uib mop500_uibs[] = {
+static struct uib __initdata mop500_uibs[] = {
         [STUIB] = {
                 .name   = "ST-UIB",
                 .option = "stuib",
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 2a08c07dec6d..cd54abaccd96 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -26,9 +26,11 @@
 #include <linux/mfd/ab8500/gpio.h>
 #include <linux/leds-lp5521.h>
 #include <linux/input.h>
+#include <linux/smsc911x.h>
 #include <linux/gpio_keys.h>
 #include <linux/delay.h>
 
+#include <linux/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
@@ -47,6 +49,26 @@
 #include "board-mop500.h"
 #include "board-mop500-regulators.h"
 
+static struct gpio_led snowball_led_array[] = {
+        {
+                .name = "user_led",
+                .default_trigger = "none",
+                .gpio = 142,
+        },
+};
+
+static struct gpio_led_platform_data snowball_led_data = {
+        .leds = snowball_led_array,
+        .num_leds = ARRAY_SIZE(snowball_led_array),
+};
+
+static struct platform_device snowball_led_dev = {
+        .name = "leds-gpio",
+        .dev = {
+                .platform_data = &snowball_led_data,
+        },
+};
+
 static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
         .gpio_base              = MOP500_AB8500_GPIO(0),
         .irq_base               = MOP500_AB8500_VIR_GPIO_IRQ_BASE,
@@ -69,6 +91,97 @@ static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
                                         0x7A, 0x00, 0x00},
 };
 
+static struct gpio_keys_button snowball_key_array[] = {
+        {
+                .gpio           = 32,
+                .type           = EV_KEY,
+                .code           = KEY_1,
+                .desc           = "userpb",
+                .active_low     = 1,
+                .debounce_interval = 50,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = 151,
+                .type           = EV_KEY,
+                .code           = KEY_2,
+                .desc           = "extkb1",
+                .active_low     = 1,
+                .debounce_interval = 50,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = 152,
+                .type           = EV_KEY,
+                .code           = KEY_3,
+                .desc           = "extkb2",
+                .active_low     = 1,
+                .debounce_interval = 50,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = 161,
+                .type           = EV_KEY,
+                .code           = KEY_4,
+                .desc           = "extkb3",
+                .active_low     = 1,
+                .debounce_interval = 50,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = 162,
+                .type           = EV_KEY,
+                .code           = KEY_5,
+                .desc           = "extkb4",
+                .active_low     = 1,
+                .debounce_interval = 50,
+                .wakeup         = 1,
+        },
+};
+
+static struct gpio_keys_platform_data snowball_key_data = {
+        .buttons        = snowball_key_array,
+        .nbuttons       = ARRAY_SIZE(snowball_key_array),
+};
+
+static struct platform_device snowball_key_dev = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &snowball_key_data,
+        }
+};
+
+static struct smsc911x_platform_config snowball_sbnet_cfg = {
+        .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+        .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+        .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+        .shift = 1,
+};
+
+static struct resource sbnet_res[] = {
+        {
+                .name = "smsc911x-memory",
+                .start = (0x5000 << 16),
+                .end  =  (0x5000 << 16) + 0xffff,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = NOMADIK_GPIO_TO_IRQ(140),
+                .end = NOMADIK_GPIO_TO_IRQ(140),
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        },
+};
+
+static struct platform_device snowball_sbnet_dev = {
+        .name           = "smsc911x",
+        .num_resources  = ARRAY_SIZE(sbnet_res),
+        .resource       = sbnet_res,
+        .dev            = {
+                .platform_data = &snowball_sbnet_cfg,
+        },
+};
+
 static struct ab8500_platform_data ab8500_platdata = {
         .irq_base       = MOP500_AB8500_IRQ_BASE,
         .regulator_reg_init = ab8500_regulator_reg_init,
@@ -295,8 +408,9 @@ static void mop500_prox_deactivate(struct device *dev)
 }
 
 /* add any platform devices here - TODO */
-static struct platform_device *platform_devs[] __initdata = {
+static struct platform_device *mop500_platform_devs[] __initdata = {
         &mop500_gpio_keys_device,
+        &ab8500_device,
 };
 
 #ifdef CONFIG_STE_DMA40
@@ -478,6 +592,13 @@ static void __init mop500_uart_init(void)
         db8500_add_uart2(&uart2_plat);
 }
 
+static struct platform_device *snowball_platform_devs[] __initdata = {
+        &snowball_led_dev,
+        &snowball_key_dev,
+        &snowball_sbnet_dev,
+        &ab8500_device,
+};
+
 static void __init mop500_init_machine(void)
 {
         int i2c0_devs;
@@ -487,24 +608,29 @@ static void __init mop500_init_machine(void)
          * all these GPIO pins to the internal GPIO controller
          * instead.
          */
-        if (machine_is_hrefv60())
-                mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
-        else
-                mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
+        if (!machine_is_snowball()) {
+                if (machine_is_hrefv60())
+                        mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
+                else
+                        mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
+        }
 
         u8500_init_devices();
 
         mop500_pins_init();
 
-        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
+        if (machine_is_snowball())
+                platform_add_devices(snowball_platform_devs,
+                                        ARRAY_SIZE(snowball_platform_devs));
+        else
+                platform_add_devices(mop500_platform_devs,
+                                        ARRAY_SIZE(mop500_platform_devs));
 
         mop500_i2c_init();
         mop500_sdi_init();
         mop500_spi_init();
         mop500_uart_init();
 
-        platform_device_register(&ab8500_device);
-
         i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
         if (machine_is_hrefv60())
                 i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
@@ -512,6 +638,9 @@ static void __init mop500_init_machine(void)
         i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
         i2c_register_board_info(2, mop500_i2c2_devices,
                                 ARRAY_SIZE(mop500_i2c2_devices));
+
+        /* This board has full regulator constraints */
+        regulator_has_full_constraints();
 }
 
 MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
@@ -531,3 +660,12 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
         .timer          = &ux500_timer,
         .init_machine   = mop500_init_machine,
 MACHINE_END
+
+MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
+        .boot_params    = 0x100,
+        .map_io         = u8500_map_io,
+        .init_irq       = ux500_init_irq,
+        /* we re-use nomadik timer here */
+        .timer          = &ux500_timer,
+        .init_machine   = mop500_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 03a31cc9b084..ee77a8970c33 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -7,6 +7,11 @@
 #ifndef __BOARD_MOP500_H
 #define __BOARD_MOP500_H
 
+/* snowball GPIO for MMC card */
+#define SNOWBALL_SDMMC_EN_GPIO 217
+#define SNOWBALL_SDMMC_1V8_3V_GPIO 228
+#define SNOWBALL_SDMMC_CD_GPIO 218
+
 /* HREFv60-specific GPIO assignments, this board has no GPIO expander */
 #define HREFV60_TOUCH_RST_GPIO          143
 #define HREFV60_PROX_SENSE_GPIO         217
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 7d107be63eb4..e832664d1bd9 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -14,6 +14,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/clkdev.h>
+#include <linux/cpufreq.h>
 
 #include <plat/mtu.h>
 #include <mach/hardware.h>
@@ -742,6 +743,51 @@ err_out:
 late_initcall(clk_debugfs_init);
 #endif /* defined(CONFIG_DEBUG_FS) */
 
+unsigned long clk_smp_twd_rate = 400000000;
+
+unsigned long clk_smp_twd_get_rate(struct clk *clk)
+{
+        return clk_smp_twd_rate;
+}
+
+static struct clk clk_smp_twd = {
+        .get_rate = clk_smp_twd_get_rate,
+        .name =  "smp_twd",
+};
+
+static struct clk_lookup clk_smp_twd_lookup = {
+        .dev_id = "smp_twd",
+        .clk = &clk_smp_twd,
+};
+
+#ifdef CONFIG_CPU_FREQ
+
+static int clk_twd_cpufreq_transition(struct notifier_block *nb,
+                                      unsigned long state, void *data)
+{
+        struct cpufreq_freqs *f = data;
+
+        if (state == CPUFREQ_PRECHANGE) {
+                /* Save frequency in simple Hz */
+                clk_smp_twd_rate = f->new * 1000;
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block clk_twd_cpufreq_nb = {
+        .notifier_call = clk_twd_cpufreq_transition,
+};
+
+static int clk_init_smp_twd_cpufreq(void)
+{
+        return cpufreq_register_notifier(&clk_twd_cpufreq_nb,
+                                  CPUFREQ_TRANSITION_NOTIFIER);
+}
+late_initcall(clk_init_smp_twd_cpufreq);
+
+#endif
+
 int __init clk_init(void)
 {
         if (cpu_is_u8500ed()) {
@@ -762,6 +808,8 @@ int __init clk_init(void)
         else
                 clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
 
+        clkdev_add(&clk_smp_twd_lookup);
+
 #ifdef CONFIG_DEBUG_FS
         clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
         if (cpu_is_u8500ed())
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index c01bc19e3c5e..22705d246fc7 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -44,6 +44,7 @@ static struct map_desc u5500_io_desc[] __initdata = {
         __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K),
         __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K),
         __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K),
+        __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K),
 };
 
 static struct resource db5500_pmu_resources[] = {
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 088b550c40df..7dd08074c37b 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -54,7 +54,8 @@ static inline void arch_decomp_setup(void)
         if (machine_is_u8500() ||
             machine_is_svp8500v1() ||
             machine_is_svp8500v2() ||
-            machine_is_hrefv60())
+            machine_is_hrefv60()   ||
+            machine_is_snowball())
                 ux500_uart_base = U8500_UART2_BASE;
         else if (machine_is_u5500())
                 ux500_uart_base = U5500_UART0_BASE;
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 82e535953fd9..0a01cbdfe063 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -6,6 +6,7 @@
  */
 #include <linux/platform_device.h>
 #include <linux/usb/musb.h>
+#include <linux/dma-mapping.h>
 #include <plat/ste_dma40.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index a0ea5848d40d..88633fe01a5d 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -822,7 +822,7 @@ config CACHE_L2X0
                    REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
                    ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
                    ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
-                   ARCH_PRIMA2 || ARCH_ZYNQ
+                   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX
         default y
         select OUTER_CACHE
         select OUTER_CACHE_SYNC
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index fb166b20f60f..0d6ed31bdbf2 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -95,8 +95,22 @@ struct device mxc_aips_bus = {
         .parent         = &platform_bus,
 };
 
+struct device mxc_ahb_bus = {
+        .init_name      = "mxc_ahb",
+        .parent         = &platform_bus,
+};
+
 static int __init mxc_device_init(void)
 {
-        return device_register(&mxc_aips_bus);
+        int ret;
+
+        ret = device_register(&mxc_aips_bus);
+        if (IS_ERR_VALUE(ret))
+                goto done;
+
+        ret = device_register(&mxc_ahb_bus);
+
+done:
+        return ret;
 }
 core_initcall(mxc_device_init);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
index c64f015e031b..2b0fdb23beb8 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-dma.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
@@ -6,207 +6,29 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
-#include <linux/compiler.h>
-#include <linux/err.h>
-#include <linux/init.h>
-
-#include <mach/hardware.h>
 #include <mach/devices-common.h>
-#include <mach/sdma.h>
-
-struct imx_imx_sdma_data {
-        resource_size_t iobase;
-        resource_size_t irq;
-        struct sdma_platform_data pdata;
-};
-
-#define imx_imx_sdma_data_entry_single(soc, _sdma_version, _cpu_name, _to_version)\
-        {                                                               \
-                .iobase = soc ## _SDMA ## _BASE_ADDR,                   \
-                .irq = soc ## _INT_SDMA,                                \
-                .pdata = {                                              \
-                        .sdma_version = _sdma_version,                  \
-                        .cpu_name = _cpu_name,                          \
-                        .to_version = _to_version,                      \
-                },                                                      \
-        }
-
-#ifdef CONFIG_SOC_IMX25
-struct imx_imx_sdma_data imx25_imx_sdma_data __initconst =
-        imx_imx_sdma_data_entry_single(MX25, 2, "imx25", 1);
-#endif /* ifdef CONFIG_SOC_IMX25 */
 
-#ifdef CONFIG_SOC_IMX31
-struct imx_imx_sdma_data imx31_imx_sdma_data __initdata =
-        imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 1);
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-struct imx_imx_sdma_data imx35_imx_sdma_data __initdata =
-        imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 1);
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-#ifdef CONFIG_SOC_IMX51
-struct imx_imx_sdma_data imx51_imx_sdma_data __initconst =
-        imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 1);
-#endif /* ifdef CONFIG_SOC_IMX51 */
+struct platform_device __init __maybe_unused *imx_add_imx_dma(void)
+{
+        return platform_device_register_resndata(&mxc_ahb_bus,
+                        "imx-dma", -1, NULL, 0, NULL, 0);
+}
 
-static struct platform_device __init __maybe_unused *imx_add_imx_sdma(
-                const struct imx_imx_sdma_data *data)
+struct platform_device __init __maybe_unused *imx_add_imx_sdma(
+        resource_size_t iobase, int irq, struct sdma_platform_data *pdata)
 {
         struct resource res[] = {
                 {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_16K - 1,
+                        .start = iobase,
+                        .end = iobase + SZ_16K - 1,
                         .flags = IORESOURCE_MEM,
                 }, {
-                        .start = data->irq,
-                        .end = data->irq,
+                        .start = irq,
+                        .end = irq,
                         .flags = IORESOURCE_IRQ,
                 },
         };
 
-        return imx_add_platform_device("imx-sdma", -1,
-                        res, ARRAY_SIZE(res),
-                        &data->pdata, sizeof(data->pdata));
-}
-
-static struct platform_device __init __maybe_unused *imx_add_imx_dma(void)
-{
-        return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0);
-}
-
-#ifdef CONFIG_ARCH_MX25
-static struct sdma_script_start_addrs addr_imx25 = {
-        .ap_2_ap_addr = 729,
-        .uart_2_mcu_addr = 904,
-        .per_2_app_addr = 1255,
-        .mcu_2_app_addr = 834,
-        .uartsh_2_mcu_addr = 1120,
-        .per_2_shp_addr = 1329,
-        .mcu_2_shp_addr = 1048,
-        .ata_2_mcu_addr = 1560,
-        .mcu_2_ata_addr = 1479,
-        .app_2_per_addr = 1189,
-        .app_2_mcu_addr = 770,
-        .shp_2_per_addr = 1407,
-        .shp_2_mcu_addr = 979,
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX31
-static struct sdma_script_start_addrs addr_imx31_to1 = {
-        .per_2_per_addr = 1677,
-};
-
-static struct sdma_script_start_addrs addr_imx31_to2 = {
-        .ap_2_ap_addr = 423,
-        .ap_2_bp_addr = 829,
-        .bp_2_ap_addr = 1029,
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX35
-static struct sdma_script_start_addrs addr_imx35_to1 = {
-        .ap_2_ap_addr = 642,
-        .uart_2_mcu_addr = 817,
-        .mcu_2_app_addr = 747,
-        .uartsh_2_mcu_addr = 1183,
-        .per_2_shp_addr = 1033,
-        .mcu_2_shp_addr = 961,
-        .ata_2_mcu_addr = 1333,
-        .mcu_2_ata_addr = 1252,
-        .app_2_mcu_addr = 683,
-        .shp_2_per_addr = 1111,
-        .shp_2_mcu_addr = 892,
-};
-
-static struct sdma_script_start_addrs addr_imx35_to2 = {
-        .ap_2_ap_addr = 729,
-        .uart_2_mcu_addr = 904,
-        .per_2_app_addr = 1597,
-        .mcu_2_app_addr = 834,
-        .uartsh_2_mcu_addr = 1270,
-        .per_2_shp_addr = 1120,
-        .mcu_2_shp_addr = 1048,
-        .ata_2_mcu_addr = 1429,
-        .mcu_2_ata_addr = 1339,
-        .app_2_per_addr = 1531,
-        .app_2_mcu_addr = 770,
-        .shp_2_per_addr = 1198,
-        .shp_2_mcu_addr = 979,
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX51
-static struct sdma_script_start_addrs addr_imx51 = {
-        .ap_2_ap_addr = 642,
-        .uart_2_mcu_addr = 817,
-        .mcu_2_app_addr = 747,
-        .mcu_2_shp_addr = 961,
-        .ata_2_mcu_addr = 1473,
-        .mcu_2_ata_addr = 1392,
-        .app_2_per_addr = 1033,
-        .app_2_mcu_addr = 683,
-        .shp_2_per_addr = 1251,
-        .shp_2_mcu_addr = 892,
-};
-#endif
-
-static int __init imxXX_add_imx_dma(void)
-{
-        struct platform_device *ret;
-
-#if defined(CONFIG_SOC_IMX21) || defined(CONFIG_SOC_IMX27)
-        if (cpu_is_mx21() || cpu_is_mx27())
-                ret = imx_add_imx_dma();
-        else
-#endif
-
-#if defined(CONFIG_SOC_IMX25)
-        if (cpu_is_mx25()) {
-                imx25_imx_sdma_data.pdata.script_addrs = &addr_imx25;
-                ret = imx_add_imx_sdma(&imx25_imx_sdma_data);
-        } else
-#endif
-
-#if defined(CONFIG_SOC_IMX31)
-        if (cpu_is_mx31()) {
-                int to_version = mx31_revision() >> 4;
-                imx31_imx_sdma_data.pdata.to_version = to_version;
-                if (to_version == 1)
-                        imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to1;
-                else
-                        imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to2;
-                ret = imx_add_imx_sdma(&imx31_imx_sdma_data);
-        } else
-#endif
-
-#if defined(CONFIG_SOC_IMX35)
-        if (cpu_is_mx35()) {
-                int to_version = mx35_revision() >> 4;
-                imx35_imx_sdma_data.pdata.to_version = to_version;
-                if (to_version == 1)
-                        imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to1;
-                else
-                        imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to2;
-                ret = imx_add_imx_sdma(&imx35_imx_sdma_data);
-        } else
-#endif
-
-#if defined(CONFIG_SOC_IMX51)
-        if (cpu_is_mx51()) {
-                int to_version = mx51_revision() >> 4;
-                imx51_imx_sdma_data.pdata.to_version = to_version;
-                imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51;
-                ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
-        } else
-#endif
-                ret = ERR_PTR(-ENODEV);
-
-        if (IS_ERR(ret))
-                return PTR_ERR(ret);
-
-        return 0;
+        return platform_device_register_resndata(&mxc_ahb_bus, "imx-sdma",
+                        -1, res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
 }
-arch_initcall(imxXX_add_imx_dma);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index 2ab74f0da9a6..afe60f7244a8 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -94,8 +94,9 @@ const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst = {
         imx_imx_i2c_data_entry(MX53, _id, _hwid, SZ_4K)
         imx53_imx_i2c_data_entry(0, 1),
         imx53_imx_i2c_data_entry(1, 2),
+        imx53_imx_i2c_data_entry(2, 3),
 };
-#endif /* ifdef CONFIG_SOC_IMX51 */
+#endif /* ifdef CONFIG_SOC_IMX53 */
 
 struct platform_device *__init imx_add_imx_i2c(
                 const struct imx_imx_i2c_data *data,
diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
index 26366114b021..479c3e9f771f 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-keypad.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
@@ -46,6 +46,11 @@ const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst =
         imx_imx_keypad_data_entry_single(MX51, SZ_16);
 #endif /* ifdef CONFIG_SOC_IMX51 */
 
+#ifdef CONFIG_SOC_IMX53
+const struct imx_imx_keypad_data imx53_imx_keypad_data __initconst =
+        imx_imx_keypad_data_entry_single(MX53, SZ_16);
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
 struct platform_device *__init imx_add_imx_keypad(
                 const struct imx_imx_keypad_data *data,
                 const struct matrix_keymap_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
index 66b8593e9b69..21c6f30e1017 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
@@ -76,6 +76,16 @@ const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX51 */
 
+#ifdef CONFIG_SOC_IMX53
+const struct imx_imx_ssi_data imx53_imx_ssi_data[] __initconst = {
+#define imx53_imx_ssi_data_entry(_id, _hwid)                            \
+        imx_imx_ssi_data_entry(MX53, _id, _hwid, SZ_16K)
+        imx53_imx_ssi_data_entry(0, 1),
+        imx53_imx_ssi_data_entry(1, 2),
+        imx53_imx_ssi_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
 struct platform_device *__init imx_add_imx_ssi(
                 const struct imx_imx_ssi_data *data,
                 const struct imx_ssi_platform_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
index 3c854c2cc6dd..cfce8c918b73 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-uart.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -123,6 +123,8 @@ const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = {
         imx53_imx_uart_data_entry(0, 1),
         imx53_imx_uart_data_entry(1, 2),
         imx53_imx_uart_data_entry(2, 3),
+        imx53_imx_uart_data_entry(3, 4),
+        imx53_imx_uart_data_entry(4, 5),
 };
 #endif /* ifdef CONFIG_SOC_IMX53 */
 
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 03f626645374..bf93820ab61c 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -9,8 +9,10 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/init.h>
+#include <mach/sdma.h>
 
 extern struct device mxc_aips_bus;
+extern struct device mxc_ahb_bus;
 
 struct platform_device *imx_add_platform_device_dmamask(
                 const char *name, int id,
@@ -293,3 +295,7 @@ struct imx_spi_imx_data {
 struct platform_device *__init imx_add_spi_imx(
                 const struct imx_spi_imx_data *data,
                 const struct spi_imx_master *pdata);
+
+struct platform_device *imx_add_imx_dma(void);
+struct platform_device *imx_add_imx_sdma(
+        resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index 74cd093203e0..5e3c3236ebf3 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -176,10 +176,10 @@
 /*
  * DMA request assignments
  */
-#define MX53_DMA_REQ_SSI3_TX1           47
-#define MX53_DMA_REQ_SSI3_RX1           46
-#define MX53_DMA_REQ_SSI3_TX2           45
-#define MX53_DMA_REQ_SSI3_RX2           44
+#define MX53_DMA_REQ_SSI3_TX0           47
+#define MX53_DMA_REQ_SSI3_RX0           46
+#define MX53_DMA_REQ_SSI3_TX1           45
+#define MX53_DMA_REQ_SSI3_RX1           44
 #define MX53_DMA_REQ_UART3_TX   43
 #define MX53_DMA_REQ_UART3_RX   42
 #define MX53_DMA_REQ_ESAI_TX            41
@@ -194,14 +194,14 @@
 #define MX53_DMA_REQ_ASRC_DMA1  32
 #define MX53_DMA_REQ_EMI_WR             31
 #define MX53_DMA_REQ_EMI_RD             30
-#define MX53_DMA_REQ_SSI1_TX1           29
-#define MX53_DMA_REQ_SSI1_RX1           28
-#define MX53_DMA_REQ_SSI1_TX2           27
-#define MX53_DMA_REQ_SSI1_RX2           26
-#define MX53_DMA_REQ_SSI2_TX1           25
-#define MX53_DMA_REQ_SSI2_RX1           24
-#define MX53_DMA_REQ_SSI2_TX2           23
-#define MX53_DMA_REQ_SSI2_RX2           22
+#define MX53_DMA_REQ_SSI1_TX0           29
+#define MX53_DMA_REQ_SSI1_RX0           28
+#define MX53_DMA_REQ_SSI1_TX1           27
+#define MX53_DMA_REQ_SSI1_RX1           26
+#define MX53_DMA_REQ_SSI2_TX0           25
+#define MX53_DMA_REQ_SSI2_RX0           24
+#define MX53_DMA_REQ_SSI2_TX1           23
+#define MX53_DMA_REQ_SSI2_RX1           22
 #define MX53_DMA_REQ_I2C2_SDHC2 21
 #define MX53_DMA_REQ_I2C1_SDHC1 20
 #define MX53_DMA_REQ_UART1_TX   19
@@ -241,7 +241,7 @@
 #define MX53_INT_IPU_ERR        10
 #define MX53_INT_IPU_SYN        11
 #define MX53_INT_GPU    12
-#define MX53_INT_RESV13 13
+#define MX53_INT_UART4  13
 #define MX53_INT_USB_H1 14
 #define MX53_INT_EMI    15
 #define MX53_INT_USB_H2 16
@@ -314,7 +314,7 @@
 #define MX53_INT_CAN2   83
 #define MX53_INT_GPU2_IRQ       84
 #define MX53_INT_GPU2_BUSY      85
-#define MX53_INT_RESV86 86
+#define MX53_INT_UART5  86
 #define MX53_INT_FEC    87
 #define MX53_INT_OWIRE  88
 #define MX53_INT_CTI1_TG2       89
diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h
index 913e0432e40e..f495c87c113f 100644
--- a/arch/arm/plat-mxc/include/mach/sdma.h
+++ b/arch/arm/plat-mxc/include/mach/sdma.h
@@ -49,14 +49,12 @@ struct sdma_script_start_addrs {
  * struct sdma_platform_data - platform specific data for SDMA engine
  *
  * @sdma_version        The version of this SDMA engine
- * @cpu_name            used to generate the firmware name
- * @to_version          CPU Tape out version
+ * @fw_name             The firmware name
  * @script_addrs        SDMA scripts addresses in SDMA ROM
  */
 struct sdma_platform_data {
         int sdma_version;
-        char *cpu_name;
-        int to_version;
+        char *fw_name;
         struct sdma_script_start_addrs *script_addrs;
 };
 
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index d85e2d1c0324..88fd40452567 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -117,6 +117,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
         case MACH_TYPE_MX53_EVK:
         case MACH_TYPE_MX53_LOCO:
         case MACH_TYPE_MX53_SMD:
+        case MACH_TYPE_MX53_ARD:
                 uart_base = MX53_UART1_BASE_ADDR;
                 break;
         default:
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c
index e1c6eff7258a..96953e2e4f11 100644
--- a/arch/arm/plat-mxc/irq-common.c
+++ b/arch/arm/plat-mxc/irq-common.c
@@ -42,17 +42,16 @@ EXPORT_SYMBOL(imx_irq_set_priority);
 
 int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
 {
-        struct mxc_irq_chip *chip;
-        struct irq_chip *base;
+        struct irq_chip_generic *gc;
+        int (*set_irq_fiq)(unsigned int, unsigned int);
         int ret;
 
         ret = -ENOSYS;
 
-        base = irq_get_chip(irq);
-        if (base) {
-                chip = container_of(base, struct mxc_irq_chip, base);
-                if (chip->set_irq_fiq)
-                        ret = chip->set_irq_fiq(irq, type);
+        gc = irq_get_chip_data(irq);
+        if (gc && gc->private) {
+                set_irq_fiq = gc->private;
+                ret = set_irq_fiq(irq, type);
         }
 
         return ret;
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 710f2e7da4ce..f257fccdc394 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -68,78 +68,34 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
 
         return 0;
 }
+#else
+#define tzic_set_irq_fiq NULL
 #endif
 
-/**
- * tzic_mask_irq() - Disable interrupt source "d" in the TZIC
- *
- * @param  d            interrupt source
- */
-static void tzic_mask_irq(struct irq_data *d)
-{
-        int index, off;
-
-        index = d->irq >> 5;
-        off = d->irq & 0x1F;
-        __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
-}
-
-/**
- * tzic_unmask_irq() - Enable interrupt source "d" in the TZIC
- *
- * @param  d            interrupt source
- */
-static void tzic_unmask_irq(struct irq_data *d)
-{
-        int index, off;
-
-        index = d->irq >> 5;
-        off = d->irq & 0x1F;
-        __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
-}
-
-static unsigned int wakeup_intr[4];
+static unsigned int *wakeup_intr[4];
 
-/**
- * tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source.
- *
- * @param  d            interrupt source
- * @param  enable       enable as wake-up if equal to non-zero
- *                      disble as wake-up if equal to zero
- *
- * @return       This function returns 0 on success.
- */
-static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable)
+static __init void tzic_init_gc(unsigned int irq_start)
 {
-        unsigned int index, off;
-
-        index = d->irq >> 5;
-        off = d->irq & 0x1F;
-
-        if (index > 3)
-                return -EINVAL;
-
-        if (enable)
-                wakeup_intr[index] |= (1 << off);
-        else
-                wakeup_intr[index] &= ~(1 << off);
-
-        return 0;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+        int idx = irq_start >> 5;
+
+        gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
+                                    handle_level_irq);
+        gc->private = tzic_set_irq_fiq;
+        gc->wake_enabled = IRQ_MSK(32);
+        wakeup_intr[idx] = &gc->wake_active;
+
+        ct = gc->chip_types;
+        ct->chip.irq_mask = irq_gc_mask_disable_reg;
+        ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+        ct->chip.irq_set_wake = irq_gc_set_wake;
+        ct->regs.disable = TZIC_ENCLEAR0(idx);
+        ct->regs.enable = TZIC_ENSET0(idx);
+
+        irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 }
 
-static struct mxc_irq_chip mxc_tzic_chip = {
-        .base = {
-                .name = "MXC_TZIC",
-                .irq_ack = tzic_mask_irq,
-                .irq_mask = tzic_mask_irq,
-                .irq_unmask = tzic_unmask_irq,
-                .irq_set_wake = tzic_set_wake_irq,
-        },
-#ifdef CONFIG_FIQ
-        .set_irq_fiq = tzic_set_irq_fiq,
-#endif
-};
-
 /*
  * This function initializes the TZIC hardware and disables all the
  * interrupts. It registers the interrupt enable and disable functions
@@ -168,11 +124,8 @@ void __init tzic_init_irq(void __iomem *irqbase)
 
         /* all IRQ no FIQ Warning :: No selection */
 
-        for (i = 0; i < TZIC_NUM_IRQS; i++) {
-                irq_set_chip_and_handler(i, &mxc_tzic_chip.base,
-                                         handle_level_irq);
-                set_irq_flags(i, IRQF_VALID);
-        }
+        for (i = 0; i < TZIC_NUM_IRQS; i += 32)
+                tzic_init_gc(i);
 
 #ifdef CONFIG_FIQ
         /* Initialize FIQ */
@@ -199,7 +152,7 @@ int tzic_enable_wake(int is_idle)
 
         for (i = 0; i < 4; i++) {
                 v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
-                        wakeup_intr[i];
+                        *wakeup_intr[i];
                 __raw_writel(v, tzic_base + TZIC_WAKEUP0(i));
         }
 
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index e98f5c5c7879..9843c954c042 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -39,6 +39,7 @@ config S5P_GPIO_INT
 
 config S5P_HRT
         bool
+        select SAMSUNG_DEV_PWM
         help
           Use the High Resolution timer support
 
@@ -70,6 +71,16 @@ config S5P_DEV_FIMC3
         help
           Compile in platform device definitions for FIMC controller 3
 
+config S5P_DEV_FIMD0
+        bool
+        help
+          Compile in platform device definitions for FIMD controller 0
+
+config S5P_DEV_MFC
+        bool
+        help
+          Compile in platform device definitions for MFC
+
 config S5P_DEV_ONENAND
         bool
         help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index e234cc4d49a0..4b53e04eeca4 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -25,11 +25,12 @@ obj-$(CONFIG_PM)		+= irq-pm.o
 obj-$(CONFIG_S5P_HRT)           += s5p-time.o
 
 # devices
-
+obj-$(CONFIG_S5P_DEV_MFC)       += dev-mfc.o
 obj-$(CONFIG_S5P_DEV_FIMC0)     += dev-fimc0.o
 obj-$(CONFIG_S5P_DEV_FIMC1)     += dev-fimc1.o
 obj-$(CONFIG_S5P_DEV_FIMC2)     += dev-fimc2.o
 obj-$(CONFIG_S5P_DEV_FIMC3)     += dev-fimc3.o
+obj-$(CONFIG_S5P_DEV_FIMD0)     += dev-fimd0.o
 obj-$(CONFIG_S5P_DEV_ONENAND)   += dev-onenand.o
 obj-$(CONFIG_S5P_DEV_CSIS0)     += dev-csis0.o
 obj-$(CONFIG_S5P_DEV_CSIS1)     += dev-csis1.o
diff --git a/arch/arm/plat-s5p/dev-fimd0.c b/arch/arm/plat-s5p/dev-fimd0.c
new file mode 100644
index 000000000000..f728bb5abcef
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-fimd0.c
@@ -0,0 +1,67 @@
+/* linux/arch/arm/plat-s5p/dev-fimd0.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Core file for Samsung Display Controller (FIMD) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/fb.h>
+#include <linux/gfp.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/fb.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s5p_fimd0_resource[] = {
+        [0] = {
+                .start  = S5P_PA_FIMD0,
+                .end    = S5P_PA_FIMD0 + SZ_32K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_FIMD0_VSYNC,
+                .end    = IRQ_FIMD0_VSYNC,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_FIMD0_FIFO,
+                .end    = IRQ_FIMD0_FIFO,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_FIMD0_SYSTEM,
+                .end    = IRQ_FIMD0_SYSTEM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 fimd0_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5p_device_fimd0 = {
+        .name           = "s5p-fb",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p_fimd0_resource),
+        .resource       = s5p_fimd0_resource,
+        .dev            = {
+                .dma_mask               = &fimd0_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
+{
+        s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
+                        &s5p_device_fimd0);
+}
diff --git a/arch/arm/plat-s5p/dev-mfc.c b/arch/arm/plat-s5p/dev-mfc.c
new file mode 100644
index 000000000000..94226a0010f7
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-mfc.c
@@ -0,0 +1,123 @@
+/* linux/arch/arm/plat-s5p/dev-mfc.c
+ *
+ * Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
+ *
+ * Base S5P MFC resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/memblock.h>
+#include <linux/ioport.h>
+
+#include <mach/map.h>
+#include <plat/devs.h>
+#include <plat/irqs.h>
+#include <plat/mfc.h>
+
+static struct resource s5p_mfc_resource[] = {
+        [0] = {
+                .start  = S5P_PA_MFC,
+                .end    = S5P_PA_MFC + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_MFC,
+                .end    = IRQ_MFC,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device s5p_device_mfc = {
+        .name           = "s5p-mfc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p_mfc_resource),
+        .resource       = s5p_mfc_resource,
+};
+
+/*
+ * MFC hardware has 2 memory interfaces which are modelled as two separate
+ * platform devices to let dma-mapping distinguish between them.
+ *
+ * MFC parent device (s5p_device_mfc) must be registered before memory
+ * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
+ */
+
+static u64 s5p_mfc_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device s5p_device_mfc_l = {
+        .name           = "s5p-mfc-l",
+        .id             = -1,
+        .dev            = {
+                .parent                 = &s5p_device_mfc.dev,
+                .dma_mask               = &s5p_mfc_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+struct platform_device s5p_device_mfc_r = {
+        .name           = "s5p-mfc-r",
+        .id             = -1,
+        .dev            = {
+                .parent                 = &s5p_device_mfc.dev,
+                .dma_mask               = &s5p_mfc_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+struct s5p_mfc_reserved_mem {
+        phys_addr_t     base;
+        unsigned long   size;
+        struct device   *dev;
+};
+
+static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
+
+void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
+                                phys_addr_t lbase, unsigned int lsize)
+{
+        int i;
+
+        s5p_mfc_mem[0].dev = &s5p_device_mfc_r.dev;
+        s5p_mfc_mem[0].base = rbase;
+        s5p_mfc_mem[0].size = rsize;
+
+        s5p_mfc_mem[1].dev = &s5p_device_mfc_l.dev;
+        s5p_mfc_mem[1].base = lbase;
+        s5p_mfc_mem[1].size = lsize;
+
+        for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
+                struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
+                if (memblock_remove(area->base, area->size)) {
+                        printk(KERN_ERR "Failed to reserve memory for MFC device (%ld bytes at 0x%08lx)\n",
+                               area->size, (unsigned long) area->base);
+                        area->base = 0;
+                }
+        }
+}
+
+static int __init s5p_mfc_memory_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
+                struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
+                if (!area->base)
+                        continue;
+
+                if (dma_declare_coherent_memory(area->dev, area->base,
+                                area->base, area->size,
+                                DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0)
+                        printk(KERN_ERR "Failed to declare coherent memory for MFC device (%ld bytes at 0x%08lx)\n",
+                               area->size, (unsigned long) area->base);
+        }
+        return 0;
+}
+device_initcall(s5p_mfc_memory_init);
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index d973d39666a3..36d3551173b2 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -35,9 +35,10 @@
 #define S5P_VA_COREPERI_BASE    S3C_ADDR(0x02800000)
 #define S5P_VA_COREPERI(x)      (S5P_VA_COREPERI_BASE + (x))
 #define S5P_VA_SCU              S5P_VA_COREPERI(0x0)
-#define S5P_VA_GIC_CPU          S5P_VA_COREPERI(0x100)
 #define S5P_VA_TWD              S5P_VA_COREPERI(0x600)
-#define S5P_VA_GIC_DIST         S5P_VA_COREPERI(0x1000)
+
+#define S5P_VA_GIC_CPU          S3C_ADDR(0x02810000)
+#define S5P_VA_GIC_DIST         S3C_ADDR(0x02820000)
 
 #define S3C_VA_USB_HSPHY        S3C_ADDR(0x02900000)
 
diff --git a/arch/arm/plat-s5p/include/plat/mfc.h b/arch/arm/plat-s5p/include/plat/mfc.h
new file mode 100644
index 000000000000..6697f8cb2949
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/mfc.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __PLAT_S5P_MFC_H
+#define __PLAT_S5P_MFC_H
+
+/**
+ * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
+ * @rbase:      base address for MFC 'right' memory interface
+ * @rsize:      size of the memory reserved for MFC 'right' interface
+ * @lbase:      base address for MFC 'left' memory interface
+ * @lsize:      size of the memory reserved for MFC 'left' interface
+ *
+ * This function reserves system memory for both MFC device memory
+ * interfaces and registers it to respective struct device entries as
+ * coherent memory.
+ */
+void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
+                                phys_addr_t lbase, unsigned int lsize);
+
+#endif /* __PLAT_S5P_MFC_H */
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index e8f2be2d67f2..ee8deef19481 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -21,6 +21,7 @@
 #include <linux/clk.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/regulator/consumer.h>
 
 #include <plat/regs-adc.h>
 #include <plat/adc.h>
@@ -39,8 +40,9 @@
  */
 
 enum s3c_cpu_type {
-        TYPE_S3C24XX,
-        TYPE_S3C64XX
+        TYPE_ADCV1, /* S3C24XX */
+        TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
+        TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
 };
 
 struct s3c_adc_client {
@@ -71,6 +73,7 @@ struct adc_device {
         unsigned int             prescale;
 
         int                      irq;
+        struct regulator        *vdd;
 };
 
 static struct adc_device *adc_dev;
@@ -91,6 +94,7 @@ static inline void s3c_adc_select(struct adc_device *adc,
                                   struct s3c_adc_client *client)
 {
         unsigned con = readl(adc->regs + S3C2410_ADCCON);
+        enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
 
         client->select_cb(client, 1);
 
@@ -98,8 +102,12 @@ static inline void s3c_adc_select(struct adc_device *adc,
         con &= ~S3C2410_ADCCON_STDBM;
         con &= ~S3C2410_ADCCON_STARTMASK;
 
-        if (!client->is_ts)
-                con |= S3C2410_ADCCON_SELMUX(client->channel);
+        if (!client->is_ts) {
+                if (cpu == TYPE_ADCV3)
+                        writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
+                else
+                        con |= S3C2410_ADCCON_SELMUX(client->channel);
+        }
 
         writel(con, adc->regs + S3C2410_ADCCON);
 }
@@ -285,8 +293,8 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
 
         client->nr_samples--;
 
-        if (cpu == TYPE_S3C64XX) {
-                /* S3C64XX ADC resolution is 12-bit */
+        if (cpu != TYPE_ADCV1) {
+                /* S3C64XX/S5P ADC resolution is 12-bit */
                 data0 &= 0xfff;
                 data1 &= 0xfff;
         } else {
@@ -312,7 +320,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
         }
 
 exit:
-        if (cpu == TYPE_S3C64XX) {
+        if (cpu != TYPE_ADCV1) {
                 /* Clear ADC interrupt */
                 writel(0, adc->regs + S3C64XX_ADCCLRINT);
         }
@@ -338,17 +346,24 @@ static int s3c_adc_probe(struct platform_device *pdev)
         adc->pdev = pdev;
         adc->prescale = S3C2410_ADCCON_PRSCVL(49);
 
+        adc->vdd = regulator_get(dev, "vdd");
+        if (IS_ERR(adc->vdd)) {
+                dev_err(dev, "operating without regulator \"vdd\" .\n");
+                ret = PTR_ERR(adc->vdd);
+                goto err_alloc;
+        }
+
         adc->irq = platform_get_irq(pdev, 1);
         if (adc->irq <= 0) {
                 dev_err(dev, "failed to get adc irq\n");
                 ret = -ENOENT;
-                goto err_alloc;
+                goto err_reg;
         }
 
         ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc);
         if (ret < 0) {
                 dev_err(dev, "failed to attach adc irq\n");
-                goto err_alloc;
+                goto err_reg;
         }
 
         adc->clk = clk_get(dev, "adc");
@@ -372,10 +387,14 @@ static int s3c_adc_probe(struct platform_device *pdev)
                 goto err_clk;
         }
 
+        ret = regulator_enable(adc->vdd);
+        if (ret)
+                goto err_ioremap;
+
         clk_enable(adc->clk);
 
         tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
-        if (platform_get_device_id(pdev)->driver_data == TYPE_S3C64XX) {
+        if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1) {
                 /* Enable 12-bit ADC resolution */
                 tmp |= S3C64XX_ADCCON_RESSEL;
         }
@@ -388,12 +407,15 @@ static int s3c_adc_probe(struct platform_device *pdev)
 
         return 0;
 
+ err_ioremap:
+        iounmap(adc->regs);
  err_clk:
         clk_put(adc->clk);
 
  err_irq:
         free_irq(adc->irq, adc);
-
+ err_reg:
+        regulator_put(adc->vdd);
  err_alloc:
         kfree(adc);
         return ret;
@@ -406,6 +428,8 @@ static int __devexit s3c_adc_remove(struct platform_device *pdev)
         iounmap(adc->regs);
         free_irq(adc->irq, adc);
         clk_disable(adc->clk);
+        regulator_disable(adc->vdd);
+        regulator_put(adc->vdd);
         clk_put(adc->clk);
         kfree(adc);
 
@@ -413,8 +437,10 @@ static int __devexit s3c_adc_remove(struct platform_device *pdev)
 }
 
 #ifdef CONFIG_PM
-static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
+static int s3c_adc_suspend(struct device *dev)
 {
+        struct platform_device *pdev = container_of(dev,
+                        struct platform_device, dev);
         struct adc_device *adc = platform_get_drvdata(pdev);
         unsigned long flags;
         u32 con;
@@ -428,19 +454,30 @@ static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
         disable_irq(adc->irq);
         spin_unlock_irqrestore(&adc->lock, flags);
         clk_disable(adc->clk);
+        regulator_disable(adc->vdd);
 
         return 0;
 }
 
-static int s3c_adc_resume(struct platform_device *pdev)
+static int s3c_adc_resume(struct device *dev)
 {
+        struct platform_device *pdev = container_of(dev,
+                        struct platform_device, dev);
         struct adc_device *adc = platform_get_drvdata(pdev);
+        int ret;
+        unsigned long tmp;
 
+        ret = regulator_enable(adc->vdd);
+        if (ret)
+                return ret;
         clk_enable(adc->clk);
         enable_irq(adc->irq);
 
-        writel(adc->prescale | S3C2410_ADCCON_PRSCEN,
-               adc->regs + S3C2410_ADCCON);
+        tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
+        /* Enable 12-bit ADC resolution */
+        if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1)
+                tmp |= S3C64XX_ADCCON_RESSEL;
+        writel(tmp, adc->regs + S3C2410_ADCCON);
 
         return 0;
 }
@@ -453,25 +490,32 @@ static int s3c_adc_resume(struct platform_device *pdev)
 static struct platform_device_id s3c_adc_driver_ids[] = {
         {
                 .name           = "s3c24xx-adc",
-                .driver_data    = TYPE_S3C24XX,
+                .driver_data    = TYPE_ADCV1,
         }, {
                 .name           = "s3c64xx-adc",
-                .driver_data    = TYPE_S3C64XX,
+                .driver_data    = TYPE_ADCV2,
+        }, {
+                .name           = "samsung-adc-v3",
+                .driver_data    = TYPE_ADCV3,
         },
         { }
 };
 MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids);
 
+static const struct dev_pm_ops adc_pm_ops = {
+        .suspend        = s3c_adc_suspend,
+        .resume         = s3c_adc_resume,
+};
+
 static struct platform_driver s3c_adc_driver = {
         .id_table       = s3c_adc_driver_ids,
         .driver         = {
                 .name   = "s3c-adc",
                 .owner  = THIS_MODULE,
+                .pm     = &adc_pm_ops,
         },
         .probe          = s3c_adc_probe,
         .remove         = __devexit_p(s3c_adc_remove),
-        .suspend        = s3c_adc_suspend,
-        .resume         = s3c_adc_resume,
 };
 
 static int __init adc_init(void)
@@ -485,4 +529,4 @@ static int __init adc_init(void)
         return ret;
 }
 
-arch_initcall(adc_init);
+module_init(adc_init);
diff --git a/arch/arm/plat-samsung/dev-asocdma.c b/arch/arm/plat-samsung/dev-asocdma.c
index a068c4f42d56..97e35d3c064d 100644
--- a/arch/arm/plat-samsung/dev-asocdma.c
+++ b/arch/arm/plat-samsung/dev-asocdma.c
@@ -23,3 +23,13 @@ struct platform_device samsung_asoc_dma = {
         }
 };
 EXPORT_SYMBOL(samsung_asoc_dma);
+
+struct platform_device samsung_asoc_idma = {
+        .name           = "samsung-idma",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &audio_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        }
+};
+EXPORT_SYMBOL(samsung_asoc_idma);
diff --git a/arch/arm/plat-samsung/include/plat/audio.h b/arch/arm/plat-samsung/include/plat/audio.h
index a0826ed2f9fe..aa9875f77c40 100644
--- a/arch/arm/plat-samsung/include/plat/audio.h
+++ b/arch/arm/plat-samsung/include/plat/audio.h
@@ -44,6 +44,7 @@ struct samsung_i2s {
          * Also corresponds to clocks of I2SMOD[10]
          */
         const char **src_clk;
+        dma_addr_t idma_addr;
 };
 
 /**
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index e3b31c26ac3e..24ebb1e1de41 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -40,6 +40,7 @@ extern struct platform_device s3c64xx_device_spi0;
 extern struct platform_device s3c64xx_device_spi1;
 
 extern struct platform_device samsung_asoc_dma;
+extern struct platform_device samsung_asoc_idma;
 
 extern struct platform_device s3c64xx_device_pcm0;
 extern struct platform_device s3c64xx_device_pcm1;
@@ -49,6 +50,7 @@ extern struct platform_device s3c64xx_device_ac97;
 extern struct platform_device s3c_device_ts;
 
 extern struct platform_device s3c_device_fb;
+extern struct platform_device s5p_device_fimd0;
 extern struct platform_device s3c_device_ohci;
 extern struct platform_device s3c_device_lcd;
 extern struct platform_device s3c_device_wdt;
@@ -112,6 +114,7 @@ extern struct platform_device exynos4_device_i2s2;
 extern struct platform_device exynos4_device_spdif;
 extern struct platform_device exynos4_device_pd[];
 extern struct platform_device exynos4_device_ahci;
+extern struct platform_device exynos4_device_dwmci;
 
 extern struct platform_device s5p6440_device_pcm;
 extern struct platform_device s5p6440_device_iis;
@@ -136,6 +139,9 @@ extern struct platform_device s5p_device_fimc1;
 extern struct platform_device s5p_device_fimc2;
 extern struct platform_device s5p_device_fimc3;
 
+extern struct platform_device s5p_device_mfc;
+extern struct platform_device s5p_device_mfc_l;
+extern struct platform_device s5p_device_mfc_r;
 extern struct platform_device s5p_device_mipi_csis0;
 extern struct platform_device s5p_device_mipi_csis1;
 
diff --git a/arch/arm/plat-samsung/include/plat/fb-core.h b/arch/arm/plat-samsung/include/plat/fb-core.h
index bca383efcf6d..6abcbf139cee 100644
--- a/arch/arm/plat-samsung/include/plat/fb-core.h
+++ b/arch/arm/plat-samsung/include/plat/fb-core.h
@@ -26,4 +26,19 @@ static inline void s3c_fb_setname(char *name)
 #endif
 }
 
+/* Re-define device name depending on support. */
+static inline void s5p_fb_setname(int id, char *name)
+{
+        switch (id) {
+#ifdef CONFIG_S5P_DEV_FIMD0
+        case 0:
+                s5p_device_fimd0.name = name;
+        break;
+#endif
+        default:
+                printk(KERN_ERR "%s: invalid device id(%d)\n", __func__, id);
+        break;
+        }
+}
+
 #endif /* __ASM_PLAT_FB_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index cb3ca3adc685..01f10e4d00c7 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -74,6 +74,14 @@ struct s3c_fb_platdata {
 extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
 
 /**
+ * s5p_fimd0_set_platdata() - Setup the FB device with platform data.
+ * @pd: The platform data to set. The data is copied from the passed structure
+ *      so the machine data can mark the data __initdata so that any unused
+ *      machines will end up dumping their data at runtime.
+ */
+extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
+
+/**
  * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
  *
  * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
@@ -94,4 +102,11 @@ extern void s5pc100_fb_gpio_setup_24bpp(void);
  */
 extern void s5pv210_fb_gpio_setup_24bpp(void);
 
+/**
+ * exynos4_fimd0_gpio_setup_24bpp() - Exynos4 setup function for 24bpp LCD0
+ *
+ * Initialise the GPIO for an 24bpp LCD display on the RGB interface 0.
+ */
+extern void exynos4_fimd0_gpio_setup_24bpp(void);
+
 #endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h
index 7554c4fcddb9..035e8c38d69c 100644
--- a/arch/arm/plat-samsung/include/plat/regs-adc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-adc.h
@@ -21,6 +21,7 @@
 #define S3C2410_ADCDAT1    S3C2410_ADCREG(0x10)
 #define S3C64XX_ADCUPDN         S3C2410_ADCREG(0x14)
 #define S3C64XX_ADCCLRINT       S3C2410_ADCREG(0x18)
+#define S5P_ADCMUX              S3C2410_ADCREG(0x1C)
 #define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
 
 
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
index 657405c481d0..3014c7226bd1 100644
--- a/arch/arm/plat-samsung/irq-uart.c
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -19,6 +19,8 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 
+#include <asm/mach/irq.h>
+
 #include <mach/map.h>
 #include <plat/irq-uart.h>
 #include <plat/regs-serial.h>
@@ -30,9 +32,12 @@
 static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
 {
         struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
+        struct irq_chip *chip = irq_get_chip(irq);
         u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
         int base = uirq->base_irq;
 
+        chained_irq_enter(chip, desc);
+
         if (pend & (1 << 0))
                 generic_handle_irq(base);
         if (pend & (1 << 1))
@@ -41,6 +46,8 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
                 generic_handle_irq(base + 2);
         if (pend & (1 << 3))
                 generic_handle_irq(base + 3);
+
+        chained_irq_exit(chip, desc);
 }
 
 static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 5fa1742d019b..ae6f99834cdd 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -269,6 +269,7 @@ static int s3c_pm_enter(suspend_state_t state)
         /* save all necessary core registers not covered by the drivers */
 
         s3c_pm_save_gpios();
+        s3c_pm_saved_gpios();
         s3c_pm_save_uarts();
         s3c_pm_save_core();
 
@@ -306,6 +307,7 @@ static int s3c_pm_enter(suspend_state_t state)
         s3c_pm_restore_core();
         s3c_pm_restore_uarts();
         s3c_pm_restore_gpios();
+        s3c_pm_restored_gpios();
 
         s3c_pm_debug_init();