423 files changed, 9321 insertions, 25136 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 70505d8f85c5..8ac460a8f4ca 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -345,22 +345,12 @@ config ARCH_BCM2835
           This enables support for the Broadcom BCM2835 SoC. This SoC is
           use in the Raspberry Pi, and Roku 2 devices.
 
-config ARCH_BCMRING
-        bool "Broadcom BCMRING"
-        depends on MMU
-        select CPU_V6
-        select ARM_AMBA
-        select ARM_TIMER_SP804
-        select CLKDEV_LOOKUP
-        select GENERIC_CLOCKEVENTS
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        help
-          Support for Broadcom's BCMRing platform.
-
 config ARCH_CLPS711X
         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
         select CPU_ARM720T
         select ARCH_USES_GETTIMEOFFSET
+        select COMMON_CLK
+        select CLKDEV_LOOKUP
         select NEED_MACH_MEMORY_H
         help
           Support for Cirrus Logic 711x/721x/731x based boards.
@@ -458,7 +448,9 @@ config ARCH_MXS
         select CLKSRC_MMIO
         select COMMON_CLK
         select HAVE_CLK_PREPARE
+        select MULTI_IRQ_HANDLER
         select PINCTRL
+        select SPARSE_IRQ
         select USE_OF
         help
           Support for Freescale MXS-based family of processors
@@ -900,6 +892,7 @@ config ARCH_NOMADIK
         select COMMON_CLK
         select GENERIC_CLOCKEVENTS
         select PINCTRL
+        select PINCTRL_STN8815
         select MIGHT_HAVE_CACHE_L2X0
         select ARCH_REQUIRE_GPIOLIB
         help
@@ -951,6 +944,10 @@ config ARCH_VT8500
         select ARCH_HAS_CPUFREQ
         select GENERIC_CLOCKEVENTS
         select ARCH_REQUIRE_GPIOLIB
+        select USE_OF
+        select COMMON_CLK
+        select HAVE_CLK
+        select CLKDEV_LOOKUP
         help
           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 
@@ -1021,8 +1018,6 @@ source "arch/arm/mach-mvebu/Kconfig"
 
 source "arch/arm/mach-at91/Kconfig"
 
-source "arch/arm/mach-bcmring/Kconfig"
-
 source "arch/arm/mach-clps711x/Kconfig"
 
 source "arch/arm/mach-cns3xxx/Kconfig"
@@ -1127,8 +1122,6 @@ source "arch/arm/mach-versatile/Kconfig"
 source "arch/arm/mach-vexpress/Kconfig"
 source "arch/arm/plat-versatile/Kconfig"
 
-source "arch/arm/mach-vt8500/Kconfig"
-
 source "arch/arm/mach-w90x900/Kconfig"
 
 # Definitions to make life easier
@@ -1619,6 +1612,7 @@ config ARCH_NR_GPIO
         default 355 if ARCH_U8500
         default 264 if MACH_H4700
         default 512 if SOC_OMAP5
+        default 288 if ARCH_VT8500
         default 0
         help
           Maximum number of GPIOs in the system.
@@ -1777,59 +1771,6 @@ config FORCE_MAX_ZONEORDER
           This config option is actually maximum order plus one. For example,
           a value of 11 means that the largest free memory block is 2^10 pages.
 
-config LEDS
-        bool "Timer and CPU usage LEDs"
-        depends on ARCH_CDB89712 || ARCH_EBSA110 || \
-                   ARCH_EBSA285 || ARCH_INTEGRATOR || \
-                   ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
-                   ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
-                   ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
-                   ARCH_AT91 || ARCH_DAVINCI || \
-                   ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
-        help
-          If you say Y here, the LEDs on your machine will be used
-          to provide useful information about your current system status.
-
-          If you are compiling a kernel for a NetWinder or EBSA-285, you will
-          be able to select which LEDs are active using the options below. If
-          you are compiling a kernel for the EBSA-110 or the LART however, the
-          red LED will simply flash regularly to indicate that the system is
-          still functional. It is safe to say Y here if you have a CATS
-          system, but the driver will do nothing.
-
-config LEDS_TIMER
-        bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
-                            OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
-                            || MACH_OMAP_PERSEUS2
-        depends on LEDS
-        depends on !GENERIC_CLOCKEVENTS
-        default y if ARCH_EBSA110
-        help
-          If you say Y here, one of the system LEDs (the green one on the
-          NetWinder, the amber one on the EBSA285, or the red one on the LART)
-          will flash regularly to indicate that the system is still
-          operational. This is mainly useful to kernel hackers who are
-          debugging unstable kernels.
-
-          The LART uses the same LED for both Timer LED and CPU usage LED
-          functions. You may choose to use both, but the Timer LED function
-          will overrule the CPU usage LED.
-
-config LEDS_CPU
-        bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
-                        !ARCH_OMAP) \
-                        || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
-                        || MACH_OMAP_PERSEUS2
-        depends on LEDS
-        help
-          If you say Y here, the red LED will be used to give a good real
-          time indication of CPU usage, by lighting whenever the idle task
-          is not currently executing.
-
-          The LART uses the same LED for both Timer LED and CPU usage LED
-          functions. You may choose to use both, but the Timer LED function
-          will overrule the CPU usage LED.
-
 config ALIGNMENT_TRAP
         bool
         depends on CPU_CP15_MMU
@@ -1893,6 +1834,16 @@ config DEPRECATED_PARAM_STRUCT
           This was deprecated in 2001 and announced to live on for 5 years.
           Some old boot loaders still use this way.
 
+config XEN_DOM0
+        def_bool y
+        depends on XEN
+
+config XEN
+        bool "Xen guest support on ARM (EXPERIMENTAL)"
+        depends on EXPERIMENTAL && ARM && OF
+        help
+          Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
+
 endmenu
 
 menu "Boot options"
@@ -2309,7 +2260,7 @@ menu "Power management options"
 source "kernel/power/Kconfig"
 
 config ARCH_SUSPEND_POSSIBLE
-        depends on !ARCH_S5PC100 && !ARCH_TEGRA
+        depends on !ARCH_S5PC100
         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
         def_bool y
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index a7eb28260b2e..b0f3857b3a4c 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -224,6 +224,20 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on i.MX6Q UART4.
 
+        config DEBUG_MMP_UART2
+                bool "Kernel low-level debugging message via MMP UART2"
+                depends on ARCH_MMP
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on MMP UART2.
+
+        config DEBUG_MMP_UART3
+                bool "Kernel low-level debugging message via MMP UART3"
+                depends on ARCH_MMP
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on MMP UART3.
+
         config DEBUG_MSM_UART1
                 bool "Kernel low-level debugging messages via MSM UART1"
                 depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1c974cf9db1b..40ea991b6782 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -137,7 +137,6 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AT91)             += at91
 machine-$(CONFIG_ARCH_BCM2835)          += bcm2835
-machine-$(CONFIG_ARCH_BCMRING)          += bcmring
 machine-$(CONFIG_ARCH_CLPS711X)         += clps711x
 machine-$(CONFIG_ARCH_CNS3XXX)          += cns3xxx
 machine-$(CONFIG_ARCH_DAVINCI)          += davinci
@@ -251,10 +250,12 @@ endif
 core-$(CONFIG_FPE_NWFPE)        += arch/arm/nwfpe/
 core-$(CONFIG_FPE_FASTFPE)      += $(FASTFPE_OBJ)
 core-$(CONFIG_VFP)              += arch/arm/vfp/
+core-$(CONFIG_XEN)              += arch/arm/xen/
 
 # If we have a machine-specific directory, then include it in the build.
 core-y                          += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
 core-y                          += arch/arm/net/
+core-y                          += arch/arm/crypto/
 core-y                          += $(machdirs) $(platdirs)
 
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 81769c1341fa..bc67cbff3944 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -653,6 +653,7 @@ __armv7_mmu_cache_on:
                 mcrne   p15, 0, r0, c8, c7, 0   @ flush I,D TLBs
 #endif
                 mrc     p15, 0, r0, c1, c0, 0   @ read control reg
+                bic     r0, r0, #1 << 28        @ clear SCTLR.TRE
                 orr     r0, r0, #0x5000         @ I-cache enable, RR cache replacement
                 orr     r0, r0, #0x003c         @ write buffer
 #ifdef CONFIG_MMU
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d4ad2df08920..29f541f0e653 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
         dove-dove-db.dtb
 dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos4210-smdkv310.dtb \
+        exynos4210-trats.dtb \
         exynos5250-smdk5250.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
 dtb-$(CONFIG_ARCH_IMX5) += imx51-babbage.dtb \
@@ -101,6 +102,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
         vexpress-v2p-ca9.dtb \
         vexpress-v2p-ca15-tc1.dtb \
-        vexpress-v2p-ca15_a7.dtb
+        vexpress-v2p-ca15_a7.dtb \
+        xenvm-4.2.dtb
 
 endif
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 66389c1c6f62..7c95f76398de 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -104,6 +104,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioB: gpio@fffff600 {
@@ -113,6 +114,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioC: gpio@fffff800 {
@@ -122,6 +124,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         dbgu: serial@fffff200 {
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index b460d6ce9eb5..195019b7ca0e 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -95,6 +95,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioB: gpio@fffff400 {
@@ -104,6 +105,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioC: gpio@fffff600 {
@@ -113,6 +115,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioD: gpio@fffff800 {
@@ -122,6 +125,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioE: gpio@fffffa00 {
@@ -131,6 +135,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         dbgu: serial@ffffee00 {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index bafa8806fc17..63751b1e744b 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -113,6 +113,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioB: gpio@fffff400 {
@@ -122,6 +123,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioC: gpio@fffff600 {
@@ -131,6 +133,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioD: gpio@fffff800 {
@@ -140,6 +143,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioE: gpio@fffffa00 {
@@ -149,6 +153,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         dbgu: serial@ffffee00 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index bfac0dfc332c..ef9336ae9614 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -107,6 +107,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioB: gpio@fffff600 {
@@ -116,6 +117,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioC: gpio@fffff800 {
@@ -125,6 +127,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioD: gpio@fffffa00 {
@@ -134,6 +137,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         dbgu: serial@fffff200 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 4a18c393b136..8a387a8d61b7 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -115,6 +115,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioB: gpio@fffff600 {
@@ -124,6 +125,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioC: gpio@fffff800 {
@@ -133,6 +135,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         pioD: gpio@fffffa00 {
@@ -142,6 +145,7 @@
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         dbgu: serial@fffff200 {
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 3180a9c588b9..748ba7aa746c 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -194,6 +194,8 @@
                         interrupts = <0 47 0x4>;
                         #address-cells = <1>;
                         #size-cells = <1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
                         ranges;
 
                         prcmu-timer-4@80157450 {
@@ -330,6 +332,7 @@
                         ab8500@5 {
                                 compatible = "stericsson,ab8500";
                                 reg = <5>; /* mailbox 5 is i2c */
+                                interrupt-parent = <&intc>;
                                 interrupts = <0 40 0x4>;
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
@@ -371,7 +374,7 @@
                                 };
 
                                 ab8500-ponkey {
-                                        compatible = "stericsson,ab8500-ponkey";
+                                        compatible = "stericsson,ab8500-poweron-key";
                                         interrupts = <6 0x4
                                                       7 0x4>;
                                         interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
@@ -389,6 +392,12 @@
                                         compatible = "stericsson,ab8500-debug";
                                 };
 
+                                codec: ab8500-codec {
+                                        compatible = "stericsson,ab8500-codec";
+
+                                        stericsson,earpeice-cmv = <950>; /* Units in mV. */
+                                };
+
                                 ab8500-regulators {
                                         compatible = "stericsson,ab8500-regulator";
 
@@ -471,48 +480,63 @@
                 };
 
                 i2c@80004000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80004000 0x1000>;
                         interrupts = <0 21 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+
+                        clock-frequency = <400000>;
                 };
 
                 i2c@80122000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80122000 0x1000>;
                         interrupts = <0 22 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+
+                        clock-frequency = <400000>;
                 };
 
                 i2c@80128000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80128000 0x1000>;
                         interrupts = <0 55 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+
+                        clock-frequency = <400000>;
                 };
 
                 i2c@80110000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80110000 0x1000>;
                         interrupts = <0 12 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+
+                        clock-frequency = <400000>;
                 };
 
                 i2c@8012a000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x8012a000 0x1000>;
                         interrupts = <0 51 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+
+                        clock-frequency = <400000>;
                 };
 
                 ssp@80002000 {
                         compatible = "arm,pl022", "arm,primecell";
-                        reg = <80002000 0x1000>;
+                        reg = <0x80002000 0x1000>;
                         interrupts = <0 14 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -580,6 +604,39 @@
                         status = "disabled";
                 };
 
+                msp0: msp@80123000 {
+                        compatible = "stericsson,ux500-msp-i2s";
+                        reg = <0x80123000 0x1000>;
+                        interrupts = <0 31 0x4>;
+                        v-ape-supply = <&db8500_vape_reg>;
+                        status = "disabled";
+                };
+
+                msp1: msp@80124000 {
+                        compatible = "stericsson,ux500-msp-i2s";
+                        reg = <0x80124000 0x1000>;
+                        interrupts = <0 62 0x4>;
+                        v-ape-supply = <&db8500_vape_reg>;
+                        status = "disabled";
+                };
+
+                // HDMI sound
+                msp2: msp@80117000 {
+                        compatible = "stericsson,ux500-msp-i2s";
+                        reg = <0x80117000 0x1000>;
+                        interrupts = <0 98 0x4>;
+                        v-ape-supply = <&db8500_vape_reg>;
+                        status = "disabled";
+                };
+
+                msp3: msp@80125000 {
+                        compatible = "stericsson,ux500-msp-i2s";
+                        reg = <0x80125000 0x1000>;
+                        interrupts = <0 62 0x4>;
+                        v-ape-supply = <&db8500_vape_reg>;
+                        status = "disabled";
+                };
+
                 external-bus@50000000 {
                         compatible = "simple-bus";
                         reg = <0x50000000 0x4000000>;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
new file mode 100644
index 000000000000..a26c3dd58269
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -0,0 +1,248 @@
+/*
+ * Samsung's Exynos4 SoC series common device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * Samsung's Exynos4 SoC series device nodes are listed in this file.  Particular
+ * SoCs from Exynos4 series can include this file and provide values for SoCs
+ * specfic bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&gic>;
+
+        aliases {
+                spi0 = &spi_0;
+                spi1 = &spi_1;
+                spi2 = &spi_2;
+        };
+
+        gic:interrupt-controller@10490000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+        };
+
+        combiner:interrupt-controller@10440000 {
+                compatible = "samsung,exynos4210-combiner";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0x10440000 0x1000>;
+        };
+
+        watchdog@10060000 {
+                compatible = "samsung,s3c2410-wdt";
+                reg = <0x10060000 0x100>;
+                interrupts = <0 43 0>;
+                status = "disabled";
+        };
+
+        rtc@10070000 {
+                compatible = "samsung,s3c6410-rtc";
+                reg = <0x10070000 0x100>;
+                interrupts = <0 44 0>, <0 45 0>;
+                status = "disabled";
+        };
+
+        keypad@100A0000 {
+                compatible = "samsung,s5pv210-keypad";
+                reg = <0x100A0000 0x100>;
+                interrupts = <0 109 0>;
+                status = "disabled";
+        };
+
+        sdhci@12510000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12510000 0x100>;
+                interrupts = <0 73 0>;
+                status = "disabled";
+        };
+
+        sdhci@12520000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12520000 0x100>;
+                interrupts = <0 74 0>;
+                status = "disabled";
+        };
+
+        sdhci@12530000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12530000 0x100>;
+                interrupts = <0 75 0>;
+                status = "disabled";
+        };
+
+        sdhci@12540000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12540000 0x100>;
+                interrupts = <0 76 0>;
+                status = "disabled";
+        };
+
+        serial@13800000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13800000 0x100>;
+                interrupts = <0 52 0>;
+                status = "disabled";
+        };
+
+        serial@13810000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13810000 0x100>;
+                interrupts = <0 53 0>;
+                status = "disabled";
+        };
+
+        serial@13820000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13820000 0x100>;
+                interrupts = <0 54 0>;
+                status = "disabled";
+        };
+
+        serial@13830000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13830000 0x100>;
+                interrupts = <0 55 0>;
+                status = "disabled";
+        };
+
+        i2c@13860000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13860000 0x100>;
+                interrupts = <0 58 0>;
+                status = "disabled";
+        };
+
+        i2c@13870000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13870000 0x100>;
+                interrupts = <0 59 0>;
+                status = "disabled";
+        };
+
+        i2c@13880000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13880000 0x100>;
+                interrupts = <0 60 0>;
+                status = "disabled";
+        };
+
+        i2c@13890000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13890000 0x100>;
+                interrupts = <0 61 0>;
+                status = "disabled";
+        };
+
+        i2c@138A0000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138A0000 0x100>;
+                interrupts = <0 62 0>;
+                status = "disabled";
+        };
+
+        i2c@138B0000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138B0000 0x100>;
+                interrupts = <0 63 0>;
+                status = "disabled";
+        };
+
+        i2c@138C0000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138C0000 0x100>;
+                interrupts = <0 64 0>;
+                status = "disabled";
+        };
+
+        i2c@138D0000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138D0000 0x100>;
+                interrupts = <0 65 0>;
+                status = "disabled";
+        };
+
+        spi_0: spi@13920000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x13920000 0x100>;
+                interrupts = <0 66 0>;
+                tx-dma-channel = <&pdma0 7>; /* preliminary */
+                rx-dma-channel = <&pdma0 6>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        spi_1: spi@13930000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x13930000 0x100>;
+                interrupts = <0 67 0>;
+                tx-dma-channel = <&pdma1 7>; /* preliminary */
+                rx-dma-channel = <&pdma1 6>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        spi_2: spi@13940000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x13940000 0x100>;
+                interrupts = <0 68 0>;
+                tx-dma-channel = <&pdma0 9>; /* preliminary */
+                rx-dma-channel = <&pdma0 8>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        amba {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,amba-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+
+                pdma0: pdma@12680000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x12680000 0x1000>;
+                        interrupts = <0 35 0>;
+                };
+
+                pdma1: pdma@12690000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x12690000 0x1000>;
+                        interrupts = <0 36 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 0c49caa09978..3e68f52e8454 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -40,6 +40,7 @@
                         <&gpk2 4 2 3 3>,
                         <&gpk2 5 2 3 3>,
                         <&gpk2 6 2 3 3>;
+                status = "okay";
         };
 
         sdhci@12510000 {
@@ -53,6 +54,7 @@
                         <&gpk0 4 2 3 3>,
                         <&gpk0 5 2 3 3>,
                         <&gpk0 6 2 3 3>;
+                status = "okay";
         };
 
         gpio_keys {
@@ -62,88 +64,45 @@
 
                 up {
                         label = "Up";
-                        gpios = <&gpx2 0 0 0 2>;
+                        gpios = <&gpx2 0 0 0x10000 2>;
                         linux,code = <103>;
+                        gpio-key,wakeup;
                 };
 
                 down {
                         label = "Down";
-                        gpios = <&gpx2 1 0 0 2>;
+                        gpios = <&gpx2 1 0 0x10000 2>;
                         linux,code = <108>;
+                        gpio-key,wakeup;
                 };
 
                 back {
                         label = "Back";
-                        gpios = <&gpx1 7 0 0 2>;
+                        gpios = <&gpx1 7 0 0x10000 2>;
                         linux,code = <158>;
+                        gpio-key,wakeup;
                 };
 
                 home {
                         label = "Home";
-                        gpios = <&gpx1 6 0 0 2>;
+                        gpios = <&gpx1 6 0 0x10000 2>;
                         linux,code = <102>;
+                        gpio-key,wakeup;
                 };
 
                 menu {
                         label = "Menu";
-                        gpios = <&gpx1 5 0 0 2>;
+                        gpios = <&gpx1 5 0 0x10000 2>;
                         linux,code = <139>;
+                        gpio-key,wakeup;
                 };
         };
 
-        keypad@100A0000 {
-                status = "disabled";
-        };
-
-        sdhci@12520000 {
-                status = "disabled";
-        };
-
-        sdhci@12540000 {
-                status = "disabled";
-        };
-
-        i2c@13860000 {
-                status = "disabled";
-        };
-
-        i2c@13870000 {
-                status = "disabled";
-        };
-
-        i2c@13880000 {
-                status = "disabled";
-        };
-
-        i2c@13890000 {
-                status = "disabled";
-        };
-
-        i2c@138A0000 {
-                status = "disabled";
-        };
-
-        i2c@138B0000 {
-                status = "disabled";
-        };
-
-        i2c@138C0000 {
-                status = "disabled";
-        };
-
-        i2c@138D0000 {
-                status = "disabled";
-        };
-
-        spi_0: spi@13920000 {
-                status = "disabled";
-        };
-
-        spi_1: spi@13930000 {
-                status = "disabled";
-        };
-
-        spi_2: spi@13940000 {
-                status = "disabled";
+        leds {
+                compatible = "gpio-leds";
+                status {
+                        gpios = <&gpx1 3 0 0x10000 2>;
+                        linux,default-trigger = "heartbeat";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
new file mode 100644
index 000000000000..b12cf272ad0d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -0,0 +1,457 @@
+/*
+ * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2011-2012 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+        pinctrl@11400000 {
+                uart0_data: uart0-data {
+                        samsung,pins = "gpa0-0", "gpa0-1";
+                        samsung,pin-function = <0x2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart0_fctl: uart0-fctl {
+                        samsung,pins = "gpa0-2", "gpa0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart1_data: uart1-data {
+                        samsung,pins = "gpa0-4", "gpa0-5";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart1_fctl: uart1-fctl {
+                        samsung,pins = "gpa0-6", "gpa0-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c2_bus: i2c2-bus {
+                        samsung,pins = "gpa0-6", "gpa0-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart2_data: uart2-data {
+                        samsung,pins = "gpa1-0", "gpa1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart2_fctl: uart2-fctl {
+                        samsung,pins = "gpa1-2", "gpa1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart_audio_a: uart-audio-a {
+                        samsung,pins = "gpa1-0", "gpa1-1";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c3_bus: i2c3-bus {
+                        samsung,pins = "gpa1-2", "gpa1-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart3_data: uart3-data {
+                        samsung,pins = "gpa1-4", "gpa1-5";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart_audio_b: uart-audio-b {
+                        samsung,pins = "gpa1-4", "gpa1-5";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                spi0_bus: spi0-bus {
+                        samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c4_bus: i2c4-bus {
+                        samsung,pins = "gpb-2", "gpb-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                spi1_bus: spi1-bus {
+                        samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c5_bus: i2c5-bus {
+                        samsung,pins = "gpb-6", "gpb-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2s1_bus: i2s1-bus {
+                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                        "gpc0-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                pcm1_bus: pcm1-bus {
+                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                        "gpc0-4";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                ac97_bus: ac97-bus {
+                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                        "gpc0-4";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2s2_bus: i2s2-bus {
+                        samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                        "gpc1-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                pcm2_bus: pcm2-bus {
+                        samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                        "gpc1-4";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                spdif_bus: spdif-bus {
+                        samsung,pins = "gpc1-0", "gpc1-1";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c6_bus: i2c6-bus {
+                        samsung,pins = "gpc1-3", "gpc1-4";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                spi2_bus: spi2-bus {
+                        samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
+                        samsung,pin-function = <5>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c7_bus: i2c7-bus {
+                        samsung,pins = "gpd0-2", "gpd0-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c0_bus: i2c0-bus {
+                        samsung,pins = "gpd1-0", "gpd1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c1_bus: i2c1-bus {
+                        samsung,pins = "gpd1-2", "gpd1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+
+        pinctrl@11000000 {
+                sd0_clk: sd0-clk {
+                        samsung,pins = "gpk0-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd0_cmd: sd0-cmd {
+                        samsung,pins = "gpk0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd0_cd: sd0-cd {
+                        samsung,pins = "gpk0-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd0_bus1: sd0-bus-width1 {
+                        samsung,pins = "gpk0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd0_bus4: sd0-bus-width4 {
+                        samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd0_bus8: sd0-bus-width8 {
+                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd4_clk: sd4-clk {
+                        samsung,pins = "gpk0-0";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd4_cmd: sd4-cmd {
+                        samsung,pins = "gpk0-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd4_cd: sd4-cd {
+                        samsung,pins = "gpk0-2";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd4_bus1: sd4-bus-width1 {
+                        samsung,pins = "gpk0-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd4_bus4: sd4-bus-width4 {
+                        samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd4_bus8: sd4-bus-width8 {
+                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <4>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd1_clk: sd1-clk {
+                        samsung,pins = "gpk1-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd1_cmd: sd1-cmd {
+                        samsung,pins = "gpk1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd1_cd: sd1-cd {
+                        samsung,pins = "gpk1-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd1_bus1: sd1-bus-width1 {
+                        samsung,pins = "gpk1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd1_bus4: sd1-bus-width4 {
+                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd2_clk: sd2-clk {
+                        samsung,pins = "gpk2-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd2_cmd: sd2-cmd {
+                        samsung,pins = "gpk2-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd2_cd: sd2-cd {
+                        samsung,pins = "gpk2-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd2_bus1: sd2-bus-width1 {
+                        samsung,pins = "gpk2-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd2_bus4: sd2-bus-width4 {
+                        samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd2_bus8: sd2-bus-width8 {
+                        samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd3_clk: sd3-clk {
+                        samsung,pins = "gpk3-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd3_cmd: sd3-cmd {
+                        samsung,pins = "gpk3-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd3_cd: sd3-cd {
+                        samsung,pins = "gpk3-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd3_bus1: sd3-bus-width1 {
+                        samsung,pins = "gpk3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd3_bus4: sd3-bus-width4 {
+                        samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                eint0: ext-int0 {
+                        samsung,pins = "gpx0-0";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                eint8: ext-int8 {
+                        samsung,pins = "gpx1-0";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                eint15: ext-int15 {
+                        samsung,pins = "gpx1-7";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                eint16: ext-int16 {
+                        samsung,pins = "gpx2-0";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                eint31: ext-int31 {
+                        samsung,pins = "gpx3-7";
+                        samsung,pin-function = <0xf>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+
+        pinctrl@03860000 {
+                i2s0_bus: i2s0-bus {
+                        samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                        "gpz-4", "gpz-5", "gpz-6";
+                        samsung,pin-function = <0x2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                pcm0_bus: pcm0-bus {
+                        samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                        "gpz-4";
+                        samsung,pin-function = <0x3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 1beccc8f14ff..63610c3ba3af 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -26,7 +26,7 @@
         };
 
         chosen {
-                bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
+                bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
         };
 
         sdhci@12530000 {
@@ -40,6 +40,7 @@
                         <&gpk2 4 2 3 3>,
                         <&gpk2 5 2 3 3>,
                         <&gpk2 6 2 3 3>;
+                status = "okay";
         };
 
         keypad@100A0000 {
@@ -47,6 +48,7 @@
                 samsung,keypad-num-columns = <8>;
                 linux,keypad-no-autorepeat;
                 linux,keypad-wakeup;
+                status = "okay";
 
                 row-gpios = <&gpx2 0 3 3 0>,
                             <&gpx2 1 3 3 0>;
@@ -128,6 +130,7 @@
                 samsung,i2c-max-bus-freq = <20000>;
                 gpios = <&gpd1 0 2 3 0>,
                         <&gpd1 1 2 3 0>;
+                status = "okay";
 
                 eeprom@50 {
                         compatible = "samsung,24ad0xd1";
@@ -140,58 +143,11 @@
                 };
         };
 
-        sdhci@12510000 {
-                status = "disabled";
-        };
-
-        sdhci@12520000 {
-                status = "disabled";
-        };
-
-        sdhci@12540000 {
-                status = "disabled";
-        };
-
-        i2c@13870000 {
-                status = "disabled";
-        };
-
-        i2c@13880000 {
-                status = "disabled";
-        };
-
-        i2c@13890000 {
-                status = "disabled";
-        };
-
-        i2c@138A0000 {
-                status = "disabled";
-        };
-
-        i2c@138B0000 {
-                status = "disabled";
-        };
-
-        i2c@138C0000 {
-                status = "disabled";
-        };
-
-        i2c@138D0000 {
-                status = "disabled";
-        };
-
-        spi_0: spi@13920000 {
-                status = "disabled";
-        };
-
-        spi_1: spi@13930000 {
-                status = "disabled";
-        };
-
         spi_2: spi@13940000 {
                 gpios = <&gpc1 1 5 3 0>,
                         <&gpc1 3 5 3 0>,
                         <&gpc1 4 5 3 0>;
+                status = "okay";
 
                 w25x80@0 {
                         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
new file mode 100644
index 000000000000..73567b843e72
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -0,0 +1,237 @@
+/*
+ * Samsung's Exynos4210 based Trats board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Trats board which is based on
+ * Samsung's Exynos4210 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4210.dtsi"
+
+/ {
+        model = "Samsung Trats based on Exynos4210";
+        compatible = "samsung,trats", "samsung,exynos4210";
+
+        memory {
+                reg =  <0x40000000 0x20000000
+                        0x60000000 0x20000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
+        };
+
+        vemmc_reg: voltage-regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "VMEM_VDD_2.8V";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpk0 2 1 0 0>;
+                enable-active-high;
+        };
+
+        sdhci_emmc: sdhci@12510000 {
+                bus-width = <8>;
+                non-removable;
+                broken-voltage;
+                gpios = <&gpk0 0 2 0 3>,
+                        <&gpk0 1 2 0 3>,
+                        <&gpk0 3 2 2 3>,
+                        <&gpk0 4 2 2 3>,
+                        <&gpk0 5 2 2 3>,
+                        <&gpk0 6 2 2 3>,
+                        <&gpk1 3 3 3 3>,
+                        <&gpk1 4 3 3 3>,
+                        <&gpk1 5 3 3 3>,
+                        <&gpk1 6 3 3 3>;
+                vmmc-supply = <&vemmc_reg>;
+                status = "okay";
+        };
+
+        serial@13800000 {
+                status = "okay";
+        };
+
+        serial@13810000 {
+                status = "okay";
+        };
+
+        serial@13820000 {
+                status = "okay";
+        };
+
+        serial@13830000 {
+                status = "okay";
+        };
+
+        i2c@138B0000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-slave-addr = <0x10>;
+                samsung,i2c-max-bus-freq = <100000>;
+                gpios = <&gpb 6 3 3 0>,
+                        <&gpb 7 3 3 0>;
+                status = "okay";
+
+                max8997_pmic@66 {
+                        compatible = "maxim,max8997-pmic";
+
+                        reg = <0x66>;
+
+                        max8997,pmic-buck1-uses-gpio-dvs;
+                        max8997,pmic-buck2-uses-gpio-dvs;
+                        max8997,pmic-buck5-uses-gpio-dvs;
+
+                        max8997,pmic-ignore-gpiodvs-side-effect;
+                        max8997,pmic-buck125-default-dvs-idx = <0>;
+
+                        max8997,pmic-buck125-dvs-gpios = <&gpx0 5 1 0 0>,
+                                                         <&gpx0 6 1 0 0>,
+                                                         <&gpl0 0 1 0 0>;
+
+                        max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
+                                                         <1250000>, <1200000>,
+                                                         <1150000>, <1100000>,
+                                                         <1000000>, <950000>;
+
+                        max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>,
+                                                         <950000>,  <900000>,
+                                                         <1100000>, <1000000>,
+                                                         <950000>,  <900000>;
+
+                        max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>;
+
+                        regulators {
+                                valive_reg: LDO2 {
+                                     regulator-name = "VALIVE_1.1V_C210";
+                                     regulator-min-microvolt = <1100000>;
+                                     regulator-max-microvolt = <1100000>;
+                                     regulator-always-on;
+                                };
+
+                                vusb_reg: LDO3 {
+                                     regulator-name = "VUSB_1.1V_C210";
+                                     regulator-min-microvolt = <1100000>;
+                                     regulator-max-microvolt = <1100000>;
+                                };
+
+                                vmipi_reg: LDO4 {
+                                     regulator-name = "VMIPI_1.8V";
+                                     regulator-min-microvolt = <1800000>;
+                                     regulator-max-microvolt = <1800000>;
+                                };
+
+                                vpda_reg: LDO6 {
+                                     regulator-name = "VCC_1.8V_PDA";
+                                     regulator-min-microvolt = <1800000>;
+                                     regulator-max-microvolt = <1800000>;
+                                     regulator-always-on;
+                                };
+
+                                vcam_reg: LDO7 {
+                                     regulator-name = "CAM_ISP_1.8V";
+                                     regulator-min-microvolt = <1800000>;
+                                     regulator-max-microvolt = <1800000>;
+                                };
+
+                                vusbdac_reg: LDO8 {
+                                     regulator-name = "VUSB/VDAC_3.3V_C210";
+                                     regulator-min-microvolt = <3300000>;
+                                     regulator-max-microvolt = <3300000>;
+                                };
+
+                                vccpda_reg: LDO9 {
+                                     regulator-name = "VCC_2.8V_PDA";
+                                     regulator-min-microvolt = <2800000>;
+                                     regulator-max-microvolt = <2800000>;
+                                     regulator-always-on;
+                                };
+
+                                vpll_reg: LDO10 {
+                                     regulator-name = "VPLL_1.1V_C210";
+                                     regulator-min-microvolt = <1100000>;
+                                     regulator-max-microvolt = <1100000>;
+                                     regulator-always-on;
+                                };
+
+                                vcclcd_reg: LDO13 {
+                                     regulator-name = "VCC_3.3V_LCD";
+                                     regulator-min-microvolt = <3300000>;
+                                     regulator-max-microvolt = <3300000>;
+                                };
+
+                                vlcd_reg: LDO15 {
+                                     regulator-name = "VLCD_2.2V";
+                                     regulator-min-microvolt = <2200000>;
+                                     regulator-max-microvolt = <2200000>;
+                                };
+
+                                camsensor_reg: LDO16 {
+                                     regulator-name = "CAM_SENSOR_IO_1.8V";
+                                     regulator-min-microvolt = <1800000>;
+                                     regulator-max-microvolt = <1800000>;
+                                };
+
+                                vddq_reg: LDO21 {
+                                     regulator-name = "VDDQ_M1M2_1.2V";
+                                     regulator-min-microvolt = <1200000>;
+                                     regulator-max-microvolt = <1200000>;
+                                     regulator-always-on;
+                                };
+
+                                varm_breg: BUCK1 {
+                                     regulator-name = "VARM_1.2V_C210";
+                                     regulator-min-microvolt = <900000>;
+                                     regulator-max-microvolt = <1350000>;
+                                     regulator-always-on;
+                                };
+
+                                vint_breg: BUCK2 {
+                                     regulator-name = "VINT_1.1V_C210";
+                                     regulator-min-microvolt = <900000>;
+                                     regulator-max-microvolt = <1100000>;
+                                     regulator-always-on;
+                                };
+
+                                camisp_breg: BUCK4 {
+                                     regulator-name = "CAM_ISP_CORE_1.2V";
+                                     regulator-min-microvolt = <1200000>;
+                                     regulator-max-microvolt = <1200000>;
+                                };
+
+                                vmem_breg: BUCK5 {
+                                     regulator-name = "VMEM_1.2V_C210";
+                                     regulator-min-microvolt = <1200000>;
+                                     regulator-max-microvolt = <1200000>;
+                                     regulator-always-on;
+                                };
+
+                                vccsub_breg: BUCK7 {
+                                     regulator-name = "VCC_SUB_2.0V";
+                                     regulator-min-microvolt = <2000000>;
+                                     regulator-max-microvolt = <2000000>;
+                                     regulator-always-on;
+                                };
+
+                                safe1_sreg: ESAFEOUT1 {
+                                     regulator-name = "SAFEOUT1";
+                                     regulator-always-on;
+                                };
+
+                                safe2_sreg: ESAFEOUT2 {
+                                     regulator-name = "SAFEOUT2";
+                                     regulator-boot-on;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 02891fe876e4..214c557eda7f 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,199 +19,60 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "skeleton.dtsi"
+/include/ "exynos4.dtsi"
+/include/ "exynos4210-pinctrl.dtsi"
 
 / {
         compatible = "samsung,exynos4210";
-        interrupt-parent = <&gic>;
 
         aliases {
-                spi0 = &spi_0;
-                spi1 = &spi_1;
-                spi2 = &spi_2;
+                pinctrl0 = &pinctrl_0;
+                pinctrl1 = &pinctrl_1;
+                pinctrl2 = &pinctrl_2;
         };
 
         gic:interrupt-controller@10490000 {
-                compatible = "arm,cortex-a9-gic";
-                #interrupt-cells = <3>;
-                interrupt-controller;
                 cpu-offset = <0x8000>;
-                reg = <0x10490000 0x1000>, <0x10480000 0x100>;
         };
 
         combiner:interrupt-controller@10440000 {
-                compatible = "samsung,exynos4210-combiner";
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                reg = <0x10440000 0x1000>;
                 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
                              <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
                              <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
         };
 
-        watchdog@10060000 {
-                compatible = "samsung,s3c2410-wdt";
-                reg = <0x10060000 0x100>;
-                interrupts = <0 43 0>;
-        };
-
-        rtc@10070000 {
-                compatible = "samsung,s3c6410-rtc";
-                reg = <0x10070000 0x100>;
-                interrupts = <0 44 0>, <0 45 0>;
-        };
-
-        keypad@100A0000 {
-                compatible = "samsung,s5pv210-keypad";
-                reg = <0x100A0000 0x100>;
-                interrupts = <0 109 0>;
-        };
-
-        sdhci@12510000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12510000 0x100>;
-                interrupts = <0 73 0>;
-        };
-
-        sdhci@12520000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12520000 0x100>;
-                interrupts = <0 74 0>;
-        };
-
-        sdhci@12530000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12530000 0x100>;
-                interrupts = <0 75 0>;
-        };
-
-        sdhci@12540000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12540000 0x100>;
-                interrupts = <0 76 0>;
-        };
-
-        serial@13800000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x13800000 0x100>;
-                interrupts = <0 52 0>;
-        };
-
-        serial@13810000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x13810000 0x100>;
-                interrupts = <0 53 0>;
-        };
-
-        serial@13820000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x13820000 0x100>;
-                interrupts = <0 54 0>;
-        };
-
-        serial@13830000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x13830000 0x100>;
-                interrupts = <0 55 0>;
-        };
-
-        i2c@13860000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x13860000 0x100>;
-                interrupts = <0 58 0>;
-        };
-
-        i2c@13870000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x13870000 0x100>;
-                interrupts = <0 59 0>;
-        };
-
-        i2c@13880000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x13880000 0x100>;
-                interrupts = <0 60 0>;
-        };
-
-        i2c@13890000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x13890000 0x100>;
-                interrupts = <0 61 0>;
-        };
-
-        i2c@138A0000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x138A0000 0x100>;
-                interrupts = <0 62 0>;
-        };
-
-        i2c@138B0000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x138B0000 0x100>;
-                interrupts = <0 63 0>;
-        };
-
-        i2c@138C0000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x138C0000 0x100>;
-                interrupts = <0 64 0>;
-        };
-
-        i2c@138D0000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x138D0000 0x100>;
-                interrupts = <0 65 0>;
-        };
-
-        spi_0: spi@13920000 {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0x13920000 0x100>;
-                interrupts = <0 66 0>;
-                tx-dma-channel = <&pdma0 7>; /* preliminary */
-                rx-dma-channel = <&pdma0 6>; /* preliminary */
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
-
-        spi_1: spi@13930000 {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0x13930000 0x100>;
-                interrupts = <0 67 0>;
-                tx-dma-channel = <&pdma1 7>; /* preliminary */
-                rx-dma-channel = <&pdma1 6>; /* preliminary */
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
-
-        spi_2: spi@13940000 {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0x13940000 0x100>;
-                interrupts = <0 68 0>;
-                tx-dma-channel = <&pdma0 9>; /* preliminary */
-                rx-dma-channel = <&pdma0 8>; /* preliminary */
-                #address-cells = <1>;
-                #size-cells = <0>;
+        pinctrl_0: pinctrl@11400000 {
+                compatible = "samsung,pinctrl-exynos4210";
+                reg = <0x11400000 0x1000>;
+                interrupts = <0 47 0>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
         };
 
-        amba {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "arm,amba-bus";
-                interrupt-parent = <&gic>;
-                ranges;
+        pinctrl_1: pinctrl@11000000 {
+                compatible = "samsung,pinctrl-exynos4210";
+                reg = <0x11000000 0x1000>;
+                interrupts = <0 46 0>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
 
-                pdma0: pdma@12680000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x12680000 0x1000>;
-                        interrupts = <0 35 0>;
+                wakup_eint: wakeup-interrupt-controller {
+                        compatible = "samsung,exynos4210-wakeup-eint";
+                        interrupt-parent = <&gic>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                                     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+                                     <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+                                     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
+                                     <0 32 0>;
                 };
+        };
 
-                pdma1: pdma@12690000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x12690000 0x1000>;
-                        interrupts = <0 36 0>;
-                };
+        pinctrl_2: pinctrl@03860000 {
+                compatible = "samsung,pinctrl-exynos4210";
+                reg = <0x03860000 0x1000>;
         };
 
         gpio-controllers {
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348793c7..a352df403b7a 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -16,12 +16,19 @@
         model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
         compatible = "samsung,smdk5250", "samsung,exynos5250";
 
+        aliases {
+                mshc0 = &dwmmc_0;
+                mshc1 = &dwmmc_1;
+                mshc2 = &dwmmc_2;
+                mshc3 = &dwmmc_3;
+        };
+
         memory {
                 reg = <0x40000000 0x80000000>;
         };
 
         chosen {
-                bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
+                bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
         };
 
         i2c@12C60000 {
@@ -72,6 +79,56 @@
                 status = "disabled";
         };
 
+        dwmmc_0: dwmmc0@12200000 {
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3 3>;
+                samsung,dw-mshc-ddr-timing = <1 2 3>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                        gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
+                                <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
+                                <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
+                                <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
+                                <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
+                };
+        };
+
+        dwmmc_1: dwmmc1@12210000 {
+                status = "disabled";
+        };
+
+        dwmmc_2: dwmmc2@12220000 {
+                num-slots = <1>;
+                supports-highspeed;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3 3>;
+                samsung,dw-mshc-ddr-timing = <1 2 3>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <4>;
+                        samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
+                        gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
+                                <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
+                                <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>,
+                                <&gpc4 3 3 3 3>, <&gpc4 3 3 3 3>,
+                                <&gpc4 5 3 3 3>, <&gpc4 6 3 3 3>;
+                };
+        };
+
+        dwmmc_3: dwmmc3@12230000 {
+                status = "disabled";
+        };
+
         spi_0: spi@12d20000 {
                 status = "disabled";
         };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 004aaa8d123c..dddfd6e444dc 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -27,6 +27,10 @@
                 spi0 = &spi_0;
                 spi1 = &spi_1;
                 spi2 = &spi_2;
+                gsc0 = &gsc_0;
+                gsc1 = &gsc_1;
+                gsc2 = &gsc_2;
+                gsc3 = &gsc_3;
         };
 
         gic:interrupt-controller@10481000 {
@@ -182,6 +186,38 @@
                 #size-cells = <0>;
         };
 
+        dwmmc0@12200000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                reg = <0x12200000 0x1000>;
+                interrupts = <0 75 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        dwmmc1@12210000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                reg = <0x12210000 0x1000>;
+                interrupts = <0 76 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        dwmmc2@12220000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                reg = <0x12220000 0x1000>;
+                interrupts = <0 77 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        dwmmc3@12230000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                reg = <0x12230000 0x1000>;
+                interrupts = <0 78 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
         amba {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -460,4 +496,28 @@
                         #gpio-cells = <4>;
                 };
         };
+
+        gsc_0:  gsc@0x13e00000 {
+                compatible = "samsung,exynos5-gsc";
+                reg = <0x13e00000 0x1000>;
+                interrupts = <0 85 0>;
+        };
+
+        gsc_1:  gsc@0x13e10000 {
+                compatible = "samsung,exynos5-gsc";
+                reg = <0x13e10000 0x1000>;
+                interrupts = <0 86 0>;
+        };
+
+        gsc_2:  gsc@0x13e20000 {
+                compatible = "samsung,exynos5-gsc";
+                reg = <0x13e20000 0x1000>;
+                interrupts = <0 87 0>;
+        };
+
+        gsc_3:  gsc@0x13e30000 {
+                compatible = "samsung,exynos5-gsc";
+                reg = <0x13e30000 0x1000>;
+                interrupts = <0 88 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 9fecf1ae777b..0c6fc34821f9 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -121,6 +121,10 @@
                         compatible = "calxeda,hb-ahci";
                         reg = <0xffe08000 0x10000>;
                         interrupts = <0 83 4>;
+                        calxeda,port-phys = <&combophy5 0 &combophy0 0
+                                             &combophy0 1 &combophy0 2
+                                             &combophy0 3>;
+                        dma-coherent;
                 };
 
                 sdhci@ffe0e000 {
@@ -306,5 +310,19 @@
                         reg = <0xfff51000 0x1000>;
                         interrupts = <0 80 4  0 81 4  0 82 4>;
                 };
+
+                combophy0: combo-phy@fff58000 {
+                        compatible = "calxeda,hb-combophy";
+                        #phy-cells = <1>;
+                        reg = <0xfff58000 0x1000>;
+                        phydev = <5>;
+                };
+
+                combophy5: combo-phy@fff5d000 {
+                        compatible = "calxeda,hb-combophy";
+                        #phy-cells = <1>;
+                        reg = <0xfff5d000 0x1000>;
+                        phydev = <31>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
new file mode 100644
index 000000000000..2131d77dc9c9
--- /dev/null
+++ b/arch/arm/boot/dts/hrefv60plus.dts
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2012 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "dbx5x0.dtsi"
+
+/ {
+        model = "ST-Ericsson HREF platform with Device Tree";
+        compatible = "st-ericsson,hrefv60+";
+
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+
+        soc-u9500 {
+                uart@80120000 {
+                        status = "okay";
+                };
+
+                uart@80121000 {
+                        status = "okay";
+                };
+
+                uart@80007000 {
+                        status = "okay";
+                };
+
+                i2c@80004000 {
+                        tc3589x@42 {
+                                compatible = "tc3589x";
+                                reg = <0x42>;
+                                interrupt-parent = <&gpio6>;
+                                interrupts = <25 0x1>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+
+                                tc3589x_gpio: tc3589x_gpio {
+                                        compatible = "tc3589x-gpio";
+                                        interrupts = <0 0x1>;
+
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+                        };
+
+                        tps61052@33 {
+                                compatible = "tps61052";
+                                reg = <0x33>;
+                        };
+                };
+
+                i2c@80128000 {
+                        lp5521@0x33 {
+                                compatible = "lp5521";
+                                reg = <0x33>;
+                        };
+
+                        lp5521@0x34 {
+                                compatible = "lp5521";
+                                reg = <0x34>;
+                        };
+
+                        bh1780@0x29 {
+                                compatible = "rohm,bh1780gli";
+                                reg = <0x33>;
+                        };
+                };
+
+                sound {
+                        compatible = "stericsson,snd-soc-mop500";
+
+                        stericsson,cpu-dai = <&msp1 &msp3>;
+                        stericsson,audio-codec = <&codec>;
+                };
+
+                msp1: msp@80124000 {
+                        status = "okay";
+                };
+
+                msp3: msp@80125000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 3f3b6fc229b3..9ca4ca70c1bc 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -43,7 +43,7 @@
                         ranges;
 
                         icoll: interrupt-controller@80000000 {
-                                compatible = "fsl,imx23-icoll", "fsl,mxs-icoll";
+                                compatible = "fsl,imx23-icoll", "fsl,icoll";
                                 interrupt-controller;
                                 #interrupt-cells = <1>;
                                 reg = <0x80000000 0x2000>;
@@ -407,8 +407,9 @@
                         };
 
                         timrot@80068000 {
+                                compatible = "fsl,imx23-timrot", "fsl,timrot";
                                 reg = <0x80068000 0x2000>;
-                                status = "disabled";
+                                interrupts = <28 29 30 31>;
                         };
 
                         auart0: serial@8006c000 {
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 724147eab84b..59fbfba23df8 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -52,7 +52,7 @@
                         ranges;
 
                         icoll: interrupt-controller@80000000 {
-                                compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
+                                compatible = "fsl,imx28-icoll", "fsl,icoll";
                                 interrupt-controller;
                                 #interrupt-cells = <1>;
                                 reg = <0x80000000 0x2000>;
@@ -787,8 +787,9 @@
                         };
 
                         timrot@80068000 {
+                                compatible = "fsl,imx28-timrot", "fsl,timrot";
                                 reg = <0x80068000 0x2000>;
-                                status = "disabled";
+                                interrupts = <48 49 50 51>;
                         };
 
                         auart0: serial@8006a000 {
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 35e5895ba3df..f3990b04fecf 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -400,8 +400,8 @@
                                 #clock-cells = <1>;
                         };
 
-                        anatop@020c8000 {
-                                compatible = "fsl,imx6q-anatop";
+                        anatop: anatop@020c8000 {
+                                compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
                                 reg = <0x020c8000 0x1000>;
                                 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 
@@ -531,6 +531,11 @@
                                 interrupts = <0 89 0x04 0 90 0x04>;
                         };
 
+                        gpr: iomuxc-gpr@020e0000 {
+                                compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+                                reg = <0x020e0000 0x38>;
+                        };
+
                         iomuxc@020e0000 {
                                 compatible = "fsl,imx6q-iomuxc";
                                 reg = <0x020e0000 0x4000>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 5d1c48459e6e..3883f94fdbd0 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -430,5 +430,13 @@
                         hw-caps-ll-interface;
                         hw-caps-temp-alert;
                 };
+
+                ocp2scp {
+                        compatible = "ti,omap-ocp2scp";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        ti,hwmods = "ocp2scp_usb_phy";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 9ac75b37c992..5db33f481a33 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -33,9 +33,21 @@
         cpus {
                 cpu@0 {
                         compatible = "arm,cortex-a15";
+                        timer {
+                                compatible = "arm,armv7-timer";
+                                /* 14th PPI IRQ, active low level-sensitive */
+                                interrupts = <1 14 0x308>;
+                                clock-frequency = <6144000>;
+                        };
                 };
                 cpu@1 {
                         compatible = "arm,cortex-a15";
+                        timer {
+                                compatible = "arm,armv7-timer";
+                                /* 14th PPI IRQ, active low level-sensitive */
+                                interrupts = <1 14 0x308>;
+                                clock-frequency = <6144000>;
+                        };
                 };
         };
 
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
index a7ad85e4b8f9..90fdbd77f274 100644
--- a/arch/arm/boot/dts/phy3250.dts
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -189,16 +189,14 @@
         leds {
                 compatible = "gpio-leds";
 
-                led0 {
-                        gpios = <&gpio 5 1 1>; /* GPO_P3 1, GPIO 80, active low */
-                        linux,default-trigger = "heartbeat";
+                led0 { /* red */
+                        gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
                         default-state = "off";
                 };
 
-                led1 {
-                        gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
-                        linux,default-trigger = "timer";
-                        default-state = "off";
+                led1 { /* green */
+                        gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
+                        linux,default-trigger = "heartbeat";
                 };
         };
 };
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
index e92be5a474e7..595492aa5053 100644
--- a/arch/arm/boot/dts/pxa910-dkb.dts
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -29,6 +29,143 @@
                         };
                         twsi1: i2c@d4011000 {
                                 status = "okay";
+
+                                pmic: 88pm860x@34 {
+                                        compatible = "marvell,88pm860x";
+                                        reg = <0x34>;
+                                        interrupts = <4>;
+                                        interrupt-parent = <&intc>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <1>;
+
+                                        marvell,88pm860x-irq-read-clr;
+                                        marvell,88pm860x-slave-addr = <0x11>;
+
+                                        regulators {
+                                                BUCK1 {
+                                                        regulator-min-microvolt = <1000000>;
+                                                        regulator-max-microvolt = <1500000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                BUCK2 {
+                                                        regulator-min-microvolt = <1000000>;
+                                                        regulator-max-microvolt = <1500000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                BUCK3 {
+                                                        regulator-min-microvolt = <1000000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO1 {
+                                                        regulator-min-microvolt = <1200000>;
+                                                        regulator-max-microvolt = <2800000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO2 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO3 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO4 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
+                                                };
+                                                LDO5 {
+                                                        regulator-min-microvolt = <2900000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO6 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO7 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <2900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO8 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <2900000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO9 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO10 {
+                                                        regulator-min-microvolt = <1200000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-boot-on;
+                                                        regulator-always-on;
+                                                };
+                                                LDO12 {
+                                                        regulator-min-microvolt = <1200000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
+                                                };
+                                                LDO13 {
+                                                        regulator-min-microvolt = <1200000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
+                                                };
+                                                LDO14 {
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
+                                                };
+                                        };
+                                        rtc {
+                                                marvell,88pm860x-vrtc = <1>;
+                                        };
+                                        touch {
+                                                marvell,88pm860x-gpadc-prebias = <1>;
+                                                marvell,88pm860x-gpadc-slot-cycle = <1>;
+                                                marvell,88pm860x-tsi-prebias = <6>;
+                                                marvell,88pm860x-pen-prebias = <16>;
+                                                marvell,88pm860x-pen-prechg = <2>;
+                                                marvell,88pm860x-resistor-X = <300>;
+                                        };
+                                        backlights {
+                                                backlight-0 {
+                                                        marvell,88pm860x-iset = <4>;
+                                                        marvell,88pm860x-pwm = <3>;
+                                                };
+                                                backlight-2 {
+                                                };
+                                        };
+                                        leds {
+                                                led0-red {
+                                                        marvell,88pm860x-iset = <12>;
+                                                };
+                                                led0-green {
+                                                        marvell,88pm860x-iset = <12>;
+                                                };
+                                                led0-blue {
+                                                        marvell,88pm860x-iset = <12>;
+                                                };
+                                        };
+                                };
                         };
                         rtc: rtc@d4010000 {
                                 status = "okay";
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index a3be44d86bcd..825aaca33034 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -120,6 +120,8 @@
 
                         twsi1: i2c@d4011000 {
                                 compatible = "mrvl,mmp-twsi";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 reg = <0xd4011000 0x1000>;
                                 interrupts = <7>;
                                 mrvl,i2c-fast-mode;
@@ -128,6 +130,8 @@
 
                         twsi2: i2c@d4037000 {
                                 compatible = "mrvl,mmp-twsi";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 reg = <0xd4037000 0x1000>;
                                 interrupts = <54>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 7e334d4cae21..702c0baa6004 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-/include/ "db8500.dtsi"
+/include/ "dbx5x0.dtsi"
 
 / {
         model = "Calao Systems Snowball platform with device tree";
@@ -83,6 +83,22 @@
         };
 
         soc-u9500 {
+
+                sound {
+                        compatible = "stericsson,snd-soc-mop500";
+
+                        stericsson,cpu-dai = <&msp1 &msp3>;
+                        stericsson,audio-codec = <&codec>;
+                };
+
+                msp1: msp@80124000 {
+                        status = "okay";
+                };
+
+                msp3: msp@80125000 {
+                        status = "okay";
+                };
+
                 external-bus@50000000 {
                         status = "okay";
 
@@ -111,7 +127,6 @@
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux3_reg>;
 
-                        #gpio-cells = <1>;
                         cd-gpios  = <&gpio6 26 0x4>; // 218
                         cd-inverted;
 
diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
new file mode 100644
index 000000000000..567cf4e8ab84
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500-bv07.dts
@@ -0,0 +1,36 @@
+/*
+ * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "vt8500.dtsi"
+
+/ {
+        model = "Benign BV07 Netbook";
+
+        /*
+         * Display node is based on Sascha Hauer's patch on dri-devel.
+         * Added a bpp property to calculate the size of the framebuffer
+         * until the binding is formalized.
+         */
+        display: display@0 {
+                modes {
+                        mode0: mode@0 {
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <88>;
+                                hfront-porch = <40>;
+                                hsync-len = <0>;
+                                vback-porch = <32>;
+                                vfront-porch = <11>;
+                                vsync-len = <1>;
+                                clock = <0>;    /* unused but required */
+                                bpp = <16>;     /* non-standard but required */
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
new file mode 100644
index 000000000000..d8645e990b21
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -0,0 +1,116 @@
+/*
+ * vt8500.dtsi - Device tree file for VIA VT8500 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "via,vt8500";
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                interrupt-parent = <&intc>;
+
+                intc: interrupt-controller@d8140000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        reg = <0xd8140000 0x10000>;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio: gpio-controller@d8110000 {
+                        compatible = "via,vt8500-gpio";
+                        gpio-controller;
+                        reg = <0xd8110000 0x10000>;
+                        #gpio-cells = <3>;
+                };
+
+                pmc@d8130000 {
+                        compatible = "via,vt8500-pmc";
+                        reg = <0xd8130000 0x1000>;
+
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ref24: ref24M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <24000000>;
+                                };
+                        };
+                };
+
+                timer@d8130100 {
+                        compatible = "via,vt8500-timer";
+                        reg = <0xd8130100 0x28>;
+                        interrupts = <36>;
+                };
+
+                ehci@d8007900 {
+                        compatible = "via,vt8500-ehci";
+                        reg = <0xd8007900 0x200>;
+                        interrupts = <43>;
+                };
+
+                uhci@d8007b00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8007b00 0x200>;
+                        interrupts = <43>;
+                };
+
+                fb@d800e400 {
+                        compatible = "via,vt8500-fb";
+                        reg = <0xd800e400 0x400>;
+                        interrupts = <12>;
+                        display = <&display>;
+                        default-mode = <&mode0>;
+                };
+
+                ge_rops@d8050400 {
+                        compatible = "wm,prizm-ge-rops";
+                        reg = <0xd8050400 0x100>;
+                };
+
+                uart@d8200000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8200000 0x1040>;
+                        interrupts = <32>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d82b0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82b0000 0x1040>;
+                        interrupts = <33>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d8210000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8210000 0x1040>;
+                        interrupts = <47>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d82c0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82c0000 0x1040>;
+                        interrupts = <50>;
+                        clocks = <&ref24>;
+                };
+
+                rtc@d8100000 {
+                        compatible = "via,vt8500-rtc";
+                        reg = <0xd8100000 0x10000>;
+                        interrupts = <48>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
new file mode 100644
index 000000000000..fd4e248074c6
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505-ref.dts
@@ -0,0 +1,36 @@
+/*
+ * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8505.dtsi"
+
+/ {
+        model = "Wondermedia WM8505 Netbook";
+
+        /*
+         * Display node is based on Sascha Hauer's patch on dri-devel.
+         * Added a bpp property to calculate the size of the framebuffer
+         * until the binding is formalized.
+         */
+        display: display@0 {
+                modes {
+                        mode0: mode@0 {
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <88>;
+                                hfront-porch = <40>;
+                                hsync-len = <0>;
+                                vback-porch = <32>;
+                                vfront-porch = <11>;
+                                vsync-len = <1>;
+                                clock = <0>;    /* unused but required */
+                                bpp = <32>;     /* non-standard but required */
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
new file mode 100644
index 000000000000..b459691655ab
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -0,0 +1,143 @@
+/*
+ * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "wm,wm8505";
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                interrupt-parent = <&intc0>;
+
+                intc0: interrupt-controller@d8140000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        reg = <0xd8140000 0x10000>;
+                        #interrupt-cells = <1>;
+                };
+
+                /* Secondary IC cascaded to intc0 */
+                intc1: interrupt-controller@d8150000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xD8150000 0x10000>;
+                        interrupts = <56 57 58 59 60 61 62 63>;
+                };
+
+                gpio: gpio-controller@d8110000 {
+                        compatible = "wm,wm8505-gpio";
+                        gpio-controller;
+                        reg = <0xd8110000 0x10000>;
+                        #gpio-cells = <3>;
+                };
+
+                pmc@d8130000 {
+                        compatible = "via,vt8500-pmc";
+                        reg = <0xd8130000 0x1000>;
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ref24: ref24M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <24000000>;
+                                };
+                        };
+                };
+
+                timer@d8130100 {
+                        compatible = "via,vt8500-timer";
+                        reg = <0xd8130100 0x28>;
+                        interrupts = <36>;
+                };
+
+                ehci@d8007100 {
+                        compatible = "via,vt8500-ehci";
+                        reg = <0xd8007100 0x200>;
+                        interrupts = <43>;
+                };
+
+                uhci@d8007300 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8007300 0x200>;
+                        interrupts = <43>;
+                };
+
+                fb@d8050800 {
+                        compatible = "wm,wm8505-fb";
+                        reg = <0xd8050800 0x200>;
+                        display = <&display>;
+                        default-mode = <&mode0>;
+                };
+
+                ge_rops@d8050400 {
+                        compatible = "wm,prizm-ge-rops";
+                        reg = <0xd8050400 0x100>;
+                };
+
+                uart@d8200000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8200000 0x1040>;
+                        interrupts = <32>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d82b0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82b0000 0x1040>;
+                        interrupts = <33>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d8210000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8210000 0x1040>;
+                        interrupts = <47>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d82c0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82c0000 0x1040>;
+                        interrupts = <50>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d8370000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8370000 0x1040>;
+                        interrupts = <31>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d8380000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8380000 0x1040>;
+                        interrupts = <30>;
+                        clocks = <&ref24>;
+                };
+
+                rtc@d8100000 {
+                        compatible = "via,vt8500-rtc";
+                        reg = <0xd8100000 0x10000>;
+                        interrupts = <48>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
new file mode 100644
index 000000000000..cefd938f842f
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650-mid.dts
@@ -0,0 +1,36 @@
+/*
+ * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8650.dtsi"
+
+/ {
+        model = "Wondermedia WM8650-MID Tablet";
+
+        /*
+         * Display node is based on Sascha Hauer's patch on dri-devel.
+         * Added a bpp property to calculate the size of the framebuffer
+         * until the binding is formalized.
+         */
+        display: display@0 {
+                modes {
+                        mode0: mode@0 {
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <88>;
+                                hfront-porch = <40>;
+                                hsync-len = <0>;
+                                vback-porch = <32>;
+                                vfront-porch = <11>;
+                                vsync-len = <1>;
+                                clock = <0>;    /* unused but required */
+                                bpp = <16>;     /* non-standard but required */
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
new file mode 100644
index 000000000000..83b9467559bb
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -0,0 +1,147 @@
+/*
+ * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "wm,wm8650";
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                interrupt-parent = <&intc0>;
+
+                intc0: interrupt-controller@d8140000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        reg = <0xd8140000 0x10000>;
+                        #interrupt-cells = <1>;
+                };
+
+                /* Secondary IC cascaded to intc0 */
+                intc1: interrupt-controller@d8150000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xD8150000 0x10000>;
+                        interrupts = <56 57 58 59 60 61 62 63>;
+                };
+
+                gpio: gpio-controller@d8110000 {
+                        compatible = "wm,wm8650-gpio";
+                        gpio-controller;
+                        reg = <0xd8110000 0x10000>;
+                        #gpio-cells = <3>;
+                };
+
+                pmc@d8130000 {
+                        compatible = "via,vt8500-pmc";
+                        reg = <0xd8130000 0x1000>;
+
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ref25: ref25M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <25000000>;
+                                };
+
+                                ref24: ref24M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <24000000>;
+                                };
+
+                                plla: plla {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x200>;
+                                };
+
+                                pllb: pllb {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x204>;
+                                };
+
+                                arm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+
+                                sdhc: sdhc {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x328>;
+                                        divisor-mask = <0x3f>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <18>;
+                                };
+                        };
+                };
+
+                timer@d8130100 {
+                        compatible = "via,vt8500-timer";
+                        reg = <0xd8130100 0x28>;
+                        interrupts = <36>;
+                };
+
+                ehci@d8007900 {
+                        compatible = "via,vt8500-ehci";
+                        reg = <0xd8007900 0x200>;
+                        interrupts = <43>;
+                };
+
+                uhci@d8007b00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8007b00 0x200>;
+                        interrupts = <43>;
+                };
+
+                fb@d8050800 {
+                        compatible = "wm,wm8505-fb";
+                        reg = <0xd8050800 0x200>;
+                        display = <&display>;
+                        default-mode = <&mode0>;
+                };
+
+                ge_rops@d8050400 {
+                        compatible = "wm,prizm-ge-rops";
+                        reg = <0xd8050400 0x100>;
+                };
+
+                uart@d8200000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8200000 0x1040>;
+                        interrupts = <32>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d82b0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82b0000 0x1040>;
+                        interrupts = <33>;
+                        clocks = <&ref24>;
+                };
+
+                rtc@d8100000 {
+                        compatible = "via,vt8500-rtc";
+                        reg = <0xd8100000 0x10000>;
+                        interrupts = <48>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/xenvm-4.2.dts b/arch/arm/boot/dts/xenvm-4.2.dts
new file mode 100644
index 000000000000..ec3f9528e180
--- /dev/null
+++ b/arch/arm/boot/dts/xenvm-4.2.dts
@@ -0,0 +1,68 @@
+/*
+ * Xen Virtual Machine for unprivileged guests
+ *
+ * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU)
+ * Cortex-A15 MPCore (V2P-CA15)
+ *
+ */
+
+/dts-v1/;
+
+/ {
+        model = "XENVM-4.2";
+        compatible = "xen,xenvm-4.2", "xen,xenvm";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        chosen {
+                /* this field is going to be adjusted by the hypervisor */
+                bootargs = "console=hvc0 root=/dev/xvda";
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                };
+        };
+
+        memory@80000000 {
+                device_type = "memory";
+                /* this field is going to be adjusted by the hypervisor */
+                reg = <0 0x80000000 0 0x08000000>;
+        };
+
+        gic: interrupt-controller@2c001000 {
+                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0 0x2c001000 0 0x1000>,
+                      <0 0x2c002000 0 0x100>;
+        };
+
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
+        };
+
+        hypervisor {
+                compatible = "xen,xen-4.2", "xen,xen";
+                /* this field is going to be adjusted by the hypervisor */
+                reg = <0 0xb0000000 0 0x20000>;
+                /* this field is going to be adjusted by the hypervisor */
+                interrupts = <1 15 0xf08>;
+        };
+
+        motherboard {
+                arm,v2m-memory-map = "rs1";
+        };
+};
diff --git a/arch/arm/configs/afeb9260_defconfig b/arch/arm/configs/afeb9260_defconfig
index 2afdf67c2127..c285a9d777d9 100644
--- a/arch/arm/configs/afeb9260_defconfig
+++ b/arch/arm/configs/afeb9260_defconfig
@@ -39,7 +39,6 @@ CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_ATMEL_SSC=y
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index 90610c7030f7..f78d259f8d23 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -85,6 +85,7 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=8
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
 CONFIG_I2C_SH_MOBILE=y
 # CONFIG_HWMON is not set
 CONFIG_MEDIA_SUPPORT=y
@@ -120,6 +121,8 @@ CONFIG_USB_ETH=m
 CONFIG_MMC=y
 CONFIG_MMC_SDHI=y
 CONFIG_MMC_SH_MMCIF=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_S35390A=y
 CONFIG_DMADEVICES=y
 CONFIG_SH_DMAE=y
 CONFIG_UIO=y
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
index d54e2acd3ab1..4ae57a34a582 100644
--- a/arch/arm/configs/at91rm9200_defconfig
+++ b/arch/arm/configs/at91rm9200_defconfig
@@ -232,7 +232,7 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 CONFIG_USB_MASS_STORAGE=m
 CONFIG_MMC=y
-CONFIG_MMC_AT91=y
+CONFIG_MMC_ATMELMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/at91sam9261_defconfig b/arch/arm/configs/at91sam9261_defconfig
index ade6b2f23116..1e8712ef062e 100644
--- a/arch/arm/configs/at91sam9261_defconfig
+++ b/arch/arm/configs/at91sam9261_defconfig
@@ -128,7 +128,7 @@ CONFIG_USB_GADGETFS=m
 CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
-CONFIG_MMC_AT91=m
+CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index 1cf96264cba1..d2050cada82d 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -61,7 +61,6 @@ CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_BLOCK2MTD=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
@@ -138,7 +137,7 @@ CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
 CONFIG_SDIO_UART=m
-CONFIG_MMC_AT91=m
+CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_ATMEL_PWM=y
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9g20_defconfig
index 994d331b2319..e1b0e80b54a5 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9g20_defconfig
@@ -99,7 +99,7 @@ CONFIG_USB_GADGETFS=m
 CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
-CONFIG_MMC_AT91=m
+CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/at91sam9rl_defconfig b/arch/arm/configs/at91sam9rl_defconfig
index ad562ee64209..7cf87856d63c 100644
--- a/arch/arm/configs/at91sam9rl_defconfig
+++ b/arch/arm/configs/at91sam9rl_defconfig
@@ -60,7 +60,7 @@ CONFIG_AT91SAM9X_WATCHDOG=y
 CONFIG_FB=y
 CONFIG_FB_ATMEL=y
 CONFIG_MMC=y
-CONFIG_MMC_AT91=m
+CONFIG_MMC_ATMELMCI=m
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/bcmring_defconfig b/arch/arm/configs/bcmring_defconfig
deleted file mode 100644
index 9e6a8fe13164..000000000000
--- a/arch/arm/configs/bcmring_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_PERF_EVENTS=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_BCMRING=y
-CONFIG_BCM_ZRELADDR=0x8000
-CONFIG_CPU_32v6K=y
-CONFIG_NO_HZ=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_ZBOOT_ROM_TEXT=0x0e000000
-CONFIG_ZBOOT_ROM_BSS=0x0ea00000
-CONFIG_ZBOOT_ROM=y
-CONFIG_NET=y
-# CONFIG_WIRELESS is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
-CONFIG_MTD_NAND_BCM_UMI=y
-CONFIG_MTD_NAND_BCM_UMI_HWCS=y
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=64
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-# CONFIG_JFFS2_FS_SECURITY is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_HEADERS_CHECK=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/cpu9260_defconfig b/arch/arm/configs/cpu9260_defconfig
index bbf729e2fb6f..921480c23b98 100644
--- a/arch/arm/configs/cpu9260_defconfig
+++ b/arch/arm/configs/cpu9260_defconfig
@@ -82,7 +82,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 CONFIG_MMC=y
-CONFIG_MMC_AT91=m
+CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/cpu9g20_defconfig b/arch/arm/configs/cpu9g20_defconfig
index e7d7942927f3..ea116cbdffa1 100644
--- a/arch/arm/configs/cpu9g20_defconfig
+++ b/arch/arm/configs/cpu9g20_defconfig
@@ -82,7 +82,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 CONFIG_MMC=y
-CONFIG_MMC_AT91=m
+CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 565132d02105..66aa7a6db884 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -40,7 +40,6 @@ CONFIG_VMSPLIT_2G=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
 CONFIG_VFP=y
 CONFIG_NEON=y
@@ -177,6 +176,9 @@ CONFIG_SND_SOC_IMX_MC13783=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_MXS_PHY=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 5d0c66708960..c88b57886e79 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -23,7 +23,6 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_SHMOBILE=y
-CONFIG_KEYBOARD_GPIO_POLLED=y
 CONFIG_ARCH_SH73A0=y
 CONFIG_MACH_KZM9G=y
 CONFIG_MEMORY_START=0x41000000
@@ -71,6 +70,7 @@ CONFIG_INPUT_SPARSEKMAP=y
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ST1232=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index e42a0e3d4c3a..92386b20bd09 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -133,7 +133,6 @@ CONFIG_SND_DEBUG_VERBOSE=y
 # CONFIG_SND_ARM is not set
 # CONFIG_SND_SPI is not set
 CONFIG_SND_SOC=y
-# CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
@@ -149,6 +148,7 @@ CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_PCA9532=y
 CONFIG_LEDS_PCA9532_GPIO=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
@@ -161,10 +161,13 @@ CONFIG_RTC_DRV_DS1374=y
 CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_LPC32XX=y
 CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
 CONFIG_STAGING=y
 CONFIG_LPC32XX_ADC=y
-CONFIG_MAX517=y
 CONFIG_IIO=y
+CONFIG_MAX517=y
+CONFIG_PWM=y
+CONFIG_PWM_LPC32XX=y
 CONFIG_EXT2_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_MSDOS_FS=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 864f9a5c39dd..53382b6c8bb4 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -1,13 +1,14 @@
 # CONFIG_ARM_PATCH_PHYS_VIRT is not set
 CONFIG_EXPERIMENTAL=y
 CONFIG_KERNEL_LZMA=y
+CONFIG_NO_HZ=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
-# CONFIG_BLOCK is not set
+# CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_SHMOBILE=y
 CONFIG_ARCH_R8A7779=y
 CONFIG_MACH_MARZEN=y
@@ -21,7 +22,6 @@ CONFIG_ARM_ERRATA_458693=y
 CONFIG_ARM_ERRATA_460075=y
 CONFIG_ARM_ERRATA_743622=y
 CONFIG_ARM_ERRATA_754322=y
-CONFIG_NO_HZ=y
 CONFIG_SMP=y
 # CONFIG_ARM_CPU_TOPOLOGY is not set
 CONFIG_AEABI=y
@@ -29,13 +29,16 @@ CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
+CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on"
 CONFIG_CMDLINE_FORCE=y
 CONFIG_KEXEC=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
+CONFIG_UNIX=y
 CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
@@ -68,17 +71,21 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_RCAR_THERMAL=y
 CONFIG_SSB=y
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
-# CONFIG_FILE_LOCKING is not set
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY_USER is not set
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_INFO_REDUCED=y
diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 5a584520db2f..f1cb95e58af0 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -16,7 +16,7 @@ CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=128M user_debug=255"
+CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=128M user_debug=255 earlyprintk"
 CONFIG_VFP=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -90,6 +90,9 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_DYNAMIC_DEBUG is not set
 CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_MMP_UART3=y
+CONFIG_EARLY_PRINTK=y
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
new file mode 100644
index 000000000000..159f75fc4377
--- /dev/null
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -0,0 +1,57 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_MACH_ARMADA_370=y
+CONFIG_MACH_ARMADA_XP=y
+CONFIG_ARCH_HIGHBANK=y
+CONFIG_ARCH_SOCFPGA=y
+# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_SMP=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_NET=y
+CONFIG_ATA=y
+CONFIG_SATA_HIGHBANK=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_CALXEDA_XGMAC=y
+CONFIG_SMSC911X=y
+CONFIG_STMMAC_ETH=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_IPMI_HANDLER=y
+CONFIG_IPMI_SI=y
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_GPIOLIB=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_USB=y
+CONFIG_USB_ISP1760_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EDAC=y
+CONFIG_EDAC_MM_EDAC=y
+CONFIG_EDAC_HIGHBANK_MC=y
+CONFIG_EDAC_HIGHBANK_L2=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_DMADEVICES=y
+CONFIG_PL330_DMA=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 36d60dda310c..048aaca60814 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -53,6 +53,9 @@ CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 # CONFIG_BLK_DEV is not set
 CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_M25P80
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_GPMI_NAND=y
 CONFIG_NETDEVICES=y
@@ -82,13 +85,13 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MXS=y
 CONFIG_SPI=y
 CONFIG_SPI_GPIO=m
+CONFIG_SPI_MXS=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 # CONFIG_MFD_SUPPORT is not set
 CONFIG_DISPLAY_SUPPORT=m
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
@@ -103,14 +106,45 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 CONFIG_SND_SOC_SGTL5000=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_FB=y
+CONFIG_FB_MXS=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_LOGO=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_MMC=y
 CONFIG_MMC_MXS=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1307=m
 CONFIG_RTC_DRV_STMP=y
 CONFIG_DMADEVICES=y
 CONFIG_MXS_DMA=y
+CONFIG_STAGING=y
+CONFIG_MXS_LRADC=y
+CONFIG_IIO_SYSFS_TRIGGER=y
 CONFIG_COMMON_CLK_DEBUG=y
+CONFIG_IIO=y
+CONFIG_PWM=y
+CONFIG_PWM_MXS=y
 CONFIG_EXT3_FS=y
 # CONFIG_DNOTIFY is not set
 CONFIG_FSCACHE=m
diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig
index 1cd381e1d47d..191118caa5c0 100644
--- a/arch/arm/configs/pxa910_defconfig
+++ b/arch/arm/configs/pxa910_defconfig
@@ -17,7 +17,7 @@ CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M"
+CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M earlyprintk"
 CONFIG_FPE_NWFPE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -66,5 +66,7 @@ CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_MMP_UART2=y
+CONFIG_EARLY_PRINTK=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/qil-a9260_defconfig b/arch/arm/configs/qil-a9260_defconfig
index 9160f3b7751f..42d5db1876ab 100644
--- a/arch/arm/configs/qil-a9260_defconfig
+++ b/arch/arm/configs/qil-a9260_defconfig
@@ -50,7 +50,6 @@ CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
@@ -87,7 +86,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 CONFIG_MMC=y
-CONFIG_MMC_AT91=m
+CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig
index ba6a515086b5..3a186d653dac 100644
--- a/arch/arm/configs/s3c6400_defconfig
+++ b/arch/arm/configs/s3c6400_defconfig
@@ -9,11 +9,14 @@ CONFIG_ARCH_S3C64XX=y
 CONFIG_S3C_BOOT_ERROR_RESET=y
 CONFIG_MACH_SMDK6400=y
 CONFIG_MACH_ANW6410=y
+CONFIG_MACH_MINI6410=y
+CONFIG_MACH_REAL6410=y
 CONFIG_MACH_SMDK6410=y
 CONFIG_MACH_NCP=y
 CONFIG_MACH_HMT=y
 CONFIG_MACH_SMARTQ5=y
 CONFIG_MACH_SMARTQ7=y
+CONFIG_MACH_WLF_CRAGG_6410=y
 CONFIG_CPU_32v6K=y
 CONFIG_AEABI=y
 CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc initrd=0x51000000,6M ramdisk_size=6144"
diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
index ecf2531523a1..b4384af1bea6 100644
--- a/arch/arm/configs/sam9_l9260_defconfig
+++ b/arch/arm/configs/sam9_l9260_defconfig
@@ -39,7 +39,7 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_RESERVE=3
+CONFIG_MTD_UBI_BEB_LIMIT=25
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
diff --git a/arch/arm/configs/stamp9g20_defconfig b/arch/arm/configs/stamp9g20_defconfig
index d5e260b8b160..52f1488591c7 100644
--- a/arch/arm/configs/stamp9g20_defconfig
+++ b/arch/arm/configs/stamp9g20_defconfig
@@ -100,7 +100,6 @@ CONFIG_USB_ETH=m
 CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
-# CONFIG_MMC_AT91 is not set
 CONFIG_MMC_ATMELMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 0d6bb738c6de..e2184f6c20b3 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -24,11 +24,11 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_TEGRA=y
+CONFIG_GPIO_PCA953X=y
 CONFIG_ARCH_TEGRA_2x_SOC=y
 CONFIG_ARCH_TEGRA_3x_SOC=y
-CONFIG_MACH_HARMONY=y
-CONFIG_MACH_PAZ00=y
-CONFIG_MACH_TRIMSLICE=y
+CONFIG_TEGRA_PCI=y
+CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA=y
 CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
@@ -67,7 +67,18 @@ CONFIG_INET6_IPCOMP=y
 CONFIG_IPV6_MIP6=y
 CONFIG_IPV6_TUNNEL=y
 CONFIG_IPV6_MULTIPLE_TABLES=y
-# CONFIG_WIRELESS is not set
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIBTUSB=m
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_GPIO=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
@@ -87,7 +98,8 @@ CONFIG_USB_PEGASUS=y
 CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
-# CONFIG_WLAN is not set
+CONFIG_RT2X00=y
+CONFIG_RT2800USB=m
 CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
@@ -105,25 +117,31 @@ CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
 CONFIG_SPI_TEGRA=y
-CONFIG_GPIO_TPS65910=y
+CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GPIO_TPS6586X=y
+CONFIG_GPIO_TPS65910=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_BATTERY_SBS=y
 CONFIG_SENSORS_LM90=y
 CONFIG_MFD_TPS6586X=y
 CONFIG_MFD_TPS65910=y
+CONFIG_MFD_MAX8907=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MAX8907=y
 CONFIG_REGULATOR_TPS62360=y
 CONFIG_REGULATOR_TPS6586X=y
 CONFIG_REGULATOR_TPS65910=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
 CONFIG_SOUND=y
 CONFIG_SND=y
 # CONFIG_SND_SUPPORT_OLD_API is not set
 # CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_PCI is not set
 # CONFIG_SND_ARM is not set
 # CONFIG_SND_SPI is not set
 # CONFIG_SND_USB is not set
@@ -136,13 +154,25 @@ CONFIG_SND_SOC_TEGRA_ALC5632=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_ACM=y
+CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_DRV_MAX8907=y
+CONFIG_RTC_DRV_TPS65910=y
 CONFIG_RTC_DRV_EM3027=y
 CONFIG_RTC_DRV_TEGRA=y
 CONFIG_DMADEVICES=y
@@ -154,10 +184,14 @@ CONFIG_SENSORS_AK8975=y
 CONFIG_MFD_NVEC=y
 CONFIG_KEYBOARD_NVEC=y
 CONFIG_SERIO_NVEC_PS2=y
+CONFIG_NVEC_POWER=y
+CONFIG_NVEC_PAZ00=y
 CONFIG_TEGRA_IOMMU_GART=y
 CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_MEMORY=y
 CONFIG_IIO=y
+CONFIG_PWM=y
+CONFIG_PWM_TEGRA=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
@@ -170,6 +204,7 @@ CONFIG_EXT4_FS=y
 # CONFIG_DNOTIFY is not set
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
@@ -188,8 +223,6 @@ CONFIG_DEBUG_VM=y
 CONFIG_DEBUG_SG=y
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ARC4=y
 CONFIG_CRYPTO_TWOFISH=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_DEV_TEGRA_AES=y
diff --git a/arch/arm/configs/usb-a9260_defconfig b/arch/arm/configs/usb-a9260_defconfig
index 2e39f38b9627..a1501e1e1a90 100644
--- a/arch/arm/configs/usb-a9260_defconfig
+++ b/arch/arm/configs/usb-a9260_defconfig
@@ -49,7 +49,6 @@ CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile
new file mode 100644
index 000000000000..a2c83851bc90
--- /dev/null
+++ b/arch/arm/crypto/Makefile
@@ -0,0 +1,9 @@
+#
+# Arch-specific CryptoAPI modules.
+#
+
+obj-$(CONFIG_CRYPTO_AES_ARM) += aes-arm.o
+obj-$(CONFIG_CRYPTO_SHA1_ARM) += sha1-arm.o
+
+aes-arm-y  := aes-armv4.o aes_glue.o
+sha1-arm-y := sha1-armv4-large.o sha1_glue.o
diff --git a/arch/arm/crypto/aes-armv4.S b/arch/arm/crypto/aes-armv4.S
new file mode 100644
index 000000000000..e59b1d505d6c
--- /dev/null
+++ b/arch/arm/crypto/aes-armv4.S
@@ -0,0 +1,1112 @@
+#define __ARM_ARCH__ __LINUX_ARM_ARCH__
+@ ====================================================================
+@ Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
+@ project. The module is, however, dual licensed under OpenSSL and
+@ CRYPTOGAMS licenses depending on where you obtain it. For further
+@ details see http://www.openssl.org/~appro/cryptogams/.
+@ ====================================================================
+
+@ AES for ARMv4
+
+@ January 2007.
+@
+@ Code uses single 1K S-box and is >2 times faster than code generated
+@ by gcc-3.4.1. This is thanks to unique feature of ARMv4 ISA, which
+@ allows to merge logical or arithmetic operation with shift or rotate
+@ in one instruction and emit combined result every cycle. The module
+@ is endian-neutral. The performance is ~42 cycles/byte for 128-bit
+@ key [on single-issue Xscale PXA250 core].
+
+@ May 2007.
+@
+@ AES_set_[en|de]crypt_key is added.
+
+@ July 2010.
+@
+@ Rescheduling for dual-issue pipeline resulted in 12% improvement on
+@ Cortex A8 core and ~25 cycles per byte processed with 128-bit key.
+
+@ February 2011.
+@
+@ Profiler-assisted and platform-specific optimization resulted in 16%
+@ improvement on Cortex A8 core and ~21.5 cycles per byte.
+
+@ A little glue here to select the correct code below for the ARM CPU
+@ that is being targetted.
+
+.text
+.code   32
+
+.type   AES_Te,%object
+.align  5
+AES_Te:
+.word   0xc66363a5, 0xf87c7c84, 0xee777799, 0xf67b7b8d
+.word   0xfff2f20d, 0xd66b6bbd, 0xde6f6fb1, 0x91c5c554
+.word   0x60303050, 0x02010103, 0xce6767a9, 0x562b2b7d
+.word   0xe7fefe19, 0xb5d7d762, 0x4dababe6, 0xec76769a
+.word   0x8fcaca45, 0x1f82829d, 0x89c9c940, 0xfa7d7d87
+.word   0xeffafa15, 0xb25959eb, 0x8e4747c9, 0xfbf0f00b
+.word   0x41adadec, 0xb3d4d467, 0x5fa2a2fd, 0x45afafea
+.word   0x239c9cbf, 0x53a4a4f7, 0xe4727296, 0x9bc0c05b
+.word   0x75b7b7c2, 0xe1fdfd1c, 0x3d9393ae, 0x4c26266a
+.word   0x6c36365a, 0x7e3f3f41, 0xf5f7f702, 0x83cccc4f
+.word   0x6834345c, 0x51a5a5f4, 0xd1e5e534, 0xf9f1f108
+.word   0xe2717193, 0xabd8d873, 0x62313153, 0x2a15153f
+.word   0x0804040c, 0x95c7c752, 0x46232365, 0x9dc3c35e
+.word   0x30181828, 0x379696a1, 0x0a05050f, 0x2f9a9ab5
+.word   0x0e070709, 0x24121236, 0x1b80809b, 0xdfe2e23d
+.word   0xcdebeb26, 0x4e272769, 0x7fb2b2cd, 0xea75759f
+.word   0x1209091b, 0x1d83839e, 0x582c2c74, 0x341a1a2e
+.word   0x361b1b2d, 0xdc6e6eb2, 0xb45a5aee, 0x5ba0a0fb
+.word   0xa45252f6, 0x763b3b4d, 0xb7d6d661, 0x7db3b3ce
+.word   0x5229297b, 0xdde3e33e, 0x5e2f2f71, 0x13848497
+.word   0xa65353f5, 0xb9d1d168, 0x00000000, 0xc1eded2c
+.word   0x40202060, 0xe3fcfc1f, 0x79b1b1c8, 0xb65b5bed
+.word   0xd46a6abe, 0x8dcbcb46, 0x67bebed9, 0x7239394b
+.word   0x944a4ade, 0x984c4cd4, 0xb05858e8, 0x85cfcf4a
+.word   0xbbd0d06b, 0xc5efef2a, 0x4faaaae5, 0xedfbfb16
+.word   0x864343c5, 0x9a4d4dd7, 0x66333355, 0x11858594
+.word   0x8a4545cf, 0xe9f9f910, 0x04020206, 0xfe7f7f81
+.word   0xa05050f0, 0x783c3c44, 0x259f9fba, 0x4ba8a8e3
+.word   0xa25151f3, 0x5da3a3fe, 0x804040c0, 0x058f8f8a
+.word   0x3f9292ad, 0x219d9dbc, 0x70383848, 0xf1f5f504
+.word   0x63bcbcdf, 0x77b6b6c1, 0xafdada75, 0x42212163
+.word   0x20101030, 0xe5ffff1a, 0xfdf3f30e, 0xbfd2d26d
+.word   0x81cdcd4c, 0x180c0c14, 0x26131335, 0xc3ecec2f
+.word   0xbe5f5fe1, 0x359797a2, 0x884444cc, 0x2e171739
+.word   0x93c4c457, 0x55a7a7f2, 0xfc7e7e82, 0x7a3d3d47
+.word   0xc86464ac, 0xba5d5de7, 0x3219192b, 0xe6737395
+.word   0xc06060a0, 0x19818198, 0x9e4f4fd1, 0xa3dcdc7f
+.word   0x44222266, 0x542a2a7e, 0x3b9090ab, 0x0b888883
+.word   0x8c4646ca, 0xc7eeee29, 0x6bb8b8d3, 0x2814143c
+.word   0xa7dede79, 0xbc5e5ee2, 0x160b0b1d, 0xaddbdb76
+.word   0xdbe0e03b, 0x64323256, 0x743a3a4e, 0x140a0a1e
+.word   0x924949db, 0x0c06060a, 0x4824246c, 0xb85c5ce4
+.word   0x9fc2c25d, 0xbdd3d36e, 0x43acacef, 0xc46262a6
+.word   0x399191a8, 0x319595a4, 0xd3e4e437, 0xf279798b
+.word   0xd5e7e732, 0x8bc8c843, 0x6e373759, 0xda6d6db7
+.word   0x018d8d8c, 0xb1d5d564, 0x9c4e4ed2, 0x49a9a9e0
+.word   0xd86c6cb4, 0xac5656fa, 0xf3f4f407, 0xcfeaea25
+.word   0xca6565af, 0xf47a7a8e, 0x47aeaee9, 0x10080818
+.word   0x6fbabad5, 0xf0787888, 0x4a25256f, 0x5c2e2e72
+.word   0x381c1c24, 0x57a6a6f1, 0x73b4b4c7, 0x97c6c651
+.word   0xcbe8e823, 0xa1dddd7c, 0xe874749c, 0x3e1f1f21
+.word   0x964b4bdd, 0x61bdbddc, 0x0d8b8b86, 0x0f8a8a85
+.word   0xe0707090, 0x7c3e3e42, 0x71b5b5c4, 0xcc6666aa
+.word   0x904848d8, 0x06030305, 0xf7f6f601, 0x1c0e0e12
+.word   0xc26161a3, 0x6a35355f, 0xae5757f9, 0x69b9b9d0
+.word   0x17868691, 0x99c1c158, 0x3a1d1d27, 0x279e9eb9
+.word   0xd9e1e138, 0xebf8f813, 0x2b9898b3, 0x22111133
+.word   0xd26969bb, 0xa9d9d970, 0x078e8e89, 0x339494a7
+.word   0x2d9b9bb6, 0x3c1e1e22, 0x15878792, 0xc9e9e920
+.word   0x87cece49, 0xaa5555ff, 0x50282878, 0xa5dfdf7a
+.word   0x038c8c8f, 0x59a1a1f8, 0x09898980, 0x1a0d0d17
+.word   0x65bfbfda, 0xd7e6e631, 0x844242c6, 0xd06868b8
+.word   0x824141c3, 0x299999b0, 0x5a2d2d77, 0x1e0f0f11
+.word   0x7bb0b0cb, 0xa85454fc, 0x6dbbbbd6, 0x2c16163a
+@ Te4[256]
+.byte   0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5
+.byte   0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76
+.byte   0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0
+.byte   0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0
+.byte   0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc
+.byte   0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15
+.byte   0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a
+.byte   0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75
+.byte   0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0
+.byte   0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84
+.byte   0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b
+.byte   0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf
+.byte   0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85
+.byte   0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8
+.byte   0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5
+.byte   0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2
+.byte   0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17
+.byte   0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73
+.byte   0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88
+.byte   0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb
+.byte   0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c
+.byte   0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79
+.byte   0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9
+.byte   0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08
+.byte   0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6
+.byte   0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a
+.byte   0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e
+.byte   0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e
+.byte   0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94
+.byte   0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf
+.byte   0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68
+.byte   0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
+@ rcon[]
+.word   0x01000000, 0x02000000, 0x04000000, 0x08000000
+.word   0x10000000, 0x20000000, 0x40000000, 0x80000000
+.word   0x1B000000, 0x36000000, 0, 0, 0, 0, 0, 0
+.size   AES_Te,.-AES_Te
+
+@ void AES_encrypt(const unsigned char *in, unsigned char *out,
+@                const AES_KEY *key) {
+.global AES_encrypt
+.type   AES_encrypt,%function
+.align  5
+AES_encrypt:
+        sub     r3,pc,#8                @ AES_encrypt
+        stmdb   sp!,{r1,r4-r12,lr}
+        mov     r12,r0          @ inp
+        mov     r11,r2
+        sub     r10,r3,#AES_encrypt-AES_Te      @ Te
+#if __ARM_ARCH__<7
+        ldrb    r0,[r12,#3]     @ load input data in endian-neutral
+        ldrb    r4,[r12,#2]     @ manner...
+        ldrb    r5,[r12,#1]
+        ldrb    r6,[r12,#0]
+        orr     r0,r0,r4,lsl#8
+        ldrb    r1,[r12,#7]
+        orr     r0,r0,r5,lsl#16
+        ldrb    r4,[r12,#6]
+        orr     r0,r0,r6,lsl#24
+        ldrb    r5,[r12,#5]
+        ldrb    r6,[r12,#4]
+        orr     r1,r1,r4,lsl#8
+        ldrb    r2,[r12,#11]
+        orr     r1,r1,r5,lsl#16
+        ldrb    r4,[r12,#10]
+        orr     r1,r1,r6,lsl#24
+        ldrb    r5,[r12,#9]
+        ldrb    r6,[r12,#8]
+        orr     r2,r2,r4,lsl#8
+        ldrb    r3,[r12,#15]
+        orr     r2,r2,r5,lsl#16
+        ldrb    r4,[r12,#14]
+        orr     r2,r2,r6,lsl#24
+        ldrb    r5,[r12,#13]
+        ldrb    r6,[r12,#12]
+        orr     r3,r3,r4,lsl#8
+        orr     r3,r3,r5,lsl#16
+        orr     r3,r3,r6,lsl#24
+#else
+        ldr     r0,[r12,#0]
+        ldr     r1,[r12,#4]
+        ldr     r2,[r12,#8]
+        ldr     r3,[r12,#12]
+#ifdef __ARMEL__
+        rev     r0,r0
+        rev     r1,r1
+        rev     r2,r2
+        rev     r3,r3
+#endif
+#endif
+        bl      _armv4_AES_encrypt
+
+        ldr     r12,[sp],#4             @ pop out
+#if __ARM_ARCH__>=7
+#ifdef __ARMEL__
+        rev     r0,r0
+        rev     r1,r1
+        rev     r2,r2
+        rev     r3,r3
+#endif
+        str     r0,[r12,#0]
+        str     r1,[r12,#4]
+        str     r2,[r12,#8]
+        str     r3,[r12,#12]
+#else
+        mov     r4,r0,lsr#24            @ write output in endian-neutral
+        mov     r5,r0,lsr#16            @ manner...
+        mov     r6,r0,lsr#8
+        strb    r4,[r12,#0]
+        strb    r5,[r12,#1]
+        mov     r4,r1,lsr#24
+        strb    r6,[r12,#2]
+        mov     r5,r1,lsr#16
+        strb    r0,[r12,#3]
+        mov     r6,r1,lsr#8
+        strb    r4,[r12,#4]
+        strb    r5,[r12,#5]
+        mov     r4,r2,lsr#24
+        strb    r6,[r12,#6]
+        mov     r5,r2,lsr#16
+        strb    r1,[r12,#7]
+        mov     r6,r2,lsr#8
+        strb    r4,[r12,#8]
+        strb    r5,[r12,#9]
+        mov     r4,r3,lsr#24
+        strb    r6,[r12,#10]
+        mov     r5,r3,lsr#16
+        strb    r2,[r12,#11]
+        mov     r6,r3,lsr#8
+        strb    r4,[r12,#12]
+        strb    r5,[r12,#13]
+        strb    r6,[r12,#14]
+        strb    r3,[r12,#15]
+#endif
+#if __ARM_ARCH__>=5
+        ldmia   sp!,{r4-r12,pc}
+#else
+        ldmia   sp!,{r4-r12,lr}
+        tst     lr,#1
+        moveq   pc,lr                   @ be binary compatible with V4, yet
+        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
+#endif
+.size   AES_encrypt,.-AES_encrypt
+
+.type   _armv4_AES_encrypt,%function
+.align  2
+_armv4_AES_encrypt:
+        str     lr,[sp,#-4]!            @ push lr
+        ldmia   r11!,{r4-r7}
+        eor     r0,r0,r4
+        ldr     r12,[r11,#240-16]
+        eor     r1,r1,r5
+        eor     r2,r2,r6
+        eor     r3,r3,r7
+        sub     r12,r12,#1
+        mov     lr,#255
+
+        and     r7,lr,r0
+        and     r8,lr,r0,lsr#8
+        and     r9,lr,r0,lsr#16
+        mov     r0,r0,lsr#24
+.Lenc_loop:
+        ldr     r4,[r10,r7,lsl#2]       @ Te3[s0>>0]
+        and     r7,lr,r1,lsr#16 @ i0
+        ldr     r5,[r10,r8,lsl#2]       @ Te2[s0>>8]
+        and     r8,lr,r1
+        ldr     r6,[r10,r9,lsl#2]       @ Te1[s0>>16]
+        and     r9,lr,r1,lsr#8
+        ldr     r0,[r10,r0,lsl#2]       @ Te0[s0>>24]
+        mov     r1,r1,lsr#24
+
+        ldr     r7,[r10,r7,lsl#2]       @ Te1[s1>>16]
+        ldr     r8,[r10,r8,lsl#2]       @ Te3[s1>>0]
+        ldr     r9,[r10,r9,lsl#2]       @ Te2[s1>>8]
+        eor     r0,r0,r7,ror#8
+        ldr     r1,[r10,r1,lsl#2]       @ Te0[s1>>24]
+        and     r7,lr,r2,lsr#8  @ i0
+        eor     r5,r5,r8,ror#8
+        and     r8,lr,r2,lsr#16 @ i1
+        eor     r6,r6,r9,ror#8
+        and     r9,lr,r2
+        ldr     r7,[r10,r7,lsl#2]       @ Te2[s2>>8]
+        eor     r1,r1,r4,ror#24
+        ldr     r8,[r10,r8,lsl#2]       @ Te1[s2>>16]
+        mov     r2,r2,lsr#24
+
+        ldr     r9,[r10,r9,lsl#2]       @ Te3[s2>>0]
+        eor     r0,r0,r7,ror#16
+        ldr     r2,[r10,r2,lsl#2]       @ Te0[s2>>24]
+        and     r7,lr,r3                @ i0
+        eor     r1,r1,r8,ror#8
+        and     r8,lr,r3,lsr#8  @ i1
+        eor     r6,r6,r9,ror#16
+        and     r9,lr,r3,lsr#16 @ i2
+        ldr     r7,[r10,r7,lsl#2]       @ Te3[s3>>0]
+        eor     r2,r2,r5,ror#16
+        ldr     r8,[r10,r8,lsl#2]       @ Te2[s3>>8]
+        mov     r3,r3,lsr#24
+
+        ldr     r9,[r10,r9,lsl#2]       @ Te1[s3>>16]
+        eor     r0,r0,r7,ror#24
+        ldr     r7,[r11],#16
+        eor     r1,r1,r8,ror#16
+        ldr     r3,[r10,r3,lsl#2]       @ Te0[s3>>24]
+        eor     r2,r2,r9,ror#8
+        ldr     r4,[r11,#-12]
+        eor     r3,r3,r6,ror#8
+
+        ldr     r5,[r11,#-8]
+        eor     r0,r0,r7
+        ldr     r6,[r11,#-4]
+        and     r7,lr,r0
+        eor     r1,r1,r4
+        and     r8,lr,r0,lsr#8
+        eor     r2,r2,r5
+        and     r9,lr,r0,lsr#16
+        eor     r3,r3,r6
+        mov     r0,r0,lsr#24
+
+        subs    r12,r12,#1
+        bne     .Lenc_loop
+
+        add     r10,r10,#2
+
+        ldrb    r4,[r10,r7,lsl#2]       @ Te4[s0>>0]
+        and     r7,lr,r1,lsr#16 @ i0
+        ldrb    r5,[r10,r8,lsl#2]       @ Te4[s0>>8]
+        and     r8,lr,r1
+        ldrb    r6,[r10,r9,lsl#2]       @ Te4[s0>>16]
+        and     r9,lr,r1,lsr#8
+        ldrb    r0,[r10,r0,lsl#2]       @ Te4[s0>>24]
+        mov     r1,r1,lsr#24
+
+        ldrb    r7,[r10,r7,lsl#2]       @ Te4[s1>>16]
+        ldrb    r8,[r10,r8,lsl#2]       @ Te4[s1>>0]
+        ldrb    r9,[r10,r9,lsl#2]       @ Te4[s1>>8]
+        eor     r0,r7,r0,lsl#8
+        ldrb    r1,[r10,r1,lsl#2]       @ Te4[s1>>24]
+        and     r7,lr,r2,lsr#8  @ i0
+        eor     r5,r8,r5,lsl#8
+        and     r8,lr,r2,lsr#16 @ i1
+        eor     r6,r9,r6,lsl#8
+        and     r9,lr,r2
+        ldrb    r7,[r10,r7,lsl#2]       @ Te4[s2>>8]
+        eor     r1,r4,r1,lsl#24
+        ldrb    r8,[r10,r8,lsl#2]       @ Te4[s2>>16]
+        mov     r2,r2,lsr#24
+
+        ldrb    r9,[r10,r9,lsl#2]       @ Te4[s2>>0]
+        eor     r0,r7,r0,lsl#8
+        ldrb    r2,[r10,r2,lsl#2]       @ Te4[s2>>24]
+        and     r7,lr,r3                @ i0
+        eor     r1,r1,r8,lsl#16
+        and     r8,lr,r3,lsr#8  @ i1
+        eor     r6,r9,r6,lsl#8
+        and     r9,lr,r3,lsr#16 @ i2
+        ldrb    r7,[r10,r7,lsl#2]       @ Te4[s3>>0]
+        eor     r2,r5,r2,lsl#24
+        ldrb    r8,[r10,r8,lsl#2]       @ Te4[s3>>8]
+        mov     r3,r3,lsr#24
+
+        ldrb    r9,[r10,r9,lsl#2]       @ Te4[s3>>16]
+        eor     r0,r7,r0,lsl#8
+        ldr     r7,[r11,#0]
+        ldrb    r3,[r10,r3,lsl#2]       @ Te4[s3>>24]
+        eor     r1,r1,r8,lsl#8
+        ldr     r4,[r11,#4]
+        eor     r2,r2,r9,lsl#16
+        ldr     r5,[r11,#8]
+        eor     r3,r6,r3,lsl#24
+        ldr     r6,[r11,#12]
+
+        eor     r0,r0,r7
+        eor     r1,r1,r4
+        eor     r2,r2,r5
+        eor     r3,r3,r6
+
+        sub     r10,r10,#2
+        ldr     pc,[sp],#4              @ pop and return
+.size   _armv4_AES_encrypt,.-_armv4_AES_encrypt
+
+.global private_AES_set_encrypt_key
+.type   private_AES_set_encrypt_key,%function
+.align  5
+private_AES_set_encrypt_key:
+_armv4_AES_set_encrypt_key:
+        sub     r3,pc,#8                @ AES_set_encrypt_key
+        teq     r0,#0
+        moveq   r0,#-1
+        beq     .Labrt
+        teq     r2,#0
+        moveq   r0,#-1
+        beq     .Labrt
+
+        teq     r1,#128
+        beq     .Lok
+        teq     r1,#192
+        beq     .Lok
+        teq     r1,#256
+        movne   r0,#-1
+        bne     .Labrt
+
+.Lok:   stmdb   sp!,{r4-r12,lr}
+        sub     r10,r3,#_armv4_AES_set_encrypt_key-AES_Te-1024  @ Te4
+
+        mov     r12,r0          @ inp
+        mov     lr,r1                   @ bits
+        mov     r11,r2                  @ key
+
+#if __ARM_ARCH__<7
+        ldrb    r0,[r12,#3]     @ load input data in endian-neutral
+        ldrb    r4,[r12,#2]     @ manner...
+        ldrb    r5,[r12,#1]
+        ldrb    r6,[r12,#0]
+        orr     r0,r0,r4,lsl#8
+        ldrb    r1,[r12,#7]
+        orr     r0,r0,r5,lsl#16
+        ldrb    r4,[r12,#6]
+        orr     r0,r0,r6,lsl#24
+        ldrb    r5,[r12,#5]
+        ldrb    r6,[r12,#4]
+        orr     r1,r1,r4,lsl#8
+        ldrb    r2,[r12,#11]
+        orr     r1,r1,r5,lsl#16
+        ldrb    r4,[r12,#10]
+        orr     r1,r1,r6,lsl#24
+        ldrb    r5,[r12,#9]
+        ldrb    r6,[r12,#8]
+        orr     r2,r2,r4,lsl#8
+        ldrb    r3,[r12,#15]
+        orr     r2,r2,r5,lsl#16
+        ldrb    r4,[r12,#14]
+        orr     r2,r2,r6,lsl#24
+        ldrb    r5,[r12,#13]
+        ldrb    r6,[r12,#12]
+        orr     r3,r3,r4,lsl#8
+        str     r0,[r11],#16
+        orr     r3,r3,r5,lsl#16
+        str     r1,[r11,#-12]
+        orr     r3,r3,r6,lsl#24
+        str     r2,[r11,#-8]
+        str     r3,[r11,#-4]
+#else
+        ldr     r0,[r12,#0]
+        ldr     r1,[r12,#4]
+        ldr     r2,[r12,#8]
+        ldr     r3,[r12,#12]
+#ifdef __ARMEL__
+        rev     r0,r0
+        rev     r1,r1
+        rev     r2,r2
+        rev     r3,r3
+#endif
+        str     r0,[r11],#16
+        str     r1,[r11,#-12]
+        str     r2,[r11,#-8]
+        str     r3,[r11,#-4]
+#endif
+
+        teq     lr,#128
+        bne     .Lnot128
+        mov     r12,#10
+        str     r12,[r11,#240-16]
+        add     r6,r10,#256                     @ rcon
+        mov     lr,#255
+
+.L128_loop:
+        and     r5,lr,r3,lsr#24
+        and     r7,lr,r3,lsr#16
+        ldrb    r5,[r10,r5]
+        and     r8,lr,r3,lsr#8
+        ldrb    r7,[r10,r7]
+        and     r9,lr,r3
+        ldrb    r8,[r10,r8]
+        orr     r5,r5,r7,lsl#24
+        ldrb    r9,[r10,r9]
+        orr     r5,r5,r8,lsl#16
+        ldr     r4,[r6],#4                      @ rcon[i++]
+        orr     r5,r5,r9,lsl#8
+        eor     r5,r5,r4
+        eor     r0,r0,r5                        @ rk[4]=rk[0]^...
+        eor     r1,r1,r0                        @ rk[5]=rk[1]^rk[4]
+        str     r0,[r11],#16
+        eor     r2,r2,r1                        @ rk[6]=rk[2]^rk[5]
+        str     r1,[r11,#-12]
+        eor     r3,r3,r2                        @ rk[7]=rk[3]^rk[6]
+        str     r2,[r11,#-8]
+        subs    r12,r12,#1
+        str     r3,[r11,#-4]
+        bne     .L128_loop
+        sub     r2,r11,#176
+        b       .Ldone
+
+.Lnot128:
+#if __ARM_ARCH__<7
+        ldrb    r8,[r12,#19]
+        ldrb    r4,[r12,#18]
+        ldrb    r5,[r12,#17]
+        ldrb    r6,[r12,#16]
+        orr     r8,r8,r4,lsl#8
+        ldrb    r9,[r12,#23]
+        orr     r8,r8,r5,lsl#16
+        ldrb    r4,[r12,#22]
+        orr     r8,r8,r6,lsl#24
+        ldrb    r5,[r12,#21]
+        ldrb    r6,[r12,#20]
+        orr     r9,r9,r4,lsl#8
+        orr     r9,r9,r5,lsl#16
+        str     r8,[r11],#8
+        orr     r9,r9,r6,lsl#24
+        str     r9,[r11,#-4]
+#else
+        ldr     r8,[r12,#16]
+        ldr     r9,[r12,#20]
+#ifdef __ARMEL__
+        rev     r8,r8
+        rev     r9,r9
+#endif
+        str     r8,[r11],#8
+        str     r9,[r11,#-4]
+#endif
+
+        teq     lr,#192
+        bne     .Lnot192
+        mov     r12,#12
+        str     r12,[r11,#240-24]
+        add     r6,r10,#256                     @ rcon
+        mov     lr,#255
+        mov     r12,#8
+
+.L192_loop:
+        and     r5,lr,r9,lsr#24
+        and     r7,lr,r9,lsr#16
+        ldrb    r5,[r10,r5]
+        and     r8,lr,r9,lsr#8
+        ldrb    r7,[r10,r7]
+        and     r9,lr,r9
+        ldrb    r8,[r10,r8]
+        orr     r5,r5,r7,lsl#24
+        ldrb    r9,[r10,r9]
+        orr     r5,r5,r8,lsl#16
+        ldr     r4,[r6],#4                      @ rcon[i++]
+        orr     r5,r5,r9,lsl#8
+        eor     r9,r5,r4
+        eor     r0,r0,r9                        @ rk[6]=rk[0]^...
+        eor     r1,r1,r0                        @ rk[7]=rk[1]^rk[6]
+        str     r0,[r11],#24
+        eor     r2,r2,r1                        @ rk[8]=rk[2]^rk[7]
+        str     r1,[r11,#-20]
+        eor     r3,r3,r2                        @ rk[9]=rk[3]^rk[8]
+        str     r2,[r11,#-16]
+        subs    r12,r12,#1
+        str     r3,[r11,#-12]
+        subeq   r2,r11,#216
+        beq     .Ldone
+
+        ldr     r7,[r11,#-32]
+        ldr     r8,[r11,#-28]
+        eor     r7,r7,r3                        @ rk[10]=rk[4]^rk[9]
+        eor     r9,r8,r7                        @ rk[11]=rk[5]^rk[10]
+        str     r7,[r11,#-8]
+        str     r9,[r11,#-4]
+        b       .L192_loop
+
+.Lnot192:
+#if __ARM_ARCH__<7
+        ldrb    r8,[r12,#27]
+        ldrb    r4,[r12,#26]
+        ldrb    r5,[r12,#25]
+        ldrb    r6,[r12,#24]
+        orr     r8,r8,r4,lsl#8
+        ldrb    r9,[r12,#31]
+        orr     r8,r8,r5,lsl#16
+        ldrb    r4,[r12,#30]
+        orr     r8,r8,r6,lsl#24
+        ldrb    r5,[r12,#29]
+        ldrb    r6,[r12,#28]
+        orr     r9,r9,r4,lsl#8
+        orr     r9,r9,r5,lsl#16
+        str     r8,[r11],#8
+        orr     r9,r9,r6,lsl#24
+        str     r9,[r11,#-4]
+#else
+        ldr     r8,[r12,#24]
+        ldr     r9,[r12,#28]
+#ifdef __ARMEL__
+        rev     r8,r8
+        rev     r9,r9
+#endif
+        str     r8,[r11],#8
+        str     r9,[r11,#-4]
+#endif
+
+        mov     r12,#14
+        str     r12,[r11,#240-32]
+        add     r6,r10,#256                     @ rcon
+        mov     lr,#255
+        mov     r12,#7
+
+.L256_loop:
+        and     r5,lr,r9,lsr#24
+        and     r7,lr,r9,lsr#16
+        ldrb    r5,[r10,r5]
+        and     r8,lr,r9,lsr#8
+        ldrb    r7,[r10,r7]
+        and     r9,lr,r9
+        ldrb    r8,[r10,r8]
+        orr     r5,r5,r7,lsl#24
+        ldrb    r9,[r10,r9]
+        orr     r5,r5,r8,lsl#16
+        ldr     r4,[r6],#4                      @ rcon[i++]
+        orr     r5,r5,r9,lsl#8
+        eor     r9,r5,r4
+        eor     r0,r0,r9                        @ rk[8]=rk[0]^...
+        eor     r1,r1,r0                        @ rk[9]=rk[1]^rk[8]
+        str     r0,[r11],#32
+        eor     r2,r2,r1                        @ rk[10]=rk[2]^rk[9]
+        str     r1,[r11,#-28]
+        eor     r3,r3,r2                        @ rk[11]=rk[3]^rk[10]
+        str     r2,[r11,#-24]
+        subs    r12,r12,#1
+        str     r3,[r11,#-20]
+        subeq   r2,r11,#256
+        beq     .Ldone
+
+        and     r5,lr,r3
+        and     r7,lr,r3,lsr#8
+        ldrb    r5,[r10,r5]
+        and     r8,lr,r3,lsr#16
+        ldrb    r7,[r10,r7]
+        and     r9,lr,r3,lsr#24
+        ldrb    r8,[r10,r8]
+        orr     r5,r5,r7,lsl#8
+        ldrb    r9,[r10,r9]
+        orr     r5,r5,r8,lsl#16
+        ldr     r4,[r11,#-48]
+        orr     r5,r5,r9,lsl#24
+
+        ldr     r7,[r11,#-44]
+        ldr     r8,[r11,#-40]
+        eor     r4,r4,r5                        @ rk[12]=rk[4]^...
+        ldr     r9,[r11,#-36]
+        eor     r7,r7,r4                        @ rk[13]=rk[5]^rk[12]
+        str     r4,[r11,#-16]
+        eor     r8,r8,r7                        @ rk[14]=rk[6]^rk[13]
+        str     r7,[r11,#-12]
+        eor     r9,r9,r8                        @ rk[15]=rk[7]^rk[14]
+        str     r8,[r11,#-8]
+        str     r9,[r11,#-4]
+        b       .L256_loop
+
+.Ldone: mov     r0,#0
+        ldmia   sp!,{r4-r12,lr}
+.Labrt: tst     lr,#1
+        moveq   pc,lr                   @ be binary compatible with V4, yet
+        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
+.size   private_AES_set_encrypt_key,.-private_AES_set_encrypt_key
+
+.global private_AES_set_decrypt_key
+.type   private_AES_set_decrypt_key,%function
+.align  5
+private_AES_set_decrypt_key:
+        str     lr,[sp,#-4]!            @ push lr
+#if 0
+        @ kernel does both of these in setkey so optimise this bit out by
+        @ expecting the key to already have the enc_key work done (see aes_glue.c)
+        bl      _armv4_AES_set_encrypt_key
+#else
+        mov     r0,#0
+#endif
+        teq     r0,#0
+        ldrne   lr,[sp],#4              @ pop lr
+        bne     .Labrt
+
+        stmdb   sp!,{r4-r12}
+
+        ldr     r12,[r2,#240]   @ AES_set_encrypt_key preserves r2,
+        mov     r11,r2                  @ which is AES_KEY *key
+        mov     r7,r2
+        add     r8,r2,r12,lsl#4
+
+.Linv:  ldr     r0,[r7]
+        ldr     r1,[r7,#4]
+        ldr     r2,[r7,#8]
+        ldr     r3,[r7,#12]
+        ldr     r4,[r8]
+        ldr     r5,[r8,#4]
+        ldr     r6,[r8,#8]
+        ldr     r9,[r8,#12]
+        str     r0,[r8],#-16
+        str     r1,[r8,#16+4]
+        str     r2,[r8,#16+8]
+        str     r3,[r8,#16+12]
+        str     r4,[r7],#16
+        str     r5,[r7,#-12]
+        str     r6,[r7,#-8]
+        str     r9,[r7,#-4]
+        teq     r7,r8
+        bne     .Linv
+        ldr     r0,[r11,#16]!           @ prefetch tp1
+        mov     r7,#0x80
+        mov     r8,#0x1b
+        orr     r7,r7,#0x8000
+        orr     r8,r8,#0x1b00
+        orr     r7,r7,r7,lsl#16
+        orr     r8,r8,r8,lsl#16
+        sub     r12,r12,#1
+        mvn     r9,r7
+        mov     r12,r12,lsl#2   @ (rounds-1)*4
+
+.Lmix:  and     r4,r0,r7
+        and     r1,r0,r9
+        sub     r4,r4,r4,lsr#7
+        and     r4,r4,r8
+        eor     r1,r4,r1,lsl#1  @ tp2
+
+        and     r4,r1,r7
+        and     r2,r1,r9
+        sub     r4,r4,r4,lsr#7
+        and     r4,r4,r8
+        eor     r2,r4,r2,lsl#1  @ tp4
+
+        and     r4,r2,r7
+        and     r3,r2,r9
+        sub     r4,r4,r4,lsr#7
+        and     r4,r4,r8
+        eor     r3,r4,r3,lsl#1  @ tp8
+
+        eor     r4,r1,r2
+        eor     r5,r0,r3                @ tp9
+        eor     r4,r4,r3                @ tpe
+        eor     r4,r4,r1,ror#24
+        eor     r4,r4,r5,ror#24 @ ^= ROTATE(tpb=tp9^tp2,8)
+        eor     r4,r4,r2,ror#16
+        eor     r4,r4,r5,ror#16 @ ^= ROTATE(tpd=tp9^tp4,16)
+        eor     r4,r4,r5,ror#8  @ ^= ROTATE(tp9,24)
+
+        ldr     r0,[r11,#4]             @ prefetch tp1
+        str     r4,[r11],#4
+        subs    r12,r12,#1
+        bne     .Lmix
+
+        mov     r0,#0
+#if __ARM_ARCH__>=5
+        ldmia   sp!,{r4-r12,pc}
+#else
+        ldmia   sp!,{r4-r12,lr}
+        tst     lr,#1
+        moveq   pc,lr                   @ be binary compatible with V4, yet
+        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
+#endif
+.size   private_AES_set_decrypt_key,.-private_AES_set_decrypt_key
+
+.type   AES_Td,%object
+.align  5
+AES_Td:
+.word   0x51f4a750, 0x7e416553, 0x1a17a4c3, 0x3a275e96
+.word   0x3bab6bcb, 0x1f9d45f1, 0xacfa58ab, 0x4be30393
+.word   0x2030fa55, 0xad766df6, 0x88cc7691, 0xf5024c25
+.word   0x4fe5d7fc, 0xc52acbd7, 0x26354480, 0xb562a38f
+.word   0xdeb15a49, 0x25ba1b67, 0x45ea0e98, 0x5dfec0e1
+.word   0xc32f7502, 0x814cf012, 0x8d4697a3, 0x6bd3f9c6
+.word   0x038f5fe7, 0x15929c95, 0xbf6d7aeb, 0x955259da
+.word   0xd4be832d, 0x587421d3, 0x49e06929, 0x8ec9c844
+.word   0x75c2896a, 0xf48e7978, 0x99583e6b, 0x27b971dd
+.word   0xbee14fb6, 0xf088ad17, 0xc920ac66, 0x7dce3ab4
+.word   0x63df4a18, 0xe51a3182, 0x97513360, 0x62537f45
+.word   0xb16477e0, 0xbb6bae84, 0xfe81a01c, 0xf9082b94
+.word   0x70486858, 0x8f45fd19, 0x94de6c87, 0x527bf8b7
+.word   0xab73d323, 0x724b02e2, 0xe31f8f57, 0x6655ab2a
+.word   0xb2eb2807, 0x2fb5c203, 0x86c57b9a, 0xd33708a5
+.word   0x302887f2, 0x23bfa5b2, 0x02036aba, 0xed16825c
+.word   0x8acf1c2b, 0xa779b492, 0xf307f2f0, 0x4e69e2a1
+.word   0x65daf4cd, 0x0605bed5, 0xd134621f, 0xc4a6fe8a
+.word   0x342e539d, 0xa2f355a0, 0x058ae132, 0xa4f6eb75
+.word   0x0b83ec39, 0x4060efaa, 0x5e719f06, 0xbd6e1051
+.word   0x3e218af9, 0x96dd063d, 0xdd3e05ae, 0x4de6bd46
+.word   0x91548db5, 0x71c45d05, 0x0406d46f, 0x605015ff
+.word   0x1998fb24, 0xd6bde997, 0x894043cc, 0x67d99e77
+.word   0xb0e842bd, 0x07898b88, 0xe7195b38, 0x79c8eedb
+.word   0xa17c0a47, 0x7c420fe9, 0xf8841ec9, 0x00000000
+.word   0x09808683, 0x322bed48, 0x1e1170ac, 0x6c5a724e
+.word   0xfd0efffb, 0x0f853856, 0x3daed51e, 0x362d3927
+.word   0x0a0fd964, 0x685ca621, 0x9b5b54d1, 0x24362e3a
+.word   0x0c0a67b1, 0x9357e70f, 0xb4ee96d2, 0x1b9b919e
+.word   0x80c0c54f, 0x61dc20a2, 0x5a774b69, 0x1c121a16
+.word   0xe293ba0a, 0xc0a02ae5, 0x3c22e043, 0x121b171d
+.word   0x0e090d0b, 0xf28bc7ad, 0x2db6a8b9, 0x141ea9c8
+.word   0x57f11985, 0xaf75074c, 0xee99ddbb, 0xa37f60fd
+.word   0xf701269f, 0x5c72f5bc, 0x44663bc5, 0x5bfb7e34
+.word   0x8b432976, 0xcb23c6dc, 0xb6edfc68, 0xb8e4f163
+.word   0xd731dcca, 0x42638510, 0x13972240, 0x84c61120
+.word   0x854a247d, 0xd2bb3df8, 0xaef93211, 0xc729a16d
+.word   0x1d9e2f4b, 0xdcb230f3, 0x0d8652ec, 0x77c1e3d0
+.word   0x2bb3166c, 0xa970b999, 0x119448fa, 0x47e96422
+.word   0xa8fc8cc4, 0xa0f03f1a, 0x567d2cd8, 0x223390ef
+.word   0x87494ec7, 0xd938d1c1, 0x8ccaa2fe, 0x98d40b36
+.word   0xa6f581cf, 0xa57ade28, 0xdab78e26, 0x3fadbfa4
+.word   0x2c3a9de4, 0x5078920d, 0x6a5fcc9b, 0x547e4662
+.word   0xf68d13c2, 0x90d8b8e8, 0x2e39f75e, 0x82c3aff5
+.word   0x9f5d80be, 0x69d0937c, 0x6fd52da9, 0xcf2512b3
+.word   0xc8ac993b, 0x10187da7, 0xe89c636e, 0xdb3bbb7b
+.word   0xcd267809, 0x6e5918f4, 0xec9ab701, 0x834f9aa8
+.word   0xe6956e65, 0xaaffe67e, 0x21bccf08, 0xef15e8e6
+.word   0xbae79bd9, 0x4a6f36ce, 0xea9f09d4, 0x29b07cd6
+.word   0x31a4b2af, 0x2a3f2331, 0xc6a59430, 0x35a266c0
+.word   0x744ebc37, 0xfc82caa6, 0xe090d0b0, 0x33a7d815
+.word   0xf104984a, 0x41ecdaf7, 0x7fcd500e, 0x1791f62f
+.word   0x764dd68d, 0x43efb04d, 0xccaa4d54, 0xe49604df
+.word   0x9ed1b5e3, 0x4c6a881b, 0xc12c1fb8, 0x4665517f
+.word   0x9d5eea04, 0x018c355d, 0xfa877473, 0xfb0b412e
+.word   0xb3671d5a, 0x92dbd252, 0xe9105633, 0x6dd64713
+.word   0x9ad7618c, 0x37a10c7a, 0x59f8148e, 0xeb133c89
+.word   0xcea927ee, 0xb761c935, 0xe11ce5ed, 0x7a47b13c
+.word   0x9cd2df59, 0x55f2733f, 0x1814ce79, 0x73c737bf
+.word   0x53f7cdea, 0x5ffdaa5b, 0xdf3d6f14, 0x7844db86
+.word   0xcaaff381, 0xb968c43e, 0x3824342c, 0xc2a3405f
+.word   0x161dc372, 0xbce2250c, 0x283c498b, 0xff0d9541
+.word   0x39a80171, 0x080cb3de, 0xd8b4e49c, 0x6456c190
+.word   0x7bcb8461, 0xd532b670, 0x486c5c74, 0xd0b85742
+@ Td4[256]
+.byte   0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38
+.byte   0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb
+.byte   0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87
+.byte   0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb
+.byte   0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d
+.byte   0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e
+.byte   0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2
+.byte   0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25
+.byte   0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16
+.byte   0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92
+.byte   0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda
+.byte   0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84
+.byte   0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a
+.byte   0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06
+.byte   0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02
+.byte   0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b
+.byte   0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea
+.byte   0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73
+.byte   0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85
+.byte   0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e
+.byte   0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89
+.byte   0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b
+.byte   0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20
+.byte   0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4
+.byte   0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31
+.byte   0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f
+.byte   0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d
+.byte   0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef
+.byte   0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0
+.byte   0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61
+.byte   0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26
+.byte   0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
+.size   AES_Td,.-AES_Td
+
+@ void AES_decrypt(const unsigned char *in, unsigned char *out,
+@                const AES_KEY *key) {
+.global AES_decrypt
+.type   AES_decrypt,%function
+.align  5
+AES_decrypt:
+        sub     r3,pc,#8                @ AES_decrypt
+        stmdb   sp!,{r1,r4-r12,lr}
+        mov     r12,r0          @ inp
+        mov     r11,r2
+        sub     r10,r3,#AES_decrypt-AES_Td              @ Td
+#if __ARM_ARCH__<7
+        ldrb    r0,[r12,#3]     @ load input data in endian-neutral
+        ldrb    r4,[r12,#2]     @ manner...
+        ldrb    r5,[r12,#1]
+        ldrb    r6,[r12,#0]
+        orr     r0,r0,r4,lsl#8
+        ldrb    r1,[r12,#7]
+        orr     r0,r0,r5,lsl#16
+        ldrb    r4,[r12,#6]
+        orr     r0,r0,r6,lsl#24
+        ldrb    r5,[r12,#5]
+        ldrb    r6,[r12,#4]
+        orr     r1,r1,r4,lsl#8
+        ldrb    r2,[r12,#11]
+        orr     r1,r1,r5,lsl#16
+        ldrb    r4,[r12,#10]
+        orr     r1,r1,r6,lsl#24
+        ldrb    r5,[r12,#9]
+        ldrb    r6,[r12,#8]
+        orr     r2,r2,r4,lsl#8
+        ldrb    r3,[r12,#15]
+        orr     r2,r2,r5,lsl#16
+        ldrb    r4,[r12,#14]
+        orr     r2,r2,r6,lsl#24
+        ldrb    r5,[r12,#13]
+        ldrb    r6,[r12,#12]
+        orr     r3,r3,r4,lsl#8
+        orr     r3,r3,r5,lsl#16
+        orr     r3,r3,r6,lsl#24
+#else
+        ldr     r0,[r12,#0]
+        ldr     r1,[r12,#4]
+        ldr     r2,[r12,#8]
+        ldr     r3,[r12,#12]
+#ifdef __ARMEL__
+        rev     r0,r0
+        rev     r1,r1
+        rev     r2,r2
+        rev     r3,r3
+#endif
+#endif
+        bl      _armv4_AES_decrypt
+
+        ldr     r12,[sp],#4             @ pop out
+#if __ARM_ARCH__>=7
+#ifdef __ARMEL__
+        rev     r0,r0
+        rev     r1,r1
+        rev     r2,r2
+        rev     r3,r3
+#endif
+        str     r0,[r12,#0]
+        str     r1,[r12,#4]
+        str     r2,[r12,#8]
+        str     r3,[r12,#12]
+#else
+        mov     r4,r0,lsr#24            @ write output in endian-neutral
+        mov     r5,r0,lsr#16            @ manner...
+        mov     r6,r0,lsr#8
+        strb    r4,[r12,#0]
+        strb    r5,[r12,#1]
+        mov     r4,r1,lsr#24
+        strb    r6,[r12,#2]
+        mov     r5,r1,lsr#16
+        strb    r0,[r12,#3]
+        mov     r6,r1,lsr#8
+        strb    r4,[r12,#4]
+        strb    r5,[r12,#5]
+        mov     r4,r2,lsr#24
+        strb    r6,[r12,#6]
+        mov     r5,r2,lsr#16
+        strb    r1,[r12,#7]
+        mov     r6,r2,lsr#8
+        strb    r4,[r12,#8]
+        strb    r5,[r12,#9]
+        mov     r4,r3,lsr#24
+        strb    r6,[r12,#10]
+        mov     r5,r3,lsr#16
+        strb    r2,[r12,#11]
+        mov     r6,r3,lsr#8
+        strb    r4,[r12,#12]
+        strb    r5,[r12,#13]
+        strb    r6,[r12,#14]
+        strb    r3,[r12,#15]
+#endif
+#if __ARM_ARCH__>=5
+        ldmia   sp!,{r4-r12,pc}
+#else
+        ldmia   sp!,{r4-r12,lr}
+        tst     lr,#1
+        moveq   pc,lr                   @ be binary compatible with V4, yet
+        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
+#endif
+.size   AES_decrypt,.-AES_decrypt
+
+.type   _armv4_AES_decrypt,%function
+.align  2
+_armv4_AES_decrypt:
+        str     lr,[sp,#-4]!            @ push lr
+        ldmia   r11!,{r4-r7}
+        eor     r0,r0,r4
+        ldr     r12,[r11,#240-16]
+        eor     r1,r1,r5
+        eor     r2,r2,r6
+        eor     r3,r3,r7
+        sub     r12,r12,#1
+        mov     lr,#255
+
+        and     r7,lr,r0,lsr#16
+        and     r8,lr,r0,lsr#8
+        and     r9,lr,r0
+        mov     r0,r0,lsr#24
+.Ldec_loop:
+        ldr     r4,[r10,r7,lsl#2]       @ Td1[s0>>16]
+        and     r7,lr,r1                @ i0
+        ldr     r5,[r10,r8,lsl#2]       @ Td2[s0>>8]
+        and     r8,lr,r1,lsr#16
+        ldr     r6,[r10,r9,lsl#2]       @ Td3[s0>>0]
+        and     r9,lr,r1,lsr#8
+        ldr     r0,[r10,r0,lsl#2]       @ Td0[s0>>24]
+        mov     r1,r1,lsr#24
+
+        ldr     r7,[r10,r7,lsl#2]       @ Td3[s1>>0]
+        ldr     r8,[r10,r8,lsl#2]       @ Td1[s1>>16]
+        ldr     r9,[r10,r9,lsl#2]       @ Td2[s1>>8]
+        eor     r0,r0,r7,ror#24
+        ldr     r1,[r10,r1,lsl#2]       @ Td0[s1>>24]
+        and     r7,lr,r2,lsr#8  @ i0
+        eor     r5,r8,r5,ror#8
+        and     r8,lr,r2                @ i1
+        eor     r6,r9,r6,ror#8
+        and     r9,lr,r2,lsr#16
+        ldr     r7,[r10,r7,lsl#2]       @ Td2[s2>>8]
+        eor     r1,r1,r4,ror#8
+        ldr     r8,[r10,r8,lsl#2]       @ Td3[s2>>0]
+        mov     r2,r2,lsr#24
+
+        ldr     r9,[r10,r9,lsl#2]       @ Td1[s2>>16]
+        eor     r0,r0,r7,ror#16
+        ldr     r2,[r10,r2,lsl#2]       @ Td0[s2>>24]
+        and     r7,lr,r3,lsr#16 @ i0
+        eor     r1,r1,r8,ror#24
+        and     r8,lr,r3,lsr#8  @ i1
+        eor     r6,r9,r6,ror#8
+        and     r9,lr,r3                @ i2
+        ldr     r7,[r10,r7,lsl#2]       @ Td1[s3>>16]
+        eor     r2,r2,r5,ror#8
+        ldr     r8,[r10,r8,lsl#2]       @ Td2[s3>>8]
+        mov     r3,r3,lsr#24
+
+        ldr     r9,[r10,r9,lsl#2]       @ Td3[s3>>0]
+        eor     r0,r0,r7,ror#8
+        ldr     r7,[r11],#16
+        eor     r1,r1,r8,ror#16
+        ldr     r3,[r10,r3,lsl#2]       @ Td0[s3>>24]
+        eor     r2,r2,r9,ror#24
+
+        ldr     r4,[r11,#-12]
+        eor     r0,r0,r7
+        ldr     r5,[r11,#-8]
+        eor     r3,r3,r6,ror#8
+        ldr     r6,[r11,#-4]
+        and     r7,lr,r0,lsr#16
+        eor     r1,r1,r4
+        and     r8,lr,r0,lsr#8
+        eor     r2,r2,r5
+        and     r9,lr,r0
+        eor     r3,r3,r6
+        mov     r0,r0,lsr#24
+
+        subs    r12,r12,#1
+        bne     .Ldec_loop
+
+        add     r10,r10,#1024
+
+        ldr     r5,[r10,#0]             @ prefetch Td4
+        ldr     r6,[r10,#32]
+        ldr     r4,[r10,#64]
+        ldr     r5,[r10,#96]
+        ldr     r6,[r10,#128]
+        ldr     r4,[r10,#160]
+        ldr     r5,[r10,#192]
+        ldr     r6,[r10,#224]
+
+        ldrb    r0,[r10,r0]             @ Td4[s0>>24]
+        ldrb    r4,[r10,r7]             @ Td4[s0>>16]
+        and     r7,lr,r1                @ i0
+        ldrb    r5,[r10,r8]             @ Td4[s0>>8]
+        and     r8,lr,r1,lsr#16
+        ldrb    r6,[r10,r9]             @ Td4[s0>>0]
+        and     r9,lr,r1,lsr#8
+
+        ldrb    r7,[r10,r7]             @ Td4[s1>>0]
+        ldrb    r1,[r10,r1,lsr#24]      @ Td4[s1>>24]
+        ldrb    r8,[r10,r8]             @ Td4[s1>>16]
+        eor     r0,r7,r0,lsl#24
+        ldrb    r9,[r10,r9]             @ Td4[s1>>8]
+        eor     r1,r4,r1,lsl#8
+        and     r7,lr,r2,lsr#8  @ i0
+        eor     r5,r5,r8,lsl#8
+        and     r8,lr,r2                @ i1
+        ldrb    r7,[r10,r7]             @ Td4[s2>>8]
+        eor     r6,r6,r9,lsl#8
+        ldrb    r8,[r10,r8]             @ Td4[s2>>0]
+        and     r9,lr,r2,lsr#16
+
+        ldrb    r2,[r10,r2,lsr#24]      @ Td4[s2>>24]
+        eor     r0,r0,r7,lsl#8
+        ldrb    r9,[r10,r9]             @ Td4[s2>>16]
+        eor     r1,r8,r1,lsl#16
+        and     r7,lr,r3,lsr#16 @ i0
+        eor     r2,r5,r2,lsl#16
+        and     r8,lr,r3,lsr#8  @ i1
+        ldrb    r7,[r10,r7]             @ Td4[s3>>16]
+        eor     r6,r6,r9,lsl#16
+        ldrb    r8,[r10,r8]             @ Td4[s3>>8]
+        and     r9,lr,r3                @ i2
+
+        ldrb    r9,[r10,r9]             @ Td4[s3>>0]
+        ldrb    r3,[r10,r3,lsr#24]      @ Td4[s3>>24]
+        eor     r0,r0,r7,lsl#16
+        ldr     r7,[r11,#0]
+        eor     r1,r1,r8,lsl#8
+        ldr     r4,[r11,#4]
+        eor     r2,r9,r2,lsl#8
+        ldr     r5,[r11,#8]
+        eor     r3,r6,r3,lsl#24
+        ldr     r6,[r11,#12]
+
+        eor     r0,r0,r7
+        eor     r1,r1,r4
+        eor     r2,r2,r5
+        eor     r3,r3,r6
+
+        sub     r10,r10,#1024
+        ldr     pc,[sp],#4              @ pop and return
+.size   _armv4_AES_decrypt,.-_armv4_AES_decrypt
+.asciz  "AES for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
+.align  2
diff --git a/arch/arm/crypto/aes_glue.c b/arch/arm/crypto/aes_glue.c
new file mode 100644
index 000000000000..59f7877ead6a
--- /dev/null
+++ b/arch/arm/crypto/aes_glue.c
@@ -0,0 +1,108 @@
+/*
+ * Glue Code for the asm optimized version of the AES Cipher Algorithm
+ */
+
+#include <linux/module.h>
+#include <linux/crypto.h>
+#include <crypto/aes.h>
+
+#define AES_MAXNR 14
+
+typedef struct {
+        unsigned int rd_key[4 *(AES_MAXNR + 1)];
+        int rounds;
+} AES_KEY;
+
+struct AES_CTX {
+        AES_KEY enc_key;
+        AES_KEY dec_key;
+};
+
+asmlinkage void AES_encrypt(const u8 *in, u8 *out, AES_KEY *ctx);
+asmlinkage void AES_decrypt(const u8 *in, u8 *out, AES_KEY *ctx);
+asmlinkage int private_AES_set_decrypt_key(const unsigned char *userKey, const int bits, AES_KEY *key);
+asmlinkage int private_AES_set_encrypt_key(const unsigned char *userKey, const int bits, AES_KEY *key);
+
+static void aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
+{
+        struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
+        AES_encrypt(src, dst, &ctx->enc_key);
+}
+
+static void aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
+{
+        struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
+        AES_decrypt(src, dst, &ctx->dec_key);
+}
+
+static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
+                unsigned int key_len)
+{
+        struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
+
+        switch (key_len) {
+        case AES_KEYSIZE_128:
+                key_len = 128;
+                break;
+        case AES_KEYSIZE_192:
+                key_len = 192;
+                break;
+        case AES_KEYSIZE_256:
+                key_len = 256;
+                break;
+        default:
+                tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+                return -EINVAL;
+        }
+
+        if (private_AES_set_encrypt_key(in_key, key_len, &ctx->enc_key) == -1) {
+                tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+                return -EINVAL;
+        }
+        /* private_AES_set_decrypt_key expects an encryption key as input */
+        ctx->dec_key = ctx->enc_key;
+        if (private_AES_set_decrypt_key(in_key, key_len, &ctx->dec_key) == -1) {
+                tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static struct crypto_alg aes_alg = {
+        .cra_name               = "aes",
+        .cra_driver_name        = "aes-asm",
+        .cra_priority           = 200,
+        .cra_flags              = CRYPTO_ALG_TYPE_CIPHER,
+        .cra_blocksize          = AES_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct AES_CTX),
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(aes_alg.cra_list),
+        .cra_u  = {
+                .cipher = {
+                        .cia_min_keysize        = AES_MIN_KEY_SIZE,
+                        .cia_max_keysize        = AES_MAX_KEY_SIZE,
+                        .cia_setkey                     = aes_set_key,
+                        .cia_encrypt            = aes_encrypt,
+                        .cia_decrypt            = aes_decrypt
+                }
+        }
+};
+
+static int __init aes_init(void)
+{
+        return crypto_register_alg(&aes_alg);
+}
+
+static void __exit aes_fini(void)
+{
+        crypto_unregister_alg(&aes_alg);
+}
+
+module_init(aes_init);
+module_exit(aes_fini);
+
+MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm (ASM)");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("aes");
+MODULE_ALIAS("aes-asm");
+MODULE_AUTHOR("David McCullough <ucdevel@gmail.com>");
diff --git a/arch/arm/crypto/sha1-armv4-large.S b/arch/arm/crypto/sha1-armv4-large.S
new file mode 100644
index 000000000000..7050ab133b9d
--- /dev/null
+++ b/arch/arm/crypto/sha1-armv4-large.S
@@ -0,0 +1,503 @@
+#define __ARM_ARCH__ __LINUX_ARM_ARCH__
+@ ====================================================================
+@ Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
+@ project. The module is, however, dual licensed under OpenSSL and
+@ CRYPTOGAMS licenses depending on where you obtain it. For further
+@ details see http://www.openssl.org/~appro/cryptogams/.
+@ ====================================================================
+
+@ sha1_block procedure for ARMv4.
+@
+@ January 2007.
+
+@ Size/performance trade-off
+@ ====================================================================
+@ impl          size in bytes   comp cycles[*]  measured performance
+@ ====================================================================
+@ thumb         304             3212            4420
+@ armv4-small   392/+29%        1958/+64%       2250/+96%
+@ armv4-compact 740/+89%        1552/+26%       1840/+22%
+@ armv4-large   1420/+92%       1307/+19%       1370/+34%[***]
+@ full unroll   ~5100/+260%     ~1260/+4%       ~1300/+5%
+@ ====================================================================
+@ thumb         = same as 'small' but in Thumb instructions[**] and
+@                 with recurring code in two private functions;
+@ small         = detached Xload/update, loops are folded;
+@ compact       = detached Xload/update, 5x unroll;
+@ large         = interleaved Xload/update, 5x unroll;
+@ full unroll   = interleaved Xload/update, full unroll, estimated[!];
+@
+@ [*]   Manually counted instructions in "grand" loop body. Measured
+@       performance is affected by prologue and epilogue overhead,
+@       i-cache availability, branch penalties, etc.
+@ [**]  While each Thumb instruction is twice smaller, they are not as
+@       diverse as ARM ones: e.g., there are only two arithmetic
+@       instructions with 3 arguments, no [fixed] rotate, addressing
+@       modes are limited. As result it takes more instructions to do
+@       the same job in Thumb, therefore the code is never twice as
+@       small and always slower.
+@ [***] which is also ~35% better than compiler generated code. Dual-
+@       issue Cortex A8 core was measured to process input block in
+@       ~990 cycles.
+
+@ August 2010.
+@
+@ Rescheduling for dual-issue pipeline resulted in 13% improvement on
+@ Cortex A8 core and in absolute terms ~870 cycles per input block
+@ [or 13.6 cycles per byte].
+
+@ February 2011.
+@
+@ Profiler-assisted and platform-specific optimization resulted in 10%
+@ improvement on Cortex A8 core and 12.2 cycles per byte.
+
+.text
+
+.global sha1_block_data_order
+.type   sha1_block_data_order,%function
+
+.align  2
+sha1_block_data_order:
+        stmdb   sp!,{r4-r12,lr}
+        add     r2,r1,r2,lsl#6  @ r2 to point at the end of r1
+        ldmia   r0,{r3,r4,r5,r6,r7}
+.Lloop:
+        ldr     r8,.LK_00_19
+        mov     r14,sp
+        sub     sp,sp,#15*4
+        mov     r5,r5,ror#30
+        mov     r6,r6,ror#30
+        mov     r7,r7,ror#30            @ [6]
+.L_00_15:
+#if __ARM_ARCH__<7
+        ldrb    r10,[r1,#2]
+        ldrb    r9,[r1,#3]
+        ldrb    r11,[r1,#1]
+        add     r7,r8,r7,ror#2                  @ E+=K_00_19
+        ldrb    r12,[r1],#4
+        orr     r9,r9,r10,lsl#8
+        eor     r10,r5,r6                       @ F_xx_xx
+        orr     r9,r9,r11,lsl#16
+        add     r7,r7,r3,ror#27                 @ E+=ROR(A,27)
+        orr     r9,r9,r12,lsl#24
+#else
+        ldr     r9,[r1],#4                      @ handles unaligned
+        add     r7,r8,r7,ror#2                  @ E+=K_00_19
+        eor     r10,r5,r6                       @ F_xx_xx
+        add     r7,r7,r3,ror#27                 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+        rev     r9,r9                           @ byte swap
+#endif
+#endif
+        and     r10,r4,r10,ror#2
+        add     r7,r7,r9                        @ E+=X[i]
+        eor     r10,r10,r6,ror#2                @ F_00_19(B,C,D)
+        str     r9,[r14,#-4]!
+        add     r7,r7,r10                       @ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+        ldrb    r10,[r1,#2]
+        ldrb    r9,[r1,#3]
+        ldrb    r11,[r1,#1]
+        add     r6,r8,r6,ror#2                  @ E+=K_00_19
+        ldrb    r12,[r1],#4
+        orr     r9,r9,r10,lsl#8
+        eor     r10,r4,r5                       @ F_xx_xx
+        orr     r9,r9,r11,lsl#16
+        add     r6,r6,r7,ror#27                 @ E+=ROR(A,27)
+        orr     r9,r9,r12,lsl#24
+#else
+        ldr     r9,[r1],#4                      @ handles unaligned
+        add     r6,r8,r6,ror#2                  @ E+=K_00_19
+        eor     r10,r4,r5                       @ F_xx_xx
+        add     r6,r6,r7,ror#27                 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+        rev     r9,r9                           @ byte swap
+#endif
+#endif
+        and     r10,r3,r10,ror#2
+        add     r6,r6,r9                        @ E+=X[i]
+        eor     r10,r10,r5,ror#2                @ F_00_19(B,C,D)
+        str     r9,[r14,#-4]!
+        add     r6,r6,r10                       @ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+        ldrb    r10,[r1,#2]
+        ldrb    r9,[r1,#3]
+        ldrb    r11,[r1,#1]
+        add     r5,r8,r5,ror#2                  @ E+=K_00_19
+        ldrb    r12,[r1],#4
+        orr     r9,r9,r10,lsl#8
+        eor     r10,r3,r4                       @ F_xx_xx
+        orr     r9,r9,r11,lsl#16
+        add     r5,r5,r6,ror#27                 @ E+=ROR(A,27)
+        orr     r9,r9,r12,lsl#24
+#else
+        ldr     r9,[r1],#4                      @ handles unaligned
+        add     r5,r8,r5,ror#2                  @ E+=K_00_19
+        eor     r10,r3,r4                       @ F_xx_xx
+        add     r5,r5,r6,ror#27                 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+        rev     r9,r9                           @ byte swap
+#endif
+#endif
+        and     r10,r7,r10,ror#2
+        add     r5,r5,r9                        @ E+=X[i]
+        eor     r10,r10,r4,ror#2                @ F_00_19(B,C,D)
+        str     r9,[r14,#-4]!
+        add     r5,r5,r10                       @ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+        ldrb    r10,[r1,#2]
+        ldrb    r9,[r1,#3]
+        ldrb    r11,[r1,#1]
+        add     r4,r8,r4,ror#2                  @ E+=K_00_19
+        ldrb    r12,[r1],#4
+        orr     r9,r9,r10,lsl#8
+        eor     r10,r7,r3                       @ F_xx_xx
+        orr     r9,r9,r11,lsl#16
+        add     r4,r4,r5,ror#27                 @ E+=ROR(A,27)
+        orr     r9,r9,r12,lsl#24
+#else
+        ldr     r9,[r1],#4                      @ handles unaligned
+        add     r4,r8,r4,ror#2                  @ E+=K_00_19
+        eor     r10,r7,r3                       @ F_xx_xx
+        add     r4,r4,r5,ror#27                 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+        rev     r9,r9                           @ byte swap
+#endif
+#endif
+        and     r10,r6,r10,ror#2
+        add     r4,r4,r9                        @ E+=X[i]
+        eor     r10,r10,r3,ror#2                @ F_00_19(B,C,D)
+        str     r9,[r14,#-4]!
+        add     r4,r4,r10                       @ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+        ldrb    r10,[r1,#2]
+        ldrb    r9,[r1,#3]
+        ldrb    r11,[r1,#1]
+        add     r3,r8,r3,ror#2                  @ E+=K_00_19
+        ldrb    r12,[r1],#4
+        orr     r9,r9,r10,lsl#8
+        eor     r10,r6,r7                       @ F_xx_xx
+        orr     r9,r9,r11,lsl#16
+        add     r3,r3,r4,ror#27                 @ E+=ROR(A,27)
+        orr     r9,r9,r12,lsl#24
+#else
+        ldr     r9,[r1],#4                      @ handles unaligned
+        add     r3,r8,r3,ror#2                  @ E+=K_00_19
+        eor     r10,r6,r7                       @ F_xx_xx
+        add     r3,r3,r4,ror#27                 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+        rev     r9,r9                           @ byte swap
+#endif
+#endif
+        and     r10,r5,r10,ror#2
+        add     r3,r3,r9                        @ E+=X[i]
+        eor     r10,r10,r7,ror#2                @ F_00_19(B,C,D)
+        str     r9,[r14,#-4]!
+        add     r3,r3,r10                       @ E+=F_00_19(B,C,D)
+        teq     r14,sp
+        bne     .L_00_15                @ [((11+4)*5+2)*3]
+#if __ARM_ARCH__<7
+        ldrb    r10,[r1,#2]
+        ldrb    r9,[r1,#3]
+        ldrb    r11,[r1,#1]
+        add     r7,r8,r7,ror#2                  @ E+=K_00_19
+        ldrb    r12,[r1],#4
+        orr     r9,r9,r10,lsl#8
+        eor     r10,r5,r6                       @ F_xx_xx
+        orr     r9,r9,r11,lsl#16
+        add     r7,r7,r3,ror#27                 @ E+=ROR(A,27)
+        orr     r9,r9,r12,lsl#24
+#else
+        ldr     r9,[r1],#4                      @ handles unaligned
+        add     r7,r8,r7,ror#2                  @ E+=K_00_19
+        eor     r10,r5,r6                       @ F_xx_xx
+        add     r7,r7,r3,ror#27                 @ E+=ROR(A,27)
+#ifdef __ARMEL__
+        rev     r9,r9                           @ byte swap
+#endif
+#endif
+        and     r10,r4,r10,ror#2
+        add     r7,r7,r9                        @ E+=X[i]
+        eor     r10,r10,r6,ror#2                @ F_00_19(B,C,D)
+        str     r9,[r14,#-4]!
+        add     r7,r7,r10                       @ E+=F_00_19(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r6,r8,r6,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r4,r5                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r6,r6,r7,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r3,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r6,r6,r9                        @ E+=X[i]
+        eor     r10,r10,r5,ror#2                @ F_00_19(B,C,D)
+        add     r6,r6,r10                       @ E+=F_00_19(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r5,r8,r5,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r3,r4                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r5,r5,r6,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r7,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r5,r5,r9                        @ E+=X[i]
+        eor     r10,r10,r4,ror#2                @ F_00_19(B,C,D)
+        add     r5,r5,r10                       @ E+=F_00_19(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r4,r8,r4,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r7,r3                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r4,r4,r5,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r6,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r4,r4,r9                        @ E+=X[i]
+        eor     r10,r10,r3,ror#2                @ F_00_19(B,C,D)
+        add     r4,r4,r10                       @ E+=F_00_19(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r3,r8,r3,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r6,r7                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r3,r3,r4,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r5,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r3,r3,r9                        @ E+=X[i]
+        eor     r10,r10,r7,ror#2                @ F_00_19(B,C,D)
+        add     r3,r3,r10                       @ E+=F_00_19(B,C,D)
+
+        ldr     r8,.LK_20_39            @ [+15+16*4]
+        sub     sp,sp,#25*4
+        cmn     sp,#0                   @ [+3], clear carry to denote 20_39
+.L_20_39_or_60_79:
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r7,r8,r7,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r5,r6                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r7,r7,r3,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        eor r10,r4,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r7,r7,r9                        @ E+=X[i]
+        add     r7,r7,r10                       @ E+=F_20_39(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r6,r8,r6,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r4,r5                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r6,r6,r7,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        eor r10,r3,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r6,r6,r9                        @ E+=X[i]
+        add     r6,r6,r10                       @ E+=F_20_39(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r5,r8,r5,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r3,r4                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r5,r5,r6,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        eor r10,r7,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r5,r5,r9                        @ E+=X[i]
+        add     r5,r5,r10                       @ E+=F_20_39(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r4,r8,r4,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r7,r3                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r4,r4,r5,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        eor r10,r6,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r4,r4,r9                        @ E+=X[i]
+        add     r4,r4,r10                       @ E+=F_20_39(B,C,D)
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r3,r8,r3,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r6,r7                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r3,r3,r4,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        eor r10,r5,r10,ror#2                                    @ F_xx_xx
+                                                @ F_xx_xx
+        add     r3,r3,r9                        @ E+=X[i]
+        add     r3,r3,r10                       @ E+=F_20_39(B,C,D)
+        teq     r14,sp                  @ preserve carry
+        bne     .L_20_39_or_60_79       @ [+((12+3)*5+2)*4]
+        bcs     .L_done                 @ [+((12+3)*5+2)*4], spare 300 bytes
+
+        ldr     r8,.LK_40_59
+        sub     sp,sp,#20*4             @ [+2]
+.L_40_59:
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r7,r8,r7,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r5,r6                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r7,r7,r3,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r4,r10,ror#2                                    @ F_xx_xx
+        and r11,r5,r6                                   @ F_xx_xx
+        add     r7,r7,r9                        @ E+=X[i]
+        add     r7,r7,r10                       @ E+=F_40_59(B,C,D)
+        add     r7,r7,r11,ror#2
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r6,r8,r6,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r4,r5                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r6,r6,r7,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r3,r10,ror#2                                    @ F_xx_xx
+        and r11,r4,r5                                   @ F_xx_xx
+        add     r6,r6,r9                        @ E+=X[i]
+        add     r6,r6,r10                       @ E+=F_40_59(B,C,D)
+        add     r6,r6,r11,ror#2
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r5,r8,r5,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r3,r4                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r5,r5,r6,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r7,r10,ror#2                                    @ F_xx_xx
+        and r11,r3,r4                                   @ F_xx_xx
+        add     r5,r5,r9                        @ E+=X[i]
+        add     r5,r5,r10                       @ E+=F_40_59(B,C,D)
+        add     r5,r5,r11,ror#2
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r4,r8,r4,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r7,r3                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r4,r4,r5,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r6,r10,ror#2                                    @ F_xx_xx
+        and r11,r7,r3                                   @ F_xx_xx
+        add     r4,r4,r9                        @ E+=X[i]
+        add     r4,r4,r10                       @ E+=F_40_59(B,C,D)
+        add     r4,r4,r11,ror#2
+        ldr     r9,[r14,#15*4]
+        ldr     r10,[r14,#13*4]
+        ldr     r11,[r14,#7*4]
+        add     r3,r8,r3,ror#2                  @ E+=K_xx_xx
+        ldr     r12,[r14,#2*4]
+        eor     r9,r9,r10
+        eor     r11,r11,r12                     @ 1 cycle stall
+        eor     r10,r6,r7                       @ F_xx_xx
+        mov     r9,r9,ror#31
+        add     r3,r3,r4,ror#27                 @ E+=ROR(A,27)
+        eor     r9,r9,r11,ror#31
+        str     r9,[r14,#-4]!
+        and r10,r5,r10,ror#2                                    @ F_xx_xx
+        and r11,r6,r7                                   @ F_xx_xx
+        add     r3,r3,r9                        @ E+=X[i]
+        add     r3,r3,r10                       @ E+=F_40_59(B,C,D)
+        add     r3,r3,r11,ror#2
+        teq     r14,sp
+        bne     .L_40_59                @ [+((12+5)*5+2)*4]
+
+        ldr     r8,.LK_60_79
+        sub     sp,sp,#20*4
+        cmp     sp,#0                   @ set carry to denote 60_79
+        b       .L_20_39_or_60_79       @ [+4], spare 300 bytes
+.L_done:
+        add     sp,sp,#80*4             @ "deallocate" stack frame
+        ldmia   r0,{r8,r9,r10,r11,r12}
+        add     r3,r8,r3
+        add     r4,r9,r4
+        add     r5,r10,r5,ror#2
+        add     r6,r11,r6,ror#2
+        add     r7,r12,r7,ror#2
+        stmia   r0,{r3,r4,r5,r6,r7}
+        teq     r1,r2
+        bne     .Lloop                  @ [+18], total 1307
+
+#if __ARM_ARCH__>=5
+        ldmia   sp!,{r4-r12,pc}
+#else
+        ldmia   sp!,{r4-r12,lr}
+        tst     lr,#1
+        moveq   pc,lr                   @ be binary compatible with V4, yet
+        .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
+#endif
+.align  2
+.LK_00_19:      .word   0x5a827999
+.LK_20_39:      .word   0x6ed9eba1
+.LK_40_59:      .word   0x8f1bbcdc
+.LK_60_79:      .word   0xca62c1d6
+.size   sha1_block_data_order,.-sha1_block_data_order
+.asciz  "SHA1 block transform for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
+.align  2
diff --git a/arch/arm/crypto/sha1_glue.c b/arch/arm/crypto/sha1_glue.c
new file mode 100644
index 000000000000..76cd976230bc
--- /dev/null
+++ b/arch/arm/crypto/sha1_glue.c
@@ -0,0 +1,179 @@
+/*
+ * Cryptographic API.
+ * Glue code for the SHA1 Secure Hash Algorithm assembler implementation
+ *
+ * This file is based on sha1_generic.c and sha1_ssse3_glue.c
+ *
+ * Copyright (c) Alan Smithee.
+ * Copyright (c) Andrew McDonald <andrew@mcdonald.org.uk>
+ * Copyright (c) Jean-Francois Dive <jef@linuxbe.org>
+ * Copyright (c) Mathias Krause <minipli@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ */
+
+#include <crypto/internal/hash.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/cryptohash.h>
+#include <linux/types.h>
+#include <crypto/sha.h>
+#include <asm/byteorder.h>
+
+struct SHA1_CTX {
+        uint32_t h0,h1,h2,h3,h4;
+        u64 count;
+        u8 data[SHA1_BLOCK_SIZE];
+};
+
+asmlinkage void sha1_block_data_order(struct SHA1_CTX *digest,
+                const unsigned char *data, unsigned int rounds);
+
+
+static int sha1_init(struct shash_desc *desc)
+{
+        struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+        memset(sctx, 0, sizeof(*sctx));
+        sctx->h0 = SHA1_H0;
+        sctx->h1 = SHA1_H1;
+        sctx->h2 = SHA1_H2;
+        sctx->h3 = SHA1_H3;
+        sctx->h4 = SHA1_H4;
+        return 0;
+}
+
+
+static int __sha1_update(struct SHA1_CTX *sctx, const u8 *data,
+                               unsigned int len, unsigned int partial)
+{
+        unsigned int done = 0;
+
+        sctx->count += len;
+
+        if (partial) {
+                done = SHA1_BLOCK_SIZE - partial;
+                memcpy(sctx->data + partial, data, done);
+                sha1_block_data_order(sctx, sctx->data, 1);
+        }
+
+        if (len - done >= SHA1_BLOCK_SIZE) {
+                const unsigned int rounds = (len - done) / SHA1_BLOCK_SIZE;
+                sha1_block_data_order(sctx, data + done, rounds);
+                done += rounds * SHA1_BLOCK_SIZE;
+        }
+
+        memcpy(sctx->data, data + done, len - done);
+        return 0;
+}
+
+
+static int sha1_update(struct shash_desc *desc, const u8 *data,
+                             unsigned int len)
+{
+        struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+        unsigned int partial = sctx->count % SHA1_BLOCK_SIZE;
+        int res;
+
+        /* Handle the fast case right here */
+        if (partial + len < SHA1_BLOCK_SIZE) {
+                sctx->count += len;
+                memcpy(sctx->data + partial, data, len);
+                return 0;
+        }
+        res = __sha1_update(sctx, data, len, partial);
+        return res;
+}
+
+
+/* Add padding and return the message digest. */
+static int sha1_final(struct shash_desc *desc, u8 *out)
+{
+        struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+        unsigned int i, index, padlen;
+        __be32 *dst = (__be32 *)out;
+        __be64 bits;
+        static const u8 padding[SHA1_BLOCK_SIZE] = { 0x80, };
+
+        bits = cpu_to_be64(sctx->count << 3);
+
+        /* Pad out to 56 mod 64 and append length */
+        index = sctx->count % SHA1_BLOCK_SIZE;
+        padlen = (index < 56) ? (56 - index) : ((SHA1_BLOCK_SIZE+56) - index);
+        /* We need to fill a whole block for __sha1_update() */
+        if (padlen <= 56) {
+                sctx->count += padlen;
+                memcpy(sctx->data + index, padding, padlen);
+        } else {
+                __sha1_update(sctx, padding, padlen, index);
+        }
+        __sha1_update(sctx, (const u8 *)&bits, sizeof(bits), 56);
+
+        /* Store state in digest */
+        for (i = 0; i < 5; i++)
+                dst[i] = cpu_to_be32(((u32 *)sctx)[i]);
+
+        /* Wipe context */
+        memset(sctx, 0, sizeof(*sctx));
+        return 0;
+}
+
+
+static int sha1_export(struct shash_desc *desc, void *out)
+{
+        struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+        memcpy(out, sctx, sizeof(*sctx));
+        return 0;
+}
+
+
+static int sha1_import(struct shash_desc *desc, const void *in)
+{
+        struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+        memcpy(sctx, in, sizeof(*sctx));
+        return 0;
+}
+
+
+static struct shash_alg alg = {
+        .digestsize     =       SHA1_DIGEST_SIZE,
+        .init           =       sha1_init,
+        .update         =       sha1_update,
+        .final          =       sha1_final,
+        .export         =       sha1_export,
+        .import         =       sha1_import,
+        .descsize       =       sizeof(struct SHA1_CTX),
+        .statesize      =       sizeof(struct SHA1_CTX),
+        .base           =       {
+                .cra_name       =       "sha1",
+                .cra_driver_name=       "sha1-asm",
+                .cra_priority   =       150,
+                .cra_flags      =       CRYPTO_ALG_TYPE_SHASH,
+                .cra_blocksize  =       SHA1_BLOCK_SIZE,
+                .cra_module     =       THIS_MODULE,
+        }
+};
+
+
+static int __init sha1_mod_init(void)
+{
+        return crypto_register_shash(&alg);
+}
+
+
+static void __exit sha1_mod_fini(void)
+{
+        crypto_unregister_shash(&alg);
+}
+
+
+module_init(sha1_mod_init);
+module_exit(sha1_mod_fini);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm (ARM)");
+MODULE_ALIAS("sha1");
+MODULE_AUTHOR("David McCullough <ucdevel@gmail.com>");
diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
index 05112380dc53..8dcd9c702d90 100644
--- a/arch/arm/include/asm/barrier.h
+++ b/arch/arm/include/asm/barrier.h
@@ -44,10 +44,9 @@
 #define rmb()           dsb()
 #define wmb()           mb()
 #else
-#include <asm/memory.h>
-#define mb()    do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
-#define rmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
-#define wmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
+#define mb()            barrier()
+#define rmb()           barrier()
+#define wmb()           barrier()
 #endif
 
 #ifndef CONFIG_SMP
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 5c44dcb0987b..23004847bb05 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -13,6 +13,7 @@
 
 #define DMA_ERROR_CODE  (~0)
 extern struct dma_map_ops arm_dma_ops;
+extern struct dma_map_ops arm_coherent_dma_ops;
 
 static inline struct dma_map_ops *get_dma_ops(struct device *dev)
 {
diff --git a/arch/arm/include/asm/hypervisor.h b/arch/arm/include/asm/hypervisor.h
new file mode 100644
index 000000000000..b90d9e523d6f
--- /dev/null
+++ b/arch/arm/include/asm/hypervisor.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_ARM_HYPERVISOR_H
+#define _ASM_ARM_HYPERVISOR_H
+
+#include <asm/xen/hypervisor.h>
+
+#endif
diff --git a/arch/arm/include/asm/leds.h b/arch/arm/include/asm/leds.h
deleted file mode 100644
index c545739f39b7..000000000000
--- a/arch/arm/include/asm/leds.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- *  arch/arm/include/asm/leds.h
- *
- *  Copyright (C) 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Event-driven interface for LEDs on machines
- *  Added led_start and led_stop- Alex Holden, 28th Dec 1998.
- */
-#ifndef ASM_ARM_LEDS_H
-#define ASM_ARM_LEDS_H
-
-
-typedef enum {
-        led_idle_start,
-        led_idle_end,
-        led_timer,
-        led_start,
-        led_stop,
-        led_claim,              /* override idle & timer leds */
-        led_release,            /* restore idle & timer leds */
-        led_start_timer_mode,
-        led_stop_timer_mode,
-        led_green_on,
-        led_green_off,
-        led_amber_on,
-        led_amber_off,
-        led_red_on,
-        led_red_off,
-        led_blue_on,
-        led_blue_off,
-        /*
-         * I want this between led_timer and led_start, but
-         * someone has decided to export this to user space
-         */
-        led_halted
-} led_event_t;
-
-/* Use this routine to handle LEDs */
-
-#ifdef CONFIG_LEDS
-extern void (*leds_event)(led_event_t);
-#else
-#define leds_event(e)
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 5f6ddcc56452..73cf03aa981e 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -275,14 +275,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 #define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 #define virt_addr_valid(kaddr)  ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
 
-/*
- * Optional coherency support.  Currently used only by selected
- * Intel XSC3-based systems.
- */
-#ifndef arch_is_coherent
-#define arch_is_coherent()              0
-#endif
-
 #endif
 
 #include <asm-generic/memory_model.h>
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index ecf901902e44..812a4944e783 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -19,7 +19,7 @@
 
 #ifndef CONFIG_MMU
 
-#include "page-nommu.h"
+#include <asm/page-nommu.h>
 
 #else
 
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 41dc31f834c3..08c12312a1f9 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -16,7 +16,7 @@
 #ifndef CONFIG_MMU
 
 #include <asm-generic/4level-fixup.h>
-#include "pgtable-nommu.h"
+#include <asm/pgtable-nommu.h>
 
 #else
 
diff --git a/arch/arm/include/asm/sync_bitops.h b/arch/arm/include/asm/sync_bitops.h
new file mode 100644
index 000000000000..63479eecbf76
--- /dev/null
+++ b/arch/arm/include/asm/sync_bitops.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_SYNC_BITOPS_H__
+#define __ASM_SYNC_BITOPS_H__
+
+#include <asm/bitops.h>
+#include <asm/system.h>
+
+/* sync_bitops functions are equivalent to the SMP implementation of the
+ * original functions, independently from CONFIG_SMP being defined.
+ *
+ * We need them because _set_bit etc are not SMP safe if !CONFIG_SMP. But
+ * under Xen you might be communicating with a completely external entity
+ * who might be on another CPU (e.g. two uniprocessor guests communicating
+ * via event channels and grant tables). So we need a variant of the bit
+ * ops which are SMP safe even on a UP kernel.
+ */
+
+#define sync_set_bit(nr, p)             _set_bit(nr, p)
+#define sync_clear_bit(nr, p)           _clear_bit(nr, p)
+#define sync_change_bit(nr, p)          _change_bit(nr, p)
+#define sync_test_and_set_bit(nr, p)    _test_and_set_bit(nr, p)
+#define sync_test_and_clear_bit(nr, p)  _test_and_clear_bit(nr, p)
+#define sync_test_and_change_bit(nr, p) _test_and_change_bit(nr, p)
+#define sync_test_bit(nr, addr)         test_bit(nr, addr)
+#define sync_cmpxchg                    cmpxchg
+
+
+#endif
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 0cab47d4a83f..2fde5fd1acce 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -404,6 +404,7 @@
 #define __NR_setns                      (__NR_SYSCALL_BASE+375)
 #define __NR_process_vm_readv           (__NR_SYSCALL_BASE+376)
 #define __NR_process_vm_writev          (__NR_SYSCALL_BASE+377)
+                                        /* 378 for kcmp */
 
 /*
  * The following SWIs are ARM private.
@@ -483,6 +484,7 @@
  */
 #define __IGNORE_fadvise64_64
 #define __IGNORE_migrate_pages
+#define __IGNORE_kcmp
 
 #endif /* __KERNEL__ */
 #endif /* __ASM_ARM_UNISTD_H */
diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
index 3d5fc41ae8d3..a7aadbd9a6dd 100644
--- a/arch/arm/include/asm/vfpmacros.h
+++ b/arch/arm/include/asm/vfpmacros.h
@@ -5,7 +5,7 @@
  */
 #include <asm/hwcap.h>
 
-#include "vfp.h"
+#include <asm/vfp.h>
 
 @ Macros to allow building with old toolkits (with no VFP support)
         .macro  VFPFMRX, rd, sysreg, cond
diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h
new file mode 100644
index 000000000000..94b4e9020b02
--- /dev/null
+++ b/arch/arm/include/asm/xen/events.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_ARM_XEN_EVENTS_H
+#define _ASM_ARM_XEN_EVENTS_H
+
+#include <asm/ptrace.h>
+
+enum ipi_vector {
+        XEN_PLACEHOLDER_VECTOR,
+
+        /* Xen IPIs go here */
+        XEN_NR_IPIS,
+};
+
+static inline int xen_irqs_disabled(struct pt_regs *regs)
+{
+        return raw_irqs_disabled_flags(regs->ARM_cpsr);
+}
+
+#endif /* _ASM_ARM_XEN_EVENTS_H */
diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h
new file mode 100644
index 000000000000..8a823253d775
--- /dev/null
+++ b/arch/arm/include/asm/xen/hypercall.h
@@ -0,0 +1,69 @@
+/******************************************************************************
+ * hypercall.h
+ *
+ * Linux-specific hypervisor handling.
+ *
+ * Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef _ASM_ARM_XEN_HYPERCALL_H
+#define _ASM_ARM_XEN_HYPERCALL_H
+
+#include <xen/interface/xen.h>
+
+long privcmd_call(unsigned call, unsigned long a1,
+                unsigned long a2, unsigned long a3,
+                unsigned long a4, unsigned long a5);
+int HYPERVISOR_xen_version(int cmd, void *arg);
+int HYPERVISOR_console_io(int cmd, int count, char *str);
+int HYPERVISOR_grant_table_op(unsigned int cmd, void *uop, unsigned int count);
+int HYPERVISOR_sched_op(int cmd, void *arg);
+int HYPERVISOR_event_channel_op(int cmd, void *arg);
+unsigned long HYPERVISOR_hvm_op(int op, void *arg);
+int HYPERVISOR_memory_op(unsigned int cmd, void *arg);
+int HYPERVISOR_physdev_op(int cmd, void *arg);
+
+static inline void
+MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va,
+                        unsigned int new_val, unsigned long flags)
+{
+        BUG();
+}
+
+static inline void
+MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req,
+                 int count, int *success_count, domid_t domid)
+{
+        BUG();
+}
+
+static inline int
+HYPERVISOR_multicall(void *call_list, int nr_calls)
+{
+        BUG();
+}
+#endif /* _ASM_ARM_XEN_HYPERCALL_H */
diff --git a/arch/arm/include/asm/xen/hypervisor.h b/arch/arm/include/asm/xen/hypervisor.h
new file mode 100644
index 000000000000..d7ab99a0c9eb
--- /dev/null
+++ b/arch/arm/include/asm/xen/hypervisor.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_ARM_XEN_HYPERVISOR_H
+#define _ASM_ARM_XEN_HYPERVISOR_H
+
+extern struct shared_info *HYPERVISOR_shared_info;
+extern struct start_info *xen_start_info;
+
+/* Lazy mode for batching updates / context switch */
+enum paravirt_lazy_mode {
+        PARAVIRT_LAZY_NONE,
+        PARAVIRT_LAZY_MMU,
+        PARAVIRT_LAZY_CPU,
+};
+
+static inline enum paravirt_lazy_mode paravirt_get_lazy_mode(void)
+{
+        return PARAVIRT_LAZY_NONE;
+}
+
+#endif /* _ASM_ARM_XEN_HYPERVISOR_H */
diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
new file mode 100644
index 000000000000..ae05e56dd17d
--- /dev/null
+++ b/arch/arm/include/asm/xen/interface.h
@@ -0,0 +1,73 @@
+/******************************************************************************
+ * Guest OS interface to ARM Xen.
+ *
+ * Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012
+ */
+
+#ifndef _ASM_ARM_XEN_INTERFACE_H
+#define _ASM_ARM_XEN_INTERFACE_H
+
+#include <linux/types.h>
+
+#define uint64_aligned_t uint64_t __attribute__((aligned(8)))
+
+#define __DEFINE_GUEST_HANDLE(name, type) \
+        typedef struct { union { type *p; uint64_aligned_t q; }; }  \
+        __guest_handle_ ## name
+
+#define DEFINE_GUEST_HANDLE_STRUCT(name) \
+        __DEFINE_GUEST_HANDLE(name, struct name)
+#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name)
+#define GUEST_HANDLE(name)        __guest_handle_ ## name
+
+#define set_xen_guest_handle(hnd, val)                  \
+        do {                                            \
+                if (sizeof(hnd) == 8)                   \
+                        *(uint64_t *)&(hnd) = 0;        \
+                (hnd).p = val;                          \
+        } while (0)
+
+#ifndef __ASSEMBLY__
+/* Explicitly size integers that represent pfns in the interface with
+ * Xen so that we can have one ABI that works for 32 and 64 bit guests. */
+typedef uint64_t xen_pfn_t;
+typedef uint64_t xen_ulong_t;
+/* Guest handles for primitive C types. */
+__DEFINE_GUEST_HANDLE(uchar, unsigned char);
+__DEFINE_GUEST_HANDLE(uint,  unsigned int);
+__DEFINE_GUEST_HANDLE(ulong, unsigned long);
+DEFINE_GUEST_HANDLE(char);
+DEFINE_GUEST_HANDLE(int);
+DEFINE_GUEST_HANDLE(long);
+DEFINE_GUEST_HANDLE(void);
+DEFINE_GUEST_HANDLE(uint64_t);
+DEFINE_GUEST_HANDLE(uint32_t);
+DEFINE_GUEST_HANDLE(xen_pfn_t);
+
+/* Maximum number of virtual CPUs in multi-processor guests. */
+#define MAX_VIRT_CPUS 1
+
+struct arch_vcpu_info { };
+struct arch_shared_info { };
+
+/* TODO: Move pvclock definitions some place arch independent */
+struct pvclock_vcpu_time_info {
+        u32   version;
+        u32   pad0;
+        u64   tsc_timestamp;
+        u64   system_time;
+        u32   tsc_to_system_mul;
+        s8    tsc_shift;
+        u8    flags;
+        u8    pad[2];
+} __attribute__((__packed__)); /* 32 bytes */
+
+/* It is OK to have a 12 bytes struct with no padding because it is packed */
+struct pvclock_wall_clock {
+        u32   version;
+        u32   sec;
+        u32   nsec;
+} __attribute__((__packed__));
+#endif
+
+#endif /* _ASM_ARM_XEN_INTERFACE_H */
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
new file mode 100644
index 000000000000..174202318dff
--- /dev/null
+++ b/arch/arm/include/asm/xen/page.h
@@ -0,0 +1,82 @@
+#ifndef _ASM_ARM_XEN_PAGE_H
+#define _ASM_ARM_XEN_PAGE_H
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+#include <linux/pfn.h>
+#include <linux/types.h>
+
+#include <xen/interface/grant_table.h>
+
+#define pfn_to_mfn(pfn)                 (pfn)
+#define phys_to_machine_mapping_valid   (1)
+#define mfn_to_pfn(mfn)                 (mfn)
+#define mfn_to_virt(m)                  (__va(mfn_to_pfn(m) << PAGE_SHIFT))
+
+#define pte_mfn     pte_pfn
+#define mfn_pte     pfn_pte
+
+/* Xen machine address */
+typedef struct xmaddr {
+        phys_addr_t maddr;
+} xmaddr_t;
+
+/* Xen pseudo-physical address */
+typedef struct xpaddr {
+        phys_addr_t paddr;
+} xpaddr_t;
+
+#define XMADDR(x)       ((xmaddr_t) { .maddr = (x) })
+#define XPADDR(x)       ((xpaddr_t) { .paddr = (x) })
+
+static inline xmaddr_t phys_to_machine(xpaddr_t phys)
+{
+        unsigned offset = phys.paddr & ~PAGE_MASK;
+        return XMADDR(PFN_PHYS(pfn_to_mfn(PFN_DOWN(phys.paddr))) | offset);
+}
+
+static inline xpaddr_t machine_to_phys(xmaddr_t machine)
+{
+        unsigned offset = machine.maddr & ~PAGE_MASK;
+        return XPADDR(PFN_PHYS(mfn_to_pfn(PFN_DOWN(machine.maddr))) | offset);
+}
+/* VIRT <-> MACHINE conversion */
+#define virt_to_machine(v)      (phys_to_machine(XPADDR(__pa(v))))
+#define virt_to_pfn(v)          (PFN_DOWN(__pa(v)))
+#define virt_to_mfn(v)          (pfn_to_mfn(virt_to_pfn(v)))
+#define mfn_to_virt(m)          (__va(mfn_to_pfn(m) << PAGE_SHIFT))
+
+static inline xmaddr_t arbitrary_virt_to_machine(void *vaddr)
+{
+        /* TODO: assuming it is mapped in the kernel 1:1 */
+        return virt_to_machine(vaddr);
+}
+
+/* TODO: this shouldn't be here but it is because the frontend drivers
+ * are using it (its rolled in headers) even though we won't hit the code path.
+ * So for right now just punt with this.
+ */
+static inline pte_t *lookup_address(unsigned long address, unsigned int *level)
+{
+        BUG();
+        return NULL;
+}
+
+static inline int m2p_add_override(unsigned long mfn, struct page *page,
+                struct gnttab_map_grant_ref *kmap_op)
+{
+        return 0;
+}
+
+static inline int m2p_remove_override(struct page *page, bool clear_pte)
+{
+        return 0;
+}
+
+static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
+{
+        BUG();
+        return false;
+}
+#endif /* _ASM_ARM_XEN_PAGE_H */
diff --git a/arch/arm/include/uapi/asm/Kbuild b/arch/arm/include/uapi/asm/Kbuild
new file mode 100644
index 000000000000..baebb3da1d44
--- /dev/null
+++ b/arch/arm/include/uapi/asm/Kbuild
@@ -0,0 +1,3 @@
+# UAPI Header export list
+include include/uapi/asm-generic/Kbuild.asm
+
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 1c4321430737..d81f3a6d9ad8 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -21,7 +21,6 @@ obj-y		:= elf.o entry-armv.o entry-common.o irq.o opcodes.o \
 
 obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
 
-obj-$(CONFIG_LEDS)              += leds.o
 obj-$(CONFIG_OC_ETM)            += etm.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_ISA_DMA_API)       += dma.o
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index b244696de1a3..9b722612553d 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -271,15 +271,6 @@ static void __devinit pci_fixup_it8152(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
 
-
-
-void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
-{
-        if (debug_pci)
-                printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev));
-        pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
-}
-
 /*
  * If the bus contains any of these devices, then we must not turn on
  * parity checking of any kind.  Currently this is CyberPro 20x0 only.
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 463ff4a0ec8a..e337879595e5 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -387,6 +387,7 @@
 /* 375 */       CALL(sys_setns)
                 CALL(sys_process_vm_readv)
                 CALL(sys_process_vm_writev)
+                CALL(sys_ni_syscall)    /* reserved for sys_kcmp */
 #ifndef syscalls_counted
 .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
 #define syscalls_counted
diff --git a/arch/arm/kernel/leds.c b/arch/arm/kernel/leds.c
deleted file mode 100644
index 1911dae19e4f..000000000000
--- a/arch/arm/kernel/leds.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * LED support code, ripped out of arch/arm/kernel/time.c
- *
- *  Copyright (C) 1994-2001 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/syscore_ops.h>
-#include <linux/string.h>
-
-#include <asm/leds.h>
-
-static void dummy_leds_event(led_event_t evt)
-{
-}
-
-void (*leds_event)(led_event_t) = dummy_leds_event;
-
-struct leds_evt_name {
-        const char      name[8];
-        int             on;
-        int             off;
-};
-
-static const struct leds_evt_name evt_names[] = {
-        { "amber", led_amber_on, led_amber_off },
-        { "blue",  led_blue_on,  led_blue_off  },
-        { "green", led_green_on, led_green_off },
-        { "red",   led_red_on,   led_red_off   },
-};
-
-static ssize_t leds_store(struct device *dev,
-                        struct device_attribute *attr,
-                        const char *buf, size_t size)
-{
-        int ret = -EINVAL, len = strcspn(buf, " ");
-
-        if (len > 0 && buf[len] == '\0')
-                len--;
-
-        if (strncmp(buf, "claim", len) == 0) {
-                leds_event(led_claim);
-                ret = size;
-        } else if (strncmp(buf, "release", len) == 0) {
-                leds_event(led_release);
-                ret = size;
-        } else {
-                int i;
-
-                for (i = 0; i < ARRAY_SIZE(evt_names); i++) {
-                        if (strlen(evt_names[i].name) != len ||
-                            strncmp(buf, evt_names[i].name, len) != 0)
-                                continue;
-                        if (strncmp(buf+len, " on", 3) == 0) {
-                                leds_event(evt_names[i].on);
-                                ret = size;
-                        } else if (strncmp(buf+len, " off", 4) == 0) {
-                                leds_event(evt_names[i].off);
-                                ret = size;
-                        }
-                        break;
-                }
-        }
-        return ret;
-}
-
-static DEVICE_ATTR(event, 0200, NULL, leds_store);
-
-static struct bus_type leds_subsys = {
-        .name           = "leds",
-        .dev_name       = "leds",
-};
-
-static struct device leds_device = {
-        .id             = 0,
-        .bus            = &leds_subsys,
-};
-
-static int leds_suspend(void)
-{
-        leds_event(led_stop);
-        return 0;
-}
-
-static void leds_resume(void)
-{
-        leds_event(led_start);
-}
-
-static void leds_shutdown(void)
-{
-        leds_event(led_halted);
-}
-
-static struct syscore_ops leds_syscore_ops = {
-        .shutdown       = leds_shutdown,
-        .suspend        = leds_suspend,
-        .resume         = leds_resume,
-};
-
-static int __init leds_init(void)
-{
-        int ret;
-        ret = subsys_system_register(&leds_subsys, NULL);
-        if (ret == 0)
-                ret = device_register(&leds_device);
-        if (ret == 0)
-                ret = device_create_file(&leds_device, &dev_attr_event);
-        if (ret == 0)
-                register_syscore_ops(&leds_syscore_ops);
-        return ret;
-}
-
-device_initcall(leds_init);
-
-EXPORT_SYMBOL(leds_event);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 693b744fd572..04eea22d7958 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -31,9 +31,9 @@
 #include <linux/random.h>
 #include <linux/hw_breakpoint.h>
 #include <linux/cpuidle.h>
+#include <linux/leds.h>
 
 #include <asm/cacheflush.h>
-#include <asm/leds.h>
 #include <asm/processor.h>
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
@@ -189,7 +189,7 @@ void cpu_idle(void)
         while (1) {
                 tick_nohz_idle_enter();
                 rcu_idle_enter();
-                leds_event(led_idle_start);
+                ledtrig_cpu(CPU_LED_IDLE_START);
                 while (!need_resched()) {
 #ifdef CONFIG_HOTPLUG_CPU
                         if (cpu_is_offline(smp_processor_id()))
@@ -220,7 +220,7 @@ void cpu_idle(void)
                         } else
                                 local_irq_enable();
                 }
-                leds_event(led_idle_end);
+                ledtrig_cpu(CPU_LED_IDLE_END);
                 rcu_idle_exit();
                 tick_nohz_idle_exit();
                 schedule_preempt_disabled();
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index aa4ffe6e5ecf..dea7a925c7e2 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -24,6 +24,7 @@
 #include <linux/percpu.h>
 #include <linux/clockchips.h>
 #include <linux/completion.h>
+#include <linux/cpufreq.h>
 
 #include <linux/atomic.h>
 #include <asm/smp.h>
@@ -650,3 +651,56 @@ int setup_profiling_timer(unsigned int multiplier)
 {
         return -EINVAL;
 }
+
+#ifdef CONFIG_CPU_FREQ
+
+static DEFINE_PER_CPU(unsigned long, l_p_j_ref);
+static DEFINE_PER_CPU(unsigned long, l_p_j_ref_freq);
+static unsigned long global_l_p_j_ref;
+static unsigned long global_l_p_j_ref_freq;
+
+static int cpufreq_callback(struct notifier_block *nb,
+                                        unsigned long val, void *data)
+{
+        struct cpufreq_freqs *freq = data;
+        int cpu = freq->cpu;
+
+        if (freq->flags & CPUFREQ_CONST_LOOPS)
+                return NOTIFY_OK;
+
+        if (!per_cpu(l_p_j_ref, cpu)) {
+                per_cpu(l_p_j_ref, cpu) =
+                        per_cpu(cpu_data, cpu).loops_per_jiffy;
+                per_cpu(l_p_j_ref_freq, cpu) = freq->old;
+                if (!global_l_p_j_ref) {
+                        global_l_p_j_ref = loops_per_jiffy;
+                        global_l_p_j_ref_freq = freq->old;
+                }
+        }
+
+        if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
+            (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
+            (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE)) {
+                loops_per_jiffy = cpufreq_scale(global_l_p_j_ref,
+                                                global_l_p_j_ref_freq,
+                                                freq->new);
+                per_cpu(cpu_data, cpu).loops_per_jiffy =
+                        cpufreq_scale(per_cpu(l_p_j_ref, cpu),
+                                        per_cpu(l_p_j_ref_freq, cpu),
+                                        freq->new);
+        }
+        return NOTIFY_OK;
+}
+
+static struct notifier_block cpufreq_notifier = {
+        .notifier_call  = cpufreq_callback,
+};
+
+static int __init register_cpufreq_notifier(void)
+{
+        return cpufreq_register_notifier(&cpufreq_notifier,
+                                                CPUFREQ_TRANSITION_NOTIFIER);
+}
+core_initcall(register_cpufreq_notifier);
+
+#endif
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index fef42b21cecb..e1f906989bb8 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -11,7 +11,6 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/clk.h>
-#include <linux/cpufreq.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/err.h>
@@ -96,7 +95,52 @@ static void twd_timer_stop(struct clock_event_device *clk)
         disable_percpu_irq(clk->irq);
 }
 
-#ifdef CONFIG_CPU_FREQ
+#ifdef CONFIG_COMMON_CLK
+
+/*
+ * Updates clockevent frequency when the cpu frequency changes.
+ * Called on the cpu that is changing frequency with interrupts disabled.
+ */
+static void twd_update_frequency(void *new_rate)
+{
+        twd_timer_rate = *((unsigned long *) new_rate);
+
+        clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate);
+}
+
+static int twd_rate_change(struct notifier_block *nb,
+        unsigned long flags, void *data)
+{
+        struct clk_notifier_data *cnd = data;
+
+        /*
+         * The twd clock events must be reprogrammed to account for the new
+         * frequency.  The timer is local to a cpu, so cross-call to the
+         * changing cpu.
+         */
+        if (flags == POST_RATE_CHANGE)
+                smp_call_function(twd_update_frequency,
+                                  (void *)&cnd->new_rate, 1);
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block twd_clk_nb = {
+        .notifier_call = twd_rate_change,
+};
+
+static int twd_clk_init(void)
+{
+        if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
+                return clk_notifier_register(twd_clk, &twd_clk_nb);
+
+        return 0;
+}
+core_initcall(twd_clk_init);
+
+#elif defined (CONFIG_CPU_FREQ)
+
+#include <linux/cpufreq.h>
 
 /*
  * Updates clockevent frequency when the cpu frequency changes.
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index af2afb019672..09be0c3c9069 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -25,7 +25,6 @@
 #include <linux/timer.h>
 #include <linux/irq.h>
 
-#include <asm/leds.h>
 #include <asm/thread_info.h>
 #include <asm/sched_clock.h>
 #include <asm/stacktrace.h>
@@ -80,21 +79,6 @@ u32 arch_gettimeoffset(void)
 }
 #endif /* CONFIG_ARCH_USES_GETTIMEOFFSET */
 
-#ifdef CONFIG_LEDS_TIMER
-static inline void do_leds(void)
-{
-        static unsigned int count = HZ/2;
-
-        if (--count == 0) {
-                count = HZ/2;
-                leds_event(led_timer);
-        }
-}
-#else
-#define do_leds()
-#endif
-
-
 #ifndef CONFIG_GENERIC_CLOCKEVENTS
 /*
  * Kernel system timer support.
@@ -102,7 +86,6 @@ static inline void do_leds(void)
 void timer_tick(void)
 {
         profile_tick(CPU_PROFILING);
-        do_leds();
         xtime_update(1);
 #ifndef CONFIG_SMP
         update_process_times(user_mode(get_irq_regs()));
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 01fb7325fecc..9ac427a702da 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -294,9 +294,9 @@ void __init at91_add_device_cf(struct at91_cf_data *data) {}
  *  MMC / SD
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
 static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct at91_mmc_data mmc_data;
+static struct mci_platform_data mmc_data;
 
 static struct resource mmc_resources[] = {
         [0] = {
@@ -312,7 +312,7 @@ static struct resource mmc_resources[] = {
 };
 
 static struct platform_device at91rm9200_mmc_device = {
-        .name           = "at91_mci",
+        .name           = "atmel_mci",
         .id             = -1,
         .dev            = {
                                 .dma_mask               = &mmc_dmamask,
@@ -323,53 +323,69 @@ static struct platform_device at91rm9200_mmc_device = {
         .num_resources  = ARRAY_SIZE(mmc_resources),
 };
 
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 {
+        unsigned int i;
+        unsigned int slot_count = 0;
+
         if (!data)
                 return;
 
-        /* input/irq */
-        if (gpio_is_valid(data->det_pin)) {
-                at91_set_gpio_input(data->det_pin, 1);
-                at91_set_deglitch(data->det_pin, 1);
-        }
-        if (gpio_is_valid(data->wp_pin))
-                at91_set_gpio_input(data->wp_pin, 1);
-        if (gpio_is_valid(data->vcc_pin))
-                at91_set_gpio_output(data->vcc_pin, 0);
-
-        /* CLK */
-        at91_set_A_periph(AT91_PIN_PA27, 0);
+        for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
 
-        if (data->slot_b) {
-                /* CMD */
-                at91_set_B_periph(AT91_PIN_PA8, 1);
+                if (!data->slot[i].bus_width)
+                        continue;
 
-                /* DAT0, maybe DAT1..DAT3 */
-                at91_set_B_periph(AT91_PIN_PA9, 1);
-                if (data->wire4) {
-                        at91_set_B_periph(AT91_PIN_PA10, 1);
-                        at91_set_B_periph(AT91_PIN_PA11, 1);
-                        at91_set_B_periph(AT91_PIN_PA12, 1);
+                /* input/irq */
+                if (gpio_is_valid(data->slot[i].detect_pin)) {
+                        at91_set_gpio_input(data->slot[i].detect_pin, 1);
+                        at91_set_deglitch(data->slot[i].detect_pin, 1);
                 }
-        } else {
-                /* CMD */
-                at91_set_A_periph(AT91_PIN_PA28, 1);
-
-                /* DAT0, maybe DAT1..DAT3 */
-                at91_set_A_periph(AT91_PIN_PA29, 1);
-                if (data->wire4) {
-                        at91_set_B_periph(AT91_PIN_PB3, 1);
-                        at91_set_B_periph(AT91_PIN_PB4, 1);
-                        at91_set_B_periph(AT91_PIN_PB5, 1);
+                if (gpio_is_valid(data->slot[i].wp_pin))
+                        at91_set_gpio_input(data->slot[i].wp_pin, 1);
+
+                switch (i) {
+                case 0:                                 /* slot A */
+                        /* CMD */
+                        at91_set_A_periph(AT91_PIN_PA28, 1);
+                        /* DAT0, maybe DAT1..DAT3 */
+                        at91_set_A_periph(AT91_PIN_PA29, 1);
+                        if (data->slot[i].bus_width == 4) {
+                                at91_set_B_periph(AT91_PIN_PB3, 1);
+                                at91_set_B_periph(AT91_PIN_PB4, 1);
+                                at91_set_B_periph(AT91_PIN_PB5, 1);
+                        }
+                        slot_count++;
+                        break;
+                case 1:                                 /* slot B */
+                        /* CMD */
+                        at91_set_B_periph(AT91_PIN_PA8, 1);
+                        /* DAT0, maybe DAT1..DAT3 */
+                        at91_set_B_periph(AT91_PIN_PA9, 1);
+                        if (data->slot[i].bus_width == 4) {
+                                at91_set_B_periph(AT91_PIN_PA10, 1);
+                                at91_set_B_periph(AT91_PIN_PA11, 1);
+                                at91_set_B_periph(AT91_PIN_PA12, 1);
+                        }
+                        slot_count++;
+                        break;
+                default:
+                        printk(KERN_ERR
+                               "AT91: SD/MMC slot %d not available\n", i);
+                        break;
+                }
+                if (slot_count) {
+                        /* CLK */
+                        at91_set_A_periph(AT91_PIN_PA27, 0);
+
+                        mmc_data = *data;
+                        platform_device_register(&at91rm9200_mmc_device);
                 }
         }
 
-        mmc_data = *data;
-        platform_device_register(&at91rm9200_mmc_device);
 }
 #else
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
 #endif
 
 
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index bce572a530ef..af50ff3281c7 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -209,92 +209,10 @@ void __init at91_add_device_eth(struct macb_platform_data *data) {}
 
 
 /* --------------------------------------------------------------------
- *  MMC / SD
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
-static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct at91_mmc_data mmc_data;
-
-static struct resource mmc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_MCI,
-                .end    = AT91SAM9260_BASE_MCI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91sam9260_mmc_device = {
-        .name           = "at91_mci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc_data,
-        },
-        .resource       = mmc_resources,
-        .num_resources  = ARRAY_SIZE(mmc_resources),
-};
-
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
-{
-        if (!data)
-                return;
-
-        /* input/irq */
-        if (gpio_is_valid(data->det_pin)) {
-                at91_set_gpio_input(data->det_pin, 1);
-                at91_set_deglitch(data->det_pin, 1);
-        }
-        if (gpio_is_valid(data->wp_pin))
-                at91_set_gpio_input(data->wp_pin, 1);
-        if (gpio_is_valid(data->vcc_pin))
-                at91_set_gpio_output(data->vcc_pin, 0);
-
-        /* CLK */
-        at91_set_A_periph(AT91_PIN_PA8, 0);
-
-        if (data->slot_b) {
-                /* CMD */
-                at91_set_B_periph(AT91_PIN_PA1, 1);
-
-                /* DAT0, maybe DAT1..DAT3 */
-                at91_set_B_periph(AT91_PIN_PA0, 1);
-                if (data->wire4) {
-                        at91_set_B_periph(AT91_PIN_PA5, 1);
-                        at91_set_B_periph(AT91_PIN_PA4, 1);
-                        at91_set_B_periph(AT91_PIN_PA3, 1);
-                }
-        } else {
-                /* CMD */
-                at91_set_A_periph(AT91_PIN_PA7, 1);
-
-                /* DAT0, maybe DAT1..DAT3 */
-                at91_set_A_periph(AT91_PIN_PA6, 1);
-                if (data->wire4) {
-                        at91_set_A_periph(AT91_PIN_PA9, 1);
-                        at91_set_A_periph(AT91_PIN_PA10, 1);
-                        at91_set_A_periph(AT91_PIN_PA11, 1);
-                }
-        }
-
-        mmc_data = *data;
-        platform_device_register(&at91sam9260_mmc_device);
-}
-#else
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
-#endif
-
-/* --------------------------------------------------------------------
  *  MMC / SD Slot for Atmel MCI Driver
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
 static u64 mmc_dmamask = DMA_BIT_MASK(32);
 static struct mci_platform_data mmc_data;
 
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index bc2590d712d0..11e9fa835cde 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -137,9 +137,9 @@ void __init at91_add_device_udc(struct at91_udc_data *data) {}
  *  MMC / SD
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
 static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct at91_mmc_data mmc_data;
+static struct mci_platform_data mmc_data;
 
 static struct resource mmc_resources[] = {
         [0] = {
@@ -155,7 +155,7 @@ static struct resource mmc_resources[] = {
 };
 
 static struct platform_device at91sam9261_mmc_device = {
-        .name           = "at91_mci",
+        .name           = "atmel_mci",
         .id             = -1,
         .dev            = {
                                 .dma_mask               = &mmc_dmamask,
@@ -166,40 +166,40 @@ static struct platform_device at91sam9261_mmc_device = {
         .num_resources  = ARRAY_SIZE(mmc_resources),
 };
 
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 {
         if (!data)
                 return;
 
-        /* input/irq */
-        if (gpio_is_valid(data->det_pin)) {
-                at91_set_gpio_input(data->det_pin, 1);
-                at91_set_deglitch(data->det_pin, 1);
-        }
-        if (gpio_is_valid(data->wp_pin))
-                at91_set_gpio_input(data->wp_pin, 1);
-        if (gpio_is_valid(data->vcc_pin))
-                at91_set_gpio_output(data->vcc_pin, 0);
-
-        /* CLK */
-        at91_set_B_periph(AT91_PIN_PA2, 0);
-
-        /* CMD */
-        at91_set_B_periph(AT91_PIN_PA1, 1);
-
-        /* DAT0, maybe DAT1..DAT3 */
-        at91_set_B_periph(AT91_PIN_PA0, 1);
-        if (data->wire4) {
-                at91_set_B_periph(AT91_PIN_PA4, 1);
-                at91_set_B_periph(AT91_PIN_PA5, 1);
-                at91_set_B_periph(AT91_PIN_PA6, 1);
-        }
+        if (data->slot[0].bus_width) {
+                /* input/irq */
+                if (gpio_is_valid(data->slot[0].detect_pin)) {
+                        at91_set_gpio_input(data->slot[0].detect_pin, 1);
+                        at91_set_deglitch(data->slot[0].detect_pin, 1);
+                }
+                if (gpio_is_valid(data->slot[0].wp_pin))
+                        at91_set_gpio_input(data->slot[0].wp_pin, 1);
+
+                /* CLK */
+                at91_set_B_periph(AT91_PIN_PA2, 0);
 
-        mmc_data = *data;
-        platform_device_register(&at91sam9261_mmc_device);
+                /* CMD */
+                at91_set_B_periph(AT91_PIN_PA1, 1);
+
+                /* DAT0, maybe DAT1..DAT3 */
+                at91_set_B_periph(AT91_PIN_PA0, 1);
+                if (data->slot[0].bus_width == 4) {
+                        at91_set_B_periph(AT91_PIN_PA4, 1);
+                        at91_set_B_periph(AT91_PIN_PA5, 1);
+                        at91_set_B_periph(AT91_PIN_PA6, 1);
+                }
+
+                mmc_data = *data;
+                platform_device_register(&at91sam9261_mmc_device);
+        }
 }
 #else
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
 #endif
 
 
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 84b38105231e..144ef5de51b6 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -188,8 +188,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_ID("hclk", &macb_clk),
         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 9b6ca734f1a9..7c0898fe20fa 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -218,9 +218,9 @@ void __init at91_add_device_eth(struct macb_platform_data *data) {}
  *  MMC / SD
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
 static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct at91_mmc_data mmc0_data, mmc1_data;
+static struct mci_platform_data mmc0_data, mmc1_data;
 
 static struct resource mmc0_resources[] = {
         [0] = {
@@ -236,7 +236,7 @@ static struct resource mmc0_resources[] = {
 };
 
 static struct platform_device at91sam9263_mmc0_device = {
-        .name           = "at91_mci",
+        .name           = "atmel_mci",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &mmc_dmamask,
@@ -261,7 +261,7 @@ static struct resource mmc1_resources[] = {
 };
 
 static struct platform_device at91sam9263_mmc1_device = {
-        .name           = "at91_mci",
+        .name           = "atmel_mci",
         .id             = 1,
         .dev            = {
                                 .dma_mask               = &mmc_dmamask,
@@ -272,85 +272,110 @@ static struct platform_device at91sam9263_mmc1_device = {
         .num_resources  = ARRAY_SIZE(mmc1_resources),
 };
 
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 {
+        unsigned int i;
+        unsigned int slot_count = 0;
+
         if (!data)
                 return;
 
-        /* input/irq */
-        if (gpio_is_valid(data->det_pin)) {
-                at91_set_gpio_input(data->det_pin, 1);
-                at91_set_deglitch(data->det_pin, 1);
-        }
-        if (gpio_is_valid(data->wp_pin))
-                at91_set_gpio_input(data->wp_pin, 1);
-        if (gpio_is_valid(data->vcc_pin))
-                at91_set_gpio_output(data->vcc_pin, 0);
+        for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
 
-        if (mmc_id == 0) {              /* MCI0 */
-                /* CLK */
-                at91_set_A_periph(AT91_PIN_PA12, 0);
+                if (!data->slot[i].bus_width)
+                        continue;
 
-                if (data->slot_b) {
-                        /* CMD */
-                        at91_set_A_periph(AT91_PIN_PA16, 1);
+                /* input/irq */
+                if (gpio_is_valid(data->slot[i].detect_pin)) {
+                        at91_set_gpio_input(data->slot[i].detect_pin,
+                                        1);
+                        at91_set_deglitch(data->slot[i].detect_pin,
+                                        1);
+                }
+                if (gpio_is_valid(data->slot[i].wp_pin))
+                        at91_set_gpio_input(data->slot[i].wp_pin, 1);
+
+                if (mmc_id == 0) {                              /* MCI0 */
+                        switch (i) {
+                        case 0:                                 /* slot A */
+                                /* CMD */
+                                at91_set_A_periph(AT91_PIN_PA1, 1);
+                                /* DAT0, maybe DAT1..DAT3 */
+                                at91_set_A_periph(AT91_PIN_PA0, 1);
+                                if (data->slot[i].bus_width == 4) {
+                                        at91_set_A_periph(AT91_PIN_PA3, 1);
+                                        at91_set_A_periph(AT91_PIN_PA4, 1);
+                                        at91_set_A_periph(AT91_PIN_PA5, 1);
+                                }
+                                slot_count++;
+                                break;
+                        case 1:                                 /* slot B */
+                                /* CMD */
+                                at91_set_A_periph(AT91_PIN_PA16, 1);
+                                /* DAT0, maybe DAT1..DAT3 */
+                                at91_set_A_periph(AT91_PIN_PA17, 1);
+                                if (data->slot[i].bus_width == 4) {
+                                        at91_set_A_periph(AT91_PIN_PA18, 1);
+                                        at91_set_A_periph(AT91_PIN_PA19, 1);
+                                        at91_set_A_periph(AT91_PIN_PA20, 1);
+                                }
+                                slot_count++;
+                                break;
+                        default:
+                                printk(KERN_ERR
+                                       "AT91: SD/MMC slot %d not available\n", i);
+                                break;
+                        }
+                        if (slot_count) {
+                                /* CLK */
+                                at91_set_A_periph(AT91_PIN_PA12, 0);
 
-                        /* DAT0, maybe DAT1..DAT3 */
-                        at91_set_A_periph(AT91_PIN_PA17, 1);
-                        if (data->wire4) {
-                                at91_set_A_periph(AT91_PIN_PA18, 1);
-                                at91_set_A_periph(AT91_PIN_PA19, 1);
-                                at91_set_A_periph(AT91_PIN_PA20, 1);
+                                mmc0_data = *data;
+                                platform_device_register(&at91sam9263_mmc0_device);
                         }
-                } else {
-                        /* CMD */
-                        at91_set_A_periph(AT91_PIN_PA1, 1);
-
-                        /* DAT0, maybe DAT1..DAT3 */
-                        at91_set_A_periph(AT91_PIN_PA0, 1);
-                        if (data->wire4) {
-                                at91_set_A_periph(AT91_PIN_PA3, 1);
-                                at91_set_A_periph(AT91_PIN_PA4, 1);
-                                at91_set_A_periph(AT91_PIN_PA5, 1);
+                } else if (mmc_id == 1) {                       /* MCI1 */
+                        switch (i) {
+                        case 0:                                 /* slot A */
+                                /* CMD */
+                                at91_set_A_periph(AT91_PIN_PA7, 1);
+                                /* DAT0, maybe DAT1..DAT3 */
+                                at91_set_A_periph(AT91_PIN_PA8, 1);
+                                if (data->slot[i].bus_width == 4) {
+                                        at91_set_A_periph(AT91_PIN_PA9, 1);
+                                        at91_set_A_periph(AT91_PIN_PA10, 1);
+                                        at91_set_A_periph(AT91_PIN_PA11, 1);
+                                }
+                                slot_count++;
+                                break;
+                        case 1:                                 /* slot B */
+                                /* CMD */
+                                at91_set_A_periph(AT91_PIN_PA21, 1);
+                                /* DAT0, maybe DAT1..DAT3 */
+                                at91_set_A_periph(AT91_PIN_PA22, 1);
+                                if (data->slot[i].bus_width == 4) {
+                                        at91_set_A_periph(AT91_PIN_PA23, 1);
+                                        at91_set_A_periph(AT91_PIN_PA24, 1);
+                                        at91_set_A_periph(AT91_PIN_PA25, 1);
+                                }
+                                slot_count++;
+                                break;
+                        default:
+                                printk(KERN_ERR
+                                       "AT91: SD/MMC slot %d not available\n", i);
+                                break;
                         }
-                }
+                        if (slot_count) {
+                                /* CLK */
+                                at91_set_A_periph(AT91_PIN_PA6, 0);
 
-                mmc0_data = *data;
-                platform_device_register(&at91sam9263_mmc0_device);
-        } else {                        /* MCI1 */
-                /* CLK */
-                at91_set_A_periph(AT91_PIN_PA6, 0);
-
-                if (data->slot_b) {
-                        /* CMD */
-                        at91_set_A_periph(AT91_PIN_PA21, 1);
-
-                        /* DAT0, maybe DAT1..DAT3 */
-                        at91_set_A_periph(AT91_PIN_PA22, 1);
-                        if (data->wire4) {
-                                at91_set_A_periph(AT91_PIN_PA23, 1);
-                                at91_set_A_periph(AT91_PIN_PA24, 1);
-                                at91_set_A_periph(AT91_PIN_PA25, 1);
-                        }
-                } else {
-                        /* CMD */
-                        at91_set_A_periph(AT91_PIN_PA7, 1);
-
-                        /* DAT0, maybe DAT1..DAT3 */
-                        at91_set_A_periph(AT91_PIN_PA8, 1);
-                        if (data->wire4) {
-                                at91_set_A_periph(AT91_PIN_PA9, 1);
-                                at91_set_A_periph(AT91_PIN_PA10, 1);
-                                at91_set_A_periph(AT91_PIN_PA11, 1);
+                                mmc1_data = *data;
+                                platform_device_register(&at91sam9263_mmc1_device);
                         }
                 }
-
-                mmc1_data = *data;
-                platform_device_register(&at91sam9263_mmc1_device);
         }
 }
 #else
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
 #endif
 
 /* --------------------------------------------------------------------
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index dcda24838b5a..deafea0e493d 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -161,9 +161,9 @@ void __init at91_add_device_usba(struct usba_platform_data *data) {}
  *  MMC / SD
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
 static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct at91_mmc_data mmc_data;
+static struct mci_platform_data mmc_data;
 
 static struct resource mmc_resources[] = {
         [0] = {
@@ -179,7 +179,7 @@ static struct resource mmc_resources[] = {
 };
 
 static struct platform_device at91sam9rl_mmc_device = {
-        .name           = "at91_mci",
+        .name           = "atmel_mci",
         .id             = -1,
         .dev            = {
                                 .dma_mask               = &mmc_dmamask,
@@ -190,40 +190,40 @@ static struct platform_device at91sam9rl_mmc_device = {
         .num_resources  = ARRAY_SIZE(mmc_resources),
 };
 
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 {
         if (!data)
                 return;
 
-        /* input/irq */
-        if (gpio_is_valid(data->det_pin)) {
-                at91_set_gpio_input(data->det_pin, 1);
-                at91_set_deglitch(data->det_pin, 1);
-        }
-        if (gpio_is_valid(data->wp_pin))
-                at91_set_gpio_input(data->wp_pin, 1);
-        if (gpio_is_valid(data->vcc_pin))
-                at91_set_gpio_output(data->vcc_pin, 0);
-
-        /* CLK */
-        at91_set_A_periph(AT91_PIN_PA2, 0);
-
-        /* CMD */
-        at91_set_A_periph(AT91_PIN_PA1, 1);
-
-        /* DAT0, maybe DAT1..DAT3 */
-        at91_set_A_periph(AT91_PIN_PA0, 1);
-        if (data->wire4) {
-                at91_set_A_periph(AT91_PIN_PA3, 1);
-                at91_set_A_periph(AT91_PIN_PA4, 1);
-                at91_set_A_periph(AT91_PIN_PA5, 1);
+        if (data->slot[0].bus_width) {
+                /* input/irq */
+                if (gpio_is_valid(data->slot[0].detect_pin)) {
+                        at91_set_gpio_input(data->slot[0].detect_pin, 1);
+                        at91_set_deglitch(data->slot[0].detect_pin, 1);
+                }
+                if (gpio_is_valid(data->slot[0].wp_pin))
+                        at91_set_gpio_input(data->slot[0].wp_pin, 1);
+
+                /* CLK */
+                at91_set_A_periph(AT91_PIN_PA2, 0);
+
+                /* CMD */
+                at91_set_A_periph(AT91_PIN_PA1, 1);
+
+                /* DAT0, maybe DAT1..DAT3 */
+                at91_set_A_periph(AT91_PIN_PA0, 1);
+                if (data->slot[0].bus_width == 4) {
+                        at91_set_A_periph(AT91_PIN_PA3, 1);
+                        at91_set_A_periph(AT91_PIN_PA4, 1);
+                        at91_set_A_periph(AT91_PIN_PA5, 1);
+                }
+
+                mmc_data = *data;
+                platform_device_register(&at91sam9rl_mmc_device);
         }
-
-        mmc_data = *data;
-        platform_device_register(&at91sam9rl_mmc_device);
 }
 #else
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
 #endif
 
 
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index de7be1931817..93a832f70232 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -133,12 +133,12 @@ static struct atmel_nand_data __initdata afeb9260_nand_data = {
 /*
  * MCI (SD/MMC)
  */
-static struct at91_mmc_data __initdata afeb9260_mmc_data = {
-        .det_pin        = AT91_PIN_PC9,
-        .wp_pin         = AT91_PIN_PC4,
-        .slot_b         = 1,
-        .wire4          = 1,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata afeb9260_mci0_data = {
+        .slot[1] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PC9,
+                .wp_pin         = AT91_PIN_PC4,
+        },
 };
 
 
@@ -199,7 +199,7 @@ static void __init afeb9260_board_init(void)
         at91_set_B_periph(AT91_PIN_PA10, 0);    /* ETX2 */
         at91_set_B_periph(AT91_PIN_PA11, 0);    /* ETX3 */
         /* MMC */
-        at91_add_device_mmc(0, &afeb9260_mmc_data);
+        at91_add_device_mci(0, &afeb9260_mci0_data);
         /* I2C */
         at91_add_device_i2c(afeb9260_i2c_devices,
                         ARRAY_SIZE(afeb9260_i2c_devices));
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index a5b002f32a61..71d8f362a1d5 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -71,12 +71,12 @@ static struct at91_udc_data __initdata carmeva_udc_data = {
         // .vcc_pin     = -EINVAL,
 // };
 
-static struct at91_mmc_data __initdata carmeva_mmc_data = {
-        .slot_b         = 0,
-        .wire4          = 1,
-        .det_pin        = AT91_PIN_PB10,
-        .wp_pin         = AT91_PIN_PC14,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata carmeva_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PB10,
+                .wp_pin         = AT91_PIN_PC14,
+        },
 };
 
 static struct spi_board_info carmeva_spi_devices[] = {
@@ -150,7 +150,7 @@ static void __init carmeva_board_init(void)
         /* Compact Flash */
 //      at91_add_device_cf(&carmeva_cf_data);
         /* MMC */
-        at91_add_device_mmc(0, &carmeva_mmc_data);
+        at91_add_device_mci(0, &carmeva_mci0_data);
         /* LEDs */
         at91_gpio_leds(carmeva_leds, ARRAY_SIZE(carmeva_leds));
 }
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index ecbc13b594de..e71c473316e3 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -254,8 +254,7 @@ static struct gpio_led cpu9krea_leds[] = {
 
 static struct i2c_board_info __initdata cpu9krea_i2c_devices[] = {
         {
-                I2C_BOARD_INFO("rtc-ds1307", 0x68),
-                .type   = "ds1339",
+                I2C_BOARD_INFO("ds1339", 0x68),
         },
 };
 
@@ -312,12 +311,12 @@ static void __init cpu9krea_add_device_buttons(void)
 /*
  * MCI (SD/MMC)
  */
-static struct at91_mmc_data __initdata cpu9krea_mmc_data = {
-        .slot_b         = 0,
-        .wire4          = 1,
-        .det_pin        = AT91_PIN_PA29,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata cpu9krea_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PA29,
+                .wp_pin         = -EINVAL,
+        },
 };
 
 static void __init cpu9krea_board_init(void)
@@ -359,7 +358,7 @@ static void __init cpu9krea_board_init(void)
         /* Ethernet */
         at91_add_device_eth(&cpu9krea_macb_data);
         /* MMC */
-        at91_add_device_mmc(0, &cpu9krea_mmc_data);
+        at91_add_device_mci(0, &cpu9krea_mci0_data);
         /* I2C */
         at91_add_device_i2c(cpu9krea_i2c_devices,
                 ARRAY_SIZE(cpu9krea_i2c_devices));
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 2e6d043c82f2..2cbd1a2b6c35 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -78,11 +78,12 @@ static struct at91_udc_data __initdata cpuat91_udc_data = {
         .pullup_pin     = AT91_PIN_PC14,
 };
 
-static struct at91_mmc_data __initdata cpuat91_mmc_data = {
-        .det_pin        = AT91_PIN_PC2,
-        .wire4          = 1,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata cpuat91_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PC2,
+                .wp_pin         = -EINVAL,
+        },
 };
 
 static struct physmap_flash_data cpuat91_flash_data = {
@@ -168,7 +169,7 @@ static void __init cpuat91_board_init(void)
         /* USB Device */
         at91_add_device_udc(&cpuat91_udc_data);
         /* MMC */
-        at91_add_device_mmc(0, &cpuat91_mmc_data);
+        at91_add_device_mci(0, &cpuat91_mci0_data);
         /* I2C */
         at91_add_device_i2c(NULL, 0);
         /* Platform devices */
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 462bc319cbc5..3e37437a7a61 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -87,12 +87,12 @@ static struct at91_cf_data __initdata csb337_cf_data = {
         .rst_pin        = AT91_PIN_PD2,
 };
 
-static struct at91_mmc_data __initdata csb337_mmc_data = {
-        .det_pin        = AT91_PIN_PD5,
-        .slot_b         = 0,
-        .wire4          = 1,
-        .wp_pin         = AT91_PIN_PD6,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata csb337_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PD5,
+                .wp_pin         = AT91_PIN_PD6,
+        },
 };
 
 static struct spi_board_info csb337_spi_devices[] = {
@@ -220,8 +220,6 @@ static struct gpio_led csb_leds[] = {
 
 static void __init csb337_board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
         /* Serial */
         /* DBGU on ttyS0 */
         at91_register_uart(0, 0, 0);
@@ -240,7 +238,7 @@ static void __init csb337_board_init(void)
         /* SPI */
         at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices));
         /* MMC */
-        at91_add_device_mmc(0, &csb337_mmc_data);
+        at91_add_device_mci(0, &csb337_mci0_data);
         /* NOR flash */
         platform_device_register(&csb_flash);
         /* LEDs */
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index d1e1f3fc0a47..0cfac16ee9d5 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -70,12 +70,12 @@ static struct at91_cf_data __initdata eb9200_cf_data = {
         .rst_pin        = AT91_PIN_PC5,
 };
 
-static struct at91_mmc_data __initdata eb9200_mmc_data = {
-        .slot_b         = 0,
-        .wire4          = 1,
-        .det_pin        = -EINVAL,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata eb9200_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = -EINVAL,
+                .wp_pin         = -EINVAL,
+        },
 };
 
 static struct i2c_board_info __initdata eb9200_i2c_devices[] = {
@@ -113,7 +113,7 @@ static void __init eb9200_board_init(void)
         at91_add_device_spi(NULL, 0);
         /* MMC */
         /* only supports 1 or 4 bit interface, not wired through to SPI */
-        at91_add_device_mmc(0, &eb9200_mmc_data);
+        at91_add_device_mci(0, &eb9200_mci0_data);
 }
 
 MACHINE_START(ATEB9200, "Embest ATEB9200")
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 9c24cb25707c..3d931ffac4bf 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -64,12 +64,12 @@ static struct at91_usbh_data __initdata ecb_at91usbh_data = {
         .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
-static struct at91_mmc_data __initdata ecb_at91mmc_data = {
-        .slot_b         = 0,
-        .wire4          = 1,
-        .det_pin        = -EINVAL,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata ecbat91_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = -EINVAL,
+                .wp_pin         = -EINVAL,
+        },
 };
 
 
@@ -138,11 +138,20 @@ static struct spi_board_info __initdata ecb_at91spi_devices[] = {
         },
 };
 
+/*
+ * LEDs
+ */
+static struct gpio_led ecb_leds[] = {
+        {       /* D1 */
+                .name                   = "led1",
+                .gpio                   = AT91_PIN_PC7,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        }
+};
+
 static void __init ecb_at91board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
-
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -161,10 +170,13 @@ static void __init ecb_at91board_init(void)
         at91_add_device_i2c(NULL, 0);
 
         /* MMC */
-        at91_add_device_mmc(0, &ecb_at91mmc_data);
+        at91_add_device_mci(0, &ecbat91_mci0_data);
 
         /* SPI */
         at91_add_device_spi(ecb_at91spi_devices, ARRAY_SIZE(ecb_at91spi_devices));
+
+        /* LEDs */
+        at91_gpio_leds(ecb_leds, ARRAY_SIZE(ecb_leds));
 }
 
 MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 82bdfde3405f..d93658a2b128 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -56,12 +56,12 @@ static struct at91_udc_data __initdata eco920_udc_data = {
         .pullup_pin     = AT91_PIN_PB13,
 };
 
-static struct at91_mmc_data __initdata eco920_mmc_data = {
-        .slot_b         = 0,
-        .wire4          = 0,
-        .det_pin        = -EINVAL,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata eco920_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 1,
+                .detect_pin     = -EINVAL,
+                .wp_pin         = -EINVAL,
+        },
 };
 
 static struct physmap_flash_data eco920_flash_data = {
@@ -93,10 +93,26 @@ static struct spi_board_info eco920_spi_devices[] = {
         },
 };
 
+/*
+ * LEDs
+ */
+static struct gpio_led eco920_leds[] = {
+        {       /* D1 */
+                .name                   = "led1",
+                .gpio                   = AT91_PIN_PB0,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+        {       /* D2 */
+                .name                   = "led2",
+                .gpio                   = AT91_PIN_PB1,
+                .active_low             = 1,
+                .default_trigger        = "timer",
+        }
+};
+
 static void __init eco920_board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
         /* DBGU on ttyS0. (Rx & Tx only */
         at91_register_uart(0, 0, 0);
         at91_add_device_serial();
@@ -104,7 +120,7 @@ static void __init eco920_board_init(void)
         at91_add_device_usbh(&eco920_usbh_data);
         at91_add_device_udc(&eco920_udc_data);
 
-        at91_add_device_mmc(0, &eco920_mmc_data);
+        at91_add_device_mci(0, &eco920_mci0_data);
         platform_device_register(&eco920_flash);
 
         at91_ramc_write(0, AT91_SMC_CSR(7),     AT91_SMC_RWHOLD_(1)
@@ -127,6 +143,8 @@ static void __init eco920_board_init(void)
         );
 
         at91_add_device_spi(eco920_spi_devices, ARRAY_SIZE(eco920_spi_devices));
+        /* LEDs */
+        at91_gpio_leds(eco920_leds, ARRAY_SIZE(eco920_leds));
 }
 
 MACHINE_START(ECO920, "eco920")
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 6cc83a87d77c..fa98abacb1ba 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -75,12 +75,12 @@ static struct spi_board_info flexibity_spi_devices[] = {
 };
 
 /* MCI (SD/MMC) */
-static struct at91_mmc_data __initdata flexibity_mmc_data = {
-        .slot_b         = 0,
-        .wire4          = 1,
-        .det_pin        = AT91_PIN_PC9,
-        .wp_pin         = AT91_PIN_PC4,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata flexibity_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PC9,
+                .wp_pin         = AT91_PIN_PC4,
+        },
 };
 
 /* LEDs */
@@ -152,7 +152,7 @@ static void __init flexibity_board_init(void)
         at91_add_device_spi(flexibity_spi_devices,
                 ARRAY_SIZE(flexibity_spi_devices));
         /* MMC */
-        at91_add_device_mmc(0, &flexibity_mmc_data);
+        at91_add_device_mci(0, &flexibity_mci0_data);
         /* LEDs */
         at91_gpio_leds(flexibity_leds, ARRAY_SIZE(flexibity_leds));
 }
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index 69ab1247ef81..6e47071d8206 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -86,7 +86,7 @@ static struct at91_udc_data __initdata foxg20_udc_data = {
  * SPI devices.
  */
 static struct spi_board_info foxg20_spi_devices[] = {
-#if !defined(CONFIG_MMC_AT91)
+#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
         {
                 .modalias       = "mtd_dataflash",
                 .chip_select    = 1,
@@ -109,12 +109,12 @@ static struct macb_platform_data __initdata foxg20_macb_data = {
  * MCI (SD/MMC)
  * det_pin, wp_pin and vcc_pin are not connected
  */
-static struct at91_mmc_data __initdata foxg20_mmc_data = {
-        .slot_b         = 1,
-        .wire4          = 1,
-        .det_pin        = -EINVAL,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata foxg20_mci0_data = {
+        .slot[1] = {
+                .bus_width      = 4,
+                .detect_pin     = -EINVAL,
+                .wp_pin         = -EINVAL,
+        },
 };
 
 
@@ -247,7 +247,7 @@ static void __init foxg20_board_init(void)
         /* Ethernet */
         at91_add_device_eth(&foxg20_macb_data);
         /* MMC */
-        at91_add_device_mmc(0, &foxg20_mmc_data);
+        at91_add_device_mci(0, &foxg20_mci0_data);
         /* I2C */
         at91_add_device_i2c(foxg20_i2c_devices, ARRAY_SIZE(foxg20_i2c_devices));
         /* LEDs */
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 64c1dbf88a07..86050da3ba53 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -66,11 +66,20 @@ static struct at91_udc_data __initdata kafa_udc_data = {
         .pullup_pin     = AT91_PIN_PB7,
 };
 
+/*
+ * LEDs
+ */
+static struct gpio_led kafa_leds[] = {
+        {       /* D1 */
+                .name                   = "led1",
+                .gpio                   = AT91_PIN_PB4,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+};
+
 static void __init kafa_board_init(void)
 {
-        /* Set up the LEDs */
-        at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4);
-
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -88,6 +97,8 @@ static void __init kafa_board_init(void)
         at91_add_device_i2c(NULL, 0);
         /* SPI */
         at91_add_device_spi(NULL, 0);
+        /* LEDs */
+        at91_gpio_leds(kafa_leds, ARRAY_SIZE(kafa_leds));
 }
 
 MACHINE_START(KAFA, "Sperry-Sun KAFA")
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 5d96cb85175f..abe9fed7a3e0 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -69,12 +69,12 @@ static struct at91_udc_data __initdata kb9202_udc_data = {
         .pullup_pin     = AT91_PIN_PB22,
 };
 
-static struct at91_mmc_data __initdata kb9202_mmc_data = {
-        .det_pin        = AT91_PIN_PB2,
-        .slot_b         = 0,
-        .wire4          = 1,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata kb9202_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PB2,
+                .wp_pin         = -EINVAL,
+        },
 };
 
 static struct mtd_partition __initdata kb9202_nand_partition[] = {
@@ -96,11 +96,26 @@ static struct atmel_nand_data __initdata kb9202_nand_data = {
         .num_parts      = ARRAY_SIZE(kb9202_nand_partition),
 };
 
+/*
+ * LEDs
+ */
+static struct gpio_led kb9202_leds[] = {
+        {       /* D1 */
+                .name                   = "led1",
+                .gpio                   = AT91_PIN_PC19,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+        {       /* D2 */
+                .name                   = "led2",
+                .gpio                   = AT91_PIN_PC18,
+                .active_low             = 1,
+                .default_trigger        = "timer",
+        }
+};
+
 static void __init kb9202_board_init(void)
 {
-        /* Set up the LEDs */
-        at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
-
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -121,13 +136,15 @@ static void __init kb9202_board_init(void)
         /* USB Device */
         at91_add_device_udc(&kb9202_udc_data);
         /* MMC */
-        at91_add_device_mmc(0, &kb9202_mmc_data);
+        at91_add_device_mci(0, &kb9202_mci0_data);
         /* I2C */
         at91_add_device_i2c(NULL, 0);
         /* SPI */
         at91_add_device_spi(NULL, 0);
         /* NAND */
         at91_add_device_nand(&kb9202_nand_data);
+        /* LEDs */
+        at91_gpio_leds(kb9202_leds, ARRAY_SIZE(kb9202_leds));
 }
 
 MACHINE_START(KB9200, "KB920x")
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index 18103c5d993c..9cda3fd346ae 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -138,11 +138,12 @@ static struct spi_board_info neocore926_spi_devices[] = {
 /*
  * MCI (SD/MMC)
  */
-static struct at91_mmc_data __initdata neocore926_mmc_data = {
-        .wire4          = 1,
-        .det_pin        = AT91_PIN_PE18,
-        .wp_pin         = AT91_PIN_PE19,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata neocore926_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PE18,
+                .wp_pin         = AT91_PIN_PE19,
+        },
 };
 
 
@@ -354,7 +355,7 @@ static void __init neocore926_board_init(void)
         neocore926_add_device_ts();
 
         /* MMC */
-        at91_add_device_mmc(1, &neocore926_mmc_data);
+        at91_add_device_mci(0, &neocore926_mci0_data);
 
         /* Ethernet */
         at91_add_device_eth(&neocore926_macb_data);
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 127065504508..f83e1de699e6 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -62,12 +62,12 @@ static struct at91_usbh_data __initdata picotux200_usbh_data = {
         .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
-static struct at91_mmc_data __initdata picotux200_mmc_data = {
-        .det_pin        = AT91_PIN_PB27,
-        .slot_b         = 0,
-        .wire4          = 1,
-        .wp_pin         = AT91_PIN_PA17,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata picotux200_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PB27,
+                .wp_pin         = AT91_PIN_PA17,
+        },
 };
 
 #define PICOTUX200_FLASH_BASE   AT91_CHIPSELECT_0
@@ -112,7 +112,7 @@ static void __init picotux200_board_init(void)
         at91_add_device_i2c(NULL, 0);
         /* MMC */
         at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
-        at91_add_device_mmc(0, &picotux200_mmc_data);
+        at91_add_device_mci(0, &picotux200_mci0_data);
         /* NOR Flash */
         platform_device_register(&picotux200_flash);
 }
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index bf351e285422..799f214edebe 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -156,12 +156,12 @@ static void __init ek_add_device_nand(void)
 /*
  * MCI (SD/MMC)
  */
-static struct at91_mmc_data __initdata ek_mmc_data = {
-        .slot_b         = 0,
-        .wire4          = 1,
-        .det_pin        = -EINVAL,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata ek_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = -EINVAL,
+                .wp_pin         = -EINVAL,
+        },
 };
 
 /*
@@ -245,7 +245,7 @@ static void __init ek_board_init(void)
         /* Ethernet */
         at91_add_device_eth(&ek_macb_data);
         /* MMC */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        at91_add_device_mci(0, &ek_mci0_data);
         /* Push Buttons */
         ek_add_device_buttons();
         /* LEDs */
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index cc2bf9796073..66338e7ebfba 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -77,12 +77,12 @@ static struct at91_cf_data __initdata dk_cf_data = {
 };
 
 #ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
-static struct at91_mmc_data __initdata dk_mmc_data = {
-        .slot_b         = 0,
-        .wire4          = 1,
-        .det_pin        = -EINVAL,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata dk_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = -EINVAL,
+                .wp_pin         = -EINVAL,
+        },
 };
 #endif
 
@@ -177,9 +177,6 @@ static struct gpio_led dk_leds[] = {
 
 static void __init dk_board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
-
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -208,7 +205,7 @@ static void __init dk_board_init(void)
 #else
         /* MMC */
         at91_set_gpio_output(AT91_PIN_PB7, 1);  /* this MMC card slot can optionally use SPI signaling (CS3). */
-        at91_add_device_mmc(0, &dk_mmc_data);
+        at91_add_device_mci(0, &dk_mci0_data);
 #endif
         /* NAND */
         at91_add_device_nand(&dk_nand_data);
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 62e19e64c9d3..5d1b5729dc69 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -70,12 +70,12 @@ static struct at91_udc_data __initdata ek_udc_data = {
 };
 
 #ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
-static struct at91_mmc_data __initdata ek_mmc_data = {
-        .det_pin        = AT91_PIN_PB27,
-        .slot_b         = 0,
-        .wire4          = 1,
-        .wp_pin         = AT91_PIN_PA17,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata ek_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PB27,
+                .wp_pin         = AT91_PIN_PA17,
+        }
 };
 #endif
 
@@ -148,9 +148,6 @@ static struct gpio_led ek_leds[] = {
 
 static void __init ek_board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
-
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -177,7 +174,7 @@ static void __init ek_board_init(void)
 #else
         /* MMC */
         at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        at91_add_device_mci(0, &ek_mci0_data);
 #endif
         /* NOR Flash */
         platform_device_register(&ek_flash);
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index c3b43aefdb75..a0ecf04e9ae3 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -58,11 +58,12 @@ static struct at91_usbh_data rsi_ews_usbh_data __initdata = {
 /*
  * SD/MC
  */
-static struct at91_mmc_data rsi_ews_mmc_data __initdata = {
-        .slot_b         = 0,
-        .wire4          = 1,
-        .det_pin        = AT91_PIN_PB27,
-        .wp_pin         = AT91_PIN_PB29,
+static struct mci_platform_data __initdata rsi_ews_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PB27,
+                .wp_pin         = AT91_PIN_PB29,
+        },
 };
 
 /*
@@ -185,9 +186,6 @@ static struct platform_device rsiews_nor_flash = {
  */
 static void __init rsi_ews_board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9);
-
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         /* This one is for debugging */
@@ -215,7 +213,7 @@ static void __init rsi_ews_board_init(void)
         at91_add_device_spi(rsi_ews_spi_devices,
                         ARRAY_SIZE(rsi_ews_spi_devices));
         /* MMC */
-        at91_add_device_mmc(0, &rsi_ews_mmc_data);
+        at91_add_device_mci(0, &rsi_ews_mci0_data);
         /* NOR Flash */
         platform_device_register(&rsiews_nor_flash);
         /* LEDs */
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 7bf6da70d7d5..c5f01acce3c0 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -73,7 +73,7 @@ static struct at91_udc_data __initdata ek_udc_data = {
  * SPI devices.
  */
 static struct spi_board_info ek_spi_devices[] = {
-#if !defined(CONFIG_MMC_AT91)
+#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
         {       /* DataFlash chip */
                 .modalias       = "mtd_dataflash",
                 .chip_select    = 1,
@@ -158,19 +158,34 @@ static void __init ek_add_device_nand(void)
 /*
  * MCI (SD/MMC)
  */
-static struct at91_mmc_data __initdata ek_mmc_data = {
-        .slot_b         = 1,
-        .wire4          = 1,
-        .det_pin        = AT91_PIN_PC8,
-        .wp_pin         = AT91_PIN_PC4,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata ek_mci0_data = {
+        .slot[1] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PC8,
+                .wp_pin         = AT91_PIN_PC4,
+        },
+};
+
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* D1 */
+                .name                   = "led1",
+                .gpio                   = AT91_PIN_PA9,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+        {       /* D2 */
+                .name                   = "led2",
+                .gpio                   = AT91_PIN_PA6,
+                .active_low             = 1,
+                .default_trigger        = "timer",
+        }
 };
 
 static void __init ek_board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6);
-
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -194,9 +209,11 @@ static void __init ek_board_init(void)
         /* Ethernet */
         at91_add_device_eth(&ek_macb_data);
         /* MMC */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        at91_add_device_mci(0, &ek_mci0_data);
         /* I2C */
         at91_add_device_i2c(NULL, 0);
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
 }
 
 MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 889c1bf71eb5..8cd6e679fbe0 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -108,7 +108,7 @@ static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
  * SPI devices.
  */
 static struct spi_board_info ek_spi_devices[] = {
-#if !defined(CONFIG_MMC_AT91)
+#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
         {       /* DataFlash chip */
                 .modalias       = "mtd_dataflash",
                 .chip_select    = 1,
@@ -211,12 +211,12 @@ static void __init ek_add_device_nand(void)
 /*
  * MCI (SD/MMC)
  */
-static struct at91_mmc_data __initdata ek_mmc_data = {
-        .slot_b         = 1,
-        .wire4          = 1,
-        .det_pin        = -EINVAL,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata ek_mci0_data = {
+        .slot[1] = {
+                .bus_width      = 4,
+                .detect_pin     = -EINVAL,
+                .wp_pin         = -EINVAL,
+        },
 };
 
 
@@ -329,7 +329,7 @@ static void __init ek_board_init(void)
         /* Ethernet */
         at91_add_device_eth(&ek_macb_data);
         /* MMC */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        at91_add_device_mci(0, &ek_mci0_data);
         /* I2C */
         at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
         /* SSC (to AT73C213) */
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 2269be5fa384..27b3af1a3047 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -340,11 +340,12 @@ static struct spi_board_info ek_spi_devices[] = {
  * MCI (SD/MMC)
  * det_pin, wp_pin and vcc_pin are not connected
  */
-static struct at91_mmc_data __initdata ek_mmc_data = {
-        .wire4          = 1,
-        .det_pin        = -EINVAL,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = -EINVAL,
+                .wp_pin         = -EINVAL,
+        },
 };
 
 #endif /* CONFIG_SPI_ATMEL_* */
@@ -569,9 +570,6 @@ static struct gpio_led ek_leds[] = {
 
 static void __init ek_board_init(void)
 {
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
-
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -598,7 +596,7 @@ static void __init ek_board_init(void)
         at91_add_device_ssc(AT91SAM9261_ID_SSC1, ATMEL_SSC_TX);
 #else
         /* MMC */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        at91_add_device_mci(0, &mci0_data);
 #endif
         /* LCD Controller */
         at91_add_device_lcdc(&ek_lcdc_data);
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 82adf581afc2..073e17403d98 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -141,11 +141,12 @@ static struct spi_board_info ek_spi_devices[] = {
 /*
  * MCI (SD/MMC)
  */
-static struct at91_mmc_data __initdata ek_mmc_data = {
-        .wire4          = 1,
-        .det_pin        = AT91_PIN_PE18,
-        .wp_pin         = AT91_PIN_PE19,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata mci1_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PE18,
+                .wp_pin         = AT91_PIN_PE19,
+        },
 };
 
 
@@ -420,7 +421,7 @@ static void __init ek_board_init(void)
         /* Touchscreen */
         ek_add_device_ts();
         /* MMC */
-        at91_add_device_mmc(1, &ek_mmc_data);
+        at91_add_device_mci(1, &mci1_data);
         /* Ethernet */
         at91_add_device_eth(&ek_macb_data);
         /* NAND */
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 4ea4ee00364b..3ab2b86a3762 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -92,7 +92,7 @@ static struct at91_udc_data __initdata ek_udc_data = {
  * SPI devices.
  */
 static struct spi_board_info ek_spi_devices[] = {
-#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91))
+#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
         {       /* DataFlash chip */
                 .modalias       = "mtd_dataflash",
                 .chip_select    = 1,
@@ -199,7 +199,6 @@ static void __init ek_add_device_nand(void)
  * MCI (SD/MMC)
  * wp_pin and vcc_pin are not connected
  */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
 static struct mci_platform_data __initdata ek_mmc_data = {
         .slot[1] = {
                 .bus_width      = 4,
@@ -208,28 +207,15 @@ static struct mci_platform_data __initdata ek_mmc_data = {
         },
 
 };
-#else
-static struct at91_mmc_data __initdata ek_mmc_data = {
-        .slot_b         = 1,    /* Only one slot so use slot B */
-        .wire4          = 1,
-        .det_pin        = AT91_PIN_PC9,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
-};
-#endif
 
 static void __init ek_add_device_mmc(void)
 {
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
         if (ek_have_2mmc()) {
                 ek_mmc_data.slot[0].bus_width = 4;
                 ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2;
                 ek_mmc_data.slot[0].wp_pin = -1;
         }
         at91_add_device_mci(0, &ek_mmc_data);
-#else
-        at91_add_device_mmc(0, &ek_mmc_data);
-#endif
 }
 
 /*
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index e7dc3ead7045..fb89ea92e3f2 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -56,11 +56,12 @@ static struct usba_platform_data __initdata ek_usba_udc_data = {
 /*
  * MCI (SD/MMC)
  */
-static struct at91_mmc_data __initdata ek_mmc_data = {
-        .wire4          = 1,
-        .det_pin        = AT91_PIN_PA15,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PA15,
+                .wp_pin         = -EINVAL,
+        },
 };
 
 
@@ -303,7 +304,7 @@ static void __init ek_board_init(void)
         /* SPI */
         at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
         /* MMC */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        at91_add_device_mci(0, &mci0_data);
         /* LCD Controller */
         at91_add_device_lcdc(&ek_lcdc_data);
         /* AC97 */
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 29eae1626bf7..c3fb31d5116e 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -83,7 +83,6 @@ static void __init add_device_nand(void)
  * MCI (SD/MMC)
  * det_pin, wp_pin and vcc_pin are not connected
  */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
 static struct mci_platform_data __initdata mmc_data = {
         .slot[0] = {
                 .bus_width      = 4,
@@ -91,15 +90,6 @@ static struct mci_platform_data __initdata mmc_data = {
                 .wp_pin         = -1,
         },
 };
-#else
-static struct at91_mmc_data __initdata mmc_data = {
-        .slot_b         = 0,
-        .wire4          = 1,
-        .det_pin        = -EINVAL,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
-};
-#endif
 
 
 /*
@@ -223,11 +213,7 @@ void __init stamp9g20_board_init(void)
         /* NAND */
         add_device_nand();
         /* MMC */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
         at91_add_device_mci(0, &mmc_data);
-#else
-        at91_add_device_mmc(0, &mmc_data);
-#endif
         /* W1 */
         add_w1();
 }
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index c1476b9fe7b9..6ea069b57335 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -109,14 +109,12 @@ static struct mmc_spi_platform_data at91_mmc_spi_pdata = {
  * SPI devices.
  */
 static struct spi_board_info usb_a9263_spi_devices[] = {
-#if !defined(CONFIG_MMC_AT91)
         {       /* DataFlash chip */
                 .modalias       = "mtd_dataflash",
                 .chip_select    = 0,
                 .max_speed_hz   = 15 * 1000 * 1000,
                 .bus_num        = 0,
         }
-#endif
 };
 
 static struct spi_board_info usb_a9g20_spi_devices[] = {
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 516d340549d8..f162fdfd66eb 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -119,11 +119,12 @@ static struct at91_udc_data __initdata yl9200_udc_data = {
 /*
  * MMC
  */
-static struct at91_mmc_data __initdata yl9200_mmc_data = {
-        .det_pin        = AT91_PIN_PB9,
-        .wire4          = 1,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
+static struct mci_platform_data __initdata yl9200_mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PB9,
+                .wp_pin         = -EINVAL,
+        },
 };
 
 /*
@@ -541,9 +542,6 @@ void __init yl9200_add_device_video(void) {}
 
 static void __init yl9200_board_init(void)
 {
-        /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
-        at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
-
         /* Serial */
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -568,7 +566,7 @@ static void __init yl9200_board_init(void)
         /* I2C */
         at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
         /* MMC */
-        at91_add_device_mmc(0, &yl9200_mmc_data);
+        at91_add_device_mci(0, &yl9200_mci0_data);
         /* NAND */
         at91_add_device_nand(&yl9200_nand_data);
         /* NOR Flash */
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 188c82971ebd..33361505c0cd 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -625,7 +625,7 @@ fail:
         return 0;
 }
 
-static struct clk *const standard_pmc_clocks[] __initdata = {
+static struct clk *const standard_pmc_clocks[] __initconst = {
         /* four primary clocks */
         &clk32k,
         &main_clk,
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 369afc2ffc5b..c55a4364ffb4 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -187,7 +187,6 @@ struct at91_can_data {
 extern void __init at91_add_device_can(struct at91_can_data *data);
 
  /* LEDs */
-extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
 extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
 extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
 
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
index 8dfafe76ffe6..1b1e62b5f41b 100644
--- a/arch/arm/mach-at91/leds.c
+++ b/arch/arm/mach-at91/leds.c
@@ -90,108 +90,3 @@ void __init at91_pwm_leds(struct gpio_led *leds, int nr)
 #else
 void __init at91_pwm_leds(struct gpio_led *leds, int nr){}
 #endif
-
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_LEDS)
-
-#include <asm/leds.h>
-
-/*
- * Old ARM-specific LED framework; not fully functional when generic time is
- * in use.
- */
-
-static u8 at91_leds_cpu;
-static u8 at91_leds_timer;
-
-static inline void at91_led_on(unsigned int led)
-{
-        at91_set_gpio_value(led, 0);
-}
-
-static inline void at91_led_off(unsigned int led)
-{
-        at91_set_gpio_value(led, 1);
-}
-
-static inline void at91_led_toggle(unsigned int led)
-{
-        unsigned long is_off = at91_get_gpio_value(led);
-        if (is_off)
-                at91_led_on(led);
-        else
-                at91_led_off(led);
-}
-
-
-/*
- * Handle LED events.
- */
-static void at91_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        switch(evt) {
-        case led_start:         /* System startup */
-                at91_led_on(at91_leds_cpu);
-                break;
-
-        case led_stop:          /* System stop / suspend */
-                at91_led_off(at91_leds_cpu);
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:         /* Every 50 timer ticks */
-                at91_led_toggle(at91_leds_timer);
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:    /* Entering idle state */
-                at91_led_off(at91_leds_cpu);
-                break;
-
-        case led_idle_end:      /* Exit idle state */
-                at91_led_on(at91_leds_cpu);
-                break;
-#endif
-
-        default:
-                break;
-        }
-
-        local_irq_restore(flags);
-}
-
-
-static int __init leds_init(void)
-{
-        if (!at91_leds_timer || !at91_leds_cpu)
-                return -ENODEV;
-
-        leds_event = at91_leds_event;
-
-        leds_event(led_start);
-        return 0;
-}
-
-__initcall(leds_init);
-
-
-void __init at91_init_leds(u8 cpu_led, u8 timer_led)
-{
-        /* Enable GPIO to access the LEDs */
-        at91_set_gpio_output(cpu_led, 1);
-        at91_set_gpio_output(timer_led, 1);
-
-        at91_leds_cpu   = cpu_led;
-        at91_leds_timer = timer_led;
-}
-
-#else
-void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
-#endif
diff --git a/arch/arm/mach-bcmring/Kconfig b/arch/arm/mach-bcmring/Kconfig
deleted file mode 100644
index 9170d16dca50..000000000000
--- a/arch/arm/mach-bcmring/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-choice
-        prompt "Processor selection in BCMRING family of devices"
-        depends on ARCH_BCMRING
-        default ARCH_BCM11107
-
-config ARCH_FPGA11107
-        bool "FPGA11107"
-
-config ARCH_BCM11107
-        bool "BCM11107"
-endchoice
-
-menu "BCMRING Options"
-        depends on ARCH_BCMRING
-
-config BCM_ZRELADDR
-        hex "Compressed ZREL ADDR"
-
-endmenu
diff --git a/arch/arm/mach-bcmring/Makefile b/arch/arm/mach-bcmring/Makefile
deleted file mode 100644
index f8d9fcedf917..000000000000
--- a/arch/arm/mach-bcmring/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o
-obj-y += csp/
diff --git a/arch/arm/mach-bcmring/Makefile.boot b/arch/arm/mach-bcmring/Makefile.boot
deleted file mode 100644
index aef2467757fa..000000000000
--- a/arch/arm/mach-bcmring/Makefile.boot
+++ /dev/null
@@ -1,6 +0,0 @@
-# Address where decompressor will be written and eventually executed.
-#
-# default to SDRAM
-zreladdr-y      += $(CONFIG_BCM_ZRELADDR)
-params_phys-y   := 0x00000800
-
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
deleted file mode 100644
index c18a5048b6c5..000000000000
--- a/arch/arm/mach-bcmring/arch.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-
-#include <linux/proc_fs.h>
-#include <linux/sysctl.h>
-
-#include <asm/irq.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/time.h>
-
-#include <asm/mach/arch.h>
-#include <mach/dma.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <mach/cfg_global.h>
-
-#include "core.h"
-
-HW_DECLARE_SPINLOCK(arch)
-HW_DECLARE_SPINLOCK(gpio)
-#if defined(CONFIG_DEBUG_SPINLOCK)
-    EXPORT_SYMBOL(bcmring_gpio_reg_lock);
-#endif
-
-/* sysctl */
-static int bcmring_arch_warm_reboot;    /* do a warm reboot on hard reset */
-
-static void bcmring_restart(char mode, const char *cmd)
-{
-        printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
-
-        if (mode == 'h') {
-                /* Reboot configured in proc entry */
-                if (bcmring_arch_warm_reboot) {
-                        printk("warm reset\n");
-                        /* Issue Warm reset (do not reset ethernet switch, keep alive) */
-                        chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
-                } else {
-                        /* Force reset of everything */
-                        printk("force reset\n");
-                        chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-                }
-        } else {
-                /* Force reset of everything */
-                printk("force reset\n");
-                chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-        }
-}
-
-static struct ctl_table_header *bcmring_sysctl_header;
-
-static struct ctl_table bcmring_sysctl_warm_reboot[] = {
-        {
-         .procname = "warm",
-         .data = &bcmring_arch_warm_reboot,
-         .maxlen = sizeof(int),
-         .mode = 0644,
-         .proc_handler = proc_dointvec},
-        {}
-};
-
-static struct ctl_table bcmring_sysctl_reboot[] = {
-        {
-         .procname = "reboot",
-         .mode = 0555,
-         .child = bcmring_sysctl_warm_reboot},
-        {}
-};
-
-static struct resource nand_resource[] = {
-        [0] = {
-                .start = MM_ADDR_IO_NAND,
-                .end = MM_ADDR_IO_NAND + 0x1000 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device nand_device = {
-        .name = "bcm-nand",
-        .id = -1,
-        .resource = nand_resource,
-        .num_resources  = ARRAY_SIZE(nand_resource),
-};
-
-static struct resource pmu_resource = {
-        .start  = IRQ_PMUIRQ,
-        .end    = IRQ_PMUIRQ,
-        .flags  = IORESOURCE_IRQ,
-};
-
-static struct platform_device pmu_device = {
-        .name           = "arm-pmu",
-        .id             = -1,
-        .resource       = &pmu_resource,
-        .num_resources  = 1,
-};
-
-
-static struct platform_device *devices[] __initdata = {
-        &nand_device,
-        &pmu_device,
-};
-
-/****************************************************************************
-*
-*   Called from the customize_machine function in arch/arm/kernel/setup.c
-*
-*   The customize_machine function is tagged as an arch_initcall
-*   (see include/linux/init.h for the order that the various init sections
-*   are called in.
-*
-*****************************************************************************/
-static void __init bcmring_init_machine(void)
-{
-
-        bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot);
-
-        /* Enable spread spectrum */
-        chipcHw_enableSpreadSpectrum();
-
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-
-        bcmring_amba_init();
-
-        dma_init();
-}
-
-/****************************************************************************
-*
-*   Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags
-*   passed in by the boot loader.
-*
-*****************************************************************************/
-
-static void __init bcmring_fixup(struct tag *t, char **cmdline,
-        struct meminfo *mi) {
-#ifdef CONFIG_BLK_DEV_INITRD
-        printk(KERN_NOTICE "bcmring_fixup\n");
-        t->hdr.tag = ATAG_CORE;
-        t->hdr.size = tag_size(tag_core);
-        t->u.core.flags = 0;
-        t->u.core.pagesize = PAGE_SIZE;
-        t->u.core.rootdev = 31 << 8 | 0;
-        t = tag_next(t);
-
-        t->hdr.tag = ATAG_MEM;
-        t->hdr.size = tag_size(tag_mem32);
-        t->u.mem.start = CFG_GLOBAL_RAM_BASE;
-        t->u.mem.size = CFG_GLOBAL_RAM_SIZE;
-
-        t = tag_next(t);
-
-        t->hdr.tag = ATAG_NONE;
-        t->hdr.size = 0;
-#endif
-}
-
-/****************************************************************************
-*
-*   Machine Description
-*
-*****************************************************************************/
-
-MACHINE_START(BCMRING, "BCMRING")
-        /* Maintainer: Broadcom Corporation */
-        .fixup = bcmring_fixup,
-        .map_io = bcmring_map_io,
-        .init_early = bcmring_init_early,
-        .init_irq = bcmring_init_irq,
-        .timer = &bcmring_timer,
-        .init_machine = bcmring_init_machine,
-        .restart = bcmring_restart,
-MACHINE_END
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
deleted file mode 100644
index ad237a42d265..000000000000
--- a/arch/arm/mach-bcmring/clock.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/clkdev.h>
-#include <mach/csp/hw_cfg.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include "clock.h"
-
-#define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
-#define clk_is_pll1(x)          ((x)->type & CLK_TYPE_PLL1)
-#define clk_is_pll2(x)          ((x)->type & CLK_TYPE_PLL2)
-#define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
-#define clk_is_bypassable(x)    ((x)->type & CLK_TYPE_BYPASSABLE)
-
-#define clk_is_using_xtal(x)    ((x)->mode & CLK_MODE_XTAL)
-
-static DEFINE_SPINLOCK(clk_lock);
-
-static void __clk_enable(struct clk *clk)
-{
-        if (!clk)
-                return;
-
-        /* enable parent clock first */
-        if (clk->parent)
-                __clk_enable(clk->parent);
-
-        if (clk->use_cnt++ == 0) {
-                if (clk_is_pll1(clk)) { /* PLL1 */
-                        chipcHw_pll1Enable(clk->rate_hz, 0);
-                } else if (clk_is_pll2(clk)) {  /* PLL2 */
-                        chipcHw_pll2Enable(clk->rate_hz);
-                } else if (clk_is_using_xtal(clk)) {    /* source is crystal */
-                        if (!clk_is_primary(clk))
-                                chipcHw_bypassClockEnable(clk->csp_id);
-                } else {        /* source is PLL */
-                        chipcHw_setClockEnable(clk->csp_id);
-                }
-        }
-}
-
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-
-        if (!clk)
-                return -EINVAL;
-
-        spin_lock_irqsave(&clk_lock, flags);
-        __clk_enable(clk);
-        spin_unlock_irqrestore(&clk_lock, flags);
-
-        return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void __clk_disable(struct clk *clk)
-{
-        if (!clk)
-                return;
-
-        BUG_ON(clk->use_cnt == 0);
-
-        if (--clk->use_cnt == 0) {
-                if (clk_is_pll1(clk)) { /* PLL1 */
-                        chipcHw_pll1Disable();
-                } else if (clk_is_pll2(clk)) {  /* PLL2 */
-                        chipcHw_pll2Disable();
-                } else if (clk_is_using_xtal(clk)) {    /* source is crystal */
-                        if (!clk_is_primary(clk))
-                                chipcHw_bypassClockDisable(clk->csp_id);
-                } else {        /* source is PLL */
-                        chipcHw_setClockDisable(clk->csp_id);
-                }
-        }
-
-        if (clk->parent)
-                __clk_disable(clk->parent);
-}
-
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-
-        if (!clk)
-                return;
-
-        spin_lock_irqsave(&clk_lock, flags);
-        __clk_disable(clk);
-        spin_unlock_irqrestore(&clk_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-        if (!clk)
-                return 0;
-
-        return clk->rate_hz;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long flags;
-        unsigned long actual;
-        unsigned long rate_hz;
-
-        if (!clk)
-                return -EINVAL;
-
-        if (!clk_is_programmable(clk))
-                return -EINVAL;
-
-        if (clk->use_cnt)
-                return -EBUSY;
-
-        spin_lock_irqsave(&clk_lock, flags);
-        actual = clk->parent->rate_hz;
-        rate_hz = min(actual, rate);
-        spin_unlock_irqrestore(&clk_lock, flags);
-
-        return rate_hz;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long flags;
-        unsigned long actual;
-        unsigned long rate_hz;
-
-        if (!clk)
-                return -EINVAL;
-
-        if (!clk_is_programmable(clk))
-                return -EINVAL;
-
-        if (clk->use_cnt)
-                return -EBUSY;
-
-        spin_lock_irqsave(&clk_lock, flags);
-        actual = clk->parent->rate_hz;
-        rate_hz = min(actual, rate);
-        rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
-        clk->rate_hz = rate_hz;
-        spin_unlock_irqrestore(&clk_lock, flags);
-
-        return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
-        if (!clk)
-                return NULL;
-
-        return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        unsigned long flags;
-        struct clk *old_parent;
-
-        if (!clk || !parent)
-                return -EINVAL;
-
-        if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
-                return -EINVAL;
-
-        /* if more than one user, parent is not allowed */
-        if (clk->use_cnt > 1)
-                return -EBUSY;
-
-        if (clk->parent == parent)
-                return 0;
-
-        spin_lock_irqsave(&clk_lock, flags);
-        old_parent = clk->parent;
-        clk->parent = parent;
-        if (clk_is_using_xtal(parent))
-                clk->mode |= CLK_MODE_XTAL;
-        else
-                clk->mode &= (~CLK_MODE_XTAL);
-
-        /* if clock is active */
-        if (clk->use_cnt != 0) {
-                clk->use_cnt--;
-                /* enable clock with the new parent */
-                __clk_enable(clk);
-                /* disable the old parent */
-                __clk_disable(old_parent);
-        }
-        spin_unlock_irqrestore(&clk_lock, flags);
-
-        return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h
deleted file mode 100644
index 5e0b98138973..000000000000
--- a/arch/arm/mach-bcmring/clock.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <mach/csp/chipcHw_def.h>
-
-#define CLK_TYPE_PRIMARY         1      /* primary clock must NOT have a parent */
-#define CLK_TYPE_PLL1            2      /* PPL1 */
-#define CLK_TYPE_PLL2            4      /* PPL2 */
-#define CLK_TYPE_PROGRAMMABLE    8      /* programmable clock rate */
-#define CLK_TYPE_BYPASSABLE      16     /* parent can be changed */
-
-#define CLK_MODE_XTAL            1      /* clock source is from crystal */
-
-struct clk {
-        const char *name;       /* clock name */
-        unsigned int type;      /* clock type */
-        unsigned int mode;      /* current mode */
-        volatile int use_bypass;        /* indicate if it's in bypass mode */
-        chipcHw_CLOCK_e csp_id; /* clock ID for CSP CHIPC */
-        unsigned long rate_hz;  /* clock rate in Hz */
-        unsigned int use_cnt;   /* usage count */
-        struct clk *parent;     /* parent clock */
-};
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
deleted file mode 100644
index 4b50228a6771..000000000000
--- a/arch/arm/mach-bcmring/core.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- *  derived from linux/arch/arm/mach-versatile/core.c
- *  linux/arch/arm/mach-bcmring/core.c
- *
- *  Copyright (C) 1999 - 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/* Portions copyright Broadcom 2008 */
-
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/amba/bus.h>
-#include <linux/clkdev.h>
-
-#include <mach/csp/mm_addr.h>
-#include <mach/hardware.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/hardware/arm_timer.h>
-#include <asm/hardware/timer-sp.h>
-#include <asm/mach-types.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include <mach/cfg_global.h>
-
-#include "clock.h"
-
-#include <mach/csp/secHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <mach/csp/tmrHw_reg.h>
-
-static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
-static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
-
-static struct clk pll1_clk = {
-        .name = "PLL1",
-        .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
-        .rate_hz = 2000000000,
-        .use_cnt = 7,
-};
-
-static struct clk uart_clk = {
-        .name = "UART",
-        .type = CLK_TYPE_PROGRAMMABLE,
-        .csp_id = chipcHw_CLOCK_UART,
-        .rate_hz = HW_CFG_UART_CLK_HZ,
-        .parent = &pll1_clk,
-};
-
-static struct clk dummy_apb_pclk = {
-        .name = "BUSCLK",
-        .type = CLK_TYPE_PRIMARY,
-        .mode = CLK_MODE_XTAL,
-};
-
-/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically  150-166 MHz */
-#if defined(CONFIG_ARCH_FPGA11107)
-/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
-/* slow down Linux's sense of time */
-#define TIMER0_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
-#define TIMER1_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
-#define TIMER3_FREQUENCY_MHZ  (tmrHw_HIGH_FREQUENCY_MHZ * 30)
-#define TIMER3_FREQUENCY_KHZ   (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
-#else
-#define TIMER0_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
-#define TIMER1_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
-#define TIMER3_FREQUENCY_MHZ  tmrHw_HIGH_FREQUENCY_MHZ
-#define TIMER3_FREQUENCY_KHZ  (tmrHw_HIGH_FREQUENCY_HZ / 1000)
-#endif
-
-static struct clk sp804_timer012_clk = {
-        .name = "sp804-timer-0,1,2",
-        .type = CLK_TYPE_PRIMARY,
-        .mode = CLK_MODE_XTAL,
-        .rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
-};
-
-static struct clk sp804_timer3_clk = {
-        .name = "sp804-timer-3",
-        .type = CLK_TYPE_PRIMARY,
-        .mode = CLK_MODE_XTAL,
-        .rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
-};
-
-static struct clk_lookup lookups[] = {
-        {                       /* Bus clock */
-                .con_id = "apb_pclk",
-                .clk = &dummy_apb_pclk,
-        }, {                    /* UART0 */
-                .dev_id = "uarta",
-                .clk = &uart_clk,
-        }, {                    /* UART1 */
-                .dev_id = "uartb",
-                .clk = &uart_clk,
-        }, {                    /* SP804 timer 0 */
-                .dev_id = "sp804",
-                .con_id = "timer0",
-                .clk = &sp804_timer012_clk,
-        }, {                    /* SP804 timer 1 */
-                .dev_id = "sp804",
-                .con_id = "timer1",
-                .clk = &sp804_timer012_clk,
-        }, {                    /* SP804 timer 3 */
-                .dev_id = "sp804",
-                .con_id = "timer3",
-                .clk = &sp804_timer3_clk,
-        }
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-        &uartA_device,
-        &uartB_device,
-};
-
-void __init bcmring_amba_init(void)
-{
-        int i;
-        u32 bus_clock;
-
-/* Linux is run initially in non-secure mode. Secure peripherals */
-/* generate FIQ, and must be handled in secure mode. Until we have */
-/* a linux security monitor implementation, keep everything in */
-/* non-secure mode. */
-        chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
-        secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
-                          secHw_BLK_MASK_KEY_SCAN |
-                          secHw_BLK_MASK_TOUCH_SCREEN |
-                          secHw_BLK_MASK_UART0 |
-                          secHw_BLK_MASK_UART1 |
-                          secHw_BLK_MASK_WATCHDOG |
-                          secHw_BLK_MASK_SPUM |
-                          secHw_BLK_MASK_DDR2 |
-                          secHw_BLK_MASK_SPU |
-                          secHw_BLK_MASK_PKA |
-                          secHw_BLK_MASK_RNG |
-                          secHw_BLK_MASK_RTC |
-                          secHw_BLK_MASK_OTP |
-                          secHw_BLK_MASK_BOOT |
-                          secHw_BLK_MASK_MPU |
-                          secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
-
-        /* Only the devices attached to the AMBA bus are enabled just before the bus is */
-        /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
-        /* driver to access these blocks. The bus is probed, and the drivers are loaded. */
-        /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
-        bus_clock = chipcHw_REG_BUS_CLOCK_GE
-            | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
-
-        chipcHw_busInterfaceClockEnable(bus_clock);
-
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-                struct amba_device *d = amba_devs[i];
-                amba_device_register(d, &iomem_resource);
-        }
-}
-
-/*
- * Where is the timer (VA)?
- */
-#define TIMER0_VA_BASE          ((void __iomem *)MM_IO_BASE_TMR)
-#define TIMER1_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x20))
-#define TIMER2_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
-#define TIMER3_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
-
-static int __init bcmring_clocksource_init(void)
-{
-        /* setup timer1 as free-running clocksource */
-        sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
-
-        /* setup timer3 as free-running clocksource */
-        sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
-
-        return 0;
-}
-
-/*
- * Set up timer interrupt, and return the current time in seconds.
- */
-void __init bcmring_init_timer(void)
-{
-        printk(KERN_INFO "bcmring_init_timer\n");
-        /*
-         * Initialise to a known state (all timers off)
-         */
-        writel(0, TIMER0_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER2_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
-
-        /*
-         * Make irqs happen for the system timer
-         */
-        bcmring_clocksource_init();
-
-        sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
-}
-
-struct sys_timer bcmring_timer = {
-        .init = bcmring_init_timer,
-};
-
-void __init bcmring_init_early(void)
-{
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-}
diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h
deleted file mode 100644
index e0e02c48f9b1..000000000000
--- a/arch/arm/mach-bcmring/core.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *  linux/arch/arm/mach-versatile/core.h
- *
- *  Copyright (C) 2004 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/* Portions copyright Broadcom 2008 */
-#ifndef __ASM_ARCH_BCMRING_H
-#define __ASM_ARCH_BCMRING_H
-
-void __init bcmring_amba_init(void);
-void __init bcmring_map_io(void);
-void __init bcmring_init_irq(void);
-void __init bcmring_init_early(void);
-
-extern struct sys_timer bcmring_timer;
-#endif
diff --git a/arch/arm/mach-bcmring/csp/Makefile b/arch/arm/mach-bcmring/csp/Makefile
deleted file mode 100644
index 648c0377530e..000000000000
--- a/arch/arm/mach-bcmring/csp/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-obj-y += dmac/
-obj-y += tmr/
-obj-y += chipc/
diff --git a/arch/arm/mach-bcmring/csp/chipc/Makefile b/arch/arm/mach-bcmring/csp/chipc/Makefile
deleted file mode 100644
index 673952768ee5..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
deleted file mode 100644
index 5050833817b7..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
+++ /dev/null
@@ -1,779 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw.c
-*
-*  @brief   Low level Various CHIP clock controlling routines
-*
-*  @note
-*
-*   These routines provide basic clock controlling functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <linux/errno.h>
-#include <linux/types.h>
-#include <linux/export.h>
-
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <mach/csp/reg.h>
-#include <linux/delay.h>
-
-/* ---- Private Constants and Types --------------------------------------- */
-
-/* VPM alignment algorithm uses this */
-#define MAX_PHASE_ADJUST_COUNT         0xFFFF   /* Max number of times allowed to adjust the phase */
-#define MAX_PHASE_ALIGN_ATTEMPTS       10       /* Max number of attempt to align the phase */
-
-/* Local definition of clock type */
-#define PLL_CLOCK                      1        /* PLL Clock */
-#define NON_PLL_CLOCK                  2        /* Divider clock */
-
-static int chipcHw_divide(int num, int denom)
-    __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in hertz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock    /*  [ IN ] Configurable clock */
-    ) {
-        uint32_t __iomem *pPLLReg = NULL;
-        uint32_t __iomem *pClockCtrl = NULL;
-        uint32_t __iomem *pDependentClock = NULL;
-        uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
-        uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
-        uint32_t dependentClockType = 0;
-        uint32_t vcoHz = 0;
-
-        /* Get VCO frequencies */
-        if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-                uint64_t adjustFreq = 0;
-
-                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-                /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
-                adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
-                        (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
-                        chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
-                vcoFreqPll1Hz += (uint32_t) adjustFreq;
-        } else {
-                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-        }
-        vcoFreqPll2Hz =
-            chipcHw_XTAL_FREQ_Hz *
-                 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-            ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-        switch (clock) {
-        case chipcHw_CLOCK_DDR:
-                pPLLReg = &pChipcHw->DDRClock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ARM:
-                pPLLReg = &pChipcHw->ARMClock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ESW:
-                pPLLReg = &pChipcHw->ESWClock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_VPM:
-                pPLLReg = &pChipcHw->VPMClock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ESW125:
-                pPLLReg = &pChipcHw->ESW125Clock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_UART:
-                pPLLReg = &pChipcHw->UARTClock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_SDIO0:
-                pPLLReg = &pChipcHw->SDIO0Clock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_SDIO1:
-                pPLLReg = &pChipcHw->SDIO1Clock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_SPI:
-                pPLLReg = &pChipcHw->SPIClock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ETM:
-                pPLLReg = &pChipcHw->ETMClock;
-                vcoHz = vcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_USB:
-                pPLLReg = &pChipcHw->USBClock;
-                vcoHz = vcoFreqPll2Hz;
-                break;
-        case chipcHw_CLOCK_LCD:
-                pPLLReg = &pChipcHw->LCDClock;
-                vcoHz = vcoFreqPll2Hz;
-                break;
-        case chipcHw_CLOCK_APM:
-                pPLLReg = &pChipcHw->APMClock;
-                vcoHz = vcoFreqPll2Hz;
-                break;
-        case chipcHw_CLOCK_BUS:
-                pClockCtrl = &pChipcHw->ACLKClock;
-                pDependentClock = &pChipcHw->ARMClock;
-                vcoHz = vcoFreqPll1Hz;
-                dependentClockType = PLL_CLOCK;
-                break;
-        case chipcHw_CLOCK_OTP:
-                pClockCtrl = &pChipcHw->OTPClock;
-                break;
-        case chipcHw_CLOCK_I2C:
-                pClockCtrl = &pChipcHw->I2CClock;
-                break;
-        case chipcHw_CLOCK_I2S0:
-                pClockCtrl = &pChipcHw->I2S0Clock;
-                break;
-        case chipcHw_CLOCK_RTBUS:
-                pClockCtrl = &pChipcHw->RTBUSClock;
-                pDependentClock = &pChipcHw->ACLKClock;
-                dependentClockType = NON_PLL_CLOCK;
-                break;
-        case chipcHw_CLOCK_APM100:
-                pClockCtrl = &pChipcHw->APM100Clock;
-                pDependentClock = &pChipcHw->APMClock;
-                vcoHz = vcoFreqPll2Hz;
-                dependentClockType = PLL_CLOCK;
-                break;
-        case chipcHw_CLOCK_TSC:
-                pClockCtrl = &pChipcHw->TSCClock;
-                break;
-        case chipcHw_CLOCK_LED:
-                pClockCtrl = &pChipcHw->LEDClock;
-                break;
-        case chipcHw_CLOCK_I2S1:
-                pClockCtrl = &pChipcHw->I2S1Clock;
-                break;
-        }
-
-        if (pPLLReg) {
-                /* Obtain PLL clock frequency */
-                if (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
-                        /* Return crystal clock frequency when bypassed */
-                        return chipcHw_XTAL_FREQ_Hz;
-                } else if (clock == chipcHw_CLOCK_DDR) {
-                        /* DDR frequency is configured in PLLDivider register */
-                        return chipcHw_divide (vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
-                } else {
-                        /* From chip revision number B0, LCD clock is internally divided by 2 */
-                        if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
-                                vcoHz >>= 1;
-                        }
-                        /* Obtain PLL clock frequency using VCO dividers */
-                        return chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ?  (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
-                }
-        } else if (pClockCtrl) {
-                /* Obtain divider clock frequency */
-                uint32_t div;
-                uint32_t freq = 0;
-
-                if (readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
-                        /* Return crystal clock frequency when bypassed */
-                        return chipcHw_XTAL_FREQ_Hz;
-                } else if (pDependentClock) {
-                        /* Identify the dependent clock frequency */
-                        switch (dependentClockType) {
-                        case PLL_CLOCK:
-                                if (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
-                                        /* Use crystal clock frequency when dependent PLL clock is bypassed */
-                                        freq = chipcHw_XTAL_FREQ_Hz;
-                                } else {
-                                        /* Obtain PLL clock frequency using VCO dividers */
-                                        div = readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
-                                        freq = div ? chipcHw_divide(vcoHz, div) : 0;
-                                }
-                                break;
-                        case NON_PLL_CLOCK:
-                                if (pDependentClock == &pChipcHw->ACLKClock) {
-                                        freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
-                                } else {
-                                        if (readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
-                                                /* Use crystal clock frequency when dependent divider clock is bypassed */
-                                                freq = chipcHw_XTAL_FREQ_Hz;
-                                        } else {
-                                                /* Obtain divider clock frequency using XTAL dividers */
-                                                div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-                                                freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
-                                        }
-                                }
-                                break;
-                        }
-                } else {
-                        /* Dependent on crystal clock */
-                        freq = chipcHw_XTAL_FREQ_Hz;
-                }
-
-                div = readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-                return chipcHw_divide(freq, (div ? div : 256));
-        }
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in Hz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,   /*  [ IN ] Configurable clock */
-                                       uint32_t freq    /*  [ IN ] Clock frequency in Hz */
-    ) {
-        uint32_t __iomem *pPLLReg = NULL;
-        uint32_t __iomem *pClockCtrl = NULL;
-        uint32_t __iomem *pDependentClock = NULL;
-        uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
-        uint32_t desVcoFreqPll1Hz = 0;  /* Desired VCO frequency for PLL1 in Hz */
-        uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
-        uint32_t dependentClockType = 0;
-        uint32_t vcoHz = 0;
-        uint32_t desVcoHz = 0;
-
-        /* Get VCO frequencies */
-        if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-                uint64_t adjustFreq = 0;
-
-                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-                /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
-                adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
-                        (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
-                        chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
-                vcoFreqPll1Hz += (uint32_t) adjustFreq;
-
-                /* Desired VCO frequency */
-                desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    (((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-                      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
-        } else {
-                vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                    ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-        }
-        vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-            ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-        switch (clock) {
-        case chipcHw_CLOCK_DDR:
-                /* Configure the DDR_ctrl:BUS ratio settings */
-                {
-                        REG_LOCAL_IRQ_SAVE;
-                        /* Dvide DDR_phy by two to obtain DDR_ctrl clock */
-                        writel((readl(&pChipcHw->DDRClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->DDRClock);
-                        REG_LOCAL_IRQ_RESTORE;
-                }
-                pPLLReg = &pChipcHw->DDRClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ARM:
-                pPLLReg = &pChipcHw->ARMClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ESW:
-                pPLLReg = &pChipcHw->ESWClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_VPM:
-                /* Configure the VPM:BUS ratio settings */
-                {
-                        REG_LOCAL_IRQ_SAVE;
-                        writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->VPMClock);
-                        REG_LOCAL_IRQ_RESTORE;
-                }
-                pPLLReg = &pChipcHw->VPMClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ESW125:
-                pPLLReg = &pChipcHw->ESW125Clock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_UART:
-                pPLLReg = &pChipcHw->UARTClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_SDIO0:
-                pPLLReg = &pChipcHw->SDIO0Clock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_SDIO1:
-                pPLLReg = &pChipcHw->SDIO1Clock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_SPI:
-                pPLLReg = &pChipcHw->SPIClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_ETM:
-                pPLLReg = &pChipcHw->ETMClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                break;
-        case chipcHw_CLOCK_USB:
-                pPLLReg = &pChipcHw->USBClock;
-                vcoHz = vcoFreqPll2Hz;
-                desVcoHz = vcoFreqPll2Hz;
-                break;
-        case chipcHw_CLOCK_LCD:
-                pPLLReg = &pChipcHw->LCDClock;
-                vcoHz = vcoFreqPll2Hz;
-                desVcoHz = vcoFreqPll2Hz;
-                break;
-        case chipcHw_CLOCK_APM:
-                pPLLReg = &pChipcHw->APMClock;
-                vcoHz = vcoFreqPll2Hz;
-                desVcoHz = vcoFreqPll2Hz;
-                break;
-        case chipcHw_CLOCK_BUS:
-                pClockCtrl = &pChipcHw->ACLKClock;
-                pDependentClock = &pChipcHw->ARMClock;
-                vcoHz = vcoFreqPll1Hz;
-                desVcoHz = desVcoFreqPll1Hz;
-                dependentClockType = PLL_CLOCK;
-                break;
-        case chipcHw_CLOCK_OTP:
-                pClockCtrl = &pChipcHw->OTPClock;
-                break;
-        case chipcHw_CLOCK_I2C:
-                pClockCtrl = &pChipcHw->I2CClock;
-                break;
-        case chipcHw_CLOCK_I2S0:
-                pClockCtrl = &pChipcHw->I2S0Clock;
-                break;
-        case chipcHw_CLOCK_RTBUS:
-                pClockCtrl = &pChipcHw->RTBUSClock;
-                pDependentClock = &pChipcHw->ACLKClock;
-                dependentClockType = NON_PLL_CLOCK;
-                break;
-        case chipcHw_CLOCK_APM100:
-                pClockCtrl = &pChipcHw->APM100Clock;
-                pDependentClock = &pChipcHw->APMClock;
-                vcoHz = vcoFreqPll2Hz;
-                desVcoHz = vcoFreqPll2Hz;
-                dependentClockType = PLL_CLOCK;
-                break;
-        case chipcHw_CLOCK_TSC:
-                pClockCtrl = &pChipcHw->TSCClock;
-                break;
-        case chipcHw_CLOCK_LED:
-                pClockCtrl = &pChipcHw->LEDClock;
-                break;
-        case chipcHw_CLOCK_I2S1:
-                pClockCtrl = &pChipcHw->I2S1Clock;
-                break;
-        }
-
-        if (pPLLReg) {
-                /* Select XTAL as bypass source */
-                reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO);
-                reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-                /* For DDR settings use only the PLL divider clock */
-                if (pPLLReg == &pChipcHw->DDRClock) {
-                        /* Set M1DIV for PLL1, which controls the DDR clock */
-                        reg32_write(&pChipcHw->PLLDivider, (readl(&pChipcHw->PLLDivider) & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
-                        /* Calculate expected frequency */
-                        freq = chipcHw_divide(vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
-                } else {
-                        /* From chip revision number B0, LCD clock is internally divided by 2 */
-                        if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
-                                desVcoHz >>= 1;
-                                vcoHz >>= 1;
-                        }
-                        /* Set MDIV to change the frequency */
-                        reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
-                        reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
-                        /* Calculate expected frequency */
-                        freq = chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
-                }
-                /* Wait for for atleast 200ns as per the protocol to change frequency */
-                udelay(1);
-                /* Do not bypass */
-                reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-                /* Return the configured frequency */
-                return freq;
-        } else if (pClockCtrl) {
-                uint32_t divider = 0;
-
-                /* Divider clock should not be bypassed  */
-                reg32_modify_and(pClockCtrl,
-                                 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-
-                /* Identify the clock source */
-                if (pDependentClock) {
-                        switch (dependentClockType) {
-                        case PLL_CLOCK:
-                                divider = chipcHw_divide(chipcHw_divide (desVcoHz, (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
-                                break;
-                        case NON_PLL_CLOCK:
-                                {
-                                        uint32_t sourceClock = 0;
-
-                                        if (pDependentClock == &pChipcHw->ACLKClock) {
-                                                sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
-                                        } else {
-                                                uint32_t div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-                                                sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
-                                        }
-                                        divider = chipcHw_divide(sourceClock, freq);
-                                }
-                                break;
-                        }
-                } else {
-                        divider = chipcHw_divide(chipcHw_XTAL_FREQ_Hz, freq);
-                }
-
-                if (divider) {
-                        REG_LOCAL_IRQ_SAVE;
-                        /* Set the divider to obtain the required frequency */
-                        writel((readl(pClockCtrl) & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK), pClockCtrl);
-                        REG_LOCAL_IRQ_RESTORE;
-                        return freq;
-                }
-        }
-
-        return 0;
-}
-
-EXPORT_SYMBOL(chipcHw_setClockFrequency);
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock for Chip Rev #A0
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success (# of adjustment required)
-*            -1 : On failure
-*
-*/
-/****************************************************************************/
-static int vpmPhaseAlignA0(void)
-{
-        uint32_t phaseControl;
-        uint32_t phaseValue;
-        uint32_t prevPhaseComp;
-        int iter = 0;
-        int adjustCount = 0;
-        int count = 0;
-
-        for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) {
-                phaseControl = (readl(&pChipcHw->VPMClock) & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
-                phaseValue = 0;
-                prevPhaseComp = 0;
-
-                /* Step 1: Look for falling PH_COMP transition */
-
-                /* Read the contents of VPM Clock resgister */
-                phaseValue = readl(&pChipcHw->VPMClock);
-                do {
-                        /* Store previous value of phase comparator */
-                        prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
-                        /* Change the value of PH_CTRL. */
-                        reg32_write(&pChipcHw->VPMClock,
-                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-                        /* Wait atleast 20 ns */
-                        udelay(1);
-                        /* Toggle the LOAD_CH after phase control is written. */
-                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
-                        /* Read the contents of  VPM Clock resgister. */
-                        phaseValue = readl(&pChipcHw->VPMClock);
-
-                        if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
-                                phaseControl = (0x3F & (phaseControl - 1));
-                        } else {
-                                /* Increment to the Phase count value for next write, if Phase is not stable. */
-                                phaseControl = (0x3F & (phaseControl + 1));
-                        }
-                        /* Count number of adjustment made */
-                        adjustCount++;
-                } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || /* Look for a transition */
-                          ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) &&  /* Look for a falling edge */
-                         (adjustCount < MAX_PHASE_ADJUST_COUNT) /* Do not exceed the limit while trying */
-                    );
-
-                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-                        return -1;
-                }
-
-                /* Step 2: Keep moving forward to make sure falling PH_COMP transition was valid */
-
-                for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
-                        phaseControl = (0x3F & (phaseControl + 1));
-                        reg32_write(&pChipcHw->VPMClock,
-                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-                        /* Wait atleast 20 ns */
-                        udelay(1);
-                        /* Toggle the LOAD_CH after phase control is written. */
-                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
-                        phaseValue = readl(&pChipcHw->VPMClock);
-                        /* Count number of adjustment made */
-                        adjustCount++;
-                }
-
-                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-                        return -1;
-                }
-
-                if (count != 5) {
-                        /* Detected false transition */
-                        continue;
-                }
-
-                /* Step 3: Keep moving backward to make sure falling PH_COMP transition was stable */
-
-                for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
-                        phaseControl = (0x3F & (phaseControl - 1));
-                        reg32_write(&pChipcHw->VPMClock,
-                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-                        /* Wait atleast 20 ns */
-                        udelay(1);
-                        /* Toggle the LOAD_CH after phase control is written. */
-                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
-                        phaseValue = readl(&pChipcHw->VPMClock);
-                        /* Count number of adjustment made */
-                        adjustCount++;
-                }
-
-                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-                        return -1;
-                }
-
-                if (count != 3) {
-                        /* Detected noisy transition */
-                        continue;
-                }
-
-                /* Step 4: Keep moving backward before the original transition took place. */
-
-                for (count = 0; (count < 5); count++) {
-                        phaseControl = (0x3F & (phaseControl - 1));
-                        reg32_write(&pChipcHw->VPMClock,
-                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-                        /* Wait atleast 20 ns */
-                        udelay(1);
-                        /* Toggle the LOAD_CH after phase control is written. */
-                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
-                        phaseValue = readl(&pChipcHw->VPMClock);
-                        /* Count number of adjustment made */
-                        adjustCount++;
-                }
-
-                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-                        return -1;
-                }
-
-                if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0) {
-                        /* Detected false transition */
-                        continue;
-                }
-
-                /* Step 5: Re discover the valid transition */
-
-                do {
-                        /* Store previous value of phase comparator */
-                        prevPhaseComp = phaseValue;
-                        /* Change the value of PH_CTRL. */
-                        reg32_write(&pChipcHw->VPMClock,
-                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-                        /* Wait atleast 20 ns */
-                        udelay(1);
-                        /* Toggle the LOAD_CH after phase control is written. */
-                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
-                        /* Read the contents of  VPM Clock resgister. */
-                        phaseValue = readl(&pChipcHw->VPMClock);
-
-                        if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
-                                phaseControl = (0x3F & (phaseControl - 1));
-                        } else {
-                                /* Increment to the Phase count value for next write, if Phase is not stable. */
-                                phaseControl = (0x3F & (phaseControl + 1));
-                        }
-
-                        /* Count number of adjustment made */
-                        adjustCount++;
-                } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && (adjustCount < MAX_PHASE_ADJUST_COUNT));
-
-                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries  */
-                        return -1;
-                } else {
-                        /* Valid phase must have detected */
-                        break;
-                }
-        }
-
-        /* For VPM Phase should be perfectly aligned. */
-        phaseControl = (((readl(&pChipcHw->VPMClock) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
-        {
-                REG_LOCAL_IRQ_SAVE;
-
-                writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT), &pChipcHw->VPMClock);
-                /* Load new phase value */
-                writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
-
-                REG_LOCAL_IRQ_RESTORE;
-        }
-        /* Return the status */
-        return (int)adjustCount;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success (# of adjustment required)
-*            -1 : On failure
-*
-*/
-/****************************************************************************/
-int chipcHw_vpmPhaseAlign(void)
-{
-
-        if (chipcHw_getChipRevisionNumber() == chipcHw_REV_NUMBER_A0) {
-                return vpmPhaseAlignA0();
-        } else {
-                uint32_t phaseControl = chipcHw_getVpmPhaseControl();
-                uint32_t phaseValue = 0;
-                int adjustCount = 0;
-
-                /* Disable VPM access */
-                writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
-                /* Disable HW VPM phase alignment  */
-                chipcHw_vpmHwPhaseAlignDisable();
-                /* Enable SW VPM phase alignment  */
-                chipcHw_vpmSwPhaseAlignEnable();
-                /* Adjust VPM phase */
-                while (adjustCount < MAX_PHASE_ADJUST_COUNT) {
-                        phaseValue = chipcHw_getVpmHwPhaseAlignStatus();
-
-                        /* Adjust phase control value */
-                        if (phaseValue > 0xF) {
-                                /* Increment phase control value */
-                                phaseControl++;
-                        } else if (phaseValue < 0xF) {
-                                /* Decrement phase control value */
-                                phaseControl--;
-                        } else {
-                                /* Enable VPM access */
-                                writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
-                                /* Return adjust count */
-                                return adjustCount;
-                        }
-                        /* Change the value of PH_CTRL. */
-                        reg32_write(&pChipcHw->VPMClock,
-                        (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-                        /* Wait atleast 20 ns */
-                        udelay(1);
-                        /* Toggle the LOAD_CH after phase control is written. */
-                        writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
-                        /* Count adjustment */
-                        adjustCount++;
-                }
-        }
-
-        /* Disable VPM access */
-        writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
-        return -1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Local Divide function
-*
-*  This function does the divide
-*
-*  @return divide value
-*
-*/
-/****************************************************************************/
-static int chipcHw_divide(int num, int denom)
-{
-        int r;
-        int t = 1;
-
-        /* Shift denom and t up to the largest value to optimize algorithm */
-        /* t contains the units of each divide */
-        while ((denom & 0x40000000) == 0) {     /* fails if denom=0 */
-                denom = denom << 1;
-                t = t << 1;
-        }
-
-        /* Initialize the result */
-        r = 0;
-
-        do {
-                /* Determine if there exists a positive remainder */
-                if ((num - denom) >= 0) {
-                        /* Accumlate t to the result and calculate a new remainder */
-                        num = num - denom;
-                        r = r + t;
-                }
-                /* Continue to shift denom and shift t down to 0 */
-                denom = denom >> 1;
-                t = t >> 1;
-        } while (t != 0);
-
-        return r;
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
deleted file mode 100644
index 8377d8054168..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw_init.c
-*
-*  @brief   Low level CHIPC PLL configuration functions
-*
-*  @note
-*
-*   These routines provide basic PLL controlling functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <linux/errno.h>
-#include <linux/types.h>
-#include <linux/export.h>
-
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <mach/csp/reg.h>
-#include <linux/delay.h>
-/* ---- Private Constants and Types --------------------------------------- */
-
-/*
-    Calculation for NDIV_i to obtain VCO frequency
-    -----------------------------------------------
-
-        Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f)
-        for Freq_vco = VCO_FREQ_MHz
-                Freq_ref = chipcHw_XTAL_FREQ_Hz
-                PLL_P1 = PLL_P2 = 1
-                and
-                PLL_NDIV_f = 0
-
-        We get:
-                PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz
-
-    Calculation for PLL MDIV to obtain frequency Freq_x for channel x
-    -----------------------------------------------------------------
-                Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = VCO_FREQ_MHz / PLL_MDIV_x
-
-                PLL_MDIV_x = VCO_FREQ_MHz / Freq_x
-*/
-
-/* ---- Private Variables ------------------------------------------------- */
-/****************************************************************************/
-/**
-*  @brief  Initializes the PLL2
-*
-*  This function initializes the PLL2
-*
-*/
-/****************************************************************************/
-void chipcHw_pll2Enable(uint32_t vcoFreqHz)
-{
-        uint32_t pllPreDivider2 = 0;
-
-        {
-                REG_LOCAL_IRQ_SAVE;
-                writel(chipcHw_REG_PLL_CONFIG_D_RESET |
-                       chipcHw_REG_PLL_CONFIG_A_RESET,
-                        &pChipcHw->PLLConfig2);
-
-                pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
-                    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
-                    (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
-                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-                    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-                     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-                    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-                     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-
-                /* Enable CHIPC registers to control the PLL */
-                writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
-
-                /* Set pre divider to get desired VCO frequency */
-                writel(pllPreDivider2, &pChipcHw->PLLPreDivider2);
-                /* Set NDIV Frac */
-                writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2);
-
-                /* This has to be removed once the default values are fixed for PLL2. */
-                writel(0x38000700, &pChipcHw->PLLControl12);
-                writel(0x00000015, &pChipcHw->PLLControl22);
-
-                /* Reset PLL2 */
-                if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-                        writel(chipcHw_REG_PLL_CONFIG_D_RESET |
-                            chipcHw_REG_PLL_CONFIG_A_RESET |
-                            chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-                            chipcHw_REG_PLL_CONFIG_POWER_DOWN,
-                            &pChipcHw->PLLConfig2);
-                } else {
-                        writel(chipcHw_REG_PLL_CONFIG_D_RESET |
-                            chipcHw_REG_PLL_CONFIG_A_RESET |
-                            chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-                            chipcHw_REG_PLL_CONFIG_POWER_DOWN,
-                            &pChipcHw->PLLConfig2);
-                }
-                REG_LOCAL_IRQ_RESTORE;
-        }
-
-        /* Insert certain amount of delay before deasserting ARESET. */
-        udelay(1);
-
-        {
-                REG_LOCAL_IRQ_SAVE;
-                /* Remove analog reset and Power on the PLL */
-                writel(readl(&pChipcHw->PLLConfig2) &
-                    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-                      chipcHw_REG_PLL_CONFIG_POWER_DOWN),
-                      &pChipcHw->PLLConfig2);
-
-                REG_LOCAL_IRQ_RESTORE;
-
-        }
-
-        /* Wait until PLL is locked */
-        while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
-                ;
-
-        {
-                REG_LOCAL_IRQ_SAVE;
-                /* Remove digital reset */
-                writel(readl(&pChipcHw->PLLConfig2) &
-                        ~chipcHw_REG_PLL_CONFIG_D_RESET,
-                        &pChipcHw->PLLConfig2);
-
-                REG_LOCAL_IRQ_RESTORE;
-        }
-}
-
-EXPORT_SYMBOL(chipcHw_pll2Enable);
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the PLL1
-*
-*  This function initializes the PLL1
-*
-*/
-/****************************************************************************/
-void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
-{
-        uint32_t pllPreDivider = 0;
-
-        {
-                REG_LOCAL_IRQ_SAVE;
-
-                writel(chipcHw_REG_PLL_CONFIG_D_RESET |
-                    chipcHw_REG_PLL_CONFIG_A_RESET,
-                    &pChipcHw->PLLConfig);
-                /* Setting VCO frequency */
-                if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-                        pllPreDivider =
-                            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 |
-                            ((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) -
-                              1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-                            (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-                             chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-                            (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-                             chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-                } else {
-                        pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
-                            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
-                            (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
-                             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-                            (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-                             chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-                            (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-                             chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-                }
-
-                /* Enable CHIPC registers to control the PLL */
-                writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
-
-                /* Set pre divider to get desired VCO frequency */
-                writel(pllPreDivider, &pChipcHw->PLLPreDivider);
-                /* Set NDIV Frac */
-                if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-                        writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider);
-                } else {
-                        writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider);
-                }
-
-                /* Reset PLL1 */
-                if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-                        writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
-                } else {
-                        writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
-                }
-
-                REG_LOCAL_IRQ_RESTORE;
-
-                /* Insert certain amount of delay before deasserting ARESET. */
-                udelay(1);
-
-                {
-                        REG_LOCAL_IRQ_SAVE;
-                        /* Remove analog reset and Power on the PLL */
-                        writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig);
-                        REG_LOCAL_IRQ_RESTORE;
-                }
-
-                /* Wait until PLL is locked */
-                while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED)
-                       || !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
-                        ;
-
-                /* Remove digital reset */
-                {
-                        REG_LOCAL_IRQ_SAVE;
-                        writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig);
-                        REG_LOCAL_IRQ_RESTORE;
-                }
-        }
-}
-
-EXPORT_SYMBOL(chipcHw_pll1Enable);
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the chipc module
-*
-*  This function initializes the PLLs and core system clocks
-*
-*/
-/****************************************************************************/
-
-void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam       /*  [ IN ] Misc chip initialization parameter */
-    ) {
-#if !(defined(__KERNEL__) && !defined(STANDALONE))
-        delay_init();
-#endif
-
-        /* Do not program PLL, when warm reset */
-        if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) {
-                chipcHw_pll1Enable(initParam->pllVcoFreqHz,
-                                   initParam->ssSupport);
-                chipcHw_pll2Enable(initParam->pll2VcoFreqHz);
-        } else {
-                /* Clear sticky bits */
-                chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET);
-        }
-        /* Clear sticky bits */
-        chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
-
-        /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
-        writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock);
-
-        /* Set various core component frequencies. The order in which this is done is important for some. */
-        /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
-        /* frequency to find its ratio with the BUS.  Hence we must set the ARM first, followed by the BUS,  */
-        /* then VPM and RTBUS. */
-
-        chipcHw_setClockFrequency(chipcHw_CLOCK_ARM,
-                                  initParam->busClockFreqHz *
-                                  initParam->armBusRatio);
-        chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz);
-        chipcHw_setClockFrequency(chipcHw_CLOCK_VPM,
-                                  initParam->busClockFreqHz *
-                                  initParam->vpmBusRatio);
-        chipcHw_setClockFrequency(chipcHw_CLOCK_DDR,
-                                  initParam->busClockFreqHz *
-                                  initParam->ddrBusRatio);
-        chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS,
-                                  initParam->busClockFreqHz / 2);
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
deleted file mode 100644
index f95ce913fa1e..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <linux/types.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <mach/csp/intcHw_reg.h>
-#include <asm/cacheflush.h>
-
-/* ---- Private Constants and Types --------------------------------------- */
-/* ---- Private Variables ------------------------------------------------- */
-void chipcHw_reset_run_from_aram(void);
-
-typedef void (*RUNFUNC) (void);
-
-/****************************************************************************/
-/**
-*  @brief   warmReset
-*
-*  @note warmReset configures the clocks which are not reset back to the state
-*   required to execute on reset.  To do so we need to copy the code into internal
-*   memory to change the ARM clock while we are not executing from DDR.
-*/
-/****************************************************************************/
-void chipcHw_reset(uint32_t mask)
-{
-        int i = 0;
-        RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM;
-
-        /* Disable all interrupts */
-        intcHw_irq_disable(INTCHW_INTC0, 0xffffffff);
-        intcHw_irq_disable(INTCHW_INTC1, 0xffffffff);
-        intcHw_irq_disable(INTCHW_SINTC, 0xffffffff);
-
-        {
-                REG_LOCAL_IRQ_SAVE;
-                if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) {
-                        chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-                }
-                /* Bypass the PLL clocks before reboot */
-                writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
-                        &pChipcHw->UARTClock);
-                writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
-                        &pChipcHw->SPIClock);
-
-                /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
-                do {
-                        writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i);
-                        i++;
-                } while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f);   /* 0xe1a0f00f == asm ("mov r15, r15"); */
-
-                flush_cache_all();
-
-                /* run the function from ARAM */
-                runFunc();
-
-                /* Code will never get here, but include it to balance REG_LOCAL_IRQ_SAVE above */
-                REG_LOCAL_IRQ_RESTORE;
-        }
-}
-
-/* This function must run from internal memory */
-void chipcHw_reset_run_from_aram(void)
-{
-/* Make sure, pipeline is filled with instructions coming from ARAM */
-__asm (" nop                                                            \n\t"
-                " nop                                                            \n\t"
-#if defined(__KERNEL__) && !defined(STANDALONE)
-                " MRC      p15,#0x0,r0,c1,c0,#0                                  \n\t"
-                " BIC      r0,r0,#0xd                                            \n\t"
-                " MCR      p15,#0x0,r0,c1,c0,#0                                  \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-#endif
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-/* Bypass the ARM clock and switch to XTAL clock */
-                " MOV      r2,#0x80000000                                        \n\t"
-                " LDR      r3,[r2,#8]                                            \n\t"
-                " ORR      r3,r3,#0x20000                                        \n\t"
-                " STR      r3,[r2,#8]                                            \n\t"
-
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-                " nop                                                            \n\t"
-/* Issue reset */
-                " MOV      r3,#0x2                                               \n\t"
-                " STR      r3,[r2,#0x80]                                         \n\t"
-/* End here */
-                " MOV      pc,pc                                                 \n\t");
-/* 0xe1a0f00f ==  asm ("mov r15, r15"); */
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
deleted file mode 100644
index 54ad964fe94c..000000000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*****************************************************************************
-* Copyright 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    chipcHw_str.c
-*
-*  @brief   Contains strings which are useful to linux and csp
-*
-*  @note
-*/
-/****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <mach/csp/chipcHw_inline.h>
-
-/* ---- Private Constants and Types --------------------------------------- */
-
-static const char *gMuxStr[] = {
-        "GPIO",                 /* 0 */
-        "KeyPad",               /* 1 */
-        "I2C-Host",             /* 2 */
-        "SPI",                  /* 3 */
-        "Uart",                 /* 4 */
-        "LED-Mtx-P",            /* 5 */
-        "LED-Mtx-S",            /* 6 */
-        "SDIO-0",               /* 7 */
-        "SDIO-1",               /* 8 */
-        "PCM",                  /* 9 */
-        "I2S",                  /* 10 */
-        "ETM",                  /* 11 */
-        "Debug",                /* 12 */
-        "Misc",                 /* 13 */
-        "0xE",                  /* 14 */
-        "0xF",                  /* 15 */
-};
-
-/****************************************************************************/
-/**
-*  @brief   Retrieves a string representation of the mux setting for a pin.
-*
-*  @return  Pointer to a character string.
-*/
-/****************************************************************************/
-
-const char *chipcHw_getGpioPinFunctionStr(int pin)
-{
-        if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) {
-                return "";
-        }
-
-        return gMuxStr[chipcHw_getGpioPinFunction(pin)];
-}
diff --git a/arch/arm/mach-bcmring/csp/dmac/Makefile b/arch/arm/mach-bcmring/csp/dmac/Makefile
deleted file mode 100644
index fb1104fe56b2..000000000000
--- a/arch/arm/mach-bcmring/csp/dmac/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += dmacHw.o dmacHw_extra.o
\ No newline at end of file
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
deleted file mode 100644
index 547f746c7ff4..000000000000
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
+++ /dev/null
@@ -1,916 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw.c
-*
-*  @brief   Low level DMA controller driver routines
-*
-*  @note
-*
-*   These routines provide basic DMA functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/stddef.h>
-
-#include <mach/csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-#include <mach/csp/chipcHw_inline.h>
-
-/* ---- External Function Prototypes ------------------------------------- */
-
-/* Allocate DMA control blocks */
-dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];
-
-uint32_t dmaChannelCount_0 = dmacHw_MAX_CHANNEL_COUNT / 2;
-uint32_t dmaChannelCount_1 = dmacHw_MAX_CHANNEL_COUNT / 2;
-
-/****************************************************************************/
-/**
-*  @brief   Get maximum FIFO for a DMA channel
-*
-*  @return  Maximum allowable FIFO size
-*
-*
-*/
-/****************************************************************************/
-static uint32_t GetFifoSize(dmacHw_HANDLE_t handle      /*   [ IN ] DMA Channel handle */
-    ) {
-        uint32_t val = 0;
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module);
-
-        switch (pCblk->channel) {
-        case 0:
-                val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28;
-                break;
-        case 1:
-                val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28;
-                break;
-        case 2:
-                val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28;
-                break;
-        case 3:
-                val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28;
-                break;
-        case 4:
-                val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28;
-                break;
-        case 5:
-                val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28;
-                break;
-        case 6:
-                val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28;
-                break;
-        case 7:
-                val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28;
-                break;
-        }
-
-        if (val <= 0x4) {
-                return 8 << val;
-        } else {
-                dmacHw_ASSERT(0);
-        }
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to initiate transfer
-*
-*  @return  void
-*
-*
-*  @note
-*     - Descriptor buffer MUST ALWAYS be flushed before calling this function
-*     - This function should also be called from ISR to program the channel with
-*       pending descriptors
-*/
-/****************************************************************************/
-void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,    /*   [ IN ] DMA Channel handle */
-                             dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
-                             void *pDescriptor  /*   [ IN ] Descriptor buffer */
-    ) {
-        dmacHw_DESC_RING_t *pRing;
-        dmacHw_DESC_t *pProg;
-        dmacHw_CBLK_t *pCblk;
-
-        pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-        if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-                /* Not safe yet to program the channel */
-                return;
-        }
-
-        if (pCblk->varDataStarted) {
-                if (pCblk->descUpdated) {
-                        pCblk->descUpdated = 0;
-                        pProg =
-                            (dmacHw_DESC_t *) ((uint32_t)
-                                               dmacHw_REG_LLP(pCblk->module,
-                                                              pCblk->channel) +
-                                               pRing->virt2PhyOffset);
-
-                        /* Load descriptor if not loaded */
-                        if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) {
-                                dmacHw_SET_SAR(pCblk->module, pCblk->channel,
-                                               pProg->sar);
-                                dmacHw_SET_DAR(pCblk->module, pCblk->channel,
-                                               pProg->dar);
-                                dmacHw_REG_CTL_LO(pCblk->module,
-                                                  pCblk->channel) =
-                                    pProg->ctl.lo;
-                                dmacHw_REG_CTL_HI(pCblk->module,
-                                                  pCblk->channel) =
-                                    pProg->ctl.hi;
-                        } else if (pProg == (dmacHw_DESC_t *) pRing->pEnd->llp) {
-                                /* Return as end descriptor is processed */
-                                return;
-                        } else {
-                                dmacHw_ASSERT(0);
-                        }
-                } else {
-                        return;
-                }
-        } else {
-                if (pConfig->transferMode == dmacHw_TRANSFER_MODE_PERIODIC) {
-                        /* Do not make a single chain, rather process one descriptor at a time */
-                        pProg = pRing->pHead;
-                        /* Point to the next descriptor for next iteration */
-                        dmacHw_NEXT_DESC(pRing, pHead);
-                } else {
-                        /* Return if no more pending descriptor */
-                        if (pRing->pEnd == NULL) {
-                                return;
-                        }
-
-                        pProg = pRing->pProg;
-                        if (pConfig->transferMode ==
-                            dmacHw_TRANSFER_MODE_CONTINUOUS) {
-                                /* Make sure a complete ring can be formed */
-                                dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pEnd->
-                                              llp == pRing->pProg);
-                                /* Make sure pProg pointing to the pHead */
-                                dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pProg ==
-                                              pRing->pHead);
-                                /* Make a complete ring */
-                                do {
-                                        pRing->pProg->ctl.lo |=
-                                            (dmacHw_REG_CTL_LLP_DST_EN |
-                                             dmacHw_REG_CTL_LLP_SRC_EN);
-                                        pRing->pProg =
-                                            (dmacHw_DESC_t *) pRing->pProg->llp;
-                                } while (pRing->pProg != pRing->pHead);
-                        } else {
-                                /* Make a single long chain */
-                                while (pRing->pProg != pRing->pEnd) {
-                                        pRing->pProg->ctl.lo |=
-                                            (dmacHw_REG_CTL_LLP_DST_EN |
-                                             dmacHw_REG_CTL_LLP_SRC_EN);
-                                        pRing->pProg =
-                                            (dmacHw_DESC_t *) pRing->pProg->llp;
-                                }
-                        }
-                }
-
-                /* Program the channel registers */
-                dmacHw_SET_SAR(pCblk->module, pCblk->channel, pProg->sar);
-                dmacHw_SET_DAR(pCblk->module, pCblk->channel, pProg->dar);
-                dmacHw_SET_LLP(pCblk->module, pCblk->channel,
-                               (uint32_t) pProg - pRing->virt2PhyOffset);
-                dmacHw_REG_CTL_LO(pCblk->module, pCblk->channel) =
-                    pProg->ctl.lo;
-                dmacHw_REG_CTL_HI(pCblk->module, pCblk->channel) =
-                    pProg->ctl.hi;
-                if (pRing->pEnd) {
-                        /* Remember the descriptor to use next */
-                        pRing->pProg = (dmacHw_DESC_t *) pRing->pEnd->llp;
-                }
-                /* Indicate no more pending descriptor  */
-                pRing->pEnd = (dmacHw_DESC_t *) NULL;
-        }
-        /* Start DMA operation */
-        dmacHw_DMA_START(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes DMA
-*
-*  This function initializes DMA CSP driver
-*
-*  @note
-*     Must be called before using any DMA channel
-*/
-/****************************************************************************/
-void dmacHw_initDma(void)
-{
-
-        uint32_t i = 0;
-
-        dmaChannelCount_0 = dmacHw_GET_NUM_CHANNEL(0);
-        dmaChannelCount_1 = dmacHw_GET_NUM_CHANNEL(1);
-
-        /* Enable access to the DMA block */
-        chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC0);
-        chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC1);
-
-        if ((dmaChannelCount_0 + dmaChannelCount_1) > dmacHw_MAX_CHANNEL_COUNT) {
-                dmacHw_ASSERT(0);
-        }
-
-        memset((void *)dmacHw_gCblk, 0,
-               sizeof(dmacHw_CBLK_t) * (dmaChannelCount_0 + dmaChannelCount_1));
-        for (i = 0; i < dmaChannelCount_0; i++) {
-                dmacHw_gCblk[i].module = 0;
-                dmacHw_gCblk[i].channel = i;
-        }
-        for (i = 0; i < dmaChannelCount_1; i++) {
-                dmacHw_gCblk[i + dmaChannelCount_0].module = 1;
-                dmacHw_gCblk[i + dmaChannelCount_0].channel = i;
-        }
-}
-
-/****************************************************************************/
-/**
-*  @brief   Exit function for  DMA
-*
-*  This function isolates DMA from the system
-*
-*/
-/****************************************************************************/
-void dmacHw_exitDma(void)
-{
-        /* Disable access to the DMA block */
-        chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC0);
-        chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets a handle to a DMA channel
-*
-*  This function returns a handle, representing a control block of a particular DMA channel
-*
-*  @return  -1       - On Failure
-*            handle  - On Success, representing a channel control block
-*
-*  @note
-*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId   /* [ IN ] DMA Channel Id */
-    ) {
-        int idx;
-
-        switch ((channelId >> 8)) {
-        case 0:
-                dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_0);
-                idx = (channelId & 0xff);
-                break;
-        case 1:
-                dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_1);
-                idx = dmaChannelCount_0 + (channelId & 0xff);
-                break;
-        default:
-                dmacHw_ASSERT(0);
-                return (dmacHw_HANDLE_t) -1;
-        }
-
-        return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[idx]);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes a DMA channel for use
-*
-*  This function initializes and resets a DMA channel for use
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_initChannel(dmacHw_HANDLE_t handle   /*   [ IN ] DMA Channel handle */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        int module = pCblk->module;
-        int channel = pCblk->channel;
-
-        /* Reinitialize the control block */
-        memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t));
-        pCblk->module = module;
-        pCblk->channel = channel;
-
-        /* Enable DMA controller */
-        dmacHw_DMA_ENABLE(pCblk->module);
-        /* Reset DMA channel */
-        dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel);
-        dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel);
-        dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel);
-        dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel);
-
-        /* Clear all raw interrupt status */
-        dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-        dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-        dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-
-        /* Mask event specific interrupts */
-        dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-        dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
-        dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-        dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-        dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
-
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief  Finds amount of memory required to form a descriptor ring
-*
-*
-*  @return   Number of bytes required to form a descriptor ring
-*
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorLen(uint32_t descCnt  /* [ IN ] Number of descriptor in the ring */
-    ) {
-        /* Need extra 4 byte to ensure 32 bit alignment  */
-        return (descCnt * sizeof(dmacHw_DESC_t)) + sizeof(dmacHw_DESC_RING_t) +
-                sizeof(uint32_t);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes descriptor ring
-*
-*  This function will initializes the descriptor ring of a DMA channel
-*
-*
-*  @return   -1 - On failure
-*             0 - On success
-*  @note
-*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
-*     - Descriptor buffer MUST be 32 bit aligned and uncached as it is
-*       accessed by ARM and DMA
-*/
-/****************************************************************************/
-int dmacHw_initDescriptor(void *pDescriptorVirt,        /*  [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
-                          uint32_t descriptorPhyAddr,   /*  [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
-                          uint32_t len, /*  [ IN ] Size of the pBuf */
-                          uint32_t num  /*  [ IN ] Number of descriptor in the ring */
-    ) {
-        uint32_t i;
-        dmacHw_DESC_RING_t *pRing;
-        dmacHw_DESC_t *pDesc;
-
-        /* Check the alignment of the descriptor */
-        if ((uint32_t) pDescriptorVirt & 0x00000003) {
-                dmacHw_ASSERT(0);
-                return -1;
-        }
-
-        /* Check if enough space has been allocated for descriptor ring */
-        if (len < dmacHw_descriptorLen(num)) {
-                return -1;
-        }
-
-        pRing = dmacHw_GET_DESC_RING(pDescriptorVirt);
-        pRing->pHead =
-            (dmacHw_DESC_t *) ((uint32_t) pRing + sizeof(dmacHw_DESC_RING_t));
-        pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
-        pRing->pProg = dmacHw_DESC_INIT;
-        /* Initialize link item chain, starting from the head */
-        pDesc = pRing->pHead;
-        /* Find the offset between virtual to physical address */
-        pRing->virt2PhyOffset = (uint32_t) pDescriptorVirt - descriptorPhyAddr;
-
-        /* Form the descriptor ring */
-        for (i = 0; i < num - 1; i++) {
-                /* Clear link list item */
-                memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
-                /* Point to the next item in the physical address */
-                pDesc->llpPhy = (uint32_t) (pDesc + 1) - pRing->virt2PhyOffset;
-                /* Point to the next item in the virtual address */
-                pDesc->llp = (uint32_t) (pDesc + 1);
-                /* Mark descriptor is ready to use */
-                pDesc->ctl.hi = dmacHw_DESC_FREE;
-                /* Look into next link list item */
-                pDesc++;
-        }
-
-        /* Clear last link list item */
-        memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
-        /* Last item pointing to the first item in the
-           physical address to complete the ring */
-        pDesc->llpPhy = (uint32_t) pRing->pHead - pRing->virt2PhyOffset;
-        /* Last item pointing to the first item in the
-           virtual address to complete the ring
-         */
-        pDesc->llp = (uint32_t) pRing->pHead;
-        /* Mark descriptor is ready to use */
-        pDesc->ctl.hi = dmacHw_DESC_FREE;
-        /* Set the number of descriptors in the ring */
-        pRing->num = num;
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configure DMA channel
-*
-*  @return  0  : On success
-*           -1 : On failure
-*/
-/****************************************************************************/
-int dmacHw_configChannel(dmacHw_HANDLE_t handle,        /*   [ IN ] DMA Channel handle */
-                         dmacHw_CONFIG_t *pConfig       /*   [ IN ] Configuration settings */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        uint32_t cfgHigh = 0;
-        int srcTrSize;
-        int dstTrSize;
-
-        pCblk->varDataStarted = 0;
-        pCblk->userData = NULL;
-
-        /* Configure
-           - Burst transaction when enough data in available in FIFO
-           - AHB Access protection 1
-           - Source and destination peripheral ports
-         */
-        cfgHigh =
-            dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
-            dmacHw_SRC_PERI_INTF(pConfig->
-                                 srcPeripheralPort) |
-            dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
-        /* Set priority */
-        dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
-                                    pConfig->channelPriority);
-
-        if (pConfig->dstStatusRegisterAddress != 0) {
-                /* Destination status update enable */
-                cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
-                /* Configure status registers */
-                dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
-                                   pConfig->dstStatusRegisterAddress);
-        }
-
-        if (pConfig->srcStatusRegisterAddress != 0) {
-                /* Source status update enable */
-                cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
-                /* Source status update enable */
-                dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
-                                   pConfig->srcStatusRegisterAddress);
-        }
-        /* Configure the config high register */
-        dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;
-
-        /* Clear all raw interrupt status */
-        dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-        dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-        dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-
-        /* Configure block interrupt */
-        if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
-                dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
-        } else {
-                dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
-        }
-        /* Configure complete transfer interrupt */
-        if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
-                dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
-        } else {
-                dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-        }
-        /* Configure error interrupt */
-        if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
-                dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
-        } else {
-                dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
-        }
-        /* Configure gather register */
-        if (pConfig->srcGatherWidth) {
-                srcTrSize =
-                    dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-                if (!
-                    ((pConfig->srcGatherWidth % srcTrSize)
-                     && (pConfig->srcGatherJump % srcTrSize))) {
-                        dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
-                            ((pConfig->srcGatherWidth /
-                              srcTrSize) << 20) | (pConfig->srcGatherJump /
-                                                   srcTrSize);
-                } else {
-                        return -1;
-                }
-        }
-        /* Configure scatter register */
-        if (pConfig->dstScatterWidth) {
-                dstTrSize =
-                    dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-                if (!
-                    ((pConfig->dstScatterWidth % dstTrSize)
-                     && (pConfig->dstScatterJump % dstTrSize))) {
-                        dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
-                            ((pConfig->dstScatterWidth /
-                              dstTrSize) << 20) | (pConfig->dstScatterJump /
-                                                   dstTrSize);
-                } else {
-                        return -1;
-                }
-        }
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indicates whether DMA transfer is in progress or completed
-*
-*  @return   DMA transfer status
-*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
-*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
-*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
-*
-*/
-/****************************************************************************/
-dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle        /*   [ IN ] DMA Channel handle */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-        if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-                return dmacHw_TRANSFER_STATUS_BUSY;
-        } else if (dmacHw_REG_INT_RAW_ERROR(pCblk->module) &
-                   (0x00000001 << pCblk->channel)) {
-                return dmacHw_TRANSFER_STATUS_ERROR;
-        }
-
-        return dmacHw_TRANSFER_STATUS_DONE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptors for known data length
-*
-*  When DMA has to work as a flow controller, this function prepares the
-*  descriptor chain to transfer data
-*
-*  from:
-*          - Memory to memory
-*          - Peripheral to memory
-*          - Memory to Peripheral
-*          - Peripheral to Peripheral
-*
-*  @return   -1 - On failure
-*             0 - On success
-*
-*/
-/****************************************************************************/
-int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
-                             void *pDescriptor, /*   [ IN ] Descriptor buffer */
-                             void *pSrcAddr,    /*   [ IN ] Source (Peripheral/Memory) address */
-                             void *pDstAddr,    /*   [ IN ] Destination (Peripheral/Memory) address */
-                             size_t dataLen     /*   [ IN ] Data length in bytes */
-    ) {
-        dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
-        dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
-        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-        dmacHw_DESC_t *pStart;
-        dmacHw_DESC_t *pProg;
-        int srcTs = 0;
-        int blkTs = 0;
-        int oddSize = 0;
-        int descCount = 0;
-        int count = 0;
-        int dstTrSize = 0;
-        int srcTrSize = 0;
-        uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
-
-        dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-        srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-
-        /* Skip Tx if buffer is NULL  or length is unknown */
-        if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
-                /* Do not initiate transfer */
-                return -1;
-        }
-
-        /* Ensure scatter and gather are transaction aligned */
-        if ((pConfig->srcGatherWidth % srcTrSize)
-            || (pConfig->dstScatterWidth % dstTrSize)) {
-                return -2;
-        }
-
-        /*
-           Background 1: DMAC can not perform DMA if source and destination addresses are
-           not properly aligned with the channel's transaction width. So, for successful
-           DMA transfer, transaction width must be set according to the alignment of the
-           source and destination address.
-         */
-
-        /* Adjust destination transaction width if destination address is not aligned properly */
-        dstTrWidth = pConfig->dstMaxTransactionWidth;
-        while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
-                dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
-                dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
-        }
-
-        /* Adjust source transaction width if source address is not aligned properly */
-        srcTrWidth = pConfig->srcMaxTransactionWidth;
-        while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
-                srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
-                srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
-        }
-
-        /* Find the maximum transaction per descriptor */
-        if (pConfig->maxDataPerBlock
-            && ((pConfig->maxDataPerBlock / srcTrSize) <
-                dmacHw_MAX_BLOCKSIZE)) {
-                maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
-        }
-
-        /* Find number of source transactions needed to complete the DMA transfer */
-        srcTs = dataLen / srcTrSize;
-        /* Find the odd number of bytes that need to be transferred as single byte transaction width */
-        if (srcTs && (dstTrSize > srcTrSize)) {
-                oddSize = dataLen % dstTrSize;
-                /* Adjust source transaction count due to "oddSize" */
-                srcTs = srcTs - (oddSize / srcTrSize);
-        } else {
-                oddSize = dataLen % srcTrSize;
-        }
-        /* Adjust "descCount" due to "oddSize" */
-        if (oddSize) {
-                descCount++;
-        }
-        /* Find the number of descriptor needed for total "srcTs" */
-        if (srcTs) {
-                descCount += ((srcTs - 1) / maxBlockSize) + 1;
-        }
-
-        /* Check the availability of "descCount" discriptors in the ring */
-        pProg = pRing->pHead;
-        for (count = 0; (descCount <= pRing->num) && (count < descCount);
-             count++) {
-                if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) {
-                        /* Sufficient descriptors are not available */
-                        return -3;
-                }
-                pProg = (dmacHw_DESC_t *) pProg->llp;
-        }
-
-        /* Remember the link list item to program the channel registers */
-        pStart = pProg = pRing->pHead;
-        /* Make a link list with "descCount(=count)" number of descriptors */
-        while (count) {
-                /* Reset channel control information */
-                pProg->ctl.lo = 0;
-                /* Enable source gather if configured */
-                if (pConfig->srcGatherWidth) {
-                        pProg->ctl.lo |= dmacHw_REG_CTL_SG_ENABLE;
-                }
-                /* Enable destination scatter if configured */
-                if (pConfig->dstScatterWidth) {
-                        pProg->ctl.lo |= dmacHw_REG_CTL_DS_ENABLE;
-                }
-                /* Set source and destination address */
-                pProg->sar = (uint32_t) pSrcAddr;
-                pProg->dar = (uint32_t) pDstAddr;
-                /* Use "devCtl" to mark that user memory need to be freed later if needed */
-                if (pProg == pRing->pHead) {
-                        pProg->devCtl = dmacHw_FREE_USER_MEMORY;
-                } else {
-                        pProg->devCtl = 0;
-                }
-
-                blkTs = srcTs;
-
-                /* Special treatmeant for last descriptor */
-                if (count == 1) {
-                        /* Mark the last descriptor */
-                        pProg->ctl.lo &=
-                            ~(dmacHw_REG_CTL_LLP_DST_EN |
-                              dmacHw_REG_CTL_LLP_SRC_EN);
-                        /* Treatment for odd data bytes */
-                        if (oddSize) {
-                                /* Adjust for single byte transaction width */
-                                switch (pConfig->transferType) {
-                                case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-                                        dstTrWidth =
-                                            dmacHw_DST_TRANSACTION_WIDTH_8;
-                                        blkTs =
-                                            (oddSize / srcTrSize) +
-                                            ((oddSize % srcTrSize) ? 1 : 0);
-                                        break;
-                                case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-                                        srcTrWidth =
-                                            dmacHw_SRC_TRANSACTION_WIDTH_8;
-                                        blkTs = oddSize;
-                                        break;
-                                case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
-                                        srcTrWidth =
-                                            dmacHw_SRC_TRANSACTION_WIDTH_8;
-                                        dstTrWidth =
-                                            dmacHw_DST_TRANSACTION_WIDTH_8;
-                                        blkTs = oddSize;
-                                        break;
-                                case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
-                                        /* Do not adjust the transaction width  */
-                                        break;
-                                }
-                        } else {
-                                srcTs -= blkTs;
-                        }
-                } else {
-                        if (srcTs / maxBlockSize) {
-                                blkTs = maxBlockSize;
-                        }
-                        /* Remaining source transactions for next iteration */
-                        srcTs -= blkTs;
-                }
-                /* Must have a valid source transactions */
-                dmacHw_ASSERT(blkTs > 0);
-                /* Set control information */
-                if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
-                        pProg->ctl.lo |= pConfig->transferType |
-                            pConfig->srcUpdate |
-                            pConfig->dstUpdate |
-                            srcTrWidth |
-                            dstTrWidth |
-                            pConfig->srcMaxBurstWidth |
-                            pConfig->dstMaxBurstWidth |
-                            pConfig->srcMasterInterface |
-                            pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-                } else {
-                        uint32_t transferType = 0;
-                        switch (pConfig->transferType) {
-                        case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-                                transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
-                                break;
-                        case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-                                transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
-                                break;
-                        default:
-                                dmacHw_ASSERT(0);
-                        }
-                        pProg->ctl.lo |= transferType |
-                            pConfig->srcUpdate |
-                            pConfig->dstUpdate |
-                            srcTrWidth |
-                            dstTrWidth |
-                            pConfig->srcMaxBurstWidth |
-                            pConfig->dstMaxBurstWidth |
-                            pConfig->srcMasterInterface |
-                            pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-                }
-
-                /* Set block transaction size */
-                pProg->ctl.hi = blkTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
-                /* Look for next descriptor */
-                if (count > 1) {
-                        /* Point to the next descriptor */
-                        pProg = (dmacHw_DESC_t *) pProg->llp;
-
-                        /* Update source and destination address for next iteration */
-                        switch (pConfig->transferType) {
-                        case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-                                if (pConfig->dstScatterWidth) {
-                                        pDstAddr =
-                                            (char *)pDstAddr +
-                                            blkTs * srcTrSize +
-                                            (((blkTs * srcTrSize) /
-                                              pConfig->dstScatterWidth) *
-                                             pConfig->dstScatterJump);
-                                } else {
-                                        pDstAddr =
-                                            (char *)pDstAddr +
-                                            blkTs * srcTrSize;
-                                }
-                                break;
-                        case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-                                if (pConfig->srcGatherWidth) {
-                                        pSrcAddr =
-                                            (char *)pDstAddr +
-                                            blkTs * srcTrSize +
-                                            (((blkTs * srcTrSize) /
-                                              pConfig->srcGatherWidth) *
-                                             pConfig->srcGatherJump);
-                                } else {
-                                        pSrcAddr =
-                                            (char *)pSrcAddr +
-                                            blkTs * srcTrSize;
-                                }
-                                break;
-                        case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
-                                if (pConfig->dstScatterWidth) {
-                                        pDstAddr =
-                                            (char *)pDstAddr +
-                                            blkTs * srcTrSize +
-                                            (((blkTs * srcTrSize) /
-                                              pConfig->dstScatterWidth) *
-                                             pConfig->dstScatterJump);
-                                } else {
-                                        pDstAddr =
-                                            (char *)pDstAddr +
-                                            blkTs * srcTrSize;
-                                }
-
-                                if (pConfig->srcGatherWidth) {
-                                        pSrcAddr =
-                                            (char *)pDstAddr +
-                                            blkTs * srcTrSize +
-                                            (((blkTs * srcTrSize) /
-                                              pConfig->srcGatherWidth) *
-                                             pConfig->srcGatherJump);
-                                } else {
-                                        pSrcAddr =
-                                            (char *)pSrcAddr +
-                                            blkTs * srcTrSize;
-                                }
-                                break;
-                        case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
-                                /* Do not adjust the address */
-                                break;
-                        default:
-                                dmacHw_ASSERT(0);
-                        }
-                } else {
-                        /* At the end of transfer "srcTs" must be zero */
-                        dmacHw_ASSERT(srcTs == 0);
-                }
-                count--;
-        }
-
-        /* Remember the descriptor to initialize the registers */
-        if (pRing->pProg == dmacHw_DESC_INIT) {
-                pRing->pProg = pStart;
-        }
-        /* Indicate that the descriptor is updated */
-        pRing->pEnd = pProg;
-        /* Head pointing to the next descriptor */
-        pRing->pHead = (dmacHw_DESC_t *) pProg->llp;
-        /* Update Tail pointer if destination is a peripheral,
-           because no one is going to read from the pTail
-         */
-        if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-                pRing->pTail = pRing->pHead;
-        }
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Provides DMA controller attributes
-*
-*
-*  @return  DMA controller attributes
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,       /*  [ IN ]  DMA Channel handle */
-                                          dmacHw_CONTROLLER_ATTRIB_e attr       /*  [ IN ]  DMA Controller attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-        switch (attr) {
-        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM:
-                return dmacHw_GET_NUM_CHANNEL(pCblk->module);
-        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE:
-                return (1 <<
-                         (dmacHw_GET_MAX_BLOCK_SIZE
-                          (pCblk->module, pCblk->module) + 2)) - 8;
-        case dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM:
-                return dmacHw_GET_NUM_INTERFACE(pCblk->module);
-        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH:
-                return 32 << dmacHw_GET_CHANNEL_DATA_WIDTH(pCblk->module,
-                                                           pCblk->channel);
-        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE:
-                return GetFifoSize(handle);
-        }
-        dmacHw_ASSERT(0);
-        return 0;
-}
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
deleted file mode 100644
index fe438699d11e..000000000000
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ /dev/null
@@ -1,1017 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_extra.c
-*
-*  @brief   Extra Low level DMA controller driver routines
-*
-*  @note
-*
-*   These routines provide basic DMA functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <linux/types.h>
-#include <linux/stddef.h>
-
-#include <mach/csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-
-extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];    /* Declared in dmacHw.c */
-
-/* ---- External Function Prototypes ------------------------------------- */
-
-/* ---- Internal Use Function Prototypes --------------------------------- */
-/****************************************************************************/
-/**
-*  @brief   Overwrites data length in the descriptor
-*
-*  This function overwrites data length in the descriptor
-*
-*
-*  @return   void
-*
-*  @note
-*          This is only used for PCM channel
-*/
-/****************************************************************************/
-void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,     /*   [ IN ] Configuration settings */
-                          void *pDescriptor,    /*   [ IN ] Descriptor buffer */
-                          size_t dataLen        /*   [ IN ] Data length in bytes */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Helper function to display DMA registers
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static void DisplayRegisterContents(int module, /*   [ IN ] DMA Controller unit  (0-1) */
-                                    int channel,        /*   [ IN ] DMA Channel          (0-7) / -1(all) */
-                                    int (*fpPrint) (const char *, ...)  /*   [ IN ] Callback to the print function */
-    ) {
-        int chan;
-
-        (*fpPrint) ("Displaying register content \n\n");
-        (*fpPrint) ("Module %d: Interrupt raw transfer              0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_RAW_TRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt raw block                 0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_RAW_BLOCK(module)));
-        (*fpPrint) ("Module %d: Interrupt raw src transfer          0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_RAW_STRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt raw dst transfer          0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_RAW_DTRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt raw error                 0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_RAW_ERROR(module)));
-        (*fpPrint) ("--------------------------------------------------\n");
-        (*fpPrint) ("Module %d: Interrupt stat transfer             0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_STAT_TRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt stat block                0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_STAT_BLOCK(module)));
-        (*fpPrint) ("Module %d: Interrupt stat src transfer         0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_STAT_STRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt stat dst transfer         0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_STAT_DTRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt stat error                0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_STAT_ERROR(module)));
-        (*fpPrint) ("--------------------------------------------------\n");
-        (*fpPrint) ("Module %d: Interrupt mask transfer             0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_MASK_TRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt mask block                0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_MASK_BLOCK(module)));
-        (*fpPrint) ("Module %d: Interrupt mask src transfer         0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_MASK_STRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt mask dst transfer         0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_MASK_DTRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt mask error                0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_MASK_ERROR(module)));
-        (*fpPrint) ("--------------------------------------------------\n");
-        (*fpPrint) ("Module %d: Interrupt clear transfer            0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_TRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt clear block               0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_BLOCK(module)));
-        (*fpPrint) ("Module %d: Interrupt clear src transfer        0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_STRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt clear dst transfer        0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_DTRAN(module)));
-        (*fpPrint) ("Module %d: Interrupt clear error               0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_ERROR(module)));
-        (*fpPrint) ("--------------------------------------------------\n");
-        (*fpPrint) ("Module %d: SW source req                       0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_REQ(module)));
-        (*fpPrint) ("Module %d: SW dest req                         0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_SW_HS_DST_REQ(module)));
-        (*fpPrint) ("Module %d: SW source signal                    0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_SGL_REQ(module)));
-        (*fpPrint) ("Module %d: SW dest signal                      0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_SW_HS_DST_SGL_REQ(module)));
-        (*fpPrint) ("Module %d: SW source last                      0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_LST_REQ(module)));
-        (*fpPrint) ("Module %d: SW dest last                        0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_SW_HS_DST_LST_REQ(module)));
-        (*fpPrint) ("--------------------------------------------------\n");
-        (*fpPrint) ("Module %d: misc config                         0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_MISC_CFG(module)));
-        (*fpPrint) ("Module %d: misc channel enable                 0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_MISC_CH_ENABLE(module)));
-        (*fpPrint) ("Module %d: misc ID                             0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_MISC_ID(module)));
-        (*fpPrint) ("Module %d: misc test                           0x%X\n",
-                    module, (uint32_t) (dmacHw_REG_MISC_TEST(module)));
-
-        if (channel == -1) {
-                for (chan = 0; chan < 8; chan++) {
-                        (*fpPrint)
-                            ("--------------------------------------------------\n");
-                        (*fpPrint)
-                            ("Module %d: Channel %d Source                   0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_SAR(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Destination              0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_DAR(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d LLP                      0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_LLP(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Control (LO)             0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Control (HI)             0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Source Stats             0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Dest Stats               0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Source Stats Addr        0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Config (LO)              0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
-                        (*fpPrint)
-                            ("Module %d: Channel %d Config (HI)              0x%X\n",
-                             module, chan,
-                             (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
-                }
-        } else {
-                chan = channel;
-                (*fpPrint)
-                    ("--------------------------------------------------\n");
-                (*fpPrint)
-                    ("Module %d: Channel %d Source                   0x%X\n",
-                     module, chan, (uint32_t) (dmacHw_REG_SAR(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Destination              0x%X\n",
-                     module, chan, (uint32_t) (dmacHw_REG_DAR(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d LLP                      0x%X\n",
-                     module, chan, (uint32_t) (dmacHw_REG_LLP(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Control (LO)             0x%X\n",
-                     module, chan,
-                     (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Control (HI)             0x%X\n",
-                     module, chan,
-                     (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Source Stats             0x%X\n",
-                     module, chan, (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Dest Stats               0x%X\n",
-                     module, chan, (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Source Stats Addr        0x%X\n",
-                     module, chan,
-                     (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
-                     module, chan,
-                     (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Config (LO)              0x%X\n",
-                     module, chan,
-                     (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
-                (*fpPrint)
-                    ("Module %d: Channel %d Config (HI)              0x%X\n",
-                     module, chan,
-                     (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
-        }
-}
-
-/****************************************************************************/
-/**
-*  @brief   Helper function to display descriptor ring
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static void DisplayDescRing(void *pDescriptor,  /*   [ IN ] Descriptor buffer */
-                            int (*fpPrint) (const char *, ...)  /*   [ IN ] Callback to the print function */
-    ) {
-        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-        dmacHw_DESC_t *pStart;
-
-        if (pRing->pHead == NULL) {
-                return;
-        }
-
-        pStart = pRing->pHead;
-
-        while ((dmacHw_DESC_t *) pStart->llp != pRing->pHead) {
-                if (pStart == pRing->pHead) {
-                        (*fpPrint) ("Head\n");
-                }
-                if (pStart == pRing->pTail) {
-                        (*fpPrint) ("Tail\n");
-                }
-                if (pStart == pRing->pProg) {
-                        (*fpPrint) ("Prog\n");
-                }
-                if (pStart == pRing->pEnd) {
-                        (*fpPrint) ("End\n");
-                }
-                if (pStart == pRing->pFree) {
-                        (*fpPrint) ("Free\n");
-                }
-                (*fpPrint) ("0x%X:\n", (uint32_t) pStart);
-                (*fpPrint) ("sar    0x%0X\n", pStart->sar);
-                (*fpPrint) ("dar    0x%0X\n", pStart->dar);
-                (*fpPrint) ("llp    0x%0X\n", pStart->llp);
-                (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
-                (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
-                (*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
-                (*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
-                (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
-
-                pStart = (dmacHw_DESC_t *) pStart->llp;
-        }
-        if (pStart == pRing->pHead) {
-                (*fpPrint) ("Head\n");
-        }
-        if (pStart == pRing->pTail) {
-                (*fpPrint) ("Tail\n");
-        }
-        if (pStart == pRing->pProg) {
-                (*fpPrint) ("Prog\n");
-        }
-        if (pStart == pRing->pEnd) {
-                (*fpPrint) ("End\n");
-        }
-        if (pStart == pRing->pFree) {
-                (*fpPrint) ("Free\n");
-        }
-        (*fpPrint) ("0x%X:\n", (uint32_t) pStart);
-        (*fpPrint) ("sar    0x%0X\n", pStart->sar);
-        (*fpPrint) ("dar    0x%0X\n", pStart->dar);
-        (*fpPrint) ("llp    0x%0X\n", pStart->llp);
-        (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
-        (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
-        (*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
-        (*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
-        (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Check if DMA channel is the flow controller
-*
-*  @return  1 : If DMA is a flow controller
-*           0 : Peripheral is the flow controller
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline int DmaIsFlowController(void *pDescriptor /*   [ IN ] Descriptor buffer */
-    ) {
-        uint32_t ttfc =
-            (dmacHw_GET_DESC_RING(pDescriptor))->pTail->ctl.
-            lo & dmacHw_REG_CTL_TTFC_MASK;
-
-        switch (ttfc) {
-        case dmacHw_REG_CTL_TTFC_MM_DMAC:
-        case dmacHw_REG_CTL_TTFC_MP_DMAC:
-        case dmacHw_REG_CTL_TTFC_PM_DMAC:
-        case dmacHw_REG_CTL_TTFC_PP_DMAC:
-                return 1;
-        }
-
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Overwrites data length in the descriptor
-*
-*  This function overwrites data length in the descriptor
-*
-*
-*  @return   void
-*
-*  @note
-*          This is only used for PCM channel
-*/
-/****************************************************************************/
-void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,     /*   [ IN ] Configuration settings */
-                          void *pDescriptor,    /*   [ IN ] Descriptor buffer */
-                          size_t dataLen        /*   [ IN ] Data length in bytes */
-    ) {
-        dmacHw_DESC_t *pProg;
-        dmacHw_DESC_t *pHead;
-        int srcTs = 0;
-        int srcTrSize = 0;
-
-        pHead = (dmacHw_GET_DESC_RING(pDescriptor))->pHead;
-        pProg = pHead;
-
-        srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-        srcTs = dataLen / srcTrSize;
-        do {
-                pProg->ctl.hi = srcTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
-                pProg = (dmacHw_DESC_t *) pProg->llp;
-        } while (pProg != pHead);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the DMA channel specific interrupt
-*
-*
-*  @return   void
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle       /* [ IN ] DMA Channel handle */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-        dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-        dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-        dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Returns the cause of channel specific DMA interrupt
-*
-*  This function returns the cause of interrupt
-*
-*  @return  Interrupt status, each bit representing a specific type of interrupt
-*
-*  @note
-*     Should be called under the context of ISR
-*/
-/****************************************************************************/
-dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle      /* [ IN ] DMA Channel handle */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        dmacHw_INTERRUPT_STATUS_e status = dmacHw_INTERRUPT_STATUS_NONE;
-
-        if (dmacHw_REG_INT_STAT_TRAN(pCblk->module) &
-            ((0x00000001 << pCblk->channel))) {
-                status |= dmacHw_INTERRUPT_STATUS_TRANS;
-        }
-        if (dmacHw_REG_INT_STAT_BLOCK(pCblk->module) &
-            ((0x00000001 << pCblk->channel))) {
-                status |= dmacHw_INTERRUPT_STATUS_BLOCK;
-        }
-        if (dmacHw_REG_INT_STAT_ERROR(pCblk->module) &
-            ((0x00000001 << pCblk->channel))) {
-                status |= dmacHw_INTERRUPT_STATUS_ERROR;
-        }
-
-        return status;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a DMA channel causing interrupt
-*
-*  This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
-*
-*  @return  NULL   : No channel causing DMA interrupt
-*           ! NULL : Handle to a channel causing DMA interrupt
-*  @note
-*     dmacHw_clearInterrupt() must be called with a valid handle after calling this function
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getInterruptSource(void)
-{
-        uint32_t i;
-
-        for (i = 0; i < dmaChannelCount_0 + dmaChannelCount_1; i++) {
-                if ((dmacHw_REG_INT_STAT_TRAN(dmacHw_gCblk[i].module) &
-                     ((0x00000001 << dmacHw_gCblk[i].channel)))
-                    || (dmacHw_REG_INT_STAT_BLOCK(dmacHw_gCblk[i].module) &
-                        ((0x00000001 << dmacHw_gCblk[i].channel)))
-                    || (dmacHw_REG_INT_STAT_ERROR(dmacHw_gCblk[i].module) &
-                        ((0x00000001 << dmacHw_gCblk[i].channel)))
-                    ) {
-                        return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[i]);
-                }
-        }
-        return dmacHw_CBLK_TO_HANDLE(NULL);
-}
-
-/****************************************************************************/
-/**
-*  @brief  Estimates number of descriptor needed to perform certain DMA transfer
-*
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor count
-*
-*
-*/
-/****************************************************************************/
-int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,   /*   [ IN ] Configuration settings */
-                                    void *pSrcAddr,     /*   [ IN ] Source (Peripheral/Memory) address */
-                                    void *pDstAddr,     /*   [ IN ] Destination (Peripheral/Memory) address */
-                                    size_t dataLen      /*   [ IN ] Data length in bytes */
-    ) {
-        int srcTs = 0;
-        int oddSize = 0;
-        int descCount = 0;
-        int dstTrSize = 0;
-        int srcTrSize = 0;
-        uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
-        dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
-        dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
-
-        dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-        srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-
-        /* Skip Tx if buffer is NULL  or length is unknown */
-        if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
-                /* Do not initiate transfer */
-                return -1;
-        }
-
-        /* Ensure scatter and gather are transaction aligned */
-        if (pConfig->srcGatherWidth % srcTrSize
-            || pConfig->dstScatterWidth % dstTrSize) {
-                return -1;
-        }
-
-        /*
-           Background 1: DMAC can not perform DMA if source and destination addresses are
-           not properly aligned with the channel's transaction width. So, for successful
-           DMA transfer, transaction width must be set according to the alignment of the
-           source and destination address.
-         */
-
-        /* Adjust destination transaction width if destination address is not aligned properly */
-        dstTrWidth = pConfig->dstMaxTransactionWidth;
-        while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
-                dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
-                dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
-        }
-
-        /* Adjust source transaction width if source address is not aligned properly */
-        srcTrWidth = pConfig->srcMaxTransactionWidth;
-        while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
-                srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
-                srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
-        }
-
-        /* Find the maximum transaction per descriptor */
-        if (pConfig->maxDataPerBlock
-            && ((pConfig->maxDataPerBlock / srcTrSize) <
-                dmacHw_MAX_BLOCKSIZE)) {
-                maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
-        }
-
-        /* Find number of source transactions needed to complete the DMA transfer */
-        srcTs = dataLen / srcTrSize;
-        /* Find the odd number of bytes that need to be transferred as single byte transaction width */
-        if (srcTs && (dstTrSize > srcTrSize)) {
-                oddSize = dataLen % dstTrSize;
-                /* Adjust source transaction count due to "oddSize" */
-                srcTs = srcTs - (oddSize / srcTrSize);
-        } else {
-                oddSize = dataLen % srcTrSize;
-        }
-        /* Adjust "descCount" due to "oddSize" */
-        if (oddSize) {
-                descCount++;
-        }
-
-        /* Find the number of descriptor needed for total "srcTs" */
-        if (srcTs) {
-                descCount += ((srcTs - 1) / maxBlockSize) + 1;
-        }
-
-        return descCount;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Check the existence of pending descriptor
-*
-*  This function confirmes if there is any pending descriptor in the chain
-*  to program the channel
-*
-*  @return  1 : Channel need to be programmed with pending descriptor
-*           0 : No more pending descriptor to programe the channel
-*
-*  @note
-*     - This function should be called from ISR in case there are pending
-*       descriptor to program the channel.
-*
-*     Example:
-*
-*     dmac_isr ()
-*     {
-*         ...
-*         if (dmacHw_descriptorPending (handle))
-*         {
-*            dmacHw_initiateTransfer (handle);
-*         }
-*     }
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,       /*   [ IN ] DMA Channel handle */
-                                  void *pDescriptor     /*   [ IN ] Descriptor buffer */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-        /* Make sure channel is not busy */
-        if (!CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-                /* Check if pEnd is not processed */
-                if (pRing->pEnd) {
-                        /* Something left for processing */
-                        return 1;
-                }
-        }
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to stop transfer
-*
-*  Ensures the channel is not doing any transfer after calling this function
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /*   [ IN ] DMA Channel handle */
-    ) {
-        dmacHw_CBLK_t *pCblk;
-
-        pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-        /* Stop the channel */
-        dmacHw_DMA_STOP(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Deallocates source or destination memory, allocated
-*
-*  This function can be called to deallocate data memory that was DMAed successfully
-*
-*  @return  On failure : -1
-*           On success : Number of buffer freed
-*
-*  @note
-*     This function will be called ONLY, when source OR destination address is pointing
-*     to dynamic memory
-*/
-/****************************************************************************/
-int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,    /*   [ IN ] Configuration settings */
-                   void *pDescriptor,   /*   [ IN ] Descriptor buffer */
-                   void (*fpFree) (void *)      /*   [ IN ] Function pointer to free data memory */
-    ) {
-        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-        uint32_t count = 0;
-
-        if (fpFree == NULL) {
-                return -1;
-        }
-
-        while ((pRing->pFree != pRing->pTail)
-               && (pRing->pFree->ctl.lo & dmacHw_DESC_FREE)) {
-                if (pRing->pFree->devCtl == dmacHw_FREE_USER_MEMORY) {
-                        /* Identify, which memory to free */
-                        if (dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-                                (*fpFree) ((void *)pRing->pFree->dar);
-                        } else {
-                                /* Destination was a peripheral */
-                                (*fpFree) ((void *)pRing->pFree->sar);
-                        }
-                        /* Unmark user memory to indicate it is freed */
-                        pRing->pFree->devCtl = ~dmacHw_FREE_USER_MEMORY;
-                }
-                dmacHw_NEXT_DESC(pRing, pFree);
-
-                count++;
-        }
-
-        return count;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Prepares descriptor ring, when source peripheral working as a flow controller
-*
-*  This function will update the discriptor ring by allocating buffers, when source peripheral
-*  has to work as a flow controller to transfer data from:
-*           - Peripheral to memory.
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor updated
-*
-*
-*  @note
-*     Channel must be configured for peripheral to memory transfer
-*
-*/
-/****************************************************************************/
-int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,    /*   [ IN ] DMA Channel handle */
-                                     dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
-                                     void *pDescriptor, /*   [ IN ] Descriptor buffer */
-                                     uint32_t srcAddr,  /*   [ IN ] Source peripheral address */
-                                     void *(*fpAlloc) (int len),        /*   [ IN ] Function pointer  that provides destination memory */
-                                     int len,   /*   [ IN ] Number of bytes "fpAlloc" will allocate for destination */
-                                     int num    /*   [ IN ] Number of descriptor to set */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-        dmacHw_DESC_t *pProg = NULL;
-        dmacHw_DESC_t *pLast = NULL;
-        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-        uint32_t dstAddr;
-        uint32_t controlParam;
-        int i;
-
-        dmacHw_ASSERT(pConfig->transferType ==
-                      dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM);
-
-        if (num > pRing->num) {
-                return -1;
-        }
-
-        pLast = pRing->pEnd;    /* Last descriptor updated */
-        pProg = pRing->pHead;   /* First descriptor in the new list */
-
-        controlParam = pConfig->srcUpdate |
-            pConfig->dstUpdate |
-            pConfig->srcMaxTransactionWidth |
-            pConfig->dstMaxTransactionWidth |
-            pConfig->srcMasterInterface |
-            pConfig->dstMasterInterface |
-            pConfig->srcMaxBurstWidth |
-            pConfig->dstMaxBurstWidth |
-            dmacHw_REG_CTL_TTFC_PM_PERI |
-            dmacHw_REG_CTL_LLP_DST_EN |
-            dmacHw_REG_CTL_LLP_SRC_EN | dmacHw_REG_CTL_INT_EN;
-
-        for (i = 0; i < num; i++) {
-                /* Allocate Rx buffer only for idle descriptor */
-                if (((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) ||
-                    ((dmacHw_DESC_t *) pRing->pHead->llp == pRing->pTail)
-                    ) {
-                        /* Rx descriptor is not idle */
-                        break;
-                }
-                /* Set source address */
-                pRing->pHead->sar = srcAddr;
-                if (fpAlloc) {
-                        /* Allocate memory for buffer in descriptor */
-                        dstAddr = (uint32_t) (*fpAlloc) (len);
-                        /* Check the destination address */
-                        if (dstAddr == 0) {
-                                if (i == 0) {
-                                        /* Not a single descriptor is available */
-                                        return -1;
-                                }
-                                break;
-                        }
-                        /* Set destination address */
-                        pRing->pHead->dar = dstAddr;
-                }
-                /* Set control information */
-                pRing->pHead->ctl.lo = controlParam;
-                /* Use "devCtl" to mark the memory that need to be freed later */
-                pRing->pHead->devCtl = dmacHw_FREE_USER_MEMORY;
-                /* Descriptor is now owned by the channel */
-                pRing->pHead->ctl.hi = 0;
-                /* Remember the descriptor last updated */
-                pRing->pEnd = pRing->pHead;
-                /* Update next descriptor */
-                dmacHw_NEXT_DESC(pRing, pHead);
-        }
-
-        /* Mark the end of the list */
-        pRing->pEnd->ctl.lo &=
-            ~(dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN);
-        /* Connect the list */
-        if (pLast != pProg) {
-                pLast->ctl.lo |=
-                    dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN;
-        }
-        /* Mark the descriptors are updated */
-        pCblk->descUpdated = 1;
-        if (!pCblk->varDataStarted) {
-                /* LLP must be pointing to the first descriptor */
-                dmacHw_SET_LLP(pCblk->module, pCblk->channel,
-                               (uint32_t) pProg - pRing->virt2PhyOffset);
-                /* Channel, handling variable data started */
-                pCblk->varDataStarted = 1;
-        }
-
-        return i;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Read data DMAed to memory
-*
-*  This function will read data that has been DMAed to memory while transferring from:
-*          - Memory to memory
-*          - Peripheral to memory
-*
-*  @param    handle     -
-*  @param    ppBbuf     -
-*  @param    pLen       -
-*
-*  @return  0 - No more data is available to read
-*           1 - More data might be available to read
-*
-*/
-/****************************************************************************/
-int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle */
-                               dmacHw_CONFIG_t *pConfig,        /*   [ IN ]  Configuration settings */
-                               void *pDescriptor,       /*   [ IN ] Descriptor buffer */
-                               void **ppBbuf,   /*   [ OUT ] Data received */
-                               size_t *pLlen    /*   [ OUT ] Length of the data received */
-    ) {
-        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-        (void)handle;
-
-        if (pConfig->transferMode != dmacHw_TRANSFER_MODE_CONTINUOUS) {
-                if (((pRing->pTail->ctl.hi & dmacHw_DESC_FREE) == 0) ||
-                    (pRing->pTail == pRing->pHead)
-                    ) {
-                        /* No receive data available */
-                        *ppBbuf = (char *)NULL;
-                        *pLlen = 0;
-
-                        return 0;
-                }
-        }
-
-        /* Return read buffer and length */
-        *ppBbuf = (char *)pRing->pTail->dar;
-
-        /* Extract length of the received data */
-        if (DmaIsFlowController(pDescriptor)) {
-                uint32_t srcTrSize = 0;
-
-                switch (pRing->pTail->ctl.lo & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
-                case dmacHw_REG_CTL_SRC_TR_WIDTH_8:
-                        srcTrSize = 1;
-                        break;
-                case dmacHw_REG_CTL_SRC_TR_WIDTH_16:
-                        srcTrSize = 2;
-                        break;
-                case dmacHw_REG_CTL_SRC_TR_WIDTH_32:
-                        srcTrSize = 4;
-                        break;
-                case dmacHw_REG_CTL_SRC_TR_WIDTH_64:
-                        srcTrSize = 8;
-                        break;
-                default:
-                        dmacHw_ASSERT(0);
-                }
-                /* Calculate length from the block size */
-                *pLlen =
-                    (pRing->pTail->ctl.hi & dmacHw_REG_CTL_BLOCK_TS_MASK) *
-                    srcTrSize;
-        } else {
-                /* Extract length from the source peripheral */
-                *pLlen = pRing->pTail->sstat;
-        }
-
-        /* Advance tail to next descriptor */
-        dmacHw_NEXT_DESC(pRing, pTail);
-
-        return 1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptor carrying control information
-*
-*  This function will be used to send specific control information to the device
-*  using the DMA channel
-*
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,       /*   [ IN ] Configuration settings */
-                                void *pDescriptor,      /*   [ IN ] Descriptor buffer */
-                                uint32_t ctlAddress,    /*   [ IN ] Address of the device control register */
-                                uint32_t control        /*   [ IN ] Device control information */
-    ) {
-        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-        if (ctlAddress == 0) {
-                return -1;
-        }
-
-        /* Check the availability of descriptors in the ring */
-        if ((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) {
-                return -1;
-        }
-        /* Set control information */
-        pRing->pHead->devCtl = control;
-        /* Set source and destination address */
-        pRing->pHead->sar = (uint32_t) &pRing->pHead->devCtl;
-        pRing->pHead->dar = ctlAddress;
-        /* Set control parameters */
-        if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
-                pRing->pHead->ctl.lo = pConfig->transferType |
-                    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
-                    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
-                    dmacHw_SRC_TRANSACTION_WIDTH_32 |
-                    pConfig->dstMaxTransactionWidth |
-                    dmacHw_SRC_BURST_WIDTH_0 |
-                    dmacHw_DST_BURST_WIDTH_0 |
-                    pConfig->srcMasterInterface |
-                    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-        } else {
-                uint32_t transferType = 0;
-                switch (pConfig->transferType) {
-                case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-                        transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
-                        break;
-                case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-                        transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
-                        break;
-                default:
-                        dmacHw_ASSERT(0);
-                }
-                pRing->pHead->ctl.lo = transferType |
-                    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
-                    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
-                    dmacHw_SRC_TRANSACTION_WIDTH_32 |
-                    pConfig->dstMaxTransactionWidth |
-                    dmacHw_SRC_BURST_WIDTH_0 |
-                    dmacHw_DST_BURST_WIDTH_0 |
-                    pConfig->srcMasterInterface |
-                    pConfig->dstMasterInterface |
-                    pConfig->flowControler | dmacHw_REG_CTL_INT_EN;
-        }
-
-        /* Set block transaction size to one 32 bit transaction */
-        pRing->pHead->ctl.hi = dmacHw_REG_CTL_BLOCK_TS_MASK & 1;
-
-        /* Remember the descriptor to initialize the registers */
-        if (pRing->pProg == dmacHw_DESC_INIT) {
-                pRing->pProg = pRing->pHead;
-        }
-        pRing->pEnd = pRing->pHead;
-
-        /* Advance the descriptor */
-        dmacHw_NEXT_DESC(pRing, pHead);
-
-        /* Update Tail pointer if destination is a peripheral */
-        if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-                pRing->pTail = pRing->pHead;
-        }
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Sets channel specific user data
-*
-*  This function associates user data to a specific DMA channel
-*
-*/
-/****************************************************************************/
-void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle */
-                               void *userData   /*  [ IN ] User data */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-        pCblk->userData = userData;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets channel specific user data
-*
-*  This function returns user data specific to a DMA channel
-*
-*  @return   user data
-*/
-/****************************************************************************/
-void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle  /*  [ IN ] DMA Channel handle */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-        return pCblk->userData;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Resets descriptor control information
-*
-*  @return  void
-*/
-/****************************************************************************/
-void dmacHw_resetDescriptorControl(void *pDescriptor    /*   [ IN ] Descriptor buffer  */
-    ) {
-        int i;
-        dmacHw_DESC_RING_t *pRing;
-        dmacHw_DESC_t *pDesc;
-
-        pRing = dmacHw_GET_DESC_RING(pDescriptor);
-        pDesc = pRing->pHead;
-
-        for (i = 0; i < pRing->num; i++) {
-                /* Mark descriptor is ready to use */
-                pDesc->ctl.hi = dmacHw_DESC_FREE;
-                /* Look into next link list item */
-                pDesc++;
-        }
-        pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
-        pRing->pProg = dmacHw_DESC_INIT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Displays channel specific registers and other control parameters
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,      /*  [ IN ] DMA Channel handle */
-                           void *pDescriptor,   /*   [ IN ] Descriptor buffer */
-                           int (*fpPrint) (const char *, ...)   /*  [ IN ] Print callback function */
-    ) {
-        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-        DisplayRegisterContents(pCblk->module, pCblk->channel, fpPrint);
-        DisplayDescRing(pDescriptor, fpPrint);
-}
diff --git a/arch/arm/mach-bcmring/csp/tmr/Makefile b/arch/arm/mach-bcmring/csp/tmr/Makefile
deleted file mode 100644
index 244a61ab7697..000000000000
--- a/arch/arm/mach-bcmring/csp/tmr/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += tmrHw.o
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
deleted file mode 100644
index dc4137ff75ca..000000000000
--- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw.c
-*
-*  @brief   Low level Timer driver routines
-*
-*  @note
-*
-*   These routines provide basic timer functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <linux/errno.h>
-#include <linux/types.h>
-
-#include <mach/csp/tmrHw.h>
-#include <mach/csp/tmrHw_reg.h>
-
-#define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
-#define tmrHw_MILLISEC_PER_SEC              (1000)
-
-#define tmrHw_LOW_1_RESOLUTION_COUNT        (tmrHw_LOW_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
-#define tmrHw_LOW_1_MAX_MILLISEC            (0xFFFFFFFF / tmrHw_LOW_1_RESOLUTION_COUNT)
-#define tmrHw_LOW_16_RESOLUTION_COUNT       (tmrHw_LOW_1_RESOLUTION_COUNT / 16)
-#define tmrHw_LOW_16_MAX_MILLISEC           (0xFFFFFFFF / tmrHw_LOW_16_RESOLUTION_COUNT)
-#define tmrHw_LOW_256_RESOLUTION_COUNT      (tmrHw_LOW_1_RESOLUTION_COUNT / 256)
-#define tmrHw_LOW_256_MAX_MILLISEC          (0xFFFFFFFF / tmrHw_LOW_256_RESOLUTION_COUNT)
-
-#define tmrHw_HIGH_1_RESOLUTION_COUNT       (tmrHw_HIGH_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
-#define tmrHw_HIGH_1_MAX_MILLISEC           (0xFFFFFFFF / tmrHw_HIGH_1_RESOLUTION_COUNT)
-#define tmrHw_HIGH_16_RESOLUTION_COUNT      (tmrHw_HIGH_1_RESOLUTION_COUNT / 16)
-#define tmrHw_HIGH_16_MAX_MILLISEC          (0xFFFFFFFF / tmrHw_HIGH_16_RESOLUTION_COUNT)
-#define tmrHw_HIGH_256_RESOLUTION_COUNT     (tmrHw_HIGH_1_RESOLUTION_COUNT / 256)
-#define tmrHw_HIGH_256_MAX_MILLISEC         (0xFFFFFFFF / tmrHw_HIGH_256_RESOLUTION_COUNT)
-
-static void ResetTimer(tmrHw_ID_t timerId)
-    __attribute__ ((section(".aramtext")));
-static int tmrHw_divide(int num, int denom)
-    __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Get timer capability
-*
-*  This function returns various capabilities/attributes of a timer
-*
-*  @return  Capability
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,   /*  [ IN ] Timer Id */
-                                  tmrHw_CAPABILITY_e capability /*  [ IN ] Timer capability */
-) {
-        switch (capability) {
-        case tmrHw_CAPABILITY_CLOCK:
-                return (timerId <=
-                        1) ? tmrHw_LOW_RESOLUTION_CLOCK :
-                    tmrHw_HIGH_RESOLUTION_CLOCK;
-        case tmrHw_CAPABILITY_RESOLUTION:
-                return 32;
-        default:
-                return 0;
-        }
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Resets a timer
-*
-*  This function initializes  timer
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-static void ResetTimer(tmrHw_ID_t timerId       /*  [ IN ] Timer Id */
-) {
-        /* Reset timer */
-        pTmrHw[timerId].LoadValue = 0;
-        pTmrHw[timerId].CurrentValue = 0xFFFFFFFF;
-        pTmrHw[timerId].Control = 0;
-        pTmrHw[timerId].BackgroundLoad = 0;
-        /* Always configure as a 32 bit timer */
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT;
-        /* Clear interrupt only if raw status interrupt is set */
-        if (pTmrHw[timerId].RawInterruptStatus) {
-                pTmrHw[timerId].InterruptClear = 0xFFFFFFFF;
-        }
-}
-
-/****************************************************************************/
-/**
-*  @brief   Sets counter value for an interval in ms
-*
-*  @return   On success: Effective counter value set
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-static tmrHw_INTERVAL_t SetTimerPeriod(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
-                                       tmrHw_INTERVAL_t msec    /*  [ IN ] Interval in milli-second */
-) {
-        uint32_t scale = 0;
-        uint32_t count = 0;
-
-        if (timerId == 0 || timerId == 1) {
-                if (msec <= tmrHw_LOW_1_MAX_MILLISEC) {
-                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-                        scale = tmrHw_LOW_1_RESOLUTION_COUNT;
-                } else if (msec <= tmrHw_LOW_16_MAX_MILLISEC) {
-                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-                        scale = tmrHw_LOW_16_RESOLUTION_COUNT;
-                } else if (msec <= tmrHw_LOW_256_MAX_MILLISEC) {
-                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-                        scale = tmrHw_LOW_256_RESOLUTION_COUNT;
-                } else {
-                        return 0;
-                }
-
-                count = msec * scale;
-                /* Set counter value */
-                pTmrHw[timerId].LoadValue = count;
-                pTmrHw[timerId].BackgroundLoad = count;
-
-        } else if (timerId == 2 || timerId == 3) {
-                if (msec <= tmrHw_HIGH_1_MAX_MILLISEC) {
-                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-                        scale = tmrHw_HIGH_1_RESOLUTION_COUNT;
-                } else if (msec <= tmrHw_HIGH_16_MAX_MILLISEC) {
-                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-                        scale = tmrHw_HIGH_16_RESOLUTION_COUNT;
-                } else if (msec <= tmrHw_HIGH_256_MAX_MILLISEC) {
-                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-                        scale = tmrHw_HIGH_256_RESOLUTION_COUNT;
-                } else {
-                        return 0;
-                }
-
-                count = msec * scale;
-                /* Set counter value */
-                pTmrHw[timerId].LoadValue = count;
-                pTmrHw[timerId].BackgroundLoad = count;
-        }
-        return count / scale;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer in terms of timer interrupt rate
-*
-*  This function initializes a periodic timer to generate specific number of
-*  timer interrupt per second
-*
-*  @return   On success: Effective timer frequency
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
-                                        tmrHw_RATE_t rate       /*  [ IN ] Number of timer interrupt per second */
-) {
-        uint32_t resolution = 0;
-        uint32_t count = 0;
-        ResetTimer(timerId);
-
-        /* Set timer mode periodic */
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-        /* Set timer in highest resolution */
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-
-        if (rate && (timerId == 0 || timerId == 1)) {
-                if (rate > tmrHw_LOW_RESOLUTION_CLOCK) {
-                        return 0;
-                }
-                resolution = tmrHw_LOW_RESOLUTION_CLOCK;
-        } else if (rate && (timerId == 2 || timerId == 3)) {
-                if (rate > tmrHw_HIGH_RESOLUTION_CLOCK) {
-                        return 0;
-                } else {
-                        resolution = tmrHw_HIGH_RESOLUTION_CLOCK;
-                }
-        } else {
-                return 0;
-        }
-        /* Find the counter value */
-        count = resolution / rate;
-        /* Set counter value */
-        pTmrHw[timerId].LoadValue = count;
-        pTmrHw[timerId].BackgroundLoad = count;
-
-        return resolution / count;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt after
-*           certain time interval
-*
-*  This function initializes a periodic timer to generate timer interrupt
-*  after every time interval in millisecond
-*
-*  @return   On success: Effective interval set in milli-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
-                                                tmrHw_INTERVAL_t msec   /*  [ IN ] Interval in milli-second */
-) {
-        ResetTimer(timerId);
-
-        /* Set timer mode periodic */
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-
-        return SetTimerPeriod(timerId, msec);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt just once
-*           after certain time interval
-*
-*  This function initializes a periodic timer to generate a single ticks after
-*  certain time interval in millisecond
-*
-*  @return   On success: Effective interval set in milli-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
-                                               tmrHw_INTERVAL_t msec    /*  [ IN ] Interval in milli-second */
-) {
-        ResetTimer(timerId);
-
-        /* Set timer mode oneshot */
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_ONESHOT;
-
-        return SetTimerPeriod(timerId, msec);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a timer to run as a free running timer
-*
-*  This function initializes a timer to run as a free running timer
-*
-*  @return   Timer resolution (count / sec)
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
-                                       uint32_t divider /*  [ IN ] Dividing the clock frequency */
-) {
-        uint32_t scale = 0;
-
-        ResetTimer(timerId);
-        /* Set timer as free running mode */
-        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_PERIODIC;
-        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-
-        if (divider >= 64) {
-                pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-                scale = 256;
-        } else if (divider >= 8) {
-                pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-                scale = 16;
-        } else {
-                pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-                scale = 1;
-        }
-
-        if (timerId == 0 || timerId == 1) {
-                return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, scale);
-        } else if (timerId == 2 || timerId == 3) {
-                return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, scale);
-        }
-
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Starts a timer
-*
-*  This function starts a preconfigured timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*/
-/****************************************************************************/
-int tmrHw_startTimer(tmrHw_ID_t timerId /*  [ IN ] Timer id */
-) {
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_TIMER_ENABLE;
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Stops a timer
-*
-*  This function stops a running timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*/
-/****************************************************************************/
-int tmrHw_stopTimer(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
-) {
-        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_TIMER_ENABLE;
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets current timer count
-*
-*  This function returns the current timer value
-*
-*  @return  Current downcounting timer value
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId       /*  [ IN ] Timer id */
-) {
-        /* return 32 bit timer value */
-        switch (pTmrHw[timerId].Control & tmrHw_CONTROL_MODE_MASK) {
-        case tmrHw_CONTROL_FREE_RUNNING:
-                if (pTmrHw[timerId].CurrentValue) {
-                        return tmrHw_MAX_COUNT - pTmrHw[timerId].CurrentValue;
-                }
-                break;
-        case tmrHw_CONTROL_PERIODIC:
-        case tmrHw_CONTROL_ONESHOT:
-                return pTmrHw[timerId].BackgroundLoad -
-                    pTmrHw[timerId].CurrentValue;
-        }
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets timer count rate
-*
-*  This function returns the number of counts per second
-*
-*  @return  Count rate
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId      /*  [ IN ] Timer id */
-) {
-        uint32_t divider = 0;
-
-        switch (pTmrHw[timerId].Control & tmrHw_CONTROL_PRESCALE_MASK) {
-        case tmrHw_CONTROL_PRESCALE_1:
-                divider = 1;
-                break;
-        case tmrHw_CONTROL_PRESCALE_16:
-                divider = 16;
-                break;
-        case tmrHw_CONTROL_PRESCALE_256:
-                divider = 256;
-                break;
-        default:
-                tmrHw_ASSERT(0);
-        }
-
-        if (timerId == 0 || timerId == 1) {
-                return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, divider);
-        } else {
-                return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, divider);
-        }
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables timer interrupt
-*
-*  This function enables the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_enableInterrupt(tmrHw_ID_t timerId   /*  [ IN ] Timer id */
-) {
-        pTmrHw[timerId].Control |= tmrHw_CONTROL_INTERRUPT_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables timer interrupt
-*
-*  This function disable the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_disableInterrupt(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
-) {
-        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_INTERRUPT_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the timer interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void tmrHw_clearInterrupt(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
-) {
-        pTmrHw[timerId].InterruptClear = 0x1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets the interrupt status
-*
-*  This function returns timer interrupt status
-*
-*  @return   Interrupt status
-*/
-/****************************************************************************/
-tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
-) {
-        if (pTmrHw[timerId].InterruptStatus) {
-                return tmrHw_INTERRUPT_STATUS_SET;
-        } else {
-                return tmrHw_INTERRUPT_STATUS_UNSET;
-        }
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a timer causing interrupt
-*
-*  This functions returns a timer causing interrupt
-*
-*  @return  0xFFFFFFFF   : No timer causing an interrupt
-*           ! 0xFFFFFFFF : timer causing an interrupt
-*  @note
-*     tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
-*/
-/****************************************************************************/
-tmrHw_ID_t tmrHw_getInterruptSource(void        /*  void */
-) {
-        int i;
-
-        for (i = 0; i < tmrHw_TIMER_NUM_COUNT; i++) {
-                if (pTmrHw[i].InterruptStatus) {
-                        return i;
-                }
-        }
-
-        return 0xFFFFFFFF;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Displays specific timer registers
-*
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void tmrHw_printDebugInfo(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
-                          int (*fpPrint) (const char *, ...)    /*  [ IN ] Print callback function */
-) {
-        (*fpPrint) ("Displaying register contents \n\n");
-        (*fpPrint) ("Timer %d: Load value              0x%X\n", timerId,
-                    pTmrHw[timerId].LoadValue);
-        (*fpPrint) ("Timer %d: Background load value   0x%X\n", timerId,
-                    pTmrHw[timerId].BackgroundLoad);
-        (*fpPrint) ("Timer %d: Control                 0x%X\n", timerId,
-                    pTmrHw[timerId].Control);
-        (*fpPrint) ("Timer %d: Interrupt clear         0x%X\n", timerId,
-                    pTmrHw[timerId].InterruptClear);
-        (*fpPrint) ("Timer %d: Interrupt raw interrupt 0x%X\n", timerId,
-                    pTmrHw[timerId].RawInterruptStatus);
-        (*fpPrint) ("Timer %d: Interrupt status        0x%X\n", timerId,
-                    pTmrHw[timerId].InterruptStatus);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_udelay(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
-                  unsigned long usecs /*  [ IN ] usec to delay */
-) {
-        tmrHw_RATE_t usec_tick_rate;
-        tmrHw_COUNT_t start_time;
-        tmrHw_COUNT_t delta_time;
-
-        start_time = tmrHw_GetCurrentCount(timerId);
-        usec_tick_rate = tmrHw_divide(tmrHw_getCountRate(timerId), 1000000);
-        delta_time = usecs * usec_tick_rate;
-
-        /* Busy wait */
-        while (delta_time > (tmrHw_GetCurrentCount(timerId) - start_time))
-                ;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Local Divide function
-*
-*  This function does the divide
-*
-*  @return divide value
-*
-*/
-/****************************************************************************/
-static int tmrHw_divide(int num, int denom)
-{
-        int r;
-        int t = 1;
-
-        /* Shift denom and t up to the largest value to optimize algorithm */
-        /* t contains the units of each divide */
-        while ((denom & 0x40000000) == 0) {     /* fails if denom=0 */
-                denom = denom << 1;
-                t = t << 1;
-        }
-
-        /* Initialize the result */
-        r = 0;
-
-        do {
-                /* Determine if there exists a positive remainder */
-                if ((num - denom) >= 0) {
-                        /* Accumlate t to the result and calculate a new remainder */
-                        num = num - denom;
-                        r = r + t;
-                }
-                /* Continue to shift denom and shift t down to 0 */
-                denom = denom >> 1;
-                t = t >> 1;
-        } while (t != 0);
-        return r;
-}
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
deleted file mode 100644
index e5fd241fccdc..000000000000
--- a/arch/arm/mach-bcmring/dma.c
+++ /dev/null
@@ -1,1518 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma.c
-*
-*   @brief  Implements the DMA interface.
-*/
-/****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/irqreturn.h>
-#include <linux/proc_fs.h>
-#include <linux/slab.h>
-
-#include <mach/timer.h>
-
-#include <linux/pfn.h>
-#include <linux/atomic.h>
-#include <mach/dma.h>
-
-/* ---- Public Variables ------------------------------------------------- */
-
-/* ---- Private Constants and Types -------------------------------------- */
-
-#define MAKE_HANDLE(controllerIdx, channelIdx)    (((controllerIdx) << 4) | (channelIdx))
-
-#define CONTROLLER_FROM_HANDLE(handle)    (((handle) >> 4) & 0x0f)
-#define CHANNEL_FROM_HANDLE(handle)       ((handle) & 0x0f)
-
-
-/* ---- Private Variables ------------------------------------------------ */
-
-static DMA_Global_t gDMA;
-static struct proc_dir_entry *gDmaDir;
-
-#include "dma_device.c"
-
-/* ---- Private Function Prototypes -------------------------------------- */
-
-/* ---- Functions  ------------------------------------------------------- */
-
-/****************************************************************************/
-/**
-*   Displays information for /proc/dma/channels
-*/
-/****************************************************************************/
-
-static int dma_proc_read_channels(char *buf, char **start, off_t offset,
-                                  int count, int *eof, void *data)
-{
-        int controllerIdx;
-        int channelIdx;
-        int limit = count - 200;
-        int len = 0;
-        DMA_Channel_t *channel;
-
-        if (down_interruptible(&gDMA.lock) < 0) {
-                return -ERESTARTSYS;
-        }
-
-        for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-             controllerIdx++) {
-                for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-                     channelIdx++) {
-                        if (len >= limit) {
-                                break;
-                        }
-
-                        channel =
-                            &gDMA.controller[controllerIdx].channel[channelIdx];
-
-                        len +=
-                            sprintf(buf + len, "%d:%d ", controllerIdx,
-                                    channelIdx);
-
-                        if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
-                            0) {
-                                len +=
-                                    sprintf(buf + len, "Dedicated for %s ",
-                                            DMA_gDeviceAttribute[channel->
-                                                                 devType].name);
-                        } else {
-                                len += sprintf(buf + len, "Shared ");
-                        }
-
-                        if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) != 0) {
-                                len += sprintf(buf + len, "No ISR ");
-                        }
-
-                        if ((channel->flags & DMA_CHANNEL_FLAG_LARGE_FIFO) != 0) {
-                                len += sprintf(buf + len, "Fifo: 128 ");
-                        } else {
-                                len += sprintf(buf + len, "Fifo: 64  ");
-                        }
-
-                        if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
-                                len +=
-                                    sprintf(buf + len, "InUse by %s",
-                                            DMA_gDeviceAttribute[channel->
-                                                                 devType].name);
-#if (DMA_DEBUG_TRACK_RESERVATION)
-                                len +=
-                                    sprintf(buf + len, " (%s:%d)",
-                                            channel->fileName,
-                                            channel->lineNum);
-#endif
-                        } else {
-                                len += sprintf(buf + len, "Avail ");
-                        }
-
-                        if (channel->lastDevType != DMA_DEVICE_NONE) {
-                                len +=
-                                    sprintf(buf + len, "Last use: %s ",
-                                            DMA_gDeviceAttribute[channel->
-                                                                 lastDevType].
-                                            name);
-                        }
-
-                        len += sprintf(buf + len, "\n");
-                }
-        }
-        up(&gDMA.lock);
-        *eof = 1;
-
-        return len;
-}
-
-/****************************************************************************/
-/**
-*   Displays information for /proc/dma/devices
-*/
-/****************************************************************************/
-
-static int dma_proc_read_devices(char *buf, char **start, off_t offset,
-                                 int count, int *eof, void *data)
-{
-        int limit = count - 200;
-        int len = 0;
-        int devIdx;
-
-        if (down_interruptible(&gDMA.lock) < 0) {
-                return -ERESTARTSYS;
-        }
-
-        for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
-                DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
-
-                if (devAttr->name == NULL) {
-                        continue;
-                }
-
-                if (len >= limit) {
-                        break;
-                }
-
-                len += sprintf(buf + len, "%-12s ", devAttr->name);
-
-                if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-                        len +=
-                            sprintf(buf + len, "Dedicated %d:%d ",
-                                    devAttr->dedicatedController,
-                                    devAttr->dedicatedChannel);
-                } else {
-                        len += sprintf(buf + len, "Shared DMA:");
-                        if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA0) != 0) {
-                                len += sprintf(buf + len, "0");
-                        }
-                        if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA1) != 0) {
-                                len += sprintf(buf + len, "1");
-                        }
-                        len += sprintf(buf + len, " ");
-                }
-                if ((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0) {
-                        len += sprintf(buf + len, "NoISR ");
-                }
-                if ((devAttr->flags & DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO) != 0) {
-                        len += sprintf(buf + len, "Allow-128 ");
-                }
-
-                len +=
-                    sprintf(buf + len,
-                            "Xfer #: %Lu Ticks: %Lu Bytes: %Lu DescLen: %u\n",
-                            devAttr->numTransfers, devAttr->transferTicks,
-                            devAttr->transferBytes,
-                            devAttr->ring.bytesAllocated);
-
-        }
-
-        up(&gDMA.lock);
-        *eof = 1;
-
-        return len;
-}
-
-/****************************************************************************/
-/**
-*   Determines if a DMA_Device_t is "valid".
-*
-*   @return
-*       TRUE        - dma device is valid
-*       FALSE       - dma device isn't valid
-*/
-/****************************************************************************/
-
-static inline int IsDeviceValid(DMA_Device_t device)
-{
-        return (device >= 0) && (device < DMA_NUM_DEVICE_ENTRIES);
-}
-
-/****************************************************************************/
-/**
-*   Translates a DMA handle into a pointer to a channel.
-*
-*   @return
-*       non-NULL    - pointer to DMA_Channel_t
-*       NULL        - DMA Handle was invalid
-*/
-/****************************************************************************/
-
-static inline DMA_Channel_t *HandleToChannel(DMA_Handle_t handle)
-{
-        int controllerIdx;
-        int channelIdx;
-
-        controllerIdx = CONTROLLER_FROM_HANDLE(handle);
-        channelIdx = CHANNEL_FROM_HANDLE(handle);
-
-        if ((controllerIdx > DMA_NUM_CONTROLLERS)
-            || (channelIdx > DMA_NUM_CHANNELS)) {
-                return NULL;
-        }
-        return &gDMA.controller[controllerIdx].channel[channelIdx];
-}
-
-/****************************************************************************/
-/**
-*   Interrupt handler which is called to process DMA interrupts.
-*/
-/****************************************************************************/
-
-static irqreturn_t dma_interrupt_handler(int irq, void *dev_id)
-{
-        DMA_Channel_t *channel;
-        DMA_DeviceAttribute_t *devAttr;
-        int irqStatus;
-
-        channel = (DMA_Channel_t *) dev_id;
-
-        /* Figure out why we were called, and knock down the interrupt */
-
-        irqStatus = dmacHw_getInterruptStatus(channel->dmacHwHandle);
-        dmacHw_clearInterrupt(channel->dmacHwHandle);
-
-        if ((channel->devType < 0)
-            || (channel->devType > DMA_NUM_DEVICE_ENTRIES)) {
-                printk(KERN_ERR "dma_interrupt_handler: Invalid devType: %d\n",
-                       channel->devType);
-                return IRQ_NONE;
-        }
-        devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-        /* Update stats */
-
-        if ((irqStatus & dmacHw_INTERRUPT_STATUS_TRANS) != 0) {
-                devAttr->transferTicks +=
-                    (timer_get_tick_count() - devAttr->transferStartTime);
-        }
-
-        if ((irqStatus & dmacHw_INTERRUPT_STATUS_ERROR) != 0) {
-                printk(KERN_ERR
-                       "dma_interrupt_handler: devType :%d DMA error (%s)\n",
-                       channel->devType, devAttr->name);
-        } else {
-                devAttr->numTransfers++;
-                devAttr->transferBytes += devAttr->numBytes;
-        }
-
-        /* Call any installed handler */
-
-        if (devAttr->devHandler != NULL) {
-                devAttr->devHandler(channel->devType, irqStatus,
-                                    devAttr->userData);
-        }
-
-        return IRQ_HANDLED;
-}
-
-/****************************************************************************/
-/**
-*   Allocates memory to hold a descriptor ring. The descriptor ring then
-*   needs to be populated by making one or more calls to
-*   dna_add_descriptors.
-*
-*   The returned descriptor ring will be automatically initialized.
-*
-*   @return
-*       0           Descriptor ring was allocated successfully
-*       -EINVAL     Invalid parameters passed in
-*       -ENOMEM     Unable to allocate memory for the desired number of descriptors.
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,       /* Descriptor ring to populate */
-                              int numDescriptors        /* Number of descriptors that need to be allocated. */
-    ) {
-        size_t bytesToAlloc = dmacHw_descriptorLen(numDescriptors);
-
-        if ((ring == NULL) || (numDescriptors <= 0)) {
-                return -EINVAL;
-        }
-
-        ring->physAddr = 0;
-        ring->descriptorsAllocated = 0;
-        ring->bytesAllocated = 0;
-
-        ring->virtAddr = dma_alloc_writecombine(NULL,
-                                                     bytesToAlloc,
-                                                     &ring->physAddr,
-                                                     GFP_KERNEL);
-        if (ring->virtAddr == NULL) {
-                return -ENOMEM;
-        }
-
-        ring->bytesAllocated = bytesToAlloc;
-        ring->descriptorsAllocated = numDescriptors;
-
-        return dma_init_descriptor_ring(ring, numDescriptors);
-}
-
-EXPORT_SYMBOL(dma_alloc_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Releases the memory which was previously allocated for a descriptor ring.
-*/
-/****************************************************************************/
-
-void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring        /* Descriptor to release */
-    ) {
-        if (ring->virtAddr != NULL) {
-                dma_free_writecombine(NULL,
-                                      ring->bytesAllocated,
-                                      ring->virtAddr, ring->physAddr);
-        }
-
-        ring->bytesAllocated = 0;
-        ring->descriptorsAllocated = 0;
-        ring->virtAddr = NULL;
-        ring->physAddr = 0;
-}
-
-EXPORT_SYMBOL(dma_free_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Initializes a descriptor ring, so that descriptors can be added to it.
-*   Once a descriptor ring has been allocated, it may be reinitialized for
-*   use with additional/different regions of memory.
-*
-*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
-*   initialize the ring with a smaller number of descriptors. The amount
-*   of memory allocated for the descriptor ring will not be reduced, and
-*   the descriptor ring may be reinitialized later
-*
-*   @return
-*       0           Descriptor ring was initialized successfully
-*       -ENOMEM     The descriptor which was passed in has insufficient space
-*                   to hold the desired number of descriptors.
-*/
-/****************************************************************************/
-
-int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,        /* Descriptor ring to initialize */
-                             int numDescriptors /* Number of descriptors to initialize. */
-    ) {
-        if (ring->virtAddr == NULL) {
-                return -EINVAL;
-        }
-        if (dmacHw_initDescriptor(ring->virtAddr,
-                                  ring->physAddr,
-                                  ring->bytesAllocated, numDescriptors) < 0) {
-                printk(KERN_ERR
-                       "dma_init_descriptor_ring: dmacHw_initDescriptor failed\n");
-                return -ENOMEM;
-        }
-
-        return 0;
-}
-
-EXPORT_SYMBOL(dma_init_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Determines the number of descriptors which would be required for a
-*   transfer of the indicated memory region.
-*
-*   This function also needs to know which DMA device this transfer will
-*   be destined for, so that the appropriate DMA configuration can be retrieved.
-*   DMA parameters such as transfer width, and whether this is a memory-to-memory
-*   or memory-to-peripheral, etc can all affect the actual number of descriptors
-*   required.
-*
-*   @return
-*       > 0     Returns the number of descriptors required for the indicated transfer
-*       -ENODEV - Device handed in is invalid.
-*       -EINVAL Invalid parameters
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */
-                                   dma_addr_t srcData,  /* Place to get data to write to device */
-                                   dma_addr_t dstData,  /* Pointer to device data address */
-                                   size_t numBytes      /* Number of bytes to transfer to the device */
-    ) {
-        int numDescriptors;
-        DMA_DeviceAttribute_t *devAttr;
-
-        if (!IsDeviceValid(device)) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[device];
-
-        numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
-                                                              (void *)srcData,
-                                                              (void *)dstData,
-                                                              numBytes);
-        if (numDescriptors < 0) {
-                printk(KERN_ERR
-                       "dma_calculate_descriptor_count: dmacHw_calculateDescriptorCount failed\n");
-                return -EINVAL;
-        }
-
-        return numDescriptors;
-}
-
-EXPORT_SYMBOL(dma_calculate_descriptor_count);
-
-/****************************************************************************/
-/**
-*   Adds a region of memory to the descriptor ring. Note that it may take
-*   multiple descriptors for each region of memory. It is the callers
-*   responsibility to allocate a sufficiently large descriptor ring.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*       -EINVAL Invalid parameters
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_add_descriptors(DMA_DescriptorRing_t *ring,     /* Descriptor ring to add descriptors to */
-                        DMA_Device_t device,    /* DMA Device that descriptors are for */
-                        dma_addr_t srcData,     /* Place to get data (memory or device) */
-                        dma_addr_t dstData,     /* Place to put data (memory or device) */
-                        size_t numBytes /* Number of bytes to transfer to the device */
-    ) {
-        int rc;
-        DMA_DeviceAttribute_t *devAttr;
-
-        if (!IsDeviceValid(device)) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[device];
-
-        rc = dmacHw_setDataDescriptor(&devAttr->config,
-                                      ring->virtAddr,
-                                      (void *)srcData,
-                                      (void *)dstData, numBytes);
-        if (rc < 0) {
-                printk(KERN_ERR
-                       "dma_add_descriptors: dmacHw_setDataDescriptor failed with code: %d\n",
-                       rc);
-                return -ENOMEM;
-        }
-
-        return 0;
-}
-
-EXPORT_SYMBOL(dma_add_descriptors);
-
-/****************************************************************************/
-/**
-*   Sets the descriptor ring associated with a device.
-*
-*   Once set, the descriptor ring will be associated with the device, even
-*   across channel request/free calls. Passing in a NULL descriptor ring
-*   will release any descriptor ring currently associated with the device.
-*
-*   Note: If you call dma_transfer, or one of the other dma_alloc_ functions
-*         the descriptor ring may be released and reallocated.
-*
-*   Note: This function will release the descriptor memory for any current
-*         descriptor ring associated with this device.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */
-                                   DMA_DescriptorRing_t *ring   /* Descriptor ring to add descriptors to */
-    ) {
-        DMA_DeviceAttribute_t *devAttr;
-
-        if (!IsDeviceValid(device)) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[device];
-
-        /* Free the previously allocated descriptor ring */
-
-        dma_free_descriptor_ring(&devAttr->ring);
-
-        if (ring != NULL) {
-                /* Copy in the new one */
-
-                devAttr->ring = *ring;
-        }
-
-        /* Set things up so that if dma_transfer is called then this descriptor */
-        /* ring will get freed. */
-
-        devAttr->prevSrcData = 0;
-        devAttr->prevDstData = 0;
-        devAttr->prevNumBytes = 0;
-
-        return 0;
-}
-
-EXPORT_SYMBOL(dma_set_device_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Retrieves the descriptor ring associated with a device.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */
-                                   DMA_DescriptorRing_t *ring   /* Place to store retrieved ring */
-    ) {
-        DMA_DeviceAttribute_t *devAttr;
-
-        memset(ring, 0, sizeof(*ring));
-
-        if (!IsDeviceValid(device)) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[device];
-
-        *ring = devAttr->ring;
-
-        return 0;
-}
-
-EXPORT_SYMBOL(dma_get_device_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Configures a DMA channel.
-*
-*   @return
-*       >= 0    - Initialization was successful.
-*
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-static int ConfigChannel(DMA_Handle_t handle)
-{
-        DMA_Channel_t *channel;
-        DMA_DeviceAttribute_t *devAttr;
-        int controllerIdx;
-
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[channel->devType];
-        controllerIdx = CONTROLLER_FROM_HANDLE(handle);
-
-        if ((devAttr->flags & DMA_DEVICE_FLAG_PORT_PER_DMAC) != 0) {
-                if (devAttr->config.transferType ==
-                    dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL) {
-                        devAttr->config.dstPeripheralPort =
-                            devAttr->dmacPort[controllerIdx];
-                } else if (devAttr->config.transferType ==
-                           dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) {
-                        devAttr->config.srcPeripheralPort =
-                            devAttr->dmacPort[controllerIdx];
-                }
-        }
-
-        if (dmacHw_configChannel(channel->dmacHwHandle, &devAttr->config) != 0) {
-                printk(KERN_ERR "ConfigChannel: dmacHw_configChannel failed\n");
-                return -EIO;
-        }
-
-        return 0;
-}
-
-/****************************************************************************/
-/**
-*   Initializes all of the data structures associated with the DMA.
-*   @return
-*       >= 0    - Initialization was successful.
-*
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_init(void)
-{
-        int rc = 0;
-        int controllerIdx;
-        int channelIdx;
-        DMA_Device_t devIdx;
-        DMA_Channel_t *channel;
-        DMA_Handle_t dedicatedHandle;
-
-        memset(&gDMA, 0, sizeof(gDMA));
-
-        sema_init(&gDMA.lock, 0);
-        init_waitqueue_head(&gDMA.freeChannelQ);
-
-        /* Initialize the Hardware */
-
-        dmacHw_initDma();
-
-        /* Start off by marking all of the DMA channels as shared. */
-
-        for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-             controllerIdx++) {
-                for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-                     channelIdx++) {
-                        channel =
-                            &gDMA.controller[controllerIdx].channel[channelIdx];
-
-                        channel->flags = 0;
-                        channel->devType = DMA_DEVICE_NONE;
-                        channel->lastDevType = DMA_DEVICE_NONE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-                        channel->fileName = "";
-                        channel->lineNum = 0;
-#endif
-
-                        channel->dmacHwHandle =
-                            dmacHw_getChannelHandle(dmacHw_MAKE_CHANNEL_ID
-                                                    (controllerIdx,
-                                                     channelIdx));
-                        dmacHw_initChannel(channel->dmacHwHandle);
-                }
-        }
-
-        /* Record any special attributes that channels may have */
-
-        gDMA.controller[0].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-        gDMA.controller[0].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-        gDMA.controller[1].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-        gDMA.controller[1].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-
-        /* Now walk through and record the dedicated channels. */
-
-        for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
-                DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
-
-                if (((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0)
-                    && ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0)) {
-                        printk(KERN_ERR
-                               "DMA Device: %s Can only request NO_ISR for dedicated devices\n",
-                               devAttr->name);
-                        rc = -EINVAL;
-                        goto out;
-                }
-
-                if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-                        /* This is a dedicated device. Mark the channel as being reserved. */
-
-                        if (devAttr->dedicatedController >= DMA_NUM_CONTROLLERS) {
-                                printk(KERN_ERR
-                                       "DMA Device: %s DMA Controller %d is out of range\n",
-                                       devAttr->name,
-                                       devAttr->dedicatedController);
-                                rc = -EINVAL;
-                                goto out;
-                        }
-
-                        if (devAttr->dedicatedChannel >= DMA_NUM_CHANNELS) {
-                                printk(KERN_ERR
-                                       "DMA Device: %s DMA Channel %d is out of range\n",
-                                       devAttr->name,
-                                       devAttr->dedicatedChannel);
-                                rc = -EINVAL;
-                                goto out;
-                        }
-
-                        dedicatedHandle =
-                            MAKE_HANDLE(devAttr->dedicatedController,
-                                        devAttr->dedicatedChannel);
-                        channel = HandleToChannel(dedicatedHandle);
-
-                        if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
-                            0) {
-                                printk
-                                    ("DMA Device: %s attempting to use same DMA Controller:Channel (%d:%d) as %s\n",
-                                     devAttr->name,
-                                     devAttr->dedicatedController,
-                                     devAttr->dedicatedChannel,
-                                     DMA_gDeviceAttribute[channel->devType].
-                                     name);
-                                rc = -EBUSY;
-                                goto out;
-                        }
-
-                        channel->flags |= DMA_CHANNEL_FLAG_IS_DEDICATED;
-                        channel->devType = devIdx;
-
-                        if (devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) {
-                                channel->flags |= DMA_CHANNEL_FLAG_NO_ISR;
-                        }
-
-                        /* For dedicated channels, we can go ahead and configure the DMA channel now */
-                        /* as well. */
-
-                        ConfigChannel(dedicatedHandle);
-                }
-        }
-
-        /* Go through and register the interrupt handlers */
-
-        for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-             controllerIdx++) {
-                for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-                     channelIdx++) {
-                        channel =
-                            &gDMA.controller[controllerIdx].channel[channelIdx];
-
-                        if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) == 0) {
-                                snprintf(channel->name, sizeof(channel->name),
-                                         "dma %d:%d %s", controllerIdx,
-                                         channelIdx,
-                                         channel->devType ==
-                                         DMA_DEVICE_NONE ? "" :
-                                         DMA_gDeviceAttribute[channel->devType].
-                                         name);
-
-                                rc =
-                                     request_irq(IRQ_DMA0C0 +
-                                                 (controllerIdx *
-                                                  DMA_NUM_CHANNELS) +
-                                                 channelIdx,
-                                                 dma_interrupt_handler,
-                                                 IRQF_DISABLED, channel->name,
-                                                 channel);
-                                if (rc != 0) {
-                                        printk(KERN_ERR
-                                               "request_irq for IRQ_DMA%dC%d failed\n",
-                                               controllerIdx, channelIdx);
-                                }
-                        }
-                }
-        }
-
-        /* Create /proc/dma/channels and /proc/dma/devices */
-
-        gDmaDir = proc_mkdir("dma", NULL);
-
-        if (gDmaDir == NULL) {
-                printk(KERN_ERR "Unable to create /proc/dma\n");
-        } else {
-                create_proc_read_entry("channels", 0, gDmaDir,
-                                       dma_proc_read_channels, NULL);
-                create_proc_read_entry("devices", 0, gDmaDir,
-                                       dma_proc_read_devices, NULL);
-        }
-
-out:
-
-        up(&gDMA.lock);
-
-        return rc;
-}
-
-/****************************************************************************/
-/**
-*   Reserves a channel for use with @a dev. If the device is setup to use
-*   a shared channel, then this function will block until a free channel
-*   becomes available.
-*
-*   @return
-*       >= 0    - A valid DMA Handle.
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-DMA_Handle_t dma_request_channel_dbg
-    (DMA_Device_t dev, const char *fileName, int lineNum)
-#else
-DMA_Handle_t dma_request_channel(DMA_Device_t dev)
-#endif
-{
-        DMA_Handle_t handle;
-        DMA_DeviceAttribute_t *devAttr;
-        DMA_Channel_t *channel;
-        int controllerIdx;
-        int controllerIdx2;
-        int channelIdx;
-
-        if (down_interruptible(&gDMA.lock) < 0) {
-                return -ERESTARTSYS;
-        }
-
-        if ((dev < 0) || (dev >= DMA_NUM_DEVICE_ENTRIES)) {
-                handle = -ENODEV;
-                goto out;
-        }
-        devAttr = &DMA_gDeviceAttribute[dev];
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-        {
-                char *s;
-
-                s = strrchr(fileName, '/');
-                if (s != NULL) {
-                        fileName = s + 1;
-                }
-        }
-#endif
-        if ((devAttr->flags & DMA_DEVICE_FLAG_IN_USE) != 0) {
-                /* This device has already been requested and not been freed */
-
-                printk(KERN_ERR "%s: device %s is already requested\n",
-                       __func__, devAttr->name);
-                handle = -EBUSY;
-                goto out;
-        }
-
-        if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-                /* This device has a dedicated channel. */
-
-                channel =
-                    &gDMA.controller[devAttr->dedicatedController].
-                    channel[devAttr->dedicatedChannel];
-                if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
-                        handle = -EBUSY;
-                        goto out;
-                }
-
-                channel->flags |= DMA_CHANNEL_FLAG_IN_USE;
-                devAttr->flags |= DMA_DEVICE_FLAG_IN_USE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-                channel->fileName = fileName;
-                channel->lineNum = lineNum;
-#endif
-                handle =
-                    MAKE_HANDLE(devAttr->dedicatedController,
-                                devAttr->dedicatedChannel);
-                goto out;
-        }
-
-        /* This device needs to use one of the shared channels. */
-
-        handle = DMA_INVALID_HANDLE;
-        while (handle == DMA_INVALID_HANDLE) {
-                /* Scan through the shared channels and see if one is available */
-
-                for (controllerIdx2 = 0; controllerIdx2 < DMA_NUM_CONTROLLERS;
-                     controllerIdx2++) {
-                        /* Check to see if we should try on controller 1 first. */
-
-                        controllerIdx = controllerIdx2;
-                        if ((devAttr->
-                             flags & DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST) != 0) {
-                                controllerIdx = 1 - controllerIdx;
-                        }
-
-                        /* See if the device is available on the controller being tested */
-
-                        if ((devAttr->
-                             flags & (DMA_DEVICE_FLAG_ON_DMA0 << controllerIdx))
-                            != 0) {
-                                for (channelIdx = 0;
-                                     channelIdx < DMA_NUM_CHANNELS;
-                                     channelIdx++) {
-                                        channel =
-                                            &gDMA.controller[controllerIdx].
-                                            channel[channelIdx];
-
-                                        if (((channel->
-                                              flags &
-                                              DMA_CHANNEL_FLAG_IS_DEDICATED) ==
-                                             0)
-                                            &&
-                                            ((channel->
-                                              flags & DMA_CHANNEL_FLAG_IN_USE)
-                                             == 0)) {
-                                                if (((channel->
-                                                      flags &
-                                                      DMA_CHANNEL_FLAG_LARGE_FIFO)
-                                                     != 0)
-                                                    &&
-                                                    ((devAttr->
-                                                      flags &
-                                                      DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO)
-                                                     == 0)) {
-                                                        /* This channel is a large fifo - don't tie it up */
-                                                        /* with devices that we don't want using it. */
-
-                                                        continue;
-                                                }
-
-                                                channel->flags |=
-                                                    DMA_CHANNEL_FLAG_IN_USE;
-                                                channel->devType = dev;
-                                                devAttr->flags |=
-                                                    DMA_DEVICE_FLAG_IN_USE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-                                                channel->fileName = fileName;
-                                                channel->lineNum = lineNum;
-#endif
-                                                handle =
-                                                    MAKE_HANDLE(controllerIdx,
-                                                                channelIdx);
-
-                                                /* Now that we've reserved the channel - we can go ahead and configure it */
-
-                                                if (ConfigChannel(handle) != 0) {
-                                                        handle = -EIO;
-                                                        printk(KERN_ERR
-                                                               "dma_request_channel: ConfigChannel failed\n");
-                                                }
-                                                goto out;
-                                        }
-                                }
-                        }
-                }
-
-                /* No channels are currently available. Let's wait for one to free up. */
-
-                {
-                        DEFINE_WAIT(wait);
-
-                        prepare_to_wait(&gDMA.freeChannelQ, &wait,
-                                        TASK_INTERRUPTIBLE);
-                        up(&gDMA.lock);
-                        schedule();
-                        finish_wait(&gDMA.freeChannelQ, &wait);
-
-                        if (signal_pending(current)) {
-                                /* We don't currently hold gDMA.lock, so we return directly */
-
-                                return -ERESTARTSYS;
-                        }
-                }
-
-                if (down_interruptible(&gDMA.lock)) {
-                        return -ERESTARTSYS;
-                }
-        }
-
-out:
-        up(&gDMA.lock);
-
-        return handle;
-}
-
-/* Create both _dbg and non _dbg functions for modules. */
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-#undef dma_request_channel
-DMA_Handle_t dma_request_channel(DMA_Device_t dev)
-{
-        return dma_request_channel_dbg(dev, __FILE__, __LINE__);
-}
-
-EXPORT_SYMBOL(dma_request_channel_dbg);
-#endif
-EXPORT_SYMBOL(dma_request_channel);
-
-/****************************************************************************/
-/**
-*   Frees a previously allocated DMA Handle.
-*/
-/****************************************************************************/
-
-int dma_free_channel(DMA_Handle_t handle        /* DMA handle. */
-    ) {
-        int rc = 0;
-        DMA_Channel_t *channel;
-        DMA_DeviceAttribute_t *devAttr;
-
-        if (down_interruptible(&gDMA.lock) < 0) {
-                return -ERESTARTSYS;
-        }
-
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                rc = -EINVAL;
-                goto out;
-        }
-
-        devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-        if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) == 0) {
-                channel->lastDevType = channel->devType;
-                channel->devType = DMA_DEVICE_NONE;
-        }
-        channel->flags &= ~DMA_CHANNEL_FLAG_IN_USE;
-        devAttr->flags &= ~DMA_DEVICE_FLAG_IN_USE;
-
-out:
-        up(&gDMA.lock);
-
-        wake_up_interruptible(&gDMA.freeChannelQ);
-
-        return rc;
-}
-
-EXPORT_SYMBOL(dma_free_channel);
-
-/****************************************************************************/
-/**
-*   Determines if a given device has been configured as using a shared
-*   channel.
-*
-*   @return
-*       0           Device uses a dedicated channel
-*       > zero      Device uses a shared channel
-*       < zero      Error code
-*/
-/****************************************************************************/
-
-int dma_device_is_channel_shared(DMA_Device_t device    /* Device to check. */
-    ) {
-        DMA_DeviceAttribute_t *devAttr;
-
-        if (!IsDeviceValid(device)) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[device];
-
-        return ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0);
-}
-
-EXPORT_SYMBOL(dma_device_is_channel_shared);
-
-/****************************************************************************/
-/**
-*   Allocates buffers for the descriptors. This is normally done automatically
-*   but needs to be done explicitly when initiating a dma from interrupt
-*   context.
-*
-*   @return
-*       0       Descriptors were allocated successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptors(DMA_Handle_t handle,  /* DMA Handle */
-                          dmacHw_TRANSFER_TYPE_e transferType,  /* Type of transfer being performed */
-                          dma_addr_t srcData,   /* Place to get data to write to device */
-                          dma_addr_t dstData,   /* Pointer to device data address */
-                          size_t numBytes       /* Number of bytes to transfer to the device */
-    ) {
-        DMA_Channel_t *channel;
-        DMA_DeviceAttribute_t *devAttr;
-        int numDescriptors;
-        size_t ringBytesRequired;
-        int rc = 0;
-
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                return -ENODEV;
-        }
-
-        devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-        if (devAttr->config.transferType != transferType) {
-                return -EINVAL;
-        }
-
-        /* Figure out how many descriptors we need. */
-
-        /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
-        /*        srcData, dstData, numBytes); */
-
-        numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
-                                                              (void *)srcData,
-                                                              (void *)dstData,
-                                                              numBytes);
-        if (numDescriptors < 0) {
-                printk(KERN_ERR "%s: dmacHw_calculateDescriptorCount failed\n",
-                       __func__);
-                return -EINVAL;
-        }
-
-        /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */
-        /* a new one. */
-
-        ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
-
-        /* printk("ringBytesRequired: %d\n", ringBytesRequired); */
-
-        if (ringBytesRequired > devAttr->ring.bytesAllocated) {
-                /* Make sure that this code path is never taken from interrupt context. */
-                /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */
-                /* allocation needs to have already been done. */
-
-                might_sleep();
-
-                /* Free the old descriptor ring and allocate a new one. */
-
-                dma_free_descriptor_ring(&devAttr->ring);
-
-                /* And allocate a new one. */
-
-                rc =
-                     dma_alloc_descriptor_ring(&devAttr->ring,
-                                               numDescriptors);
-                if (rc < 0) {
-                        printk(KERN_ERR
-                               "%s: dma_alloc_descriptor_ring(%d) failed\n",
-                               __func__, numDescriptors);
-                        return rc;
-                }
-                /* Setup the descriptor for this transfer */
-
-                if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
-                                          devAttr->ring.physAddr,
-                                          devAttr->ring.bytesAllocated,
-                                          numDescriptors) < 0) {
-                        printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n",
-                               __func__);
-                        return -EINVAL;
-                }
-        } else {
-                /* We've already got enough ring buffer allocated. All we need to do is reset */
-                /* any control information, just in case the previous DMA was stopped. */
-
-                dmacHw_resetDescriptorControl(devAttr->ring.virtAddr);
-        }
-
-        /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */
-        /* as last time, then we don't need to call setDataDescriptor again. */
-
-        if (dmacHw_setDataDescriptor(&devAttr->config,
-                                     devAttr->ring.virtAddr,
-                                     (void *)srcData,
-                                     (void *)dstData, numBytes) < 0) {
-                printk(KERN_ERR "%s: dmacHw_setDataDescriptor failed\n",
-                       __func__);
-                return -EINVAL;
-        }
-
-        /* Remember the critical information for this transfer so that we can eliminate */
-        /* another call to dma_alloc_descriptors if the caller reuses the same buffers */
-
-        devAttr->prevSrcData = srcData;
-        devAttr->prevDstData = dstData;
-        devAttr->prevNumBytes = numBytes;
-
-        return 0;
-}
-
-EXPORT_SYMBOL(dma_alloc_descriptors);
-
-/****************************************************************************/
-/**
-*   Allocates and sets up descriptors for a double buffered circular buffer.
-*
-*   This is primarily intended to be used for things like the ingress samples
-*   from a microphone.
-*
-*   @return
-*       > 0     Number of descriptors actually allocated.
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,       /* DMA Handle */
-                                     dma_addr_t srcData,        /* Physical address of source data */
-                                     dma_addr_t dstData1,       /* Physical address of first destination buffer */
-                                     dma_addr_t dstData2,       /* Physical address of second destination buffer */
-                                     size_t numBytes    /* Number of bytes in each destination buffer */
-    ) {
-        DMA_Channel_t *channel;
-        DMA_DeviceAttribute_t *devAttr;
-        int numDst1Descriptors;
-        int numDst2Descriptors;
-        int numDescriptors;
-        size_t ringBytesRequired;
-        int rc = 0;
-
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                return -ENODEV;
-        }
-
-        devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-        /* Figure out how many descriptors we need. */
-
-        /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
-        /*        srcData, dstData, numBytes); */
-
-        numDst1Descriptors =
-             dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
-                                             (void *)dstData1, numBytes);
-        if (numDst1Descriptors < 0) {
-                return -EINVAL;
-        }
-        numDst2Descriptors =
-             dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
-                                             (void *)dstData2, numBytes);
-        if (numDst2Descriptors < 0) {
-                return -EINVAL;
-        }
-        numDescriptors = numDst1Descriptors + numDst2Descriptors;
-        /* printk("numDescriptors: %d\n", numDescriptors); */
-
-        /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */
-        /* a new one. */
-
-        ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
-
-        /* printk("ringBytesRequired: %d\n", ringBytesRequired); */
-
-        if (ringBytesRequired > devAttr->ring.bytesAllocated) {
-                /* Make sure that this code path is never taken from interrupt context. */
-                /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */
-                /* allocation needs to have already been done. */
-
-                might_sleep();
-
-                /* Free the old descriptor ring and allocate a new one. */
-
-                dma_free_descriptor_ring(&devAttr->ring);
-
-                /* And allocate a new one. */
-
-                rc =
-                     dma_alloc_descriptor_ring(&devAttr->ring,
-                                               numDescriptors);
-                if (rc < 0) {
-                        printk(KERN_ERR
-                               "%s: dma_alloc_descriptor_ring(%d) failed\n",
-                               __func__, ringBytesRequired);
-                        return rc;
-                }
-        }
-
-        /* Setup the descriptor for this transfer. Since this function is used with */
-        /* CONTINUOUS DMA operations, we need to reinitialize every time, otherwise */
-        /* setDataDescriptor will keep trying to append onto the end. */
-
-        if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
-                                  devAttr->ring.physAddr,
-                                  devAttr->ring.bytesAllocated,
-                                  numDescriptors) < 0) {
-                printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n", __func__);
-                return -EINVAL;
-        }
-
-        /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */
-        /* as last time, then we don't need to call setDataDescriptor again. */
-
-        if (dmacHw_setDataDescriptor(&devAttr->config,
-                                     devAttr->ring.virtAddr,
-                                     (void *)srcData,
-                                     (void *)dstData1, numBytes) < 0) {
-                printk(KERN_ERR "%s: dmacHw_setDataDescriptor 1 failed\n",
-                       __func__);
-                return -EINVAL;
-        }
-        if (dmacHw_setDataDescriptor(&devAttr->config,
-                                     devAttr->ring.virtAddr,
-                                     (void *)srcData,
-                                     (void *)dstData2, numBytes) < 0) {
-                printk(KERN_ERR "%s: dmacHw_setDataDescriptor 2 failed\n",
-                       __func__);
-                return -EINVAL;
-        }
-
-        /* You should use dma_start_transfer rather than dma_transfer_xxx so we don't */
-        /* try to make the 'prev' variables right. */
-
-        devAttr->prevSrcData = 0;
-        devAttr->prevDstData = 0;
-        devAttr->prevNumBytes = 0;
-
-        return numDescriptors;
-}
-
-EXPORT_SYMBOL(dma_alloc_double_dst_descriptors);
-
-/****************************************************************************/
-/**
-*   Initiates a transfer when the descriptors have already been setup.
-*
-*   This is a special case, and normally, the dma_transfer_xxx functions should
-*   be used.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_start_transfer(DMA_Handle_t handle)
-{
-        DMA_Channel_t *channel;
-        DMA_DeviceAttribute_t *devAttr;
-
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-        dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
-                                devAttr->ring.virtAddr);
-
-        /* Since we got this far, everything went successfully */
-
-        return 0;
-}
-
-EXPORT_SYMBOL(dma_start_transfer);
-
-/****************************************************************************/
-/**
-*   Stops a previously started DMA transfer.
-*
-*   @return
-*       0       Transfer was stopped successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_stop_transfer(DMA_Handle_t handle)
-{
-        DMA_Channel_t *channel;
-
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                return -ENODEV;
-        }
-
-        dmacHw_stopTransfer(channel->dmacHwHandle);
-
-        return 0;
-}
-
-EXPORT_SYMBOL(dma_stop_transfer);
-
-/****************************************************************************/
-/**
-*   Waits for a DMA to complete by polling. This function is only intended
-*   to be used for testing. Interrupts should be used for most DMA operations.
-*/
-/****************************************************************************/
-
-int dma_wait_transfer_done(DMA_Handle_t handle)
-{
-        DMA_Channel_t *channel;
-        dmacHw_TRANSFER_STATUS_e status;
-
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                return -ENODEV;
-        }
-
-        while ((status =
-                dmacHw_transferCompleted(channel->dmacHwHandle)) ==
-               dmacHw_TRANSFER_STATUS_BUSY) {
-                ;
-        }
-
-        if (status == dmacHw_TRANSFER_STATUS_ERROR) {
-                printk(KERN_ERR "%s: DMA transfer failed\n", __func__);
-                return -EIO;
-        }
-        return 0;
-}
-
-EXPORT_SYMBOL(dma_wait_transfer_done);
-
-/****************************************************************************/
-/**
-*   Initiates a DMA, allocating the descriptors as required.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
-*/
-/****************************************************************************/
-
-int dma_transfer(DMA_Handle_t handle,   /* DMA Handle */
-                 dmacHw_TRANSFER_TYPE_e transferType,   /* Type of transfer being performed */
-                 dma_addr_t srcData,    /* Place to get data to write to device */
-                 dma_addr_t dstData,    /* Pointer to device data address */
-                 size_t numBytes        /* Number of bytes to transfer to the device */
-    ) {
-        DMA_Channel_t *channel;
-        DMA_DeviceAttribute_t *devAttr;
-        int rc = 0;
-
-        channel = HandleToChannel(handle);
-        if (channel == NULL) {
-                return -ENODEV;
-        }
-
-        devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-        if (devAttr->config.transferType != transferType) {
-                return -EINVAL;
-        }
-
-        /* We keep track of the information about the previous request for this */
-        /* device, and if the attributes match, then we can use the descriptors we setup */
-        /* the last time, and not have to reinitialize everything. */
-
-        {
-                rc =
-                     dma_alloc_descriptors(handle, transferType, srcData,
-                                           dstData, numBytes);
-                if (rc != 0) {
-                        return rc;
-                }
-        }
-
-        /* And kick off the transfer */
-
-        devAttr->numBytes = numBytes;
-        devAttr->transferStartTime = timer_get_tick_count();
-
-        dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
-                                devAttr->ring.virtAddr);
-
-        /* Since we got this far, everything went successfully */
-
-        return 0;
-}
-
-EXPORT_SYMBOL(dma_transfer);
-
-/****************************************************************************/
-/**
-*   Set the callback function which will be called when a transfer completes.
-*   If a NULL callback function is set, then no callback will occur.
-*
-*   @note   @a devHandler will be called from IRQ context.
-*
-*   @return
-*       0       - Success
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_handler(DMA_Device_t dev,    /* Device to set the callback for. */
-                           DMA_DeviceHandler_t devHandler,      /* Function to call when the DMA completes */
-                           void *userData       /* Pointer which will be passed to devHandler. */
-    ) {
-        DMA_DeviceAttribute_t *devAttr;
-        unsigned long flags;
-
-        if (!IsDeviceValid(dev)) {
-                return -ENODEV;
-        }
-        devAttr = &DMA_gDeviceAttribute[dev];
-
-        local_irq_save(flags);
-
-        devAttr->userData = userData;
-        devAttr->devHandler = devHandler;
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-EXPORT_SYMBOL(dma_set_device_handler);
diff --git a/arch/arm/mach-bcmring/dma_device.c b/arch/arm/mach-bcmring/dma_device.c
deleted file mode 100644
index ca0ad736870b..000000000000
--- a/arch/arm/mach-bcmring/dma_device.c
+++ /dev/null
@@ -1,593 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma_device.c
-*
-*   @brief  private array of DMA_DeviceAttribute_t
-*/
-/****************************************************************************/
-
-DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = {
-        [DMA_DEVICE_MEM_TO_MEM] =       /* MEM 2 MEM */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "mem-to-mem",
-         .config = {
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-
-                    },
-         },
-        [DMA_DEVICE_VPM_MEM_TO_MEM] =   /* VPM */
-        {
-         .flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR,
-         .name = "vpm",
-         .dedicatedController = 0,
-         .dedicatedChannel = 0,
-         /* reserve DMA0:0 for VPM */
-         },
-        [DMA_DEVICE_NAND_MEM_TO_MEM] =  /* NAND */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "nand",
-         .config = {
-                    .srcPeripheralPort = 0,
-                    .dstPeripheralPort = 0,
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_6,
-                    },
-         },
-        [DMA_DEVICE_PIF_MEM_TO_DEV] =   /* PIF TX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
-         | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
-         | DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC,
-         .name = "pif_tx",
-         .dmacPort = {14, 5},
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    /* dstPeripheralPort          = 5 or 14 */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-                    .maxDataPerBlock = 16256,
-                    },
-         },
-        [DMA_DEVICE_PIF_DEV_TO_MEM] =   /* PIF RX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
-         | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
-         /* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */
-         | DMA_DEVICE_FLAG_PORT_PER_DMAC,
-         .name = "pif_rx",
-         .dmacPort = {14, 5},
-         .config = {
-                    /* srcPeripheralPort          = 5 or 14 */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-                    .maxDataPerBlock = 16256,
-                    },
-         },
-        [DMA_DEVICE_I2S0_DEV_TO_MEM] =  /* I2S RX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "i2s0_rx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: I2S0 */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-                    },
-         },
-        [DMA_DEVICE_I2S0_MEM_TO_DEV] =  /* I2S TX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "i2s0_tx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 1,     /* DST: I2S0 */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    },
-         },
-        [DMA_DEVICE_I2S1_DEV_TO_MEM] =  /* I2S1 RX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "i2s1_rx",
-         .config = {
-                    .srcPeripheralPort = 2,     /* SRC: I2S1 */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-                    },
-         },
-        [DMA_DEVICE_I2S1_MEM_TO_DEV] =  /* I2S1 TX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "i2s1_tx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 3,     /* DST: I2S1 */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    },
-         },
-        [DMA_DEVICE_ESW_MEM_TO_DEV] =   /* ESW TX */
-        {
-         .name = "esw_tx",
-         .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
-         .dedicatedController = 1,
-         .dedicatedChannel = 3,
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 1,     /* DST: ESW (MTP) */
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    /* DMAx_AHB_SSTATARy */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    /* DMAx_AHB_DSTATARy */
-                    .dstStatusRegisterAddress = 0x30490010,
-                    /* DMAx_AHB_CFGy */
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    /* DMAx_AHB_CTLy */
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    },
-         },
-        [DMA_DEVICE_ESW_DEV_TO_MEM] =   /* ESW RX */
-        {
-         .name = "esw_rx",
-         .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
-         .dedicatedController = 1,
-         .dedicatedChannel = 2,
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: ESW (PTM) */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    /* DMAx_AHB_SSTATARy */
-                    .srcStatusRegisterAddress = 0x30480010,
-                    /* DMAx_AHB_DSTATARy */
-                    .dstStatusRegisterAddress = 0x00000000,
-                    /* DMAx_AHB_CFGy */
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    /* DMAx_AHB_CTLy */
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    },
-         },
-        [DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] =   /* APM Codec A Ingress */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "apm_a_rx",
-         .config = {
-                    .srcPeripheralPort = 2,     /* SRC: Codec A Ingress FIFO */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-                    },
-         },
-        [DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] =   /* APM Codec A Egress */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "apm_a_tx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 3,     /* DST: Codec A Egress FIFO */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    },
-         },
-        [DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] =   /* APM Codec B Ingress */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "apm_b_rx",
-         .config = {
-                    .srcPeripheralPort = 4,     /* SRC: Codec B Ingress FIFO */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-                    },
-         },
-        [DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] =   /* APM Codec B Egress */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "apm_b_tx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 5,     /* DST: Codec B Egress FIFO */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    },
-         },
-        [DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] =   /* APM Codec C Ingress */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "apm_c_rx",
-         .config = {
-                    .srcPeripheralPort = 4,     /* SRC: Codec C Ingress FIFO */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-                    },
-         },
-        [DMA_DEVICE_APM_PCM0_DEV_TO_MEM] =      /* PCM0 RX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "pcm0_rx",
-         .config = {
-                    .srcPeripheralPort = 12,    /* SRC: PCM0 */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-                    },
-         },
-        [DMA_DEVICE_APM_PCM0_MEM_TO_DEV] =      /* PCM0 TX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0,
-         .name = "pcm0_tx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 13,    /* DST: PCM0 */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    },
-         },
-        [DMA_DEVICE_APM_PCM1_DEV_TO_MEM] =      /* PCM1 RX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "pcm1_rx",
-         .config = {
-                    .srcPeripheralPort = 14,    /* SRC: PCM1 */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-                    },
-         },
-        [DMA_DEVICE_APM_PCM1_MEM_TO_DEV] =      /* PCM1 TX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "pcm1_tx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 15,    /* DST: PCM1 */
-                    .srcStatusRegisterAddress = 0,
-                    .dstStatusRegisterAddress = 0,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    },
-         },
-        [DMA_DEVICE_SPUM_DEV_TO_MEM] =  /* SPUM RX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "spum_rx",
-         .config = {
-                    .srcPeripheralPort = 6,     /* SRC: Codec A Ingress FIFO */
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    /* Busrt size **MUST** be 16 for SPUM to work */
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    /* on the RX side, SPU needs to be the flow controller */
-                    .flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL,
-                    },
-         },
-        [DMA_DEVICE_SPUM_MEM_TO_DEV] =  /* SPUM TX */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "spum_tx",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .dstPeripheralPort = 7,     /* DST: SPUM */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-                    /* Busrt size **MUST** be 16 for SPUM to work */
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
-                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-                    },
-         },
-        [DMA_DEVICE_MEM_TO_VRAM] =      /* MEM 2 VRAM */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "mem-to-vram",
-         .config = {
-                    .srcPeripheralPort = 0,     /* SRC: memory */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-                    },
-         },
-        [DMA_DEVICE_VRAM_TO_MEM] =      /* VRAM 2 MEM */
-        {
-         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-         .name = "vram-to-mem",
-         .config = {
-                    .dstPeripheralPort = 0,     /* DST: memory */
-                    .srcStatusRegisterAddress = 0x00000000,
-                    .dstStatusRegisterAddress = 0x00000000,
-                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-                    },
-         },
-};
-EXPORT_SYMBOL(DMA_gDeviceAttribute);    /* primarily for dma-test.c */
diff --git a/arch/arm/mach-bcmring/include/mach/cfg_global.h b/arch/arm/mach-bcmring/include/mach/cfg_global.h
deleted file mode 100644
index 449133eacdf5..000000000000
--- a/arch/arm/mach-bcmring/include/mach/cfg_global.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*****************************************************************************
-* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CFG_GLOBAL_DEFINES_H
-#define CFG_GLOBAL_DEFINES_H
-
-/* CHIP */
-#define BCM1103 1
-
-#define BCM1191 4
-#define BCM2153 5
-#define BCM2820 6
-
-#define BCM2826 8
-#define FPGA11107 9
-#define BCM11107   10
-#define BCM11109   11
-#define BCM11170   12
-#define BCM11110   13
-#define BCM11211   14
-
-/* CFG_GLOBAL_CHIP_FAMILY types */
-#define CFG_GLOBAL_CHIP_FAMILY_NONE        0
-#define CFG_GLOBAL_CHIP_FAMILY_BCM116X     2
-#define CFG_GLOBAL_CHIP_FAMILY_BCMRING     4
-#define CFG_GLOBAL_CHIP_FAMILY_BCM1103     8
-
-#define IMAGE_HEADER_SIZE_CHECKSUM    4
-#endif
-#ifndef _CFG_GLOBAL_H_
-#define _CFG_GLOBAL_H_
-
-#define CFG_GLOBAL_CHIP                         BCM11107
-#define CFG_GLOBAL_CHIP_FAMILY                  CFG_GLOBAL_CHIP_FAMILY_BCMRING
-#define CFG_GLOBAL_CHIP_REV                     0xB0
-#define CFG_GLOBAL_RAM_SIZE                     0x10000000
-#define CFG_GLOBAL_RAM_BASE                     0x00000000
-#define CFG_GLOBAL_RAM_RESERVED_SIZE            0x000000
-
-#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap.h b/arch/arm/mach-bcmring/include/mach/csp/cap.h
deleted file mode 100644
index 30fa2d540630..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/cap.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*****************************************************************************
-* Copyright 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CAP_H
-#define CAP_H
-
-/* ---- Include Files ---------------------------------------------------- */
-/* ---- Public Constants and Types --------------------------------------- */
-typedef enum {
-        CAP_NOT_PRESENT = 0,
-        CAP_PRESENT
-} CAP_RC_T;
-
-typedef enum {
-        CAP_VPM,
-        CAP_ETH_PHY,
-        CAP_ETH_GMII,
-        CAP_ETH_SGMII,
-        CAP_USB,
-        CAP_TSC,
-        CAP_EHSS,
-        CAP_SDIO,
-        CAP_UARTB,
-        CAP_KEYPAD,
-        CAP_CLCD,
-        CAP_GE,
-        CAP_LEDM,
-        CAP_BBL,
-        CAP_VDEC,
-        CAP_PIF,
-        CAP_APM,
-        CAP_SPU,
-        CAP_PKA,
-        CAP_RNG,
-} CAP_CAPABILITY_T;
-
-typedef enum {
-        CAP_LCD_WVGA = 0,
-        CAP_LCD_VGA = 0x1,
-        CAP_LCD_WQVGA = 0x2,
-        CAP_LCD_QVGA = 0x3
-} CAP_LCD_RES_T;
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index);
-static inline uint32_t cap_getMaxArmSpeedHz(void);
-static inline uint32_t cap_getMaxVpmSpeedHz(void);
-static inline CAP_LCD_RES_T cap_getMaxLcdRes(void);
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
deleted file mode 100644
index 0a89e0c63419..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*****************************************************************************
-* Copyright 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CAP_INLINE_H
-#define CAP_INLINE_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/cap.h>
-#include <mach/cfg_global.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-#define CAP_CONFIG0_VPM_DIS          0x00000001
-#define CAP_CONFIG0_ETH_PHY0_DIS     0x00000002
-#define CAP_CONFIG0_ETH_PHY1_DIS     0x00000004
-#define CAP_CONFIG0_ETH_GMII0_DIS    0x00000008
-#define CAP_CONFIG0_ETH_GMII1_DIS    0x00000010
-#define CAP_CONFIG0_ETH_SGMII0_DIS   0x00000020
-#define CAP_CONFIG0_ETH_SGMII1_DIS   0x00000040
-#define CAP_CONFIG0_USB0_DIS         0x00000080
-#define CAP_CONFIG0_USB1_DIS         0x00000100
-#define CAP_CONFIG0_TSC_DIS          0x00000200
-#define CAP_CONFIG0_EHSS0_DIS        0x00000400
-#define CAP_CONFIG0_EHSS1_DIS        0x00000800
-#define CAP_CONFIG0_SDIO0_DIS        0x00001000
-#define CAP_CONFIG0_SDIO1_DIS        0x00002000
-#define CAP_CONFIG0_UARTB_DIS        0x00004000
-#define CAP_CONFIG0_KEYPAD_DIS       0x00008000
-#define CAP_CONFIG0_CLCD_DIS         0x00010000
-#define CAP_CONFIG0_GE_DIS           0x00020000
-#define CAP_CONFIG0_LEDM_DIS         0x00040000
-#define CAP_CONFIG0_BBL_DIS          0x00080000
-#define CAP_CONFIG0_VDEC_DIS         0x00100000
-#define CAP_CONFIG0_PIF_DIS          0x00200000
-#define CAP_CONFIG0_RESERVED1_DIS    0x00400000
-#define CAP_CONFIG0_RESERVED2_DIS    0x00800000
-
-#define CAP_CONFIG1_APMA_DIS         0x00000001
-#define CAP_CONFIG1_APMB_DIS         0x00000002
-#define CAP_CONFIG1_APMC_DIS         0x00000004
-#define CAP_CONFIG1_CLCD_RES_MASK    0x00000600
-#define CAP_CONFIG1_CLCD_RES_SHIFT   9
-#define CAP_CONFIG1_CLCD_RES_WVGA    (CAP_LCD_WVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_VGA     (CAP_LCD_VGA << CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_WQVGA   (CAP_LCD_WQVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_QVGA    (CAP_LCD_QVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
-
-#define CAP_CONFIG2_SPU_DIS          0x00000010
-#define CAP_CONFIG2_PKA_DIS          0x00000020
-#define CAP_CONFIG2_RNG_DIS          0x00000080
-
-#if   (CFG_GLOBAL_CHIP == BCM11107)
-#define capConfig0 0
-#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 3
-#elif (CFG_GLOBAL_CHIP == FPGA11107)
-#define capConfig0 0
-#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 3
-#elif (CFG_GLOBAL_CHIP == BCM11109)
-#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11170)
-#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11110)
-#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 CAP_CONFIG1_APMC_DIS
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | CAP_CONFIG0_CLCD_DIS)
-#define capConfig1 CAP_CONFIG1_APMC_DIS
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 2
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
-#define CAP_HW_CFG_ARM_CLK_HZ 500000000
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
-#define CAP_HW_CFG_ARM_CLK_HZ 300000000
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-#define CAP_HW_CFG_ARM_CLK_HZ 666666666
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
-#define CAP_HW_CFG_VPM_CLK_HZ 333333333
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
-#define CAP_HW_CFG_VPM_CLK_HZ 200000000
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-/****************************************************************************
-*  cap_isPresent -
-*
-*  PURPOSE:
-*     Determines if the chip has a certain capability present
-*
-*  PARAMETERS:
-*     capability - type of capability to determine if present
-*
-*  RETURNS:
-*     CAP_PRESENT or CAP_NOT_PRESENT
-****************************************************************************/
-static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index)
-{
-        CAP_RC_T returnVal = CAP_NOT_PRESENT;
-
-        switch (capability) {
-        case CAP_VPM:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_ETH_PHY:
-                {
-                        if ((index == 0)
-                            && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 1)
-                            && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_ETH_GMII:
-                {
-                        if ((index == 0)
-                            && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 1)
-                            && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_ETH_SGMII:
-                {
-                        if ((index == 0)
-                            && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 1)
-                            && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_USB:
-                {
-                        if ((index == 0)
-                            && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 1)
-                            && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_TSC:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_EHSS:
-                {
-                        if ((index == 0)
-                            && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 1)
-                            && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_SDIO:
-                {
-                        if ((index == 0)
-                            && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 1)
-                            && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_UARTB:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_KEYPAD:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_CLCD:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_GE:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_LEDM:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_BBL:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_VDEC:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_PIF:
-                {
-                        if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_APM:
-                {
-                        if ((index == 0)
-                            && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 1)
-                            && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                        if ((index == 2)
-                            && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_SPU:
-                {
-                        if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_PKA:
-                {
-                        if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        case CAP_RNG:
-                {
-                        if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) {
-                                returnVal = CAP_PRESENT;
-                        }
-                }
-                break;
-
-        default:
-                {
-                }
-                break;
-        }
-        return returnVal;
-}
-
-/****************************************************************************
-*  cap_getMaxArmSpeedHz -
-*
-*  PURPOSE:
-*     Determines the maximum speed of the ARM CPU
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*     clock speed in Hz that the ARM processor is able to run at
-****************************************************************************/
-static inline uint32_t cap_getMaxArmSpeedHz(void)
-{
-#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
-        return 500000000;
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
-        return 300000000;
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-        return 666666666;
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-}
-
-/****************************************************************************
-*  cap_getMaxVpmSpeedHz -
-*
-*  PURPOSE:
-*     Determines the maximum speed of the VPM
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*     clock speed in Hz that the VPM is able to run at
-****************************************************************************/
-static inline uint32_t cap_getMaxVpmSpeedHz(void)
-{
-#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
-        return 333333333;
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
-        return 200000000;
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-}
-
-/****************************************************************************
-*  cap_getMaxLcdRes -
-*
-*  PURPOSE:
-*     Determines the maximum LCD resolution capabilities
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*   CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA
-*
-****************************************************************************/
-static inline CAP_LCD_RES_T cap_getMaxLcdRes(void)
-{
-        return (CAP_LCD_RES_T)
-                ((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >>
-                 CAP_CONFIG1_CLCD_RES_SHIFT);
-}
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
deleted file mode 100644
index 39f09cb89208..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
+++ /dev/null
@@ -1,1123 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CHIPC_DEF_H
-#define CHIPC_DEF_H
-
-/* ---- Include Files ----------------------------------------------------- */
-
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <mach/csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-
-/* ---- Public Constants and Types ---------------------------------------- */
-
-/* Set 1 to configure DDR/VPM phase alignment by HW */
-#define chipcHw_DDR_HW_PHASE_ALIGN    0
-#define chipcHw_VPM_HW_PHASE_ALIGN    0
-
-typedef uint32_t chipcHw_freq;
-
-/* Configurable miscellaneous clocks */
-typedef enum {
-        chipcHw_CLOCK_DDR,      /* DDR PHY Clock */
-        chipcHw_CLOCK_ARM,      /* ARM Clock */
-        chipcHw_CLOCK_ESW,      /* Ethernet Switch Clock */
-        chipcHw_CLOCK_VPM,      /* VPM Clock */
-        chipcHw_CLOCK_ESW125,   /* Ethernet MII Clock */
-        chipcHw_CLOCK_UART,     /* UART Clock */
-        chipcHw_CLOCK_SDIO0,    /* SDIO 0 Clock */
-        chipcHw_CLOCK_SDIO1,    /* SDIO 1 Clock */
-        chipcHw_CLOCK_SPI,      /* SPI Clock */
-        chipcHw_CLOCK_ETM,      /* ARM ETM Clock */
-
-        chipcHw_CLOCK_BUS,      /* BUS Clock */
-        chipcHw_CLOCK_OTP,      /* OTP Clock */
-        chipcHw_CLOCK_I2C,      /* I2C Host Clock */
-        chipcHw_CLOCK_I2S0,     /* I2S 0 Host Clock */
-        chipcHw_CLOCK_RTBUS,    /* DDR PHY Configuration Clock */
-        chipcHw_CLOCK_APM100,   /* APM100 Clock */
-        chipcHw_CLOCK_TSC,      /* Touch screen Clock */
-        chipcHw_CLOCK_LED,      /* LED Clock */
-
-        chipcHw_CLOCK_USB,      /* USB Clock */
-        chipcHw_CLOCK_LCD,      /* LCD CLock */
-        chipcHw_CLOCK_APM,      /* APM Clock */
-
-        chipcHw_CLOCK_I2S1,     /* I2S 1 Host Clock */
-} chipcHw_CLOCK_e;
-
-/* System booting strap options */
-typedef enum {
-        chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART,
-        chipcHw_BOOT_DEVICE_SERIAL_FLASH =
-            chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH,
-        chipcHw_BOOT_DEVICE_NOR_FLASH_16 =
-            chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16,
-        chipcHw_BOOT_DEVICE_NAND_FLASH_8 =
-            chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8,
-        chipcHw_BOOT_DEVICE_NAND_FLASH_16 =
-            chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16
-} chipcHw_BOOT_DEVICE_e;
-
-/* System booting modes */
-typedef enum {
-        chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL,
-        chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW,
-        chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT,
-        chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET
-} chipcHw_BOOT_MODE_e;
-
-/* NAND Flash page size strap options */
-typedef enum {
-        chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512,
-        chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048,
-        chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096,
-        chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT
-} chipcHw_NAND_PAGESIZE_e;
-
-/* GPIO Pin function */
-typedef enum {
-        chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD,
-        chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH,
-        chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI,
-        chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART,
-        chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP,
-        chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS,
-        chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0,
-        chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1,
-        chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM,
-        chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S,
-        chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM,
-        chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG,
-        chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC,
-        chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO
-} chipcHw_GPIO_FUNCTION_e;
-
-/* PIN Output slew rate */
-typedef enum {
-        chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH,
-        chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL
-} chipcHw_PIN_SLEW_RATE_e;
-
-/* PIN Current drive strength */
-typedef enum {
-        chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA,
-        chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA,
-        chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA,
-        chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA,
-        chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA,
-        chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA
-} chipcHw_PIN_CURRENT_STRENGTH_e;
-
-/* PIN Pull up register settings */
-typedef enum {
-        chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE,
-        chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP,
-        chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN
-} chipcHw_PIN_PULL_e;
-
-/* PIN input type settings */
-typedef enum {
-        chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS,
-        chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST
-} chipcHw_PIN_INPUTTYPE_e;
-
-/* Allow/Disalow the support of spread spectrum  */
-typedef enum {
-        chipcHw_SPREAD_SPECTRUM_DISALLOW,       /* Spread spectrum support is not allowed */
-        chipcHw_SPREAD_SPECTRUM_ALLOW   /* Spread spectrum support is allowed */
-} chipcHw_SPREAD_SPECTRUM_e;
-
-typedef struct {
-        chipcHw_SPREAD_SPECTRUM_e ssSupport;    /* Allow/Disalow to support spread spectrum.
-                                                   If supported, call chipcHw_enableSpreadSpectrum ()
-                                                   to activate the spread spectrum with desired spread. */
-        uint32_t pllVcoFreqHz;  /* PLL VCO frequency in Hz */
-        uint32_t pll2VcoFreqHz; /* PLL2 VCO frequency in Hz */
-        uint32_t busClockFreqHz;        /* Bus clock frequency in Hz */
-        uint32_t armBusRatio;   /* ARM clock : Bus clock */
-        uint32_t vpmBusRatio;   /* VPM clock : Bus clock */
-        uint32_t ddrBusRatio;   /* DDR clock : Bus clock */
-} chipcHw_INIT_PARAM_t;
-
-/* CHIP revision number */
-typedef enum {
-        chipcHw_REV_NUMBER_A0 = chipcHw_REG_REV_A0,
-        chipcHw_REV_NUMBER_B0 = chipcHw_REG_REV_B0
-} chipcHw_REV_NUMBER_e;
-
-typedef enum {
-        chipcHw_VPM_HW_PHASE_INTR_DISABLE = chipcHw_REG_VPM_INTR_DISABLE,
-        chipcHw_VPM_HW_PHASE_INTR_FAST = chipcHw_REG_VPM_INTR_FAST,
-        chipcHw_VPM_HW_PHASE_INTR_MEDIUM = chipcHw_REG_VPM_INTR_MEDIUM,
-        chipcHw_VPM_HW_PHASE_INTR_SLOW = chipcHw_REG_VPM_INTR_SLOW
-} chipcHw_VPM_HW_PHASE_INTR_e;
-
-typedef enum {
-        chipcHw_DDR_HW_PHASE_MARGIN_STRICT,     /*  Strict margin for DDR phase align condition */
-        chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM,     /*  Medium margin for DDR phase align condition */
-        chipcHw_DDR_HW_PHASE_MARGIN_WIDE        /*  Wider margin for DDR phase align condition */
-} chipcHw_DDR_HW_PHASE_MARGIN_e;
-
-typedef enum {
-        chipcHw_VPM_HW_PHASE_MARGIN_STRICT,     /*  Strict margin for VPM phase align condition */
-        chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM,     /*  Medium margin for VPM phase align condition */
-        chipcHw_VPM_HW_PHASE_MARGIN_WIDE        /*  Wider margin for VPM phase align condition */
-} chipcHw_VPM_HW_PHASE_MARGIN_e;
-
-#define chipcHw_XTAL_FREQ_Hz                    25000000        /* Reference clock frequency in Hz */
-
-/* Programmable pin defines */
-#define chipcHw_PIN_GPIO(n)                     ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF)
-                                                                             /* GPIO pin 0 - 60 */
-#define chipcHw_PIN_UARTTXD                     (chipcHw_GPIO_COUNT + 0)        /* UART Transmit */
-#define chipcHw_PIN_NVI_A                       (chipcHw_GPIO_COUNT + 1)        /* NVI Interface */
-#define chipcHw_PIN_NVI_D                       (chipcHw_GPIO_COUNT + 2)        /* NVI Interface */
-#define chipcHw_PIN_NVI_OEB                     (chipcHw_GPIO_COUNT + 3)        /* NVI Interface */
-#define chipcHw_PIN_NVI_WEB                     (chipcHw_GPIO_COUNT + 4)        /* NVI Interface */
-#define chipcHw_PIN_NVI_CS                      (chipcHw_GPIO_COUNT + 5)        /* NVI Interface */
-#define chipcHw_PIN_NVI_NAND_CSB                (chipcHw_GPIO_COUNT + 6)        /* NVI Interface */
-#define chipcHw_PIN_NVI_FLASHWP                 (chipcHw_GPIO_COUNT + 7)        /* NVI Interface */
-#define chipcHw_PIN_NVI_NAND_RDYB               (chipcHw_GPIO_COUNT + 8)        /* NVI Interface */
-#define chipcHw_PIN_CL_DATA_0_17                (chipcHw_GPIO_COUNT + 9)        /* LCD Data 0 - 17 */
-#define chipcHw_PIN_CL_DATA_18_20               (chipcHw_GPIO_COUNT + 10)       /* LCD Data 18 - 20 */
-#define chipcHw_PIN_CL_DATA_21_23               (chipcHw_GPIO_COUNT + 11)       /* LCD Data 21 - 23 */
-#define chipcHw_PIN_CL_POWER                    (chipcHw_GPIO_COUNT + 12)       /* LCD Power */
-#define chipcHw_PIN_CL_ACK                      (chipcHw_GPIO_COUNT + 13)       /* LCD Ack */
-#define chipcHw_PIN_CL_FP                       (chipcHw_GPIO_COUNT + 14)       /* LCD FP */
-#define chipcHw_PIN_CL_LP                       (chipcHw_GPIO_COUNT + 15)       /* LCD LP */
-#define chipcHw_PIN_UARTRXD                     (chipcHw_GPIO_COUNT + 16)       /* UART Receive */
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the clock module
-*
-*/
-/****************************************************************************/
-void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam       /*  [ IN ] Misc chip initialization parameter */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Enables the PLL1
-*
-*  This function enables the PLL1
-*
-*/
-/****************************************************************************/
-void chipcHw_pll1Enable(uint32_t vcoFreqHz,     /*  [ IN ] VCO frequency in Hz */
-                        chipcHw_SPREAD_SPECTRUM_e ssSupport     /*  [ IN ] SS status */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Enables the PLL2
-*
-*  This function enables the PLL2
-*
-*/
-/****************************************************************************/
-void chipcHw_pll2Enable(uint32_t vcoFreqHz      /*  [ IN ] VCO frequency in Hz */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL1
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll1Disable(void);
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL2
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll2Disable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in KHz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock    /*  [ IN ] Configurable clock */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in Hz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,   /*  [ IN ] Configurable clock */
-                                       uint32_t freq    /*  [ IN ] Clock frequency in Hz */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success ( # of adjustment required )
-*            -1 : On failure
-*/
-/****************************************************************************/
-int chipcHw_vpmPhaseAlign(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables core a clock of a certain device
-*
-*  This function enables a core clock
-*
-*  @return  void
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock /*  [ IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disabled a core clock of a certain device
-*
-*  This function disables a core clock
-*
-*  @return  void
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock        /*  [ IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Enables bypass clock of a certain device
-*
-*  This function enables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock      /*  [ IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disabled bypass clock of a certain device
-*
-*  This function disables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock     /*  [ IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Get Numeric Chip ID
-*
-*  This function returns Chip ID that includes the revison number
-*
-*  @return  Complete numeric Chip ID
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipId(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get Chip Product ID
-*
-*  This function returns Chip Product ID
-*
-*  @return  Chip Product ID
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipProductId(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get revision number
-*
-*  This function returns revision number of the chip
-*
-*  @return  Revision number
-*/
-/****************************************************************************/
-static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables bus interface clock
-*
-*  Enables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockEnable(uint32_t mask        /*  [ IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disables bus interface clock
-*
-*  Disables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockDisable(uint32_t mask       /*  [ IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Enables various audio channels
-*
-*  Enables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelEnable(uint32_t mask     /*  [ IN ] Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disables various audio channels
-*
-*  Disables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelDisable(uint32_t mask    /*  [ IN ] Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Soft resets devices
-*
-*  Soft resets various devices
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
-*/
-/****************************************************************************/
-static inline void chipcHw_softReset(uint64_t mask      /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-static inline void chipcHw_softResetDisable(uint64_t mask       /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-static inline void chipcHw_softResetEnable(uint64_t mask        /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Configures misc CHIP functionality
-*
-*  Configures CHIP functionality
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_miscControl(uint32_t mask    /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-static inline void chipcHw_miscControlDisable(uint32_t mask     /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-static inline void chipcHw_miscControlEnable(uint32_t mask      /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Set OTP options
-*
-*  Set OTP options
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_OTP_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setOTPOption(uint64_t mask   /*  [ IN ] Bit map of type chipcHw_REG_OTP_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Get sticky bits
-*
-*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getStickyBits(void);
-
-/****************************************************************************/
-/**
-*  @brief    Set sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setStickyBits(uint32_t mask  /*  [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Clear sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_clearStickyBits(uint32_t mask        /*  [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Get software override strap options
-*
-*  Retrieves software override strap options
-*
-*  @return   Software override strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getSoftStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Set software override strap options
-*
-*  set software override strap options
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setSoftStraps(uint32_t strapOptions);
-
-/****************************************************************************/
-/**
-*  @brief    Get pin strap options
-*
-*  Retrieves pin strap options
-*
-*  @return   Pin strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getPinStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Get valid pin strap options
-*
-*  Retrieves valid pin strap options
-*
-*  @return   valid Pin strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getValidStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Initialize valid pin strap options
-*
-*  Retrieves valid pin strap options by copying HW strap options to soft register
-*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_initValidStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get status (enabled/disabled) of bus interface clock
-*
-*  This function returns the status of devices' bus interface clock
-*
-*  @return  Bus interface clock
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getBusInterfaceClockStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get boot device
-*
-*  This function returns the device type used in booting the system
-*
-*  @return  Boot device of type chipcHw_BOOT_DEVICE_e
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get boot mode
-*
-*  This function returns the way the system was booted
-*
-*  @return  Boot mode of type chipcHw_BOOT_MODE_e
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash page size
-*
-*  This function returns the NAND device page size
-*
-*  @return  Boot NAND device page size
-*
-*/
-/****************************************************************************/
-static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash address cycle configuration
-*
-*  This function returns the NAND flash address cycle configuration
-*
-*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
-*
-*/
-/****************************************************************************/
-static inline int chipcHw_getNandExtraCycle(void);
-
-/****************************************************************************/
-/**
-*  @brief   Activates PIF interface
-*
-*  This function activates PIF interface by taking control of LCD pins
-*
-*  @note
-*       When activated, LCD pins will be defined as follows for PIF operation
-*
-*       CLD[17:0]  = pif_data[17:0]
-*       CLD[23:18] = pif_address[5:0]
-*       CLPOWER    = pif_wr_str
-*       CLCP       = pif_rd_str
-*       CLAC       = pif_hat1
-*       CLFP       = pif_hrdy1
-*       CLLP       = pif_hat2
-*       GPIO[42]   = pif_hrdy2
-*
-*       In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_activatePifInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Activates LCD interface
-*
-*  This function activates LCD interface
-*
-*  @note
-*       When activated, LCD pins will be defined as follows
-*
-*       CLD[17:0]  = LCD data
-*       CLD[23:18] = LCD data
-*       CLPOWER    = LCD power
-*       CLCP       =
-*       CLAC       = LCD ack
-*       CLFP       =
-*       CLLP       =
-*/
-/****************************************************************************/
-static inline void chipcHw_activateLcdInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Deactivates PIF/LCD interface
-*
-*  This function deactivates PIF/LCD interface
-*
-*  @note
-*       When deactivated LCD pins will be in rti-stated
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_deactivatePifLcdInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get to know the configuration of GPIO pin
-*
-*/
-/****************************************************************************/
-static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin        /* GPIO Pin number */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Configure GPIO pin function
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setGpioPinFunction(int pin,  /* GPIO Pin number */
-                                              chipcHw_GPIO_FUNCTION_e func      /* Configuration function */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin slew rate
-*
-*  This function sets the slew of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinSlewRate(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
-                                          chipcHw_PIN_SLEW_RATE_e slewRate      /* Pin slew rate */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin output drive current
-*
-*  This function sets output drive current of individual pin
-*
-*  Note: Avoid the use of the word 'current' since linux headers define this
-*        to be the current task.
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinOutputCurrent(uint32_t pin,    /* Pin of type chipcHw_PIN_XXXXX */
-                                               chipcHw_PIN_CURRENT_STRENGTH_e curr      /* Pin current rating */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin pullup register
-*
-*  This function sets pullup register of individual  pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinPullup(uint32_t pin,   /* Pin of type chipcHw_PIN_XXXXX */
-                                        chipcHw_PIN_PULL_e pullup       /* Pullup register settings */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin input type
-*
-*  This function sets input type of individual Pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinInputType(uint32_t pin,        /* Pin of type chipcHw_PIN_XXXXX */
-                                           chipcHw_PIN_INPUTTYPE_e inputType    /* Pin input type */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Retrieves a string representation of the mux setting for a pin.
-*
-*  @return  Pointer to a character string.
-*/
-/****************************************************************************/
-
-const char *chipcHw_getGpioPinFunctionStr(int pin);
-
-/****************************************************************************/
-/**  @brief issue warmReset
- */
-/****************************************************************************/
-void chipcHw_reset(uint32_t mask);
-
-/****************************************************************************/
-/**  @brief clock reconfigure
- */
-/****************************************************************************/
-void chipcHw_clockReconfig(uint32_t busHz, uint32_t armRatio, uint32_t vpmRatio,
-                           uint32_t ddrRatio);
-
-/****************************************************************************/
-/**
-*  @brief   Enable Spread Spectrum
-*
-*  @note chipcHw_Init() must be called earlier
-*/
-/****************************************************************************/
-static inline void chipcHw_enableSpreadSpectrum(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable Spread Spectrum
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_disableSpreadSpectrum(void);
-
-/****************************************************************************/
-/**  @brief Checks if software strap is enabled
- *
- *   @return 1 : When enable
- *           0 : When disable
- */
-/****************************************************************************/
-static inline int chipcHw_isSoftwareStrapsEnable(void);
-
-/****************************************************************************/
-/**  @brief Enable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsEnable(void);
-
-/****************************************************************************/
-/**  @brief Disable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsDisable(void);
-
-/****************************************************************************/
-/**  @brief PLL test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL2 test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestDisable(void);
-
-/****************************************************************************/
-/**  @brief PLL2 test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestDisable(void);
-
-/****************************************************************************/
-/**  @brief Get PLL test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPllTestEnable(void);
-
-/****************************************************************************/
-/**  @brief Get PLL2 test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPll2TestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL test select
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestSelect(uint32_t val);
-
-/****************************************************************************/
-/**  @brief PLL2 test select
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestSelect(uint32_t val);
-
-/****************************************************************************/
-/**  @brief Get PLL test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPllTestSelected(void);
-
-/****************************************************************************/
-/**  @brief Get PLL2 test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPll2TestSelected(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM SW phase alignment interrupt mode
-*
-*  This function sets VPM phase alignment interrupt
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode);
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set DDR phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin        /* Margin alinging DDR  phase */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin        /* Margin alinging VPM  phase */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Checks DDR phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isDdrHwPhaseAligned(void);
-
-/****************************************************************************/
-/**
-*  @brief   Checks VPM phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isVpmHwPhaseAligned(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrPhaseControl(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmPhaseControl(void);
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a DDR phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle     /* Timeout in bus cycle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a VPM phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle     /* Timeout in bus cycle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Clear DDR phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void);
-
-/****************************************************************************/
-/**
-*  @brief   Clear VPM phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void);
-
-/* ---- Private Constants and Types -------------------------------------- */
-
-#endif /* CHIPC_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
deleted file mode 100644
index a66f3f7abb86..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
+++ /dev/null
@@ -1,1682 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CHIPC_INLINE_H
-#define CHIPC_INLINE_H
-
-/* ---- Include Files ----------------------------------------------------- */
-
-#include <linux/errno.h>
-#include <mach/csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_def.h>
-
-/* ---- Private Constants and Types --------------------------------------- */
-typedef enum {
-        chipcHw_OPTYPE_BYPASS,  /* Bypass operation */
-        chipcHw_OPTYPE_OUTPUT   /* Output operation */
-} chipcHw_OPTYPE_e;
-
-/* ---- Public Constants and Types ---------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------- */
-/* ---- Public Function Prototypes ---------------------------------------- */
-/* ---- Private Function Prototypes --------------------------------------- */
-static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
-                                    chipcHw_OPTYPE_e type, int mode);
-
-/****************************************************************************/
-/**
-*  @brief   Get Numeric Chip ID
-*
-*  This function returns Chip ID that includes the revison number
-*
-*  @return  Complete numeric Chip ID
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipId(void)
-{
-        return readl(&pChipcHw->ChipId);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable Spread Spectrum
-*
-*  @note chipcHw_Init() must be called earlier
-*/
-/****************************************************************************/
-static inline void chipcHw_enableSpreadSpectrum(void)
-{
-        if ((readl(&pChipcHw->
-             PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
-            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-                writel((0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
-                    (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
-                     ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT),
-                     &ddrcReg_PHY_ADDR_CTL_REGP->ssCfg);
-                writel(readl(&ddrcReg_PHY_ADDR_CTL_REGP->ssCtl) |
-                    ddrcReg_PHY_ADDR_SS_CTRL_ENABLE,
-                    &ddrcReg_PHY_ADDR_CTL_REGP->ssCtl);
-        }
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable Spread Spectrum
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_disableSpreadSpectrum(void)
-{
-        ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Chip Product ID
-*
-*  This function returns Chip Product ID
-*
-*  @return  Chip Product ID
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipProductId(void)
-{
-        return (readl(&pChipcHw->
-                 ChipId) & chipcHw_REG_CHIPID_BASE_MASK) >>
-                chipcHw_REG_CHIPID_BASE_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get revision number
-*
-*  This function returns revision number of the chip
-*
-*  @return  Revision number
-*/
-/****************************************************************************/
-static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
-{
-        return readl(&pChipcHw->ChipId) & chipcHw_REG_CHIPID_REV_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables bus interface clock
-*
-*  Enables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX for mask
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockEnable(uint32_t mask)
-{
-        reg32_modify_or(&pChipcHw->BusIntfClock, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables bus interface clock
-*
-*  Disables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
-{
-        reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get status (enabled/disabled) of bus interface clock
-*
-*  This function returns the status of devices' bus interface clock
-*
-*  @return  Bus interface clock
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
-{
-        return readl(&pChipcHw->BusIntfClock);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables various audio channels
-*
-*  Enables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelEnable(uint32_t mask)
-{
-        reg32_modify_or(&pChipcHw->AudioEnable, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables various audio channels
-*
-*  Disables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelDisable(uint32_t mask)
-{
-        reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Soft resets devices
-*
-*  Soft resets various devices
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
-*/
-/****************************************************************************/
-static inline void chipcHw_softReset(uint64_t mask)
-{
-        chipcHw_softResetEnable(mask);
-        chipcHw_softResetDisable(mask);
-}
-
-static inline void chipcHw_softResetDisable(uint64_t mask)
-{
-        uint32_t ctrl1 = (uint32_t) mask;
-        uint32_t ctrl2 = (uint32_t) (mask >> 32);
-
-        /* Deassert module soft reset */
-        REG_LOCAL_IRQ_SAVE;
-        writel(readl(&pChipcHw->SoftReset1) ^ ctrl1, &pChipcHw->SoftReset1);
-        writel(readl(&pChipcHw->SoftReset2) ^ (ctrl2 &
-                (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void chipcHw_softResetEnable(uint64_t mask)
-{
-        uint32_t ctrl1 = (uint32_t) mask;
-        uint32_t ctrl2 = (uint32_t) (mask >> 32);
-        uint32_t unhold = 0;
-
-        REG_LOCAL_IRQ_SAVE;
-        writel(readl(&pChipcHw->SoftReset1) | ctrl1, &pChipcHw->SoftReset1);
-        /* Mask out unhold request bits */
-        writel(readl(&pChipcHw->SoftReset2) | (ctrl2 &
-                (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
-
-        /* Process unhold requests */
-        if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
-                unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD;
-        }
-
-        if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) {
-                unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD;
-        }
-
-        if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) {
-                unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD;
-        }
-
-        if (unhold) {
-                /* Make sure unhold request is effective */
-                writel(readl(&pChipcHw->SoftReset1) & ~unhold, &pChipcHw->SoftReset1);
-        }
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Configures misc CHIP functionality
-*
-*  Configures CHIP functionality
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_miscControl(uint32_t mask)
-{
-        reg32_write(&pChipcHw->MiscCtrl, mask);
-}
-
-static inline void chipcHw_miscControlDisable(uint32_t mask)
-{
-        reg32_modify_and(&pChipcHw->MiscCtrl, ~mask);
-}
-
-static inline void chipcHw_miscControlEnable(uint32_t mask)
-{
-        reg32_modify_or(&pChipcHw->MiscCtrl, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set OTP options
-*
-*  Set OTP options
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_OTP_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setOTPOption(uint64_t mask)
-{
-        uint32_t ctrl1 = (uint32_t) mask;
-        uint32_t ctrl2 = (uint32_t) (mask >> 32);
-
-        reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1);
-        reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Get sticky bits
-*
-*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getStickyBits(void)
-{
-        return readl(&pChipcHw->Sticky);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setStickyBits(uint32_t mask)
-{
-        uint32_t bits = 0;
-
-        REG_LOCAL_IRQ_SAVE;
-        if (mask & chipcHw_REG_STICKY_POR_BROM) {
-                bits |= chipcHw_REG_STICKY_POR_BROM;
-        } else {
-                uint32_t sticky;
-                sticky = readl(pChipcHw->Sticky);
-
-                if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
-                    && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
-                        bits |= chipcHw_REG_STICKY_BOOT_DONE;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_1)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_1;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_2)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_2;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_3)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_3;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_4)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_4;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_5)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_5;
-                }
-        }
-        writel(bits, pChipcHw->Sticky);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Clear sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_clearStickyBits(uint32_t mask)
-{
-        uint32_t bits = 0;
-
-        REG_LOCAL_IRQ_SAVE;
-        if (mask &
-            (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
-             chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
-             chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
-                uint32_t sticky = readl(&pChipcHw->Sticky);
-
-                if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
-                    && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
-                        bits = chipcHw_REG_STICKY_BOOT_DONE;
-                        mask &= ~chipcHw_REG_STICKY_BOOT_DONE;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_1)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_1)) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_1;
-                        mask &= ~chipcHw_REG_STICKY_GENERAL_1;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_2)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_2)) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_2;
-                        mask &= ~chipcHw_REG_STICKY_GENERAL_2;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_3)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_3)) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_3;
-                        mask &= ~chipcHw_REG_STICKY_GENERAL_3;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_4)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_4)) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_4;
-                        mask &= ~chipcHw_REG_STICKY_GENERAL_4;
-                }
-                if ((mask & chipcHw_REG_STICKY_GENERAL_5)
-                    && (sticky & chipcHw_REG_STICKY_GENERAL_5)) {
-                        bits |= chipcHw_REG_STICKY_GENERAL_5;
-                        mask &= ~chipcHw_REG_STICKY_GENERAL_5;
-                }
-        }
-        writel(bits | mask, &pChipcHw->Sticky);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Get software strap value
-*
-*  Retrieves software strap value
-*
-*  @return   Software strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getSoftStraps(void)
-{
-        return readl(&pChipcHw->SoftStraps);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set software override strap options
-*
-*  set software override strap options
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
-{
-        reg32_write(&pChipcHw->SoftStraps, strapOptions);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Pin Strap Options
-*
-*  This function returns the raw boot strap options
-*
-*  @return  strap options
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getPinStraps(void)
-{
-        return readl(&pChipcHw->PinStraps);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Valid Strap Options
-*
-*  This function returns the valid raw boot strap options
-*
-*  @return  strap options
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getValidStraps(void)
-{
-        uint32_t softStraps;
-
-        /*
-         ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps
-         ** which copies HW straps to soft straps if there is no override
-         */
-        softStraps = chipcHw_getSoftStraps();
-
-        return softStraps;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Initialize valid pin strap options
-*
-*  Retrieves valid pin strap options by copying HW strap options to soft register
-*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_initValidStraps(void)
-{
-        uint32_t softStraps;
-
-        REG_LOCAL_IRQ_SAVE;
-        softStraps = chipcHw_getSoftStraps();
-
-        if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) {
-                /* Copy HW straps to software straps */
-                chipcHw_setSoftStraps(chipcHw_getPinStraps());
-        }
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get boot device
-*
-*  This function returns the device type used in booting the system
-*
-*  @return  Boot device of type chipcHw_BOOT_DEVICE
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void)
-{
-        return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get boot mode
-*
-*  This function returns the way the system was booted
-*
-*  @return  Boot mode of type chipcHw_BOOT_MODE
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void)
-{
-        return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash page size
-*
-*  This function returns the NAND device page size
-*
-*  @return  Boot NAND device page size
-*
-*/
-/****************************************************************************/
-static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void)
-{
-        return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash address cycle configuration
-*
-*  This function returns the NAND flash address cycle configuration
-*
-*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
-*
-*/
-/****************************************************************************/
-static inline int chipcHw_getNandExtraCycle(void)
-{
-        if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) {
-                return 1;
-        } else {
-                return 0;
-        }
-}
-
-/****************************************************************************/
-/**
-*  @brief   Activates PIF interface
-*
-*  This function activates PIF interface by taking control of LCD pins
-*
-*  @note
-*       When activated, LCD pins will be defined as follows for PIF operation
-*
-*       CLD[17:0]  = pif_data[17:0]
-*       CLD[23:18] = pif_address[5:0]
-*       CLPOWER    = pif_wr_str
-*       CLCP       = pif_rd_str
-*       CLAC       = pif_hat1
-*       CLFP       = pif_hrdy1
-*       CLLP       = pif_hat2
-*       GPIO[42]   = pif_hrdy2
-*
-*       In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_activatePifInterface(void)
-{
-        reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Activates LCD interface
-*
-*  This function activates LCD interface
-*
-*  @note
-*       When activated, LCD pins will be defined as follows
-*
-*       CLD[17:0]  = LCD data
-*       CLD[23:18] = LCD data
-*       CLPOWER    = LCD power
-*       CLCP       =
-*       CLAC       = LCD ack
-*       CLFP       =
-*       CLLP       =
-*/
-/****************************************************************************/
-static inline void chipcHw_activateLcdInterface(void)
-{
-        reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Deactivates PIF/LCD interface
-*
-*  This function deactivates PIF/LCD interface
-*
-*  @note
-*       When deactivated LCD pins will be in rti-stated
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_deactivatePifLcdInterface(void)
-{
-        reg32_write(&pChipcHw->LcdPifMode, 0);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Select GE2
-*
-*  This function select GE2 as the graphic engine
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_selectGE2(void)
-{
-        reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Select GE3
-*
-*  This function select GE3 as the graphic engine
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_selectGE3(void)
-{
-        reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get to know the configuration of GPIO pin
-*
-*/
-/****************************************************************************/
-static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
-{
-        return (readl(chipcHw_REG_GPIO_MUX(pin))) &
-                (chipcHw_REG_GPIO_MUX_MASK <<
-                 chipcHw_REG_GPIO_MUX_POSITION(pin)) >>
-            chipcHw_REG_GPIO_MUX_POSITION(pin);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configure GPIO pin function
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setGpioPinFunction(int pin,
-                                              chipcHw_GPIO_FUNCTION_e func)
-{
-        REG_LOCAL_IRQ_SAVE;
-        *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &=
-            ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin));
-        *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |=
-            func << chipcHw_REG_GPIO_MUX_POSITION(pin);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin slew rate
-*
-*  This function sets the slew of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinSlewRate(uint32_t pin,
-                                          chipcHw_PIN_SLEW_RATE_e slewRate)
-{
-        REG_LOCAL_IRQ_SAVE;
-        *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &=
-            ~(chipcHw_REG_SLEW_RATE_MASK <<
-              chipcHw_REG_SLEW_RATE_POSITION(pin));
-        *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |=
-            (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin output drive current
-*
-*  This function sets output drive current of individual pin
-*
-*  Note: Avoid the use of the word 'current' since linux headers define this
-*        to be the current task.
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinOutputCurrent(uint32_t pin,
-                                               chipcHw_PIN_CURRENT_STRENGTH_e
-                                               curr)
-{
-        REG_LOCAL_IRQ_SAVE;
-        *((uint32_t *) chipcHw_REG_CURRENT(pin)) &=
-            ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin));
-        *((uint32_t *) chipcHw_REG_CURRENT(pin)) |=
-            (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin pullup register
-*
-*  This function sets pullup register of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinPullup(uint32_t pin, chipcHw_PIN_PULL_e pullup)
-{
-        REG_LOCAL_IRQ_SAVE;
-        *((uint32_t *) chipcHw_REG_PULLUP(pin)) &=
-            ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin));
-        *((uint32_t *) chipcHw_REG_PULLUP(pin)) |=
-            (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin input type
-*
-*  This function sets input type of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinInputType(uint32_t pin,
-                                           chipcHw_PIN_INPUTTYPE_e inputType)
-{
-        REG_LOCAL_IRQ_SAVE;
-        *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &=
-            ~(chipcHw_REG_INPUTTYPE_MASK <<
-              chipcHw_REG_INPUTTYPE_POSITION(pin));
-        *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |=
-            (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Power up the USB PHY
-*
-*  This function powers up the USB PHY
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_powerUpUsbPhy(void)
-{
-        reg32_modify_and(&pChipcHw->MiscCtrl,
-                         chipcHw_REG_MISC_CTRL_USB_POWERON);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Power down the USB PHY
-*
-*  This function powers down the USB PHY
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_powerDownUsbPhy(void)
-{
-        reg32_modify_or(&pChipcHw->MiscCtrl,
-                        chipcHw_REG_MISC_CTRL_USB_POWEROFF);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set the 2nd USB as host
-*
-*  This function sets the 2nd USB as host
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setUsbHost(void)
-{
-        reg32_modify_or(&pChipcHw->MiscCtrl,
-                        chipcHw_REG_MISC_CTRL_USB_MODE_HOST);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set the 2nd USB as device
-*
-*  This function sets the 2nd USB as device
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setUsbDevice(void)
-{
-        reg32_modify_and(&pChipcHw->MiscCtrl,
-                         chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Lower layer function to enable/disable a clock of a certain device
-*
-*  This function enables/disables a core clock
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
-                                    chipcHw_OPTYPE_e type, int mode)
-{
-        uint32_t __iomem *pPLLReg = NULL;
-        uint32_t __iomem *pClockCtrl = NULL;
-
-        switch (clock) {
-        case chipcHw_CLOCK_DDR:
-                pPLLReg = &pChipcHw->DDRClock;
-                break;
-        case chipcHw_CLOCK_ARM:
-                pPLLReg = &pChipcHw->ARMClock;
-                break;
-        case chipcHw_CLOCK_ESW:
-                pPLLReg = &pChipcHw->ESWClock;
-                break;
-        case chipcHw_CLOCK_VPM:
-                pPLLReg = &pChipcHw->VPMClock;
-                break;
-        case chipcHw_CLOCK_ESW125:
-                pPLLReg = &pChipcHw->ESW125Clock;
-                break;
-        case chipcHw_CLOCK_UART:
-                pPLLReg = &pChipcHw->UARTClock;
-                break;
-        case chipcHw_CLOCK_SDIO0:
-                pPLLReg = &pChipcHw->SDIO0Clock;
-                break;
-        case chipcHw_CLOCK_SDIO1:
-                pPLLReg = &pChipcHw->SDIO1Clock;
-                break;
-        case chipcHw_CLOCK_SPI:
-                pPLLReg = &pChipcHw->SPIClock;
-                break;
-        case chipcHw_CLOCK_ETM:
-                pPLLReg = &pChipcHw->ETMClock;
-                break;
-        case chipcHw_CLOCK_USB:
-                pPLLReg = &pChipcHw->USBClock;
-                if (type == chipcHw_OPTYPE_OUTPUT) {
-                        if (mode) {
-                                reg32_modify_and(pPLLReg,
-                                                 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-                        } else {
-                                reg32_modify_or(pPLLReg,
-                                                chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-                        }
-                }
-                break;
-        case chipcHw_CLOCK_LCD:
-                pPLLReg = &pChipcHw->LCDClock;
-                if (type == chipcHw_OPTYPE_OUTPUT) {
-                        if (mode) {
-                                reg32_modify_and(pPLLReg,
-                                                 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-                        } else {
-                                reg32_modify_or(pPLLReg,
-                                                chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-                        }
-                }
-                break;
-        case chipcHw_CLOCK_APM:
-                pPLLReg = &pChipcHw->APMClock;
-                if (type == chipcHw_OPTYPE_OUTPUT) {
-                        if (mode) {
-                                reg32_modify_and(pPLLReg,
-                                                 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-                        } else {
-                                reg32_modify_or(pPLLReg,
-                                                chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-                        }
-                }
-                break;
-        case chipcHw_CLOCK_BUS:
-                pClockCtrl = &pChipcHw->ACLKClock;
-                break;
-        case chipcHw_CLOCK_OTP:
-                pClockCtrl = &pChipcHw->OTPClock;
-                break;
-        case chipcHw_CLOCK_I2C:
-                pClockCtrl = &pChipcHw->I2CClock;
-                break;
-        case chipcHw_CLOCK_I2S0:
-                pClockCtrl = &pChipcHw->I2S0Clock;
-                break;
-        case chipcHw_CLOCK_RTBUS:
-                pClockCtrl = &pChipcHw->RTBUSClock;
-                break;
-        case chipcHw_CLOCK_APM100:
-                pClockCtrl = &pChipcHw->APM100Clock;
-                break;
-        case chipcHw_CLOCK_TSC:
-                pClockCtrl = &pChipcHw->TSCClock;
-                break;
-        case chipcHw_CLOCK_LED:
-                pClockCtrl = &pChipcHw->LEDClock;
-                break;
-        case chipcHw_CLOCK_I2S1:
-                pClockCtrl = &pChipcHw->I2S1Clock;
-                break;
-        }
-
-        if (pPLLReg) {
-                switch (type) {
-                case chipcHw_OPTYPE_OUTPUT:
-                        /* PLL clock output enable/disable */
-                        if (mode) {
-                                if (clock == chipcHw_CLOCK_DDR) {
-                                        /* DDR clock enable is inverted */
-                                        reg32_modify_and(pPLLReg,
-                                                         ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-                                } else {
-                                        reg32_modify_or(pPLLReg,
-                                                        chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-                                }
-                        } else {
-                                if (clock == chipcHw_CLOCK_DDR) {
-                                        /* DDR clock disable is inverted */
-                                        reg32_modify_or(pPLLReg,
-                                                        chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-                                } else {
-                                        reg32_modify_and(pPLLReg,
-                                                         ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-                                }
-                        }
-                        break;
-                case chipcHw_OPTYPE_BYPASS:
-                        /* PLL clock bypass enable/disable */
-                        if (mode) {
-                                reg32_modify_or(pPLLReg,
-                                                chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-                        } else {
-                                reg32_modify_and(pPLLReg,
-                                                 ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-                        }
-                        break;
-                }
-        } else if (pClockCtrl) {
-                switch (type) {
-                case chipcHw_OPTYPE_OUTPUT:
-                        if (mode) {
-                                reg32_modify_or(pClockCtrl,
-                                                chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
-                        } else {
-                                reg32_modify_and(pClockCtrl,
-                                                 ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
-                        }
-                        break;
-                case chipcHw_OPTYPE_BYPASS:
-                        if (mode) {
-                                reg32_modify_or(pClockCtrl,
-                                                chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-                        } else {
-                                reg32_modify_and(pClockCtrl,
-                                                 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-                        }
-                        break;
-                }
-        }
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables a core clock of a certain device
-*
-*  This function disables a core clock
-*
-*  @note    no change in power consumption
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock)
-{
-
-        /* Disable output of the clock */
-        chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable a core clock of a certain device
-*
-*  This function enables a core clock
-*
-*  @note    no change in power consumption
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock)
-{
-
-        /* Enable output of the clock */
-        chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables bypass clock of a certain device
-*
-*  This function enables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock)
-{
-        /* Enable bypass clock */
-        chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disabled bypass clock of a certain device
-*
-*  This function disables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
-{
-        /* Disable bypass clock */
-        chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0);
-
-}
-
-/****************************************************************************/
-/**  @brief Checks if software strap is enabled
- *
- *   @return 1 : When enable
- *           0 : When disable
- */
-/****************************************************************************/
-static inline int chipcHw_isSoftwareStrapsEnable(void)
-{
-        return readl(&pChipcHw->SoftStraps) & 0x00000001;
-}
-
-/****************************************************************************/
-/**  @brief Enable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsEnable(void)
-{
-        reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001);
-}
-
-/****************************************************************************/
-/**  @brief Disable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsDisable(void)
-{
-        reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001));
-}
-
-/****************************************************************************/
-/**  @brief PLL test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestEnable(void)
-{
-        reg32_modify_or(&pChipcHw->PLLConfig,
-                        chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestEnable(void)
-{
-        reg32_modify_or(&pChipcHw->PLLConfig2,
-                        chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestDisable(void)
-{
-        reg32_modify_and(&pChipcHw->PLLConfig,
-                         ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestDisable(void)
-{
-        reg32_modify_and(&pChipcHw->PLLConfig2,
-                         ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief Get PLL test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPllTestEnable(void)
-{
-        return readl(&pChipcHw->PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
-}
-
-/****************************************************************************/
-/**  @brief Get PLL2 test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPll2TestEnable(void)
-{
-        return readl(&pChipcHw->PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
-}
-
-/****************************************************************************/
-/**  @brief PLL test select
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestSelect(uint32_t val)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
-        pChipcHw->PLLConfig |=
-            (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test select
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestSelect(uint32_t val)
-{
-
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
-        pChipcHw->PLLConfig2 |=
-            (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**  @brief Get PLL test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPllTestSelected(void)
-{
-        return (uint8_t) ((readl(&pChipcHw->
-                           PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
-                          >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
-}
-
-/****************************************************************************/
-/**  @brief Get PLL2 test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPll2TestSelected(void)
-{
-        return (uint8_t) ((readl(&pChipcHw->
-                           PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
-                          >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
-}
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL1
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll1Disable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        writel(readl(&pChipcHw->PLLConfig) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
-                &pChipcHw->PLLConfig);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL2
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll2Disable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        writel(readl(&pChipcHw->PLLConfig2) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
-                &pChipcHw->PLLConfig2);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
-                &pChipcHw->Spare1);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
-                &pChipcHw->Spare1);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM SW phase alignment interrupt mode
-*
-*  This function sets VPM phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void
-chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode)
-{
-        REG_LOCAL_IRQ_SAVE;
-        if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) {
-                pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
-        } else {
-                pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
-        }
-        pChipcHw->VPMPhaseCtrl2 =
-            (pChipcHw->
-             VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK <<
-                               chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignEnable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignDisable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignEnable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignDisable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignEnable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        writel(readl(&pChipcHw->VPMPhaseCtrl1) | chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE,
-                        &pChipcHw->VPMPhaseCtrl1);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignDisable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignEnable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignDisable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        writel(readl(&pChipcHw->VPMPhaseCtrl1) & ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE,
-                &pChipcHw->VPMPhaseCtrl1);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set DDR phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin)
-{
-        uint32_t ge = 0;
-        uint32_t le = 0;
-
-        switch (margin) {
-        case chipcHw_DDR_HW_PHASE_MARGIN_STRICT:
-                ge = 0x0F;
-                le = 0x0F;
-                break;
-        case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM:
-                ge = 0x03;
-                le = 0x3F;
-                break;
-        case chipcHw_DDR_HW_PHASE_MARGIN_WIDE:
-                ge = 0x01;
-                le = 0x7F;
-                break;
-        }
-
-        {
-                REG_LOCAL_IRQ_SAVE;
-
-                pChipcHw->DDRPhaseCtrl1 &=
-                    ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK <<
-                       chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
-                      || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK <<
-                          chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
-
-                pChipcHw->DDRPhaseCtrl1 |=
-                    ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
-                     || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
-
-                REG_LOCAL_IRQ_RESTORE;
-        }
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
-{
-        uint32_t ge = 0;
-        uint32_t le = 0;
-
-        switch (margin) {
-        case chipcHw_VPM_HW_PHASE_MARGIN_STRICT:
-                ge = 0x0F;
-                le = 0x0F;
-                break;
-        case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM:
-                ge = 0x03;
-                le = 0x3F;
-                break;
-        case chipcHw_VPM_HW_PHASE_MARGIN_WIDE:
-                ge = 0x01;
-                le = 0x7F;
-                break;
-        }
-
-        {
-                REG_LOCAL_IRQ_SAVE;
-
-                pChipcHw->VPMPhaseCtrl1 &=
-                    ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK <<
-                       chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
-                      || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK <<
-                          chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
-
-                pChipcHw->VPMPhaseCtrl1 |=
-                    ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
-                     || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
-
-                REG_LOCAL_IRQ_RESTORE;
-        }
-}
-
-/****************************************************************************/
-/**
-*  @brief   Checks DDR phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
-{
-        return (readl(&pChipcHw->
-                PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Checks VPM phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
-{
-        return (readl(&pChipcHw->
-                PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
-{
-        return (readl(&pChipcHw->
-                PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
-            chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
-{
-        return (readl(&pChipcHw->
-                PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
-            chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrPhaseControl(void)
-{
-        return (readl(&pChipcHw->
-                PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
-            chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmPhaseControl(void)
-{
-        return (readl(&pChipcHw->
-                PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
-            chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a DDR phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->DDRPhaseCtrl2 &=
-            ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK <<
-              chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT);
-        pChipcHw->DDRPhaseCtrl2 |=
-            (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) <<
-            chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a VPM phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->VPMPhaseCtrl2 &=
-            ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK <<
-              chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT);
-        pChipcHw->VPMPhaseCtrl2 |=
-            (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) <<
-            chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clear DDR phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        /* Clear timeout interrupt service bit */
-        pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED;
-        pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clear VPM phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        /* Clear timeout interrupt service bit */
-        pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED;
-        pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
-        /* Enable timeout interrupt */
-        pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
-        /* Enable timeout interrupt */
-        pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void)
-{
-        REG_LOCAL_IRQ_SAVE;
-        pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-#endif /* CHIPC_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
deleted file mode 100644
index 26f5d0e4e1dd..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
+++ /dev/null
@@ -1,530 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw_reg.h
-*
-*  @brief   Definitions for low level chip control registers
-*
-*/
-/****************************************************************************/
-#ifndef CHIPCHW_REG_H
-#define CHIPCHW_REG_H
-
-#include <mach/csp/mm_io.h>
-#include <mach/csp/reg.h>
-#include <mach/csp/ddrcReg.h>
-
-#define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
-
-typedef struct {
-        uint32_t ChipId;        /* Chip ID */
-        uint32_t DDRClock;      /* PLL1 Channel 1 for DDR clock */
-        uint32_t ARMClock;      /* PLL1 Channel 2 for ARM clock */
-        uint32_t ESWClock;      /* PLL1 Channel 3 for ESW system clock */
-        uint32_t VPMClock;      /* PLL1 Channel 4 for VPM clock */
-        uint32_t ESW125Clock;   /* PLL1 Channel 5 for ESW 125MHz clock */
-        uint32_t UARTClock;     /* PLL1 Channel 6 for UART clock */
-        uint32_t SDIO0Clock;    /* PLL1 Channel 7 for SDIO 0 clock */
-        uint32_t SDIO1Clock;    /* PLL1 Channel 8 for SDIO 1 clock */
-        uint32_t SPIClock;      /* PLL1 Channel 9 for SPI master Clock  */
-        uint32_t ETMClock;      /* PLL1 Channel 10 for ARM ETM Clock  */
-
-        uint32_t ACLKClock;     /* ACLK Clock (Divider) */
-        uint32_t OTPClock;      /* OTP Clock  (Divider) */
-        uint32_t I2CClock;      /* I2C Clock (CK_13m) (Divider) */
-        uint32_t I2S0Clock;     /* I2S0 Clock (Divider) */
-        uint32_t RTBUSClock;    /* RTBUS (DDR PHY Config.) Clock (Divider) */
-        uint32_t pad1;
-        uint32_t APM100Clock;   /* APM 100MHz CLK Clock (Divider) */
-        uint32_t TSCClock;      /* TSC Clock (Divider) */
-        uint32_t LEDClock;      /* LED Clock (Divider) */
-
-        uint32_t USBClock;      /* PLL2 Channel 1 for USB clock */
-        uint32_t LCDClock;      /* PLL2 Channel 2 for LCD clock */
-        uint32_t APMClock;      /* PLL2 Channel 3 for APM 200 MHz clock */
-
-        uint32_t BusIntfClock;  /* Bus interface clock */
-
-        uint32_t PLLStatus;     /* PLL status register (PLL1) */
-        uint32_t PLLConfig;     /* PLL configuration register  (PLL1) */
-        uint32_t PLLPreDivider; /* PLL pre-divider control register (PLL1) */
-        uint32_t PLLDivider;    /* PLL divider control register (PLL1) */
-        uint32_t PLLControl1;   /* PLL analog control register #1 (PLL1) */
-        uint32_t PLLControl2;   /* PLL analog control register #2 (PLL1) */
-
-        uint32_t I2S1Clock;     /* I2S1 Clock  */
-        uint32_t AudioEnable;   /* Enable/ disable audio channel */
-        uint32_t SoftReset1;    /* Reset blocks */
-        uint32_t SoftReset2;    /* Reset blocks */
-        uint32_t Spare1;        /* Phase align interrupts */
-        uint32_t Sticky;        /* Sticky bits */
-        uint32_t MiscCtrl;      /* Misc. control */
-        uint32_t pad3[3];
-
-        uint32_t PLLStatus2;    /* PLL status register (PLL2) */
-        uint32_t PLLConfig2;    /* PLL configuration register  (PLL2) */
-        uint32_t PLLPreDivider2;        /* PLL pre-divider control register (PLL2) */
-        uint32_t PLLDivider2;   /* PLL divider control register (PLL2) */
-        uint32_t PLLControl12;  /* PLL analog control register #1 (PLL2) */
-        uint32_t PLLControl22;  /* PLL analog control register #2 (PLL2) */
-
-        uint32_t DDRPhaseCtrl1; /* DDR Clock Phase Alignment control1 */
-        uint32_t VPMPhaseCtrl1; /* VPM Clock Phase Alignment control1 */
-        uint32_t PhaseAlignStatus;      /* DDR/VPM Clock Phase Alignment Status */
-        uint32_t PhaseCtrlStatus;       /* DDR/VPM Clock HW DDR/VPM ph_ctrl and load_ch Status */
-        uint32_t DDRPhaseCtrl2; /* DDR Clock Phase Alignment control2 */
-        uint32_t VPMPhaseCtrl2; /* VPM Clock Phase Alignment control2 */
-        uint32_t pad4[9];
-
-        uint32_t SoftOTP1;      /* Software OTP control */
-        uint32_t SoftOTP2;      /* Software OTP control */
-        uint32_t SoftStraps;    /* Software strap */
-        uint32_t PinStraps;     /* Pin Straps */
-        uint32_t DiffOscCtrl;   /* Diff oscillator control */
-        uint32_t DiagsCtrl;     /* Diagnostic control */
-        uint32_t DiagsOutputCtrl;       /* Diagnostic output enable */
-        uint32_t DiagsReadBackCtrl;     /* Diagnostic read back control */
-
-        uint32_t LcdPifMode;    /* LCD/PIF Pin Sharing MUX Mode */
-
-        uint32_t GpioMux_0_7;   /* Pin Sharing MUX0 Control */
-        uint32_t GpioMux_8_15;  /* Pin Sharing MUX1 Control */
-        uint32_t GpioMux_16_23; /* Pin Sharing MUX2 Control */
-        uint32_t GpioMux_24_31; /* Pin Sharing MUX3 Control */
-        uint32_t GpioMux_32_39; /* Pin Sharing MUX4 Control */
-        uint32_t GpioMux_40_47; /* Pin Sharing MUX5 Control */
-        uint32_t GpioMux_48_55; /* Pin Sharing MUX6 Control */
-        uint32_t GpioMux_56_63; /* Pin Sharing MUX7 Control */
-
-        uint32_t GpioSR_0_7;    /* Slew rate for GPIO 0 - 7 */
-        uint32_t GpioSR_8_15;   /* Slew rate for GPIO 8 - 15 */
-        uint32_t GpioSR_16_23;  /* Slew rate for GPIO 16 - 23 */
-        uint32_t GpioSR_24_31;  /* Slew rate for GPIO 24 - 31 */
-        uint32_t GpioSR_32_39;  /* Slew rate for GPIO 32 - 39 */
-        uint32_t GpioSR_40_47;  /* Slew rate for GPIO 40 - 47 */
-        uint32_t GpioSR_48_55;  /* Slew rate for GPIO 48 - 55 */
-        uint32_t GpioSR_56_63;  /* Slew rate for GPIO 56 - 63 */
-        uint32_t MiscSR_0_7;    /* Slew rate for MISC 0 - 7 */
-        uint32_t MiscSR_8_15;   /* Slew rate for MISC 8 - 15 */
-
-        uint32_t GpioPull_0_15; /* Pull up registers for GPIO 0 - 15 */
-        uint32_t GpioPull_16_31;        /* Pull up registers for GPIO 16 - 31 */
-        uint32_t GpioPull_32_47;        /* Pull up registers for GPIO 32 - 47 */
-        uint32_t GpioPull_48_63;        /* Pull up registers for GPIO 48 - 63 */
-        uint32_t MiscPull_0_15; /* Pull up registers for MISC 0 - 15 */
-
-        uint32_t GpioInput_0_31;        /* Input type for GPIO 0 - 31 */
-        uint32_t GpioInput_32_63;       /* Input type for GPIO 32 - 63 */
-        uint32_t MiscInput_0_15;        /* Input type for MISC 0 - 16 */
-} chipcHw_REG_t;
-
-#define pChipcHw  ((chipcHw_REG_t __iomem *) chipcHw_BASE_ADDRESS)
-#define pChipcPhysical  (MM_ADDR_IO_CHIPC)
-
-#define chipcHw_REG_CHIPID_BASE_MASK                    0xFFFFF000
-#define chipcHw_REG_CHIPID_BASE_SHIFT                   12
-#define chipcHw_REG_CHIPID_REV_MASK                     0x00000FFF
-#define chipcHw_REG_REV_A0                              0xA00
-#define chipcHw_REG_REV_B0                              0x0B0
-
-#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE           0x80000000      /* Allow controlling PLL registers */
-#define chipcHw_REG_PLL_STATUS_LOCKED                   0x00000001      /* PLL is settled */
-#define chipcHw_REG_PLL_CONFIG_D_RESET                  0x00000008      /* Digital reset */
-#define chipcHw_REG_PLL_CONFIG_A_RESET                  0x00000004      /* Analog reset */
-#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE            0x00000020      /* Bypass enable */
-#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE            0x00000010      /* Output enable */
-#define chipcHw_REG_PLL_CONFIG_POWER_DOWN               0x00000001      /* Power down */
-#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ           1600000000      /* 1.6GHz VCO split frequency */
-#define chipcHw_REG_PLL_CONFIG_VCO_800_1600             0x00000000      /* VCO range 800-1600 MHz */
-#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200            0x00000080      /* VCO range 1601-3200 MHz */
-#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE              0x00010000      /* PLL test output enable */
-#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK         0x003E0000      /* Mask to set test values */
-#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT        17
-
-#define chipcHw_REG_PLL_CLOCK_PHASE_COMP                0x00800000      /* Phase comparator output */
-#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK         0x00300000      /* Clock to bus ratio mask */
-#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT        20      /* Number of bits to be shifted */
-#define chipcHw_REG_PLL_CLOCK_POWER_DOWN                0x00080000      /* PLL channel power down */
-#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO               0x00040000      /* Use GPIO as source */
-#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT             0x00020000      /* Select bypass clock */
-#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE             0x00010000      /* Clock gated ON */
-#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE       0x00008000      /* Clock phase update enable */
-#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT       8       /* Number of bits to be shifted */
-#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK        0x00003F00      /* Phase control mask */
-#define chipcHw_REG_PLL_CLOCK_MDIV_MASK                 0x000000FF      /* Clock post divider mask
-
-                                                                           00000000 = divide-by-256
-                                                                           00000001 = divide-by-1
-                                                                           00000010 = divide-by-2
-                                                                           00000011 = divide-by-3
-                                                                           00000100 = divide-by-4
-                                                                           00000101 = divide-by-5
-                                                                           00000110 = divide-by-6
-                                                                           .
-                                                                           .
-                                                                           11111011 = divide-by-251
-                                                                           11111100 = divide-by-252
-                                                                           11111101 = divide-by-253
-                                                                           11111110 = divide-by-254
-                                                                         */
-
-#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER              0x00040000      /* NON-PLL clock source select */
-#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT             0x00020000      /* NON-PLL clock bypass enable */
-#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE             0x00010000      /* NON-PLL clock output enable */
-#define chipcHw_REG_DIV_CLOCK_DIV_MASK                  0x000000FF      /* NON-PLL clock post-divide mask */
-#define chipcHw_REG_DIV_CLOCK_DIV_256                   0x00000000      /* NON-PLL clock post-divide by 256 */
-
-#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT             0
-#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT             4
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT           8
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK            0x0001FF00
-#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN           0x02000000
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK       0x00700000      /* Divider mask */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER    0x00000000      /* Integer-N Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT  0x00100000      /* MASH Sigma-Delta Modulator Unit Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT   0x00200000      /* MFB Sigma-Delta Modulator Unit Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8   0x00300000      /* MASH Sigma-Delta Modulator 1/8 Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8    0x00400000      /* MFB Sigma-Delta Modulator 1/8 Mode */
-
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco)          ((vco) / chipcHw_XTAL_FREQ_Hz)
-#define chipcHw_REG_PLL_PREDIVIDER_P1                   1
-#define chipcHw_REG_PLL_PREDIVIDER_P2                   1
-
-#define chipcHw_REG_PLL_DIVIDER_M1DIV                   0x03000000
-#define chipcHw_REG_PLL_DIVIDER_FRAC                    0x00FFFFFF      /* Fractional divider */
-
-#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS               (0x00FFFFFF)    /* To attain spread with max frequency */
-
-#define chipcHw_REG_PLL_DIVIDER_NDIV_f                  0       /* ndiv_frac = chipcHw_REG_PLL_DIVIDER_NDIV_f /
-                                                                   chipcHw_REG_PLL_DIVIDER_FRAC
-                                                                   = 0, when SS is disable
-                                                                 */
-
-#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz)           ((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz)))
-
-#define chipcHw_REG_ACLKClock_CLK_DIV_MASK              0x3
-
-/* System booting strap options */
-#define chipcHw_STRAPS_SOFT_OVERRIDE                    0x00000001      /* Software Strap Override */
-
-#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8         0x00000000      /* 8 bit NAND FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16         0x00000002      /* 16 bit NOR FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH         0x00000004      /* Serial FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16        0x00000006      /* 16 bit NAND FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_UART                 0x00000008      /* UART Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_MASK                 0x0000000E      /* Mask */
-
-/* System boot option */
-#define chipcHw_STRAPS_BOOT_OPTION_BROM                 0x00000000      /* Boot from Boot ROM */
-#define chipcHw_STRAPS_BOOT_OPTION_ARAM                 0x00000020      /* Boot from ARAM */
-#define chipcHw_STRAPS_BOOT_OPTION_NOR                  0x00000030      /* Boot from NOR flash */
-
-/* NAND Flash page size strap options */
-#define chipcHw_STRAPS_NAND_PAGESIZE_512                0x00000000      /* NAND FLASH page size of 512 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_2048               0x00000040      /* NAND FLASH page size of 2048 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_4096               0x00000080      /* NAND FLASH page size of 4096 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_EXT                0x000000C0      /* NAND FLASH page of extened size */
-#define chipcHw_STRAPS_NAND_PAGESIZE_MASK               0x000000C0      /* Mask */
-
-#define chipcHw_STRAPS_NAND_EXTRA_CYCLE                 0x00000400      /* NAND FLASH address cycle configuration */
-#define chipcHw_STRAPS_REBOOT_TO_UART                   0x00000800      /* Reboot to UART on error */
-
-/* Secure boot mode strap options */
-#define chipcHw_STRAPS_BOOT_MODE_NORMAL                 0x00000000      /* Normal Boot */
-#define chipcHw_STRAPS_BOOT_MODE_DBG_SW                 0x00000100      /* Software debugging Boot */
-#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT               0x00000200      /* Boot rom debugging Boot */
-#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET           0x00000300      /* Normal Boot (Quiet BootRom) */
-#define chipcHw_STRAPS_BOOT_MODE_MASK                   0x00000300      /* Mask */
-
-/* Slave Mode straps */
-#define chipcHw_STRAPS_I2CS                             0x02000000      /* I2C Slave  */
-#define chipcHw_STRAPS_SPIS                             0x01000000      /* SPI Slave  */
-
-/* Strap pin options */
-#define chipcHw_REG_SW_STRAPS                           ((pChipcHw->PinStraps & 0x0000FC00) >> 10)
-
-/* PIF/LCD pin sharing defines */
-#define chipcHw_REG_LCD_PIN_ENABLE                      0x00000001      /* LCD Controller is used and the pins have LCD functions */
-#define chipcHw_REG_PIF_PIN_ENABLE                      0x00000002      /* LCD pins are used to perform PIF functions  */
-
-#define chipcHw_GPIO_COUNT                              61      /* Number of GPIO pin accessible thorugh CHIPC */
-
-/* NOTE: Any changes to these constants will require a corresponding change to chipcHw_str.c */
-#define chipcHw_REG_GPIO_MUX_KEYPAD                     0x00000001      /* GPIO mux for Keypad */
-#define chipcHw_REG_GPIO_MUX_I2CH                       0x00000002      /* GPIO mux for I2CH */
-#define chipcHw_REG_GPIO_MUX_SPI                        0x00000003      /* GPIO mux for SPI */
-#define chipcHw_REG_GPIO_MUX_UART                       0x00000004      /* GPIO mux for UART */
-#define chipcHw_REG_GPIO_MUX_LEDMTXP                    0x00000005      /* GPIO mux for LEDMTXP */
-#define chipcHw_REG_GPIO_MUX_LEDMTXS                    0x00000006      /* GPIO mux for LEDMTXS */
-#define chipcHw_REG_GPIO_MUX_SDIO0                      0x00000007      /* GPIO mux for SDIO0 */
-#define chipcHw_REG_GPIO_MUX_SDIO1                      0x00000008      /* GPIO mux for SDIO1 */
-#define chipcHw_REG_GPIO_MUX_PCM                        0x00000009      /* GPIO mux for PCM */
-#define chipcHw_REG_GPIO_MUX_I2S                        0x0000000A      /* GPIO mux for I2S */
-#define chipcHw_REG_GPIO_MUX_ETM                        0x0000000B      /* GPIO mux for ETM */
-#define chipcHw_REG_GPIO_MUX_DEBUG                      0x0000000C      /* GPIO mux for DEBUG */
-#define chipcHw_REG_GPIO_MUX_MISC                       0x0000000D      /* GPIO mux for MISC */
-#define chipcHw_REG_GPIO_MUX_GPIO                       0x00000000      /* GPIO mux for GPIO */
-#define chipcHw_REG_GPIO_MUX(pin)                       (&pChipcHw->GpioMux_0_7 + ((pin) >> 3))
-#define chipcHw_REG_GPIO_MUX_POSITION(pin)              (((pin) & 0x00000007) << 2)
-#define chipcHw_REG_GPIO_MUX_MASK                       0x0000000F      /* Mask */
-
-#define chipcHw_REG_SLEW_RATE_HIGH                      0x00000000      /* High speed slew rate */
-#define chipcHw_REG_SLEW_RATE_NORMAL                    0x00000008      /* Normal slew rate */
-                                                        /* Pins beyond 42 are defined by skipping 8 bits within the register */
-#define chipcHw_REG_SLEW_RATE(pin)                      (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
-#define chipcHw_REG_SLEW_RATE_POSITION(pin)             (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
-#define chipcHw_REG_SLEW_RATE_MASK                      0x00000008      /* Mask */
-
-#define chipcHw_REG_CURRENT_STRENGTH_2mA                0x00000001      /* Current driving strength 2 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_4mA                0x00000002      /* Current driving strength 4 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_6mA                0x00000004      /* Current driving strength 6 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_8mA                0x00000005      /* Current driving strength 8 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_10mA               0x00000006      /* Current driving strength 10 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_12mA               0x00000007      /* Current driving strength 12 milli ampere */
-#define chipcHw_REG_CURRENT_MASK                        0x00000007      /* Mask */
-                                                        /* Pins beyond 42 are defined by skipping 8 bits */
-#define chipcHw_REG_CURRENT(pin)                        (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
-#define chipcHw_REG_CURRENT_POSITION(pin)               (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
-
-#define chipcHw_REG_PULL_NONE                           0x00000000      /* No pull up register */
-#define chipcHw_REG_PULL_UP                             0x00000001      /* Pull up register enable */
-#define chipcHw_REG_PULL_DOWN                           0x00000002      /* Pull down register enable */
-#define chipcHw_REG_PULLUP_MASK                         0x00000003      /* Mask */
-                                                        /* Pins beyond 42 are defined by skipping 4 bits */
-#define chipcHw_REG_PULLUP(pin)                         (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChipcHw->GpioPull_0_15 + ((pin) >> 4)))
-#define chipcHw_REG_PULLUP_POSITION(pin)                (((pin) > 42) ? ((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1))
-
-#define chipcHw_REG_INPUTTYPE_CMOS                      0x00000000      /* Normal CMOS logic */
-#define chipcHw_REG_INPUTTYPE_ST                        0x00000001      /* High speed Schmitt Trigger */
-#define chipcHw_REG_INPUTTYPE_MASK                      0x00000001      /* Mask */
-                                                        /* Pins beyond 42 are defined by skipping 2 bits */
-#define chipcHw_REG_INPUTTYPE(pin)                      (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&pChipcHw->GpioInput_0_31 + ((pin) >> 5)))
-#define chipcHw_REG_INPUTTYPE_POSITION(pin)             (((pin) > 42) ? ((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F)))
-
-/* Device connected to the bus clock */
-#define chipcHw_REG_BUS_CLOCK_ARM                       0x00000001      /* Bus interface clock for ARM */
-#define chipcHw_REG_BUS_CLOCK_VDEC                      0x00000002      /* Bus interface clock for VDEC */
-#define chipcHw_REG_BUS_CLOCK_ARAM                      0x00000004      /* Bus interface clock for ARAM */
-#define chipcHw_REG_BUS_CLOCK_HPM                       0x00000008      /* Bus interface clock for HPM */
-#define chipcHw_REG_BUS_CLOCK_DDRC                      0x00000010      /* Bus interface clock for DDRC */
-#define chipcHw_REG_BUS_CLOCK_DMAC0                     0x00000020      /* Bus interface clock for DMAC0 */
-#define chipcHw_REG_BUS_CLOCK_DMAC1                     0x00000040      /* Bus interface clock for DMAC1 */
-#define chipcHw_REG_BUS_CLOCK_NVI                       0x00000080      /* Bus interface clock for NVI */
-#define chipcHw_REG_BUS_CLOCK_ESW                       0x00000100      /* Bus interface clock for ESW */
-#define chipcHw_REG_BUS_CLOCK_GE                        0x00000200      /* Bus interface clock for GE */
-#define chipcHw_REG_BUS_CLOCK_I2CH                      0x00000400      /* Bus interface clock for I2CH */
-#define chipcHw_REG_BUS_CLOCK_I2S0                      0x00000800      /* Bus interface clock for I2S0 */
-#define chipcHw_REG_BUS_CLOCK_I2S1                      0x00001000      /* Bus interface clock for I2S1 */
-#define chipcHw_REG_BUS_CLOCK_VRAM                      0x00002000      /* Bus interface clock for VRAM */
-#define chipcHw_REG_BUS_CLOCK_CLCD                      0x00004000      /* Bus interface clock for CLCD */
-#define chipcHw_REG_BUS_CLOCK_LDK                       0x00008000      /* Bus interface clock for LDK */
-#define chipcHw_REG_BUS_CLOCK_LED                       0x00010000      /* Bus interface clock for LED */
-#define chipcHw_REG_BUS_CLOCK_OTP                       0x00020000      /* Bus interface clock for OTP */
-#define chipcHw_REG_BUS_CLOCK_PIF                       0x00040000      /* Bus interface clock for PIF */
-#define chipcHw_REG_BUS_CLOCK_SPU                       0x00080000      /* Bus interface clock for SPU */
-#define chipcHw_REG_BUS_CLOCK_SDIO0                     0x00100000      /* Bus interface clock for SDIO0 */
-#define chipcHw_REG_BUS_CLOCK_SDIO1                     0x00200000      /* Bus interface clock for SDIO1 */
-#define chipcHw_REG_BUS_CLOCK_SPIH                      0x00400000      /* Bus interface clock for SPIH */
-#define chipcHw_REG_BUS_CLOCK_SPIS                      0x00800000      /* Bus interface clock for SPIS */
-#define chipcHw_REG_BUS_CLOCK_UART0                     0x01000000      /* Bus interface clock for UART0 */
-#define chipcHw_REG_BUS_CLOCK_UART1                     0x02000000      /* Bus interface clock for UART1 */
-#define chipcHw_REG_BUS_CLOCK_BBL                       0x04000000      /* Bus interface clock for BBL */
-#define chipcHw_REG_BUS_CLOCK_I2CS                      0x08000000      /* Bus interface clock for I2CS */
-#define chipcHw_REG_BUS_CLOCK_USBH                      0x10000000      /* Bus interface clock for USB Host */
-#define chipcHw_REG_BUS_CLOCK_USBD                      0x20000000      /* Bus interface clock for USB Device */
-#define chipcHw_REG_BUS_CLOCK_BROM                      0x40000000      /* Bus interface clock for Boot ROM */
-#define chipcHw_REG_BUS_CLOCK_TSC                       0x80000000      /* Bus interface clock for Touch screen */
-
-/* Software resets defines */
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD          0x0000000080000000ULL   /* Reset Global VPM and hold */
-#define chipcHw_REG_SOFT_RESET_VPM_HOLD                 0x0000000040000000ULL   /* Reset VPM and hold */
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL               0x0000000020000000ULL   /* Reset Global VPM */
-#define chipcHw_REG_SOFT_RESET_VPM                      0x0000000010000000ULL   /* Reset VPM */
-#define chipcHw_REG_SOFT_RESET_KEYPAD                   0x0000000008000000ULL   /* Reset Key pad */
-#define chipcHw_REG_SOFT_RESET_LED                      0x0000000004000000ULL   /* Reset LED */
-#define chipcHw_REG_SOFT_RESET_SPU                      0x0000000002000000ULL   /* Reset SPU */
-#define chipcHw_REG_SOFT_RESET_RNG                      0x0000000001000000ULL   /* Reset RNG */
-#define chipcHw_REG_SOFT_RESET_PKA                      0x0000000000800000ULL   /* Reset PKA */
-#define chipcHw_REG_SOFT_RESET_LCD                      0x0000000000400000ULL   /* Reset LCD */
-#define chipcHw_REG_SOFT_RESET_PIF                      0x0000000000200000ULL   /* Reset PIF */
-#define chipcHw_REG_SOFT_RESET_I2CS                     0x0000000000100000ULL   /* Reset I2C Slave */
-#define chipcHw_REG_SOFT_RESET_I2CH                     0x0000000000080000ULL   /* Reset I2C Host */
-#define chipcHw_REG_SOFT_RESET_SDIO1                    0x0000000000040000ULL   /* Reset SDIO 1 */
-#define chipcHw_REG_SOFT_RESET_SDIO0                    0x0000000000020000ULL   /* Reset SDIO 0 */
-#define chipcHw_REG_SOFT_RESET_BBL                      0x0000000000010000ULL   /* Reset BBL */
-#define chipcHw_REG_SOFT_RESET_I2S1                     0x0000000000008000ULL   /* Reset I2S1 */
-#define chipcHw_REG_SOFT_RESET_I2S0                     0x0000000000004000ULL   /* Reset I2S0 */
-#define chipcHw_REG_SOFT_RESET_SPIS                     0x0000000000002000ULL   /* Reset SPI Slave */
-#define chipcHw_REG_SOFT_RESET_SPIH                     0x0000000000001000ULL   /* Reset SPI Host */
-#define chipcHw_REG_SOFT_RESET_GPIO1                    0x0000000000000800ULL   /* Reset GPIO block 1 */
-#define chipcHw_REG_SOFT_RESET_GPIO0                    0x0000000000000400ULL   /* Reset GPIO block 0 */
-#define chipcHw_REG_SOFT_RESET_UART1                    0x0000000000000200ULL   /* Reset UART 1 */
-#define chipcHw_REG_SOFT_RESET_UART0                    0x0000000000000100ULL   /* Reset UART 0 */
-#define chipcHw_REG_SOFT_RESET_NVI                      0x0000000000000080ULL   /* Reset NVI */
-#define chipcHw_REG_SOFT_RESET_WDOG                     0x0000000000000040ULL   /* Reset Watch dog */
-#define chipcHw_REG_SOFT_RESET_TMR                      0x0000000000000020ULL   /* Reset Timer */
-#define chipcHw_REG_SOFT_RESET_ETM                      0x0000000000000010ULL   /* Reset ETM */
-#define chipcHw_REG_SOFT_RESET_ARM_HOLD                 0x0000000000000008ULL   /* Reset ARM and HOLD */
-#define chipcHw_REG_SOFT_RESET_ARM                      0x0000000000000004ULL   /* Reset ARM */
-#define chipcHw_REG_SOFT_RESET_CHIP_WARM                0x0000000000000002ULL   /* Chip warm reset */
-#define chipcHw_REG_SOFT_RESET_CHIP_SOFT                0x0000000000000001ULL   /* Chip soft reset */
-#define chipcHw_REG_SOFT_RESET_VDEC                     0x0000100000000000ULL   /* Video decoder */
-#define chipcHw_REG_SOFT_RESET_GE                       0x0000080000000000ULL   /* Graphics engine */
-#define chipcHw_REG_SOFT_RESET_OTP                      0x0000040000000000ULL   /* Reset OTP */
-#define chipcHw_REG_SOFT_RESET_USB2                     0x0000020000000000ULL   /* Reset USB2 */
-#define chipcHw_REG_SOFT_RESET_USB1                     0x0000010000000000ULL   /* Reset USB 1 */
-#define chipcHw_REG_SOFT_RESET_USB                      0x0000008000000000ULL   /* Reset USB 1 and USB2 soft reset */
-#define chipcHw_REG_SOFT_RESET_ESW                      0x0000004000000000ULL   /* Reset Ethernet switch */
-#define chipcHw_REG_SOFT_RESET_ESWCLK                   0x0000002000000000ULL   /* Reset Ethernet switch clock */
-#define chipcHw_REG_SOFT_RESET_DDRPHY                   0x0000001000000000ULL   /* Reset DDR Physical */
-#define chipcHw_REG_SOFT_RESET_DDR                      0x0000000800000000ULL   /* Reset DDR Controller */
-#define chipcHw_REG_SOFT_RESET_TSC                      0x0000000400000000ULL   /* Reset Touch screen */
-#define chipcHw_REG_SOFT_RESET_PCM                      0x0000000200000000ULL   /* Reset PCM device */
-#define chipcHw_REG_SOFT_RESET_APM                      0x0000200100000000ULL   /* Reset APM device */
-
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD        0x8000000000000000ULL   /* Unhold Global VPM */
-#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD               0x4000000000000000ULL   /* Unhold VPM */
-#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD               0x2000000000000000ULL   /* Unhold ARM reset  */
-#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK              0xF000000000000000ULL   /* Mask to handle unhold request */
-
-/* Audio channel control defines */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL            0x00000001      /* Enable all audio channel */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A              0x00000002      /* Enable channel A */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B              0x00000004      /* Enable channel B */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C              0x00000008      /* Enable channel C */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK      0x00000010      /* Enable NTP clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK     0x00000020      /* Enable PCM0 clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK     0x00000040      /* Enable PCM1 clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK      0x00000080      /* Enable APM clock */
-
-/* Misc. chip control defines */
-#define chipcHw_REG_MISC_CTRL_GE_SEL                    0x00040000      /* Select GE2/GE3 */
-#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP         0x00000000      /* Use on chip clock for I2S1 */
-#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO           0x00020000      /* Use external clock via GPIO pin 26 for I2S1 */
-#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP         0x00000000      /* Use on chip clock for I2S0 */
-#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO           0x00010000      /* Use external clock via GPIO pin 45 for I2S0 */
-#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE          0x00008000      /* Disable ARM CP15 bit */
-#define chipcHw_REG_MISC_CTRL_RTC_DISABLE               0x00000008      /* Disable RTC registers */
-#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE             0x00000004      /* Disable Battery Backed RAM */
-#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST             0x00000002      /* Set USB as host */
-#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE           0xFFFFFFFD      /* Set USB as device */
-#define chipcHw_REG_MISC_CTRL_USB_POWERON               0xFFFFFFFE      /* Power up USB */
-#define chipcHw_REG_MISC_CTRL_USB_POWEROFF              0x00000001      /* Power down USB */
-
-/* OTP configuration defines */
-#define chipcHw_REG_OTP_SECURITY_OFF                    0x0000020000000000ULL   /* Security support is OFF */
-#define chipcHw_REG_OTP_SPU_SLOW                        0x0000010000000000ULL   /* Limited SPU throughput */
-#define chipcHw_REG_OTP_LCD_SPEED                       0x0000000600000000ULL   /* Set VPM speed one */
-#define chipcHw_REG_OTP_VPM_SPEED_1                     0x0000000100000000ULL   /* Set VPM speed one */
-#define chipcHw_REG_OTP_VPM_SPEED_0                     0x0000000080000000ULL   /* Set VPM speed zero */
-#define chipcHw_REG_OTP_AXI_SPEED                       0x0000000060000000ULL   /* Set maximum AXI bus speed */
-#define chipcHw_REG_OTP_APM_DISABLE                     0x000000001F000000ULL   /* Disable APM */
-#define chipcHw_REG_OTP_PIF_DISABLE                     0x0000000000200000ULL   /* Disable PIF */
-#define chipcHw_REG_OTP_VDEC_DISABLE                    0x0000000000100000ULL   /* Disable Video decoder */
-#define chipcHw_REG_OTP_BBL_DISABLE                     0x0000000000080000ULL   /* Disable RTC and BBRAM */
-#define chipcHw_REG_OTP_LED_DISABLE                     0x0000000000040000ULL   /* Disable LED */
-#define chipcHw_REG_OTP_GE_DISABLE                      0x0000000000020000ULL   /* Disable Graphics Engine */
-#define chipcHw_REG_OTP_LCD_DISABLE                     0x0000000000010000ULL   /* Disable LCD */
-#define chipcHw_REG_OTP_KEYPAD_DISABLE                  0x0000000000008000ULL   /* Disable keypad */
-#define chipcHw_REG_OTP_UART_DISABLE                    0x0000000000004000ULL   /* Disable UART */
-#define chipcHw_REG_OTP_SDIOH_DISABLE                   0x0000000000003000ULL   /* Disable SDIO host */
-#define chipcHw_REG_OTP_HSS_DISABLE                     0x0000000000000C00ULL   /* Disable HSS */
-#define chipcHw_REG_OTP_TSC_DISABLE                     0x0000000000000200ULL   /* Disable touch screen */
-#define chipcHw_REG_OTP_USB_DISABLE                     0x0000000000000180ULL   /* Disable USB */
-#define chipcHw_REG_OTP_SGMII_DISABLE                   0x0000000000000060ULL   /* Disable SGMII */
-#define chipcHw_REG_OTP_ETH_DISABLE                     0x0000000000000018ULL   /* Disable gigabit ethernet */
-#define chipcHw_REG_OTP_ETH_PHY_DISABLE                 0x0000000000000006ULL   /* Disable ethernet PHY */
-#define chipcHw_REG_OTP_VPM_DISABLE                     0x0000000000000001ULL   /* Disable VPM */
-
-/* Sticky bit defines */
-#define chipcHw_REG_STICKY_BOOT_DONE                    0x00000001      /* Boot done */
-#define chipcHw_REG_STICKY_SOFT_RESET                   0x00000002      /* ARM soft reset */
-#define chipcHw_REG_STICKY_GENERAL_1                    0x00000004      /* General purpose bit 1 */
-#define chipcHw_REG_STICKY_GENERAL_2                    0x00000008      /* General purpose bit 2 */
-#define chipcHw_REG_STICKY_GENERAL_3                    0x00000010      /* General purpose bit 3 */
-#define chipcHw_REG_STICKY_GENERAL_4                    0x00000020      /* General purpose bit 4 */
-#define chipcHw_REG_STICKY_GENERAL_5                    0x00000040      /* General purpose bit 5 */
-#define chipcHw_REG_STICKY_POR_BROM                     0x00000080      /* Special sticky bit for security - set in BROM to avoid other modes being entered */
-#define chipcHw_REG_STICKY_ARM_RESET                    0x00000100      /* ARM reset */
-#define chipcHw_REG_STICKY_CHIP_SOFT_RESET              0x00000200      /* Chip soft reset */
-#define chipcHw_REG_STICKY_CHIP_WARM_RESET              0x00000400      /* Chip warm reset */
-#define chipcHw_REG_STICKY_WDOG_RESET                   0x00000800      /* Watchdog reset */
-#define chipcHw_REG_STICKY_OTP_RESET                    0x00001000      /* OTP reset */
-
-                                                        /* HW phase alignment defines *//* Spare1 register definitions */
-#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE        0x80000000      /* Enable DDR phase align panic interrupt */
-#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE        0x40000000      /* Enable VPM phase align panic interrupt */
-#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE        0x00000002      /* Enable access to VPM using system BUS */
-#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE        0x00000001      /* Enable access to DDR using system BUS */
-                                                        /* DDRPhaseCtrl1 register definitions */
-#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE            0x80000000      /* Enable DDR SW phase alignment */
-#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE            0x40000000      /* Enable DDR HW phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK             0x0000007F      /* DDR lower threshold for phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT            23
-#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK             0x0000007F      /* DDR upper threshold for phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT            16
-#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF      /* BUS Cycle to wait to run next DDR phase alignment */
-#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
-                                                        /* VPMPhaseCtrl1 register definitions */
-#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE            0x80000000      /* Enable VPM SW phase alignment */
-#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE            0x40000000      /* Enable VPM HW phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK             0x0000007F      /* VPM lower threshold for phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT            23
-#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK             0x0000007F      /* VPM upper threshold for phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT            16
-#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF      /* BUS Cycle to wait to complete the VPM phase alignment */
-#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
-                                                        /* PhaseAlignStatus register definitions */
-#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS             0x80000000      /* DDR time out interrupt status */
-#define chipcHw_REG_DDR_PHASE_STATUS_MASK               0x0000007F      /* DDR phase status value */
-#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT              24
-#define chipcHw_REG_DDR_PHASE_ALIGNED                   0x00800000      /* DDR Phase aligned status */
-#define chipcHw_REG_DDR_LOAD                            0x00400000      /* Load DDR phase status */
-#define chipcHw_REG_DDR_PHASE_CTRL_MASK                 0x0000003F      /* DDR phase control value */
-#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT                16
-#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS             0x80000000      /* VPM time out interrupt status */
-#define chipcHw_REG_VPM_PHASE_STATUS_MASK               0x0000007F      /* VPM phase status value */
-#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT              8
-#define chipcHw_REG_VPM_PHASE_ALIGNED                   0x00000080      /* VPM Phase aligned status */
-#define chipcHw_REG_VPM_LOAD                            0x00000040      /* Load VPM phase status */
-#define chipcHw_REG_VPM_PHASE_CTRL_MASK                 0x0000003F      /* VPM phase control value */
-#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT                0
-                                                        /* DDRPhaseCtrl2 register definitions */
-#define chipcHw_REG_DDR_INTR_SERVICED                   0x02000000      /* Acknowledge that interrupt was serviced */
-#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE             0x01000000      /* Enable time out interrupt */
-#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F      /* Wait before toggling load_ch */
-#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT     20
-#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F      /* Total wait to settle ph_ctrl and load_ch */
-#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
-#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF      /* Time out value for DDR HW phase alignment */
-#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT       0
-                                                        /* VPMPhaseCtrl2 register definitions */
-#define chipcHw_REG_VPM_INTR_SELECT_MASK                0x00000003      /* Interrupt select */
-#define chipcHw_REG_VPM_INTR_SELECT_SHIFT               26
-#define chipcHw_REG_VPM_INTR_DISABLE                    0x00000000
-#define chipcHw_REG_VPM_INTR_FAST                       (0x1 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_MEDIUM                     (0x2 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_SLOW                       (0x3 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_SERVICED                   0x02000000      /* Acknowledge that interrupt was serviced */
-#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE             0x01000000      /* Enable time out interrupt */
-#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F      /* Wait before toggling load_ch */
-#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT     20
-#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F      /* Total wait cycle to settle ph_ctrl and load_ch */
-#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
-#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF      /* Time out value for VPM HW phase alignment */
-#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT       0
-
-#endif /* CHIPCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
deleted file mode 100644
index 39da2c1fdafb..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
+++ /dev/null
@@ -1,872 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    ddrcReg.h
-*
-*  @brief   Register definitions for BCMRING DDR2 Controller and PHY
-*
-*/
-/****************************************************************************/
-
-#ifndef DDRC_REG_H
-#define DDRC_REG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <mach/csp/reg.h>
-#include <linux/types.h>
-
-#include <mach/csp/mm_io.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-/*********************************************************************/
-/* DDR2 Controller (ARM PL341) register definitions */
-/*********************************************************************/
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 DDR2 configuration registers, offset 0x000 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-        typedef struct {
-                uint32_t memcStatus;
-                uint32_t memcCmd;
-                uint32_t directCmd;
-                uint32_t memoryCfg;
-                uint32_t refreshPrd;
-                uint32_t casLatency;
-                uint32_t writeLatency;
-                uint32_t tMrd;
-                uint32_t tRas;
-                uint32_t tRc;
-                uint32_t tRcd;
-                uint32_t tRfc;
-                uint32_t tRp;
-                uint32_t tRrd;
-                uint32_t tWr;
-                uint32_t tWtr;
-                uint32_t tXp;
-                uint32_t tXsr;
-                uint32_t tEsr;
-                uint32_t memoryCfg2;
-                uint32_t memoryCfg3;
-                uint32_t tFaw;
-        } ddrcReg_CTLR_MEMC_REG_t;
-
-#define ddrcReg_CTLR_MEMC_REG_OFFSET                    0x0000
-#define ddrcReg_CTLR_MEMC_REGP                          ((volatile ddrcReg_CTLR_MEMC_REG_t *)  (MM_IO_BASE_DDRC + ddrcReg_CTLR_MEMC_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK             (0x3 << 12)
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_4                (0x0 << 12)
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_8                (0x3 << 12)
-
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK          (0x3 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0             (0x0 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1             (0x1 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2             (0x2 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4             (0x3 << 10)
-
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK             (0x3 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1                (0x0 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2                (0x1 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3                (0x2 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4                (0x3 << 7)
-
-#define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK              (0x7 << 4)
-#define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2              (0x5 << 4)
-
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK             (0x3 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16               (0x0 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32               (0x1 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64               (0x2 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128              (0x3 << 2)
-
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK             (0x3 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG           (0x0 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_READY            (0x1 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED           (0x2 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR           (0x3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMC_CMD_MASK                      (0x7 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_GO                        (0x0 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_SLEEP                     (0x1 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_WAKEUP                    (0x2 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_PAUSE                     (0x3 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_CONFIGURE                 (0x4 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE              (0x7 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT              20
-#define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK               (0x3 << ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT)
-
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL       (0x0 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH        (0x1 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG            (0x2 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP                (0x3 << 18)
-
-#define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT              16
-#define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK               (0x3 << ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT)
-
-#define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT              0
-#define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK               (0x1ffff << ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK           (0x3 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1              (0x0 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2              (0x1 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3              (0x2 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4              (0x3 << 21)
-
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK           (0x7 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0            (0x0 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1            (0x1 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2            (0x2 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3            (0x3 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4            (0x4 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5            (0x5 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6            (0x6 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7           (0x7 << 18)
-
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK          (0x7 << 15)
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4             (0x2 << 15)
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8             (0x3 << 15)     /* @note Not supported in PL341 */
-
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE          (0x1 << 13)
-
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT    7
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK     (0x3f << ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT)
-
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK       (0x7 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11         (0x0 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12         (0x1 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13         (0x2 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14         (0x3 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15         (0x4 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16         (0x5 << 3)
-
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK       (0x7 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9          (0x1 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10         (0x2 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11         (0x3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_REFRESH_PRD_SHIFT                  0
-#define ddrcReg_CTLR_REFRESH_PRD_MASK                   (0x7fff << ddrcReg_CTLR_REFRESH_PRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_CAS_LATENCY_SHIFT                  1
-#define ddrcReg_CTLR_CAS_LATENCY_MASK                   (0x7 << ddrcReg_CTLR_CAS_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_WRITE_LATENCY_SHIFT                0
-#define ddrcReg_CTLR_WRITE_LATENCY_MASK                 (0x7 << ddrcReg_CTLR_WRITE_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_MRD_SHIFT                        0
-#define ddrcReg_CTLR_T_MRD_MASK                         (0x7f << ddrcReg_CTLR_T_MRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RAS_SHIFT                        0
-#define ddrcReg_CTLR_T_RAS_MASK                         (0x1f << ddrcReg_CTLR_T_RAS_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RC_SHIFT                         0
-#define ddrcReg_CTLR_T_RC_MASK                          (0x1f << ddrcReg_CTLR_T_RC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK          (0x7 << ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RCD_SHIFT                        0
-#define ddrcReg_CTLR_T_RCD_MASK                         (0x7 << ddrcReg_CTLR_T_RCD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK          (0x7f << ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RFC_SHIFT                        0
-#define ddrcReg_CTLR_T_RFC_MASK                         (0x7f << ddrcReg_CTLR_T_RFC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT          8
-#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK           (0x7 << ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RP_SHIFT                         0
-#define ddrcReg_CTLR_T_RP_MASK                          (0xf << ddrcReg_CTLR_T_RP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RRD_SHIFT                        0
-#define ddrcReg_CTLR_T_RRD_MASK                         (0xf << ddrcReg_CTLR_T_RRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_WR_SHIFT                         0
-#define ddrcReg_CTLR_T_WR_MASK                          (0x7 << ddrcReg_CTLR_T_WR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_WTR_SHIFT                        0
-#define ddrcReg_CTLR_T_WTR_MASK                         (0x7 << ddrcReg_CTLR_T_WTR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_XP_SHIFT                         0
-#define ddrcReg_CTLR_T_XP_MASK                          (0xff << ddrcReg_CTLR_T_XP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_XSR_SHIFT                        0
-#define ddrcReg_CTLR_T_XSR_MASK                         (0xff << ddrcReg_CTLR_T_XSR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_ESR_SHIFT                        0
-#define ddrcReg_CTLR_T_ESR_MASK                         (0xff << ddrcReg_CTLR_T_ESR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK             (0x3 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS           (0 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS           (1 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS           (2 << 6)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK     (0x3 << 4)
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2        (0 << 4)
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3        (3 << 4)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW     (0 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH    (1 << 3)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW     (0 << 2)
-#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH    (1 << 2)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK               (0x3 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC              (0 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M        (1 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M        (3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT       0
-#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK        (0x7 << ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK          (0x1f << ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT                 0
-#define ddrcReg_CTLR_T_FAW_PERIOD_MASK                  (0x1f << ddrcReg_CTLR_T_FAW_PERIOD_SHIFT)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_QOS_CNT                            16
-#define ddrcReg_CTLR_QOS_MAX                            (ddrcReg_CTLR_QOS_CNT - 1)
-
-        typedef struct {
-                uint32_t cfg[ddrcReg_CTLR_QOS_CNT];
-        } ddrcReg_CTLR_QOS_REG_t;
-
-#define ddrcReg_CTLR_QOS_REG_OFFSET                     0x100
-#define ddrcReg_CTLR_QOS_REGP                           ((volatile ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT                  2
-#define ddrcReg_CTLR_QOS_CFG_MAX_MASK                   (0xff << ddrcReg_CTLR_QOS_CFG_MAX_SHIFT)
-
-#define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT                  1
-#define ddrcReg_CTLR_QOS_CFG_MIN_MASK                   (1 << ddrcReg_CTLR_QOS_CFG_MIN_SHIFT)
-
-#define ddrcReg_CTLR_QOS_CFG_ENABLE                     (1 << 0)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 Memory chip configuration registers, offset 0x200 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_CHIP_CNT                           4
-#define ddrcReg_CTLR_CHIP_MAX                           (ddrcReg_CTLR_CHIP_CNT - 1)
-
-        typedef struct {
-                uint32_t cfg[ddrcReg_CTLR_CHIP_CNT];
-        } ddrcReg_CTLR_CHIP_REG_t;
-
-#define ddrcReg_CTLR_CHIP_REG_OFFSET                    0x200
-#define ddrcReg_CTLR_CHIP_REGP                          ((volatile ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK              (1 << 16)
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL      (0 << 16)
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL      (1 << 16)
-
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT      8
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK       (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT)
-
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT       0
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK        (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 User configuration registers, offset 0x300 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_OUTPUT_CNT                    2
-
-        typedef struct {
-                uint32_t input;
-                uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT];
-                uint32_t feature;
-        } ddrcReg_CTLR_USER_REG_t;
-
-#define ddrcReg_CTLR_USER_REG_OFFSET                    0x300
-#define ddrcReg_CTLR_USER_REGP                          ((volatile ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT            0
-#define ddrcReg_CTLR_USER_INPUT_STATUS_MASK             (0xff << ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT              0
-#define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK               (0xff << ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT)
-
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT      1
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK       (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134      (0 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301      (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE        (1 << 2)
-#define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE    (1 << 0)
-
-/*********************************************************************/
-/* Broadcom DDR23 PHY register definitions */
-/*********************************************************************/
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* Broadcom DDR23 PHY Address and Control register definitions */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-        typedef struct {
-                uint32_t revision;
-                uint32_t pmCtl;
-                 REG32_RSVD(0x0008, 0x0010);
-                uint32_t pllStatus;
-                uint32_t pllCfg;
-                uint32_t pllPreDiv;
-                uint32_t pllDiv;
-                uint32_t pllCtl1;
-                uint32_t pllCtl2;
-                uint32_t ssCtl;
-                uint32_t ssCfg;
-                uint32_t vdlStatic;
-                uint32_t vdlDynamic;
-                uint32_t padIdle;
-                uint32_t pvtComp;
-                uint32_t padDrive;
-                uint32_t clkRgltrCtl;
-        } ddrcReg_PHY_ADDR_CTL_REG_t;
-
-#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET                 0x0400
-#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile ddrcReg_PHY_ADDR_CTL_REG_t __iomem*) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
-
-/* @todo These SS definitions are duplicates of ones below */
-
-#define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE                 0x00000001
-#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK     0xFFFF0000
-#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT    16
-#define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK      10      /* Higher the value, lower the SS modulation frequency */
-#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK     0x0000FFFF
-#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT    0
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT       8
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK        (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK        (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED          (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET     (1 << 31)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT     17
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK      (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE        (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG            (1 << 7)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN         (1 << 6)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE      (1 << 5)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE      (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET            (1 << 3)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET            (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN             (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB     (1 << 26)
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN         (1 << 25)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT     20
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT      8
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK       (0x1ff << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT       4
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT           24
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK            (0xff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT         0
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK          (0xffffff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT       30
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK        (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT     27
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT     24
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT      22
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER          (0x1 << 21)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT          19
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT          17
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT          15
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT          13
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT          10
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK           (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT        5
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK         (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT     0
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK      (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT)
-
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT    4
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK     (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT    2
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK     (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE     (0x1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE     (0x1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE           (0x1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT  16
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK   (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT      0
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK       (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE           (1 << 20)
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE          (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT      12
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT      8
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT      0
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK       (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE         (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK      (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT     8
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK      (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT     0
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK      (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE            (1u << 31)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE     (1 << 8)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE  (1 << 6)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE   (1 << 5)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE   (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE  (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE   (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE   (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE           (1 << 30)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE           (1 << 29)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE       (1 << 28)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE    (1 << 27)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE     (1 << 26)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE   (1 << 25)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE     (1 << 24)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT          20
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK           (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT          16
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK           (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT     8
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT       4
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B            (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18       (1 << 3)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI      (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV         (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW             (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF     (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF      (1 << 0)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* Broadcom DDR23 PHY Byte Lane register definitions */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_CNT                       2
-#define ddrcReg_PHY_BYTE_LANE_MAX                       (ddrcReg_CTLR_BYTE_LANE_CNT - 1)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT               8
-
-        typedef struct {
-                uint32_t revision;
-                uint32_t vdlCalibrate;
-                uint32_t vdlStatus;
-                 REG32_RSVD(0x000c, 0x0010);
-                uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT];
-                uint32_t readCtl;
-                uint32_t readStatus;
-                uint32_t readClear;
-                uint32_t padIdleCtl;
-                uint32_t padDriveCtl;
-                uint32_t padClkCtl;
-                uint32_t writeCtl;
-                uint32_t clkRegCtl;
-        } ddrcReg_PHY_BYTE_LANE_REG_t;
-
-/* There are 2 instances of the byte Lane registers, one for each byte lane. */
-#define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET              0x0500
-#define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET              0x0600
-
-#define ddrcReg_PHY_BYTE_LANE_1_REGP                    ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET))
-#define ddrcReg_PHY_BYTE_LANE_2_REGP                    ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT      8
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK       (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT      0
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK       (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE      (1 << 4)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE      (0 << 4)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST            (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS          (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE            (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST            (1 << 0)
-
-/* ----------------------------------------------------- */
-
-/* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step value, [3:2] fine fall */
-/* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 in the VDL status */
-/* register. The fine rise and fall are no longer used, so add some definitions for just */
-/* the step setting to simplify things. */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT     8
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK      (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT    4
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK     (0x3ff << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK           (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE           (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE            (1 << 16)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT        12
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK         (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT        8
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK         (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT        0
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK         (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P     0
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N     1
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN        2
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM   3
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P    4
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N    5
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN       6
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM  7
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT      8
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK       (0x3 << ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE    (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST    (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE    (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST    (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT   0
-#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK    (0xf << ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS         (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE                   (1u << 31)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE         (1 << 19)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE          (1 << 18)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE           (1 << 17)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE           (1 << 16)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE         (1 << 15)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE          (1 << 14)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE           (1 << 13)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE           (1 << 12)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE   (1 << 11)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE    (1 << 10)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE     (1 << 9)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE     (1 << 8)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE        (1 << 7)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE         (1 << 6)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE          (1 << 5)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE          (1 << 4)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE        (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE         (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE          (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE          (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB      (1 << 5)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B                   (1 << 4)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18              (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI             (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV                (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW                    (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE                   (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3               (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF                  (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF                   (1 << 0)
-
-/*********************************************************************/
-/* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */
-/*********************************************************************/
-
-        typedef struct {
-                uint32_t cfg;
-                uint32_t actMonCnt;
-                uint32_t ctl;
-                uint32_t lbistCtl;
-                uint32_t lbistSeed;
-                uint32_t lbistStatus;
-                uint32_t tieOff;
-                uint32_t actMonClear;
-                uint32_t status;
-                uint32_t user;
-        } ddrcReg_CTLR_PHY_GLUE_REG_t;
-
-#define ddrcReg_CTLR_PHY_GLUE_OFFSET                            0x0700
-#define ddrcReg_CTLR_PHY_GLUE_REGP                              ((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_PHY_GLUE_OFFSET))
-
-/* ----------------------------------------------------- */
-
-/* DDR2 / AXI block phase alignment interrupt control */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT                     18
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK                      (0x3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF                       (0 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT                  (1 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM                 (2 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE                  (3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT              17
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK               (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL       (0 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS               (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT            16
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK             (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP             (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW          (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED   ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT             15
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK              (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134             (0 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301             (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED        ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301
-
-/* Software control of PHY VDL updates from control register settings. Bit 13 enables the use of Bit 14. */
-/* If software control is not enabled, then updates occur when a refresh command is issued by the hardware */
-/* controller. If 2 chips selects are being used, then software control must be enabled. */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD    (1 << 14)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE  (1 << 13)
-
-/* Use these to bypass a pipeline stage. By default the ADDR is off but the BYTE LANE in / out are on. */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE (1 << 12)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10)
-
-/* Chip select count */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT                  9
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK                   (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1                      (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2                      (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT                     8
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC                     (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC                      (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT                7
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW                  (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH                 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT                6
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW                  (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH                 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT             0
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK              (0x7 << ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT                0
-#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK                 (0x7f << ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT)
-
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#ifdef __cplusplus
-}                               /* end extern "C" */
-#endif
-#endif                          /* DDRC_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
deleted file mode 100644
index 9dc90f46a84d..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
+++ /dev/null
@@ -1,596 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw.h
-*
-*  @brief   API definitions for low level DMA controller driver
-*
-*/
-/****************************************************************************/
-#ifndef _DMACHW_H
-#define _DMACHW_H
-
-#include <linux/stddef.h>
-
-#include <linux/types.h>
-#include <mach/csp/dmacHw_reg.h>
-
-/* Define DMA Channel ID using DMA controller number (m) and channel number (c).
-
-   System specific channel ID should be defined as follows
-
-   For example:
-
-   #include <dmacHw.h>
-   ...
-   #define systemHw_LCD_CHANNEL_ID                dmacHw_MAKE_CHANNEL_ID(0,5)
-   #define systemHw_SWITCH_RX_CHANNEL_ID          dmacHw_MAKE_CHANNEL_ID(0,0)
-   #define systemHw_SWITCH_TX_CHANNEL_ID          dmacHw_MAKE_CHANNEL_ID(0,1)
-   #define systemHw_APM_RX_CHANNEL_ID             dmacHw_MAKE_CHANNEL_ID(0,3)
-   #define systemHw_APM_TX_CHANNEL_ID             dmacHw_MAKE_CHANNEL_ID(0,4)
-   ...
-   #define systemHw_SHARED1_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(1,4)
-   #define systemHw_SHARED2_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(1,5)
-   #define systemHw_SHARED3_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(0,6)
-   ...
-*/
-#define dmacHw_MAKE_CHANNEL_ID(m, c)         (m << 8 | c)
-
-typedef enum {
-        dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0,    /* Channel priority 0. Lowest priority DMA channel */
-        dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1,    /* Channel priority 1 */
-        dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2,    /* Channel priority 2 */
-        dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3,    /* Channel priority 3 */
-        dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4,    /* Channel priority 4 */
-        dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5,    /* Channel priority 5 */
-        dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6,    /* Channel priority 6 */
-        dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7     /* Channel priority 7. Highest priority DMA channel */
-} dmacHw_CHANNEL_PRIORITY_e;
-
-/* Source destination master interface */
-typedef enum {
-        dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1,   /* Source DMA master interface 1 */
-        dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2,   /* Source DMA master interface 2 */
-        dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1,   /* Destination DMA master interface 1 */
-        dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2    /* Destination DMA master interface 2 */
-} dmacHw_MASTER_INTERFACE_e;
-
-typedef enum {
-        dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, /* Source 8 bit  (1 byte) per transaction */
-        dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16,       /* Source 16 bit (2 byte) per transaction */
-        dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32,       /* Source 32 bit (4 byte) per transaction */
-        dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64,       /* Source 64 bit (8 byte) per transaction */
-        dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, /* Destination 8 bit  (1 byte) per transaction */
-        dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16,       /* Destination 16 bit (2 byte) per transaction */
-        dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32,       /* Destination 32 bit (4 byte) per transaction */
-        dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64        /* Destination 64 bit (8 byte) per transaction */
-} dmacHw_TRANSACTION_WIDTH_e;
-
-typedef enum {
-        dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0,  /* Source No burst */
-        dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4,  /* Source 4  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-        dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8,  /* Source 8  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-        dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16,        /* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-        dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0,  /* Destination No burst */
-        dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4,  /* Destination 4  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-        dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8,  /* Destination 8  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-        dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16 /* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-} dmacHw_BURST_WIDTH_e;
-
-typedef enum {
-        dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC,  /* Memory to memory transfer */
-        dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC,   /* Peripheral to memory transfer */
-        dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC,   /* Memory to peripheral transfer */
-        dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC     /* Peripheral to peripheral transfer */
-} dmacHw_TRANSFER_TYPE_e;
-
-typedef enum {
-        dmacHw_TRANSFER_MODE_PERREQUEST,        /* Block transfer per DMA request */
-        dmacHw_TRANSFER_MODE_CONTINUOUS,        /* Continuous transfer of streaming data */
-        dmacHw_TRANSFER_MODE_PERIODIC   /* Periodic transfer of streaming data */
-} dmacHw_TRANSFER_MODE_e;
-
-typedef enum {
-        dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC,   /* Increment source address after every transaction */
-        dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC,   /* Decrement source address after every transaction */
-        dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC,   /* Increment destination address after every transaction */
-        dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC,   /* Decrement destination address after every transaction */
-        dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC,     /* No change in source address after every transaction */
-        dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC      /* No change in destination address after every transaction */
-} dmacHw_ADDRESS_UPDATE_MODE_e;
-
-typedef enum {
-        dmacHw_FLOW_CONTROL_DMA,        /* DMA working as flow controller (default) */
-        dmacHw_FLOW_CONTROL_PERIPHERAL  /* Peripheral working as flow controller */
-} dmacHw_FLOW_CONTROL_e;
-
-typedef enum {
-        dmacHw_TRANSFER_STATUS_BUSY,    /* DMA Transfer ongoing */
-        dmacHw_TRANSFER_STATUS_DONE,    /* DMA Transfer completed */
-        dmacHw_TRANSFER_STATUS_ERROR    /* DMA Transfer error */
-} dmacHw_TRANSFER_STATUS_e;
-
-typedef enum {
-        dmacHw_INTERRUPT_DISABLE,       /* Interrupt disable  */
-        dmacHw_INTERRUPT_ENABLE /* Interrupt enable */
-} dmacHw_INTERRUPT_e;
-
-typedef enum {
-        dmacHw_INTERRUPT_STATUS_NONE = 0x0,     /* No DMA interrupt */
-        dmacHw_INTERRUPT_STATUS_TRANS = 0x1,    /* End of DMA transfer interrupt */
-        dmacHw_INTERRUPT_STATUS_BLOCK = 0x2,    /* End of block transfer interrupt */
-        dmacHw_INTERRUPT_STATUS_ERROR = 0x4     /* Error interrupt */
-} dmacHw_INTERRUPT_STATUS_e;
-
-typedef enum {
-        dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM,   /* Number of DMA channel */
-        dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE,        /* Maximum channel burst size */
-        dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM,       /* Number of DMA master interface */
-        dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH,     /* Channel Data bus width */
-        dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE      /* Channel FIFO size */
-} dmacHw_CONTROLLER_ATTRIB_e;
-
-typedef unsigned long dmacHw_HANDLE_t;  /* DMA channel handle */
-typedef uint32_t dmacHw_ID_t;   /* DMA channel Id.  Must be created using
-                                   "dmacHw_MAKE_CHANNEL_ID" macro
-                                 */
-/* DMA channel configuration parameters */
-typedef struct {
-        uint32_t srcPeripheralPort;     /* Source peripheral port */
-        uint32_t dstPeripheralPort;     /* Destination peripheral port */
-        uint32_t srcStatusRegisterAddress;      /* Source status register address */
-        uint32_t dstStatusRegisterAddress;      /* Destination status register address of type  */
-
-        uint32_t srcGatherWidth;        /* Number of bytes gathered before successive gather opearation */
-        uint32_t srcGatherJump; /* Number of bytes jumpped before successive gather opearation */
-        uint32_t dstScatterWidth;       /* Number of bytes sacattered before successive scatter opearation */
-        uint32_t dstScatterJump;        /* Number of bytes jumpped  before successive scatter opearation */
-        uint32_t maxDataPerBlock;       /* Maximum number of bytes to be transferred per block/descrptor.
-                                           0 = Maximum possible.
-                                         */
-
-        dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate; /* Source address update mode */
-        dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate; /* Destination address update mode */
-        dmacHw_TRANSFER_TYPE_e transferType;    /* DMA transfer type  */
-        dmacHw_TRANSFER_MODE_e transferMode;    /* DMA transfer mode */
-        dmacHw_MASTER_INTERFACE_e srcMasterInterface;   /* DMA source interface  */
-        dmacHw_MASTER_INTERFACE_e dstMasterInterface;   /* DMA destination interface */
-        dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth;      /* Source transaction width   */
-        dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth;      /* Destination transaction width */
-        dmacHw_BURST_WIDTH_e srcMaxBurstWidth;  /* Source burst width */
-        dmacHw_BURST_WIDTH_e dstMaxBurstWidth;  /* Destination burst width */
-        dmacHw_INTERRUPT_e blockTransferInterrupt;      /* Block trsnafer interrupt */
-        dmacHw_INTERRUPT_e completeTransferInterrupt;   /* Complete DMA trsnafer interrupt */
-        dmacHw_INTERRUPT_e errorInterrupt;      /* Error interrupt */
-        dmacHw_CHANNEL_PRIORITY_e channelPriority;      /* Channel priority */
-        dmacHw_FLOW_CONTROL_e flowControler;    /* Data flow controller */
-} dmacHw_CONFIG_t;
-
-/****************************************************************************/
-/**
-*  @brief   Initializes DMA
-*
-*  This function initializes DMA CSP driver
-*
-*  @note
-*     Must be called before using any DMA channel
-*/
-/****************************************************************************/
-void dmacHw_initDma(void);
-
-/****************************************************************************/
-/**
-*  @brief   Exit function for  DMA
-*
-*  This function isolates DMA from the system
-*
-*/
-/****************************************************************************/
-void dmacHw_exitDma(void);
-
-/****************************************************************************/
-/**
-*  @brief   Gets a handle to a DMA channel
-*
-*  This function returns a handle, representing a control block of a particular DMA channel
-*
-*  @return  -1       - On Failure
-*            handle  - On Success, representing a channel control block
-*
-*  @note
-*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId   /* [ IN ] DMA Channel Id */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Initializes a DMA channel for use
-*
-*  This function initializes and resets a DMA channel for use
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_initChannel(dmacHw_HANDLE_t handle   /*  [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Estimates number of descriptor needed to perform certain DMA transfer
-*
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor count
-*
-*
-*/
-/****************************************************************************/
-int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,   /*   [ IN ] Configuration settings */
-                                    void *pSrcAddr,     /*   [ IN ] Source (Peripheral/Memory) address */
-                                    void *pDstAddr,     /*   [ IN ] Destination (Peripheral/Memory) address */
-                                    size_t dataLen      /*   [ IN ] Data length in bytes */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Initializes descriptor ring
-*
-*  This function will initializes the descriptor ring of a DMA channel
-*
-*
-*  @return   -1 - On failure
-*             0 - On success
-*  @note
-*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
-*     - Descriptor buffer MUST be 32 bit aligned and uncached as it
-*       is accessed by ARM and DMA
-*/
-/****************************************************************************/
-int dmacHw_initDescriptor(void *pDescriptorVirt,        /*  [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
-                          uint32_t descriptorPhyAddr,   /*  [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
-                          uint32_t len, /*  [ IN ] Size of the pBuf */
-                          uint32_t num  /*  [ IN ] Number of descriptor in the ring */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Finds amount of memory required to form a descriptor ring
-*
-*
-*  @return   Number of bytes required to form a descriptor ring
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorLen(uint32_t descCnt  /*  [ IN ] Number of descriptor in the ring */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Configure DMA channel
-*
-*  @return  0  : On success
-*           -1 : On failure
-*/
-/****************************************************************************/
-int dmacHw_configChannel(dmacHw_HANDLE_t handle,        /*  [ IN ] DMA Channel handle  */
-                         dmacHw_CONFIG_t *pConfig       /*   [ IN ] Configuration settings */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptors for known data length
-*
-*  When DMA has to work as a flow controller, this function prepares the
-*  descriptor chain to transfer data
-*
-*  from:
-*          - Memory to memory
-*          - Peripheral to memory
-*          - Memory to Peripheral
-*          - Peripheral to Peripheral
-*
-*  @return   -1 - On failure
-*             0 - On success
-*
-*/
-/****************************************************************************/
-int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,  /*  [ IN ] Configuration settings */
-                             void *pDescriptor, /*  [ IN ] Descriptor buffer  */
-                             void *pSrcAddr,    /*  [ IN ] Source (Peripheral/Memory) address */
-                             void *pDstAddr,    /*  [ IN ] Destination (Peripheral/Memory) address */
-                             size_t dataLen     /*  [ IN ] Length in bytes   */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Indicates whether DMA transfer is in progress or completed
-*
-*  @return   DMA transfer status
-*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
-*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
-*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
-*
-*/
-/****************************************************************************/
-dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle        /*   [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptor carrying control information
-*
-*  This function will be used to send specific control information to the device
-*  using the DMA channel
-*
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,       /*  [ IN ] Configuration settings */
-                                void *pDescriptor,      /*  [ IN ] Descriptor buffer  */
-                                uint32_t ctlAddress,    /*  [ IN ] Address of the device control register  */
-                                uint32_t control        /*  [ IN ] Device control information */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Read data DMA transferred to memory
-*
-*  This function will read data that has been DMAed to memory while transferring from:
-*          - Memory to memory
-*          - Peripheral to memory
-*
-*  @return  0 - No more data is available to read
-*           1 - More data might be available to read
-*
-*/
-/****************************************************************************/
-int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle    */
-                               dmacHw_CONFIG_t *pConfig,        /*  [ IN ]  Configuration settings */
-                               void *pDescriptor,       /*  [ IN ] Descriptor buffer  */
-                               void **ppBbuf,   /*  [ OUT ] Data received */
-                               size_t *pLlen    /*  [ OUT ] Length of the data received */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Prepares descriptor ring, when source peripheral working as a flow controller
-*
-*  This function will form the descriptor ring by allocating buffers, when source peripheral
-*  has to work as a flow controller to transfer data from:
-*           - Peripheral to memory.
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,    /*  [ IN ] DMA Channel handle   */
-                                     dmacHw_CONFIG_t *pConfig,  /*  [ IN ] Configuration settings */
-                                     void *pDescriptor, /*  [ IN ] Descriptor buffer  */
-                                     uint32_t srcAddr,  /*  [ IN ] Source peripheral address */
-                                     void *(*fpAlloc) (int len),        /*  [ IN ] Function pointer  that provides destination memory */
-                                     int len,   /*  [ IN ] Number of bytes "fpAlloc" will allocate for destination */
-                                     int num    /*  [ IN ] Number of descriptor to set */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to initiate transfer
-*
-*  @return  void
-*
-*
-*  @note
-*     - Descriptor buffer MUST ALWAYS be flushed before calling this function
-*     - This function should also be called from ISR to program the channel with
-*       pending descriptors
-*/
-/****************************************************************************/
-void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,    /*   [ IN ] DMA Channel handle */
-                             dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
-                             void *pDescriptor  /*   [ IN ] Descriptor buffer  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Resets descriptor control information
-*
-*  @return  void
-*/
-/****************************************************************************/
-void dmacHw_resetDescriptorControl(void *pDescriptor    /*   [ IN ] Descriptor buffer  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to stop transfer
-*
-*  Ensures the channel is not doing any transfer after calling this function
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /*   [ IN ] DMA Channel handle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Check the existence of pending descriptor
-*
-*  This function confirmes if there is any pending descriptor in the chain
-*  to program the channel
-*
-*  @return  1 : Channel need to be programmed with pending descriptor
-*           0 : No more pending descriptor to programe the channel
-*
-*  @note
-*     - This function should be called from ISR in case there are pending
-*       descriptor to program the channel.
-*
-*     Example:
-*
-*     dmac_isr ()
-*     {
-*         ...
-*         if (dmacHw_descriptorPending (handle))
-*         {
-*            dmacHw_initiateTransfer (handle);
-*         }
-*     }
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,       /*   [ IN ] DMA Channel handle */
-                                  void *pDescriptor     /*   [ IN ] Descriptor buffer */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Deallocates source or destination memory, allocated
-*
-*  This function can be called to deallocate data memory that was DMAed successfully
-*
-*  @return  -1  - On failure
-*            0  - On success
-*
-*  @note
-*     This function will be called ONLY, when source OR destination address is pointing
-*     to dynamic memory
-*/
-/****************************************************************************/
-int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,    /*  [ IN ] Configuration settings */
-                   void *pDescriptor,   /*  [ IN ] Descriptor buffer  */
-                   void (*fpFree) (void *)      /*  [ IN ] Function pointer to free data memory */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the DMA channel specific interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle       /*  [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Returns the cause of channel specific DMA interrupt
-*
-*  This function returns the cause of interrupt
-*
-*  @return  Interrupt status, each bit representing a specific type of interrupt
-*           of type dmacHw_INTERRUPT_STATUS_e
-*  @note
-*           This function should be called under the context of ISR
-*/
-/****************************************************************************/
-dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle      /*  [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a DMA channel causing interrupt
-*
-*  This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
-*
-*  @return  NULL   : No channel causing DMA interrupt
-*           ! NULL : Handle to a channel causing DMA interrupt
-*  @note
-*     dmacHw_clearInterrupt() must be called with a valid handle after calling this function
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
-
-/****************************************************************************/
-/**
-*  @brief   Sets channel specific user data
-*
-*  This function associates user data to a specific DMA channel
-*
-*/
-/****************************************************************************/
-void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle  */
-                               void *userData   /*  [ IN ] User data  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Gets channel specific user data
-*
-*  This function returns user data specific to a DMA channel
-*
-*  @return   user data
-*/
-/****************************************************************************/
-void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle  /*  [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Displays channel specific registers and other control parameters
-*
-*
-*  @return  void
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,      /*  [ IN ] DMA Channel handle  */
-                           void *pDescriptor,   /*  [ IN ] Descriptor buffer  */
-                           int (*fpPrint) (const char *, ...)   /*  [ IN ] Print callback function */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Provides DMA controller attributes
-*
-*
-*  @return  DMA controller attributes
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,       /*  [ IN ]  DMA Channel handle  */
-                                          dmacHw_CONTROLLER_ATTRIB_e attr       /*  [ IN ]  DMA Controller attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
-    );
-
-#endif /* _DMACHW_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
deleted file mode 100644
index 9d9455e0c391..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_priv.h
-*
-*  @brief   Private Definitions for low level DMA driver
-*
-*/
-/****************************************************************************/
-
-#ifndef _DMACHW_PRIV_H
-#define _DMACHW_PRIV_H
-
-#include <linux/types.h>
-
-/* Data type for DMA Link List Item */
-typedef struct {
-        uint32_t sar;           /* Source Address Register.
-                                   Address must be aligned to CTLx.SRC_TR_WIDTH.             */
-        uint32_t dar;           /* Destination Address Register.
-                                   Address must be aligned to CTLx.DST_TR_WIDTH.             */
-        uint32_t llpPhy;        /* LLP contains the physical address of the next descriptor for block chaining using linked lists.
-                                   Address MUST be aligned to a 32-bit boundary.             */
-        dmacHw_REG64_t ctl;     /* Control Register. 64 bits */
-        uint32_t sstat;         /* Source Status Register */
-        uint32_t dstat;         /* Destination Status Register */
-        uint32_t devCtl;        /* Device specific control information */
-        uint32_t llp;           /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */
-} dmacHw_DESC_t;
-
-/*
- *  Descriptor ring pointers
- */
-typedef struct {
-        int num;                /* Number of link items */
-        dmacHw_DESC_t *pHead;   /* Head of descriptor ring (for writing) */
-        dmacHw_DESC_t *pTail;   /* Tail of descriptor ring (for reading) */
-        dmacHw_DESC_t *pProg;   /* Descriptor to program the channel (for programming the channel register) */
-        dmacHw_DESC_t *pEnd;    /* End of current descriptor chain */
-        dmacHw_DESC_t *pFree;   /* Descriptor to free memory (freeing dynamic memory) */
-        uint32_t virt2PhyOffset;        /* Virtual to physical address offset for the descriptor ring */
-} dmacHw_DESC_RING_t;
-
-/*
- *  DMA channel control block
- */
-typedef struct {
-        uint32_t module;        /* DMA controller module (0-1) */
-        uint32_t channel;       /* DMA channel (0-7) */
-        volatile uint32_t varDataStarted;       /* Flag indicating variable data channel is enabled */
-        volatile uint32_t descUpdated;  /* Flag to indicate descriptor update is complete */
-        void *userData;         /* Channel specifc user data */
-} dmacHw_CBLK_t;
-
-#define dmacHw_ASSERT(a)                  if (!(a)) while (1)
-#define dmacHw_MAX_CHANNEL_COUNT          16
-#define dmacHw_FREE_USER_MEMORY           0xFFFFFFFF
-#define dmacHw_DESC_FREE                  dmacHw_REG_CTL_DONE
-#define dmacHw_DESC_INIT                  ((dmacHw_DESC_t *) 0xFFFFFFFF)
-#define dmacHw_MAX_BLOCKSIZE              4064
-#define dmacHw_GET_DESC_RING(addr)        (dmacHw_DESC_RING_t *)(addr)
-#define dmacHw_ADDRESS_MASK(byte)         ((byte) - 1)
-#define dmacHw_NEXT_DESC(rp, dp)           ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp)
-#define dmacHw_HANDLE_TO_CBLK(handle)     ((dmacHw_CBLK_t *) (handle))
-#define dmacHw_CBLK_TO_HANDLE(cblkp)      ((dmacHw_HANDLE_t) (cblkp))
-#define dmacHw_DST_IS_MEMORY(tt)          (((tt) ==  dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
-
-/****************************************************************************/
-/**
-*  @brief   Get next available transaction width
-*
-*
-*  @return  On success  : Next available transaction width
-*           On failure : dmacHw_TRANSACTION_WIDTH_8
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw    /*   [ IN ] Current transaction width */
-    ) {
-        if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
-                return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
-                         1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
-        } else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
-                return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
-                         1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
-        }
-
-        /* Default return  */
-        return dmacHw_SRC_TRANSACTION_WIDTH_8;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get number of bytes per transaction
-*
-*  @return  Number of bytes per transaction
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw        /*   [ IN ]  Transaction width */
-    ) {
-        int width = 1;
-        switch (tw) {
-        case dmacHw_SRC_TRANSACTION_WIDTH_8:
-                width = 1;
-                break;
-        case dmacHw_SRC_TRANSACTION_WIDTH_16:
-        case dmacHw_DST_TRANSACTION_WIDTH_16:
-                width = 2;
-                break;
-        case dmacHw_SRC_TRANSACTION_WIDTH_32:
-        case dmacHw_DST_TRANSACTION_WIDTH_32:
-                width = 4;
-                break;
-        case dmacHw_SRC_TRANSACTION_WIDTH_64:
-        case dmacHw_DST_TRANSACTION_WIDTH_64:
-                width = 8;
-                break;
-        default:
-                dmacHw_ASSERT(0);
-        }
-
-        /* Default transaction width */
-        return width;
-}
-
-#endif /* _DMACHW_PRIV_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
deleted file mode 100644
index 7cd0aafa6f6e..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_reg.h
-*
-*  @brief   Definitions for low level DMA registers
-*
-*/
-/****************************************************************************/
-
-#ifndef _DMACHW_REG_H
-#define _DMACHW_REG_H
-
-#include <linux/types.h>
-#include <mach/csp/mm_io.h>
-
-/* Data type for 64 bit little endian register */
-typedef struct {
-        volatile uint32_t lo;   /* Lower 32 bit in little endian mode */
-        volatile uint32_t hi;   /* Upper 32 bit in little endian mode */
-} dmacHw_REG64_t;
-
-/* Data type representing DMA channel registers */
-typedef struct {
-        dmacHw_REG64_t ChannelSar;      /*  Source Address Register. 64 bits (upper 32 bits are reserved)
-                                           Address must be aligned to CTLx.SRC_TR_WIDTH.
-                                         */
-        dmacHw_REG64_t ChannelDar;      /*  Destination Address Register.64 bits (upper 32 bits are reserved)
-                                           Address must be aligned to CTLx.DST_TR_WIDTH.
-                                         */
-        dmacHw_REG64_t ChannelLlp;      /*  Link List Pointer.64 bits (upper 32 bits are reserved)
-                                           LLP contains the pointer to the next LLI for block chaining using linked lists.
-                                           If LLPis set to 0x0, then transfers using linked lists are not enabled.
-                                           Address MUST be aligned to a 32-bit boundary.
-                                         */
-        dmacHw_REG64_t ChannelCtl;      /* Control Register. 64 bits */
-        dmacHw_REG64_t ChannelSstat;    /* Source Status Register */
-        dmacHw_REG64_t ChannelDstat;    /* Destination Status Register */
-        dmacHw_REG64_t ChannelSstatAddr;        /* Source Status Address Register */
-        dmacHw_REG64_t ChannelDstatAddr;        /* Destination Status Address Register */
-        dmacHw_REG64_t ChannelConfig;   /* Channel Configuration Register */
-        dmacHw_REG64_t SrcGather;       /* Source gather register */
-        dmacHw_REG64_t DstScatter;      /* Destination scatter register */
-} dmacHw_CH_REG_t;
-
-/* Data type for RAW interrupt status registers */
-typedef struct {
-        dmacHw_REG64_t RawTfr;  /* Raw Status for IntTfr Interrupt */
-        dmacHw_REG64_t RawBlock;        /* Raw Status for IntBlock Interrupt */
-        dmacHw_REG64_t RawSrcTran;      /* Raw Status for IntSrcTran Interrupt */
-        dmacHw_REG64_t RawDstTran;      /* Raw Status for IntDstTran Interrupt */
-        dmacHw_REG64_t RawErr;  /* Raw Status for IntErr Interrupt */
-} dmacHw_INT_RAW_t;
-
-/* Data type for interrupt status registers */
-typedef struct {
-        dmacHw_REG64_t StatusTfr;       /* Status for IntTfr Interrupt */
-        dmacHw_REG64_t StatusBlock;     /* Status for IntBlock Interrupt */
-        dmacHw_REG64_t StatusSrcTran;   /* Status for IntSrcTran Interrupt */
-        dmacHw_REG64_t StatusDstTran;   /* Status for IntDstTran Interrupt */
-        dmacHw_REG64_t StatusErr;       /* Status for IntErr Interrupt */
-} dmacHw_INT_STATUS_t;
-
-/* Data type for interrupt mask registers*/
-typedef struct {
-        dmacHw_REG64_t MaskTfr; /* Mask for IntTfr Interrupt */
-        dmacHw_REG64_t MaskBlock;       /* Mask for IntBlock Interrupt */
-        dmacHw_REG64_t MaskSrcTran;     /* Mask for IntSrcTran Interrupt */
-        dmacHw_REG64_t MaskDstTran;     /* Mask for IntDstTran Interrupt */
-        dmacHw_REG64_t MaskErr; /* Mask for IntErr Interrupt */
-} dmacHw_INT_MASK_t;
-
-/* Data type for interrupt clear registers */
-typedef struct {
-        dmacHw_REG64_t ClearTfr;        /* Clear for IntTfr Interrupt */
-        dmacHw_REG64_t ClearBlock;      /* Clear for IntBlock Interrupt */
-        dmacHw_REG64_t ClearSrcTran;    /* Clear for IntSrcTran Interrupt */
-        dmacHw_REG64_t ClearDstTran;    /* Clear for IntDstTran Interrupt */
-        dmacHw_REG64_t ClearErr;        /* Clear for IntErr Interrupt */
-        dmacHw_REG64_t StatusInt;       /* Status for each interrupt type */
-} dmacHw_INT_CLEAR_t;
-
-/* Data type for software handshaking registers */
-typedef struct {
-        dmacHw_REG64_t ReqSrcReg;       /* Source Software Transaction Request Register */
-        dmacHw_REG64_t ReqDstReg;       /* Destination Software Transaction Request Register */
-        dmacHw_REG64_t SglReqSrcReg;    /* Single Source Transaction Request Register */
-        dmacHw_REG64_t SglReqDstReg;    /* Single Destination Transaction Request Register */
-        dmacHw_REG64_t LstSrcReg;       /* Last Source Transaction Request Register */
-        dmacHw_REG64_t LstDstReg;       /* Last Destination Transaction Request Register */
-} dmacHw_SW_HANDSHAKE_t;
-
-/* Data type for misc. registers */
-typedef struct {
-        dmacHw_REG64_t DmaCfgReg;       /* DMA Configuration Register */
-        dmacHw_REG64_t ChEnReg; /* DMA Channel Enable Register */
-        dmacHw_REG64_t DmaIdReg;        /* DMA ID Register */
-        dmacHw_REG64_t DmaTestReg;      /* DMA Test Register */
-        dmacHw_REG64_t Reserved0;       /* Reserved */
-        dmacHw_REG64_t Reserved1;       /* Reserved */
-        dmacHw_REG64_t CompParm6;       /* Component Parameter 6 */
-        dmacHw_REG64_t CompParm5;       /* Component Parameter 5 */
-        dmacHw_REG64_t CompParm4;       /* Component Parameter 4 */
-        dmacHw_REG64_t CompParm3;       /* Component Parameter 3 */
-        dmacHw_REG64_t CompParm2;       /* Component Parameter 2 */
-        dmacHw_REG64_t CompParm1;       /* Component Parameter 1 */
-        dmacHw_REG64_t CompId;  /* Compoent ID */
-} dmacHw_MISC_t;
-
-/* Base registers */
-#define dmacHw_0_MODULE_BASE_ADDR        (char __iomem*) MM_IO_BASE_DMA0        /* DMAC 0 module's base address */
-#define dmacHw_1_MODULE_BASE_ADDR        (char __iomem*) MM_IO_BASE_DMA1        /* DMAC 1 module's base address */
-
-extern uint32_t dmaChannelCount_0;
-extern uint32_t dmaChannelCount_1;
-
-/* Define channel specific registers */
-#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t __iomem*) ((char __iomem*)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
-
-/* Raw interrupt status registers */
-#define dmacHw_REG_INT_RAW_BASE(module)         ((char __iomem *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
-#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
-#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
-#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
-#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
-#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
-
-/* Interrupt status registers */
-#define dmacHw_REG_INT_STAT_BASE(module)        ((char __iomem*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
-#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
-#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
-#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
-#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
-#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
-
-/* Interrupt status registers */
-#define dmacHw_REG_INT_MASK_BASE(module)        ((char __iomem*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
-#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
-#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
-#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
-#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
-#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
-
-/* Interrupt clear registers */
-#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char __iomem*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
-#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
-#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
-#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
-#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
-#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
-#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
-
-/* Software handshaking registers */
-#define dmacHw_REG_SW_HS_BASE(module)           ((char __iomem*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
-#define dmacHw_REG_SW_HS_SRC_REQ(module)        (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_REQ(module)        (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
-
-/* Miscellaneous registers */
-#define dmacHw_REG_MISC_BASE(module)            ((char __iomem*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
-#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
-#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
-#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
-#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
-#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
-#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
-#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
-#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
-#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
-#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
-#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
-#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
-#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
-#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
-
-/* Channel control registers */
-#define dmacHw_REG_SAR(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
-#define dmacHw_REG_DAR(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo)
-#define dmacHw_REG_LLP(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo)
-
-#define dmacHw_REG_CTL_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo)
-#define dmacHw_REG_CTL_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi)
-
-#define dmacHw_REG_SSTAT(module, chan)          (dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo)
-#define dmacHw_REG_DSTAT(module, chan)          (dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo)
-#define dmacHw_REG_SSTATAR(module, chan)        (dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo)
-#define dmacHw_REG_DSTATAR(module, chan)        (dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo)
-
-#define dmacHw_REG_CFG_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo)
-#define dmacHw_REG_CFG_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi)
-
-#define dmacHw_REG_SGR_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo)
-#define dmacHw_REG_SGR_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi)
-
-#define dmacHw_REG_DSR_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo)
-#define dmacHw_REG_DSR_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi)
-
-#define INT_STATUS_MASK(channel)                (0x00000001 << (channel))
-#define CHANNEL_BUSY(mod, channel)              (dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel)))
-
-/* Bit mask for REG_DMACx_CTL_LO */
-
-#define dmacHw_REG_CTL_INT_EN                       0x00000001  /* Channel interrupt enable */
-
-#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK            0x0000000E  /* Destination transaction width mask */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT           1
-#define dmacHw_REG_CTL_DST_TR_WIDTH_8               0x00000000  /* Destination transaction width 8 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_16              0x00000002  /* Destination transaction width 16 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_32              0x00000004  /* Destination transaction width 32 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_64              0x00000006  /* Destination transaction width 64 bit */
-
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK            0x00000070  /* Source transaction width mask */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT           4
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_8               0x00000000  /* Source transaction width 8 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_16              0x00000010  /* Source transaction width 16 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_32              0x00000020  /* Source transaction width 32 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_64              0x00000030  /* Source transaction width 64 bit */
-
-#define dmacHw_REG_CTL_DS_ENABLE                    0x00040000  /* Destination scatter enable */
-#define dmacHw_REG_CTL_SG_ENABLE                    0x00020000  /* Source gather enable */
-
-#define dmacHw_REG_CTL_DINC_MASK                    0x00000180  /* Destination address inc/dec mask */
-#define dmacHw_REG_CTL_DINC_INC                     0x00000000  /* Destination address increment */
-#define dmacHw_REG_CTL_DINC_DEC                     0x00000080  /* Destination address decrement */
-#define dmacHw_REG_CTL_DINC_NC                      0x00000100  /* Destination address no change */
-
-#define dmacHw_REG_CTL_SINC_MASK                    0x00000600  /* Source address inc/dec mask */
-#define dmacHw_REG_CTL_SINC_INC                     0x00000000  /* Source address increment */
-#define dmacHw_REG_CTL_SINC_DEC                     0x00000200  /* Source address decrement */
-#define dmacHw_REG_CTL_SINC_NC                      0x00000400  /* Source address no change */
-
-#define dmacHw_REG_CTL_DST_MSIZE_MASK               0x00003800  /* Destination burst transaction length */
-#define dmacHw_REG_CTL_DST_MSIZE_0                  0x00000000  /* No Destination burst */
-#define dmacHw_REG_CTL_DST_MSIZE_4                  0x00000800  /* Destination burst transaction length 4 */
-#define dmacHw_REG_CTL_DST_MSIZE_8                  0x00001000  /* Destination burst transaction length 8 */
-#define dmacHw_REG_CTL_DST_MSIZE_16                 0x00001800  /* Destination burst transaction length 16 */
-
-#define dmacHw_REG_CTL_SRC_MSIZE_MASK               0x0001C000  /* Source burst transaction length */
-#define dmacHw_REG_CTL_SRC_MSIZE_0                  0x00000000  /* No Source burst */
-#define dmacHw_REG_CTL_SRC_MSIZE_4                  0x00004000  /* Source burst transaction length 4 */
-#define dmacHw_REG_CTL_SRC_MSIZE_8                  0x00008000  /* Source burst transaction length 8 */
-#define dmacHw_REG_CTL_SRC_MSIZE_16                 0x0000C000  /* Source burst transaction length 16 */
-
-#define dmacHw_REG_CTL_TTFC_MASK                    0x00700000  /* Transfer type and flow controller */
-#define dmacHw_REG_CTL_TTFC_MM_DMAC                 0x00000000  /* Memory to Memory with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_MP_DMAC                 0x00100000  /* Memory to Peripheral with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PM_DMAC                 0x00200000  /* Peripheral to Memory with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_DMAC                 0x00300000  /* Peripheral to Peripheral with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PM_PERI                 0x00400000  /* Peripheral to Memory with Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_SPERI                0x00500000  /* Peripheral to Peripheral with Source Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_MP_PERI                 0x00600000  /* Memory to Peripheral with Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_DPERI                0x00700000  /* Peripheral to Peripheral with Destination Peripheral as flow controller */
-
-#define dmacHw_REG_CTL_DMS_MASK                     0x01800000  /* Destination AHB master interface */
-#define dmacHw_REG_CTL_DMS_1                        0x00000000  /* Destination AHB master interface 1 */
-#define dmacHw_REG_CTL_DMS_2                        0x00800000  /* Destination AHB master interface 2 */
-
-#define dmacHw_REG_CTL_SMS_MASK                     0x06000000  /* Source AHB master interface */
-#define dmacHw_REG_CTL_SMS_1                        0x00000000  /* Source AHB master interface 1 */
-#define dmacHw_REG_CTL_SMS_2                        0x02000000  /* Source AHB master interface 2 */
-
-#define dmacHw_REG_CTL_LLP_DST_EN                   0x08000000  /* Block chaining enable for destination side */
-#define dmacHw_REG_CTL_LLP_SRC_EN                   0x10000000  /* Block chaining enable for source side */
-
-/* Bit mask for REG_DMACx_CTL_HI */
-#define dmacHw_REG_CTL_BLOCK_TS_MASK                0x00000FFF  /* Block transfer size */
-#define dmacHw_REG_CTL_DONE                         0x00001000  /* Block trasnfer done */
-
-/* Bit mask for REG_DMACx_CFG_LO */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT                  5  /* Channel priority shift */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK          0x000000E0  /* Channel priority mask */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_0             0x00000000  /* Channel priority 0 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_1             0x00000020  /* Channel priority 1 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_2             0x00000040  /* Channel priority 2 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_3             0x00000060  /* Channel priority 3 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_4             0x00000080  /* Channel priority 4 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_5             0x000000A0  /* Channel priority 5 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_6             0x000000C0  /* Channel priority 6 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_7             0x000000E0  /* Channel priority 7 */
-
-#define dmacHw_REG_CFG_LO_CH_SUSPEND                0x00000100  /* Channel suspend */
-#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY             0x00000200  /* Channel FIFO empty */
-#define dmacHw_REG_CFG_LO_DST_CH_SW_HS              0x00000400  /* Destination channel SW handshaking */
-#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS              0x00000800  /* Source channel SW handshaking */
-
-#define dmacHw_REG_CFG_LO_CH_LOCK_MASK              0x00003000  /* Channel locking mask */
-#define dmacHw_REG_CFG_LO_CH_LOCK_DMA               0x00000000  /* Channel lock over the entire DMA transfer operation */
-#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK             0x00001000  /* Channel lock over the block transfer operation */
-#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS             0x00002000  /* Channel lock over the transaction */
-#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE            0x00010000  /* Channel lock enable */
-
-#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK             0x0000C000  /* Bus locking mask */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA              0x00000000  /* Bus lock over the entire DMA transfer operation */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK            0x00004000  /* Bus lock over the block transfer operation */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS            0x00008000  /* Bus lock over the transaction */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE           0x00020000  /* Bus lock enable */
-
-#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW       0x00040000  /* Destination channel handshaking signal polarity low */
-#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW       0x00080000  /* Source channel handshaking signal polarity low */
-
-#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK   0x3FF00000  /* Maximum AMBA burst length */
-
-#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC           0x40000000  /* Source address auto reload */
-#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST           0x80000000  /* Destination address auto reload */
-
-/* Bit mask for REG_DMACx_CFG_HI */
-#define dmacHw_REG_CFG_HI_FC_DST_READY              0x00000001  /* Source transaction request is serviced when destination is ready */
-#define dmacHw_REG_CFG_HI_FIFO_ENOUGH               0x00000002  /* Initiate burst transaction when enough data in available in FIFO */
-
-#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK            0x0000001C  /* AHB protection mask */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_1               0x00000004  /* AHB protection 1 */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_2               0x00000008  /* AHB protection 2 */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_3               0x00000010  /* AHB protection 3 */
-
-#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT           0x00000020  /* Destination status update enable */
-#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT           0x00000040  /* Source status update enable */
-
-#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK        0x00000780  /* Source peripheral hardware interface mask */
-#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK        0x00007800  /* Destination peripheral hardware interface mask */
-
-/* DMA Configuration Parameters */
-#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS          0x00000700  /* Number of channels */
-#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE         0x00001800  /* Number of master interface */
-#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE          0x0000000f  /* Maximum brust size */
-#define dmacHw_REG_COMP_PARAM_DATA_WIDTH            0x00006000  /* Data transfer width */
-
-/* Define GET/SET macros to program the registers */
-#define dmacHw_SET_SAR(module, channel, addr)          (dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_DAR(module, channel, addr)          (dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_LLP(module, channel, ptr)           (dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr))
-
-#define dmacHw_GET_SSTAT(module, channel)              (dmacHw_REG_SSTAT((module), (channel)))
-#define dmacHw_GET_DSTAT(module, channel)              (dmacHw_REG_DSTAT((module), (channel)))
-
-#define dmacHw_SET_SSTATAR(module, channel, addr)      (dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_DSTATAR(module, channel, addr)      (dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr))
-
-#define dmacHw_SET_CONTROL_LO(module, channel, ctl)    (dmacHw_REG_CTL_LO((module), (channel)) |= (ctl))
-#define dmacHw_RESET_CONTROL_LO(module, channel)       (dmacHw_REG_CTL_LO((module), (channel)) = 0)
-#define dmacHw_GET_CONTROL_LO(module, channel)         (dmacHw_REG_CTL_LO((module), (channel)))
-
-#define dmacHw_SET_CONTROL_HI(module, channel, ctl)    (dmacHw_REG_CTL_HI((module), (channel)) |= (ctl))
-#define dmacHw_RESET_CONTROL_HI(module, channel)       (dmacHw_REG_CTL_HI((module), (channel)) = 0)
-#define dmacHw_GET_CONTROL_HI(module, channel)         (dmacHw_REG_CTL_HI((module), (channel)))
-
-#define dmacHw_GET_BLOCK_SIZE(module, channel)         (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK)
-#define dmacHw_DMA_COMPLETE(module, channel)           (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE)
-
-#define dmacHw_SET_CONFIG_LO(module, channel, cfg)     (dmacHw_REG_CFG_LO((module), (channel)) |= (cfg))
-#define dmacHw_RESET_CONFIG_LO(module, channel)        (dmacHw_REG_CFG_LO((module), (channel)) = 0)
-#define dmacHw_GET_CONFIG_LO(module, channel)          (dmacHw_REG_CFG_LO((module), (channel)))
-#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len)    (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK))
-#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio))
-#define dmacHw_SET_AHB_HPROT(module, channel, protect)  (dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect))
-
-#define dmacHw_SET_CONFIG_HI(module, channel, cfg)      (dmacHw_REG_CFG_HI((module), (channel)) |= (cfg))
-#define dmacHw_RESET_CONFIG_HI(module, channel)         (dmacHw_REG_CFG_HI((module), (channel)) = 0)
-#define dmacHw_GET_CONFIG_HI(module, channel)           (dmacHw_REG_CFG_HI((module), (channel)))
-#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK))
-#define dmacHw_SRC_PERI_INTF(intf)                      (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)
-#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK))
-#define dmacHw_DST_PERI_INTF(intf)                      (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)
-
-#define dmacHw_DMA_START(module, channel)              (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
-#define dmacHw_DMA_STOP(module, channel)               (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_DMA_ENABLE(module)                      (dmacHw_REG_MISC_CFG((module)) = 1)
-#define dmacHw_DMA_DISABLE(module)                     (dmacHw_REG_MISC_CFG((module)) = 0)
-
-#define dmacHw_TRAN_INT_ENABLE(module, channel)        (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
-#define dmacHw_BLOCK_INT_ENABLE(module, channel)       (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
-#define dmacHw_ERROR_INT_ENABLE(module, channel)       (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
-
-#define dmacHw_TRAN_INT_DISABLE(module, channel)       (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_BLOCK_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_ERROR_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_STRAN_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_DTRAN_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8)))
-
-#define dmacHw_TRAN_INT_CLEAR(module, channel)         (dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel)))
-#define dmacHw_BLOCK_INT_CLEAR(module, channel)        (dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel)))
-#define dmacHw_ERROR_INT_CLEAR(module, channel)        (dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel)))
-
-#define dmacHw_GET_NUM_CHANNEL(module)                 (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1)
-#define dmacHw_GET_NUM_INTERFACE(module)               (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1)
-#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel)     ((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE)
-#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13)
-
-#endif /* _DMACHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
deleted file mode 100644
index 27f59dd27792..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_HW_CFG_H
-#define CSP_HW_CFG_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <mach/cfg_global.h>
-#include <mach/csp/cap_inline.h>
-
-#if defined(__KERNEL__)
-#include <mach/memory_settings.h>
-#else
-#include <hw_cfg.h>
-#endif
-
-/* Some items that can be defined externally, but will be set to default values */
-/* if they are not defined. */
-/*      HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE   Default undefined and SS is enabled. */
-/*      HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
-/*      HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
-/*      HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values [400,533,667,800] */
-/*      HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules [8,16] */
-/*      HW_CFG_SDRAM_ADDR_BRC                Default undefined and Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */
-/*      HW_CFG_SDRAM_CLK_ASYNC               Default undefined and DDR clock is synchronous with AXI BUS clock. Define for ASYNC mode. */
-
-#if defined(CFG_GLOBAL_CHIP)
-  #if (CFG_GLOBAL_CHIP == FPGA11107)
-     #define HW_CFG_BUS_CLK_HZ            5000000
-     #define HW_CFG_DDR_CTLR_CLK_HZ      10000000
-     #define HW_CFG_DDR_PHY_OMIT
-     #define HW_CFG_UART_CLK_HZ           7500000
-  #else
-     #define HW_CFG_PLL_VCO_HZ           2000000000
-     #define HW_CFG_PLL2_VCO_HZ          1800000000
-     #define HW_CFG_ARM_CLK_HZ            CAP_HW_CFG_ARM_CLK_HZ
-     #define HW_CFG_BUS_CLK_HZ            166666666
-     #define HW_CFG_DDR_CTLR_CLK_HZ       333333333
-     #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
-     #define HW_CFG_UART_CLK_HZ           142857142
-     #define HW_CFG_VPM_CLK_HZ            CAP_HW_CFG_VPM_CLK_HZ
-  #endif
-#else
-   #define HW_CFG_PLL_VCO_HZ           1800000000
-   #define HW_CFG_PLL2_VCO_HZ          1800000000
-   #define HW_CFG_ARM_CLK_HZ            450000000
-   #define HW_CFG_BUS_CLK_HZ            150000000
-   #define HW_CFG_DDR_CTLR_CLK_HZ       300000000
-   #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
-   #define HW_CFG_UART_CLK_HZ           150000000
-   #define HW_CFG_VPM_CLK_HZ            300000000
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-
-#endif /* CSP_HW_CFG_H */
-
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
deleted file mode 100644
index f59db25b5632..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    intcHw_reg.h
-*
-*  @brief   platform specific interrupt controller bit assignments
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _INTCHW_REG_H
-#define _INTCHW_REG_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <linux/types.h>
-#include <mach/csp/reg.h>
-#include <mach/csp/mm_io.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-#define INTCHW_NUM_IRQ_PER_INTC   32    /* Maximum number of interrupt controllers */
-#define INTCHW_NUM_INTC           3
-
-/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
-#define INTCHW_INTC0    (MM_IO_BASE_INTC0)
-#define INTCHW_INTC1    (MM_IO_BASE_INTC1)
-#define INTCHW_SINTC    (MM_IO_BASE_SINTC)
-
-/* INTC0 - interrupt controller 0 */
-#define INTCHW_INTC0_PIF_BITNUM           31    /* Peripheral interface interrupt */
-#define INTCHW_INTC0_CLCD_BITNUM          30    /* LCD Controller interrupt */
-#define INTCHW_INTC0_GE_BITNUM            29    /* Graphic engine interrupt */
-#define INTCHW_INTC0_APM_BITNUM           28    /* Audio process module interrupt */
-#define INTCHW_INTC0_ESW_BITNUM           27    /* Ethernet switch interrupt */
-#define INTCHW_INTC0_SPIH_BITNUM          26    /* SPI host interrupt */
-#define INTCHW_INTC0_TIMER3_BITNUM        25    /* Timer3 interrupt */
-#define INTCHW_INTC0_TIMER2_BITNUM        24    /* Timer2 interrupt */
-#define INTCHW_INTC0_TIMER1_BITNUM        23    /* Timer1 interrupt */
-#define INTCHW_INTC0_TIMER0_BITNUM        22    /* Timer0 interrupt */
-#define INTCHW_INTC0_SDIOH1_BITNUM        21    /* SDIO1 host interrupt */
-#define INTCHW_INTC0_SDIOH0_BITNUM        20    /* SDIO0 host interrupt */
-#define INTCHW_INTC0_USBD_BITNUM          19    /* USB device interrupt */
-#define INTCHW_INTC0_USBH1_BITNUM         18    /* USB1 host interrupt */
-#define INTCHW_INTC0_USBHD2_BITNUM        17    /* USB host2/device2 interrupt */
-#define INTCHW_INTC0_VPM_BITNUM           16    /* Voice process module interrupt */
-#define INTCHW_INTC0_DMA1C7_BITNUM        15    /* DMA1 channel 7 interrupt */
-#define INTCHW_INTC0_DMA1C6_BITNUM        14    /* DMA1 channel 6 interrupt */
-#define INTCHW_INTC0_DMA1C5_BITNUM        13    /* DMA1 channel 5 interrupt */
-#define INTCHW_INTC0_DMA1C4_BITNUM        12    /* DMA1 channel 4 interrupt */
-#define INTCHW_INTC0_DMA1C3_BITNUM        11    /* DMA1 channel 3 interrupt */
-#define INTCHW_INTC0_DMA1C2_BITNUM        10    /* DMA1 channel 2 interrupt */
-#define INTCHW_INTC0_DMA1C1_BITNUM         9    /* DMA1 channel 1 interrupt */
-#define INTCHW_INTC0_DMA1C0_BITNUM         8    /* DMA1 channel 0 interrupt */
-#define INTCHW_INTC0_DMA0C7_BITNUM         7    /* DMA0 channel 7 interrupt */
-#define INTCHW_INTC0_DMA0C6_BITNUM         6    /* DMA0 channel 6 interrupt */
-#define INTCHW_INTC0_DMA0C5_BITNUM         5    /* DMA0 channel 5 interrupt */
-#define INTCHW_INTC0_DMA0C4_BITNUM         4    /* DMA0 channel 4 interrupt */
-#define INTCHW_INTC0_DMA0C3_BITNUM         3    /* DMA0 channel 3 interrupt */
-#define INTCHW_INTC0_DMA0C2_BITNUM         2    /* DMA0 channel 2 interrupt */
-#define INTCHW_INTC0_DMA0C1_BITNUM         1    /* DMA0 channel 1 interrupt */
-#define INTCHW_INTC0_DMA0C0_BITNUM         0    /* DMA0 channel 0 interrupt */
-
-#define INTCHW_INTC0_PIF                  (1<<INTCHW_INTC0_PIF_BITNUM)
-#define INTCHW_INTC0_CLCD                 (1<<INTCHW_INTC0_CLCD_BITNUM)
-#define INTCHW_INTC0_GE                   (1<<INTCHW_INTC0_GE_BITNUM)
-#define INTCHW_INTC0_APM                  (1<<INTCHW_INTC0_APM_BITNUM)
-#define INTCHW_INTC0_ESW                  (1<<INTCHW_INTC0_ESW_BITNUM)
-#define INTCHW_INTC0_SPIH                 (1<<INTCHW_INTC0_SPIH_BITNUM)
-#define INTCHW_INTC0_TIMER3               (1<<INTCHW_INTC0_TIMER3_BITNUM)
-#define INTCHW_INTC0_TIMER2               (1<<INTCHW_INTC0_TIMER2_BITNUM)
-#define INTCHW_INTC0_TIMER1               (1<<INTCHW_INTC0_TIMER1_BITNUM)
-#define INTCHW_INTC0_TIMER0               (1<<INTCHW_INTC0_TIMER0_BITNUM)
-#define INTCHW_INTC0_SDIOH1               (1<<INTCHW_INTC0_SDIOH1_BITNUM)
-#define INTCHW_INTC0_SDIOH0               (1<<INTCHW_INTC0_SDIOH0_BITNUM)
-#define INTCHW_INTC0_USBD                 (1<<INTCHW_INTC0_USBD_BITNUM)
-#define INTCHW_INTC0_USBH1                (1<<INTCHW_INTC0_USBH1_BITNUM)
-#define INTCHW_INTC0_USBHD2               (1<<INTCHW_INTC0_USBHD2_BITNUM)
-#define INTCHW_INTC0_VPM                  (1<<INTCHW_INTC0_VPM_BITNUM)
-#define INTCHW_INTC0_DMA1C7               (1<<INTCHW_INTC0_DMA1C7_BITNUM)
-#define INTCHW_INTC0_DMA1C6               (1<<INTCHW_INTC0_DMA1C6_BITNUM)
-#define INTCHW_INTC0_DMA1C5               (1<<INTCHW_INTC0_DMA1C5_BITNUM)
-#define INTCHW_INTC0_DMA1C4               (1<<INTCHW_INTC0_DMA1C4_BITNUM)
-#define INTCHW_INTC0_DMA1C3               (1<<INTCHW_INTC0_DMA1C3_BITNUM)
-#define INTCHW_INTC0_DMA1C2               (1<<INTCHW_INTC0_DMA1C2_BITNUM)
-#define INTCHW_INTC0_DMA1C1               (1<<INTCHW_INTC0_DMA1C1_BITNUM)
-#define INTCHW_INTC0_DMA1C0               (1<<INTCHW_INTC0_DMA1C0_BITNUM)
-#define INTCHW_INTC0_DMA0C7               (1<<INTCHW_INTC0_DMA0C7_BITNUM)
-#define INTCHW_INTC0_DMA0C6               (1<<INTCHW_INTC0_DMA0C6_BITNUM)
-#define INTCHW_INTC0_DMA0C5               (1<<INTCHW_INTC0_DMA0C5_BITNUM)
-#define INTCHW_INTC0_DMA0C4               (1<<INTCHW_INTC0_DMA0C4_BITNUM)
-#define INTCHW_INTC0_DMA0C3               (1<<INTCHW_INTC0_DMA0C3_BITNUM)
-#define INTCHW_INTC0_DMA0C2               (1<<INTCHW_INTC0_DMA0C2_BITNUM)
-#define INTCHW_INTC0_DMA0C1               (1<<INTCHW_INTC0_DMA0C1_BITNUM)
-#define INTCHW_INTC0_DMA0C0               (1<<INTCHW_INTC0_DMA0C0_BITNUM)
-
-/* INTC1 - interrupt controller 1 */
-#define INTCHW_INTC1_DDRVPMP_BITNUM       27    /* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRVPMT_BITNUM       26    /* DDR and VPM HW phase align timeout interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRP_BITNUM          26    /* DDR and PLL clock phase relationship interrupt (For A0 only)) */
-#define INTCHW_INTC1_RTC2_BITNUM          25    /* Real time clock tamper interrupt */
-#define INTCHW_INTC1_VDEC_BITNUM          24    /* Hantro Video Decoder interrupt */
-/* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */
-#define INTCHW_INTC1_SPUM_BITNUM          23    /* Secure process module interrupt */
-#define INTCHW_INTC1_RTC1_BITNUM          22    /* Real time clock one-shot interrupt */
-#define INTCHW_INTC1_RTC0_BITNUM          21    /* Real time clock periodic interrupt */
-#define INTCHW_INTC1_RNG_BITNUM           20    /* Random number generator interrupt */
-#define INTCHW_INTC1_FMPU_BITNUM          19    /* Flash memory parition unit interrupt */
-#define INTCHW_INTC1_VMPU_BITNUM          18    /* VRAM memory partition interrupt */
-#define INTCHW_INTC1_DMPU_BITNUM          17    /* DDR2 memory partition interrupt */
-#define INTCHW_INTC1_KEYC_BITNUM          16    /* Key pad controller interrupt */
-#define INTCHW_INTC1_TSC_BITNUM           15    /* Touch screen controller interrupt */
-#define INTCHW_INTC1_UART0_BITNUM         14    /* UART 0 */
-#define INTCHW_INTC1_WDOG_BITNUM          13    /* Watchdog timer interrupt */
-
-#define INTCHW_INTC1_UART1_BITNUM         12    /* UART 1 */
-#define INTCHW_INTC1_PMUIRQ_BITNUM        11    /* ARM performance monitor interrupt */
-#define INTCHW_INTC1_COMMRX_BITNUM        10    /* ARM DDC receive interrupt */
-#define INTCHW_INTC1_COMMTX_BITNUM         9    /* ARM DDC transmit interrupt */
-#define INTCHW_INTC1_FLASHC_BITNUM         8    /* Flash controller interrupt */
-#define INTCHW_INTC1_GPHY_BITNUM           7    /* Gigabit Phy interrupt */
-#define INTCHW_INTC1_SPIS_BITNUM           6    /* SPI slave interrupt */
-#define INTCHW_INTC1_I2CS_BITNUM           5    /* I2C slave interrupt */
-#define INTCHW_INTC1_I2CH_BITNUM           4    /* I2C host interrupt */
-#define INTCHW_INTC1_I2S1_BITNUM           3    /* I2S1 interrupt */
-#define INTCHW_INTC1_I2S0_BITNUM           2    /* I2S0 interrupt */
-#define INTCHW_INTC1_GPIO1_BITNUM          1    /* GPIO bit 64//32 combined interrupt */
-#define INTCHW_INTC1_GPIO0_BITNUM          0    /* GPIO bit 31//0 combined interrupt */
-
-#define INTCHW_INTC1_DDRVPMT              (1<<INTCHW_INTC1_DDRVPMT_BITNUM)
-#define INTCHW_INTC1_DDRVPMP              (1<<INTCHW_INTC1_DDRVPMP_BITNUM)
-#define INTCHW_INTC1_DDRP                 (1<<INTCHW_INTC1_DDRP_BITNUM)
-#define INTCHW_INTC1_VDEC                 (1<<INTCHW_INTC1_VDEC_BITNUM)
-#define INTCHW_INTC1_SPUM                 (1<<INTCHW_INTC1_SPUM_BITNUM)
-#define INTCHW_INTC1_RTC2                 (1<<INTCHW_INTC1_RTC2_BITNUM)
-#define INTCHW_INTC1_RTC1                 (1<<INTCHW_INTC1_RTC1_BITNUM)
-#define INTCHW_INTC1_RTC0                 (1<<INTCHW_INTC1_RTC0_BITNUM)
-#define INTCHW_INTC1_RNG                  (1<<INTCHW_INTC1_RNG_BITNUM)
-#define INTCHW_INTC1_FMPU                 (1<<INTCHW_INTC1_FMPU_BITNUM)
-#define INTCHW_INTC1_IMPU                 (1<<INTCHW_INTC1_IMPU_BITNUM)
-#define INTCHW_INTC1_DMPU                 (1<<INTCHW_INTC1_DMPU_BITNUM)
-#define INTCHW_INTC1_KEYC                 (1<<INTCHW_INTC1_KEYC_BITNUM)
-#define INTCHW_INTC1_TSC                  (1<<INTCHW_INTC1_TSC_BITNUM)
-#define INTCHW_INTC1_UART0                (1<<INTCHW_INTC1_UART0_BITNUM)
-#define INTCHW_INTC1_WDOG                 (1<<INTCHW_INTC1_WDOG_BITNUM)
-#define INTCHW_INTC1_UART1                (1<<INTCHW_INTC1_UART1_BITNUM)
-#define INTCHW_INTC1_PMUIRQ               (1<<INTCHW_INTC1_PMUIRQ_BITNUM)
-#define INTCHW_INTC1_COMMRX               (1<<INTCHW_INTC1_COMMRX_BITNUM)
-#define INTCHW_INTC1_COMMTX               (1<<INTCHW_INTC1_COMMTX_BITNUM)
-#define INTCHW_INTC1_FLASHC               (1<<INTCHW_INTC1_FLASHC_BITNUM)
-#define INTCHW_INTC1_GPHY                 (1<<INTCHW_INTC1_GPHY_BITNUM)
-#define INTCHW_INTC1_SPIS                 (1<<INTCHW_INTC1_SPIS_BITNUM)
-#define INTCHW_INTC1_I2CS                 (1<<INTCHW_INTC1_I2CS_BITNUM)
-#define INTCHW_INTC1_I2CH                 (1<<INTCHW_INTC1_I2CH_BITNUM)
-#define INTCHW_INTC1_I2S1                 (1<<INTCHW_INTC1_I2S1_BITNUM)
-#define INTCHW_INTC1_I2S0                 (1<<INTCHW_INTC1_I2S0_BITNUM)
-#define INTCHW_INTC1_GPIO1                (1<<INTCHW_INTC1_GPIO1_BITNUM)
-#define INTCHW_INTC1_GPIO0                (1<<INTCHW_INTC1_GPIO0_BITNUM)
-
-/* SINTC secure int controller */
-#define INTCHW_SINTC_RTC2_BITNUM          15    /* Real time clock tamper interrupt */
-#define INTCHW_SINTC_TIMER3_BITNUM        14    /* Secure timer3 interrupt */
-#define INTCHW_SINTC_TIMER2_BITNUM        13    /* Secure timer2 interrupt */
-#define INTCHW_SINTC_TIMER1_BITNUM        12    /* Secure timer1 interrupt */
-#define INTCHW_SINTC_TIMER0_BITNUM        11    /* Secure timer0 interrupt */
-#define INTCHW_SINTC_SPUM_BITNUM          10    /* Secure process module interrupt */
-#define INTCHW_SINTC_RTC1_BITNUM           9    /* Real time clock one-shot interrupt */
-#define INTCHW_SINTC_RTC0_BITNUM           8    /* Real time clock periodic interrupt */
-#define INTCHW_SINTC_RNG_BITNUM            7    /* Random number generator interrupt */
-#define INTCHW_SINTC_FMPU_BITNUM           6    /* Flash memory parition unit interrupt */
-#define INTCHW_SINTC_VMPU_BITNUM           5    /* VRAM memory partition interrupt */
-#define INTCHW_SINTC_DMPU_BITNUM           4    /* DDR2 memory partition interrupt */
-#define INTCHW_SINTC_KEYC_BITNUM           3    /* Key pad controller interrupt */
-#define INTCHW_SINTC_TSC_BITNUM            2    /* Touch screen controller interrupt */
-#define INTCHW_SINTC_UART0_BITNUM          1    /* UART0 interrupt */
-#define INTCHW_SINTC_WDOG_BITNUM           0    /* Watchdog timer interrupt */
-
-#define INTCHW_SINTC_TIMER3               (1<<INTCHW_SINTC_TIMER3_BITNUM)
-#define INTCHW_SINTC_TIMER2               (1<<INTCHW_SINTC_TIMER2_BITNUM)
-#define INTCHW_SINTC_TIMER1               (1<<INTCHW_SINTC_TIMER1_BITNUM)
-#define INTCHW_SINTC_TIMER0               (1<<INTCHW_SINTC_TIMER0_BITNUM)
-#define INTCHW_SINTC_SPUM                 (1<<INTCHW_SINTC_SPUM_BITNUM)
-#define INTCHW_SINTC_RTC2                 (1<<INTCHW_SINTC_RTC2_BITNUM)
-#define INTCHW_SINTC_RTC1                 (1<<INTCHW_SINTC_RTC1_BITNUM)
-#define INTCHW_SINTC_RTC0                 (1<<INTCHW_SINTC_RTC0_BITNUM)
-#define INTCHW_SINTC_RNG                  (1<<INTCHW_SINTC_RNG_BITNUM)
-#define INTCHW_SINTC_FMPU                 (1<<INTCHW_SINTC_FMPU_BITNUM)
-#define INTCHW_SINTC_IMPU                 (1<<INTCHW_SINTC_IMPU_BITNUM)
-#define INTCHW_SINTC_DMPU                 (1<<INTCHW_SINTC_DMPU_BITNUM)
-#define INTCHW_SINTC_KEYC                 (1<<INTCHW_SINTC_KEYC_BITNUM)
-#define INTCHW_SINTC_TSC                  (1<<INTCHW_SINTC_TSC_BITNUM)
-#define INTCHW_SINTC_UART0                (1<<INTCHW_SINTC_UART0_BITNUM)
-#define INTCHW_SINTC_WDOG                 (1<<INTCHW_SINTC_WDOG_BITNUM)
-
-/* PL192 Vectored Interrupt Controller (VIC) layout */
-#define INTCHW_IRQSTATUS      0x00      /* IRQ status register */
-#define INTCHW_FIQSTATUS      0x04      /* FIQ status register */
-#define INTCHW_RAWINTR        0x08      /* Raw Interrupt Status register */
-#define INTCHW_INTSELECT      0x0c      /* Interrupt Select Register */
-#define INTCHW_INTENABLE      0x10      /* Interrupt Enable Register */
-#define INTCHW_INTENCLEAR     0x14      /* Interrupt Enable Clear Register */
-#define INTCHW_SOFTINT        0x18      /* Soft Interrupt Register */
-#define INTCHW_SOFTINTCLEAR   0x1c      /* Soft Interrupt Clear Register */
-#define INTCHW_PROTECTION     0x20      /* Protection Enable Register */
-#define INTCHW_SWPRIOMASK     0x24      /* Software Priority Mask Register */
-#define INTCHW_PRIODAISY      0x28      /* Priority Daisy Chain Register */
-#define INTCHW_VECTADDR0      0x100     /* Vector Address Registers */
-#define INTCHW_VECTPRIO0      0x200     /* Vector Priority Registers 0-31 */
-#define INTCHW_ADDRESS        0xf00     /* Vector Address Register 0-31 */
-#define INTCHW_PID            0xfe0     /* Peripheral ID Register 0-3 */
-#define INTCHW_PCELLID        0xff0     /* PrimeCell ID Register 0-3 */
-
-/* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
-/*                intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
-/*                uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */
-/*                uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-/* Clear one or more IRQ interrupts. */
-static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask)
-{
-        writel(mask, basep + INTCHW_INTENCLEAR);
-}
-
-/* Enables one or more IRQ interrupts. */
-static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask)
-{
-        writel(mask, basep + INTCHW_INTENABLE);
-}
-
-#endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
deleted file mode 100644
index d571962f2904..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    mm_addr.h
-*
-*  @brief   Memory Map address definitions
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _MM_ADDR_H
-#define _MM_ADDR_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#if !defined(CSP_SIMULATION)
-#include <mach/cfg_global.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-/*  Memory Map address definitions */
-
-#define MM_ADDR_DDR                0x00000000
-
-#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000   /* 16 MB - Reserved external memory for VPM use */
-
-#define MM_ADDR_IO_FLASHC          0x20000000
-#define MM_ADDR_IO_BROM            0x30000000
-#define MM_ADDR_IO_ARAM            0x30100000   /* 64 KB - extra cycle latency - WS switch */
-#define MM_ADDR_IO_DMA0            0x30200000
-#define MM_ADDR_IO_DMA1            0x30300000
-#define MM_ADDR_IO_ESW             0x30400000
-#define MM_ADDR_IO_CLCD            0x30500000
-#define MM_ADDR_IO_PIF             0x30580000
-#define MM_ADDR_IO_APM             0x30600000
-#define MM_ADDR_IO_SPUM            0x30700000
-#define MM_ADDR_IO_VPM_PROG        0x30800000
-#define MM_ADDR_IO_VPM_DATA        0x30A00000
-#define MM_ADDR_IO_VRAM            0x40000000   /* 64 KB  - security block in front of it */
-#define MM_ADDR_IO_CHIPC           0x80000000
-#define MM_ADDR_IO_UMI             0x80001000
-#define MM_ADDR_IO_NAND            0x80001800
-#define MM_ADDR_IO_LEDM            0x80002000
-#define MM_ADDR_IO_PWM             0x80002040
-#define MM_ADDR_IO_VINTC           0x80003000
-#define MM_ADDR_IO_GPIO0           0x80004000
-#define MM_ADDR_IO_GPIO1           0x80004800
-#define MM_ADDR_IO_I2CS            0x80005000
-#define MM_ADDR_IO_SPIS            0x80006000
-#define MM_ADDR_IO_HPM             0x80007400
-#define MM_ADDR_IO_HPM_REMAP       0x80007800
-#define MM_ADDR_IO_TZPC            0x80008000
-#define MM_ADDR_IO_MPU             0x80009000
-#define MM_ADDR_IO_SPUMP           0x8000a000
-#define MM_ADDR_IO_PKA             0x8000b000
-#define MM_ADDR_IO_RNG             0x8000c000
-#define MM_ADDR_IO_KEYC            0x8000d000
-#define MM_ADDR_IO_BBL             0x8000e000
-#define MM_ADDR_IO_OTP             0x8000f000
-#define MM_ADDR_IO_I2S0            0x80010000
-#define MM_ADDR_IO_I2S1            0x80011000
-#define MM_ADDR_IO_UARTA           0x80012000
-#define MM_ADDR_IO_UARTB           0x80013000
-#define MM_ADDR_IO_I2CH            0x80014020
-#define MM_ADDR_IO_SPIH            0x80015000
-#define MM_ADDR_IO_TSC             0x80016000
-#define MM_ADDR_IO_TMR             0x80017000
-#define MM_ADDR_IO_WATCHDOG        0x80017800
-#define MM_ADDR_IO_ETM             0x80018000
-#define MM_ADDR_IO_DDRC            0x80019000
-#define MM_ADDR_IO_SINTC           0x80100000
-#define MM_ADDR_IO_INTC0           0x80200000
-#define MM_ADDR_IO_INTC1           0x80201000
-#define MM_ADDR_IO_GE              0x80300000
-#define MM_ADDR_IO_USB_CTLR0       0x80400000
-#define MM_ADDR_IO_USB_CTLR1       0x80410000
-#define MM_ADDR_IO_USB_PHY         0x80420000
-#define MM_ADDR_IO_SDIOH0          0x80500000
-#define MM_ADDR_IO_SDIOH1          0x80600000
-#define MM_ADDR_IO_VDEC            0x80700000
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /* _MM_ADDR_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
deleted file mode 100644
index 47450c23685a..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    mm_io.h
-*
-*  @brief   Memory Map I/O definitions
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _MM_IO_H
-#define _MM_IO_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/mm_addr.h>
-
-#if !defined(CSP_SIMULATION)
-#include <mach/cfg_global.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-#if defined(CONFIG_MMU)
-
-/* This macro is referenced in <mach/io.h>
- * Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx
- * This macro is referenced in <asm/arch/io.h>
- *
- * Assume VPM address is the last x MB of memory.  For VPM, map to
- * 0xf0000000 and up.
- */
-
-#ifndef MM_IO_PHYS_TO_VIRT
-#ifdef __ASSEMBLY__
-#define MM_IO_PHYS_TO_VIRT(phys)       (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
-#else
-#define MM_IO_PHYS_TO_VIRT(phys)       (void __iomem *)(((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
-                        (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
-#endif
-#endif
-
-/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */
-
-#ifndef MM_IO_VIRT_TO_PHYS
-#ifdef __ASSEMBLY__
-#define MM_IO_VIRT_TO_PHYS(virt)       ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
-#else
-#define MM_IO_VIRT_TO_PHYS(virt)       (((unsigned long)(virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
-                        ((((unsigned long)(virt) & 0x0F000000) << 4) | ((unsigned long)(virt) & 0xFFFFFF)))
-#endif
-#endif
-
-#else
-
-#ifndef MM_IO_PHYS_TO_VIRT
-#define MM_IO_PHYS_TO_VIRT(phys)       (phys)
-#endif
-
-#ifndef MM_IO_VIRT_TO_PHYS
-#define MM_IO_VIRT_TO_PHYS(virt)       (virt)
-#endif
-
-#endif
-
-/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */
-#define MM_IO_BASE_FLASHC              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC)
-#define MM_IO_BASE_NAND                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND)
-#define MM_IO_BASE_UMI                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI)
-
-#define MM_IO_START MM_ADDR_IO_FLASHC   /* Physical beginning of IO mapped memory */
-#define MM_IO_BASE  MM_IO_BASE_FLASHC   /* Virtual beginning of IO mapped memory */
-
-#define MM_IO_BASE_BROM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM)
-#define MM_IO_BASE_ARAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM)
-#define MM_IO_BASE_DMA0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0)
-#define MM_IO_BASE_DMA1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1)
-#define MM_IO_BASE_ESW                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW)
-#define MM_IO_BASE_CLCD                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD)
-#define MM_IO_BASE_PIF                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF)
-#define MM_IO_BASE_APM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM)
-#define MM_IO_BASE_SPUM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM)
-#define MM_IO_BASE_VPM_PROG            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG)
-#define MM_IO_BASE_VPM_DATA            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA)
-
-#define MM_IO_BASE_VRAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM)
-
-#define MM_IO_BASE_CHIPC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC)
-#define MM_IO_BASE_DDRC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC)
-#define MM_IO_BASE_LEDM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM)
-#define MM_IO_BASE_PWM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM)
-#define MM_IO_BASE_VINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC)
-#define MM_IO_BASE_GPIO0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0)
-#define MM_IO_BASE_GPIO1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1)
-#define MM_IO_BASE_TMR                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR)
-#define MM_IO_BASE_WATCHDOG            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG)
-#define MM_IO_BASE_ETM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM)
-#define MM_IO_BASE_HPM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM)
-#define MM_IO_BASE_HPM_REMAP           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP)
-#define MM_IO_BASE_TZPC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC)
-#define MM_IO_BASE_MPU                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU)
-#define MM_IO_BASE_SPUMP               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP)
-#define MM_IO_BASE_PKA                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA)
-#define MM_IO_BASE_RNG                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG)
-#define MM_IO_BASE_KEYC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC)
-#define MM_IO_BASE_BBL                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL)
-#define MM_IO_BASE_OTP                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP)
-#define MM_IO_BASE_I2S0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0)
-#define MM_IO_BASE_I2S1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1)
-#define MM_IO_BASE_UARTA               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA)
-#define MM_IO_BASE_UARTB               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB)
-#define MM_IO_BASE_I2CH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH)
-#define MM_IO_BASE_SPIH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH)
-#define MM_IO_BASE_TSC                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC)
-#define MM_IO_BASE_I2CS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS)
-#define MM_IO_BASE_SPIS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS)
-#define MM_IO_BASE_SINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC)
-#define MM_IO_BASE_INTC0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0)
-#define MM_IO_BASE_INTC1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1)
-#define MM_IO_BASE_GE                  MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE)
-#define MM_IO_BASE_USB_CTLR0           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0)
-#define MM_IO_BASE_USB_CTLR1           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1)
-#define MM_IO_BASE_USB_PHY             MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY)
-#define MM_IO_BASE_SDIOH0              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0)
-#define MM_IO_BASE_SDIOH1              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1)
-#define MM_IO_BASE_VDEC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC)
-
-#define MM_IO_BASE_VPM_EXTMEM_RSVD     MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD)
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /* _MM_IO_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/reg.h b/arch/arm/mach-bcmring/include/mach/csp/reg.h
deleted file mode 100644
index d9cbdca8cd25..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/reg.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    reg.h
-*
-*  @brief   Generic register definitions used in CSP
-*/
-/****************************************************************************/
-
-#ifndef CSP_REG_H
-#define CSP_REG_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <linux/types.h>
-#include <linux/io.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-#define __REG32(x)      (*((volatile uint32_t __iomem *)(x)))
-#define __REG16(x)      (*((volatile uint16_t __iomem *)(x)))
-#define __REG8(x)       (*((volatile uint8_t __iomem *) (x)))
-
-/* Macros used to define a sequence of reserved registers. The start / end */
-/* are byte offsets in the particular register definition, with the "end" */
-/* being the offset of the next un-reserved register. E.g. if offsets */
-/* 0x10 through to 0x1f are reserved, then this reserved area could be */
-/* specified as follows. */
-/*  typedef struct */
-/*  { */
-/*      uint32_t reg1;           offset 0x00 */
-/*      uint32_t reg2;           offset 0x04 */
-/*      uint32_t reg3;           offset 0x08 */
-/*      uint32_t reg4;           offset 0x0c */
-/*      REG32_RSVD(0x10, 0x20); */
-/*      uint32_t reg5;           offset 0x20 */
-/*      ... */
-/*  } EXAMPLE_REG_t; */
-#define REG8_RSVD(start, end)   uint8_t rsvd_##start[(end - start) / sizeof(uint8_t)]
-#define REG16_RSVD(start, end)  uint16_t rsvd_##start[(end - start) / sizeof(uint16_t)]
-#define REG32_RSVD(start, end)  uint32_t rsvd_##start[(end - start) / sizeof(uint32_t)]
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */
-/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the  */
-/* flags variable to be declared locally. */
-/* e.g. */
-/*    statement1; */
-/*    { */
-/*       REG_LOCAL_IRQ_SAVE; */
-/*       <multiple statements here> */
-/*       REG_LOCAL_IRQ_RESTORE; */
-/*    } */
-/*    statement2; */
-/*  */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <mach/hardware.h>
-#include <linux/interrupt.h>
-
-#define REG_LOCAL_IRQ_SAVE      HW_DECLARE_SPINLOCK(reg32) \
-        unsigned long flags; HW_IRQ_SAVE(reg32, flags)
-
-#define REG_LOCAL_IRQ_RESTORE   HW_IRQ_RESTORE(reg32, flags)
-
-#else
-
-#define REG_LOCAL_IRQ_SAVE
-#define REG_LOCAL_IRQ_RESTORE
-
-#endif
-
-static inline void reg32_modify_and(volatile uint32_t __iomem *reg, uint32_t value)
-{
-        REG_LOCAL_IRQ_SAVE;
-        __raw_writel(__raw_readl(reg) & value, reg);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_modify_or(volatile uint32_t __iomem *reg, uint32_t value)
-{
-        REG_LOCAL_IRQ_SAVE;
-        __raw_writel(__raw_readl(reg) | value, reg);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_modify_mask(volatile uint32_t __iomem *reg, uint32_t mask,
-                                     uint32_t value)
-{
-        REG_LOCAL_IRQ_SAVE;
-        __raw_writel((__raw_readl(reg) & mask) | value, reg);
-        REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_write(volatile uint32_t __iomem *reg, uint32_t value)
-{
-        __raw_writel(value, reg);
-}
-
-#endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
deleted file mode 100644
index d15f5f3ec2d8..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw_def.h
-*
-*  @brief   Definitions for configuring/testing secure blocks
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef SECHW_DEF_H
-#define SECHW_DEF_H
-
-#include <mach/csp/mm_io.h>
-
-/* Bit mask for various secure device */
-#define secHw_BLK_MASK_CHIP_CONTROL     0x00000001
-#define secHw_BLK_MASK_KEY_SCAN         0x00000002
-#define secHw_BLK_MASK_TOUCH_SCREEN     0x00000004
-#define secHw_BLK_MASK_UART0            0x00000008
-#define secHw_BLK_MASK_UART1            0x00000010
-#define secHw_BLK_MASK_WATCHDOG         0x00000020
-#define secHw_BLK_MASK_SPUM             0x00000040
-#define secHw_BLK_MASK_DDR2             0x00000080
-#define secHw_BLK_MASK_EXT_MEM          0x00000100
-#define secHw_BLK_MASK_ESW              0x00000200
-#define secHw_BLK_MASK_SPU              0x00010000
-#define secHw_BLK_MASK_PKA              0x00020000
-#define secHw_BLK_MASK_RNG              0x00040000
-#define secHw_BLK_MASK_RTC              0x00080000
-#define secHw_BLK_MASK_OTP              0x00100000
-#define secHw_BLK_MASK_BOOT             0x00200000
-#define secHw_BLK_MASK_MPU              0x00400000
-#define secHw_BLK_MASK_TZCTRL           0x00800000
-#define secHw_BLK_MASK_INTR             0x01000000
-
-/* Trustzone register set */
-typedef struct {
-        volatile uint32_t status;       /* read only - reflects status of writes of 2 write registers */
-        volatile uint32_t setUnsecure;  /* write only. reads back as 0 */
-        volatile uint32_t setSecure;    /* write only. reads back as 0 */
-} secHw_TZREG_t;
-
-/* There are 2 register sets. The first is for the lower 16 bits, the 2nd */
-/* is for the higher 16 bits. */
-
-typedef enum {
-        secHw_IDX_LS = 0,
-        secHw_IDX_MS = 1,
-        secHw_IDX_NUM
-} secHw_IDX_e;
-
-typedef struct {
-        volatile secHw_TZREG_t reg[secHw_IDX_NUM];
-} secHw_REGS_t;
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setSecure(uint32_t mask        /*  mask of type secHw_BLK_MASK_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a non-secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setUnsecure(uint32_t mask      /*  mask of type secHw_BLK_MASK_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Get the trustzone status for all components. 1 = non-secure, 0 = secure
-*
-*/
-/****************************************************************************/
-static inline uint32_t secHw_getStatus(void);
-
-#include <mach/csp/secHw_inline.h>
-
-#endif /* SECHW_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
deleted file mode 100644
index 55d3cd4fd1e7..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw_inline.h
-*
-*  @brief   Definitions for configuring/testing secure blocks
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef SECHW_INLINE_H
-#define SECHW_INLINE_H
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setSecure(uint32_t mask        /*  mask of type secHw_BLK_MASK_XXXXXX */
-    ) {
-        secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
-
-        if (mask & 0x0000FFFF) {
-                regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
-        }
-
-        if (mask & 0xFFFF0000) {
-                regp->reg[secHw_IDX_MS].setSecure = mask >> 16;
-        }
-}
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a non-secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setUnsecure(uint32_t mask      /*  mask of type secHw_BLK_MASK_XXXXXX */
-    ) {
-        secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
-
-        if (mask & 0x0000FFFF) {
-                writel(mask & 0x0000FFFF, &regp->reg[secHw_IDX_LS].setUnsecure);
-        }
-        if (mask & 0xFFFF0000) {
-                writel(mask >> 16, &regp->reg[secHw_IDX_MS].setUnsecure);
-        }
-}
-
-/****************************************************************************/
-/**
-*  @brief  Get the trustzone status for all components. 1 = non-secure, 0 = secure
-*
-*/
-/****************************************************************************/
-static inline uint32_t secHw_getStatus(void)
-{
-        secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
-
-        return (regp->reg[1].status << 16) + regp->reg[0].status;
-}
-
-#endif /* SECHW_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h
deleted file mode 100644
index 1cc882ae60f5..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw.h
-*
-*  @brief   API definitions for low level Timer driver
-*
-*/
-/****************************************************************************/
-#ifndef _TMRHW_H
-#define _TMRHW_H
-
-#include <linux/types.h>
-
-typedef uint32_t tmrHw_ID_t;    /* Timer ID */
-typedef uint32_t tmrHw_COUNT_t; /* Timer count */
-typedef uint32_t tmrHw_INTERVAL_t;      /* Timer interval */
-typedef uint32_t tmrHw_RATE_t;  /* Timer event (count/interrupt) rate */
-
-typedef enum {
-        tmrHw_INTERRUPT_STATUS_SET,     /* Interrupted  */
-        tmrHw_INTERRUPT_STATUS_UNSET    /* No Interrupt */
-} tmrHw_INTERRUPT_STATUS_e;
-
-typedef enum {
-        tmrHw_CAPABILITY_CLOCK, /* Clock speed in HHz */
-        tmrHw_CAPABILITY_RESOLUTION     /* Timer resolution in bits */
-} tmrHw_CAPABILITY_e;
-
-/****************************************************************************/
-/**
-*  @brief   Get timer capability
-*
-*  This function returns various capabilities/attributes of a timer
-*
-*  @return  Numeric capability
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,   /*  [ IN ] Timer Id */
-                                  tmrHw_CAPABILITY_e capability /*  [ IN ] Timer capability */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer in terms of timer interrupt rate
-*
-*  This function initializes a periodic timer to generate specific number of
-*  timer interrupt per second
-*
-*  @return   On success: Effective timer frequency
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
-                                        tmrHw_RATE_t rate       /*  [ IN ] Number of timer interrupt per second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt after
-*           certain time interval
-*
-*  This function initializes a periodic timer to generate timer interrupt
-*  after every time interval in millisecond
-*
-*  @return   On success: Effective interval set in mili-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
-                                                tmrHw_INTERVAL_t msec   /*  [ IN ] Interval in mili-second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt just once
-*           after certain time interval
-*
-*  This function initializes a periodic timer to generate a single ticks after
-*  certain time interval in millisecond
-*
-*  @return   On success: Effective interval set in mili-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
-                                               tmrHw_INTERVAL_t msec    /*  [ IN ] Interval in mili-second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a timer to run as a free running timer
-*
-*  This function initializes a timer to run as a free running timer
-*
-*  @return   Timer resolution (count / sec)
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
-                                       uint32_t divider /*  [ IN ] Dividing the clock frequency */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Starts a timer
-*
-*  This function starts a preconfigured timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*/
-/****************************************************************************/
-int tmrHw_startTimer(tmrHw_ID_t timerId /*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Stops a timer
-*
-*  This function stops a running timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*/
-/****************************************************************************/
-int tmrHw_stopTimer(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Gets current timer count
-*
-*  This function returns the current timer value
-*
-*  @return  Current downcounting timer value
-*
-*/
-/****************************************************************************/
-tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Gets timer count rate
-*
-*  This function returns the number of counts per second
-*
-*  @return  Count rate
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId      /*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Enables timer interrupt
-*
-*  This function enables the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_enableInterrupt(tmrHw_ID_t timerId   /*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Disables timer interrupt
-*
-*  This function disable the timer interrupt
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_disableInterrupt(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the timer interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void tmrHw_clearInterrupt(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Gets the interrupt status
-*
-*  This function returns timer interrupt status
-*
-*  @return   Interrupt status
-*/
-/****************************************************************************/
-tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a timer causing interrupt
-*
-*  This functions returns a timer causing interrupt
-*
-*  @return  0xFFFFFFFF   : No timer causing an interrupt
-*           ! 0xFFFFFFFF : timer causing an interrupt
-*  @note
-*     tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
-*/
-/****************************************************************************/
-tmrHw_ID_t tmrHw_getInterruptSource(void);
-
-/****************************************************************************/
-/**
-*  @brief   Displays specific timer registers
-*
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void tmrHw_printDebugInfo(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
-                          int (*fpPrint) (const char *, ...)    /*  [ IN ] Print callback function */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_udelay(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
-                  unsigned long usecs   /*  [ IN ] usec to delay */
-) __attribute__ ((section(".aramtext")));
-
-#endif /* _TMRHW_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
deleted file mode 100644
index 3080ac7239a1..000000000000
--- a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw_reg.h
-*
-*  @brief   Definitions for low level Timer registers
-*
-*/
-/****************************************************************************/
-#ifndef _TMRHW_REG_H
-#define _TMRHW_REG_H
-
-#include <mach/csp/mm_io.h>
-#include <mach/csp/hw_cfg.h>
-/* Base address */
-#define tmrHw_MODULE_BASE_ADDR          MM_IO_BASE_TMR
-
-/*
-This platform has four different timers running at different clock speed
-
-Timer one   (Timer ID 0) runs at  25 MHz
-Timer two   (Timer ID 1) runs at  25 MHz
-Timer three (Timer ID 2) runs at 150 MHz
-Timer four  (Timer ID 3) runs at 150 MHz
-*/
-#define tmrHw_LOW_FREQUENCY_MHZ         25      /* Always 25MHz from XTAL */
-#define tmrHw_LOW_FREQUENCY_HZ          25000000
-
-#if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107)
-#define tmrHw_HIGH_FREQUENCY_MHZ        150     /* Always 150MHz for FPGA */
-#define tmrHw_HIGH_FREQUENCY_HZ         150000000
-#else
-#define tmrHw_HIGH_FREQUENCY_HZ         HW_CFG_BUS_CLK_HZ
-#define tmrHw_HIGH_FREQUENCY_MHZ        (HW_CFG_BUS_CLK_HZ / 1000000)
-#endif
-
-#define tmrHw_LOW_RESOLUTION_CLOCK      tmrHw_LOW_FREQUENCY_HZ
-#define tmrHw_HIGH_RESOLUTION_CLOCK     tmrHw_HIGH_FREQUENCY_HZ
-#define tmrHw_MAX_COUNT                 (0xFFFFFFFF)    /* maximum number of count a timer can count */
-#define tmrHw_TIMER_NUM_COUNT           (4)     /* Number of timer module supported */
-
-typedef struct {
-        uint32_t LoadValue;     /* Load value for timer */
-        uint32_t CurrentValue;  /* Current value for timer */
-        uint32_t Control;       /* Control register */
-        uint32_t InterruptClear;        /* Interrupt clear register */
-        uint32_t RawInterruptStatus;    /* Raw interrupt status */
-        uint32_t InterruptStatus;       /* Masked interrupt status */
-        uint32_t BackgroundLoad;        /* Background load value */
-        uint32_t padding;       /* Padding register */
-} tmrHw_REG_t;
-
-/* Control bot masks */
-#define tmrHw_CONTROL_TIMER_ENABLE            0x00000080
-#define tmrHw_CONTROL_PERIODIC                0x00000040
-#define tmrHw_CONTROL_INTERRUPT_ENABLE        0x00000020
-#define tmrHw_CONTROL_PRESCALE_MASK           0x0000000C
-#define tmrHw_CONTROL_PRESCALE_1              0x00000000
-#define tmrHw_CONTROL_PRESCALE_16             0x00000004
-#define tmrHw_CONTROL_PRESCALE_256            0x00000008
-#define tmrHw_CONTROL_32BIT                   0x00000002
-#define tmrHw_CONTROL_ONESHOT                 0x00000001
-#define tmrHw_CONTROL_FREE_RUNNING            0x00000000
-
-#define tmrHw_CONTROL_MODE_MASK               (tmrHw_CONTROL_PERIODIC | tmrHw_CONTROL_ONESHOT)
-
-#define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR)
-
-#endif /* _TMRHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h
deleted file mode 100644
index 13e01384d6fc..000000000000
--- a/arch/arm/mach-bcmring/include/mach/dma.h
+++ /dev/null
@@ -1,630 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma.h
-*
-*   @brief  API definitions for the linux DMA interface.
-*/
-/****************************************************************************/
-
-#if !defined(ASM_ARM_ARCH_BCMRING_DMA_H)
-#define ASM_ARM_ARCH_BCMRING_DMA_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <linux/kernel.h>
-#include <linux/semaphore.h>
-#include <mach/csp/dmacHw.h>
-#include <mach/timer.h>
-
-/* ---- Constants and Types ---------------------------------------------- */
-
-/* If DMA_DEBUG_TRACK_RESERVATION is set to a non-zero value, then the filename */
-/* and line number of the reservation request will be recorded in the channel table */
-
-#define DMA_DEBUG_TRACK_RESERVATION   1
-
-#define DMA_NUM_CONTROLLERS     2
-#define DMA_NUM_CHANNELS        8       /* per controller */
-
-typedef enum {
-        DMA_DEVICE_MEM_TO_MEM,  /* For memory to memory transfers */
-        DMA_DEVICE_I2S0_DEV_TO_MEM,
-        DMA_DEVICE_I2S0_MEM_TO_DEV,
-        DMA_DEVICE_I2S1_DEV_TO_MEM,
-        DMA_DEVICE_I2S1_MEM_TO_DEV,
-        DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM,
-        DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV,
-        DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM,
-        DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV,
-        DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM,      /* Additional mic input for beam-forming */
-        DMA_DEVICE_APM_PCM0_DEV_TO_MEM,
-        DMA_DEVICE_APM_PCM0_MEM_TO_DEV,
-        DMA_DEVICE_APM_PCM1_DEV_TO_MEM,
-        DMA_DEVICE_APM_PCM1_MEM_TO_DEV,
-        DMA_DEVICE_SPUM_DEV_TO_MEM,
-        DMA_DEVICE_SPUM_MEM_TO_DEV,
-        DMA_DEVICE_SPIH_DEV_TO_MEM,
-        DMA_DEVICE_SPIH_MEM_TO_DEV,
-        DMA_DEVICE_UART_A_DEV_TO_MEM,
-        DMA_DEVICE_UART_A_MEM_TO_DEV,
-        DMA_DEVICE_UART_B_DEV_TO_MEM,
-        DMA_DEVICE_UART_B_MEM_TO_DEV,
-        DMA_DEVICE_PIF_MEM_TO_DEV,
-        DMA_DEVICE_PIF_DEV_TO_MEM,
-        DMA_DEVICE_ESW_DEV_TO_MEM,
-        DMA_DEVICE_ESW_MEM_TO_DEV,
-        DMA_DEVICE_VPM_MEM_TO_MEM,
-        DMA_DEVICE_CLCD_MEM_TO_MEM,
-        DMA_DEVICE_NAND_MEM_TO_MEM,
-        DMA_DEVICE_MEM_TO_VRAM,
-        DMA_DEVICE_VRAM_TO_MEM,
-
-        /* Add new entries before this line. */
-
-        DMA_NUM_DEVICE_ENTRIES,
-        DMA_DEVICE_NONE = 0xff, /* Special value to indicate that no device is currently assigned. */
-
-} DMA_Device_t;
-
-/****************************************************************************
-*
-*   The DMA_Handle_t is the primary object used by callers of the API.
-*
-*****************************************************************************/
-
-#define DMA_INVALID_HANDLE  ((DMA_Handle_t) -1)
-
-typedef int DMA_Handle_t;
-
-/****************************************************************************
-*
-*   The DMA_DescriptorRing_t contains a ring of descriptors which is used
-*   to point to regions of memory.
-*
-*****************************************************************************/
-
-typedef struct {
-        void *virtAddr;         /* Virtual Address of the descriptor ring */
-        dma_addr_t physAddr;    /* Physical address of the descriptor ring */
-        int descriptorsAllocated;       /* Number of descriptors allocated in the descriptor ring */
-        size_t bytesAllocated;  /* Number of bytes allocated in the descriptor ring */
-
-} DMA_DescriptorRing_t;
-
-/****************************************************************************
-*
-*   The DMA_DeviceAttribute_t contains information which describes a
-*   particular DMA device (or peripheral).
-*
-*   It is anticipated that the arrary of DMA_DeviceAttribute_t's will be
-*   statically initialized.
-*
-*****************************************************************************/
-
-/* The device handler is called whenever a DMA operation completes. The reaon */
-/* for it to be called will be a bitmask with one or more of the following bits */
-/* set. */
-
-#define DMA_HANDLER_REASON_BLOCK_COMPLETE       dmacHw_INTERRUPT_STATUS_BLOCK
-#define DMA_HANDLER_REASON_TRANSFER_COMPLETE    dmacHw_INTERRUPT_STATUS_TRANS
-#define DMA_HANDLER_REASON_ERROR                dmacHw_INTERRUPT_STATUS_ERROR
-
-typedef void (*DMA_DeviceHandler_t) (DMA_Device_t dev, int reason,
-                                     void *userData);
-
-#define DMA_DEVICE_FLAG_ON_DMA0             0x00000001
-#define DMA_DEVICE_FLAG_ON_DMA1             0x00000002
-#define DMA_DEVICE_FLAG_PORT_PER_DMAC       0x00000004  /* If set, it means that the port used on DMAC0 is different from the port used on DMAC1 */
-#define DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST    0x00000008  /* If set, allocate from DMA1 before allocating from DMA0 */
-#define DMA_DEVICE_FLAG_IS_DEDICATED        0x00000100
-#define DMA_DEVICE_FLAG_NO_ISR              0x00000200
-#define DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO    0x00000400
-#define DMA_DEVICE_FLAG_IN_USE              0x00000800  /* If set, device is in use on a channel */
-
-/* Note: Some DMA devices can be used from multiple DMA Controllers. The bitmask is used to */
-/*       determine which DMA controllers a given device can be used from, and the interface */
-/*       array determeines the actual interface number to use for a given controller. */
-
-typedef struct {
-        uint32_t flags;         /* Bitmask of DMA_DEVICE_FLAG_xxx constants */
-        uint8_t dedicatedController;    /* Controller number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
-        uint8_t dedicatedChannel;       /* Channel number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
-        const char *name;       /* Will show up in the /proc entry */
-
-        uint32_t dmacPort[DMA_NUM_CONTROLLERS]; /* Specifies the port number when DMA_DEVICE_FLAG_PORT_PER_DMAC flag is set */
-
-        dmacHw_CONFIG_t config; /* Configuration to use when DMA'ing using this device */
-
-        void *userData;         /* Passed to the devHandler */
-        DMA_DeviceHandler_t devHandler; /* Called when DMA operations finish. */
-
-        timer_tick_count_t transferStartTime;   /* Time the current transfer was started */
-
-        /* The following statistical information will be collected and presented in a proc entry. */
-        /* Note: With a contiuous bandwidth of 1 Gb/sec, it would take 584 years to overflow */
-        /*       a 64 bit counter. */
-
-        uint64_t numTransfers;  /* Number of DMA transfers performed */
-        uint64_t transferTicks; /* Total time spent doing DMA transfers (measured in timer_tick_count_t's) */
-        uint64_t transferBytes; /* Total bytes transferred */
-        uint32_t timesBlocked;  /* Number of times a channel was unavailable */
-        uint32_t numBytes;      /* Last transfer size */
-
-        /* It's not possible to free memory which is allocated for the descriptors from within */
-        /* the ISR. So make the presumption that a given device will tend to use the */
-        /* same sized buffers over and over again, and we keep them around. */
-
-        DMA_DescriptorRing_t ring;      /* Ring of descriptors allocated for this device */
-
-        /* We stash away some of the information from the previous transfer. If back-to-back */
-        /* transfers are performed from the same buffer, then we don't have to keep re-initializing */
-        /* the descriptor buffers. */
-
-        uint32_t prevNumBytes;
-        dma_addr_t prevSrcData;
-        dma_addr_t prevDstData;
-
-} DMA_DeviceAttribute_t;
-
-/****************************************************************************
-*
-*   DMA_Channel_t, DMA_Controller_t, and DMA_State_t are really internal
-*   data structures and don't belong in this header file, but are included
-*   merely for discussion.
-*
-*   By the time this is implemented, these structures will be moved out into
-*   the appropriate C source file instead.
-*
-*****************************************************************************/
-
-/****************************************************************************
-*
-*   The DMA_Channel_t contains state information about each DMA channel. Some
-*   of the channels are dedicated. Non-dedicated channels are shared
-*   amongst the other devices.
-*
-*****************************************************************************/
-
-#define DMA_CHANNEL_FLAG_IN_USE         0x00000001
-#define DMA_CHANNEL_FLAG_IS_DEDICATED   0x00000002
-#define DMA_CHANNEL_FLAG_NO_ISR         0x00000004
-#define DMA_CHANNEL_FLAG_LARGE_FIFO     0x00000008
-
-typedef struct {
-        uint32_t flags;         /* bitmask of DMA_CHANNEL_FLAG_xxx constants */
-        DMA_Device_t devType;   /* Device this channel is currently reserved for */
-        DMA_Device_t lastDevType;       /* Device type that used this previously */
-        char name[20];          /* Name passed onto request_irq */
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-        const char *fileName;   /* Place where channel reservation took place */
-        int lineNum;            /* Place where channel reservation took place */
-#endif
-        dmacHw_HANDLE_t dmacHwHandle;   /* low level channel handle. */
-
-} DMA_Channel_t;
-
-/****************************************************************************
-*
-*   The DMA_Controller_t contains state information about each DMA controller.
-*
-*   The freeChannelQ is stored in the controller data structure rather than
-*   the channel data structure since several of the devices are accessible
-*   from multiple controllers, and there is no way to know which controller
-*   will become available first.
-*
-*****************************************************************************/
-
-typedef struct {
-        DMA_Channel_t channel[DMA_NUM_CHANNELS];
-
-} DMA_Controller_t;
-
-/****************************************************************************
-*
-*   The DMA_Global_t contains all of the global state information used by
-*   the DMA code.
-*
-*   Callers which need to allocate a shared channel will be queued up
-*   on the freeChannelQ until a channel becomes available.
-*
-*****************************************************************************/
-
-typedef struct {
-        struct semaphore lock;  /* acquired when manipulating table entries */
-        wait_queue_head_t freeChannelQ;
-
-        DMA_Controller_t controller[DMA_NUM_CONTROLLERS];
-
-} DMA_Global_t;
-
-/* ---- Variable Externs ------------------------------------------------- */
-
-extern DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES];
-
-/* ---- Function Prototypes ---------------------------------------------- */
-
-#if defined(__KERNEL__)
-
-/****************************************************************************/
-/**
-*   Initializes the DMA module.
-*
-*   @return
-*       0       - Success
-*       < 0     - Error
-*/
-/****************************************************************************/
-
-int dma_init(void);
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-DMA_Handle_t dma_request_channel_dbg(DMA_Device_t dev, const char *fileName,
-                                     int lineNum);
-#define dma_request_channel(dev)  dma_request_channel_dbg(dev, __FILE__, __LINE__)
-#else
-
-/****************************************************************************/
-/**
-*   Reserves a channel for use with @a dev. If the device is setup to use
-*   a shared channel, then this function will block until a free channel
-*   becomes available.
-*
-*   @return
-*       >= 0    - A valid DMA Handle.
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-DMA_Handle_t dma_request_channel(DMA_Device_t dev       /* Device to use with the allocated channel. */
-    );
-#endif
-
-/****************************************************************************/
-/**
-*   Frees a previously allocated DMA Handle.
-*
-*   @return
-*        0      - DMA Handle was released successfully.
-*       -EINVAL - Invalid DMA handle
-*/
-/****************************************************************************/
-
-int dma_free_channel(DMA_Handle_t channel       /* DMA handle. */
-    );
-
-/****************************************************************************/
-/**
-*   Determines if a given device has been configured as using a shared
-*   channel.
-*
-*   @return boolean
-*       0           Device uses a dedicated channel
-*       non-zero    Device uses a shared channel
-*/
-/****************************************************************************/
-
-int dma_device_is_channel_shared(DMA_Device_t dev       /* Device to check. */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates memory to hold a descriptor ring. The descriptor ring then
-*   needs to be populated by making one or more calls to
-*   dna_add_descriptors.
-*
-*   The returned descriptor ring will be automatically initialized.
-*
-*   @return
-*       0           Descriptor ring was allocated successfully
-*       -ENOMEM     Unable to allocate memory for the desired number of descriptors.
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,       /* Descriptor ring to populate */
-                              int numDescriptors        /* Number of descriptors that need to be allocated. */
-    );
-
-/****************************************************************************/
-/**
-*   Releases the memory which was previously allocated for a descriptor ring.
-*/
-/****************************************************************************/
-
-void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring        /* Descriptor to release */
-    );
-
-/****************************************************************************/
-/**
-*   Initializes a descriptor ring, so that descriptors can be added to it.
-*   Once a descriptor ring has been allocated, it may be reinitialized for
-*   use with additional/different regions of memory.
-*
-*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
-*   initialize the ring with a smaller number of descriptors. The amount
-*   of memory allocated for the descriptor ring will not be reduced, and
-*   the descriptor ring may be reinitialized later
-*
-*   @return
-*       0           Descriptor ring was initialized successfully
-*       -ENOMEM     The descriptor which was passed in has insufficient space
-*                   to hold the desired number of descriptors.
-*/
-/****************************************************************************/
-
-int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,        /* Descriptor ring to initialize */
-                             int numDescriptors /* Number of descriptors to initialize. */
-    );
-
-/****************************************************************************/
-/**
-*   Determines the number of descriptors which would be required for a
-*   transfer of the indicated memory region.
-*
-*   This function also needs to know which DMA device this transfer will
-*   be destined for, so that the appropriate DMA configuration can be retrieved.
-*   DMA parameters such as transfer width, and whether this is a memory-to-memory
-*   or memory-to-peripheral, etc can all affect the actual number of descriptors
-*   required.
-*
-*   @return
-*       > 0     Returns the number of descriptors required for the indicated transfer
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */
-                                   dma_addr_t srcData,  /* Place to get data to write to device */
-                                   dma_addr_t dstData,  /* Pointer to device data address */
-                                   size_t numBytes      /* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Adds a region of memory to the descriptor ring. Note that it may take
-*   multiple descriptors for each region of memory. It is the callers
-*   responsibility to allocate a sufficiently large descriptor ring.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_add_descriptors(DMA_DescriptorRing_t *ring,     /* Descriptor ring to add descriptors to */
-                        DMA_Device_t device,    /* DMA Device that descriptors are for */
-                        dma_addr_t srcData,     /* Place to get data (memory or device) */
-                        dma_addr_t dstData,     /* Place to put data (memory or device) */
-                        size_t numBytes /* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Sets the descriptor ring associated with a device.
-*
-*   Once set, the descriptor ring will be associated with the device, even
-*   across channel request/free calls. Passing in a NULL descriptor ring
-*   will release any descriptor ring currently associated with the device.
-*
-*   Note: If you call dma_transfer, or one of the other dma_alloc_ functions
-*         the descriptor ring may be released and reallocated.
-*
-*   Note: This function will release the descriptor memory for any current
-*         descriptor ring associated with this device.
-*/
-/****************************************************************************/
-
-int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */
-                                   DMA_DescriptorRing_t *ring   /* Descriptor ring to add descriptors to */
-    );
-
-/****************************************************************************/
-/**
-*   Retrieves the descriptor ring associated with a device.
-*/
-/****************************************************************************/
-
-int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */
-                                   DMA_DescriptorRing_t *ring   /* Place to store retrieved ring */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates buffers for the descriptors. This is normally done automatically
-*   but needs to be done explicitly when initiating a dma from interrupt
-*   context.
-*
-*   @return
-*       0       Descriptors were allocated successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptors(DMA_Handle_t handle,  /* DMA Handle */
-                          dmacHw_TRANSFER_TYPE_e transferType,  /* Type of transfer being performed */
-                          dma_addr_t srcData,   /* Place to get data to write to device */
-                          dma_addr_t dstData,   /* Pointer to device data address */
-                          size_t numBytes       /* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates and sets up descriptors for a double buffered circular buffer.
-*
-*   This is primarily intended to be used for things like the ingress samples
-*   from a microphone.
-*
-*   @return
-*       > 0     Number of descriptors actually allocated.
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,       /* DMA Handle */
-                                     dma_addr_t srcData,        /* Physical address of source data */
-                                     dma_addr_t dstData1,       /* Physical address of first destination buffer */
-                                     dma_addr_t dstData2,       /* Physical address of second destination buffer */
-                                     size_t numBytes    /* Number of bytes in each destination buffer */
-    );
-
-/****************************************************************************/
-/**
-*   Initiates a transfer when the descriptors have already been setup.
-*
-*   This is a special case, and normally, the dma_transfer_xxx functions should
-*   be used.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_start_transfer(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Stops a previously started DMA transfer.
-*
-*   @return
-*       0       Transfer was stopped successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_stop_transfer(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Waits for a DMA to complete by polling. This function is only intended
-*   to be used for testing. Interrupts should be used for most DMA operations.
-*/
-/****************************************************************************/
-
-int dma_wait_transfer_done(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Initiates a DMA transfer
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*/
-/****************************************************************************/
-
-int dma_transfer(DMA_Handle_t handle,   /* DMA Handle */
-                 dmacHw_TRANSFER_TYPE_e transferType,   /* Type of transfer being performed */
-                 dma_addr_t srcData,    /* Place to get data to write to device */
-                 dma_addr_t dstData,    /* Pointer to device data address */
-                 size_t numBytes        /* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Initiates a transfer from memory to a device.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_to_device(DMA_Handle_t handle,   /* DMA Handle */
-                                         dma_addr_t srcData,    /* Place to get data to write to device (physical address) */
-                                         dma_addr_t dstData,    /* Pointer to device data address (physical address) */
-                                         size_t numBytes        /* Number of bytes to transfer to the device */
-    ) {
-        return dma_transfer(handle,
-                            dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-                            srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Initiates a transfer from a device to memory.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_from_device(DMA_Handle_t handle, /* DMA Handle */
-                                           dma_addr_t srcData,  /* Pointer to the device data address (physical address) */
-                                           dma_addr_t dstData,  /* Place to store data retrieved from the device (physical address) */
-                                           size_t numBytes      /* Number of bytes to retrieve from the device */
-    ) {
-        return dma_transfer(handle,
-                            dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-                            srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Initiates a memory to memory transfer.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device wasn't DMA_DEVICE_MEM_TO_MEM)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_mem_to_mem(DMA_Handle_t handle,  /* DMA Handle */
-                                          dma_addr_t srcData,   /* Place to transfer data from (physical address) */
-                                          dma_addr_t dstData,   /* Place to transfer data to (physical address) */
-                                          size_t numBytes       /* Number of bytes to transfer */
-    ) {
-        return dma_transfer(handle,
-                            dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-                            srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Set the callback function which will be called when a transfer completes.
-*   If a NULL callback function is set, then no callback will occur.
-*
-*   @note   @a devHandler will be called from IRQ context.
-*
-*   @return
-*       0       - Success
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_handler(DMA_Device_t dev,    /* Device to set the callback for. */
-                           DMA_DeviceHandler_t devHandler,      /* Function to call when the DMA completes */
-                           void *userData       /* Pointer which will be passed to devHandler. */
-    );
-
-#endif
-
-#endif /* ASM_ARM_ARCH_BCMRING_DMA_H */
diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S b/arch/arm/mach-bcmring/include/mach/entry-macro.S
deleted file mode 100644
index 2f316f0e6e69..000000000000
--- a/arch/arm/mach-bcmring/include/mach/entry-macro.S
+++ /dev/null
@@ -1,76 +0,0 @@
-/*****************************************************************************
-* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
- *
- * Low-level IRQ helper macros for BCMRing-based platforms
- *
- */
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =(MM_IO_BASE_INTC0)
-                ldr     \irqstat, [\base, #0]           @ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
-                ands    \irqstat, \irqstat, \irqnr
-                mov     \irqnr, #IRQ_INTC0_START
-                cmp     \irqstat, #0
-                bne     1001f
-
-                ldr     \base, =(MM_IO_BASE_INTC1)
-                ldr     \irqstat, [\base, #0]           @ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
-                ands    \irqstat, \irqstat, \irqnr
-                mov     \irqnr, #IRQ_INTC1_START
-                cmp     \irqstat, #0
-                bne     1001f
-
-                ldr     \base, =(MM_IO_BASE_SINTC)
-                ldr     \irqstat, [\base, #0]           @ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
-                ands    \irqstat, \irqstat, \irqnr
-                mov     \irqnr, #0xffffffff             @ code meaning no interrupt bits set
-                cmp     \irqstat, #0
-                beq     1002f
-
-                mov     \irqnr, #IRQ_SINTC_START        @ something is set, so fixup return value
-
-1001:
-                movs    \tmp, \irqstat, lsl #16
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #16
-
-                movs    \tmp, \irqstat, lsl #8
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #8
-
-                movs    \tmp, \irqstat, lsl #4
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #4
-
-                movs    \tmp, \irqstat, lsl #2
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #2
-
-                movs    \tmp, \irqstat, lsl #1
-                addeq   \irqnr, \irqnr, #1
-                orrs    \base, \base, #1
-
-1002:           @ irqnr will be set to 0xffffffff if no irq bits are set
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h
deleted file mode 100644
index a0c92b4b8c60..000000000000
--- a/arch/arm/mach-bcmring/include/mach/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *
- *  This file contains the hardware definitions of the BCMRing.
- *
- *  Copyright (C) 1999 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <mach/cfg_global.h>
-#include <mach/csp/mm_io.h>
-
-/* Hardware addresses of major areas.
- *  *_START is the physical address
- *  *_SIZE  is the size of the region
- *  *_BASE  is the virtual address
- */
-#define RAM_START               PHYS_OFFSET
-
-#define RAM_SIZE                (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
-#define RAM_BASE                PAGE_OFFSET
-
-/* Macros to make managing spinlocks a bit more controlled in terms of naming. */
-/* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */
-#if defined(__KERNEL__)
-#define HW_DECLARE_SPINLOCK(name)  DEFINE_SPINLOCK(bcmring_##name##_reg_lock);
-#define HW_EXTERN_SPINLOCK(name)   extern spinlock_t bcmring_##name##_reg_lock;
-#define HW_IRQ_SAVE(name, val)     spin_lock_irqsave(&bcmring_##name##_reg_lock, (val))
-#define HW_IRQ_RESTORE(name, val)  spin_unlock_irqrestore(&bcmring_##name##_reg_lock, (val))
-#else
-#define HW_DECLARE_SPINLOCK(name)
-#define HW_EXTERN_SPINLOCK(name)
-#define HW_IRQ_SAVE(name, val)     {(void)(name); (void)(val); }
-#define HW_IRQ_RESTORE(name, val)  {(void)(name); (void)(val); }
-#endif
-
-#ifndef HW_IO_PHYS_TO_VIRT
-#define HW_IO_PHYS_TO_VIRT MM_IO_PHYS_TO_VIRT
-#endif
-#define HW_IO_VIRT_TO_PHYS MM_IO_VIRT_TO_PHYS
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/irqs.h b/arch/arm/mach-bcmring/include/mach/irqs.h
deleted file mode 100644
index b279b825d4a7..000000000000
--- a/arch/arm/mach-bcmring/include/mach/irqs.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- *  Copyright (C) 2007 Broadcom
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#if !defined(ARCH_BCMRING_IRQS_H)
-#define ARCH_BCMRING_IRQS_H
-
-/* INTC0 - interrupt controller 0 */
-#define IRQ_INTC0_START     0
-#define IRQ_DMA0C0          0   /* DMA0 channel 0 interrupt */
-#define IRQ_DMA0C1          1   /* DMA0 channel 1 interrupt */
-#define IRQ_DMA0C2          2   /* DMA0 channel 2 interrupt */
-#define IRQ_DMA0C3          3   /* DMA0 channel 3 interrupt */
-#define IRQ_DMA0C4          4   /* DMA0 channel 4 interrupt */
-#define IRQ_DMA0C5          5   /* DMA0 channel 5 interrupt */
-#define IRQ_DMA0C6          6   /* DMA0 channel 6 interrupt */
-#define IRQ_DMA0C7          7   /* DMA0 channel 7 interrupt */
-#define IRQ_DMA1C0          8   /* DMA1 channel 0 interrupt */
-#define IRQ_DMA1C1          9   /* DMA1 channel 1 interrupt */
-#define IRQ_DMA1C2         10   /* DMA1 channel 2 interrupt */
-#define IRQ_DMA1C3         11   /* DMA1 channel 3 interrupt */
-#define IRQ_DMA1C4         12   /* DMA1 channel 4 interrupt */
-#define IRQ_DMA1C5         13   /* DMA1 channel 5 interrupt */
-#define IRQ_DMA1C6         14   /* DMA1 channel 6 interrupt */
-#define IRQ_DMA1C7         15   /* DMA1 channel 7 interrupt */
-#define IRQ_VPM            16   /* Voice process module interrupt */
-#define IRQ_USBHD2         17   /* USB host2/device2 interrupt */
-#define IRQ_USBH1          18   /* USB1 host interrupt */
-#define IRQ_USBD           19   /* USB device interrupt */
-#define IRQ_SDIOH0         20   /* SDIO0 host interrupt */
-#define IRQ_SDIOH1         21   /* SDIO1 host interrupt */
-#define IRQ_TIMER0         22   /* Timer0 interrupt */
-#define IRQ_TIMER1         23   /* Timer1 interrupt */
-#define IRQ_TIMER2         24   /* Timer2 interrupt */
-#define IRQ_TIMER3         25   /* Timer3 interrupt */
-#define IRQ_SPIH           26   /* SPI host interrupt */
-#define IRQ_ESW            27   /* Ethernet switch interrupt */
-#define IRQ_APM            28   /* Audio process module interrupt */
-#define IRQ_GE             29   /* Graphic engine interrupt */
-#define IRQ_CLCD           30   /* LCD Controller interrupt */
-#define IRQ_PIF            31   /* Peripheral interface interrupt */
-#define IRQ_INTC0_END      31
-
-/* INTC1 - interrupt controller 1 */
-#define IRQ_INTC1_START    32
-#define IRQ_GPIO0          32   /*  0 GPIO bit 31//0 combined interrupt */
-#define IRQ_GPIO1          33   /*  1 GPIO bit 64//32 combined interrupt */
-#define IRQ_I2S0           34   /*  2 I2S0 interrupt */
-#define IRQ_I2S1           35   /*  3 I2S1 interrupt */
-#define IRQ_I2CH           36   /*  4 I2C host interrupt */
-#define IRQ_I2CS           37   /*  5 I2C slave interrupt */
-#define IRQ_SPIS           38   /*  6 SPI slave interrupt */
-#define IRQ_GPHY           39   /*  7 Gigabit Phy interrupt */
-#define IRQ_FLASHC         40   /*  8 Flash controller interrupt */
-#define IRQ_COMMTX         41   /*  9 ARM DDC transmit interrupt */
-#define IRQ_COMMRX         42   /* 10 ARM DDC receive interrupt */
-#define IRQ_PMUIRQ         43   /* 11 ARM performance monitor interrupt */
-#define IRQ_UARTB          44   /* 12 UARTB */
-#define IRQ_WATCHDOG       45   /* 13 Watchdog timer interrupt */
-#define IRQ_UARTA          46   /* 14 UARTA */
-#define IRQ_TSC            47   /* 15 Touch screen controller interrupt */
-#define IRQ_KEYC           48   /* 16 Key pad controller interrupt */
-#define IRQ_DMPU           49   /* 17 DDR2 memory partition interrupt */
-#define IRQ_VMPU           50   /* 18 VRAM memory partition interrupt */
-#define IRQ_FMPU           51   /* 19 Flash memory parition unit interrupt */
-#define IRQ_RNG            52   /* 20 Random number generator interrupt */
-#define IRQ_RTC0           53   /* 21 Real time clock periodic interrupt */
-#define IRQ_RTC1           54   /* 22 Real time clock one-shot interrupt */
-#define IRQ_SPUM           55   /* 23 Secure process module interrupt */
-#define IRQ_VDEC           56   /* 24 Hantro video decoder interrupt */
-#define IRQ_RTC2           57   /* 25 Real time clock tamper interrupt */
-#define IRQ_DDRP           58   /* 26 DDR Panic interrupt */
-#define IRQ_INTC1_END      58
-
-/* SINTC secure int controller */
-#define IRQ_SINTC_START    59
-#define IRQ_SEC_WATCHDOG   59   /*  0 Watchdog timer interrupt */
-#define IRQ_SEC_UARTA      60   /*  1 UARTA interrupt */
-#define IRQ_SEC_TSC        61   /*  2 Touch screen controller interrupt */
-#define IRQ_SEC_KEYC       62   /*  3 Key pad controller interrupt */
-#define IRQ_SEC_DMPU       63   /*  4 DDR2 memory partition interrupt */
-#define IRQ_SEC_VMPU       64   /*  5 VRAM memory partition interrupt */
-#define IRQ_SEC_FMPU       65   /*  6 Flash memory parition unit interrupt */
-#define IRQ_SEC_RNG        66   /*  7 Random number generator interrupt */
-#define IRQ_SEC_RTC0       67   /*  8 Real time clock periodic interrupt */
-#define IRQ_SEC_RTC1       68   /*  9 Real time clock one-shot interrupt */
-#define IRQ_SEC_SPUM       69   /* 10 Secure process module interrupt */
-#define IRQ_SEC_TIMER0     70   /* 11 Secure timer0 interrupt */
-#define IRQ_SEC_TIMER1     71   /* 12 Secure timer1 interrupt */
-#define IRQ_SEC_TIMER2     72   /* 13 Secure timer2 interrupt */
-#define IRQ_SEC_TIMER3     73   /* 14 Secure timer3 interrupt */
-#define IRQ_SEC_RTC2       74   /* 15 Real time clock tamper interrupt */
-
-#define IRQ_SINTC_END      74
-
-/* Note: there are 3 INTC registers of 32 bits each. So internal IRQs could go from 0-95 */
-/*       Since IRQs are typically viewed in decimal, we start the gpio based IRQs off at 100 */
-/*       to make the mapping easy for humans to decipher. */
-
-#define IRQ_GPIO_0                  100
-
-#define NUM_INTERNAL_IRQS          (IRQ_SINTC_END+1)
-
-/* I couldn't get the gpioHw_reg.h file to be included cleanly, so I hardcoded it */
-/* define NUM_GPIO_IRQS               GPIOHW_TOTAL_NUM_PINS */
-#define NUM_GPIO_IRQS               62
-
-#define NR_IRQS                     (IRQ_GPIO_0 + NUM_GPIO_IRQS)
-
-#define IRQ_UNKNOWN                 -1
-
-/* Tune these bits to preclude noisy or unsupported interrupt sources as required. */
-#define IRQ_INTC0_VALID_MASK        0xffffffff
-#define IRQ_INTC1_VALID_MASK        0x07ffffff
-#define IRQ_SINTC_VALID_MASK        0x0000ffff
-
-#endif /* ARCH_BCMRING_IRQS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/memory_settings.h b/arch/arm/mach-bcmring/include/mach/memory_settings.h
deleted file mode 100644
index ce5cd16f2ac4..000000000000
--- a/arch/arm/mach-bcmring/include/mach/memory_settings.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef MEMORY_SETTINGS_H
-#define MEMORY_SETTINGS_H
-
-/* ---- Include Files ---------------------------------------- */
-/* ---- Constants and Types ---------------------------------- */
-
-/* Memory devices */
-/* NAND Flash timing for 166 MHz setting */
-#define HW_CFG_NAND_tBTA  (5 << 16)     /* Bus turnaround cycle (n)        0-7  (30 ns) */
-#define HW_CFG_NAND_tWP   (4 << 11)     /* Write pulse width cycle (n+1)   0-31 (25 ns) */
-#define HW_CFG_NAND_tWR   (1 << 9)      /* Write recovery cycle (n+1)      0-3  (10 ns) */
-#define HW_CFG_NAND_tAS   (0 << 7)      /* Write address setup cycle (n+1) 0-3  ( 0 ns) */
-#define HW_CFG_NAND_tOE   (3 << 5)      /* Output enable delay cycle (n)   0-3  (15 ns) */
-#define HW_CFG_NAND_tRC   (7 << 0)      /* Read access cycle (n+2)         0-31 (50 ns) */
-
-#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \
-        | HW_CFG_NAND_tWP  \
-        | HW_CFG_NAND_tWR  \
-        | HW_CFG_NAND_tAS  \
-        | HW_CFG_NAND_tOE  \
-        | HW_CFG_NAND_tRC)
-
-/* NOR Flash timing for 166 MHz setting */
-#define HW_CFG_NOR_TPRC_TWLC (0 << 19)  /* Page read access cycle / Burst write latency (n+2 / n+1) (max 25ns) */
-#define HW_CFG_NOR_TBTA      (0 << 16)  /* Bus turnaround cycle (n)                                 (DNA)      */
-#define HW_CFG_NOR_TWP       (6 << 11)  /* Write pulse width cycle (n+1)                            (35ns)     */
-#define HW_CFG_NOR_TWR       (0 << 9)   /* Write recovery cycle (n+1)                               (0ns)      */
-#define HW_CFG_NOR_TAS       (0 << 7)   /* Write address setup cycle (n+1)                          (0ns)      */
-#define HW_CFG_NOR_TOE       (0 << 5)   /* Output enable delay cycle (n)                            (max 25ns) */
-#define HW_CFG_NOR_TRC_TLC   (0x10 << 0)        /* Read access cycle / Burst read latency (n+2 / n+1)       (100ns)    */
-
-#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \
-        | HW_CFG_NOR_TBTA      \
-        | HW_CFG_NOR_TWP       \
-        | HW_CFG_NOR_TWR       \
-        | HW_CFG_NOR_TAS       \
-        | HW_CFG_NOR_TOE       \
-        | HW_CFG_NOR_TRC_TLC)
-
-#define HW_CFG_FLASH1_TCR    HW_CFG_FLASH0_TCR
-#define HW_CFG_FLASH2_TCR    HW_CFG_FLASH0_TCR
-
-/* SDRAM Settings */
-/* #define HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
-/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
-/* #define HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values [400,533,667,800] */
-/* #define HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules [8,16] */
-#define HW_CFG_SDRAM_SIZE_BYTES         0x10000000      /* Total memory, not per device size */
-
-/* ---- Variable Externs ------------------------------------- */
-/* ---- Function Prototypes ---------------------------------- */
-
-#endif /* MEMORY_SETTINGS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h b/arch/arm/mach-bcmring/include/mach/reg_nand.h
deleted file mode 100644
index f8d51a8b0b15..000000000000
--- a/arch/arm/mach-bcmring/include/mach/reg_nand.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  REG_NAND.h
-*
-*  PURPOSE:
-*
-*     This file contains definitions for the nand registers:
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(__ASM_ARCH_REG_NAND_H)
-#define __ASM_ARCH_REG_NAND_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/reg.h>
-#include <mach/reg_umi.h>
-
-/* ---- Constants and Types ---------------------------------------------- */
-
-#define HW_NAND_BASE       MM_IO_BASE_NAND      /* NAND Flash */
-
-/* DMA accesses by the bootstrap need hard nonvirtual addresses */
-#define REG_NAND_CMD            __REG16(HW_NAND_BASE + 0)
-#define REG_NAND_ADDR           __REG16(HW_NAND_BASE + 4)
-
-#define REG_NAND_PHYS_DATA16   (HW_NAND_BASE + 8)
-#define REG_NAND_PHYS_DATA8    (HW_NAND_BASE + 8)
-#define REG_NAND_DATA16         __REG16(REG_NAND_PHYS_DATA16)
-#define REG_NAND_DATA8          __REG8(REG_NAND_PHYS_DATA8)
-
-/* use appropriate offset to make sure it start at the 1K boundary */
-#define REG_NAND_PHYS_DATA_DMA   (HW_NAND_BASE + 0x400)
-#define REG_NAND_DATA_DMA         __REG32(REG_NAND_PHYS_DATA_DMA)
-
-/* Linux DMA requires physical address of the data register */
-#define REG_NAND_DATA16_PADDR    HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA16)
-#define REG_NAND_DATA8_PADDR     HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA8)
-#define REG_NAND_DATA_PADDR      HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA_DMA)
-
-#define NAND_BUS_16BIT()        (0)
-#define NAND_BUS_8BIT()         (!NAND_BUS_16BIT())
-
-/* Register offsets */
-#define REG_NAND_CMD_OFFSET     (0)
-#define REG_NAND_ADDR_OFFSET    (4)
-#define REG_NAND_DATA8_OFFSET   (8)
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h
deleted file mode 100644
index 56dd9de7d83f..000000000000
--- a/arch/arm/mach-bcmring/include/mach/reg_umi.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*****************************************************************************
-* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  REG_UMI.h
-*
-*  PURPOSE:
-*
-*     This file contains definitions for the nand registers:
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(__ASM_ARCH_REG_UMI_H)
-#define __ASM_ARCH_REG_UMI_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/reg.h>
-#include <mach/csp/mm_io.h>
-
-/* ---- Constants and Types ---------------------------------------------- */
-
-/* Unified Memory Interface Ctrl Register */
-#define HW_UMI_BASE       MM_IO_BASE_UMI
-
-/* Flash bank 0 timing and control register */
-#define REG_UMI_FLASH0_TCR         __REG32(HW_UMI_BASE  + 0x00)
-/* Flash bank 1 timing and control register */
-#define REG_UMI_FLASH1_TCR         __REG32(HW_UMI_BASE  + 0x04)
-/* Flash bank 2 timing and control register */
-#define REG_UMI_FLASH2_TCR         __REG32(HW_UMI_BASE  + 0x08)
-/* MMD interface and control register */
-#define REG_UMI_MMD_ICR            __REG32(HW_UMI_BASE  + 0x0c)
-/* NAND timing and control register */
-#define REG_UMI_NAND_TCR           __REG32(HW_UMI_BASE  + 0x18)
-/* NAND ready/chip select register */
-#define REG_UMI_NAND_RCSR          __REG32(HW_UMI_BASE  + 0x1c)
-/* NAND ECC control & status register */
-#define REG_UMI_NAND_ECC_CSR       __REG32(HW_UMI_BASE  + 0x20)
-/* NAND ECC data register XXB2B1B0 */
-#define REG_UMI_NAND_ECC_DATA      __REG32(HW_UMI_BASE  + 0x24)
-/* BCH ECC Parameter N */
-#define REG_UMI_BCH_N              __REG32(HW_UMI_BASE  + 0x40)
-/* BCH ECC Parameter T */
-#define REG_UMI_BCH_K              __REG32(HW_UMI_BASE  + 0x44)
-/* BCH ECC Parameter K */
-#define REG_UMI_BCH_T              __REG32(HW_UMI_BASE  + 0x48)
-/* BCH ECC Contro Status */
-#define REG_UMI_BCH_CTRL_STATUS    __REG32(HW_UMI_BASE  + 0x4C)
-/* BCH WR ECC 31:0 */
-#define REG_UMI_BCH_WR_ECC_0       __REG32(HW_UMI_BASE  + 0x50)
-/* BCH WR ECC 63:32 */
-#define REG_UMI_BCH_WR_ECC_1       __REG32(HW_UMI_BASE  + 0x54)
-/* BCH WR ECC 95:64 */
-#define REG_UMI_BCH_WR_ECC_2       __REG32(HW_UMI_BASE  + 0x58)
-/* BCH WR ECC 127:96 */
-#define REG_UMI_BCH_WR_ECC_3       __REG32(HW_UMI_BASE  + 0x5c)
-/* BCH WR ECC 155:128 */
-#define REG_UMI_BCH_WR_ECC_4       __REG32(HW_UMI_BASE  + 0x60)
-/* BCH Read Error Location 1,0 */
-#define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE  + 0x64)
-/* BCH Read Error Location 3,2 */
-#define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE  + 0x68)
-/* BCH Read Error Location 5,4 */
-#define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE  + 0x6c)
-/* BCH Read Error Location 7,6 */
-#define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE  + 0x70)
-/* BCH Read Error Location 9,8 */
-#define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE  + 0x74)
-/* BCH Read Error Location 11,10 */
-#define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE  + 0x78)
-
-/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */
-/* Enable wait pin during burst write or read */
-#define REG_UMI_TCR_WAITEN              0x80000000
-/* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */
-#define REG_UMI_TCR_LOWFREQ             0x40000000
-/* 1=synch write, 0=async write */
-#define REG_UMI_TCR_MEMTYPE_SYNCWRITE   0x20000000
-/* 1=synch read, 0=async read */
-#define REG_UMI_TCR_MEMTYPE_SYNCREAD    0x10000000
-/* 1=page mode read, 0=normal mode read */
-#define REG_UMI_TCR_MEMTYPE_PAGEREAD    0x08000000
-/* page size/burst size (wrap only) */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_MASK   0x07000000
-/* 4 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_4      0x00000000
-/* 8 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_8      0x01000000
-/* 16 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_16     0x02000000
-/* 32 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_32     0x03000000
-/* 64 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_64     0x04000000
-/* 128 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_128    0x05000000
-/* 256 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_256    0x06000000
-/* 512 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_512    0x07000000
-/* Page read access cycle / Burst write latency (n+2 / n+1) */
-#define REG_UMI_TCR_TPRC_TWLC_MASK      0x00f80000
-/* Bus turnaround cycle (n) */
-#define REG_UMI_TCR_TBTA_MASK           0x00070000
-/* Write pulse width cycle (n+1) */
-#define REG_UMI_TCR_TWP_MASK            0x0000f800
-/* Write recovery cycle (n+1) */
-#define REG_UMI_TCR_TWR_MASK            0x00000600
-/* Write address setup cycle (n+1) */
-#define REG_UMI_TCR_TAS_MASK            0x00000180
-/* Output enable delay cycle (n) */
-#define REG_UMI_TCR_TOE_MASK            0x00000060
-/* Read access cycle / Burst read latency (n+2 / n+1) */
-#define REG_UMI_TCR_TRC_TLC_MASK        0x0000001f
-
-/* REG_UMI_MMD_ICR bits */
-/* Flash write protection pin control */
-#define REG_UMI_MMD_ICR_FLASH_WP            0x8000
-/* Extend hold time for sram0, sram1 csn (39 MHz operation) */
-#define REG_UMI_MMD_ICR_XHCS                0x4000
-/* Enable SDRAM 2 interface control */
-#define REG_UMI_MMD_ICR_SDRAM2EN            0x2000
-/* Enable merge of flash banks 0/1 to 512 MBit bank */
-#define REG_UMI_MMD_ICR_INST512             0x1000
-/* Enable merge of flash banks 1/2 to 512 MBit bank */
-#define REG_UMI_MMD_ICR_DATA512             0x0800
-/* Enable SDRAM interface control */
-#define REG_UMI_MMD_ICR_SDRAMEN             0x0400
-/* Polarity of busy state of Burst Wait Signal */
-#define REG_UMI_MMD_ICR_WAITPOL             0x0200
-/* Enable burst clock stopped when not accessing external burst flash/sram */
-#define REG_UMI_MMD_ICR_BCLKSTOP            0x0100
-/* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */
-#define REG_UMI_MMD_ICR_PERI1EN             0x0080
-/* Enable the peri2_csn to replace sdram_csn */
-#define REG_UMI_MMD_ICR_PERI2EN             0x0040
-/* Enable the peri3_csn to replace sdram2_csn */
-#define REG_UMI_MMD_ICR_PERI3EN             0x0020
-/* Enable sram bank1 for H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSB1               0x0010
-/* Enable sram bank0 for H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSB0               0x0008
-/* Polarity for assert3ed state of H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSPOL              0x0004
-/* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */
-/* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */
-#define REG_UMI_MMD_ICR_MRSMODE             0x0002
-/* MRS state for S/W controlled mode */
-#define REG_UMI_MMD_ICR_MRSSTATE            0x0001
-
-/* REG_UMI_NAND_TCR bits */
-/* Enable software to control CS */
-#define REG_UMI_NAND_TCR_CS_SWCTRL          0x80000000
-/* 16-bit nand wordsize if set */
-#define REG_UMI_NAND_TCR_WORD16             0x40000000
-/* Bus turnaround cycle (n) */
-#define REG_UMI_NAND_TCR_TBTA_MASK          0x00070000
-/* Write pulse width cycle (n+1) */
-#define REG_UMI_NAND_TCR_TWP_MASK           0x0000f800
-/* Write recovery cycle (n+1) */
-#define REG_UMI_NAND_TCR_TWR_MASK           0x00000600
-/* Write address setup cycle (n+1) */
-#define REG_UMI_NAND_TCR_TAS_MASK           0x00000180
-/* Output enable delay cycle (n) */
-#define REG_UMI_NAND_TCR_TOE_MASK           0x00000060
-/* Read access cycle (n+2) */
-#define REG_UMI_NAND_TCR_TRC_TLC_MASK       0x0000001f
-
-/* REG_UMI_NAND_RCSR bits */
-/* Status: Ready=1, Busy=0 */
-#define REG_UMI_NAND_RCSR_RDY               0x02
-/* Keep CS asserted during operation */
-#define REG_UMI_NAND_RCSR_CS_ASSERTED       0x01
-
-/* REG_UMI_NAND_ECC_CSR bits */
-/* Interrupt status - read-only */
-#define REG_UMI_NAND_ECC_CSR_NANDINT        0x80000000
-/* Read: Status of ECC done, Write: clear ECC interrupt */
-#define REG_UMI_NAND_ECC_CSR_ECCINT_RAW     0x00800000
-/* Read: Status of R/B, Write: clear R/B interrupt */
-#define REG_UMI_NAND_ECC_CSR_RBINT_RAW      0x00400000
-/* 1 = Enable ECC Interrupt */
-#define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE  0x00008000
-/* 1 = Assert interrupt at rising edge of R/B_ */
-#define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE   0x00004000
-/* Calculate ECC by 0=512 bytes, 1=256 bytes */
-#define REG_UMI_NAND_ECC_CSR_256BYTE        0x00000080
-/* Enable ECC in hardware */
-#define REG_UMI_NAND_ECC_CSR_ECC_ENABLE     0x00000001
-
-/* REG_UMI_BCH_CTRL_STATUS bits */
-/* Shift to Indicate Number of correctable errors detected */
-#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20
-/* Indicate Number of correctable errors detected */
-#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000
-/* Indicate Errors detected during read but uncorrectable */
-#define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR    0x00080000
-/* Indicate Errors detected during read and are correctable */
-#define REG_UMI_BCH_CTRL_STATUS_CORR_ERR      0x00040000
-/* Flag indicates BCH's ECC status of read process are valid */
-#define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID  0x00020000
-/* Flag indicates BCH's ECC status of write process are valid */
-#define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID  0x00010000
-/* Pause ECC calculation */
-#define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010
-/* Enable Interrupt */
-#define REG_UMI_BCH_CTRL_STATUS_INT_EN        0x00000004
-/* Enable ECC during read */
-#define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN     0x00000002
-/* Enable ECC during write */
-#define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN     0x00000001
-/* Mask for location */
-#define REG_UMI_BCH_ERR_LOC_MASK              0x00001FFF
-/* location within a byte */
-#define REG_UMI_BCH_ERR_LOC_BYTE              0x00000007
-/* location within a word */
-#define REG_UMI_BCH_ERR_LOC_WORD              0x00000018
-/* location within a page (512 byte) */
-#define REG_UMI_BCH_ERR_LOC_PAGE              0x00001FE0
-#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (readl(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/timer.h b/arch/arm/mach-bcmring/include/mach/timer.h
deleted file mode 100644
index 5a94bbb032b6..000000000000
--- a/arch/arm/mach-bcmring/include/mach/timer.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  timer.h
-*
-*  PURPOSE:
-*
-*
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(BCM_LINUX_TIMER_H)
-#define BCM_LINUX_TIMER_H
-
-#if defined(__KERNEL__)
-
-/* ---- Include Files ---------------------------------------------------- */
-/* ---- Constants and Types ---------------------------------------------- */
-
-typedef unsigned int timer_tick_count_t;
-typedef unsigned int timer_tick_rate_t;
-typedef unsigned int timer_msec_t;
-
-/* ---- Variable Externs ------------------------------------------------- */
-/* ---- Function Prototypes ---------------------------------------------- */
-
-/****************************************************************************
-*
-*  timer_get_tick_count
-*
-*
-***************************************************************************/
-timer_tick_count_t timer_get_tick_count(void);
-
-/****************************************************************************
-*
-*  timer_get_tick_rate
-*
-*
-***************************************************************************/
-timer_tick_rate_t timer_get_tick_rate(void);
-
-/****************************************************************************
-*
-*  timer_get_msec
-*
-*
-***************************************************************************/
-timer_msec_t timer_get_msec(void);
-
-/****************************************************************************
-*
-*  timer_ticks_to_msec
-*
-*
-***************************************************************************/
-timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks);
-
-#endif /* __KERNEL__ */
-#endif /* BCM_LINUX_TIMER_H */
diff --git a/arch/arm/mach-bcmring/include/mach/timex.h b/arch/arm/mach-bcmring/include/mach/timex.h
deleted file mode 100644
index 40d033ec5892..000000000000
--- a/arch/arm/mach-bcmring/include/mach/timex.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *
- *  Integrator architecture timex specifications
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * Specifies the number of ticks per second
- */
-#define CLOCK_TICK_RATE         100000 /* REG_SMT_TICKS_PER_SEC */
diff --git a/arch/arm/mach-bcmring/include/mach/uncompress.h b/arch/arm/mach-bcmring/include/mach/uncompress.h
deleted file mode 100644
index 9c9821b77977..000000000000
--- a/arch/arm/mach-bcmring/include/mach/uncompress.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*****************************************************************************
-* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <mach/csp/mm_addr.h>
-
-#define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
-#define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18))
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-        /* Send out UARTA */
-        while (BCMRING_UART_0_FR & (1 << 5))
-                ;
-
-        BCMRING_UART_0_DR = c;
-}
-
-
-static inline void flush(void)
-{
-        /* Wait for the tx fifo to be empty */
-        while ((BCMRING_UART_0_FR & (1 << 7)) == 0)
-                ;
-
-        /* Wait for the final character to be sent on the txd line */
-        while (BCMRING_UART_0_FR & (1 << 3))
-                ;
-}
-
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
deleted file mode 100644
index 437fa683bcb2..000000000000
--- a/arch/arm/mach-bcmring/irq.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/stddef.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-#include <mach/csp/intcHw_reg.h>
-#include <mach/csp/mm_io.h>
-
-static void bcmring_mask_irq0(struct irq_data *d)
-{
-        writel(1 << (d->irq - IRQ_INTC0_START),
-               MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq0(struct irq_data *d)
-{
-        writel(1 << (d->irq - IRQ_INTC0_START),
-               MM_IO_BASE_INTC0 + INTCHW_INTENABLE);
-}
-
-static void bcmring_mask_irq1(struct irq_data *d)
-{
-        writel(1 << (d->irq - IRQ_INTC1_START),
-               MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq1(struct irq_data *d)
-{
-        writel(1 << (d->irq - IRQ_INTC1_START),
-               MM_IO_BASE_INTC1 + INTCHW_INTENABLE);
-}
-
-static void bcmring_mask_irq2(struct irq_data *d)
-{
-        writel(1 << (d->irq - IRQ_SINTC_START),
-               MM_IO_BASE_SINTC + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq2(struct irq_data *d)
-{
-        writel(1 << (d->irq - IRQ_SINTC_START),
-               MM_IO_BASE_SINTC + INTCHW_INTENABLE);
-}
-
-static struct irq_chip bcmring_irq0_chip = {
-        .name = "ARM-INTC0",
-        .irq_ack = bcmring_mask_irq0,
-        .irq_mask = bcmring_mask_irq0,  /* mask a specific interrupt, blocking its delivery. */
-        .irq_unmask = bcmring_unmask_irq0,      /* unmaks an interrupt */
-};
-
-static struct irq_chip bcmring_irq1_chip = {
-        .name = "ARM-INTC1",
-        .irq_ack = bcmring_mask_irq1,
-        .irq_mask = bcmring_mask_irq1,
-        .irq_unmask = bcmring_unmask_irq1,
-};
-
-static struct irq_chip bcmring_irq2_chip = {
-        .name = "ARM-SINTC",
-        .irq_ack = bcmring_mask_irq2,
-        .irq_mask = bcmring_mask_irq2,
-        .irq_unmask = bcmring_unmask_irq2,
-};
-
-static void vic_init(void __iomem *base, struct irq_chip *chip,
-                     unsigned int irq_start, unsigned int vic_sources)
-{
-        unsigned int i;
-        for (i = 0; i < 32; i++) {
-                unsigned int irq = irq_start + i;
-                irq_set_chip(irq, chip);
-                irq_set_chip_data(irq, base);
-
-                if (vic_sources & (1 << i)) {
-                        irq_set_handler(irq, handle_level_irq);
-                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-                }
-        }
-        writel(0, base + INTCHW_INTSELECT);
-        writel(0, base + INTCHW_INTENABLE);
-        writel(~0, base + INTCHW_INTENCLEAR);
-        writel(0, base + INTCHW_IRQSTATUS);
-        writel(~0, base + INTCHW_SOFTINTCLEAR);
-}
-
-void __init bcmring_init_irq(void)
-{
-        vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip,
-                 IRQ_INTC0_START, IRQ_INTC0_VALID_MASK);
-        vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip,
-                 IRQ_INTC1_START, IRQ_INTC1_VALID_MASK);
-        vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip,
-                 IRQ_SINTC_START, IRQ_SINTC_VALID_MASK);
-
-        /* special cases */
-        if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
-                irq_set_handler(IRQ_GPIO0, handle_simple_irq);
-        }
-        if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
-                irq_set_handler(IRQ_GPIO1, handle_simple_irq);
-        }
-}
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
deleted file mode 100644
index 33824a81cac4..000000000000
--- a/arch/arm/mach-bcmring/mm.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-
-#define IO_DESC(va, sz) { .virtual = (unsigned long)va, \
-        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
-        .length = sz, \
-        .type = MT_DEVICE }
-
-#define MEM_DESC(va, sz) { .virtual = (unsigned long)va, \
-        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
-        .length = sz, \
-        .type = MT_MEMORY }
-
-static struct map_desc bcmring_io_desc[] __initdata = {
-        IO_DESC(MM_IO_BASE_NAND, SZ_64K),       /* phys:0x28000000-0x28000FFF  virt:0xE8000000-0xE8000FFF  size:0x00010000 */
-        IO_DESC(MM_IO_BASE_UMI, SZ_64K),        /* phys:0x2C000000-0x2C000FFF  virt:0xEC000000-0xEC000FFF  size:0x00010000 */
-
-        IO_DESC(MM_IO_BASE_BROM, SZ_64K),       /* phys:0x30000000-0x3000FFFF  virt:0xF3000000-0xF300FFFF  size:0x00010000 */
-        MEM_DESC(MM_IO_BASE_ARAM, SZ_1M),       /* phys:0x31000000-0x31FFFFFF  virt:0xF3100000-0xF31FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_DMA0, SZ_1M),        /* phys:0x32000000-0x32FFFFFF  virt:0xF3200000-0xF32FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_DMA1, SZ_1M),        /* phys:0x33000000-0x33FFFFFF  virt:0xF3300000-0xF33FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_ESW, SZ_1M), /* phys:0x34000000-0x34FFFFFF  virt:0xF3400000-0xF34FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_CLCD, SZ_1M),        /* phys:0x35000000-0x35FFFFFF  virt:0xF3500000-0xF35FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_APM, SZ_1M), /* phys:0x36000000-0x36FFFFFF  virt:0xF3600000-0xF36FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_SPUM, SZ_1M),        /* phys:0x37000000-0x37FFFFFF  virt:0xF3700000-0xF37FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M),    /* phys:0x38000000-0x38FFFFFF  virt:0xF3800000-0xF38FFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M),    /* phys:0x3A000000-0x3AFFFFFF  virt:0xF3A00000-0xF3AFFFFF  size:0x01000000 */
-
-        IO_DESC(MM_IO_BASE_VRAM, SZ_64K),       /* phys:0x40000000-0x4000FFFF  virt:0xF4000000-0xF400FFFF  size:0x00010000 */
-        IO_DESC(MM_IO_BASE_CHIPC, SZ_16M),      /* phys:0x80000000-0x80FFFFFF  virt:0xF8000000-0xF8FFFFFF  size:0x01000000 */
-        IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
-                SZ_16M),        /* phys:0x0F000000-0x0FFFFFFF  virt:0xF0000000-0xF0FFFFFF  size:0x01000000 */
-};
-
-void __init bcmring_map_io(void)
-{
-
-        iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
-        /* Maximum DMA memory allowed is 14M */
-        init_consistent_dma_size(14 << 20);
-}
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
deleted file mode 100644
index 59412903466e..000000000000
--- a/arch/arm/mach-bcmring/timer.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/types.h>
-#include <linux/module.h>
-#include <mach/csp/tmrHw.h>
-
-#include <mach/timer.h>
-/* The core.c file initializes timers 1 and 3 as a linux clocksource. */
-/* The real time clock should probably be the real linux clocksource. */
-/* In the meantime, this file should agree with core.c as to the */
-/* profiling timer. If the clocksource is moved to rtc later, then */
-/* we can init the profiling timer here instead. */
-
-/* Timer 1 provides 25MHz resolution syncrhonized to scheduling and APM timing */
-/* Timer 3 provides bus freqeuncy sychronized to ACLK, but spread spectrum will */
-/* affect synchronization with scheduling and APM timing. */
-
-#define PROF_TIMER 1
-
-timer_tick_rate_t timer_get_tick_rate(void)
-{
-        return tmrHw_getCountRate(PROF_TIMER);
-}
-
-timer_tick_count_t timer_get_tick_count(void)
-{
-        return tmrHw_GetCurrentCount(PROF_TIMER);       /* change downcounter to upcounter */
-}
-
-timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks)
-{
-        static int tickRateMsec;
-
-        if (tickRateMsec == 0) {
-                tickRateMsec = timer_get_tick_rate() / 1000;
-        }
-
-        return ticks / tickRateMsec;
-}
-
-timer_msec_t timer_get_msec(void)
-{
-        return timer_ticks_to_msec(timer_get_tick_count());
-}
-
-EXPORT_SYMBOL(timer_get_tick_count);
-EXPORT_SYMBOL(timer_ticks_to_msec);
-EXPORT_SYMBOL(timer_get_tick_rate);
-EXPORT_SYMBOL(timer_get_msec);
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index ea036d621581..e6135363765a 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -16,12 +16,6 @@ config ARCH_CDB89712
           The board includes 2 serial ports, Ethernet, IRDA, and expansion
           headers.  It comes with 16 MB SDRAM and 8 MB flash ROM.
 
-config ARCH_CEIVA
-        bool "CEIVA"
-        help
-          Say Y here if you intend to run this kernel on the Ceiva/Polaroid
-          PhotoMax Digital Picture Frame.
-
 config ARCH_CLEP7312
         bool "CLEP7312"
         help
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index f2f0256232e3..6da6940b3656 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -9,12 +9,9 @@ obj-m			:=
 obj-n                   :=
 obj-                    :=
 
-obj-$(CONFIG_ARCH_CEIVA) += ceiva.o
 obj-$(CONFIG_ARCH_AUTCPU12) += autcpu12.o
 obj-$(CONFIG_ARCH_CDB89712) += cdb89712.o
 obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o
 obj-$(CONFIG_ARCH_EDB7211)  += edb7211-arch.o edb7211-mm.o
 obj-$(CONFIG_ARCH_FORTUNET) += fortunet.o
 obj-$(CONFIG_ARCH_P720T)    += p720t.o
-leds-$(CONFIG_ARCH_P720T)   += p720t-leds.o
-obj-$(CONFIG_LEDS)          += $(leds-y)
diff --git a/arch/arm/mach-clps711x/ceiva.c b/arch/arm/mach-clps711x/ceiva.c
deleted file mode 100644
index a70147e347ac..000000000000
--- a/arch/arm/mach-clps711x/ceiva.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/arch-ceiva.c
- *
- *  Copyright (C) 2002, Rob Scott <rscott@mtrob.fdns.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/string.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <linux/kernel.h>
-
-#include <mach/hardware.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/sizes.h>
-
-#include <asm/mach/map.h>
-
-#include "common.h"
-
-static struct map_desc ceiva_io_desc[] __initdata = {
-        /* SED1355 controlled video RAM & registers */
-        {
-                .virtual        = CEIVA_VIRT_SED1355,
-                .pfn            = __phys_to_pfn(CEIVA_PHYS_SED1355),
-                .length         = SZ_2M,
-                .type           = MT_DEVICE
-        }
-};
-
-
-static void __init ceiva_map_io(void)
-{
-        clps711x_map_io();
-        iotable_init(ceiva_io_desc, ARRAY_SIZE(ceiva_io_desc));
-}
-
-
-MACHINE_START(CEIVA, "CEIVA/Polaroid Photo MAX Digital Picture Frame")
-        /* Maintainer: Rob Scott */
-        .atag_offset    = 0x100,
-        .map_io         = ceiva_map_io,
-        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
-        .restart        = clps711x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index f15293bd7974..509243d89a32 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -19,24 +19,25 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#include <linux/kernel.h>
-#include <linux/mm.h>
+#include <linux/io.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
-#include <linux/io.h>
 #include <linux/irq.h>
-#include <linux/sched.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
 
 #include <asm/sizes.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/leds.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
 
+#include <mach/hardware.h>
+
+static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
+                  *clk_tint, *clk_spi;
+static unsigned long latch;
+
 /*
  * This maps the generic CLPS711x registers
  */
@@ -166,8 +167,8 @@ void __init clps711x_init_irq(void)
 static unsigned long clps711x_gettimeoffset(void)
 {
         unsigned long hwticks;
-        hwticks = LATCH - (clps_readl(TC2D) & 0xffff);  /* since last underflow */
-        return (hwticks * (tick_nsec / 1000)) / LATCH;
+        hwticks = latch - (clps_readl(TC2D) & 0xffff);
+        return (hwticks * (tick_nsec / 1000)) / latch;
 }
 
 /*
@@ -185,15 +186,71 @@ static struct irqaction clps711x_timer_irq = {
         .handler        = p720t_timer_interrupt,
 };
 
+static void add_fixed_clk(struct clk *clk, const char *name, int rate)
+{
+        clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+        clk_register_clkdev(clk, name, NULL);
+}
+
 static void __init clps711x_timer_init(void)
 {
-        unsigned int syscon;
+        int osc, ext, pll, cpu, bus, timl, timh, uart, spi;
+        u32 tmp;
+
+        osc = 3686400;
+        ext = 13000000;
+
+        tmp = clps_readl(PLLR) >> 24;
+        if (tmp)
+                pll = (osc * tmp) / 2;
+        else
+                pll = 73728000; /* Default value */
+
+        tmp = clps_readl(SYSFLG2);
+        if (tmp & SYSFLG2_CKMODE) {
+                cpu = ext;
+                bus = cpu;
+                spi = 135400;
+        } else {
+                cpu = pll;
+                if (cpu >= 36864000)
+                        bus = cpu / 2;
+                else
+                        bus = 36864000 / 2;
+                spi = cpu / 576;
+        }
+
+        uart = bus / 10;
+
+        if (tmp & SYSFLG2_CKMODE) {
+                tmp = clps_readl(SYSCON2);
+                if (tmp & SYSCON2_OSTB)
+                        timh = ext / 26;
+                else
+                        timh = 541440;
+        } else
+                timh = cpu / 144;
+
+        timl = timh / 256;
+
+        /* All clocks are fixed */
+        add_fixed_clk(clk_pll, "pll", pll);
+        add_fixed_clk(clk_bus, "bus", bus);
+        add_fixed_clk(clk_uart, "uart", uart);
+        add_fixed_clk(clk_timerl, "timer_lf", timl);
+        add_fixed_clk(clk_timerh, "timer_hf", timh);
+        add_fixed_clk(clk_tint, "tint", 64);
+        add_fixed_clk(clk_spi, "spi", spi);
+
+        pr_info("CPU frequency set at %i Hz.\n", cpu);
+
+        latch = (timh + HZ / 2) / HZ;
 
-        syscon = clps_readl(SYSCON1);
-        syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
-        clps_writel(syscon, SYSCON1);
+        tmp = clps_readl(SYSCON1);
+        tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
+        clps_writel(tmp, SYSCON1);
 
-        clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
+        clps_writel(latch - 1, TC2D);
 
         setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 1dd806f2847e..c82e21ca49c7 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -31,8 +31,8 @@
 #define PBDDR           (0x0041)
 #define PCDDR           (0x0042)
 #define PDDDR           (0x0043)
-#define PEDR            (0x0080)
-#define PEDDR           (0x00c0)
+#define PEDR            (0x0083)
+#define PEDDR           (0x00c3)
 #define SYSCON1         (0x0100)
 #define SYSFLG1         (0x0140)
 #define MEMCFG1         (0x0180)
@@ -77,7 +77,7 @@
 #define KBDEOI          (0x1700)
 
 #define DAIR            (0x2000)
-#define DAIR0           (0x2040)
+#define DAIDR0          (0x2040)
 #define DAIDR1          (0x2080)
 #define DAIDR2          (0x20c0)
 #define DAISR           (0x2100)
@@ -191,8 +191,7 @@
 #define UBRLCR_WRDLEN8          (3 << 17)
 #define UBRLCR_WRDLEN_MASK      (3 << 17)
 
-#define SYNCIO_FRMLEN(x)        (((x) & 0x3f) << 7)
-#define SYNCIO_CFGLEN(x)        ((x) & 0x7f)
+#define SYNCIO_FRMLEN(x)        (((x) & 0x1f) << 8)
 #define SYNCIO_SMCKEN           (1 << 13)
 #define SYNCIO_TXFRMEN          (1 << 14)
 
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S
index 118b3d930573..cb3684f8dae0 100644
--- a/arch/arm/mach-clps711x/include/mach/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S
@@ -28,17 +28,11 @@
                 .endm
 
                 .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #0x0140]     @ SYSFLGx
-                tst     \rd, #1 << 11           @ UBUSYx
-                bne     1001b
                 .endm
 
                 .macro  busyuart,rd,rx
-                tst     \rx, #0x1000            @ UART2 does not have CTS here
-                bne     1002f
 1001:           ldr     \rd, [\rx, #0x0140]     @ SYSFLGx
-                tst     \rd, #1 << 8            @ CTS
+                tst     \rd, #1 << 11           @ UBUSYx
                 bne     1001b
-1002:
                 .endm
 
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 13a64fcd7dd1..8497775d6ee5 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -116,7 +116,6 @@
 
 #endif /* CONFIG_ARCH_EDB7211 */
 
-
 /*
  * Relevant bits in port D, which controls power to the various parts of
  * the LCD on the EDB7211.
@@ -125,51 +124,4 @@
 #define EDB_PD2_LCDEN           (1<<2)
 #define EDB_PD3_LCDBL           (1<<3)
 
-
-#if defined (CONFIG_ARCH_CEIVA)
-
-/*
- * The two flash banks are wired to chip selects 0 and 1. This is the mapping
- * for them.
- *
- * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
- * in jumpered boot mode.
- */
-#define CEIVA_PHYS_FLASH1       CS0_PHYS_BASE   /* physical */
-#define CEIVA_PHYS_FLASH2       CS1_PHYS_BASE   /* physical */
-
-#define CEIVA_VIRT_FLASH1       (0xfa000000)    /* virtual */
-#define CEIVA_VIRT_FLASH2       (0xfb000000)    /* virtual */
-
-#define CEIVA_FLASH_SIZE        0x100000
-#define CEIVA_FLASH_WIDTH       2
-
-/*
- * SED1355 LCD controller
- */
-#define CEIVA_PHYS_SED1355      CS2_PHYS_BASE
-#define CEIVA_VIRT_SED1355      (0xfc000000)
-
-/*
- * Relevant bits in port D, which controls power to the various parts of
- * the LCD on the Ceiva Photo Max, and reset to the LCD controller.
- */
-
-// Reset line to SED1355 (must be high to operate)
-#define CEIVA_PD1_LCDRST        (1<<1)
-// LCD panel enable (set to one, to enable LCD)
-#define CEIVA_PD4_LCDEN         (1<<4)
-// Backlight (set to one, to turn on backlight
-#define CEIVA_PD5_LCDBL         (1<<5)
-
-/*
- * Relevant bits in port B, which report the status of the buttons.
- */
-
-// White button
-#define CEIVA_PB4_WHT_BTN       (1<<4)
-// Black button
-#define CEIVA_PB0_BLK_BTN       (1<<0)
-#endif // #if defined (CONFIG_ARCH_CEIVA)
-
 #endif
diff --git a/arch/arm/mach-clps711x/include/mach/timex.h b/arch/arm/mach-clps711x/include/mach/timex.h
index ac8823ccff93..de6fd192d1c3 100644
--- a/arch/arm/mach-clps711x/include/mach/timex.h
+++ b/arch/arm/mach-clps711x/include/mach/timex.h
@@ -1,23 +1,2 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/timex.h
- *
- *  Prospector 720T architecture timex specifications
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
+/* Bogus value */
 #define CLOCK_TICK_RATE 512000
diff --git a/arch/arm/mach-clps711x/p720t-leds.c b/arch/arm/mach-clps711x/p720t-leds.c
deleted file mode 100644
index bbc449fbe14a..000000000000
--- a/arch/arm/mach-clps711x/p720t-leds.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/leds.c
- *
- *  Integrator LED control routines
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-static void p720t_leds_event(led_event_t ledevt)
-{
-        unsigned long flags;
-        u32 pddr;
-
-        local_irq_save(flags);
-        switch(ledevt) {
-        case led_idle_start:
-                break;
-
-        case led_idle_end:
-                break;
-
-        case led_timer:
-                pddr = clps_readb(PDDR);
-                clps_writeb(pddr ^ 1, PDDR);
-                break;
-
-        default:
-                break;
-        }
-
-        local_irq_restore(flags);
-}
-
-static int __init leds_init(void)
-{
-        if (machine_is_p720t())
-                leds_event = p720t_leds_event;
-
-        return 0;
-}
-
-arch_initcall(leds_init);
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index f266d90b9efc..b752b586fc2f 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -23,6 +23,8 @@
 #include <linux/string.h>
 #include <linux/mm.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <mach/hardware.h>
 #include <asm/pgtable.h>
@@ -34,6 +36,8 @@
 #include <asm/mach/map.h>
 #include <mach/syspld.h>
 
+#include <asm/hardware/clps7111.h>
+
 #include "common.h"
 
 /*
@@ -107,6 +111,64 @@ static void __init p720t_init_early(void)
         }
 }
 
+/*
+ * LED controled by CPLD
+ */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+static void p720t_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
+{
+        u8 reg = clps_readb(PDDR);
+
+        if (b != LED_OFF)
+                reg |= 0x1;
+        else
+                reg &= ~0x1;
+
+        clps_writeb(reg, PDDR);
+}
+
+static enum led_brightness p720t_led_get(struct led_classdev *cdev)
+{
+        u8 reg = clps_readb(PDDR);
+
+        return (reg & 0x1) ? LED_FULL : LED_OFF;
+}
+
+static int __init p720t_leds_init(void)
+{
+
+        struct led_classdev *cdev;
+        int ret;
+
+        if (!machine_is_p720t())
+                return -ENODEV;
+
+        cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
+        if (!cdev)
+                return -ENOMEM;
+
+        cdev->name = "p720t:0";
+        cdev->brightness_set = p720t_led_set;
+        cdev->brightness_get = p720t_led_get;
+        cdev->default_trigger = "heartbeat";
+
+        ret = led_classdev_register(NULL, cdev);
+        if (ret < 0) {
+                kfree(cdev);
+                return ret;
+        }
+
+        return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(p720t_leds_init);
+#endif
+
 MACHINE_START(P720T, "ARM-Prospector720T")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
         .atag_offset    = 0x100,
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index ac4e003ad863..be3099733b1f 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -88,7 +88,7 @@ static struct davinci_mmc_config mmc_config = {
         .version        = MMC_CTLR_VERSION_1,
 };
 
-static const short sdio1_pins[] __initdata = {
+static const short sdio1_pins[] __initconst = {
         TNETV107X_SDIO1_CLK_1,          TNETV107X_SDIO1_CMD_1,
         TNETV107X_SDIO1_DATA0_1,        TNETV107X_SDIO1_DATA1_1,
         TNETV107X_SDIO1_DATA2_1,        TNETV107X_SDIO1_DATA3_1,
@@ -96,12 +96,12 @@ static const short sdio1_pins[] __initdata = {
         -1
 };
 
-static const short uart1_pins[] __initdata = {
+static const short uart1_pins[] __initconst = {
         TNETV107X_UART1_RD,             TNETV107X_UART1_TD,
         -1
 };
 
-static const short ssp_pins[] __initdata = {
+static const short ssp_pins[] __initconst = {
         TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
         TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
         TNETV107X_SSP1_3, -1
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index deee5c2da754..510648e0394b 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -838,7 +838,7 @@ static const struct mux_config da830_pins[] = {
 #endif
 };
 
-const short da830_emif25_pins[] __initdata = {
+const short da830_emif25_pins[] __initconst = {
         DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
         DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
         DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11,
@@ -853,19 +853,19 @@ const short da830_emif25_pins[] __initdata = {
         -1
 };
 
-const short da830_spi0_pins[] __initdata = {
+const short da830_spi0_pins[] __initconst = {
         DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA,
         DA830_NSPI0_SCS_0,
         -1
 };
 
-const short da830_spi1_pins[] __initdata = {
+const short da830_spi1_pins[] __initconst = {
         DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA,
         DA830_NSPI1_SCS_0,
         -1
 };
 
-const short da830_mmc_sd_pins[] __initdata = {
+const short da830_mmc_sd_pins[] __initconst = {
         DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
         DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
         DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
@@ -873,32 +873,32 @@ const short da830_mmc_sd_pins[] __initdata = {
         -1
 };
 
-const short da830_uart0_pins[] __initdata = {
+const short da830_uart0_pins[] __initconst = {
         DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD,
         -1
 };
 
-const short da830_uart1_pins[] __initdata = {
+const short da830_uart1_pins[] __initconst = {
         DA830_UART1_RXD, DA830_UART1_TXD,
         -1
 };
 
-const short da830_uart2_pins[] __initdata = {
+const short da830_uart2_pins[] __initconst = {
         DA830_UART2_RXD, DA830_UART2_TXD,
         -1
 };
 
-const short da830_usb20_pins[] __initdata = {
+const short da830_usb20_pins[] __initconst = {
         DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN,
         -1
 };
 
-const short da830_usb11_pins[] __initdata = {
+const short da830_usb11_pins[] __initconst = {
         DA830_USB_REFCLKIN,
         -1
 };
 
-const short da830_uhpi_pins[] __initdata = {
+const short da830_uhpi_pins[] __initconst = {
         DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3,
         DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7,
         DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11,
@@ -909,14 +909,14 @@ const short da830_uhpi_pins[] __initdata = {
         -1
 };
 
-const short da830_cpgmac_pins[] __initdata = {
+const short da830_cpgmac_pins[] __initconst = {
         DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV,
         DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK,
         DA830_MDIO_D,
         -1
 };
 
-const short da830_emif3c_pins[] __initdata = {
+const short da830_emif3c_pins[] __initconst = {
         DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0,
         DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1,
         DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2,
@@ -935,7 +935,7 @@ const short da830_emif3c_pins[] __initdata = {
         -1
 };
 
-const short da830_mcasp0_pins[] __initdata = {
+const short da830_mcasp0_pins[] __initconst = {
         DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0,
         DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0,
         DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3,
@@ -945,7 +945,7 @@ const short da830_mcasp0_pins[] __initdata = {
         -1
 };
 
-const short da830_mcasp1_pins[] __initdata = {
+const short da830_mcasp1_pins[] __initconst = {
         DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1,
         DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1,
         DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3,
@@ -954,24 +954,24 @@ const short da830_mcasp1_pins[] __initdata = {
         -1
 };
 
-const short da830_mcasp2_pins[] __initdata = {
+const short da830_mcasp2_pins[] __initconst = {
         DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2,
         DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2,
         DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3,
         -1
 };
 
-const short da830_i2c0_pins[] __initdata = {
+const short da830_i2c0_pins[] __initconst = {
         DA830_I2C0_SDA, DA830_I2C0_SCL,
         -1
 };
 
-const short da830_i2c1_pins[] __initdata = {
+const short da830_i2c1_pins[] __initconst = {
         DA830_I2C1_SCL, DA830_I2C1_SDA,
         -1
 };
 
-const short da830_lcdcntl_pins[] __initdata = {
+const short da830_lcdcntl_pins[] __initconst = {
         DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3,
         DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7,
         DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11,
@@ -981,34 +981,34 @@ const short da830_lcdcntl_pins[] __initdata = {
         -1
 };
 
-const short da830_pwm_pins[] __initdata = {
+const short da830_pwm_pins[] __initconst = {
         DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A,
         DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ,
         DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A,
         -1
 };
 
-const short da830_ecap0_pins[] __initdata = {
+const short da830_ecap0_pins[] __initconst = {
         DA830_ECAP0_APWM0,
         -1
 };
 
-const short da830_ecap1_pins[] __initdata = {
+const short da830_ecap1_pins[] __initconst = {
         DA830_ECAP1_APWM1,
         -1
 };
 
-const short da830_ecap2_pins[] __initdata = {
+const short da830_ecap2_pins[] __initconst = {
         DA830_ECAP2_APWM2,
         -1
 };
 
-const short da830_eqep0_pins[] __initdata = {
+const short da830_eqep0_pins[] __initconst = {
         DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B,
         -1
 };
 
-const short da830_eqep1_pins[] __initdata = {
+const short da830_eqep1_pins[] __initconst = {
         DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B,
         -1
 };
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index b44dc844e15e..6676dee7104e 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -576,17 +576,17 @@ static const struct mux_config da850_pins[] = {
 #endif
 };
 
-const short da850_i2c0_pins[] __initdata = {
+const short da850_i2c0_pins[] __initconst = {
         DA850_I2C0_SDA, DA850_I2C0_SCL,
         -1
 };
 
-const short da850_i2c1_pins[] __initdata = {
+const short da850_i2c1_pins[] __initconst = {
         DA850_I2C1_SCL, DA850_I2C1_SDA,
         -1
 };
 
-const short da850_lcdcntl_pins[] __initdata = {
+const short da850_lcdcntl_pins[] __initconst = {
         DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
         DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
         DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
diff --git a/arch/arm/mach-ebsa110/Makefile b/arch/arm/mach-ebsa110/Makefile
index 6520ac835802..935e4af01a27 100644
--- a/arch/arm/mach-ebsa110/Makefile
+++ b/arch/arm/mach-ebsa110/Makefile
@@ -4,9 +4,7 @@
 
 # Object file lists.
 
-obj-y                   := core.o io.o
+obj-y                   := core.o io.o leds.o
 obj-m                   :=
 obj-n                   :=
 obj-                    :=
-
-obj-$(CONFIG_LEDS)      += leds.o
diff --git a/arch/arm/mach-ebsa110/leds.c b/arch/arm/mach-ebsa110/leds.c
index 99e14e362500..0398258c20cd 100644
--- a/arch/arm/mach-ebsa110/leds.c
+++ b/arch/arm/mach-ebsa110/leds.c
@@ -1,52 +1,71 @@
 /*
- *  linux/arch/arm/mach-ebsa110/leds.c
+ * Driver for the LED found on the EBSA110 machine
+ * Based on Versatile and RealView machine LED code
  *
- *  Copyright (C) 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  EBSA-110 LED control routines.  We use the led as follows:
- *
- *   - Red - toggles state every 50 timer interrupts
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Bryan Wu <bryan.wu@canonical.com>
  */
-#include <linux/module.h>
-#include <linux/spinlock.h>
+#include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
-#include <mach/hardware.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 
 #include "core.h"
 
-static spinlock_t leds_lock;
-
-static void ebsa110_leds_event(led_event_t ledevt)
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+static void ebsa110_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
 {
-        unsigned long flags;
+        u8 reg = __raw_readb(SOFT_BASE);
 
-        spin_lock_irqsave(&leds_lock, flags);
+        if (b != LED_OFF)
+                reg |= 0x80;
+        else
+                reg &= ~0x80;
 
-        switch(ledevt) {
-        case led_timer:
-                *(volatile unsigned char *)SOFT_BASE ^= 128;
-                break;
+        __raw_writeb(reg, SOFT_BASE);
+}
 
-        default:
-                break;
-        }
+static enum led_brightness ebsa110_led_get(struct led_classdev *cdev)
+{
+        u8 reg = __raw_readb(SOFT_BASE);
 
-        spin_unlock_irqrestore(&leds_lock, flags);
+        return (reg & 0x80) ? LED_FULL : LED_OFF;
 }
 
-static int __init leds_init(void)
+static int __init ebsa110_leds_init(void)
 {
-        if (machine_is_ebsa110())
-                leds_event = ebsa110_leds_event;
+
+        struct led_classdev *cdev;
+        int ret;
+
+        if (!machine_is_ebsa110())
+                return -ENODEV;
+
+        cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
+        if (!cdev)
+                return -ENOMEM;
+
+        cdev->name = "ebsa110:0";
+        cdev->brightness_set = ebsa110_led_set;
+        cdev->brightness_get = ebsa110_led_get;
+        cdev->default_trigger = "heartbeat";
+
+        ret = led_classdev_register(NULL, cdev);
+        if (ret < 0) {
+                kfree(cdev);
+                return ret;
+        }
 
         return 0;
 }
 
-__initcall(leds_init);
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(ebsa110_leds_init);
+#endif
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index a472777e9eba..41383bf03d4b 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/sizes.h>
 
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index 437c34111155..7fd705b5efe4 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/sizes.h>
 
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 75cab2d7ec73..3c4c233391dc 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -21,7 +21,6 @@
 #include <linux/mtd/partitions.h>
 
 #include <mach/hardware.h>
-#include <mach/ts72xx.h>
 
 #include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
@@ -29,30 +28,31 @@
 #include <asm/mach/arch.h>
 
 #include "soc.h"
+#include "ts72xx.h"
 
 static struct map_desc ts72xx_io_desc[] __initdata = {
         {
-                .virtual        = TS72XX_MODEL_VIRT_BASE,
+                .virtual        = (unsigned long)TS72XX_MODEL_VIRT_BASE,
                 .pfn            = __phys_to_pfn(TS72XX_MODEL_PHYS_BASE),
                 .length         = TS72XX_MODEL_SIZE,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = TS72XX_OPTIONS_VIRT_BASE,
+                .virtual        = (unsigned long)TS72XX_OPTIONS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(TS72XX_OPTIONS_PHYS_BASE),
                 .length         = TS72XX_OPTIONS_SIZE,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = TS72XX_OPTIONS2_VIRT_BASE,
+                .virtual        = (unsigned long)TS72XX_OPTIONS2_VIRT_BASE,
                 .pfn            = __phys_to_pfn(TS72XX_OPTIONS2_PHYS_BASE),
                 .length         = TS72XX_OPTIONS2_SIZE,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = TS72XX_RTC_INDEX_VIRT_BASE,
+                .virtual        = (unsigned long)TS72XX_RTC_INDEX_VIRT_BASE,
                 .pfn            = __phys_to_pfn(TS72XX_RTC_INDEX_PHYS_BASE),
                 .length         = TS72XX_RTC_INDEX_SIZE,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = TS72XX_RTC_DATA_VIRT_BASE,
+                .virtual        = (unsigned long)TS72XX_RTC_DATA_VIRT_BASE,
                 .pfn            = __phys_to_pfn(TS72XX_RTC_DATA_PHYS_BASE),
                 .length         = TS72XX_RTC_DATA_SIZE,
                 .type           = MT_DEVICE,
diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/ts72xx.h
index f1397a13e76b..071feaa30adc 100644
--- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h
+++ b/arch/arm/mach-ep93xx/ts72xx.h
@@ -14,7 +14,7 @@
  */
 
 #define TS72XX_MODEL_PHYS_BASE          0x22000000
-#define TS72XX_MODEL_VIRT_BASE          0xfebff000
+#define TS72XX_MODEL_VIRT_BASE          IOMEM(0xfebff000)
 #define TS72XX_MODEL_SIZE               0x00001000
 
 #define TS72XX_MODEL_TS7200             0x00
@@ -26,7 +26,7 @@
 
 
 #define TS72XX_OPTIONS_PHYS_BASE        0x22400000
-#define TS72XX_OPTIONS_VIRT_BASE        0xfebfe000
+#define TS72XX_OPTIONS_VIRT_BASE        IOMEM(0xfebfe000)
 #define TS72XX_OPTIONS_SIZE             0x00001000
 
 #define TS72XX_OPTIONS_COM2_RS485       0x02
@@ -34,18 +34,18 @@
 
 
 #define TS72XX_OPTIONS2_PHYS_BASE       0x22800000
-#define TS72XX_OPTIONS2_VIRT_BASE       0xfebfd000
+#define TS72XX_OPTIONS2_VIRT_BASE       IOMEM(0xfebfd000)
 #define TS72XX_OPTIONS2_SIZE            0x00001000
 
 #define TS72XX_OPTIONS2_TS9420          0x04
 #define TS72XX_OPTIONS2_TS9420_BOOT     0x02
 
 
-#define TS72XX_RTC_INDEX_VIRT_BASE      0xfebf9000
+#define TS72XX_RTC_INDEX_VIRT_BASE      IOMEM(0xfebf9000)
 #define TS72XX_RTC_INDEX_PHYS_BASE      0x10800000
 #define TS72XX_RTC_INDEX_SIZE           0x00001000
 
-#define TS72XX_RTC_DATA_VIRT_BASE       0xfebf8000
+#define TS72XX_RTC_DATA_VIRT_BASE       IOMEM(0xfebf8000)
 #define TS72XX_RTC_DATA_PHYS_BASE       0x11700000
 #define TS72XX_RTC_DATA_SIZE            0x00001000
 
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index b5b4c8c9db11..4372075c551f 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -221,6 +221,7 @@ config MACH_SMDKV310
         select EXYNOS4_SETUP_KEYPAD
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
+        select S3C24XX_PWM
         help
           Machine support for Samsung SMDKV310
 
@@ -348,6 +349,7 @@ config MACH_ORIGEN
         select EXYNOS4_SETUP_FIMD0
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
+        select S3C24XX_PWM
         help
           Machine support for ORIGEN based on Samsung EXYNOS4210
 
@@ -383,6 +385,7 @@ config MACH_SMDK4212
         select EXYNOS4_SETUP_KEYPAD
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
+        select S3C24XX_PWM
         help
           Machine support for Samsung SMDK4212
 
@@ -405,6 +408,8 @@ config MACH_EXYNOS4_DT
         select USE_OF
         select ARM_AMBA
         select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
+        select PINCTRL
+        select PINCTRL_EXYNOS4
         help
           Machine support for Samsung Exynos4 machine with device tree enabled.
           Select this if a fdt blob is available for the Exynos4 SoC based board.
@@ -418,8 +423,8 @@ config MACH_EXYNOS5_DT
         select USE_OF
         select ARM_AMBA
         help
-          Machine support for Samsung Exynos4 machine with device tree enabled.
-          Select this if a fdt blob is available for the EXYNOS4 SoC based board.
+          Machine support for Samsung EXYNOS5 machine with device tree enabled.
+          Select this if a fdt blob is available for the EXYNOS5 SoC based board.
 
 if ARCH_EXYNOS4
 
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 2f51293c1875..6a45c9a9abe9 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -501,6 +501,10 @@ static struct clk exynos4_init_clocks_off[] = {
                 .enable         = exynos4_clk_ip_cam_ctrl,
                 .ctrlbit        = (1 << 3),
         }, {
+                .name           = "tsi",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
                 .name           = "hsmmc",
                 .devname        = "exynos4-sdhci.0",
                 .parent         = &exynos4_clk_aclk_133.clk,
@@ -530,6 +534,14 @@ static struct clk exynos4_init_clocks_off[] = {
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 9),
         }, {
+                .name           = "onenand",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 15),
+        }, {
+                .name           = "nfcon",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
                 .name           = "dac",
                 .devname        = "s5p-sdo",
                 .enable         = exynos4_clk_ip_tv_ctrl,
@@ -615,6 +627,25 @@ static struct clk exynos4_init_clocks_off[] = {
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 21),
         }, {
+                .name           = "pcm",
+                .devname        = "samsung-pcm.1",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 22),
+        }, {
+                .name           = "pcm",
+                .devname        = "samsung-pcm.2",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 23),
+        }, {
+                .name           = "slimbus",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "spdif",
+                .devname        = "samsung-spdif",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 26),
+        }, {
                 .name           = "ac97",
                 .devname        = "samsung-ac97",
                 .enable         = exynos4_clk_ip_peril_ctrl,
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 3b00e299b624..c44ca1ee1b8d 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -547,6 +547,68 @@ static struct clksrc_clk exynos5_clk_aclk_66 = {
         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
 };
 
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
+        .clk    = {
+                .name           = "mout_aclk_300_gscl_mid",
+        },
+        .sources = &exynos5_clkset_aclk,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
+        [0] = &exynos5_clk_sclk_vpll.clk,
+        [1] = &exynos5_clk_mout_cpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
+        .sources        = exynos5_clkset_aclk_300_mid1_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
+        .clk    = {
+                .name           = "mout_aclk_300_gscl_mid1",
+        },
+        .sources = &exynos5_clkset_aclk_300_gscl_mid1,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
+        [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
+        [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
+        .sources        = exynos5_clkset_aclk_300_gscl_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
+        .clk    = {
+                .name           = "mout_aclk_300_gscl",
+        },
+        .sources = &exynos5_clkset_aclk_300_gscl,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_gscl_300_list[] = {
+        [0] = &clk_ext_xtal_mux,
+        [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_gscl_300 = {
+        .sources        = exynos5_clk_src_gscl_300_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
+        .clk    = {
+                .name           = "aclk_300_gscl",
+        },
+        .sources = &exynos5_clk_src_gscl_300,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
+};
+
 static struct clk exynos5_init_clocks_off[] = {
         {
                 .name           = "timers",
@@ -564,35 +626,30 @@ static struct clk exynos5_init_clocks_off[] = {
                 .enable         = exynos5_clk_ip_peris_ctrl,
                 .ctrlbit        = (1 << 19),
         }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.0",
+                .name           = "biu",        /* bus interface unit clock */
+                .devname        = "dw_mmc.0",
                 .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 12),
         }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.1",
+                .name           = "biu",
+                .devname        = "dw_mmc.1",
                 .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 13),
         }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.2",
+                .name           = "biu",
+                .devname        = "dw_mmc.2",
                 .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 14),
         }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.3",
+                .name           = "biu",
+                .devname        = "dw_mmc.3",
                 .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 15),
         }, {
-                .name           = "dwmci",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
                 .name           = "sata",
                 .devname        = "ahci",
                 .enable         = exynos5_clk_ip_fsys_ctrl,
@@ -755,6 +812,26 @@ static struct clk exynos5_init_clocks_off[] = {
                 .enable         = exynos5_clk_ip_peric_ctrl,
                 .ctrlbit        = (1 << 18),
         }, {
+                .name           = "gscl",
+                .devname        = "exynos-gsc.0",
+                .enable         = exynos5_clk_ip_gscl_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "gscl",
+                .devname        = "exynos-gsc.1",
+                .enable         = exynos5_clk_ip_gscl_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "gscl",
+                .devname        = "exynos-gsc.2",
+                .enable         = exynos5_clk_ip_gscl_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "gscl",
+                .devname        = "exynos-gsc.3",
+                .enable         = exynos5_clk_ip_gscl_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
                 .name           = SYSMMU_CLOCK_NAME,
                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
                 .enable         = &exynos5_clk_ip_mfc_ctrl,
@@ -882,6 +959,13 @@ static struct clk exynos5_clk_mdma1 = {
         .ctrlbit        = (1 << 4),
 };
 
+static struct clk exynos5_clk_fimd1 = {
+        .name           = "fimd",
+        .devname        = "exynos5-fb.1",
+        .enable         = exynos5_clk_ip_disp1_ctrl,
+        .ctrlbit        = (1 << 0),
+};
+
 struct clk *exynos5_clkset_group_list[] = {
         [0] = &clk_ext_xtal_mux,
         [1] = NULL,
@@ -1006,8 +1090,8 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
         .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.0",
+                .name           = "ciu",        /* card interface unit clock */
+                .devname        = "dw_mmc.0",
                 .parent         = &exynos5_clk_dout_mmc0.clk,
                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 0),
@@ -1017,8 +1101,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
         .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.1",
+                .name           = "ciu",
+                .devname        = "dw_mmc.1",
                 .parent         = &exynos5_clk_dout_mmc1.clk,
                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 4),
@@ -1028,8 +1112,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
         .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.2",
+                .name           = "ciu",
+                .devname        = "dw_mmc.2",
                 .parent         = &exynos5_clk_dout_mmc2.clk,
                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 8),
@@ -1039,8 +1123,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
         .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.3",
+                .name           = "ciu",
+                .devname        = "dw_mmc.3",
                 .parent         = &exynos5_clk_dout_mmc3.clk,
                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 12),
@@ -1111,27 +1195,21 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
 };
 
+struct clksrc_clk exynos5_clk_sclk_fimd1 = {
+        .clk    = {
+                .name           = "sclk_fimd",
+                .devname        = "exynos5-fb.1",
+                .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+};
+
 static struct clksrc_clk exynos5_clksrcs[] = {
         {
                 .clk    = {
-                        .name           = "sclk_dwmci",
-                        .parent         = &exynos5_clk_dout_mmc4.clk,
-                        .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimd",
-                        .devname        = "s3cfb.1",
-                        .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
                         .name           = "aclk_266_gscl",
                 },
                 .sources = &clk_src_gscl_266,
@@ -1216,6 +1294,10 @@ static struct clksrc_clk *exynos5_sysclks[] = {
         &exynos5_clk_aclk_266,
         &exynos5_clk_aclk_200,
         &exynos5_clk_aclk_166,
+        &exynos5_clk_aclk_300_gscl,
+        &exynos5_clk_mout_aclk_300_gscl,
+        &exynos5_clk_mout_aclk_300_gscl_mid,
+        &exynos5_clk_mout_aclk_300_gscl_mid1,
         &exynos5_clk_aclk_66_pre,
         &exynos5_clk_aclk_66,
         &exynos5_clk_dout_mmc0,
@@ -1231,12 +1313,14 @@ static struct clksrc_clk *exynos5_sysclks[] = {
         &exynos5_clk_mdout_spi0,
         &exynos5_clk_mdout_spi1,
         &exynos5_clk_mdout_spi2,
+        &exynos5_clk_sclk_fimd1,
 };
 
 static struct clk *exynos5_clk_cdev[] = {
         &exynos5_clk_pdma0,
         &exynos5_clk_pdma1,
         &exynos5_clk_mdma1,
+        &exynos5_clk_fimd1,
 };
 
 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
@@ -1265,6 +1349,7 @@ static struct clk_lookup exynos5_clk_lookup[] = {
         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
+        CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
 };
 
 static unsigned long exynos5_epll_get_rate(struct clk *clk)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4eb39cdf75ea..715b690e5009 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -980,6 +980,32 @@ static int __init exynos_init_irq_eint(void)
 {
         int irq;
 
+#ifdef CONFIG_PINCTRL_SAMSUNG
+        /*
+         * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
+         * functionality along with support for external gpio and wakeup
+         * interrupts. If the samsung pinctrl driver is enabled and includes
+         * the wakeup interrupt support, then the setting up external wakeup
+         * interrupts here can be skipped. This check here is temporary to
+         * allow exynos4 platforms that do not use Samsung pinctrl driver to
+         * co-exist with platforms that do. When all of the Samsung Exynos4
+         * platforms switch over to using the pinctrl driver, the wakeup
+         * interrupt support code here can be completely removed.
+         */
+        struct device_node *pctrl_np, *wkup_np;
+        const char *pctrl_compat = "samsung,pinctrl-exynos4210";
+        const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
+
+        for_each_compatible_node(pctrl_np, NULL, pctrl_compat) {
+                if (of_device_is_available(pctrl_np)) {
+                        wkup_np = of_find_compatible_node(pctrl_np, NULL,
+                                                        wkup_compat);
+                        if (wkup_np)
+                                return -ENODEV;
+                }
+        }
+#endif
+
         if (soc_is_exynos5250())
                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
         else
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 9d1f3ac86db2..8480849affb9 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -89,7 +89,7 @@
 #define EXYNOS4_PA_L2CC                 0x10502000
 
 #define EXYNOS4_PA_MDMA0                0x10810000
-#define EXYNOS4_PA_MDMA1                0x12840000
+#define EXYNOS4_PA_MDMA1                0x12850000
 #define EXYNOS4_PA_PDMA0                0x12680000
 #define EXYNOS4_PA_PDMA1                0x12690000
 #define EXYNOS5_PA_MDMA0                0x10800000
@@ -121,6 +121,11 @@
 #define EXYNOS4_PA_SYSMMU_MFC_L         0x13620000
 #define EXYNOS4_PA_SYSMMU_MFC_R         0x13630000
 
+#define EXYNOS5_PA_GSC0                 0x13E00000
+#define EXYNOS5_PA_GSC1                 0x13E10000
+#define EXYNOS5_PA_GSC2                 0x13E20000
+#define EXYNOS5_PA_GSC3                 0x13E30000
+
 #define EXYNOS5_PA_SYSMMU_MDMA1         0x10A40000
 #define EXYNOS5_PA_SYSMMU_SSS           0x10A50000
 #define EXYNOS5_PA_SYSMMU_2D            0x10A60000
@@ -172,6 +177,10 @@
 
 #define EXYNOS4_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
 #define EXYNOS4_PA_DWMCI                0x12550000
+#define EXYNOS5_PA_DWMCI0               0x12200000
+#define EXYNOS5_PA_DWMCI1               0x12210000
+#define EXYNOS5_PA_DWMCI2               0x12220000
+#define EXYNOS5_PA_DWMCI3               0x12230000
 
 #define EXYNOS4_PA_HSOTG                0x12480000
 #define EXYNOS4_PA_USB_HSPHY            0x125B0000
diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h
index 998daf2add92..88a4543b0001 100644
--- a/arch/arm/mach-exynos/include/mach/sysmmu.h
+++ b/arch/arm/mach-exynos/include/mach/sysmmu.h
@@ -58,7 +58,7 @@ static inline void platform_set_sysmmu(
 #endif
 
 #else /* !CONFIG_EXYNOS_DEV_SYSMMU */
-#define platform_set_sysmmu(dev, sysmmu) do { } while (0)
+#define platform_set_sysmmu(sysmmu, dev) do { } while (0)
 #endif
 
 #define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index b2b5d5faa748..e58d786faf78 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -1,5 +1,5 @@
 /*
- * Samsung's Exynos4210 flattened device tree enabled machine
+ * Samsung's EXYNOS4 flattened device tree enabled machine
  *
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
@@ -36,7 +36,7 @@
  * at some point, the drivers should be capable of parsing all the platform
  * data from the device tree.
  */
-static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
+static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
                                 "exynos4210-uart.0", NULL),
         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
@@ -55,6 +55,20 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
                                 "exynos4-sdhci.3", NULL),
         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
                                 "s3c2440-i2c.0", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
+                                "s3c2440-i2c.1", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
+                                "s3c2440-i2c.2", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
+                                "s3c2440-i2c.3", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
+                                "s3c2440-i2c.4", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
+                                "s3c2440-i2c.5", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
+                                "s3c2440-i2c.6", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
+                                "s3c2440-i2c.7", NULL),
         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
                                 "exynos4210-spi.0", NULL),
         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
@@ -66,19 +80,19 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
         {},
 };
 
-static void __init exynos4210_dt_map_io(void)
+static void __init exynos4_dt_map_io(void)
 {
         exynos_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
 }
 
-static void __init exynos4210_dt_machine_init(void)
+static void __init exynos4_dt_machine_init(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table,
-                                exynos4210_auxdata_lookup, NULL);
+                                exynos4_auxdata_lookup, NULL);
 }
 
-static char const *exynos4210_dt_compat[] __initdata = {
+static char const *exynos4_dt_compat[] __initdata = {
         "samsung,exynos4210",
         NULL
 };
@@ -86,11 +100,11 @@ static char const *exynos4210_dt_compat[] __initdata = {
 DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
         /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
         .init_irq       = exynos4_init_irq,
-        .map_io         = exynos4210_dt_map_io,
+        .map_io         = exynos4_dt_map_io,
         .handle_irq     = gic_handle_irq,
-        .init_machine   = exynos4210_dt_machine_init,
+        .init_machine   = exynos4_dt_machine_init,
         .init_late      = exynos_init_late,
         .timer          = &exynos4_timer,
-        .dt_compat      = exynos4210_dt_compat,
+        .dt_compat      = exynos4_dt_compat,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 8833060f77e9..db1cd8eacf28 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -47,6 +47,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                                 "s3c2440-i2c.0", NULL),
         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
                                 "s3c2440-i2c.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
+                                "dw_mmc.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
+                                "dw_mmc.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
+                                "dw_mmc.2", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
+                                "dw_mmc.3", NULL),
         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
                                 "exynos4210-spi.0", NULL),
         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
@@ -56,6 +64,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
+                                "exynos-gsc.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
+                                "exynos-gsc.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
+                                "exynos-gsc.2", NULL),
+        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
+                                "exynos-gsc.3", NULL),
         {},
 };
 
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index fc23f74ade81..67b50bb89c0f 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -15,6 +15,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/input.h>
+#include <linux/pwm.h>
 #include <linux/pwm_backlight.h>
 #include <linux/gpio_keys.h>
 #include <linux/i2c.h>
@@ -614,6 +615,10 @@ static struct platform_device origen_lcd_hv070wsa = {
         .dev.platform_data      = &origen_lcd_hv070wsa_data,
 };
 
+static struct pwm_lookup origen_pwm_lookup[] = {
+        PWM_LOOKUP("s3c24xx-pwm.0", 0, "pwm-backlight.0", NULL),
+};
+
 #ifdef CONFIG_DRM_EXYNOS
 static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
         .panel  = {
@@ -798,6 +803,7 @@ static void __init origen_machine_init(void)
 
         platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
 
+        pwm_add_table(origen_pwm_lookup, ARRAY_SIZE(origen_pwm_lookup));
         samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
 
         origen_bt_setup();
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index 589f1db140f0..7a265d1a82d3 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -17,6 +17,7 @@
 #include <linux/mfd/max8997.h>
 #include <linux/mmc/host.h>
 #include <linux/platform_device.h>
+#include <linux/pwm.h>
 #include <linux/pwm_backlight.h>
 #include <linux/regulator/machine.h>
 #include <linux/serial_core.h>
@@ -222,6 +223,10 @@ static struct platform_pwm_backlight_data smdk4x12_bl_data = {
         .pwm_period_ns  = 1000,
 };
 
+static struct pwm_lookup smdk4x12_pwm_lookup[] = {
+        PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL),
+};
+
 static uint32_t smdk4x12_keymap[] __initdata = {
         /* KEY(row, col, keycode) */
         KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3),
@@ -349,6 +354,7 @@ static void __init smdk4x12_machine_init(void)
                                 ARRAY_SIZE(smdk4x12_i2c_devs7));
 
         samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
+        pwm_add_table(smdk4x12_pwm_lookup, ARRAY_SIZE(smdk4x12_pwm_lookup));
 
         samsung_keypad_set_platdata(&smdk4x12_keypad_data);
 
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 6e52cbd0b3e0..c15d2238ceb0 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -18,6 +18,7 @@
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/input.h>
+#include <linux/pwm.h>
 #include <linux/pwm_backlight.h>
 #include <linux/platform_data/s3c-hsotg.h>
 
@@ -360,6 +361,10 @@ static struct i2c_board_info hdmiphy_info = {
         I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
 };
 
+static struct pwm_lookup smdkv310_pwm_lookup[] = {
+        PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL),
+};
+
 static void s5p_tv_setup(void)
 {
         /* direct HPD to HDMI chip */
@@ -399,6 +404,8 @@ static void __init smdkv310_machine_init(void)
         samsung_keypad_set_platdata(&smdkv310_keypad_data);
 
         samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
+        pwm_add_table(smdkv310_pwm_lookup, ARRAY_SIZE(smdkv310_pwm_lookup));
+
 #ifdef CONFIG_DRM_EXYNOS
         s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
         exynos4_fimd0_gpio_setup_24bpp();
diff --git a/arch/arm/mach-footbridge/Makefile b/arch/arm/mach-footbridge/Makefile
index 3afb1b25946f..0b64dd430d61 100644
--- a/arch/arm/mach-footbridge/Makefile
+++ b/arch/arm/mach-footbridge/Makefile
@@ -14,15 +14,11 @@ pci-$(CONFIG_ARCH_EBSA285_HOST) += ebsa285-pci.o
 pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o
 pci-$(CONFIG_ARCH_PERSONAL_SERVER) += personal-pci.o
 
-leds-$(CONFIG_ARCH_EBSA285) += ebsa285-leds.o
-leds-$(CONFIG_ARCH_NETWINDER) += netwinder-leds.o
-
 obj-$(CONFIG_ARCH_CATS) += cats-hw.o isa-timer.o
 obj-$(CONFIG_ARCH_EBSA285) += ebsa285.o dc21285-timer.o
 obj-$(CONFIG_ARCH_NETWINDER) += netwinder-hw.o isa-timer.o
 obj-$(CONFIG_ARCH_PERSONAL_SERVER) += personal.o dc21285-timer.o
 
 obj-$(CONFIG_PCI)       +=$(pci-y)
-obj-$(CONFIG_LEDS)      +=$(leds-y)
 
 obj-$(CONFIG_ISA)       += isa.o isa-rtc.o
diff --git a/arch/arm/mach-footbridge/ebsa285-leds.c b/arch/arm/mach-footbridge/ebsa285-leds.c
deleted file mode 100644
index 5bd266754b95..000000000000
--- a/arch/arm/mach-footbridge/ebsa285-leds.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- *  linux/arch/arm/mach-footbridge/ebsa285-leds.c
- *
- *  Copyright (C) 1998-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- * EBSA-285 control routines.
- *
- * The EBSA-285 uses the leds as follows:
- *  - Green - toggles state every 50 timer interrupts
- *  - Amber - On if system is not idle
- *  - Red   - currently unused
- *
- * Changelog:
- *   02-05-1999 RMK     Various cleanups
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-static char led_state;
-static char hw_led_state;
-
-static DEFINE_SPINLOCK(leds_lock);
-
-static void ebsa285_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&leds_lock, flags);
-
-        switch (evt) {
-        case led_start:
-                hw_led_state = XBUS_LED_RED | XBUS_LED_GREEN;
-#ifndef CONFIG_LEDS_CPU
-                hw_led_state |= XBUS_LED_AMBER;
-#endif
-                led_state |= LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = XBUS_LED_RED | XBUS_LED_GREEN | XBUS_LED_AMBER;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = XBUS_LED_RED | XBUS_LED_GREEN | XBUS_LED_AMBER;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= XBUS_LED_GREEN;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= XBUS_LED_AMBER;
-                break;
-
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~XBUS_LED_AMBER;
-                break;
-#endif
-
-        case led_halted:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~XBUS_LED_RED;
-                break;
-
-        case led_green_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~XBUS_LED_GREEN;
-                break;
-
-        case led_green_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= XBUS_LED_GREEN;
-                break;
-
-        case led_amber_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~XBUS_LED_AMBER;
-                break;
-
-        case led_amber_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= XBUS_LED_AMBER;
-                break;
-
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~XBUS_LED_RED;
-                break;
-
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= XBUS_LED_RED;
-                break;
-
-        default:
-                break;
-        }
-
-        if  (led_state & LED_STATE_ENABLED)
-                *XBUS_LEDS = hw_led_state;
-
-        spin_unlock_irqrestore(&leds_lock, flags);
-}
-
-static int __init leds_init(void)
-{
-        if (machine_is_ebsa285())
-                leds_event = ebsa285_leds_event;
-
-        leds_event(led_start);
-
-        return 0;
-}
-
-__initcall(leds_init);
diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c
index 27716a7e5fc1..b09551ef89ca 100644
--- a/arch/arm/mach-footbridge/ebsa285.c
+++ b/arch/arm/mach-footbridge/ebsa285.c
@@ -5,6 +5,8 @@
  */
 #include <linux/init.h>
 #include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <asm/hardware/dec21285.h>
 #include <asm/mach-types.h>
@@ -13,6 +15,85 @@
 
 #include "common.h"
 
+/* LEDs */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct ebsa285_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} ebsa285_leds[] = {
+        { "ebsa285:amber", "heartbeat", },
+        { "ebsa285:green", "cpu0", },
+        { "ebsa285:red",},
+};
+
+static void ebsa285_led_set(struct led_classdev *cdev,
+                enum led_brightness b)
+{
+        struct ebsa285_led *led = container_of(cdev,
+                        struct ebsa285_led, cdev);
+
+        if (b != LED_OFF)
+                *XBUS_LEDS |= led->mask;
+        else
+                *XBUS_LEDS &= ~led->mask;
+}
+
+static enum led_brightness ebsa285_led_get(struct led_classdev *cdev)
+{
+        struct ebsa285_led *led = container_of(cdev,
+                        struct ebsa285_led, cdev);
+
+        return (*XBUS_LEDS & led->mask) ? LED_FULL : LED_OFF;
+}
+
+static int __init ebsa285_leds_init(void)
+{
+        int i;
+
+        if (machine_is_ebsa285())
+                return -ENODEV;
+
+        /* 3 LEDS All ON */
+        *XBUS_LEDS |= XBUS_LED_AMBER | XBUS_LED_GREEN | XBUS_LED_RED;
+
+        for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) {
+                struct ebsa285_led *led;
+
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+
+                led->cdev.name = ebsa285_leds[i].name;
+                led->cdev.brightness_set = ebsa285_led_set;
+                led->cdev.brightness_get = ebsa285_led_get;
+                led->cdev.default_trigger = ebsa285_leds[i].trigger;
+                led->mask = BIT(i);
+
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+
+        return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(ebsa285_leds_init);
+#endif
+
 MACHINE_START(EBSA285, "EBSA285")
         /* Maintainer: Russell King */
         .atag_offset    = 0x100,
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index cac9f67e7da7..d2d14339c6c4 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -12,9 +12,10 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <asm/hardware/dec21285.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
 #include <asm/system_misc.h>
@@ -27,13 +28,6 @@
 #define GP1_IO_BASE             0x338
 #define GP2_IO_BASE             0x33a
 
-
-#ifdef CONFIG_LEDS
-#define DEFAULT_LEDS    0
-#else
-#define DEFAULT_LEDS    GPIO_GREEN_LED
-#endif
-
 /*
  * Winbond WB83977F accessibility stuff
  */
@@ -611,15 +605,9 @@ static void __init rwa010_init(void)
 static int __init nw_hw_init(void)
 {
         if (machine_is_netwinder()) {
-                unsigned long flags;
-
                 wb977_init();
                 cpld_init();
                 rwa010_init();
-
-                raw_spin_lock_irqsave(&nw_gpio_lock, flags);
-                nw_gpio_modify_op(GPIO_RED_LED|GPIO_GREEN_LED, DEFAULT_LEDS);
-                raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
         }
         return 0;
 }
@@ -672,6 +660,102 @@ static void netwinder_restart(char mode, const char *cmd)
         }
 }
 
+/* LEDs */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct netwinder_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} netwinder_leds[] = {
+        { "netwinder:green", "heartbeat", },
+        { "netwinder:red", "cpu0", },
+};
+
+/*
+ * The LED control in Netwinder is reversed:
+ *  - setting bit means turn off LED
+ *  - clearing bit means turn on LED
+ */
+static void netwinder_led_set(struct led_classdev *cdev,
+                enum led_brightness b)
+{
+        struct netwinder_led *led = container_of(cdev,
+                        struct netwinder_led, cdev);
+        unsigned long flags;
+        u32 reg;
+
+        spin_lock_irqsave(&nw_gpio_lock, flags);
+        reg = nw_gpio_read();
+        if (b != LED_OFF)
+                reg &= ~led->mask;
+        else
+                reg |= led->mask;
+        nw_gpio_modify_op(led->mask, reg);
+        spin_unlock_irqrestore(&nw_gpio_lock, flags);
+}
+
+static enum led_brightness netwinder_led_get(struct led_classdev *cdev)
+{
+        struct netwinder_led *led = container_of(cdev,
+                        struct netwinder_led, cdev);
+        unsigned long flags;
+        u32 reg;
+
+        spin_lock_irqsave(&nw_gpio_lock, flags);
+        reg = nw_gpio_read();
+        spin_unlock_irqrestore(&nw_gpio_lock, flags);
+
+        return (reg & led->mask) ? LED_OFF : LED_FULL;
+}
+
+static int __init netwinder_leds_init(void)
+{
+        int i;
+
+        if (!machine_is_netwinder())
+                return -ENODEV;
+
+        for (i = 0; i < ARRAY_SIZE(netwinder_leds); i++) {
+                struct netwinder_led *led;
+
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+
+                led->cdev.name = netwinder_leds[i].name;
+                led->cdev.brightness_set = netwinder_led_set;
+                led->cdev.brightness_get = netwinder_led_get;
+                led->cdev.default_trigger = netwinder_leds[i].trigger;
+
+                if (i == 0)
+                        led->mask = GPIO_GREEN_LED;
+                else
+                        led->mask = GPIO_RED_LED;
+
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+
+        return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(netwinder_leds_init);
+#endif
+
 MACHINE_START(NETWINDER, "Rebel-NetWinder")
         /* Maintainer: Russell King/Rebel.com */
         .atag_offset    = 0x100,
diff --git a/arch/arm/mach-footbridge/netwinder-leds.c b/arch/arm/mach-footbridge/netwinder-leds.c
deleted file mode 100644
index 5a2bd89cbdca..000000000000
--- a/arch/arm/mach-footbridge/netwinder-leds.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- *  linux/arch/arm/mach-footbridge/netwinder-leds.c
- *
- *  Copyright (C) 1998-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * NetWinder LED control routines.
- *
- * The Netwinder uses the leds as follows:
- *  - Green - toggles state every 50 timer interrupts
- *  - Red   - On if the system is not idle
- *
- * Changelog:
- *   02-05-1999 RMK     Various cleanups
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-static char led_state;
-static char hw_led_state;
-
-static DEFINE_RAW_SPINLOCK(leds_lock);
-
-static void netwinder_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        raw_spin_lock_irqsave(&leds_lock, flags);
-
-        switch (evt) {
-        case led_start:
-                led_state |= LED_STATE_ENABLED;
-                hw_led_state = GPIO_GREEN_LED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= GPIO_GREEN_LED;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~GPIO_RED_LED;
-                break;
-
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= GPIO_RED_LED;
-                break;
-#endif
-
-        case led_halted:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= GPIO_RED_LED;
-                break;
-
-        case led_green_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= GPIO_GREEN_LED;
-                break;
-
-        case led_green_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~GPIO_GREEN_LED;
-                break;
-
-        case led_amber_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= GPIO_GREEN_LED | GPIO_RED_LED;
-                break;
-
-        case led_amber_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~(GPIO_GREEN_LED | GPIO_RED_LED);
-                break;
-
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= GPIO_RED_LED;
-                break;
-
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~GPIO_RED_LED;
-                break;
-
-        default:
-                break;
-        }
-
-        raw_spin_unlock_irqrestore(&leds_lock, flags);
-
-        if  (led_state & LED_STATE_ENABLED) {
-                raw_spin_lock_irqsave(&nw_gpio_lock, flags);
-                nw_gpio_modify_op(GPIO_RED_LED | GPIO_GREEN_LED, hw_led_state);
-                raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
-        }
-}
-
-static int __init leds_init(void)
-{
-        if (machine_is_netwinder())
-                leds_event = netwinder_leds_event;
-
-        leds_event(led_start);
-
-        return 0;
-}
-
-__initcall(leds_init);
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index af1da34ccf9d..40e36a50304c 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -15,6 +15,7 @@
  */
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/dma-mapping.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
@@ -23,6 +24,7 @@
 #include <linux/of_platform.h>
 #include <linux/of_address.h>
 #include <linux/smp.h>
+#include <linux/amba/bus.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
@@ -149,11 +151,61 @@ static void highbank_power_off(void)
                 cpu_do_idle();
 }
 
+static int highbank_platform_notifier(struct notifier_block *nb,
+                                  unsigned long event, void *__dev)
+{
+        struct resource *res;
+        int reg = -1;
+        struct device *dev = __dev;
+
+        if (event != BUS_NOTIFY_ADD_DEVICE)
+                return NOTIFY_DONE;
+
+        if (of_device_is_compatible(dev->of_node, "calxeda,hb-ahci"))
+                reg = 0xc;
+        else if (of_device_is_compatible(dev->of_node, "calxeda,hb-sdhci"))
+                reg = 0x18;
+        else if (of_device_is_compatible(dev->of_node, "arm,pl330"))
+                reg = 0x20;
+        else if (of_device_is_compatible(dev->of_node, "calxeda,hb-xgmac")) {
+                res = platform_get_resource(to_platform_device(dev),
+                                            IORESOURCE_MEM, 0);
+                if (res) {
+                        if (res->start == 0xfff50000)
+                                reg = 0;
+                        else if (res->start == 0xfff51000)
+                                reg = 4;
+                }
+        }
+
+        if (reg < 0)
+                return NOTIFY_DONE;
+
+        if (of_property_read_bool(dev->of_node, "dma-coherent")) {
+                writel(0xff31, sregs_base + reg);
+                set_dma_ops(dev, &arm_coherent_dma_ops);
+        } else
+                writel(0, sregs_base + reg);
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block highbank_amba_nb = {
+        .notifier_call = highbank_platform_notifier,
+};
+
+static struct notifier_block highbank_platform_nb = {
+        .notifier_call = highbank_platform_notifier,
+};
+
 static void __init highbank_init(void)
 {
         pm_power_off = highbank_power_off;
         highbank_pm_init();
 
+        bus_register_notifier(&platform_bus_type, &highbank_platform_nb);
+        bus_register_notifier(&amba_bustype, &highbank_amba_nb);
+
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 7ca5fe45945f..32197c117afe 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -298,6 +298,7 @@ config MACH_MX27_3DS
         select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_KEYPAD
+        select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MX2_CAMERA
         select IMX_HAVE_PLATFORM_MXC_EHCI
@@ -757,7 +758,7 @@ config SOC_IMX6Q
         select HAVE_IMX_MMDC
         select HAVE_IMX_SRC
         select HAVE_SMP
-        select MFD_ANATOP
+        select MFD_SYSCON
         select PINCTRL
         select PINCTRL_IMX6Q
 
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 4431a62fff5b..d20d4795f4ea 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -241,6 +241,6 @@ int __init mx25_clocks_init(void)
         clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
         clk_register_clkdev(clk[iim_ipg], "iim", NULL);
 
-        mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
+        mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
         return 0;
 }
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index f69ca4680049..3b6b640eed24 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -239,8 +239,8 @@ int __init mx27_clocks_init(unsigned long fref)
         clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
         clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
         clk_register_clkdev(clk[nfc_baud_gate], NULL, "mxc_nand.0");
-        clk_register_clkdev(clk[vpu_baud_gate], "per", "imx-vpu");
-        clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "imx-vpu");
+        clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
+        clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
         clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx-dma");
         clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx-dma");
         clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 436c5720fe6a..04822932cdd1 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -17,6 +17,10 @@ extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data;
 #define imx27_add_fsl_usb2_udc(pdata)   \
         imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
 
+extern const struct imx_imx27_coda_data imx27_coda_data;
+#define imx27_add_coda()        \
+        imx_add_imx27_coda(&imx27_coda_data)
+
 extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data;
 #define imx27_add_imx2_wdt()    \
         imx_add_imx2_wdt(&imx27_imx2_wdt_data)
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index 2c6ab3273f9e..5985ed1b8c98 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -526,7 +526,8 @@ static void __init armadillo5x0_init(void)
         imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
 
         /* set NAND page size to 2k if not configured via boot mode pins */
-        __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
+        __raw_writel(__raw_readl(mx3_ccm_base + MXC_CCM_RCSR) |
+                                        (1 << 30), mx3_ccm_base + MXC_CCM_RCSR);
 
         /* RTC */
         /* Get RTC IRQ and register the chip */
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index f264ddddd47c..821d6aac411c 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -32,13 +32,13 @@
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/leds.h>
-#include <linux/memblock.h>
 #include <media/soc_camera.h>
 #include <sound/tlv320aic32x4.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/system_info.h>
+#include <asm/memblock.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
@@ -233,10 +233,8 @@ static void __init visstrim_camera_init(void)
 static void __init visstrim_reserve(void)
 {
         /* reserve 4 MiB for mx2-camera */
-        mx2_camera_base = memblock_alloc(MX2_CAMERA_BUF_SIZE,
+        mx2_camera_base = arm_memblock_steal(3 * MX2_CAMERA_BUF_SIZE,
                         MX2_CAMERA_BUF_SIZE);
-        memblock_free(mx2_camera_base, MX2_CAMERA_BUF_SIZE);
-        memblock_remove(mx2_camera_base, MX2_CAMERA_BUF_SIZE);
 }
 
 /* GPIOs used as events for applications */
@@ -405,6 +403,47 @@ static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = {
         .flags                  = IMX_SSI_DMA | IMX_SSI_SYN,
 };
 
+/* coda */
+
+static void __init visstrim_coda_init(void)
+{
+        struct platform_device *pdev;
+        int dma;
+
+        pdev = imx27_add_coda();
+        dma = dma_declare_coherent_memory(&pdev->dev,
+                                          mx2_camera_base + MX2_CAMERA_BUF_SIZE,
+                                          mx2_camera_base + MX2_CAMERA_BUF_SIZE,
+                                          MX2_CAMERA_BUF_SIZE,
+                                          DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+        if (!(dma & DMA_MEMORY_MAP))
+                return;
+}
+
+/* DMA deinterlace */
+static struct platform_device visstrim_deinterlace = {
+        .name = "m2m-deinterlace",
+        .id = 0,
+};
+
+static void __init visstrim_deinterlace_init(void)
+{
+        int ret = -ENOMEM;
+        struct platform_device *pdev = &visstrim_deinterlace;
+        int dma;
+
+        ret = platform_device_register(pdev);
+
+        dma = dma_declare_coherent_memory(&pdev->dev,
+                                          mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
+                                          mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
+                                          MX2_CAMERA_BUF_SIZE,
+                                          DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+        if (!(dma & DMA_MEMORY_MAP))
+                return;
+}
+
+
 static void __init visstrim_m10_revision(void)
 {
         int exp_version = 0;
@@ -467,7 +506,9 @@ static void __init visstrim_m10_board_init(void)
         platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
                                       &iclink_tvp5150, sizeof(iclink_tvp5150));
         gpio_led_register_device(0, &visstrim_m10_led_data);
+        visstrim_deinterlace_init();
         visstrim_camera_init();
+        visstrim_coda_init();
 }
 
 static void __init visstrim_m10_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 36979d3dfe34..47c91f7185d2 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -23,8 +23,9 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
+#include <linux/regmap.h>
 #include <linux/micrel_phy.h>
-#include <linux/mfd/anatop.h>
+#include <linux/mfd/syscon.h>
 #include <asm/cpuidle.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -118,20 +119,7 @@ static void __init imx6q_sabrelite_init(void)
 
 static void __init imx6q_usb_init(void)
 {
-        struct device_node *np;
-        struct platform_device *pdev = NULL;
-        struct anatop *adata = NULL;
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
-        if (np)
-                pdev = of_find_device_by_node(np);
-        if (pdev)
-                adata = platform_get_drvdata(pdev);
-        if (!adata) {
-                if (np)
-                        of_node_put(np);
-                return;
-        }
+        struct regmap *anatop;
 
 #define HW_ANADIG_USB1_CHRG_DETECT              0x000001b0
 #define HW_ANADIG_USB2_CHRG_DETECT              0x00000210
@@ -139,20 +127,21 @@ static void __init imx6q_usb_init(void)
 #define BM_ANADIG_USB_CHRG_DETECT_EN_B          0x00100000
 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B    0x00080000
 
-        /*
-         * The external charger detector needs to be disabled,
-         * or the signal at DP will be poor
-         */
-        anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT,
-                        BM_ANADIG_USB_CHRG_DETECT_EN_B
-                        | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
-                        ~0);
-        anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT,
-                        BM_ANADIG_USB_CHRG_DETECT_EN_B |
-                        BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
-                        ~0);
-
-        of_node_put(np);
+        anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
+        if (!IS_ERR(anatop)) {
+                /*
+                 * The external charger detector needs to be disabled,
+                 * or the signal at DP will be poor
+                 */
+                regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
+                                BM_ANADIG_USB_CHRG_DETECT_EN_B
+                                | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+                regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
+                                BM_ANADIG_USB_CHRG_DETECT_EN_B |
+                                BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+        } else {
+                pr_warn("failed to find fsl,imx6q-anatop regmap\n");
+        }
 }
 
 static void __init imx6q_init_machine(void)
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 58c24c1a7ab7..05996f39005c 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -158,6 +158,11 @@ static const int mx27pdk_pins[] __initconst = {
         PB21_PF_CSI_HSYNC,
         CSI_PWRDWN | GPIO_GPIO | GPIO_OUT,
         CSI_RESET | GPIO_GPIO | GPIO_OUT,
+        /* SSI4 */
+        PC16_PF_SSI4_FS,
+        PC17_PF_SSI4_RXD,
+        PC18_PF_SSI4_TXD,
+        PC19_PF_SSI4_CLK,
 };
 
 static struct gpio mx27_3ds_camera_gpios[] = {
@@ -329,13 +334,24 @@ static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
 };
 
 /* MC13783 */
+static struct mc13xxx_codec_platform_data mx27_3ds_codec = {
+        .dac_ssi_port = MC13783_SSI1_PORT,
+        .adc_ssi_port = MC13783_SSI1_PORT,
+};
+
 static struct mc13xxx_platform_data mc13783_pdata = {
         .regulators = {
                 .regulators = mx27_3ds_regulators,
                 .num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
 
         },
-        .flags  = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC,
+        .flags  = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC |
+                                                MC13XXX_USE_CODEC,
+        .codec = &mx27_3ds_codec,
+};
+
+static struct imx_ssi_platform_data mx27_3ds_ssi_pdata = {
+        .flags = IMX_SSI_DMA | IMX_SSI_NET,
 };
 
 /* SPI */
@@ -512,6 +528,9 @@ static void __init mx27pdk_init(void)
         }
 
         imx27_add_mx2_camera(&mx27_3ds_cam_pdata);
+        imx27_add_imx_ssi(0, &mx27_3ds_ssi_pdata);
+
+        imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
 }
 
 static void __init mx27pdk_timer_init(void)
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index ebeef966e1f5..5521d18bf19a 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -4,11 +4,10 @@
 
 # Object file lists.
 
-obj-y                                   := core.o lm.o
+obj-y                                   := core.o lm.o leds.o
 obj-$(CONFIG_ARCH_INTEGRATOR_AP)        += integrator_ap.o
 obj-$(CONFIG_ARCH_INTEGRATOR_CP)        += integrator_cp.o
 
-obj-$(CONFIG_LEDS)                      += leds.o
 obj-$(CONFIG_PCI)                       += pci_v3.o pci.o
 obj-$(CONFIG_CPU_FREQ_INTEGRATOR)       += cpu.o
 obj-$(CONFIG_INTEGRATOR_IMPD1)          += impd1.o
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index a432d4325f89..dad3cb74ed31 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -28,7 +28,6 @@
 #include <mach/cm.h>
 #include <mach/irqs.h>
 
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/time.h>
 #include <asm/pgtable.h>
@@ -128,8 +127,6 @@ static struct amba_pl010_data integrator_uart_data = {
         .set_mctrl = integrator_uart_set_mctrl,
 };
 
-#define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_CTRL)
-
 static DEFINE_RAW_SPINLOCK(cm_lock);
 
 /**
diff --git a/arch/arm/mach-integrator/include/mach/cm.h b/arch/arm/mach-integrator/include/mach/cm.h
index 445d57adb043..1a78692e32a4 100644
--- a/arch/arm/mach-integrator/include/mach/cm.h
+++ b/arch/arm/mach-integrator/include/mach/cm.h
@@ -3,6 +3,8 @@
  */
 void cm_control(u32, u32);
 
+#define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_CTRL)
+
 #define CM_CTRL_LED                     (1 << 0)
 #define CM_CTRL_nMBDET                  (1 << 1)
 #define CM_CTRL_REMAP                   (1 << 2)
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index 466defa97842..7a7f6d3273bf 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -1,90 +1,125 @@
 /*
- *  linux/arch/arm/mach-integrator/leds.c
+ * Driver for the 4 user LEDs found on the Integrator AP/CP baseboard
+ * Based on Versatile and RealView machine LED code
  *
- *  Integrator/AP and Integrator/CP LED control routines
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Bryan Wu <bryan.wu@canonical.com>
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/spinlock.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
+#include <mach/cm.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-#include <mach/cm.h>
 
-static int saved_leds;
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+
+#define ALPHA_REG __io_address(INTEGRATOR_DBG_BASE)
+#define LEDREG  (__io_address(INTEGRATOR_DBG_BASE) + INTEGRATOR_DBG_LEDS_OFFSET)
 
-static void integrator_leds_event(led_event_t ledevt)
+struct integrator_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} integrator_leds[] = {
+        { "integrator:green0", "heartbeat", },
+        { "integrator:yellow", },
+        { "integrator:red", },
+        { "integrator:green1", },
+        { "integrator:core_module", "cpu0", },
+};
+
+static void integrator_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
 {
-        unsigned long flags;
-        const unsigned int dbg_base = IO_ADDRESS(INTEGRATOR_DBG_BASE);
-        unsigned int update_alpha_leds;
+        struct integrator_led *led = container_of(cdev,
+                                                 struct integrator_led, cdev);
+        u32 reg = __raw_readl(LEDREG);
 
-        // yup, change the LEDs
-        local_irq_save(flags);
-        update_alpha_leds = 0;
+        if (b != LED_OFF)
+                reg |= led->mask;
+        else
+                reg &= ~led->mask;
 
-        switch(ledevt) {
-        case led_idle_start:
-                cm_control(CM_CTRL_LED, 0);
-                break;
+        while (__raw_readl(ALPHA_REG) & 1)
+                cpu_relax();
 
-        case led_idle_end:
-                cm_control(CM_CTRL_LED, CM_CTRL_LED);
-                break;
+        __raw_writel(reg, LEDREG);
+}
 
-        case led_timer:
-                saved_leds ^= GREEN_LED;
-                update_alpha_leds = 1;
-                break;
+static enum led_brightness integrator_led_get(struct led_classdev *cdev)
+{
+        struct integrator_led *led = container_of(cdev,
+                                                 struct integrator_led, cdev);
+        u32 reg = __raw_readl(LEDREG);
 
-        case led_red_on:
-                saved_leds |= RED_LED;
-                update_alpha_leds = 1;
-                break;
+        return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
 
-        case led_red_off:
-                saved_leds &= ~RED_LED;
-                update_alpha_leds = 1;
-                break;
+static void cm_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
+{
+        if (b != LED_OFF)
+                cm_control(CM_CTRL_LED, CM_CTRL_LED);
+        else
+                cm_control(CM_CTRL_LED, 0);
+}
 
-        default:
-                break;
-        }
+static enum led_brightness cm_led_get(struct led_classdev *cdev)
+{
+        u32 reg = readl(CM_CTRL);
 
-        if (update_alpha_leds) {
-                while (__raw_readl(dbg_base + INTEGRATOR_DBG_ALPHA_OFFSET) & 1);
-                __raw_writel(saved_leds, dbg_base + INTEGRATOR_DBG_LEDS_OFFSET);
-        }
-        local_irq_restore(flags);
+        return (reg & CM_CTRL_LED) ? LED_FULL : LED_OFF;
 }
 
-static int __init leds_init(void)
+static int __init integrator_leds_init(void)
 {
-        if (machine_is_integrator() || machine_is_cintegrator())
-                leds_event = integrator_leds_event;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(integrator_leds); i++) {
+                struct integrator_led *led;
+
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+
+
+                led->cdev.name = integrator_leds[i].name;
+
+                if (i == 4) { /* Setting for LED in core module */
+                        led->cdev.brightness_set = cm_led_set;
+                        led->cdev.brightness_get = cm_led_get;
+                } else {
+                        led->cdev.brightness_set = integrator_led_set;
+                        led->cdev.brightness_get = integrator_led_get;
+                }
+
+                led->cdev.default_trigger = integrator_leds[i].trigger;
+                led->mask = BIT(i);
+
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
 
         return 0;
 }
 
-core_initcall(leds_init);
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(integrator_leds_init);
+#endif
diff --git a/arch/arm/mach-ks8695/Kconfig b/arch/arm/mach-ks8695/Kconfig
index f5c39a8c2b00..a545976bdbd6 100644
--- a/arch/arm/mach-ks8695/Kconfig
+++ b/arch/arm/mach-ks8695/Kconfig
@@ -21,6 +21,67 @@ config MACH_ACS5K
           say 'Y' here if you want your kernel to run on the Brivo
           Systems LLC, ACS-5000 Master board.
 
+config MACH_LITE300
+        bool "SecureComputing SG300"
+        help
+          Say 'Y' here if you want your kernel to support the
+          SecureComputing / SnapGear SG300 VPN Internet Router.
+          See http://www.securecomputing.com for more details.
+
+config MACH_SG310
+        bool "McAfee SG310"
+        help
+          Say 'Y' here if you want your kernel to support the
+          McAfee / SnapGear SG310 VPN Internet Router.
+          See http://www.mcafee.com for more details.
+
+config MACH_SE4200
+        bool "SecureComputing SE4200"
+        help
+          Say 'Y' here if you want your kernel to support the
+          SecureComputing / SnapGear SE4200 Secure Wireless VPN
+          Internet Router.
+          See http://www.securecomputing.com for more details.
+
+config MACH_CM4002
+        bool "OpenGear CM4002"
+        help
+          Say 'Y' here if you want your kernel to support the OpenGear
+          CM4002 Secure Access Server. See http://www.opengear.com for
+          more details.
+
+config MACH_CM4008
+        bool "OpenGear CM4008"
+        select MIGHT_HAVE_PCI
+        help
+          Say 'Y' here if you want your kernel to support the OpenGear
+          CM4008 Console Server. See http://www.opengear.com for more
+          details.
+
+config MACH_CM41xx
+        bool "OpenGear CM41xx"
+        select MIGHT_HAVE_PCI
+        help
+          Say 'Y' here if you want your kernel to support the OpenGear
+          CM4016 or CM4048 Console Servers. See http://www.opengear.com for
+          more details.
+
+config MACH_IM4004
+        bool "OpenGear IM4004"
+        select MIGHT_HAVE_PCI
+        help
+          Say 'Y' here if you want your kernel to support the OpenGear
+          IM4004 Secure Access Server. See http://www.opengear.com for
+          more details.
+
+config MACH_IM42xx
+        bool "OpenGear IM42xx"
+        select MIGHT_HAVE_PCI
+        help
+          Say 'Y' here if you want your kernel to support the OpenGear
+          IM4216 or IM4248 Console Servers. See http://www.opengear.com for
+          more details.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile
index 853efd9133c6..e370caf0c91b 100644
--- a/arch/arm/mach-ks8695/Makefile
+++ b/arch/arm/mach-ks8695/Makefile
@@ -11,10 +11,15 @@ obj-				:=
 # PCI support is optional
 obj-$(CONFIG_PCI)               += pci.o
 
-# LEDs
-obj-$(CONFIG_LEDS)              += leds.o
-
 # Board-specific support
 obj-$(CONFIG_MACH_KS8695)       += board-micrel.o
 obj-$(CONFIG_MACH_DSM320)       += board-dsm320.o
 obj-$(CONFIG_MACH_ACS5K)        += board-acs5k.o
+obj-$(CONFIG_MACH_LITE300)      += board-sg.o
+obj-$(CONFIG_MACH_SG310)        += board-sg.o
+obj-$(CONFIG_MACH_SE4200)       += board-sg.o
+obj-$(CONFIG_MACH_CM4002)       += board-og.o
+obj-$(CONFIG_MACH_CM4008)       += board-og.o
+obj-$(CONFIG_MACH_CM41xx)       += board-og.o
+obj-$(CONFIG_MACH_IM4004)       += board-og.o
+obj-$(CONFIG_MACH_IM42xx)       += board-og.o
diff --git a/arch/arm/mach-ks8695/board-og.c b/arch/arm/mach-ks8695/board-og.c
new file mode 100644
index 000000000000..1623ba461e47
--- /dev/null
+++ b/arch/arm/mach-ks8695/board-og.c
@@ -0,0 +1,199 @@
+/*
+ * board-og.c -- support for the OpenGear KS8695 based boards.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/devices.h>
+#include <mach/regs-gpio.h>
+#include <mach/gpio-ks8695.h>
+#include "generic.h"
+
+static int og_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        if (machine_is_im4004() && (slot == 8))
+                return KS8695_IRQ_EXTERN1;
+        return KS8695_IRQ_EXTERN0;
+}
+
+static struct ks8695_pci_cfg __initdata og_pci = {
+        .mode           = KS8695_MODE_PCI,
+        .map_irq        = og_pci_map_irq,
+};
+
+static void __init og_register_pci(void)
+{
+        /* Initialize the GPIO lines for interrupt mode */
+        ks8695_gpio_interrupt(KS8695_GPIO_0, IRQ_TYPE_LEVEL_LOW);
+
+        /* Cardbus Slot */
+        if (machine_is_im4004())
+                ks8695_gpio_interrupt(KS8695_GPIO_1, IRQ_TYPE_LEVEL_LOW);
+
+        ks8695_init_pci(&og_pci);
+}
+
+/*
+ * The PCI bus reset is driven by a dedicated GPIO line. Toggle it here
+ * and bring the PCI bus out of reset.
+ */
+static void __init og_pci_bus_reset(void)
+{
+        unsigned int rstline = 1;
+
+        /* Some boards use a different GPIO as the PCI reset line */
+        if (machine_is_im4004())
+                rstline = 2;
+        else if (machine_is_im42xx())
+                rstline = 0;
+
+        gpio_request(rstline, "PCI reset");
+        gpio_direction_output(rstline, 0);
+
+        /* Drive a reset on the PCI reset line */
+        gpio_set_value(rstline, 1);
+        gpio_set_value(rstline, 0);
+        mdelay(100);
+        gpio_set_value(rstline, 1);
+        mdelay(100);
+}
+
+/*
+ * Direct connect serial ports (non-PCI that is).
+ */
+#define S8250_PHYS      0x03800000
+#define S8250_VIRT      0xf4000000
+#define S8250_SIZE      0x00100000
+
+static struct __initdata map_desc og_io_desc[] = {
+        {
+                .virtual        = S8250_VIRT,
+                .pfn            = __phys_to_pfn(S8250_PHYS),
+                .length         = S8250_SIZE,
+                .type           = MT_DEVICE,
+        }
+};
+
+static struct resource og_uart_resources[] = {
+        {
+                .start          = S8250_VIRT,
+                .end            = S8250_VIRT + S8250_SIZE,
+                .flags          = IORESOURCE_MEM
+        },
+};
+
+static struct plat_serial8250_port og_uart_data[] = {
+        {
+                .mapbase        = S8250_VIRT,
+                .membase        = (char *) S8250_VIRT,
+                .irq            = 3,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 115200 * 16,
+        },
+        { },
+};
+
+static struct platform_device og_uart = {
+        .name                   = "serial8250",
+        .id                     = 0,
+        .dev.platform_data      = og_uart_data,
+        .num_resources          = 1,
+        .resource               = og_uart_resources
+};
+
+static struct platform_device *og_devices[] __initdata = {
+        &og_uart
+};
+
+static void __init og_init(void)
+{
+        ks8695_register_gpios();
+
+        if (machine_is_cm4002()) {
+                ks8695_gpio_interrupt(KS8695_GPIO_1, IRQ_TYPE_LEVEL_HIGH);
+                iotable_init(og_io_desc, ARRAY_SIZE(og_io_desc));
+                platform_add_devices(og_devices, ARRAY_SIZE(og_devices));
+        } else {
+                og_pci_bus_reset();
+                og_register_pci();
+        }
+
+        ks8695_add_device_lan();
+        ks8695_add_device_wan();
+}
+
+#ifdef CONFIG_MACH_CM4002
+MACHINE_START(CM4002, "OpenGear/CM4002")
+        /* OpenGear Inc. */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = og_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_CM4008
+MACHINE_START(CM4008, "OpenGear/CM4008")
+        /* OpenGear Inc. */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = og_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_CM41xx
+MACHINE_START(CM41XX, "OpenGear/CM41xx")
+        /* OpenGear Inc. */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = og_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_IM4004
+MACHINE_START(IM4004, "OpenGear/IM4004")
+        /* OpenGear Inc. */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = og_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_IM42xx
+MACHINE_START(IM42XX, "OpenGear/IM42xx")
+        /* OpenGear Inc. */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = og_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-ks8695/board-sg.c b/arch/arm/mach-ks8695/board-sg.c
new file mode 100644
index 000000000000..f35b98b5bf37
--- /dev/null
+++ b/arch/arm/mach-ks8695/board-sg.c
@@ -0,0 +1,121 @@
+/*
+ * board-sg.c -- support for the SnapGear KS8695 based boards
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/partitions.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/devices.h>
+#include "generic.h"
+
+/*
+ * The SG310 machine type is fitted with a conventional 8MB Strataflash
+ * device. Define its partitioning.
+ */
+#define FL_BASE         0x02000000
+#define FL_SIZE         SZ_8M
+
+static struct mtd_partition sg_mtd_partitions[] = {
+        [0] = {
+                .name   = "SnapGear Boot Loader",
+                .size   = SZ_128K,
+        },
+        [1] = {
+                .name   = "SnapGear non-volatile configuration",
+                .size   = SZ_512K,
+                .offset = SZ_256K,
+        },
+        [2] = {
+                .name   = "SnapGear image",
+                .offset = SZ_512K + SZ_256K,
+        },
+        [3] = {
+                .name   = "SnapGear StrataFlash",
+        },
+        [4] = {
+                .name   = "SnapGear Boot Tags",
+                .size   = SZ_128K,
+                .offset = SZ_128K,
+        },
+};
+
+static struct physmap_flash_data sg_mtd_pdata = {
+        .width          = 1,
+        .nr_parts       = ARRAY_SIZE(sg_mtd_partitions),
+        .parts          = sg_mtd_partitions,
+};
+
+
+static struct resource sg_mtd_resource[] = {
+        [0] = {
+                .start = FL_BASE,
+                .end   = FL_BASE + FL_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device sg_mtd_device = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(sg_mtd_resource),
+        .resource       = sg_mtd_resource,
+        .dev            = {
+                .platform_data = &sg_mtd_pdata,
+        },
+};
+
+static void __init sg_init(void)
+{
+        ks8695_add_device_lan();
+        ks8695_add_device_wan();
+
+        if (machine_is_sg310())
+                platform_device_register(&sg_mtd_device);
+}
+
+#ifdef CONFIG_MACH_LITE300
+MACHINE_START(LITE300, "SecureComputing/SG300")
+        /* SnapGear */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = sg_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_SG310
+MACHINE_START(SG310, "McAfee/SG310")
+        /* SnapGear */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = sg_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_SE4200
+MACHINE_START(SE4200, "SecureComputing/SE4200")
+        /* SnapGear */
+        .atag_offset    = 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = sg_init,
+        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c
index 73bd63812878..47399bc3c024 100644
--- a/arch/arm/mach-ks8695/devices.c
+++ b/arch/arm/mach-ks8695/devices.c
@@ -182,27 +182,6 @@ static void __init ks8695_add_device_watchdog(void)
 }
 
 
-/* --------------------------------------------------------------------
- *  LEDs
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_LEDS)
-short ks8695_leds_cpu = -1;
-short ks8695_leds_timer = -1;
-
-void __init ks8695_init_leds(u8 cpu_led, u8 timer_led)
-{
-        /* Enable GPIO to access the LEDs */
-        gpio_direction_output(cpu_led, 1);
-        gpio_direction_output(timer_led, 1);
-
-        ks8695_leds_cpu   = cpu_led;
-        ks8695_leds_timer = timer_led;
-}
-#else
-void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) {}
-#endif
-
 /* -------------------------------------------------------------------- */
 
 /*
diff --git a/arch/arm/mach-ks8695/include/mach/devices.h b/arch/arm/mach-ks8695/include/mach/devices.h
index 85a3c9aa7d13..1e6594a0f297 100644
--- a/arch/arm/mach-ks8695/include/mach/devices.h
+++ b/arch/arm/mach-ks8695/include/mach/devices.h
@@ -18,11 +18,6 @@ extern void __init ks8695_add_device_wan(void);
 extern void __init ks8695_add_device_lan(void);
 extern void __init ks8695_add_device_hpna(void);
 
- /* LEDs */
-extern short ks8695_leds_cpu;
-extern short ks8695_leds_timer;
-extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led);
-
  /* PCI */
 #define KS8695_MODE_PCI         0
 #define KS8695_MODE_MINIPCI     1
diff --git a/arch/arm/mach-ks8695/leds.c b/arch/arm/mach-ks8695/leds.c
deleted file mode 100644
index 4bd707547293..000000000000
--- a/arch/arm/mach-ks8695/leds.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * LED driver for KS8695-based boards.
- *
- * Copyright (C) Andrew Victor
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include <asm/leds.h>
-#include <mach/devices.h>
-
-
-static inline void ks8695_led_on(unsigned int led)
-{
-        gpio_set_value(led, 0);
-}
-
-static inline void ks8695_led_off(unsigned int led)
-{
-        gpio_set_value(led, 1);
-}
-
-static inline void ks8695_led_toggle(unsigned int led)
-{
-        unsigned long is_off = gpio_get_value(led);
-        if (is_off)
-                ks8695_led_on(led);
-        else
-                ks8695_led_off(led);
-}
-
-
-/*
- * Handle LED events.
- */
-static void ks8695_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        switch(evt) {
-        case led_start:         /* System startup */
-                ks8695_led_on(ks8695_leds_cpu);
-                break;
-
-        case led_stop:          /* System stop / suspend */
-                ks8695_led_off(ks8695_leds_cpu);
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:         /* Every 50 timer ticks */
-                ks8695_led_toggle(ks8695_leds_timer);
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:    /* Entering idle state */
-                ks8695_led_off(ks8695_leds_cpu);
-                break;
-
-        case led_idle_end:      /* Exit idle state */
-                ks8695_led_on(ks8695_leds_cpu);
-                break;
-#endif
-
-        default:
-                break;
-        }
-
-        local_irq_restore(flags);
-}
-
-
-static int __init leds_init(void)
-{
-        if ((ks8695_leds_timer == -1) || (ks8695_leds_cpu == -1))
-                return -ENODEV;
-
-        leds_event = ks8695_leds_event;
-
-        leds_event(led_start);
-        return 0;
-}
-
-__initcall(leds_init);
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h b/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
index 1816e22a3479..a544e962a818 100644
--- a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
@@ -30,7 +30,7 @@
 #define LPC32XX_GPIO_P1_MAX 24
 #define LPC32XX_GPIO_P2_MAX 13
 #define LPC32XX_GPIO_P3_MAX 6
-#define LPC32XX_GPI_P3_MAX 28
+#define LPC32XX_GPI_P3_MAX 29
 #define LPC32XX_GPO_P3_MAX 24
 
 #define LPC32XX_GPIO_P0_GRP 0
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 8f2a2f8712d7..e8ff4c3f0566 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -24,12 +24,9 @@
 #include <linux/irq.h>
 #include <linux/dma-mapping.h>
 #include <linux/device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/eeprom.h>
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
-#include <linux/amba/pl022.h>
 #include <linux/amba/pl08x.h>
 #include <linux/amba/mmci.h>
 #include <linux/of.h>
@@ -158,21 +155,6 @@ static struct clcd_board lpc32xx_clcd_data = {
         .remove         = lpc32xx_clcd_remove,
 };
 
-/*
- * AMBA SSP (SPI)
- */
-static struct pl022_ssp_controller lpc32xx_ssp0_data = {
-        .bus_id                 = 0,
-        .num_chipselect         = 1,
-        .enable_dma             = 0,
-};
-
-static struct pl022_ssp_controller lpc32xx_ssp1_data = {
-        .bus_id                 = 1,
-        .num_chipselect         = 1,
-        .enable_dma             = 0,
-};
-
 static struct pl08x_channel_data pl08x_slave_channels[] = {
         {
                 .bus_id = "nand-slc",
@@ -234,8 +216,8 @@ static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
 };
 
 static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
-        OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
+        OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL),
+        OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL),
         OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
         OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
         OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
index b6f14d203c25..5c3cc29688ab 100644
--- a/arch/arm/mach-mmp/include/mach/debug-macro.S
+++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
@@ -9,13 +9,21 @@
  * published by the Free Software Foundation.
  */
 
+#if defined(CONFIG_DEBUG_MMP_UART2)
+#define MMP_UART_OFFSET 0x00017000
+#elif defined(CONFIG_DEBUG_MMP_UART3)
+#define MMP_UART_OFFSET 0x00018000
+#else
+#error "Select uart for DEBUG_LL"
+#endif
+
 #include <mach/addr-map.h>
 
                 .macro  addruart, rp, rv, tmp
                 ldr     \rp, =APB_PHYS_BASE             @ physical
                 ldr     \rv, =APB_VIRT_BASE             @ virtual
-                orr     \rp, \rp, #0x00017000
-                orr     \rv, \rv, #0x00017000
+                orr     \rp, \rp, #MMP_UART_OFFSET
+                orr     \rv, \rv, #MMP_UART_OFFSET
                 .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 7a7de2b12a62..ce55fd8821c4 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -177,12 +177,22 @@ static struct mv_usb_platform_data ttc_usb_pdata = {
 #endif
 #endif
 
+#ifdef CONFIG_MTD_NAND_PXA3xx
+static struct pxa3xx_nand_platform_data dkb_nand_info = {
+        .enable_arbiter = 1,
+        .num_cs = 1,
+};
+#endif
+
 static void __init ttc_dkb_init(void)
 {
         mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
 
         /* on-chip devices */
         pxa910_add_uart(1);
+#ifdef CONFIG_MTD_NAND_PXA3xx
+        pxa910_add_nand(&dkb_nand_info);
+#endif
 
         /* off-chip devices */
         pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index b2740c800e8c..7902de151cc5 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1,8 +1,12 @@
 if ARCH_MSM
 
+comment "Qualcomm MSM SoC Type"
+        depends on (ARCH_MSM8X60 || ARCH_MSM8960)
+
 choice
         prompt "Qualcomm MSM SoC Type"
         default ARCH_MSM7X00A
+        depends on !(ARCH_MSM8X60 || ARCH_MSM8960)
 
 config ARCH_MSM7X00A
         bool "MSM7x00A / MSM7x01A"
@@ -36,6 +40,8 @@ config ARCH_QSD8X50
         select GPIO_MSM_V1
         select MSM_PROC_COMM
 
+endchoice
+
 config ARCH_MSM8X60
         bool "MSM8X60"
         select ARCH_MSM_SCORPIONMP
@@ -57,8 +63,6 @@ config ARCH_MSM8960
         select MSM_SCM if SMP
         select USE_OF
 
-endchoice
-
 config MSM_HAS_DEBUG_UART_HS
         bool
 
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index a344a373928b..2448fcf09eb1 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -37,8 +37,8 @@
 #include "devices.h"
 #include "common.h"
 
-static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
-static const unsigned        qsd8x50_surf_smc91x_gpio __initdata = 156;
+static const resource_size_t qsd8x50_surf_smc91x_base __initconst = 0x70000300;
+static const unsigned        qsd8x50_surf_smc91x_gpio __initconst = 156;
 
 /* Leave smc91x resources empty here, as we'll fill them in
  * at run-time: they vary from board to board, and the true
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index c6d38f1d0c98..199372e62def 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -41,21 +41,10 @@
 #define MSM8X60_QGIC_CPU_PHYS   0x02081000
 #define MSM8X60_QGIC_CPU_SIZE   SZ_4K
 
-#define MSM_ACC_BASE            IOMEM(0xF0002000)
-#define MSM_ACC_PHYS            0x02001000
-#define MSM_ACC_SIZE            SZ_4K
-
-#define MSM_GCC_BASE            IOMEM(0xF0003000)
-#define MSM_GCC_PHYS            0x02082000
-#define MSM_GCC_SIZE            SZ_4K
-
 #define MSM_TLMM_BASE           IOMEM(0xF0004000)
 #define MSM_TLMM_PHYS           0x00800000
 #define MSM_TLMM_SIZE           SZ_16K
 
-#define MSM_SHARED_RAM_BASE     IOMEM(0xF0100000)
-#define MSM_SHARED_RAM_SIZE     SZ_1M
-
 #define MSM8X60_TMR_PHYS        0x02000000
 #define MSM8X60_TMR_SIZE        SZ_4K
 
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 00afdfb8c38f..2ab7cf0919b3 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -41,12 +41,11 @@
 #include "msm_iomap-7x30.h"
 #elif defined(CONFIG_ARCH_QSD8X50)
 #include "msm_iomap-8x50.h"
-#elif defined(CONFIG_ARCH_MSM8X60)
-#include "msm_iomap-8x60.h"
 #else
 #include "msm_iomap-7x00.h"
 #endif
 
+#include "msm_iomap-8x60.h"
 #include "msm_iomap-8960.h"
 
 #define MSM_DEBUG_UART_SIZE     SZ_4K
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 3854f6f20ce2..123ef9cbce1b 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -111,8 +111,6 @@ static struct map_desc msm8x60_io_desc[] __initdata = {
         MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60),
         MSM_CHIP_DEVICE(TMR, MSM8X60),
         MSM_CHIP_DEVICE(TMR0, MSM8X60),
-        MSM_DEVICE(ACC),
-        MSM_DEVICE(GCC),
 #ifdef CONFIG_DEBUG_MSM8660_UART
         MSM_DEVICE(DEBUG_UART),
 #endif
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c
index 23ca9d083b2c..8fb23af154b3 100644
--- a/arch/arm/mach-mxs/icoll.c
+++ b/arch/arm/mach-mxs/icoll.c
@@ -19,20 +19,27 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
-
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <asm/exception.h>
 #include <mach/mxs.h>
 #include <mach/common.h>
 
 #define HW_ICOLL_VECTOR                         0x0000
 #define HW_ICOLL_LEVELACK                       0x0010
 #define HW_ICOLL_CTRL                           0x0020
+#define HW_ICOLL_STAT_OFFSET                    0x0070
 #define HW_ICOLL_INTERRUPTn_SET(n)              (0x0124 + (n) * 0x10)
 #define HW_ICOLL_INTERRUPTn_CLR(n)              (0x0128 + (n) * 0x10)
 #define BM_ICOLL_INTERRUPTn_ENABLE              0x00000004
 #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
 
+#define ICOLL_NUM_IRQS          128
+
 static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR);
+static struct irq_domain *icoll_domain;
 
 static void icoll_ack_irq(struct irq_data *d)
 {
@@ -48,13 +55,13 @@ static void icoll_ack_irq(struct irq_data *d)
 static void icoll_mask_irq(struct irq_data *d)
 {
         __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
-                        icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->irq));
+                        icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->hwirq));
 }
 
 static void icoll_unmask_irq(struct irq_data *d)
 {
         __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
-                        icoll_base + HW_ICOLL_INTERRUPTn_SET(d->irq));
+                        icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq));
 }
 
 static struct irq_chip mxs_icoll_chip = {
@@ -63,18 +70,56 @@ static struct irq_chip mxs_icoll_chip = {
         .irq_unmask = icoll_unmask_irq,
 };
 
-void __init icoll_init_irq(void)
+asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
 {
-        int i;
+        u32 irqnr;
+
+        do {
+                irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
+                if (irqnr != 0x7f) {
+                        __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
+                        irqnr = irq_find_mapping(icoll_domain, irqnr);
+                        handle_IRQ(irqnr, regs);
+                        continue;
+                }
+                break;
+        } while (1);
+}
+
+static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
+                                irq_hw_number_t hw)
+{
+        irq_set_chip_and_handler(virq, &mxs_icoll_chip, handle_level_irq);
+        set_irq_flags(virq, IRQF_VALID);
+
+        return 0;
+}
 
+static struct irq_domain_ops icoll_irq_domain_ops = {
+        .map = icoll_irq_domain_map,
+        .xlate = irq_domain_xlate_onecell,
+};
+
+void __init icoll_of_init(struct device_node *np,
+                          struct device_node *interrupt_parent)
+{
         /*
          * Interrupt Collector reset, which initializes the priority
          * for each irq to level 0.
          */
         mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
 
-        for (i = 0; i < MXS_INTERNAL_IRQS; i++) {
-                irq_set_chip_and_handler(i, &mxs_icoll_chip, handle_level_irq);
-                set_irq_flags(i, IRQF_VALID);
-        }
+        icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS,
+                                             &icoll_irq_domain_ops, NULL);
+        WARN_ON(!icoll_domain);
+}
+
+static const struct of_device_id icoll_of_match[] __initconst = {
+        {.compatible = "fsl,icoll", .data = icoll_of_init},
+        { /* sentinel */ }
+};
+
+void __init icoll_init_irq(void)
+{
+        of_irq_init(icoll_of_match);
 }
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index 4dec79563f19..be5a9c93cb2a 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -13,7 +13,7 @@
 
 extern const u32 *mxs_get_ocotp(void);
 extern int mxs_reset_block(void __iomem *);
-extern void mxs_timer_init(int);
+extern void mxs_timer_init(void);
 extern void mxs_restart(char, const char *);
 extern int mxs_saif_clkmux_select(unsigned int clkmux);
 
@@ -24,5 +24,6 @@ extern int mx28_clocks_init(void);
 extern void mx28_map_io(void);
 
 extern void icoll_init_irq(void);
+extern void icoll_handle_irq(struct pt_regs *);
 
 #endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/entry-macro.S b/arch/arm/mach-mxs/include/mach/entry-macro.S
deleted file mode 100644
index 0c14259705b9..000000000000
--- a/arch/arm/mach-mxs/include/mach/entry-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Low-level IRQ helper macros for Freescale MXS-based
- *
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <mach/mxs.h>
-
-#define MXS_ICOLL_VBASE         MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR)
-#define HW_ICOLL_STAT_OFFSET    0x70
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqnr, [\base, #HW_ICOLL_STAT_OFFSET]
-        cmp     \irqnr, #0x7F
-        strne   \irqnr, [\base]
-        moveqs  \irqnr, #0
-        .endm
-
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =MXS_ICOLL_VBASE
-        .endm
diff --git a/arch/arm/mach-mxs/include/mach/irqs.h b/arch/arm/mach-mxs/include/mach/irqs.h
deleted file mode 100644
index f771039b814a..000000000000
--- a/arch/arm/mach-mxs/include/mach/irqs.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_MXS_IRQS_H__
-#define __MACH_MXS_IRQS_H__
-
-#define MXS_INTERNAL_IRQS       128
-
-#define MXS_GPIO_IRQ_START      MXS_INTERNAL_IRQS
-
-/* the maximum for MXS-based */
-#define MXS_GPIO_IRQS           (32 * 5)
-
-/*
- * The next 16 interrupts are for board specific purposes.  Since
- * the kernel can only run on one machine at a time, we can re-use
- * these.  If you need more, increase MXS_BOARD_IRQS, but keep it
- * within sensible limits.
- */
-#define MXS_BOARD_IRQ_START     (MXS_GPIO_IRQ_START + MXS_GPIO_IRQS)
-#define MXS_BOARD_IRQS          16
-
-#define NR_IRQS                 (MXS_BOARD_IRQ_START + MXS_BOARD_IRQS)
-
-#endif /* __MACH_MXS_IRQS_H__ */
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 433af893ad8a..4748ec551a68 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -17,10 +17,8 @@
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
-#include <linux/irqdomain.h>
 #include <linux/micrel_phy.h>
 #include <linux/mxsfb.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/pinctrl/consumer.h>
@@ -141,37 +139,6 @@ static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
         { /* sentinel */ }
 };
 
-static int __init mxs_icoll_add_irq_domain(struct device_node *np,
-                                struct device_node *interrupt_parent)
-{
-        irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
-
-        return 0;
-}
-
-static int __init mxs_gpio_add_irq_domain(struct device_node *np,
-                                struct device_node *interrupt_parent)
-{
-        static int gpio_irq_base = MXS_GPIO_IRQ_START;
-
-        irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
-        gpio_irq_base += 32;
-
-        return 0;
-}
-
-static const struct of_device_id mxs_irq_match[] __initconst = {
-        { .compatible = "fsl,mxs-icoll", .data = mxs_icoll_add_irq_domain, },
-        { .compatible = "fsl,mxs-gpio", .data = mxs_gpio_add_irq_domain, },
-        { /* sentinel */ }
-};
-
-static void __init mxs_dt_init_irq(void)
-{
-        icoll_init_irq();
-        of_irq_init(mxs_irq_match);
-}
-
 static void __init imx23_timer_init(void)
 {
         mx23_clocks_init();
@@ -305,7 +272,7 @@ static void __init apx4devkit_init(void)
         enable_clk_enet_out();
 
         if (IS_BUILTIN(CONFIG_PHYLIB))
-                phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK,
+                phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK,
                                            apx4devkit_phy_fixup);
 
         mxsfb_pdata.mode_list = apx4devkit_video_modes;
@@ -421,7 +388,8 @@ static const char *imx28_dt_compat[] __initdata = {
 
 DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)")
         .map_io         = mx23_map_io,
-        .init_irq       = mxs_dt_init_irq,
+        .init_irq       = icoll_init_irq,
+        .handle_irq     = icoll_handle_irq,
         .timer          = &imx23_timer,
         .init_machine   = mxs_machine_init,
         .dt_compat      = imx23_dt_compat,
@@ -430,7 +398,8 @@ MACHINE_END
 
 DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
         .map_io         = mx28_map_io,
-        .init_irq       = mxs_dt_init_irq,
+        .init_irq       = icoll_init_irq,
+        .handle_irq     = icoll_handle_irq,
         .timer          = &imx28_timer,
         .init_machine   = mxs_machine_init,
         .dt_compat      = imx28_dt_compat,
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
index 02d36de9c4e8..7c3792613392 100644
--- a/arch/arm/mach-mxs/timer.c
+++ b/arch/arm/mach-mxs/timer.c
@@ -25,6 +25,8 @@
 #include <linux/irq.h>
 #include <linux/clockchips.h>
 #include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
 
 #include <asm/mach/time.h>
 #include <mach/mxs.h>
@@ -244,9 +246,17 @@ static int __init mxs_clocksource_init(struct clk *timer_clk)
         return 0;
 }
 
-void __init mxs_timer_init(int irq)
+void __init mxs_timer_init(void)
 {
+        struct device_node *np;
         struct clk *timer_clk;
+        int irq;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,timrot");
+        if (!np) {
+                pr_err("%s: failed find timrot node\n", __func__);
+                return;
+        }
 
         timer_clk = clk_get_sys("timrot", NULL);
         if (IS_ERR(timer_clk)) {
@@ -295,5 +305,6 @@ void __init mxs_timer_init(int irq)
         mxs_clockevent_init(timer_clk);
 
         /* Make irqs happen */
+        irq = irq_of_parse_and_map(np, 0);
         setup_irq(irq, &mxs_timer_irq);
 }
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 381c08027df4..bfa1eab91f41 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -23,6 +23,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/i2c.h>
 #include <linux/io.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/hardware/vic.h>
 #include <asm/sizes.h>
 #include <asm/mach-types.h>
@@ -33,6 +34,7 @@
 
 #include <plat/gpio-nomadik.h>
 #include <plat/mtu.h>
+#include <plat/pincfg.h>
 
 #include <linux/platform_data/mtd-nomadik-nand.h>
 #include <mach/fsmc.h>
@@ -112,8 +114,7 @@ static struct mtd_partition nhk8815_partitions[] = {
 static struct nomadik_nand_platform_data nhk8815_nand_data = {
         .parts          = nhk8815_partitions,
         .nparts         = ARRAY_SIZE(nhk8815_partitions),
-        .options        = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING \
-                        | NAND_NO_READRDY,
+        .options        = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING,
         .init           = nhk8815_nand_init,
 };
 
@@ -291,8 +292,42 @@ static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = {
         },
 };
 
+static unsigned long out_low[] = { PIN_OUTPUT_LOW };
+static unsigned long out_high[] = { PIN_OUTPUT_HIGH };
+static unsigned long in_nopull[] = { PIN_INPUT_NOPULL };
+static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
+
+static struct pinctrl_map __initdata nhk8815_pinmap[] = {
+        PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
+        /* Hog in MMC/SD card mux */
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
+        /* MCCLK */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
+        /* MCCMD */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
+        /* MCCMDDIR */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
+        /* MCDAT3-0 */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
+        /* MCDAT0DIR */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
+        /* MCDAT31DIR */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
+        /* MCMSFBCLK */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
+        /* CD input GPIO */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
+        /* CD bias drive */
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
+};
+
 static void __init nhk8815_platform_init(void)
 {
+        pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
         cpu8815_platform_init();
         nhk8815_onenand_init();
         platform_add_devices(nhk8815_platform_devices,
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 6fd8e46567a4..b617eaed0ce5 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -83,6 +83,18 @@ void cpu8815_add_gpios(resource_size_t *base, int num, int irq,
         }
 }
 
+static inline void
+cpu8815_add_pinctrl(struct device *parent, const char *name)
+{
+        struct platform_device_info pdevinfo = {
+                .parent = parent,
+                .name = name,
+                .id = -1,
+        };
+
+        platform_device_register_full(&pdevinfo);
+}
+
 static int __init cpu8815_init(void)
 {
         struct nmk_gpio_platform_data pdata = {
@@ -91,6 +103,7 @@ static int __init cpu8815_init(void)
 
         cpu8815_add_gpios(cpu8815_gpio_base, ARRAY_SIZE(cpu8815_gpio_base),
                           IRQ_GPIO0, &pdata);
+        cpu8815_add_pinctrl(NULL, "pinctrl-stn8815");
         amba_apb_device_add(NULL, "rng", NOMADIK_RNG_BASE, SZ_4K, 0, 0, NULL, 0);
         amba_apb_device_add(NULL, "rtc-pl031", NOMADIK_RTC_BASE, SZ_4K, IRQ_RTC_RTT, 0, NULL, 0);
         return 0;
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 398e9e53e189..cd169c386161 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -61,14 +61,6 @@ obj-$(CONFIG_ARCH_OMAP850)		+= gpio7xx.o
 obj-$(CONFIG_ARCH_OMAP15XX)             += gpio15xx.o
 obj-$(CONFIG_ARCH_OMAP16XX)             += gpio16xx.o
 
-# LEDs support
-led-$(CONFIG_MACH_OMAP_H2)              += leds-h2p2-debug.o
-led-$(CONFIG_MACH_OMAP_H3)              += leds-h2p2-debug.o
-led-$(CONFIG_MACH_OMAP_INNOVATOR)       += leds-innovator.o
-led-$(CONFIG_MACH_OMAP_PERSEUS2)        += leds-h2p2-debug.o
-led-$(CONFIG_MACH_OMAP_OSK)             += leds-osk.o
-obj-$(CONFIG_LEDS)                      += $(led-y)
-
 ifneq ($(CONFIG_FB_OMAP),)
 obj-y += lcd_dma.o
 endif
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index af283a2bc7c7..376f7f29ef77 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -32,6 +32,7 @@
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <linux/leds.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -307,12 +308,39 @@ static struct platform_device h2_irda_device = {
         .resource       = h2_irda_resources,
 };
 
+static struct gpio_led h2_gpio_led_pins[] = {
+        {
+                .name           = "h2:red",
+                .default_trigger = "heartbeat",
+                .gpio           = 3,
+        },
+        {
+                .name           = "h2:green",
+                .default_trigger = "cpu0",
+                .gpio           = OMAP_MPUIO(4),
+        },
+};
+
+static struct gpio_led_platform_data h2_gpio_led_data = {
+        .leds           = h2_gpio_led_pins,
+        .num_leds       = ARRAY_SIZE(h2_gpio_led_pins),
+};
+
+static struct platform_device h2_gpio_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &h2_gpio_led_data,
+        },
+};
+
 static struct platform_device *h2_devices[] __initdata = {
         &h2_nor_device,
         &h2_nand_device,
         &h2_smc91x_device,
         &h2_irda_device,
         &h2_kp_device,
+        &h2_gpio_leds,
 };
 
 static void __init h2_init_smc91x(void)
@@ -407,6 +435,10 @@ static void __init h2_init(void)
         omap_cfg_reg(E19_1610_KBR4);
         omap_cfg_reg(N19_1610_KBR5);
 
+        /* GPIO based LEDs */
+        omap_cfg_reg(P18_1610_GPIO3);
+        omap_cfg_reg(MPUIO4);
+
         h2_smc91x_resources[1].start = gpio_to_irq(0);
         h2_smc91x_resources[1].end = gpio_to_irq(0);
         platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 06d11b1ee9c6..ededdb7ef28c 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -32,6 +32,7 @@
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <linux/leds.h>
 
 #include <asm/setup.h>
 #include <asm/page.h>
@@ -325,6 +326,32 @@ static struct spi_board_info h3_spi_board_info[] __initdata = {
         },
 };
 
+static struct gpio_led h3_gpio_led_pins[] = {
+        {
+                .name           = "h3:red",
+                .default_trigger = "heartbeat",
+                .gpio           = 3,
+        },
+        {
+                .name           = "h3:green",
+                .default_trigger = "cpu0",
+                .gpio           = OMAP_MPUIO(4),
+        },
+};
+
+static struct gpio_led_platform_data h3_gpio_led_data = {
+        .leds           = h3_gpio_led_pins,
+        .num_leds       = ARRAY_SIZE(h3_gpio_led_pins),
+};
+
+static struct platform_device h3_gpio_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &h3_gpio_led_data,
+        },
+};
+
 static struct platform_device *devices[] __initdata = {
         &nor_device,
         &nand_device,
@@ -332,6 +359,7 @@ static struct platform_device *devices[] __initdata = {
         &intlat_device,
         &h3_kp_device,
         &h3_lcd_device,
+        &h3_gpio_leds,
 };
 
 static struct omap_usb_config h3_usb_config __initdata = {
@@ -399,6 +427,10 @@ static void __init h3_init(void)
         omap_cfg_reg(E19_1610_KBR4);
         omap_cfg_reg(N19_1610_KBR5);
 
+        /* GPIO based LEDs */
+        omap_cfg_reg(P18_1610_GPIO3);
+        omap_cfg_reg(MPUIO4);
+
         smc91x_resources[1].start = gpio_to_irq(40);
         smc91x_resources[1].end = gpio_to_irq(40);
         platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 2f1f9b967576..5973945a8741 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -382,10 +382,37 @@ static struct platform_device osk5912_lcd_device = {
         .id             = -1,
 };
 
+static struct gpio_led mistral_gpio_led_pins[] = {
+        {
+                .name           = "mistral:red",
+                .default_trigger = "heartbeat",
+                .gpio           = 3,
+        },
+        {
+                .name           = "mistral:green",
+                .default_trigger = "cpu0",
+                .gpio           = OMAP_MPUIO(4),
+        },
+};
+
+static struct gpio_led_platform_data mistral_gpio_led_data = {
+        .leds           = mistral_gpio_led_pins,
+        .num_leds       = ARRAY_SIZE(mistral_gpio_led_pins),
+};
+
+static struct platform_device mistral_gpio_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &mistral_gpio_led_data,
+        },
+};
+
 static struct platform_device *mistral_devices[] __initdata = {
         &osk5912_kp_device,
         &mistral_bl_device,
         &osk5912_lcd_device,
+        &mistral_gpio_leds,
 };
 
 static int mistral_get_pendown_state(void)
@@ -510,6 +537,12 @@ static void __init osk_mistral_init(void)
         if (gpio_request(2, "lcd_pwr") == 0)
                 gpio_direction_output(2, 1);
 
+        /*
+         * GPIO based LEDs
+         */
+        omap_cfg_reg(P18_1610_GPIO3);
+        omap_cfg_reg(MPUIO4);
+
         i2c_register_board_info(1, mistral_i2c_board_info,
                         ARRAY_SIZE(mistral_i2c_board_info));
 
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
deleted file mode 100644
index 6f958aec9459..000000000000
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds-h2p2-debug.c
- *
- * Copyright 2003 by Texas Instruments Incorporated
- *
- * There are 16 LEDs on the debug board (all green); four may be used
- * for logical 'green', 'amber', 'red', and 'blue' (after "claiming").
- *
- * The "surfer" expansion board and H2 sample board also have two-color
- * green+red LEDs (in parallel), used here for timer and idle indicators.
- */
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/sched.h>
-#include <linux/io.h>
-#include <linux/platform_data/gpio-omap.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#include <plat/fpga.h>
-
-#include "leds.h"
-
-
-#define GPIO_LED_RED            3
-#define GPIO_LED_GREEN          OMAP_MPUIO(4)
-
-
-#define LED_STATE_ENABLED       0x01
-#define LED_STATE_CLAIMED       0x02
-#define LED_TIMER_ON            0x04
-
-#define GPIO_IDLE               GPIO_LED_GREEN
-#define GPIO_TIMER              GPIO_LED_RED
-
-
-void h2p2_dbg_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        static struct h2p2_dbg_fpga __iomem *fpga;
-        static u16 led_state, hw_led_state;
-
-        local_irq_save(flags);
-
-        if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
-                goto done;
-
-        switch (evt) {
-        case led_start:
-                if (!fpga)
-                        fpga = ioremap(H2P2_DBG_FPGA_START,
-                                                H2P2_DBG_FPGA_SIZE);
-                if (fpga) {
-                        led_state |= LED_STATE_ENABLED;
-                        __raw_writew(~0, &fpga->leds);
-                }
-                break;
-
-        case led_stop:
-        case led_halted:
-                /* all leds off during suspend or shutdown */
-
-                if (! machine_is_omap_perseus2()) {
-                        gpio_set_value(GPIO_TIMER, 0);
-                        gpio_set_value(GPIO_IDLE, 0);
-                }
-
-                led_state &= ~LED_STATE_ENABLED;
-                if (fpga) {
-                        __raw_writew(~0, &fpga->leds);
-                        if (evt == led_halted) {
-                                iounmap(fpga);
-                                fpga = NULL;
-                        }
-                }
-
-                goto done;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                led_state ^= LED_TIMER_ON;
-
-                if (machine_is_omap_perseus2())
-                        hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER;
-                else {
-                        gpio_set_value(GPIO_TIMER, led_state & LED_TIMER_ON);
-                        goto done;
-                }
-
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (machine_is_omap_perseus2())
-                        hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE;
-                else {
-                        gpio_set_value(GPIO_IDLE, 1);
-                        goto done;
-                }
-
-                break;
-
-        case led_idle_end:
-                if (machine_is_omap_perseus2())
-                        hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE;
-                else {
-                        gpio_set_value(GPIO_IDLE, 0);
-                        goto done;
-                }
-
-                break;
-#endif
-
-        case led_green_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_GREEN;
-                break;
-        case led_green_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_GREEN;
-                break;
-
-        case led_amber_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_AMBER;
-                break;
-        case led_amber_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_AMBER;
-                break;
-
-        case led_red_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_RED;
-                break;
-        case led_red_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_RED;
-                break;
-
-        case led_blue_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_BLUE;
-                break;
-        case led_blue_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_BLUE;
-                break;
-
-        default:
-                break;
-        }
-
-
-        /*
-         *  Actually burn the LEDs
-         */
-        if (led_state & LED_STATE_ENABLED && fpga)
-                __raw_writew(~hw_led_state, &fpga->leds);
-
-done:
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-omap1/leds-innovator.c b/arch/arm/mach-omap1/leds-innovator.c
deleted file mode 100644
index 3a066ee8d02c..000000000000
--- a/arch/arm/mach-omap1/leds-innovator.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds-innovator.c
- */
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-void innovator_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        switch (evt) {
-        case led_start:
-                hw_led_state = 0;
-                led_state = LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                hw_led_state = 0;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= 0;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= 0;
-                break;
-
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~0;
-                break;
-#endif
-
-        case led_halted:
-                break;
-
-        case led_green_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~0;
-                break;
-
-        case led_green_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= 0;
-                break;
-
-        case led_amber_on:
-                break;
-
-        case led_amber_off:
-                break;
-
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~0;
-                break;
-
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= 0;
-                break;
-
-        default:
-                break;
-        }
-
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c
deleted file mode 100644
index 936ed426b84f..000000000000
--- a/arch/arm/mach-omap1/leds-osk.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds-osk.c
- *
- * LED driver for OSK with optional Mistral QVGA board
- */
-#include <linux/gpio.h>
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED       (1 << 0)
-#define LED_STATE_CLAIMED       (1 << 1)
-static u8 led_state;
-
-#define TIMER_LED               (1 << 3)        /* Mistral board */
-#define IDLE_LED                (1 << 4)        /* Mistral board */
-static u8 hw_led_state;
-
-
-#ifdef  CONFIG_OMAP_OSK_MISTRAL
-
-/* For now, all system indicators require the Mistral board, since that
- * LED can be manipulated without a task context.  This LED is either red,
- * or green, but not both; it can't give the full "disco led" effect.
- */
-
-#define GPIO_LED_RED            3
-#define GPIO_LED_GREEN          OMAP_MPUIO(4)
-
-static void mistral_setled(void)
-{
-        int     red = 0;
-        int     green = 0;
-
-        if (hw_led_state & TIMER_LED)
-                red = 1;
-        else if (hw_led_state & IDLE_LED)
-                green = 1;
-        /* else both sides are disabled */
-
-        gpio_set_value(GPIO_LED_GREEN, green);
-        gpio_set_value(GPIO_LED_RED, red);
-}
-
-#endif
-
-void osk_leds_event(led_event_t evt)
-{
-        unsigned long   flags;
-        u16             leds;
-
-        local_irq_save(flags);
-
-        if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
-                goto done;
-
-        leds = hw_led_state;
-        switch (evt) {
-        case led_start:
-                led_state |= LED_STATE_ENABLED;
-                hw_led_state = 0;
-                leds = ~0;
-                break;
-
-        case led_halted:
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                hw_led_state = 0;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                leds = ~0;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-
-#ifdef  CONFIG_OMAP_OSK_MISTRAL
-
-        case led_timer:
-                hw_led_state ^= TIMER_LED;
-                mistral_setled();
-                break;
-
-        case led_idle_start:    /* idle == off */
-                hw_led_state &= ~IDLE_LED;
-                mistral_setled();
-                break;
-
-        case led_idle_end:
-                hw_led_state |= IDLE_LED;
-                mistral_setled();
-                break;
-
-#endif  /* CONFIG_OMAP_OSK_MISTRAL */
-
-        default:
-                break;
-        }
-
-        leds ^= hw_led_state;
-
-done:
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c
deleted file mode 100644
index 4071479f7106..000000000000
--- a/arch/arm/mach-omap1/leds.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds.c
- *
- * OMAP LEDs dispatcher
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_data/gpio-omap.h>
-
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#include <mach/mux.h>
-
-#include "leds.h"
-
-static int __init
-omap_leds_init(void)
-{
-        if (!cpu_class_is_omap1())
-                return -ENODEV;
-
-        if (machine_is_omap_innovator())
-                leds_event = innovator_leds_event;
-
-        else if (machine_is_omap_h2()
-                        || machine_is_omap_h3()
-                        || machine_is_omap_perseus2())
-                leds_event = h2p2_dbg_leds_event;
-
-        else if (machine_is_omap_osk())
-                leds_event = osk_leds_event;
-
-        else
-                return -1;
-
-        if (machine_is_omap_h2()
-                        || machine_is_omap_h3()
-#ifdef  CONFIG_OMAP_OSK_MISTRAL
-                        || machine_is_omap_osk()
-#endif
-                        ) {
-
-                /* LED1/LED2 pins can be used as GPIO (as done here), or by
-                 * the LPG (works even in deep sleep!), to drive a bicolor
-                 * LED on the H2 sample board, and another on the H2/P2
-                 * "surfer" expansion board.
-                 *
-                 * The same pins drive a LED on the OSK Mistral board, but
-                 * that's a different kind of LED (just one color at a time).
-                 */
-                omap_cfg_reg(P18_1610_GPIO3);
-                if (gpio_request(3, "LED red") == 0)
-                        gpio_direction_output(3, 1);
-                else
-                        printk(KERN_WARNING "LED: can't get GPIO3/red?\n");
-
-                omap_cfg_reg(MPUIO4);
-                if (gpio_request(OMAP_MPUIO(4), "LED green") == 0)
-                        gpio_direction_output(OMAP_MPUIO(4), 1);
-                else
-                        printk(KERN_WARNING "LED: can't get MPUIO4/green?\n");
-        }
-
-        leds_event(led_start);
-        return 0;
-}
-
-__initcall(omap_leds_init);
diff --git a/arch/arm/mach-omap1/leds.h b/arch/arm/mach-omap1/leds.h
deleted file mode 100644
index a1e9fedc376c..000000000000
--- a/arch/arm/mach-omap1/leds.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern void innovator_leds_event(led_event_t evt);
-extern void h2p2_dbg_leds_event(led_event_t evt);
-extern void osk_leds_event(led_event_t evt);
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 4062480bfec7..4d4816fd6fc9 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -44,7 +44,6 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 
-#include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/sched_clock.h>
 
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index eae49c3980c9..74529549130c 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -46,7 +46,6 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 
-#include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index eef99b77c40b..a6219eaf1f68 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -25,6 +25,9 @@ config ARCH_OMAP2PLUS_TYPICAL
 config SOC_HAS_OMAP2_SDRC
         bool "OMAP2 SDRAM Controller support"
 
+config SOC_HAS_REALTIME_COUNTER
+        bool "Real time free running counter"
+
 config ARCH_OMAP2
         bool "TI OMAP2"
         depends on ARCH_OMAP2PLUS
@@ -45,6 +48,7 @@ config ARCH_OMAP3
         select ARM_CPU_SUSPEND if PM
         select MULTI_IRQ_HANDLER
         select SOC_HAS_OMAP2_SDRC
+        select OMAP_INTERCONNECT
 
 config ARCH_OMAP4
         bool "TI OMAP4"
@@ -64,6 +68,7 @@ config ARCH_OMAP4
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select ARM_CPU_SUSPEND if PM
         select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
+        select OMAP_INTERCONNECT
 
 config SOC_OMAP5
         bool "TI OMAP5"
@@ -71,6 +76,8 @@ config SOC_OMAP5
         select ARM_GIC
         select HAVE_SMP
         select ARM_CPU_SUSPEND if PM
+        select SOC_HAS_REALTIME_COUNTER
+        select ARM_ARCH_TIMER
 
 comment "OMAP Core Type"
         depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b807deb0f521..fe40d9e488c9 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -181,11 +181,6 @@ obj-$(CONFIG_ARCH_OMAP4)		+= omap_hwmod_44xx_data.o
 obj-$(CONFIG_OMAP3_EMU)                 += emu.o
 obj-$(CONFIG_HW_PERF_EVENTS)            += pmu.o
 
-# L3 interconnect
-obj-$(CONFIG_ARCH_OMAP3)                += omap_l3_smx.o
-obj-$(CONFIG_ARCH_OMAP4)                += omap_l3_noc.o
-obj-$(CONFIG_SOC_OMAP5)                 += omap_l3_noc.o
-
 obj-$(CONFIG_OMAP_MBOX_FWK)             += mailbox_mach.o
 mailbox_mach-objs                       := mailbox.o
 
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 6fe90796d462..a88809a59ea9 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -545,6 +545,14 @@ static struct twl6040_platform_data twl6040_data = {
         .audpwron_gpio  = 127,
 };
 
+static struct i2c_board_info __initdata sdp4430_i2c_1_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl6040", 0x4b),
+                .irq = 119 + OMAP44XX_IRQ_GIC_START,
+                .platform_data = &twl6040_data,
+        },
+};
+
 static struct twl4030_platform_data sdp4430_twldata = {
         /* Regulators */
         .vusim          = &sdp4430_vusim,
@@ -578,8 +586,8 @@ static int __init omap4_i2c_init(void)
                         TWL_COMMON_REGULATOR_CLK32KG |
                         TWL_COMMON_REGULATOR_V1V8 |
                         TWL_COMMON_REGULATOR_V2V1);
-        omap4_pmic_init("twl6030", &sdp4430_twldata,
-                        &twl6040_data, 119 + OMAP44XX_IRQ_GIC_START);
+        omap4_pmic_init("twl6030", &sdp4430_twldata, sdp4430_i2c_1_boardinfo,
+                        ARRAY_SIZE(sdp4430_i2c_1_boardinfo));
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
                                 ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 3fe5f0f69c73..c64e565bdef5 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -32,6 +32,7 @@
 #include <linux/spi/ads7846.h>
 #include <linux/i2c/twl.h>
 #include <linux/usb/otg.h>
+#include <linux/usb/nop-usb-xceiv.h>
 #include <linux/smsc911x.h>
 
 #include <linux/wl12xx.h>
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 556e777b9c40..2b012f9d6925 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -264,6 +264,14 @@ static struct twl6040_platform_data twl6040_data = {
         .audpwron_gpio  = 127,
 };
 
+static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl6040", 0x4b),
+                .irq = 119 + OMAP44XX_IRQ_GIC_START,
+                .platform_data = &twl6040_data,
+        },
+};
+
 /* Panda board uses the common PMIC configuration */
 static struct twl4030_platform_data omap4_panda_twldata;
 
@@ -291,8 +299,8 @@ static int __init omap4_panda_i2c_init(void)
                         TWL_COMMON_REGULATOR_CLK32KG |
                         TWL_COMMON_REGULATOR_V1V8 |
                         TWL_COMMON_REGULATOR_V2V1);
-        omap4_pmic_init("twl6030", &omap4_panda_twldata,
-                        &twl6040_data, 119 + OMAP44XX_IRQ_GIC_START);
+        omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo,
+                        ARRAY_SIZE(panda_i2c_1_boardinfo));
         omap_register_i2c_bus(2, 400, NULL, 0);
         /*
          * Bus 3 is attached to the DVI port where devices like the pico DLP
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 3945c5017085..ed85fb898c7f 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -33,6 +33,7 @@
 #include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
+#include <plat/omap-pm.h>
 #include "gpmc-smc91x.h"
 
 #include "board-rx51.h"
@@ -46,6 +47,10 @@
 #include <../drivers/staging/iio/light/tsl2563.h>
 #include <linux/lis3lv02d.h>
 
+#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
+#include <media/ir-rx51.h>
+#endif
+
 #include "mux.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
@@ -1217,6 +1222,30 @@ static void __init rx51_init_tsc2005(void)
                                 gpio_to_irq(RX51_TSC2005_IRQ_GPIO);
 }
 
+#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
+static struct lirc_rx51_platform_data rx51_lirc_data = {
+        .set_max_mpu_wakeup_lat = omap_pm_set_max_mpu_wakeup_lat,
+        .pwm_timer = 9, /* Use GPT 9 for CIR */
+};
+
+static struct platform_device rx51_lirc_device = {
+        .name           = "lirc_rx51",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &rx51_lirc_data,
+        },
+};
+
+static void __init rx51_init_lirc(void)
+{
+        platform_device_register(&rx51_lirc_device);
+}
+#else
+static void __init rx51_init_lirc(void)
+{
+}
+#endif
+
 void __init rx51_peripherals_init(void)
 {
         rx51_i2c_init();
@@ -1227,6 +1256,7 @@ void __init rx51_peripherals_init(void)
         rx51_init_wl1251();
         rx51_init_tsc2005();
         rx51_init_si4713();
+        rx51_init_lirc();
         spi_register_board_info(rx51_peripherals_spi_board_info,
                                 ARRAY_SIZE(rx51_peripherals_spi_board_info));
 
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 5a3afd2b737d..7012068ccbf6 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -76,14 +76,14 @@ struct omap_dss_hwmod_data {
         const int id;
 };
 
-static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
         { "dss_core", "omapdss_dss", -1 },
         { "dss_dispc", "omapdss_dispc", -1 },
         { "dss_rfbi", "omapdss_rfbi", -1 },
         { "dss_venc", "omapdss_venc", -1 },
 };
 
-static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
         { "dss_core", "omapdss_dss", -1 },
         { "dss_dispc", "omapdss_dispc", -1 },
         { "dss_rfbi", "omapdss_rfbi", -1 },
@@ -91,7 +91,7 @@ static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
         { "dss_dsi1", "omapdss_dsi", 0 },
 };
 
-static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
         { "dss_core", "omapdss_dss", -1 },
         { "dss_dispc", "omapdss_dispc", -1 },
         { "dss_rfbi", "omapdss_rfbi", -1 },
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index e7b246da02d0..d1058f16fb40 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -123,6 +123,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                 break;
         default:
                 WARN(1, "Invalid gpio bank_type\n");
+                kfree(pdata->regs);
                 kfree(pdata);
                 return -EINVAL;
         }
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index b3275babf192..5d3b4f4f81ae 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -230,13 +230,7 @@ static inline void omap4_irq_save_context(void)
         /* Save AuxBoot* registers */
         val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
         __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-        __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
-
-        /* Save SyncReq generation logic */
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-        __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
         __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
 
         /* Save SyncReq generation logic */
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index ae0acaf506ed..8d7a93525bc6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -6110,6 +6110,12 @@ static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
                 .pa_end         = 0x4a0ab7ff,
                 .flags          = ADDR_TYPE_RT
         },
+        {
+                /* XXX: Remove this once control module driver is in place */
+                .pa_start       = 0x4a00233c,
+                .pa_end         = 0x4a00233f,
+                .flags          = ADDR_TYPE_RT
+        },
         { }
 };
 
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
deleted file mode 100644
index f447e02102bb..000000000000
--- a/arch/arm/mach-omap2/omap_l3_noc.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * OMAP4XXX L3 Interconnect error handling driver
- *
- * Copyright (C) 2011 Texas Corporation
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *      Sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- * USA
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-
-#include "soc.h"
-#include "omap_l3_noc.h"
-
-/*
- * Interrupt Handler for L3 error detection.
- *      1) Identify the L3 clockdomain partition to which the error belongs to.
- *      2) Identify the slave where the error information is logged
- *      3) Print the logged information.
- *      4) Add dump stack to provide kernel trace.
- *
- * Two Types of errors :
- *      1) Custom errors in L3 :
- *              Target like DMM/FW/EMIF generates SRESP=ERR error
- *      2) Standard L3 error:
- *              - Unsupported CMD.
- *                      L3 tries to access target while it is idle
- *              - OCP disconnect.
- *              - Address hole error:
- *                      If DSS/ISS/FDIF/USBHOSTFS access a target where they
- *                      do not have connectivity, the error is logged in
- *                      their default target which is DMM2.
- *
- *      On High Secure devices, firewall errors are possible and those
- *      can be trapped as well. But the trapping is implemented as part
- *      secure software and hence need not be implemented here.
- */
-static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
-{
-
-        struct omap4_l3 *l3 = _l3;
-        int inttype, i, k;
-        int err_src = 0;
-        u32 std_err_main, err_reg, clear, masterid;
-        void __iomem *base, *l3_targ_base;
-        char *target_name, *master_name = "UN IDENTIFIED";
-
-        /* Get the Type of interrupt */
-        inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
-
-        for (i = 0; i < L3_MODULES; i++) {
-                /*
-                 * Read the regerr register of the clock domain
-                 * to determine the source
-                 */
-                base = l3->l3_base[i];
-                err_reg = __raw_readl(base + l3_flagmux[i] +
-                                        + L3_FLAGMUX_REGERR0 + (inttype << 3));
-
-                /* Get the corresponding error and analyse */
-                if (err_reg) {
-                        /* Identify the source from control status register */
-                        err_src = __ffs(err_reg);
-
-                        /* Read the stderrlog_main_source from clk domain */
-                        l3_targ_base = base + *(l3_targ[i] + err_src);
-                        std_err_main =  __raw_readl(l3_targ_base +
-                                        L3_TARG_STDERRLOG_MAIN);
-                        masterid = __raw_readl(l3_targ_base +
-                                        L3_TARG_STDERRLOG_MSTADDR);
-
-                        switch (std_err_main & CUSTOM_ERROR) {
-                        case STANDARD_ERROR:
-                                target_name =
-                                        l3_targ_inst_name[i][err_src];
-                                WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
-                                        target_name,
-                                        __raw_readl(l3_targ_base +
-                                                L3_TARG_STDERRLOG_SLVOFSLSB));
-                                /* clear the std error log*/
-                                clear = std_err_main | CLEAR_STDERR_LOG;
-                                writel(clear, l3_targ_base +
-                                        L3_TARG_STDERRLOG_MAIN);
-                                break;
-
-                        case CUSTOM_ERROR:
-                                target_name =
-                                        l3_targ_inst_name[i][err_src];
-                                for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
-                                        if (masterid == l3_masters[k].id)
-                                                master_name =
-                                                        l3_masters[k].name;
-                                }
-                                WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
-                                        master_name, target_name);
-                                /* clear the std error log*/
-                                clear = std_err_main | CLEAR_STDERR_LOG;
-                                writel(clear, l3_targ_base +
-                                        L3_TARG_STDERRLOG_MAIN);
-                                break;
-
-                        default:
-                                /* Nothing to be handled here as of now */
-                                break;
-                        }
-                /* Error found so break the for loop */
-                break;
-                }
-        }
-        return IRQ_HANDLED;
-}
-
-static int __devinit omap4_l3_probe(struct platform_device *pdev)
-{
-        static struct omap4_l3 *l3;
-        struct resource *res;
-        int ret;
-
-        l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
-        if (!l3)
-                return -ENOMEM;
-
-        platform_set_drvdata(pdev, l3);
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                dev_err(&pdev->dev, "couldn't find resource 0\n");
-                ret = -ENODEV;
-                goto err0;
-        }
-
-        l3->l3_base[0] = ioremap(res->start, resource_size(res));
-        if (!l3->l3_base[0]) {
-                dev_err(&pdev->dev, "ioremap failed\n");
-                ret = -ENOMEM;
-                goto err0;
-        }
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-        if (!res) {
-                dev_err(&pdev->dev, "couldn't find resource 1\n");
-                ret = -ENODEV;
-                goto err1;
-        }
-
-        l3->l3_base[1] = ioremap(res->start, resource_size(res));
-        if (!l3->l3_base[1]) {
-                dev_err(&pdev->dev, "ioremap failed\n");
-                ret = -ENOMEM;
-                goto err1;
-        }
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
-        if (!res) {
-                dev_err(&pdev->dev, "couldn't find resource 2\n");
-                ret = -ENODEV;
-                goto err2;
-        }
-
-        l3->l3_base[2] = ioremap(res->start, resource_size(res));
-        if (!l3->l3_base[2]) {
-                dev_err(&pdev->dev, "ioremap failed\n");
-                ret = -ENOMEM;
-                goto err2;
-        }
-
-        /*
-         * Setup interrupt Handlers
-         */
-        l3->debug_irq = platform_get_irq(pdev, 0);
-        ret = request_irq(l3->debug_irq,
-                        l3_interrupt_handler,
-                        IRQF_DISABLED, "l3-dbg-irq", l3);
-        if (ret) {
-                pr_crit("L3: request_irq failed to register for 0x%x\n",
-                                                9 + OMAP44XX_IRQ_GIC_START);
-                goto err3;
-        }
-
-        l3->app_irq = platform_get_irq(pdev, 1);
-        ret = request_irq(l3->app_irq,
-                        l3_interrupt_handler,
-                        IRQF_DISABLED, "l3-app-irq", l3);
-        if (ret) {
-                pr_crit("L3: request_irq failed to register for 0x%x\n",
-                                                10 + OMAP44XX_IRQ_GIC_START);
-                goto err4;
-        }
-
-        return 0;
-
-err4:
-        free_irq(l3->debug_irq, l3);
-err3:
-        iounmap(l3->l3_base[2]);
-err2:
-        iounmap(l3->l3_base[1]);
-err1:
-        iounmap(l3->l3_base[0]);
-err0:
-        kfree(l3);
-        return ret;
-}
-
-static int __devexit omap4_l3_remove(struct platform_device *pdev)
-{
-        struct omap4_l3 *l3 = platform_get_drvdata(pdev);
-
-        free_irq(l3->app_irq, l3);
-        free_irq(l3->debug_irq, l3);
-        iounmap(l3->l3_base[0]);
-        iounmap(l3->l3_base[1]);
-        iounmap(l3->l3_base[2]);
-        kfree(l3);
-
-        return 0;
-}
-
-#if defined(CONFIG_OF)
-static const struct of_device_id l3_noc_match[] = {
-        {.compatible = "ti,omap4-l3-noc", },
-        {},
-};
-MODULE_DEVICE_TABLE(of, l3_noc_match);
-#else
-#define l3_noc_match NULL
-#endif
-
-static struct platform_driver omap4_l3_driver = {
-        .probe          = omap4_l3_probe,
-        .remove         = __devexit_p(omap4_l3_remove),
-        .driver         = {
-                .name           = "omap_l3_noc",
-                .owner          = THIS_MODULE,
-                .of_match_table = l3_noc_match,
-        },
-};
-
-static int __init omap4_l3_init(void)
-{
-        return platform_driver_register(&omap4_l3_driver);
-}
-postcore_initcall_sync(omap4_l3_init);
-
-static void __exit omap4_l3_exit(void)
-{
-        platform_driver_unregister(&omap4_l3_driver);
-}
-module_exit(omap4_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
deleted file mode 100644
index a6ce34dc4814..000000000000
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * OMAP4XXX L3 Interconnect  error handling driver header
- *
- * Copyright (C) 2011 Texas Corporation
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *      sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- * USA
- */
-#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
-#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
-
-#define L3_MODULES                      3
-#define CLEAR_STDERR_LOG                (1 << 31)
-#define CUSTOM_ERROR                    0x2
-#define STANDARD_ERROR                  0x0
-#define INBAND_ERROR                    0x0
-#define L3_APPLICATION_ERROR            0x0
-#define L3_DEBUG_ERROR                  0x1
-
-/* L3 TARG register offsets */
-#define L3_TARG_STDERRLOG_MAIN          0x48
-#define L3_TARG_STDERRLOG_SLVOFSLSB     0x5c
-#define L3_TARG_STDERRLOG_MSTADDR       0x68
-#define L3_FLAGMUX_REGERR0              0xc
-
-#define NUM_OF_L3_MASTERS       (sizeof(l3_masters)/sizeof(l3_masters[0]))
-
-static u32 l3_flagmux[L3_MODULES] = {
-        0x500,
-        0x1000,
-        0X0200
-};
-
-/* L3 Target standard Error register offsets */
-static u32 l3_targ_inst_clk1[] = {
-        0x100, /* DMM1 */
-        0x200, /* DMM2 */
-        0x300, /* ABE */
-        0x400, /* L4CFG */
-        0x600,  /* CLK2 PWR DISC */
-        0x0,    /* Host CLK1 */
-        0x900   /* L4 Wakeup */
-};
-
-static u32 l3_targ_inst_clk2[] = {
-        0x500, /* CORTEX M3 */
-        0x300, /* DSS */
-        0x100, /* GPMC */
-        0x400, /* ISS */
-        0x700, /* IVAHD */
-        0xD00, /* missing in TRM  corresponds to AES1*/
-        0x900, /* L4 PER0*/
-        0x200, /* OCMRAM */
-        0x100, /* missing in TRM corresponds to GPMC sERROR*/
-        0x600, /* SGX */
-        0x800, /* SL2 */
-        0x1600, /* C2C */
-        0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
-        0xF00, /* missing in TRM corrsponds to SHA1*/
-        0xE00, /* missing in TRM corresponds to AES2*/
-        0xC00, /* L4 PER3 */
-        0xA00, /* L4 PER1*/
-        0xB00, /* L4 PER2*/
-        0x0, /* HOST CLK2 */
-        0x1800, /* CAL */
-        0x1700 /* LLI */
-};
-
-static u32 l3_targ_inst_clk3[] = {
-        0x0100  /* EMUSS */,
-        0x0300, /* DEBUGSS_CT_TBR */
-        0x0 /* HOST CLK3 */
-};
-
-static struct l3_masters_data {
-        u32 id;
-        char name[10];
-} l3_masters[] = {
-        { 0x0 , "MPU"},
-        { 0x10, "CS_ADP"},
-        { 0x14, "xxx"},
-        { 0x20, "DSP"},
-        { 0x30, "IVAHD"},
-        { 0x40, "ISS"},
-        { 0x44, "DucatiM3"},
-        { 0x48, "FaceDetect"},
-        { 0x50, "SDMA_Rd"},
-        { 0x54, "SDMA_Wr"},
-        { 0x58, "xxx"},
-        { 0x5C, "xxx"},
-        { 0x60, "SGX"},
-        { 0x70, "DSS"},
-        { 0x80, "C2C"},
-        { 0x88, "xxx"},
-        { 0x8C, "xxx"},
-        { 0x90, "HSI"},
-        { 0xA0, "MMC1"},
-        { 0xA4, "MMC2"},
-        { 0xA8, "MMC6"},
-        { 0xB0, "UNIPRO1"},
-        { 0xC0, "USBHOSTHS"},
-        { 0xC4, "USBOTGHS"},
-        { 0xC8, "USBHOSTFS"}
-};
-
-static char *l3_targ_inst_name[L3_MODULES][21] = {
-        {
-                "DMM1",
-                "DMM2",
-                "ABE",
-                "L4CFG",
-                "CLK2 PWR DISC",
-                "HOST CLK1",
-                "L4 WAKEUP"
-        },
-        {
-                "CORTEX M3" ,
-                "DSS ",
-                "GPMC ",
-                "ISS ",
-                "IVAHD ",
-                "AES1",
-                "L4 PER0",
-                "OCMRAM ",
-                "GPMC sERROR",
-                "SGX ",
-                "SL2 ",
-                "C2C ",
-                "PWR DISC CLK1",
-                "SHA1",
-                "AES2",
-                "L4 PER3",
-                "L4 PER1",
-                "L4 PER2",
-                "HOST CLK2",
-                "CAL",
-                "LLI"
-        },
-        {
-                "EMUSS",
-                "DEBUG SOURCE",
-                "HOST CLK3"
-        },
-};
-
-static u32 *l3_targ[L3_MODULES] = {
-        l3_targ_inst_clk1,
-        l3_targ_inst_clk2,
-        l3_targ_inst_clk3,
-};
-
-struct omap4_l3 {
-        struct device *dev;
-        struct clk *ick;
-
-        /* memory base */
-        void __iomem *l3_base[L3_MODULES];
-
-        int debug_irq;
-        int app_irq;
-};
-#endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
deleted file mode 100644
index acc216491b8a..000000000000
--- a/arch/arm/mach-omap2/omap_l3_smx.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * OMAP3XXX L3 Interconnect Driver
- *
- * Copyright (C) 2011 Texas Corporation
- *      Felipe Balbi <balbi@ti.com>
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *      Sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- * USA
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include "omap_l3_smx.h"
-
-static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
-{
-        return __raw_readll(base + reg);
-}
-
-static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value)
-{
-        __raw_writell(value, base + reg);
-}
-
-static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error)
-{
-        return (error & 0x0f000000) >> L3_ERROR_LOG_CODE;
-}
-
-static inline u32 omap3_l3_decode_addr(u64 error_addr)
-{
-        return error_addr & 0xffffffff;
-}
-
-static inline unsigned omap3_l3_decode_cmd(u64 error)
-{
-        return (error & 0x07) >> L3_ERROR_LOG_CMD;
-}
-
-static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error)
-{
-        return (error & 0xff00) >> L3_ERROR_LOG_INITID;
-}
-
-static inline unsigned omap3_l3_decode_req_info(u64 error)
-{
-        return (error >> 32) & 0xffff;
-}
-
-static char *omap3_l3_code_string(u8 code)
-{
-        switch (code) {
-        case OMAP_L3_CODE_NOERROR:
-                return "No Error";
-        case OMAP_L3_CODE_UNSUP_CMD:
-                return "Unsupported Command";
-        case OMAP_L3_CODE_ADDR_HOLE:
-                return "Address Hole";
-        case OMAP_L3_CODE_PROTECT_VIOLATION:
-                return "Protection Violation";
-        case OMAP_L3_CODE_IN_BAND_ERR:
-                return "In-band Error";
-        case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT:
-                return "Request Timeout Not Accepted";
-        case OMAP_L3_CODE_REQ_TOUT_NO_RESP:
-                return "Request Timeout, no response";
-        default:
-                return "UNKNOWN error";
-        }
-}
-
-static char *omap3_l3_initiator_string(u8 initid)
-{
-        switch (initid) {
-        case OMAP_L3_LCD:
-                return "LCD";
-        case OMAP_L3_SAD2D:
-                return "SAD2D";
-        case OMAP_L3_IA_MPU_SS_1:
-        case OMAP_L3_IA_MPU_SS_2:
-        case OMAP_L3_IA_MPU_SS_3:
-        case OMAP_L3_IA_MPU_SS_4:
-        case OMAP_L3_IA_MPU_SS_5:
-                return "MPU";
-        case OMAP_L3_IA_IVA_SS_1:
-        case OMAP_L3_IA_IVA_SS_2:
-        case OMAP_L3_IA_IVA_SS_3:
-                return "IVA_SS";
-        case OMAP_L3_IA_IVA_SS_DMA_1:
-        case OMAP_L3_IA_IVA_SS_DMA_2:
-        case OMAP_L3_IA_IVA_SS_DMA_3:
-        case OMAP_L3_IA_IVA_SS_DMA_4:
-        case OMAP_L3_IA_IVA_SS_DMA_5:
-        case OMAP_L3_IA_IVA_SS_DMA_6:
-                return "IVA_SS_DMA";
-        case OMAP_L3_IA_SGX:
-                return "SGX";
-        case OMAP_L3_IA_CAM_1:
-        case OMAP_L3_IA_CAM_2:
-        case OMAP_L3_IA_CAM_3:
-                return "CAM";
-        case OMAP_L3_IA_DAP:
-                return "DAP";
-        case OMAP_L3_SDMA_WR_1:
-        case OMAP_L3_SDMA_WR_2:
-                return "SDMA_WR";
-        case OMAP_L3_SDMA_RD_1:
-        case OMAP_L3_SDMA_RD_2:
-        case OMAP_L3_SDMA_RD_3:
-        case OMAP_L3_SDMA_RD_4:
-                return "SDMA_RD";
-        case OMAP_L3_USBOTG:
-                return "USB_OTG";
-        case OMAP_L3_USBHOST:
-                return "USB_HOST";
-        default:
-                return "UNKNOWN Initiator";
-        }
-}
-
-/*
- * omap3_l3_block_irq - handles a register block's irq
- * @l3: struct omap3_l3 *
- * @base: register block base address
- * @error: L3_ERROR_LOG register of our block
- *
- * Called in hard-irq context. Caller should take care of locking
- *
- * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error
- * Analysis Sequence, we are following that sequence here, please
- * refer to that Figure for more information on the subject.
- */
-static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
-                                        u64 error, int error_addr)
-{
-        u8 code = omap3_l3_decode_error_code(error);
-        u8 initid = omap3_l3_decode_initid(error);
-        u8 multi = error & L3_ERROR_LOG_MULTI;
-        u32 address = omap3_l3_decode_addr(error_addr);
-
-        pr_err("%s seen by %s %s at address %x\n",
-                        omap3_l3_code_string(code),
-                        omap3_l3_initiator_string(initid),
-                        multi ? "Multiple Errors" : "", address);
-        WARN_ON(1);
-
-        return IRQ_HANDLED;
-}
-
-static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
-{
-        struct omap3_l3 *l3 = _l3;
-        u64 status, clear;
-        u64 error;
-        u64 error_addr;
-        u64 err_source = 0;
-        void __iomem *base;
-        int int_type;
-        irqreturn_t ret = IRQ_NONE;
-
-        int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
-        if (!int_type) {
-                status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
-                /*
-                 * if we have a timeout error, there's nothing we can
-                 * do besides rebooting the board. So let's BUG on any
-                 * of such errors and handle the others. timeout error
-                 * is severe and not expected to occur.
-                 */
-                BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
-        } else {
-                status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
-                /* No timeout error for debug sources */
-        }
-
-        /* identify the error source */
-        err_source = __ffs(status);
-
-        base = l3->rt + omap3_l3_bases[int_type][err_source];
-        error = omap3_l3_readll(base, L3_ERROR_LOG);
-        if (error) {
-                error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
-                ret |= omap3_l3_block_irq(l3, error, error_addr);
-        }
-
-        /* Clear the status register */
-        clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) |
-                L3_AGENT_STATUS_CLEAR_TA;
-        omap3_l3_writell(base, L3_AGENT_STATUS, clear);
-
-        /* clear the error log register */
-        omap3_l3_writell(base, L3_ERROR_LOG, error);
-
-        return ret;
-}
-
-static int __init omap3_l3_probe(struct platform_device *pdev)
-{
-        struct omap3_l3 *l3;
-        struct resource *res;
-        int ret;
-
-        l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
-        if (!l3)
-                return -ENOMEM;
-
-        platform_set_drvdata(pdev, l3);
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                dev_err(&pdev->dev, "couldn't find resource\n");
-                ret = -ENODEV;
-                goto err0;
-        }
-        l3->rt = ioremap(res->start, resource_size(res));
-        if (!l3->rt) {
-                dev_err(&pdev->dev, "ioremap failed\n");
-                ret = -ENOMEM;
-                goto err0;
-        }
-
-        l3->debug_irq = platform_get_irq(pdev, 0);
-        ret = request_irq(l3->debug_irq, omap3_l3_app_irq,
-                IRQF_DISABLED | IRQF_TRIGGER_RISING,
-                "l3-debug-irq", l3);
-        if (ret) {
-                dev_err(&pdev->dev, "couldn't request debug irq\n");
-                goto err1;
-        }
-
-        l3->app_irq = platform_get_irq(pdev, 1);
-        ret = request_irq(l3->app_irq, omap3_l3_app_irq,
-                IRQF_DISABLED | IRQF_TRIGGER_RISING,
-                "l3-app-irq", l3);
-        if (ret) {
-                dev_err(&pdev->dev, "couldn't request app irq\n");
-                goto err2;
-        }
-
-        return 0;
-
-err2:
-        free_irq(l3->debug_irq, l3);
-err1:
-        iounmap(l3->rt);
-err0:
-        kfree(l3);
-        return ret;
-}
-
-static int __exit omap3_l3_remove(struct platform_device *pdev)
-{
-        struct omap3_l3         *l3 = platform_get_drvdata(pdev);
-
-        free_irq(l3->app_irq, l3);
-        free_irq(l3->debug_irq, l3);
-        iounmap(l3->rt);
-        kfree(l3);
-
-        return 0;
-}
-
-static struct platform_driver omap3_l3_driver = {
-        .remove         = __exit_p(omap3_l3_remove),
-        .driver         = {
-        .name   = "omap_l3_smx",
-        },
-};
-
-static int __init omap3_l3_init(void)
-{
-        return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
-}
-postcore_initcall_sync(omap3_l3_init);
-
-static void __exit omap3_l3_exit(void)
-{
-        platform_driver_unregister(&omap3_l3_driver);
-}
-module_exit(omap3_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
deleted file mode 100644
index 4f3cebca4179..000000000000
--- a/arch/arm/mach-omap2/omap_l3_smx.h
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * OMAP3XXX L3 Interconnect Driver header
- *
- * Copyright (C) 2011 Texas Corporation
- *      Felipe Balbi <balbi@ti.com>
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *      sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- * USA
- */
-#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
-#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
-
-/* Register definitions. All 64-bit wide */
-#define L3_COMPONENT                    0x000
-#define L3_CORE                         0x018
-#define L3_AGENT_CONTROL                0x020
-#define L3_AGENT_STATUS                 0x028
-#define L3_ERROR_LOG                    0x058
-
-#define L3_ERROR_LOG_MULTI              (1 << 31)
-#define L3_ERROR_LOG_SECONDARY          (1 << 30)
-
-#define L3_ERROR_LOG_ADDR               0x060
-
-/* Register definitions for Sideband Interconnect */
-#define L3_SI_CONTROL                   0x020
-#define L3_SI_FLAG_STATUS_0             0x510
-
-static const u64 shift = 1;
-
-#define L3_STATUS_0_MPUIA_BRST          (shift << 0)
-#define L3_STATUS_0_MPUIA_RSP           (shift << 1)
-#define L3_STATUS_0_MPUIA_INBAND        (shift << 2)
-#define L3_STATUS_0_IVAIA_BRST          (shift << 6)
-#define L3_STATUS_0_IVAIA_RSP           (shift << 7)
-#define L3_STATUS_0_IVAIA_INBAND        (shift << 8)
-#define L3_STATUS_0_SGXIA_BRST          (shift << 9)
-#define L3_STATUS_0_SGXIA_RSP           (shift << 10)
-#define L3_STATUS_0_SGXIA_MERROR        (shift << 11)
-#define L3_STATUS_0_CAMIA_BRST          (shift << 12)
-#define L3_STATUS_0_CAMIA_RSP           (shift << 13)
-#define L3_STATUS_0_CAMIA_INBAND        (shift << 14)
-#define L3_STATUS_0_DISPIA_BRST         (shift << 15)
-#define L3_STATUS_0_DISPIA_RSP          (shift << 16)
-#define L3_STATUS_0_DMARDIA_BRST        (shift << 18)
-#define L3_STATUS_0_DMARDIA_RSP         (shift << 19)
-#define L3_STATUS_0_DMAWRIA_BRST        (shift << 21)
-#define L3_STATUS_0_DMAWRIA_RSP         (shift << 22)
-#define L3_STATUS_0_USBOTGIA_BRST       (shift << 24)
-#define L3_STATUS_0_USBOTGIA_RSP        (shift << 25)
-#define L3_STATUS_0_USBOTGIA_INBAND     (shift << 26)
-#define L3_STATUS_0_USBHOSTIA_BRST      (shift << 27)
-#define L3_STATUS_0_USBHOSTIA_INBAND    (shift << 28)
-#define L3_STATUS_0_SMSTA_REQ           (shift << 48)
-#define L3_STATUS_0_GPMCTA_REQ          (shift << 49)
-#define L3_STATUS_0_OCMRAMTA_REQ        (shift << 50)
-#define L3_STATUS_0_OCMROMTA_REQ        (shift << 51)
-#define L3_STATUS_0_IVATA_REQ           (shift << 54)
-#define L3_STATUS_0_SGXTA_REQ           (shift << 55)
-#define L3_STATUS_0_SGXTA_SERROR        (shift << 56)
-#define L3_STATUS_0_GPMCTA_SERROR       (shift << 57)
-#define L3_STATUS_0_L4CORETA_REQ        (shift << 58)
-#define L3_STATUS_0_L4PERTA_REQ         (shift << 59)
-#define L3_STATUS_0_L4EMUTA_REQ         (shift << 60)
-#define L3_STATUS_0_MAD2DTA_REQ         (shift << 61)
-
-#define L3_STATUS_0_TIMEOUT_MASK        (L3_STATUS_0_MPUIA_BRST         \
-                                        | L3_STATUS_0_MPUIA_RSP         \
-                                        | L3_STATUS_0_IVAIA_BRST        \
-                                        | L3_STATUS_0_IVAIA_RSP         \
-                                        | L3_STATUS_0_SGXIA_BRST        \
-                                        | L3_STATUS_0_SGXIA_RSP         \
-                                        | L3_STATUS_0_CAMIA_BRST        \
-                                        | L3_STATUS_0_CAMIA_RSP         \
-                                        | L3_STATUS_0_DISPIA_BRST       \
-                                        | L3_STATUS_0_DISPIA_RSP        \
-                                        | L3_STATUS_0_DMARDIA_BRST      \
-                                        | L3_STATUS_0_DMARDIA_RSP       \
-                                        | L3_STATUS_0_DMAWRIA_BRST      \
-                                        | L3_STATUS_0_DMAWRIA_RSP       \
-                                        | L3_STATUS_0_USBOTGIA_BRST     \
-                                        | L3_STATUS_0_USBOTGIA_RSP      \
-                                        | L3_STATUS_0_USBHOSTIA_BRST    \
-                                        | L3_STATUS_0_SMSTA_REQ         \
-                                        | L3_STATUS_0_GPMCTA_REQ        \
-                                        | L3_STATUS_0_OCMRAMTA_REQ      \
-                                        | L3_STATUS_0_OCMROMTA_REQ      \
-                                        | L3_STATUS_0_IVATA_REQ         \
-                                        | L3_STATUS_0_SGXTA_REQ         \
-                                        | L3_STATUS_0_L4CORETA_REQ      \
-                                        | L3_STATUS_0_L4PERTA_REQ       \
-                                        | L3_STATUS_0_L4EMUTA_REQ       \
-                                        | L3_STATUS_0_MAD2DTA_REQ)
-
-#define L3_SI_FLAG_STATUS_1             0x530
-
-#define L3_STATUS_1_MPU_DATAIA          (1 << 0)
-#define L3_STATUS_1_DAPIA0              (1 << 3)
-#define L3_STATUS_1_DAPIA1              (1 << 4)
-#define L3_STATUS_1_IVAIA               (1 << 6)
-
-#define L3_PM_ERROR_LOG                 0x020
-#define L3_PM_CONTROL                   0x028
-#define L3_PM_ERROR_CLEAR_SINGLE        0x030
-#define L3_PM_ERROR_CLEAR_MULTI         0x038
-#define L3_PM_REQ_INFO_PERMISSION(n)    (0x048 + (0x020 * n))
-#define L3_PM_READ_PERMISSION(n)        (0x050 + (0x020 * n))
-#define L3_PM_WRITE_PERMISSION(n)       (0x058 + (0x020 * n))
-#define L3_PM_ADDR_MATCH(n)             (0x060 + (0x020 * n))
-
-/* L3 error log bit fields. Common for IA and TA */
-#define L3_ERROR_LOG_CODE               24
-#define L3_ERROR_LOG_INITID             8
-#define L3_ERROR_LOG_CMD                0
-
-/* L3 agent status bit fields. */
-#define L3_AGENT_STATUS_CLEAR_IA        0x10000000
-#define L3_AGENT_STATUS_CLEAR_TA        0x01000000
-
-#define OMAP34xx_IRQ_L3_APP             10
-#define L3_APPLICATION_ERROR            0x0
-#define L3_DEBUG_ERROR                  0x1
-
-enum omap3_l3_initiator_id {
-        /* LCD has 1 ID */
-        OMAP_L3_LCD = 29,
-        /* SAD2D has 1 ID */
-        OMAP_L3_SAD2D = 28,
-        /* MPU has 5 IDs */
-        OMAP_L3_IA_MPU_SS_1 = 27,
-        OMAP_L3_IA_MPU_SS_2 = 26,
-        OMAP_L3_IA_MPU_SS_3 = 25,
-        OMAP_L3_IA_MPU_SS_4 = 24,
-        OMAP_L3_IA_MPU_SS_5 = 23,
-        /* IVA2.2 SS has 3 IDs*/
-        OMAP_L3_IA_IVA_SS_1 = 22,
-        OMAP_L3_IA_IVA_SS_2 = 21,
-        OMAP_L3_IA_IVA_SS_3 = 20,
-        /* IVA 2.2 SS DMA has 6 IDS */
-        OMAP_L3_IA_IVA_SS_DMA_1 = 19,
-        OMAP_L3_IA_IVA_SS_DMA_2 = 18,
-        OMAP_L3_IA_IVA_SS_DMA_3 = 17,
-        OMAP_L3_IA_IVA_SS_DMA_4 = 16,
-        OMAP_L3_IA_IVA_SS_DMA_5 = 15,
-        OMAP_L3_IA_IVA_SS_DMA_6 = 14,
-        /* SGX has 1 ID */
-        OMAP_L3_IA_SGX = 13,
-        /* CAM has 3 ID */
-        OMAP_L3_IA_CAM_1 = 12,
-        OMAP_L3_IA_CAM_2 = 11,
-        OMAP_L3_IA_CAM_3 = 10,
-        /* DAP has 1 ID */
-        OMAP_L3_IA_DAP = 9,
-        /* SDMA WR has 2 IDs */
-        OMAP_L3_SDMA_WR_1 = 8,
-        OMAP_L3_SDMA_WR_2 = 7,
-        /* SDMA RD has 4 IDs */
-        OMAP_L3_SDMA_RD_1 = 6,
-        OMAP_L3_SDMA_RD_2 = 5,
-        OMAP_L3_SDMA_RD_3 = 4,
-        OMAP_L3_SDMA_RD_4 = 3,
-        /* HSUSB OTG has 1 ID */
-        OMAP_L3_USBOTG = 2,
-        /* HSUSB HOST has 1 ID */
-        OMAP_L3_USBHOST = 1,
-};
-
-enum omap3_l3_code {
-        OMAP_L3_CODE_NOERROR = 0,
-        OMAP_L3_CODE_UNSUP_CMD = 1,
-        OMAP_L3_CODE_ADDR_HOLE = 2,
-        OMAP_L3_CODE_PROTECT_VIOLATION = 3,
-        OMAP_L3_CODE_IN_BAND_ERR = 4,
-        /* codes 5 and 6 are reserved */
-        OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
-        OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
-        /* codes 9 - 15 are also reserved */
-};
-
-struct omap3_l3 {
-        struct device *dev;
-        struct clk *ick;
-
-        /* memory base*/
-        void __iomem *rt;
-
-        int debug_irq;
-        int app_irq;
-
-        /* true when and inband functional error occurs */
-        unsigned inband:1;
-};
-
-/* offsets for l3 agents in order with the Flag status register */
-static unsigned int omap3_l3_app_bases[] = {
-        /* MPU IA */
-        0x1400,
-        0x1400,
-        0x1400,
-        /* RESERVED */
-        0,
-        0,
-        0,
-        /* IVA 2.2 IA */
-        0x1800,
-        0x1800,
-        0x1800,
-        /* SGX IA */
-        0x1c00,
-        0x1c00,
-        /* RESERVED */
-        0,
-        /* CAMERA IA */
-        0x5800,
-        0x5800,
-        0x5800,
-        /* DISPLAY IA */
-        0x5400,
-        0x5400,
-        /* RESERVED */
-        0,
-        /*SDMA RD IA */
-        0x4c00,
-        0x4c00,
-        /* RESERVED */
-        0,
-        /* SDMA WR IA */
-        0x5000,
-        0x5000,
-        /* RESERVED */
-        0,
-        /* USB OTG IA */
-        0x4400,
-        0x4400,
-        0x4400,
-        /* USB HOST IA */
-        0x4000,
-        0x4000,
-        /* RESERVED */
-        0,
-        0,
-        0,
-        0,
-        /* SAD2D IA */
-        0x3000,
-        0x3000,
-        0x3000,
-        /* RESERVED */
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        /* SMA TA */
-        0x2000,
-        /* GPMC TA */
-        0x2400,
-        /* OCM RAM TA */
-        0x2800,
-        /* OCM ROM TA */
-        0x2C00,
-        /* L4 CORE TA */
-        0x6800,
-        /* L4 PER TA */
-        0x6c00,
-        /* IVA 2.2 TA */
-        0x6000,
-        /* SGX TA */
-        0x6400,
-        /* L4 EMU TA */
-        0x7000,
-        /* GPMC TA */
-        0x2400,
-        /* L4 CORE TA */
-        0x6800,
-        /* L4 PER TA */
-        0x6c00,
-        /* L4 EMU TA */
-        0x7000,
-        /* MAD2D TA */
-        0x3400,
-        /* RESERVED */
-        0,
-        0,
-};
-
-static unsigned int omap3_l3_debug_bases[] = {
-        /* MPU DATA IA */
-        0x1400,
-        /* RESERVED */
-        0,
-        0,
-        /* DAP IA */
-        0x5c00,
-        0x5c00,
-        /* RESERVED */
-        0,
-        /* IVA 2.2 IA */
-        0x1800,
-        /* REST RESERVED */
-};
-
-static u32 *omap3_l3_bases[] = {
-        omap3_l3_app_bases,
-        omap3_l3_debug_bases,
-};
-
-/*
- * REVISIT define __raw_readll/__raw_writell here, but move them to
- * <asm/io.h> at some point
- */
-#define __raw_writell(v, a)     (__chk_io_ptr(a), \
-                                *(volatile u64 __force *)(a) = (v))
-#define __raw_readll(a)         (__chk_io_ptr(a), \
-                                *(volatile u64 __force *)(a))
-
-#endif
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index 593eaea35cec..d992db8ff0b0 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -33,144 +33,6 @@
 #include "soc.h"
 #include "control.h"
 
-/* OMAP control module register for UTMI PHY */
-#define CONTROL_DEV_CONF                0x300
-#define PHY_PD                          0x1
-
-#define USBOTGHS_CONTROL                0x33c
-#define AVALID                          BIT(0)
-#define BVALID                          BIT(1)
-#define VBUSVALID                       BIT(2)
-#define SESSEND                         BIT(3)
-#define IDDIG                           BIT(4)
-
-static struct clk *phyclk, *clk48m, *clk32k;
-static void __iomem *ctrl_base;
-static int usbotghs_control;
-
-int omap4430_phy_init(struct device *dev)
-{
-        ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
-        if (!ctrl_base) {
-                pr_err("control module ioremap failed\n");
-                return -ENOMEM;
-        }
-        /* Power down the phy */
-        __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-
-        if (!dev) {
-                iounmap(ctrl_base);
-                return 0;
-        }
-
-        phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
-        if (IS_ERR(phyclk)) {
-                dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
-                iounmap(ctrl_base);
-                return PTR_ERR(phyclk);
-        }
-
-        clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m");
-        if (IS_ERR(clk48m)) {
-                dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
-                clk_put(phyclk);
-                iounmap(ctrl_base);
-                return PTR_ERR(clk48m);
-        }
-
-        clk32k = clk_get(dev, "usb_phy_cm_clk32k");
-        if (IS_ERR(clk32k)) {
-                dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n");
-                clk_put(phyclk);
-                clk_put(clk48m);
-                iounmap(ctrl_base);
-                return PTR_ERR(clk32k);
-        }
-        return 0;
-}
-
-int omap4430_phy_set_clk(struct device *dev, int on)
-{
-        static int state;
-
-        if (on && !state) {
-                /* Enable the phy clocks */
-                clk_enable(phyclk);
-                clk_enable(clk48m);
-                clk_enable(clk32k);
-                state = 1;
-        } else if (state) {
-                /* Disable the phy clocks */
-                clk_disable(phyclk);
-                clk_disable(clk48m);
-                clk_disable(clk32k);
-                state = 0;
-        }
-        return 0;
-}
-
-int omap4430_phy_power(struct device *dev, int ID, int on)
-{
-        if (on) {
-                if (ID)
-                        /* enable VBUS valid, IDDIG groung */
-                        __raw_writel(AVALID | VBUSVALID, ctrl_base +
-                                                        USBOTGHS_CONTROL);
-                else
-                        /*
-                         * Enable VBUS Valid, AValid and IDDIG
-                         * high impedance
-                         */
-                        __raw_writel(IDDIG | AVALID | VBUSVALID,
-                                                ctrl_base + USBOTGHS_CONTROL);
-        } else {
-                /* Enable session END and IDIG to high impedance. */
-                __raw_writel(SESSEND | IDDIG, ctrl_base +
-                                        USBOTGHS_CONTROL);
-        }
-        return 0;
-}
-
-int omap4430_phy_suspend(struct device *dev, int suspend)
-{
-        if (suspend) {
-                /* Disable the clocks */
-                omap4430_phy_set_clk(dev, 0);
-                /* Power down the phy */
-                __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-
-                /* save the context */
-                usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL);
-        } else {
-                /* Enable the internel phy clcoks */
-                omap4430_phy_set_clk(dev, 1);
-                /* power on the phy */
-                if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) {
-                        __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-                        mdelay(200);
-                }
-
-                /* restore the context */
-                __raw_writel(usbotghs_control, ctrl_base + USBOTGHS_CONTROL);
-        }
-
-        return 0;
-}
-
-int omap4430_phy_exit(struct device *dev)
-{
-        if (ctrl_base)
-                iounmap(ctrl_base);
-        if (phyclk)
-                clk_put(phyclk);
-        if (clk48m)
-                clk_put(clk48m);
-        if (clk32k)
-                clk_put(clk32k);
-
-        return 0;
-}
-
 void am35x_musb_reset(void)
 {
         u32     regval;
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 810aa1a332e1..8847d6eb2313 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -42,6 +42,7 @@
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
 
+#include <asm/arch_timer.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/dmtimer.h>
@@ -72,6 +73,11 @@
 #define OMAP3_SECURE_TIMER      1
 #endif
 
+#define REALTIME_COUNTER_BASE                           0x48243200
+#define INCREMENTER_NUMERATOR_OFFSET                    0x10
+#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
+#define NUMERATOR_DENUMERATOR_MASK                      0xfffff000
+
 /* Clockevent code */
 
 static struct omap_dm_timer clkev;
@@ -349,6 +355,84 @@ static void __init omap2_clocksource_init(int gptimer_id,
                 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 }
 
+#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
+/*
+ * The realtime counter also called master counter, is a free-running
+ * counter, which is related to real time. It produces the count used
+ * by the CPU local timer peripherals in the MPU cluster. The timer counts
+ * at a rate of 6.144 MHz. Because the device operates on different clocks
+ * in different power modes, the master counter shifts operation between
+ * clocks, adjusting the increment per clock in hardware accordingly to
+ * maintain a constant count rate.
+ */
+static void __init realtime_counter_init(void)
+{
+        void __iomem *base;
+        static struct clk *sys_clk;
+        unsigned long rate;
+        unsigned int reg, num, den;
+
+        base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
+        if (!base) {
+                pr_err("%s: ioremap failed\n", __func__);
+                return;
+        }
+        sys_clk = clk_get(NULL, "sys_clkin_ck");
+        if (!sys_clk) {
+                pr_err("%s: failed to get system clock handle\n", __func__);
+                iounmap(base);
+                return;
+        }
+
+        rate = clk_get_rate(sys_clk);
+        /* Numerator/denumerator values refer TRM Realtime Counter section */
+        switch (rate) {
+        case 1200000:
+                num = 64;
+                den = 125;
+                break;
+        case 1300000:
+                num = 768;
+                den = 1625;
+                break;
+        case 19200000:
+                num = 8;
+                den = 25;
+                break;
+        case 2600000:
+                num = 384;
+                den = 1625;
+                break;
+        case 2700000:
+                num = 256;
+                den = 1125;
+                break;
+        case 38400000:
+        default:
+                /* Program it for 38.4 MHz */
+                num = 4;
+                den = 25;
+                break;
+        }
+
+        /* Program numerator and denumerator registers */
+        reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+                        NUMERATOR_DENUMERATOR_MASK;
+        reg |= num;
+        __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
+
+        reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+                        NUMERATOR_DENUMERATOR_MASK;
+        reg |= den;
+        __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+
+        iounmap(base);
+}
+#else
+static inline void __init realtime_counter_init(void)
+{}
+#endif
+
 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,                  \
                                 clksrc_nr, clksrc_src)                  \
 static void __init omap##name##_timer_init(void)                        \
@@ -410,7 +494,18 @@ OMAP_SYS_TIMER(4)
 #endif
 
 #ifdef CONFIG_SOC_OMAP5
-OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
+static void __init omap5_timer_init(void)
+{
+        int err;
+
+        omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+        omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
+        realtime_counter_init();
+
+        err = arch_timer_of_register();
+        if (err)
+                pr_err("%s: arch_timer_register failed %d\n", __func__, err);
+}
 OMAP_SYS_TIMER(5)
 #endif
 
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 99be94e94547..45f77413c21d 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -40,16 +40,6 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = {
         .flags          = I2C_CLIENT_WAKE,
 };
 
-static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
-        {
-                .addr           = 0x48,
-                .flags          = I2C_CLIENT_WAKE,
-        },
-        {
-                I2C_BOARD_INFO("twl6040", 0x4b),
-        },
-};
-
 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 static int twl_set_voltage(void *data, int target_uV)
 {
@@ -79,30 +69,25 @@ void __init omap_pmic_init(int bus, u32 clkrate,
 
 void __init omap4_pmic_init(const char *pmic_type,
                     struct twl4030_platform_data *pmic_data,
-                    struct twl6040_platform_data *twl6040_data, int twl6040_irq)
+                    struct i2c_board_info *devices, int nr_devices)
 {
         /* PMIC part*/
         omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
-        strncpy(omap4_i2c1_board_info[0].type, pmic_type,
-                sizeof(omap4_i2c1_board_info[0].type));
-        omap4_i2c1_board_info[0].irq = 7 + OMAP44XX_IRQ_GIC_START;
-        omap4_i2c1_board_info[0].platform_data = pmic_data;
-
-        /* TWL6040 audio IC part */
-        omap4_i2c1_board_info[1].irq = twl6040_irq;
-        omap4_i2c1_board_info[1].platform_data = twl6040_data;
-
-        omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2);
+        omap_pmic_init(1, 400, pmic_type, 7 + OMAP44XX_IRQ_GIC_START, pmic_data);
 
+        /* Register additional devices on i2c1 bus if needed */
+        if (devices)
+                i2c_register_board_info(1, devices, nr_devices);
 }
 
 void __init omap_pmic_late_init(void)
 {
-        /* Init the OMAP TWL parameters (if PMIC has been registered) */
-        if (pmic_i2c_board_info.irq)
-                omap3_twl_init();
-        if (omap4_i2c1_board_info[0].irq)
-                omap4_twl_init();
+        /* Init the OMAP TWL parameters (if PMIC has been registerd) */
+        if (!pmic_i2c_board_info.irq)
+                return;
+
+        omap3_twl_init();
+        omap4_twl_init();
 }
 
 #if defined(CONFIG_ARCH_OMAP3)
@@ -252,11 +237,6 @@ void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
 
 #if defined(CONFIG_ARCH_OMAP4)
 static struct twl4030_usb_data omap4_usb_pdata = {
-        .phy_init       = omap4430_phy_init,
-        .phy_exit       = omap4430_phy_exit,
-        .phy_power      = omap4430_phy_power,
-        .phy_set_clock  = omap4430_phy_set_clk,
-        .phy_suspend    = omap4430_phy_suspend,
 };
 
 static struct regulator_init_data omap4_vdac_idata = {
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index d109c09ef34b..2256efe90cf1 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -32,6 +32,7 @@
 
 struct twl4030_platform_data;
 struct twl6040_platform_data;
+struct i2c_board_info;
 
 void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
                     struct twl4030_platform_data *pmic_data);
@@ -51,7 +52,7 @@ static inline void omap3_pmic_init(const char *pmic_type,
 
 void omap4_pmic_init(const char *pmic_type,
                     struct twl4030_platform_data *pmic_data,
-                    struct twl6040_platform_data *audio_data, int twl6040_irq);
+                    struct i2c_board_info *devices, int nr_devices);
 
 void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
                            u32 pdata_flags, u32 regulators_flags);
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index ac95daaa4702..3c434498e12e 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -33,10 +33,12 @@
 #ifdef CONFIG_MFD_OMAP_USB_HOST
 
 #define OMAP_USBHS_DEVICE       "usbhs_omap"
+#define OMAP_USBTLL_DEVICE      "usbhs_tll"
 #define USBHS_UHH_HWMODNAME     "usb_host_hs"
 #define USBHS_TLL_HWMODNAME     "usb_tll_hs"
 
 static struct usbhs_omap_platform_data          usbhs_data;
+static struct usbtll_omap_platform_data         usbtll_data;
 static struct ehci_hcd_omap_platform_data       ehci_data;
 static struct ohci_hcd_omap_platform_data       ohci_data;
 
@@ -485,13 +487,14 @@ void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 
 void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
 {
-        struct omap_hwmod       *oh[2];
+        struct omap_hwmod       *uhh_hwm, *tll_hwm;
         struct platform_device  *pdev;
         int                     bus_id = -1;
         int                     i;
 
         for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
                 usbhs_data.port_mode[i] = pdata->port_mode[i];
+                usbtll_data.port_mode[i] = pdata->port_mode[i];
                 ohci_data.port_mode[i] = pdata->port_mode[i];
                 ehci_data.port_mode[i] = pdata->port_mode[i];
                 ehci_data.reset_gpio_port[i] = pdata->reset_gpio_port[i];
@@ -510,25 +513,35 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
                 setup_4430ohci_io_mux(pdata->port_mode);
         }
 
-        oh[0] = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
-        if (!oh[0]) {
+        uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
+        if (!uhh_hwm) {
                 pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
                 return;
         }
 
-        oh[1] = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
-        if (!oh[1]) {
+        tll_hwm = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
+        if (!tll_hwm) {
                 pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
                 return;
         }
 
-        pdev = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
-                                (void *)&usbhs_data, sizeof(usbhs_data),
+        pdev = omap_device_build(OMAP_USBTLL_DEVICE, bus_id, tll_hwm,
+                                &usbtll_data, sizeof(usbtll_data),
                                 omap_uhhtll_latency,
                                 ARRAY_SIZE(omap_uhhtll_latency), false);
         if (IS_ERR(pdev)) {
-                pr_err("Could not build hwmod devices %s,%s\n",
-                        USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME);
+                pr_err("Could not build hwmod device %s\n",
+                       USBHS_TLL_HWMODNAME);
+                return;
+        }
+
+        pdev = omap_device_build(OMAP_USBHS_DEVICE, bus_id, uhh_hwm,
+                                &usbhs_data, sizeof(usbhs_data),
+                                omap_uhhtll_latency,
+                                ARRAY_SIZE(omap_uhhtll_latency), false);
+        if (IS_ERR(pdev)) {
+                pr_err("Could not build hwmod devices %s\n",
+                       USBHS_UHH_HWMODNAME);
                 return;
         }
 }
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 136c64bc9028..51da21cb78f1 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -116,7 +116,4 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
         dev->dma_mask = &musb_dmamask;
         dev->coherent_dma_mask = musb_dmamask;
         put_device(dev);
-
-        if (cpu_is_omap44xx())
-                omap4430_phy_init(dev);
 }
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 3e07f52f2127..b3eb3da01160 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -194,6 +194,13 @@ void __init orion5x_wdt_init(void)
 void __init orion5x_init_early(void)
 {
         orion_time_set_base(TIMER_VIRT_BASE);
+
+        /*
+         * Some Orion5x devices allocate their coherent buffers from atomic
+         * context. Increase size of atomic coherent pool to make sure such
+         * the allocations won't fail.
+         */
+        init_dma_coherent_pool_size(SZ_1M);
 }
 
 int orion5x_tclk;
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 78a6a11d8216..9b1c95310291 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -18,7 +18,6 @@
 #include <linux/ethtool.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index 2f5dc54cd4cd..51ba2b81a10b 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -19,7 +19,6 @@
 #include <linux/i2c.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 399130fac0b6..0a56b9444f1b 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -19,8 +19,8 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/ata_platform.h>
 #include <linux/i2c.h>
+#include <linux/leds.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
@@ -53,12 +53,6 @@
 #define RD88F5182_PCI_SLOT0_IRQ_A_PIN   7
 #define RD88F5182_PCI_SLOT0_IRQ_B_PIN   6
 
-/*
- * GPIO Debug LED
- */
-
-#define RD88F5182_GPIO_DBG_LED          0
-
 /*****************************************************************************
  * 16M NOR Flash on Device bus CS1
  ****************************************************************************/
@@ -83,55 +77,32 @@ static struct platform_device rd88f5182_nor_flash = {
         .resource               = &rd88f5182_nor_flash_resource,
 };
 
-#ifdef CONFIG_LEDS
-
 /*****************************************************************************
- * Use GPIO debug led as CPU active indication
+ * Use GPIO LED as CPU active indication
  ****************************************************************************/
 
-static void rd88f5182_dbgled_event(led_event_t evt)
-{
-        int val;
-
-        if (evt == led_idle_end)
-                val = 1;
-        else if (evt == led_idle_start)
-                val = 0;
-        else
-                return;
-
-        gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
-}
-
-static int __init rd88f5182_dbgled_init(void)
-{
-        int pin;
-
-        if (machine_is_rd88f5182()) {
-                pin = RD88F5182_GPIO_DBG_LED;
+#define RD88F5182_GPIO_LED              0
 
-                if (gpio_request(pin, "DBGLED") == 0) {
-                        if (gpio_direction_output(pin, 0) != 0) {
-                                printk(KERN_ERR "rd88f5182_dbgled_init failed "
-                                                "to set output pin %d\n", pin);
-                                gpio_free(pin);
-                                return 0;
-                        }
-                } else {
-                        printk(KERN_ERR "rd88f5182_dbgled_init failed "
-                                        "to request gpio %d\n", pin);
-                        return 0;
-                }
-
-                leds_event = rd88f5182_dbgled_event;
-        }
-
-        return 0;
-}
+static struct gpio_led rd88f5182_gpio_led_pins[] = {
+        {
+                .name           = "rd88f5182:cpu",
+                .default_trigger = "cpu0",
+                .gpio           = RD88F5182_GPIO_LED,
+        },
+};
 
-__initcall(rd88f5182_dbgled_init);
+static struct gpio_led_platform_data rd88f5182_gpio_led_data = {
+        .leds           = rd88f5182_gpio_led_pins,
+        .num_leds       = ARRAY_SIZE(rd88f5182_gpio_led_pins),
+};
 
-#endif
+static struct platform_device rd88f5182_gpio_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &rd88f5182_gpio_led_data,
+        },
+};
 
 /*****************************************************************************
  * PCI
@@ -298,6 +269,7 @@ static void __init rd88f5182_init(void)
 
         orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
         platform_device_register(&rd88f5182_nor_flash);
+        platform_device_register(&rd88f5182_gpio_leds);
 
         i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
 }
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 92df49c1b62a..ed50910b08a4 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -20,7 +20,6 @@
 #include <linux/ethtool.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index b4203277f3cd..b0727dcd1ef9 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -36,7 +36,7 @@
  * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
  */
 #define TS78XX_FPGA_REGS_PHYS_BASE      0xe8000000
-#define TS78XX_FPGA_REGS_VIRT_BASE      0xff900000
+#define TS78XX_FPGA_REGS_VIRT_BASE      IOMEM(0xff900000)
 #define TS78XX_FPGA_REGS_SIZE           SZ_1M
 
 static struct ts78xx_fpga_data ts78xx_fpga = {
@@ -50,7 +50,7 @@ static struct ts78xx_fpga_data ts78xx_fpga = {
  ****************************************************************************/
 static struct map_desc ts78xx_io_desc[] __initdata = {
         {
-                .virtual        = TS78XX_FPGA_REGS_VIRT_BASE,
+                .virtual        = (unsigned long)TS78XX_FPGA_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
                 .length         = TS78XX_FPGA_REGS_SIZE,
                 .type           = MT_DEVICE,
@@ -80,8 +80,8 @@ static struct mv_sata_platform_data ts78xx_sata_data = {
 /*****************************************************************************
  * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
  ****************************************************************************/
-#define TS_RTC_CTRL     (TS78XX_FPGA_REGS_VIRT_BASE | 0x808)
-#define TS_RTC_DATA     (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c)
+#define TS_RTC_CTRL     (TS78XX_FPGA_REGS_VIRT_BASE + 0x808)
+#define TS_RTC_DATA     (TS78XX_FPGA_REGS_VIRT_BASE + 0x80c)
 
 static unsigned char ts78xx_ts_rtc_readbyte(unsigned long addr)
 {
@@ -162,8 +162,8 @@ static void ts78xx_ts_rtc_unload(void)
 /*****************************************************************************
  * NAND Flash
  ****************************************************************************/
-#define TS_NAND_CTRL    (TS78XX_FPGA_REGS_VIRT_BASE | 0x800)    /* VIRT */
-#define TS_NAND_DATA    (TS78XX_FPGA_REGS_PHYS_BASE | 0x804)    /* PHYS */
+#define TS_NAND_CTRL    (TS78XX_FPGA_REGS_VIRT_BASE + 0x800)    /* VIRT */
+#define TS_NAND_DATA    (TS78XX_FPGA_REGS_PHYS_BASE + 0x804)    /* PHYS */
 
 /*
  * hardware specific access to control-lines
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 2bedc9ed076c..ee88d6eae648 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -98,12 +98,4 @@ obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR)	+= raumfeld.o
 obj-$(CONFIG_MACH_RAUMFELD_SPEAKER)     += raumfeld.o
 obj-$(CONFIG_MACH_ZIPIT2)       += z2.o
 
-# Support for blinky lights
-led-y := leds.o
-led-$(CONFIG_ARCH_LUBBOCK)      += leds-lubbock.o
-led-$(CONFIG_MACH_MAINSTONE)    += leds-mainstone.o
-led-$(CONFIG_ARCH_PXA_IDP)      += leds-idp.o
-
-obj-$(CONFIG_LEDS)              += $(led-y)
-
 obj-$(CONFIG_TOSA_BT)           += tosa-bt.o
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index c36151940d17..64507cdd2e8f 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -191,6 +191,87 @@ static void __init idp_map_io(void)
         iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc));
 }
 
+/* LEDs */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct idp_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} idp_leds[] = {
+        { "idp:green", "heartbeat", },
+        { "idp:red", "cpu0", },
+};
+
+static void idp_led_set(struct led_classdev *cdev,
+                enum led_brightness b)
+{
+        struct idp_led *led = container_of(cdev,
+                        struct idp_led, cdev);
+        u32 reg = IDP_CPLD_LED_CONTROL;
+
+        if (b != LED_OFF)
+                reg &= ~led->mask;
+        else
+                reg |= led->mask;
+
+        IDP_CPLD_LED_CONTROL = reg;
+}
+
+static enum led_brightness idp_led_get(struct led_classdev *cdev)
+{
+        struct idp_led *led = container_of(cdev,
+                        struct idp_led, cdev);
+
+        return (IDP_CPLD_LED_CONTROL & led->mask) ? LED_OFF : LED_FULL;
+}
+
+static int __init idp_leds_init(void)
+{
+        int i;
+
+        if (!machine_is_pxa_idp())
+                return -ENODEV;
+
+        for (i = 0; i < ARRAY_SIZE(idp_leds); i++) {
+                struct idp_led *led;
+
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+
+                led->cdev.name = idp_leds[i].name;
+                led->cdev.brightness_set = idp_led_set;
+                led->cdev.brightness_get = idp_led_get;
+                led->cdev.default_trigger = idp_leds[i].trigger;
+
+                if (i == 0)
+                        led->mask = IDP_HB_LED;
+                else
+                        led->mask = IDP_BUSY_LED;
+
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+
+        return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(idp_leds_init);
+#endif
 
 MACHINE_START(PXA_IDP, "Vibren PXA255 IDP")
         /* Maintainer: Vibren Technologies */
diff --git a/arch/arm/mach-pxa/leds-idp.c b/arch/arm/mach-pxa/leds-idp.c
deleted file mode 100644
index 06b060025d11..000000000000
--- a/arch/arm/mach-pxa/leds-idp.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds-idp.c
- *
- * Copyright (C) 2000 John Dorsey <john+@cs.cmu.edu>
- *
- * Copyright (c) 2001 Jeff Sutherland <jeffs@accelent.com>
- *
- * Original (leds-footbridge.c) by Russell King
- *
- * Macros for actual LED manipulation should be in machine specific
- * files in this 'mach' directory.
- */
-
-
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include <mach/pxa25x.h>
-#include <mach/idp.h>
-
-#include "leds.h"
-
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-void idp_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        switch (evt) {
-        case led_start:
-                hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
-                led_state = LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= IDP_HB_LED;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~IDP_BUSY_LED;
-                break;
-
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= IDP_BUSY_LED;
-                break;
-#endif
-
-        case led_halted:
-                break;
-
-        case led_green_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= IDP_HB_LED;
-                break;
-
-        case led_green_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~IDP_HB_LED;
-                break;
-
-        case led_amber_on:
-                break;
-
-        case led_amber_off:
-                break;
-
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= IDP_BUSY_LED;
-                break;
-
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~IDP_BUSY_LED;
-                break;
-
-        default:
-                break;
-        }
-
-        if  (led_state & LED_STATE_ENABLED)
-                IDP_CPLD_LED_CONTROL = ( (IDP_CPLD_LED_CONTROL | IDP_LEDS_MASK) & ~hw_led_state);
-        else
-                IDP_CPLD_LED_CONTROL |= IDP_LEDS_MASK;
-
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-pxa/leds-lubbock.c b/arch/arm/mach-pxa/leds-lubbock.c
deleted file mode 100644
index 0bd85c884a7c..000000000000
--- a/arch/arm/mach-pxa/leds-lubbock.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds-lubbock.c
- *
- * Copyright (C) 2000 John Dorsey <john+@cs.cmu.edu>
- *
- * Copyright (c) 2001 Jeff Sutherland <jeffs@accelent.com>
- *
- * Original (leds-footbridge.c) by Russell King
- *
- * Major surgery on April 2004 by Nicolas Pitre for less global
- * namespace collision.  Mostly adapted the Mainstone version.
- */
-
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <mach/pxa25x.h>
-#include <mach/lubbock.h>
-
-#include "leds.h"
-
-/*
- * 8 discrete leds available for general use:
- *
- * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
- * so be sure to not monkey with them here.
- */
-
-#define D28                     (1 << 0)
-#define D27                     (1 << 1)
-#define D26                     (1 << 2)
-#define D25                     (1 << 3)
-#define D24                     (1 << 4)
-#define D23                     (1 << 5)
-#define D22                     (1 << 6)
-#define D21                     (1 << 7)
-
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-void lubbock_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        switch (evt) {
-        case led_start:
-                hw_led_state = 0;
-                led_state = LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                hw_led_state ^= D26;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                hw_led_state &= ~D27;
-                break;
-
-        case led_idle_end:
-                hw_led_state |= D27;
-                break;
-#endif
-
-        case led_halted:
-                break;
-
-        case led_green_on:
-                hw_led_state |= D21;
-                break;
-
-        case led_green_off:
-                hw_led_state &= ~D21;
-                break;
-
-        case led_amber_on:
-                hw_led_state |= D22;
-                break;
-
-        case led_amber_off:
-                hw_led_state &= ~D22;
-                break;
-
-        case led_red_on:
-                hw_led_state |= D23;
-                break;
-
-        case led_red_off:
-                hw_led_state &= ~D23;
-                break;
-
-        default:
-                break;
-        }
-
-        if  (led_state & LED_STATE_ENABLED)
-                LUB_DISC_BLNK_LED = (LUB_DISC_BLNK_LED | 0xff) & ~hw_led_state;
-        else
-                LUB_DISC_BLNK_LED |= 0xff;
-
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-pxa/leds-mainstone.c b/arch/arm/mach-pxa/leds-mainstone.c
deleted file mode 100644
index 4058ab340fe6..000000000000
--- a/arch/arm/mach-pxa/leds-mainstone.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds-mainstone.c
- *
- * Author:     Nicolas Pitre
- * Created:    Nov 05, 2002
- * Copyright:  MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include <mach/pxa27x.h>
-#include <mach/mainstone.h>
-
-#include "leds.h"
-
-
-/* 8 discrete leds available for general use: */
-#define D28                     (1 << 0)
-#define D27                     (1 << 1)
-#define D26                     (1 << 2)
-#define D25                     (1 << 3)
-#define D24                     (1 << 4)
-#define D23                     (1 << 5)
-#define D22                     (1 << 6)
-#define D21                     (1 << 7)
-
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-void mainstone_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        switch (evt) {
-        case led_start:
-                hw_led_state = 0;
-                led_state = LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                hw_led_state ^= D26;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                hw_led_state &= ~D27;
-                break;
-
-        case led_idle_end:
-                hw_led_state |= D27;
-                break;
-#endif
-
-        case led_halted:
-                break;
-
-        case led_green_on:
-                hw_led_state |= D21;
-                break;
-
-        case led_green_off:
-                hw_led_state &= ~D21;
-                break;
-
-        case led_amber_on:
-                hw_led_state |= D22;
-                break;
-
-        case led_amber_off:
-                hw_led_state &= ~D22;
-                break;
-
-        case led_red_on:
-                hw_led_state |= D23;
-                break;
-
-        case led_red_off:
-                hw_led_state &= ~D23;
-                break;
-
-        default:
-                break;
-        }
-
-        if  (led_state & LED_STATE_ENABLED)
-                MST_LEDCTRL = (MST_LEDCTRL | 0xff) & ~hw_led_state;
-        else
-                MST_LEDCTRL |= 0xff;
-
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-pxa/leds.c b/arch/arm/mach-pxa/leds.c
deleted file mode 100644
index bbe4d5f6afaa..000000000000
--- a/arch/arm/mach-pxa/leds.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds.c
- *
- * xscale LEDs dispatcher
- *
- * Copyright (C) 2001 Nicolas Pitre
- *
- * Copyright (c) 2001 Jeff Sutherland, Accelent Systems Inc.
- */
-#include <linux/compiler.h>
-#include <linux/init.h>
-
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#include "leds.h"
-
-static int __init
-pxa_leds_init(void)
-{
-        if (machine_is_lubbock())
-                leds_event = lubbock_leds_event;
-        if (machine_is_mainstone())
-                leds_event = mainstone_leds_event;
-        if (machine_is_pxa_idp())
-                leds_event = idp_leds_event;
-
-        leds_event(led_start);
-        return 0;
-}
-
-core_initcall(pxa_leds_init);
diff --git a/arch/arm/mach-pxa/leds.h b/arch/arm/mach-pxa/leds.h
deleted file mode 100644
index 7f0dfe01345a..000000000000
--- a/arch/arm/mach-pxa/leds.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-pxa/leds.h
- *
- * Copyright (c) 2001 Jeff Sutherland, Accelent Systems Inc.
- *
- * blinky lights for various PXA-based systems:
- *
- */
-
-extern void idp_leds_event(led_event_t evt);
-extern void lubbock_leds_event(led_event_t evt);
-extern void mainstone_leds_event(led_event_t evt);
-extern void trizeps4_leds_event(led_event_t evt);
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 44dd7565707e..553056d9a3c5 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/syscore_ops.h>
 #include <linux/major.h>
@@ -23,6 +24,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/smc91x.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
@@ -549,6 +552,98 @@ static void __init lubbock_map_io(void)
         PCFR |= PCFR_OPDE;
 }
 
+/*
+ * Driver for the 8 discrete LEDs available for general use:
+ * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
+ * so be sure to not monkey with them here.
+ */
+
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct lubbock_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} lubbock_leds[] = {
+        { "lubbock:D28", "default-on", },
+        { "lubbock:D27", "cpu0", },
+        { "lubbock:D26", "heartbeat" },
+        { "lubbock:D25", },
+        { "lubbock:D24", },
+        { "lubbock:D23", },
+        { "lubbock:D22", },
+        { "lubbock:D21", },
+};
+
+static void lubbock_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
+{
+        struct lubbock_led *led = container_of(cdev,
+                                         struct lubbock_led, cdev);
+        u32 reg = LUB_DISC_BLNK_LED;
+
+        if (b != LED_OFF)
+                reg |= led->mask;
+        else
+                reg &= ~led->mask;
+
+        LUB_DISC_BLNK_LED = reg;
+}
+
+static enum led_brightness lubbock_led_get(struct led_classdev *cdev)
+{
+        struct lubbock_led *led = container_of(cdev,
+                                         struct lubbock_led, cdev);
+        u32 reg = LUB_DISC_BLNK_LED;
+
+        return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
+
+static int __init lubbock_leds_init(void)
+{
+        int i;
+
+        if (!machine_is_lubbock())
+                return -ENODEV;
+
+        /* All ON */
+        LUB_DISC_BLNK_LED |= 0xff;
+        for (i = 0; i < ARRAY_SIZE(lubbock_leds); i++) {
+                struct lubbock_led *led;
+
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+
+                led->cdev.name = lubbock_leds[i].name;
+                led->cdev.brightness_set = lubbock_led_set;
+                led->cdev.brightness_get = lubbock_led_get;
+                led->cdev.default_trigger = lubbock_leds[i].trigger;
+                led->mask = BIT(i);
+
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+
+        return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(lubbock_leds_init);
+#endif
+
 MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
         /* Maintainer: MontaVista Software Inc. */
         .map_io         = lubbock_map_io,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 5d9475730a3f..f27a61ee7ac7 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -28,6 +28,8 @@
 #include <linux/pwm_backlight.h>
 #include <linux/smc91x.h>
 #include <linux/i2c/pxa-i2c.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -613,6 +615,98 @@ static void __init mainstone_map_io(void)
         PCFR = 0x66;
 }
 
+/*
+ * Driver for the 8 discrete LEDs available for general use:
+ * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
+ * so be sure to not monkey with them here.
+ */
+
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct mainstone_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} mainstone_leds[] = {
+        { "mainstone:D28", "default-on", },
+        { "mainstone:D27", "cpu0", },
+        { "mainstone:D26", "heartbeat" },
+        { "mainstone:D25", },
+        { "mainstone:D24", },
+        { "mainstone:D23", },
+        { "mainstone:D22", },
+        { "mainstone:D21", },
+};
+
+static void mainstone_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
+{
+        struct mainstone_led *led = container_of(cdev,
+                                         struct mainstone_led, cdev);
+        u32 reg = MST_LEDCTRL;
+
+        if (b != LED_OFF)
+                reg |= led->mask;
+        else
+                reg &= ~led->mask;
+
+        MST_LEDCTRL = reg;
+}
+
+static enum led_brightness mainstone_led_get(struct led_classdev *cdev)
+{
+        struct mainstone_led *led = container_of(cdev,
+                                         struct mainstone_led, cdev);
+        u32 reg = MST_LEDCTRL;
+
+        return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
+
+static int __init mainstone_leds_init(void)
+{
+        int i;
+
+        if (!machine_is_mainstone())
+                return -ENODEV;
+
+        /* All ON */
+        MST_LEDCTRL |= 0xff;
+        for (i = 0; i < ARRAY_SIZE(mainstone_leds); i++) {
+                struct mainstone_led *led;
+
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+
+                led->cdev.name = mainstone_leds[i].name;
+                led->cdev.brightness_set = mainstone_led_set;
+                led->cdev.brightness_get = mainstone_led_get;
+                led->cdev.default_trigger = mainstone_leds[i].trigger;
+                led->mask = BIT(i);
+
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+
+        return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(mainstone_leds_init);
+#endif
+
 MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
         /* Maintainer: MontaVista Software Inc. */
         .atag_offset    = 0x100,        /* BLOB boot parameter setting */
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 9a154bad1984..5a406f794798 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -579,8 +579,8 @@ static int sharpsl_ac_check(void)
 static int sharpsl_pm_suspend(struct platform_device *pdev, pm_message_t state)
 {
         sharpsl_pm.flags |= SHARPSL_SUSPENDED;
-        flush_delayed_work_sync(&toggle_charger);
-        flush_delayed_work_sync(&sharpsl_bat);
+        flush_delayed_work(&toggle_charger);
+        flush_delayed_work(&sharpsl_bat);
 
         if (sharpsl_pm.charge_mode == CHRG_ON)
                 sharpsl_pm.flags |= SHARPSL_DO_OFFLINE_CHRG;
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 08ea7a84a291..456560b5aad4 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -52,7 +52,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/pxa2xx_spi.h>
 #include <linux/mfd/da903x.h>
-#include <linux/sht15.h>
+#include <linux/platform_data/sht15.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index ff007d15e0ec..682467480588 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -34,7 +34,6 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst.h>
@@ -330,44 +329,6 @@ struct clcd_board clcd_plat_data = {
         .remove         = versatile_clcd_remove_dma,
 };
 
-#ifdef CONFIG_LEDS
-#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
-
-void realview_leds_event(led_event_t ledevt)
-{
-        unsigned long flags;
-        u32 val;
-        u32 led = 1 << smp_processor_id();
-
-        local_irq_save(flags);
-        val = readl(VA_LEDS_BASE);
-
-        switch (ledevt) {
-        case led_idle_start:
-                val = val & ~led;
-                break;
-
-        case led_idle_end:
-                val = val | led;
-                break;
-
-        case led_timer:
-                val = val ^ REALVIEW_SYS_LED7;
-                break;
-
-        case led_halted:
-                val = 0;
-                break;
-
-        default:
-                break;
-        }
-
-        writel(val, VA_LEDS_BASE);
-        local_irq_restore(flags);
-}
-#endif  /* CONFIG_LEDS */
-
 /*
  * Where is the timer (VA)?
  */
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 78cd970c80f2..602ca5ec52c5 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -26,7 +26,6 @@
 #include <linux/io.h>
 
 #include <asm/setup.h>
-#include <asm/leds.h>
 
 #define APB_DEVICE(name, busid, base, plat)                     \
 static AMBA_APB_DEVICE(name, busid, 0, REALVIEW_##base##_BASE, base##_IRQ, plat)
@@ -47,7 +46,6 @@ extern void __iomem *timer1_va_base;
 extern void __iomem *timer2_va_base;
 extern void __iomem *timer3_va_base;
 
-extern void realview_leds_event(led_event_t ledevt);
 extern void realview_timer_init(unsigned int timer_irq);
 extern int realview_flash_register(struct resource *res, u32 num);
 extern int realview_eth_register(const char *name, struct resource *res);
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index ce7747692c8b..d3b3cd216d64 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -31,7 +31,6 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
@@ -463,10 +462,6 @@ static void __init realview_eb_init(void)
                 struct amba_device *d = amba_devs[i];
                 amba_device_register(d, &iomem_resource);
         }
-
-#ifdef CONFIG_LEDS
-        leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index e21711d72ee2..07d6672ddae7 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -33,7 +33,6 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
@@ -376,10 +375,6 @@ static void __init realview_pb1176_init(void)
                 struct amba_device *d = amba_devs[i];
                 amba_device_register(d, &iomem_resource);
         }
-
-#ifdef CONFIG_LEDS
-        leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index a80269981dd4..7ed53d75350f 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -31,7 +31,6 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
@@ -358,10 +357,6 @@ static void __init realview_pb11mp_init(void)
                 struct amba_device *d = amba_devs[i];
                 amba_device_register(d, &iomem_resource);
         }
-
-#ifdef CONFIG_LEDS
-        leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 1435cd863965..9992431b8a15 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -30,7 +30,6 @@
 #include <linux/platform_data/clk-realview.h>
 
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
@@ -300,10 +299,6 @@ static void __init realview_pba8_init(void)
                 struct amba_device *d = amba_devs[i];
                 amba_device_register(d, &iomem_resource);
         }
-
-#ifdef CONFIG_LEDS
-        leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index a4b1aa93bb5a..4f486f05108a 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -29,7 +29,6 @@
 #include <linux/platform_data/clk-realview.h>
 
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/smp_twd.h>
 #include <asm/pgtable.h>
@@ -395,10 +394,6 @@ static void __init realview_pbx_init(void)
                 struct amba_device *d = amba_devs[i];
                 amba_device_register(d, &iomem_resource);
         }
-
-#ifdef CONFIG_LEDS
-        leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index cb2883d553b5..749220f91a70 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
@@ -87,6 +87,19 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
+static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);
+
+        if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL))
+                return parent_rate;
+
+        camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK;
+
+        return parent_rate / (camdivn + 1) / 2;
+}
+
 /* Extra S3C2440 clocks */
 
 static struct clk s3c2440_clk_cam = {
@@ -99,6 +112,7 @@ static struct clk s3c2440_clk_cam_upll = {
         .name           = "camif-upll",
         .ops            = &(struct clk_ops) {
                 .set_rate       = s3c2440_camif_upll_setrate,
+                .get_rate       = s3c2440_camif_upll_getrate,
                 .round_rate     = s3c2440_camif_upll_round,
         },
 };
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index 9638b337593c..63aaf076f611 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -380,7 +380,7 @@ int h1940_led_blink_set(unsigned gpio, int state,
         default:
                 blink_gpio = S3C2410_GPA(3);
                 check_gpio1 = S3C2410_GPA(1);
-                check_gpio1 = S3C2410_GPA(7);
+                check_gpio2 = S3C2410_GPA(7);
                 break;
         }
 
@@ -460,7 +460,7 @@ static void h1940_set_mmc_power(unsigned char power_mode, unsigned short vdd)
                 break;
         default:
                 break;
-        };
+        }
 }
 
 static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = {
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 181aa99427fe..4e3fe57674c8 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -16,6 +16,7 @@
 #include <linux/mfd/wm831x/irq.h>
 #include <linux/mfd/wm831x/gpio.h>
 #include <linux/mfd/wm8994/pdata.h>
+#include <linux/mfd/arizona/pdata.h>
 
 #include <linux/regulator/machine.h>
 
@@ -181,9 +182,33 @@ static const struct i2c_board_info wm1277_devs[] = {
         },
 };
 
-static const struct i2c_board_info wm5102_devs[] = {
-        { I2C_BOARD_INFO("wm5102", 0x1a),
-          .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, },
+static struct arizona_pdata wm5102_pdata = {
+        .ldoena = S3C64XX_GPN(7),
+        .gpio_base = CODEC_GPIO_BASE,
+        .irq_active_high = true,
+        .micd_pol_gpio = CODEC_GPIO_BASE + 4,
+        .gpio_defaults = {
+                [2] = 0x10000, /* AIF3TXLRCLK */
+                [3] = 0x4,     /* OPCLK */
+        },
+};
+
+static struct s3c64xx_spi_csinfo wm5102_spi_csinfo = {
+        .line = S3C64XX_GPN(5),
+};
+
+static struct spi_board_info wm5102_spi_devs[] = {
+        [0] = {
+                .modalias       = "wm5102",
+                .max_speed_hz   = 10 * 1000 * 1000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_0,
+                .irq            = GLENFARCLAS_PMIC_IRQ_BASE +
+                                  WM831X_IRQ_GPIO_2,
+                .controller_data = &wm5102_spi_csinfo,
+                .platform_data = &wm5102_pdata,
+        },
 };
 
 static const struct i2c_board_info wm6230_i2c_devs[] = {
@@ -223,8 +248,9 @@ static __devinitdata const struct {
         { .id = 0x3c, .name = "1273-EV1 Longmorn" },
         { .id = 0x3d, .name = "1277-EV1 Littlemill",
           .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) },
-        { .id = 0x3e, .name = "WM5102-6271-EV1-CS127",
-          .i2c_devs = wm5102_devs, .num_i2c_devs = ARRAY_SIZE(wm5102_devs) },
+        { .id = 0x3e, .name = "WM5102-6271-EV1-CS127 Amrut",
+          .spi_devs = wm5102_spi_devs,
+          .num_spi_devs = ARRAY_SIZE(wm5102_spi_devs) },
 };
 
 static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 717d675188d4..8b4d46706645 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -287,6 +287,16 @@ static struct platform_device littlemill_device = {
         .id             = -1,
 };
 
+static struct platform_device bells_wm5102_device = {
+        .name           = "bells",
+        .id             = 0,
+};
+
+static struct platform_device bells_wm5110_device = {
+        .name           = "bells",
+        .id             = 1,
+};
+
 static struct regulator_consumer_supply wallvdd_consumers[] = {
         REGULATOR_SUPPLY("SPKVDD", "1-001a"),
         REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
@@ -359,6 +369,8 @@ static struct platform_device *crag6410_devices[] __initdata = {
         &tobermory_device,
         &littlemill_device,
         &lowland_device,
+        &bells_wm5102_device,
+        &bells_wm5110_device,
         &wallvdd_device,
 };
 
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index 60b97ec01676..1aed9e70465d 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -7,21 +7,17 @@ obj-y := clock.o generic.o irq.o time.o #nmi-oopser.o
 obj-m :=
 obj-n :=
 obj-  :=
-led-y := leds.o
 
 obj-$(CONFIG_CPU_FREQ_SA1100)           += cpu-sa1100.o
 obj-$(CONFIG_CPU_FREQ_SA1110)           += cpu-sa1110.o
 
 # Specific board support
 obj-$(CONFIG_SA1100_ASSABET)            += assabet.o
-led-$(CONFIG_SA1100_ASSABET)            += leds-assabet.o
 obj-$(CONFIG_ASSABET_NEPONSET)          += neponset.o
 
 obj-$(CONFIG_SA1100_BADGE4)             += badge4.o
-led-$(CONFIG_SA1100_BADGE4)             += leds-badge4.o
 
 obj-$(CONFIG_SA1100_CERF)               += cerf.o
-led-$(CONFIG_SA1100_CERF)               += leds-cerf.o
 
 obj-$(CONFIG_SA1100_COLLIE)             += collie.o
 
@@ -29,13 +25,11 @@ obj-$(CONFIG_SA1100_H3100)		+= h3100.o h3xxx.o
 obj-$(CONFIG_SA1100_H3600)              += h3600.o h3xxx.o
 
 obj-$(CONFIG_SA1100_HACKKIT)            += hackkit.o
-led-$(CONFIG_SA1100_HACKKIT)            += leds-hackkit.o
 
 obj-$(CONFIG_SA1100_JORNADA720)         += jornada720.o
 obj-$(CONFIG_SA1100_JORNADA720_SSP)     += jornada720_ssp.o
 
 obj-$(CONFIG_SA1100_LART)               += lart.o
-led-$(CONFIG_SA1100_LART)               += leds-lart.o
 
 obj-$(CONFIG_SA1100_NANOENGINE)         += nanoengine.o
 obj-$(CONFIG_PCI_NANOENGINE)            += pci-nanoengine.o
@@ -46,9 +40,6 @@ obj-$(CONFIG_SA1100_SHANNON)		+= shannon.o
 
 obj-$(CONFIG_SA1100_SIMPAD)             += simpad.o
 
-# LEDs support
-obj-$(CONFIG_LEDS) += $(led-y)
-
 # Miscellaneous functions
 obj-$(CONFIG_PM)                        += pm.o sleep.o
 obj-$(CONFIG_SA1100_SSP)                += ssp.o
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index ba49241b02f0..e1ccda6128eb 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -20,6 +20,8 @@
 #include <linux/mtd/partitions.h>
 #include <linux/delay.h>
 #include <linux/mm.h>
+#include <linux/leds.h>
+#include <linux/slab.h>
 
 #include <video/sa1100fb.h>
 
@@ -529,6 +531,89 @@ static void __init assabet_map_io(void)
         sa1100_register_uart(2, 3);
 }
 
+/* LEDs */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct assabet_led {
+        struct led_classdev cdev;
+        u32 mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} assabet_leds[] = {
+        { "assabet:red", "cpu0",},
+        { "assabet:green", "heartbeat", },
+};
+
+/*
+ * The LED control in Assabet is reversed:
+ *  - setting bit means turn off LED
+ *  - clearing bit means turn on LED
+ */
+static void assabet_led_set(struct led_classdev *cdev,
+                enum led_brightness b)
+{
+        struct assabet_led *led = container_of(cdev,
+                        struct assabet_led, cdev);
+
+        if (b != LED_OFF)
+                ASSABET_BCR_clear(led->mask);
+        else
+                ASSABET_BCR_set(led->mask);
+}
+
+static enum led_brightness assabet_led_get(struct led_classdev *cdev)
+{
+        struct assabet_led *led = container_of(cdev,
+                        struct assabet_led, cdev);
+
+        return (ASSABET_BCR & led->mask) ? LED_OFF : LED_FULL;
+}
+
+static int __init assabet_leds_init(void)
+{
+        int i;
+
+        if (!machine_is_assabet())
+                return -ENODEV;
+
+        for (i = 0; i < ARRAY_SIZE(assabet_leds); i++) {
+                struct assabet_led *led;
+
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+
+                led->cdev.name = assabet_leds[i].name;
+                led->cdev.brightness_set = assabet_led_set;
+                led->cdev.brightness_get = assabet_led_get;
+                led->cdev.default_trigger = assabet_leds[i].trigger;
+
+                if (!i)
+                        led->mask = ASSABET_BCR_LED_RED;
+                else
+                        led->mask = ASSABET_BCR_LED_GREEN;
+
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+
+        return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(assabet_leds_init);
+#endif
 
 MACHINE_START(ASSABET, "Intel-Assabet")
         .atag_offset    = 0x100,
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index b30fb99b587c..038df4894b0f 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -22,6 +22,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/errno.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -76,8 +78,36 @@ static struct platform_device sa1111_device = {
         .resource       = sa1111_resources,
 };
 
+/* LEDs */
+struct gpio_led badge4_gpio_leds[] = {
+        {
+                .name                   = "badge4:red",
+                .default_trigger        = "heartbeat",
+                .gpio                   = 7,
+        },
+        {
+                .name                   = "badge4:green",
+                .default_trigger        = "cpu0",
+                .gpio                   = 9,
+        },
+};
+
+static struct gpio_led_platform_data badge4_gpio_led_info = {
+        .leds           = badge4_gpio_leds,
+        .num_leds       = ARRAY_SIZE(badge4_gpio_leds),
+};
+
+static struct platform_device badge4_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &badge4_gpio_led_info,
+        }
+};
+
 static struct platform_device *devices[] __initdata = {
         &sa1111_device,
+        &badge4_leds,
 };
 
 static int __init badge4_sa1111_init(void)
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index 985d0b584717..ad0eb08ea077 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -17,6 +17,8 @@
 #include <linux/irq.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -43,8 +45,48 @@ static struct platform_device cerfuart2_device = {
         .resource       = cerfuart2_resources,
 };
 
+/* LEDs */
+struct gpio_led cerf_gpio_leds[] = {
+        {
+                .name                   = "cerf:d0",
+                .default_trigger        = "heartbeat",
+                .gpio                   = 0,
+        },
+        {
+                .name                   = "cerf:d1",
+                .default_trigger        = "cpu0",
+                .gpio                   = 1,
+        },
+        {
+                .name                   = "cerf:d2",
+                .default_trigger        = "default-on",
+                .gpio                   = 2,
+        },
+        {
+                .name                   = "cerf:d3",
+                .default_trigger        = "default-on",
+                .gpio                   = 3,
+        },
+
+};
+
+static struct gpio_led_platform_data cerf_gpio_led_info = {
+        .leds           = cerf_gpio_leds,
+        .num_leds       = ARRAY_SIZE(cerf_gpio_leds),
+};
+
+static struct platform_device cerf_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &cerf_gpio_led_info,
+        }
+};
+
+
 static struct platform_device *cerf_devices[] __initdata = {
         &cerfuart2_device,
+        &cerf_leds,
 };
 
 #ifdef CONFIG_SA1100_CERF_FLASH_32MB
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index 7f86bd911826..fc106aab7c7e 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -21,6 +21,10 @@
 #include <linux/serial_core.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/tty.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
 
 #include <asm/mach-types.h>
 #include <asm/setup.h>
@@ -183,9 +187,37 @@ static struct flash_platform_data hackkit_flash_data = {
 static struct resource hackkit_flash_resource =
         DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
 
+/* LEDs */
+struct gpio_led hackkit_gpio_leds[] = {
+        {
+                .name                   = "hackkit:red",
+                .default_trigger        = "cpu0",
+                .gpio                   = 22,
+        },
+        {
+                .name                   = "hackkit:green",
+                .default_trigger        = "heartbeat",
+                .gpio                   = 23,
+        },
+};
+
+static struct gpio_led_platform_data hackkit_gpio_led_info = {
+        .leds           = hackkit_gpio_leds,
+        .num_leds       = ARRAY_SIZE(hackkit_gpio_leds),
+};
+
+static struct platform_device hackkit_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &hackkit_gpio_led_info,
+        }
+};
+
 static void __init hackkit_init(void)
 {
         sa11x0_register_mtd(&hackkit_flash_data, &hackkit_flash_resource, 1);
+        platform_device_register(&hackkit_leds);
 }
 
 /**********************************************************************
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index 7dc1a89b1273..3048b17e84c5 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -5,6 +5,9 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/tty.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
 
 #include <video/sa1100fb.h>
 
@@ -126,6 +129,27 @@ static struct map_desc lart_io_desc[] __initdata = {
         }
 };
 
+/* LEDs */
+struct gpio_led lart_gpio_leds[] = {
+        {
+                .name                   = "lart:red",
+                .default_trigger        = "cpu0",
+                .gpio                   = 23,
+        },
+};
+
+static struct gpio_led_platform_data lart_gpio_led_info = {
+        .leds           = lart_gpio_leds,
+        .num_leds       = ARRAY_SIZE(lart_gpio_leds),
+};
+
+static struct platform_device lart_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &lart_gpio_led_info,
+        }
+};
 static void __init lart_map_io(void)
 {
         sa1100_map_io();
@@ -139,6 +163,8 @@ static void __init lart_map_io(void)
         GPDR |= GPIO_UART_TXD;
         GPDR &= ~GPIO_UART_RXD;
         PPAR |= PPAR_UPR;
+
+        platform_device_register(&lart_leds);
 }
 
 MACHINE_START(LART, "LART")
diff --git a/arch/arm/mach-sa1100/leds-assabet.c b/arch/arm/mach-sa1100/leds-assabet.c
deleted file mode 100644
index 3699176bca94..000000000000
--- a/arch/arm/mach-sa1100/leds-assabet.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-assabet.c
- *
- * Copyright (C) 2000 John Dorsey <john+@cs.cmu.edu>
- *
- * Original (leds-footbridge.c) by Russell King
- *
- * Assabet uses the LEDs as follows:
- *   - Green - toggles state every 50 timer interrupts
- *   - Red   - on if system is not idle
- */
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <mach/assabet.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define ASSABET_BCR_LED_MASK    (ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED)
-
-void assabet_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        switch (evt) {
-        case led_start:
-                hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-                led_state = LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-                ASSABET_BCR_frob(ASSABET_BCR_LED_MASK, hw_led_state);
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= ASSABET_BCR_LED_GREEN;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= ASSABET_BCR_LED_RED;
-                break;
-
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~ASSABET_BCR_LED_RED;
-                break;
-#endif
-
-        case led_halted:
-                break;
-
-        case led_green_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~ASSABET_BCR_LED_GREEN;
-                break;
-
-        case led_green_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= ASSABET_BCR_LED_GREEN;
-                break;
-
-        case led_amber_on:
-                break;
-
-        case led_amber_off:
-                break;
-
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~ASSABET_BCR_LED_RED;
-                break;
-
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= ASSABET_BCR_LED_RED;
-                break;
-
-        default:
-                break;
-        }
-
-        if  (led_state & LED_STATE_ENABLED)
-                ASSABET_BCR_frob(ASSABET_BCR_LED_MASK, hw_led_state);
-
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-badge4.c b/arch/arm/mach-sa1100/leds-badge4.c
deleted file mode 100644
index f99fac3eedb6..000000000000
--- a/arch/arm/mach-sa1100/leds-badge4.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-badge4.c
- *
- * Author: Christopher Hoover <ch@hpl.hp.com>
- * Copyright (C) 2002 Hewlett-Packard Company
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define LED_RED         GPIO_GPIO(7)
-#define LED_GREEN       GPIO_GPIO(9)
-#define LED_MASK        (LED_RED|LED_GREEN)
-
-#define LED_IDLE        LED_GREEN
-#define LED_TIMER       LED_RED
-
-void badge4_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        switch (evt) {
-        case led_start:
-                GPDR |= LED_MASK;
-                hw_led_state = LED_MASK;
-                led_state = LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= LED_TIMER;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                /* LED off when system is idle */
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_IDLE;
-                break;
-
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_IDLE;
-                break;
-#endif
-
-        case led_red_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_RED;
-                break;
-
-        case led_red_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_RED;
-                break;
-
-        case led_green_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_GREEN;
-                break;
-
-        case led_green_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_GREEN;
-                break;
-
-        default:
-                break;
-        }
-
-        if  (led_state & LED_STATE_ENABLED) {
-                GPSR = hw_led_state;
-                GPCR = hw_led_state ^ LED_MASK;
-        }
-
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-cerf.c b/arch/arm/mach-sa1100/leds-cerf.c
deleted file mode 100644
index 30fc3b2bf555..000000000000
--- a/arch/arm/mach-sa1100/leds-cerf.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-cerf.c
- *
- * Author: ???
- */
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define LED_D0          GPIO_GPIO(0)
-#define LED_D1          GPIO_GPIO(1)
-#define LED_D2          GPIO_GPIO(2)
-#define LED_D3          GPIO_GPIO(3)
-#define LED_MASK        (LED_D0|LED_D1|LED_D2|LED_D3)
-
-void cerf_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        switch (evt) {
-        case led_start:
-                hw_led_state = LED_MASK;
-                led_state = LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= LED_D0;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D1;
-                break;
-
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D1;
-                break;
-#endif
-        case led_green_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D2;
-                break;
-
-        case led_green_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D2;
-                break;
-
-        case led_amber_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D3;
-                break;
-
-        case led_amber_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D3;
-                break;
-
-        case led_red_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D1;
-                break;
-
-        case led_red_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D1;
-                break;
-
-        default:
-                break;
-        }
-
-        if  (led_state & LED_STATE_ENABLED) {
-                GPSR = hw_led_state;
-                GPCR = hw_led_state ^ LED_MASK;
-        }
-
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-hackkit.c b/arch/arm/mach-sa1100/leds-hackkit.c
deleted file mode 100644
index f8e47235babe..000000000000
--- a/arch/arm/mach-sa1100/leds-hackkit.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-hackkit.c
- *
- * based on leds-lart.c
- *
- * (C) Erik Mouw (J.A.K.Mouw@its.tudelft.nl), April 21, 2000
- * (C) Stefan Eletzhofer <stefan.eletzhofer@eletztrick.de>, 2002
- *
- * The HackKit has two leds (GPIO 22/23). The red led (gpio 22) is used
- * as cpu led, the green one is used as timer led.
- */
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define LED_GREEN    GPIO_GPIO23
-#define LED_RED    GPIO_GPIO22
-#define LED_MASK  (LED_RED | LED_GREEN)
-
-void hackkit_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        switch(evt) {
-                case led_start:
-                        /* pin 22/23 are outputs */
-                        GPDR |= LED_MASK;
-                        hw_led_state = LED_MASK;
-                        led_state = LED_STATE_ENABLED;
-                        break;
-
-                case led_stop:
-                        led_state &= ~LED_STATE_ENABLED;
-                        break;
-
-                case led_claim:
-                        led_state |= LED_STATE_CLAIMED;
-                        hw_led_state = LED_MASK;
-                        break;
-
-                case led_release:
-                        led_state &= ~LED_STATE_CLAIMED;
-                        hw_led_state = LED_MASK;
-                        break;
-
-#ifdef CONFIG_LEDS_TIMER
-                case led_timer:
-                        if (!(led_state & LED_STATE_CLAIMED))
-                                hw_led_state ^= LED_GREEN;
-                        break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-                case led_idle_start:
-                        /* The LART people like the LED to be off when the
-                           system is idle... */
-                        if (!(led_state & LED_STATE_CLAIMED))
-                                hw_led_state &= ~LED_RED;
-                        break;
-
-                case led_idle_end:
-                        /* ... and on if the system is not idle */
-                        if (!(led_state & LED_STATE_CLAIMED))
-                                hw_led_state |= LED_RED;
-                        break;
-#endif
-
-                case led_red_on:
-                        if (led_state & LED_STATE_CLAIMED)
-                                hw_led_state &= ~LED_RED;
-                        break;
-
-                case led_red_off:
-                        if (led_state & LED_STATE_CLAIMED)
-                                hw_led_state |= LED_RED;
-                        break;
-
-                case led_green_on:
-                        if (led_state & LED_STATE_CLAIMED)
-                                hw_led_state &= ~LED_GREEN;
-                        break;
-
-                case led_green_off:
-                        if (led_state & LED_STATE_CLAIMED)
-                                hw_led_state |= LED_GREEN;
-                        break;
-
-                default:
-                        break;
-        }
-
-        /* Now set the GPIO state, or nothing will happen at all */
-        if (led_state & LED_STATE_ENABLED) {
-                GPSR = hw_led_state;
-                GPCR = hw_led_state ^ LED_MASK;
-        }
-
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-lart.c b/arch/arm/mach-sa1100/leds-lart.c
deleted file mode 100644
index 50a5b143b460..000000000000
--- a/arch/arm/mach-sa1100/leds-lart.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-lart.c
- *
- * (C) Erik Mouw (J.A.K.Mouw@its.tudelft.nl), April 21, 2000
- *
- * LART uses the LED as follows:
- *   - GPIO23 is the LED, on if system is not idle
- *  You can use both CONFIG_LEDS_CPU and CONFIG_LEDS_TIMER at the same
- *  time, but in that case the timer events will still dictate the
- *  pace of the LED.
- */
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define LED_23    GPIO_GPIO23
-#define LED_MASK  (LED_23)
-
-void lart_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        switch(evt) {
-        case led_start:
-                /* pin 23 is output pin */
-                GPDR |= LED_23;
-                hw_led_state = LED_MASK;
-                led_state = LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= LED_23;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                /* The LART people like the LED to be off when the
-                   system is idle... */
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_23;
-                break;
-
-        case led_idle_end:
-                /* ... and on if the system is not idle */
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_23;
-                break;
-#endif
-
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~LED_23;
-                break;
-
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= LED_23;
-                break;
-
-        default:
-                break;
-        }
-
-        /* Now set the GPIO state, or nothing will happen at all */
-        if (led_state & LED_STATE_ENABLED) {
-                GPSR = hw_led_state;
-                GPCR = hw_led_state ^ LED_MASK;
-        }
-
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds.c b/arch/arm/mach-sa1100/leds.c
deleted file mode 100644
index 5fe71a0f1053..000000000000
--- a/arch/arm/mach-sa1100/leds.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds.c
- *
- * SA1100 LEDs dispatcher
- *
- * Copyright (C) 2001 Nicolas Pitre
- */
-#include <linux/compiler.h>
-#include <linux/init.h>
-
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#include "leds.h"
-
-static int __init
-sa1100_leds_init(void)
-{
-        if (machine_is_assabet())
-                leds_event = assabet_leds_event;
-        if (machine_is_consus())
-                leds_event = consus_leds_event;
-        if (machine_is_badge4())
-                leds_event = badge4_leds_event;
-        if (machine_is_brutus())
-                leds_event = brutus_leds_event;
-        if (machine_is_cerf())
-                leds_event = cerf_leds_event;
-        if (machine_is_flexanet())
-                leds_event = flexanet_leds_event;
-        if (machine_is_graphicsclient())
-                leds_event = graphicsclient_leds_event;
-        if (machine_is_hackkit())
-                leds_event = hackkit_leds_event;
-        if (machine_is_lart())
-                leds_event = lart_leds_event;
-        if (machine_is_pfs168())
-                leds_event = pfs168_leds_event;
-        if (machine_is_graphicsmaster())
-                leds_event = graphicsmaster_leds_event;
-        if (machine_is_adsbitsy())
-                leds_event = adsbitsy_leds_event;
-        if (machine_is_pt_system3())
-                leds_event = system3_leds_event;
-
-        leds_event(led_start);
-        return 0;
-}
-
-core_initcall(sa1100_leds_init);
diff --git a/arch/arm/mach-sa1100/leds.h b/arch/arm/mach-sa1100/leds.h
deleted file mode 100644
index 776b6020f550..000000000000
--- a/arch/arm/mach-sa1100/leds.h
+++ /dev/null
@@ -1,13 +0,0 @@
-extern void assabet_leds_event(led_event_t evt);
-extern void badge4_leds_event(led_event_t evt);
-extern void consus_leds_event(led_event_t evt);
-extern void brutus_leds_event(led_event_t evt);
-extern void cerf_leds_event(led_event_t evt);
-extern void flexanet_leds_event(led_event_t evt);
-extern void graphicsclient_leds_event(led_event_t evt);
-extern void hackkit_leds_event(led_event_t evt);
-extern void lart_leds_event(led_event_t evt);
-extern void pfs168_leds_event(led_event_t evt);
-extern void graphicsmaster_leds_event(led_event_t evt);
-extern void adsbitsy_leds_event(led_event_t evt);
-extern void system3_leds_event(led_event_t evt);
diff --git a/arch/arm/mach-shark/Makefile b/arch/arm/mach-shark/Makefile
index 45be9b04e7ba..29657183c452 100644
--- a/arch/arm/mach-shark/Makefile
+++ b/arch/arm/mach-shark/Makefile
@@ -4,9 +4,7 @@
 
 # Object file lists.
 
-obj-y                   := core.o dma.o irq.o pci.o
+obj-y                   := core.o dma.o irq.o pci.o leds.o
 obj-m                   :=
 obj-n                   :=
 obj-                    :=
-
-obj-$(CONFIG_LEDS)      += leds.o
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index d35b94ef73b7..9ad2e9737fb5 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -13,7 +13,6 @@
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/param.h>
 #include <asm/system_misc.h>
 
diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c
index 25609076921f..081c778a10ac 100644
--- a/arch/arm/mach-shark/leds.c
+++ b/arch/arm/mach-shark/leds.c
@@ -1,165 +1,117 @@
 /*
- * arch/arm/mach-shark/leds.c
- * by Alexander Schulz
- *
- * derived from:
- * arch/arm/kernel/leds-footbridge.c
- * Copyright (C) 1998-1999 Russell King
- *
  * DIGITAL Shark LED control routines.
  *
- * The leds use is as follows:
- *  - Green front - toggles state every 50 timer interrupts
- *  - Amber front - Unused, this is a dual color led (Amber/Green)
- *  - Amber back  - On if system is not idle
+ * Driver for the 3 user LEDs found on the Shark
+ * Based on Versatile and RealView machine LED code
  *
- * Changelog:
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Bryan Wu <bryan.wu@canonical.com>
  */
 #include <linux/kernel.h>
-#include <linux/module.h>
 #include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/ioport.h>
 #include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
-#include <asm/leds.h>
+#include <asm/mach-types.h>
 
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct shark_led {
+        struct led_classdev cdev;
+        u8 mask;
+};
 
-#define SEQUOIA_LED_GREEN       (1<<6)
-#define SEQUOIA_LED_AMBER       (1<<5)
-#define SEQUOIA_LED_BACK        (1<<7)
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} shark_leds[] = {
+        { "shark:amber0", "default-on", },      /* Bit 5 */
+        { "shark:green", "heartbeat", },        /* Bit 6 */
+        { "shark:amber1", "cpu0" },             /* Bit 7 */
+};
+
+static u16 led_reg_read(void)
+{
+        outw(0x09, 0x24);
+        return inw(0x26);
+}
 
-static char led_state;
-static short hw_led_state;
-static short saved_state;
+static void led_reg_write(u16 value)
+{
+        outw(0x09, 0x24);
+        outw(value, 0x26);
+}
 
-static DEFINE_RAW_SPINLOCK(leds_lock);
+static void shark_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
+{
+        struct shark_led *led = container_of(cdev,
+                                                 struct shark_led, cdev);
+        u16 reg = led_reg_read();
 
-short sequoia_read(int addr) {
-  outw(addr,0x24);
-  return inw(0x26);
-}
+        if (b != LED_OFF)
+                reg |= led->mask;
+        else
+                reg &= ~led->mask;
 
-void sequoia_write(short value,short addr) {
-  outw(addr,0x24);
-  outw(value,0x26);
+        led_reg_write(reg);
 }
 
-static void sequoia_leds_event(led_event_t evt)
+static enum led_brightness shark_led_get(struct led_classdev *cdev)
 {
-        unsigned long flags;
-
-        raw_spin_lock_irqsave(&leds_lock, flags);
+        struct shark_led *led = container_of(cdev,
+                                                 struct shark_led, cdev);
+        u16 reg = led_reg_read();
 
-        hw_led_state = sequoia_read(0x09);
+        return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
 
-        switch (evt) {
-        case led_start:
-                hw_led_state |= SEQUOIA_LED_GREEN;
-                hw_led_state |= SEQUOIA_LED_AMBER;
-#ifdef CONFIG_LEDS_CPU
-                hw_led_state |= SEQUOIA_LED_BACK;
-#else
-                hw_led_state &= ~SEQUOIA_LED_BACK;
-#endif
-                led_state |= LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                hw_led_state &= ~SEQUOIA_LED_BACK;
-                hw_led_state |= SEQUOIA_LED_GREEN;
-                hw_led_state |= SEQUOIA_LED_AMBER;
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                saved_state = hw_led_state;
-                hw_led_state &= ~SEQUOIA_LED_BACK;
-                hw_led_state |= SEQUOIA_LED_GREEN;
-                hw_led_state |= SEQUOIA_LED_AMBER;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = saved_state;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= SEQUOIA_LED_GREEN;
-                break;
-#endif
+static int __init shark_leds_init(void)
+{
+        int i;
+        u16 reg;
 
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~SEQUOIA_LED_BACK;
-                break;
+        if (!machine_is_shark())
+                return -ENODEV;
 
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= SEQUOIA_LED_BACK;
-                break;
-#endif
+        for (i = 0; i < ARRAY_SIZE(shark_leds); i++) {
+                struct shark_led *led;
 
-        case led_green_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~SEQUOIA_LED_GREEN;
-                break;
-
-        case led_green_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= SEQUOIA_LED_GREEN;
-                break;
-
-        case led_amber_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~SEQUOIA_LED_AMBER;
-                break;
-
-        case led_amber_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= SEQUOIA_LED_AMBER;
-                break;
-
-        case led_red_on:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state |= SEQUOIA_LED_BACK;
-                break;
-
-        case led_red_off:
-                if (led_state & LED_STATE_CLAIMED)
-                        hw_led_state &= ~SEQUOIA_LED_BACK;
-                break;
-
-        default:
-                break;
-        }
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
 
-        if  (led_state & LED_STATE_ENABLED)
-                sequoia_write(hw_led_state,0x09);
+                led->cdev.name = shark_leds[i].name;
+                led->cdev.brightness_set = shark_led_set;
+                led->cdev.brightness_get = shark_led_get;
+                led->cdev.default_trigger = shark_leds[i].trigger;
 
-        raw_spin_unlock_irqrestore(&leds_lock, flags);
-}
+                /* Count in 5 bits offset */
+                led->mask = BIT(i + 5);
 
-static int __init leds_init(void)
-{
-        extern void (*leds_event)(led_event_t);
-        short temp;
-        
-        leds_event = sequoia_leds_event;
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
 
         /* Make LEDs independent of power-state */
-        request_region(0x24,4,"sequoia");
-        temp = sequoia_read(0x09);
-        temp |= 1<<10;
-        sequoia_write(temp,0x09);
-        leds_event(led_start);
+        request_region(0x24, 4, "led_reg");
+        reg = led_reg_read();
+        reg |= 1 << 10;
+        led_reg_write(reg);
+
         return 0;
 }
 
-__initcall(leds_init);
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(shark_leds_init);
+#endif
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 0df5ae6740c6..fe2c97c179d1 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common objects
-obj-y                           := timer.o console.o clock.o common.o
+obj-y                           := timer.o console.o clock.o
 
 # CPU objects
 obj-$(CONFIG_ARCH_SH7367)       += setup-sh7367.o clock-sh7367.o intc-sh7367.o
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index bc3b5da59e25..790dc68c4312 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1231,6 +1231,15 @@ static struct i2c_board_info i2c1_devices[] = {
 #define USCCR1          IOMEM(0xE6058144)
 static void __init ap4evb_init(void)
 {
+        struct pm_domain_device domain_devices[] = {
+                { "A4LC", &lcdc1_device, },
+                { "A4LC", &lcdc_device, },
+                { "A4MP", &fsi_device, },
+                { "A3SP", &sh_mmcif_device, },
+                { "A3SP", &sdhi0_device, },
+                { "A3SP", &sdhi1_device, },
+                { "A4R", &ceu_device, },
+        };
         u32 srcr4;
         struct clk *clk;
 
@@ -1463,14 +1472,8 @@ static void __init ap4evb_init(void)
 
         platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
 
-        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4mp, &fsi_device);
-
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sh_mmcif_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &ceu_device);
+        rmobile_add_devices_to_domains(domain_devices,
+                                       ARRAY_SIZE(domain_devices));
 
         hdmi_init_pm_clock();
         fsi_init_pm_clock();
@@ -1485,6 +1488,6 @@ MACHINE_START(AP4EVB, "ap4evb")
         .init_irq       = sh7372_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = ap4evb_init,
-        .init_late      = shmobile_init_late,
+        .init_late      = sh7372_pm_init_late,
         .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 206c3227f83d..2912eab3b967 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -37,6 +37,7 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/i2c-gpio.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7740.h>
@@ -879,6 +880,21 @@ static struct platform_device fsi_hdmi_device = {
         },
 };
 
+/* RTC: RTC connects i2c-gpio. */
+static struct i2c_gpio_platform_data i2c_gpio_data = {
+        .sda_pin        = GPIO_PORT208,
+        .scl_pin        = GPIO_PORT91,
+        .udelay         = 5, /* 100 kHz */
+};
+
+static struct platform_device i2c_gpio_device = {
+        .name = "i2c-gpio",
+        .id = 2,
+        .dev = {
+                .platform_data = &i2c_gpio_data,
+        },
+};
+
 /* I2C */
 static struct i2c_board_info i2c0_devices[] = {
         {
@@ -890,6 +906,13 @@ static struct i2c_board_info i2c0_devices[] = {
         },
 };
 
+static struct i2c_board_info i2c2_devices[] = {
+        {
+                I2C_BOARD_INFO("s35390a", 0x30),
+                .type = "s35390a",
+        },
+};
+
 /*
  * board devices
  */
@@ -906,6 +929,7 @@ static struct platform_device *eva_devices[] __initdata = {
         &fsi_device,
         &fsi_wm8978_device,
         &fsi_hdmi_device,
+        &i2c_gpio_device,
 };
 
 static void __init eva_clock_init(void)
@@ -1176,6 +1200,7 @@ static void __init eva_init(void)
 #endif
 
         i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
+        i2c_register_board_info(2, i2c2_devices, ARRAY_SIZE(i2c2_devices));
 
         r8a7740_add_standard_devices();
 
@@ -1184,10 +1209,10 @@ static void __init eva_init(void)
 
         eva_clock_init();
 
-        rmobile_add_device_to_domain(&r8a7740_pd_a4lc, &lcdc0_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a4lc, &hdmi_lcdc_device);
+        rmobile_add_device_to_domain("A4LC", &lcdc0_device);
+        rmobile_add_device_to_domain("A4LC", &hdmi_lcdc_device);
         if (usb)
-                rmobile_add_device_to_domain(&r8a7740_pd_a3sp, usb);
+                rmobile_add_device_to_domain("A3SP", usb);
 }
 
 static void __init eva_earlytimer_init(void)
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 6525835abc0a..0a43f3189c21 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -346,11 +346,11 @@ static struct resource sh_mmcif_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(141),
+                .start  = gic_spi(140),
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
-                .start  = gic_spi(140),
+                .start  = gic_spi(141),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -482,12 +482,10 @@ static struct gpio_keys_button gpio_buttons[] = {
 static struct gpio_keys_platform_data gpio_key_info = {
         .buttons        = gpio_buttons,
         .nbuttons       = ARRAY_SIZE(gpio_buttons),
-        .poll_interval  = 250, /* poling at this point */
 };
 
 static struct platform_device gpio_keys_device = {
-        /* gpio-pcf857x.c driver doesn't support gpio_to_irq() */
-        .name   = "gpio-keys-polled",
+        .name   = "gpio-keys",
         .dev    = {
                 .platform_data  = &gpio_key_info,
         },
@@ -550,6 +548,7 @@ static struct platform_device fsi_ak4648_device = {
 /* I2C */
 static struct pcf857x_platform_data pcf8575_pdata = {
         .gpio_base      = GPIO_PCF8575_BASE,
+        .irq            = intcs_evt2irq(0x3260), /* IRQ19 */
 };
 
 static struct i2c_board_info i2c0_devices[] = {
@@ -765,7 +764,7 @@ static void __init kzm_init(void)
 
 static void kzm9g_restart(char mode, const char *cmd)
 {
-#define RESCNT2 0xe6188020
+#define RESCNT2 IOMEM(0xe6188020)
         /* Do soft power on reset */
         writel((1 << 31), RESCNT2);
 }
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 62783b5d8813..0c27c810cf99 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1412,6 +1412,22 @@ static struct i2c_board_info i2c1_devices[] = {
 #define USCCR1          IOMEM(0xE6058144)
 static void __init mackerel_init(void)
 {
+        struct pm_domain_device domain_devices[] = {
+                { "A4LC", &lcdc_device, },
+                { "A4LC", &hdmi_lcdc_device, },
+                { "A4LC", &meram_device, },
+                { "A4MP", &fsi_device, },
+                { "A3SP", &usbhs0_device, },
+                { "A3SP", &usbhs1_device, },
+                { "A3SP", &nand_flash_device, },
+                { "A3SP", &sh_mmcif_device, },
+                { "A3SP", &sdhi0_device, },
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
+                { "A3SP", &sdhi1_device, },
+#endif
+                { "A3SP", &sdhi2_device, },
+                { "A4R", &ceu_device, },
+        };
         u32 srcr4;
         struct clk *clk;
 
@@ -1626,20 +1642,8 @@ static void __init mackerel_init(void)
 
         platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
 
-        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &hdmi_lcdc_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &meram_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4mp, &fsi_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usbhs0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usbhs1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &nand_flash_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sh_mmcif_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi0_device);
-#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi1_device);
-#endif
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi2_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &ceu_device);
+        rmobile_add_devices_to_domains(domain_devices,
+                                       ARRAY_SIZE(domain_devices));
 
         hdmi_init_pm_clock();
         sh7372_pm_init();
@@ -1653,6 +1657,6 @@ MACHINE_START(MACKEREL, "mackerel")
         .init_irq       = sh7372_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = mackerel_init,
-        .init_late      = shmobile_init_late,
+        .init_late      = sh7372_pm_init_late,
         .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 01ce3f15c6a3..b8a7525a4e2f 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -30,6 +30,8 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/mfd/tmio.h>
 #include <mach/hardware.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -39,6 +41,12 @@
 #include <asm/hardware/gic.h>
 #include <asm/traps.h>
 
+/* Fixed 3.3V regulator to be used by SDHI0 */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
 /* Dummy supplies, where voltage doesn't matter */
 static struct regulator_consumer_supply dummy_supplies[] = {
         REGULATOR_SUPPLY("vddvario", "smsc911x"),
@@ -75,13 +83,61 @@ static struct platform_device eth_device = {
         .num_resources  = ARRAY_SIZE(smsc911x_resources),
 };
 
+static struct resource sdhi0_resources[] = {
+        [0] = {
+                .name   = "sdhi0",
+                .start  = 0xffe4c000,
+                .end    = 0xffe4c0ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(104),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct sh_mobile_sdhi_info sdhi0_platform_data = {
+        .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
+        .tmio_caps = MMC_CAP_SD_HIGHSPEED,
+};
+
+static struct platform_device sdhi0_device = {
+        .name = "sh_mobile_sdhi",
+        .num_resources = ARRAY_SIZE(sdhi0_resources),
+        .resource = sdhi0_resources,
+        .id = 0,
+        .dev = {
+                .platform_data = &sdhi0_platform_data,
+        }
+};
+
+/* Thermal */
+static struct resource thermal_resources[] = {
+        [0] = {
+                .start          = 0xFFC48000,
+                .end            = 0xFFC48038 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device thermal_device = {
+        .name           = "rcar_thermal",
+        .resource       = thermal_resources,
+        .num_resources  = ARRAY_SIZE(thermal_resources),
+};
+
 static struct platform_device *marzen_devices[] __initdata = {
         &eth_device,
+        &sdhi0_device,
+        &thermal_device,
 };
 
 static void __init marzen_init(void)
 {
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+        regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
+                                ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+        regulator_register_fixed(1, dummy_supplies,
+                                ARRAY_SIZE(dummy_supplies));
 
         r8a7779_pinmux_init();
 
@@ -97,6 +153,16 @@ static void __init marzen_init(void)
         gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
         gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
 
+        /* SD0 (CN20) */
+        gpio_request(GPIO_FN_SD0_CLK, NULL);
+        gpio_request(GPIO_FN_SD0_CMD, NULL);
+        gpio_request(GPIO_FN_SD0_DAT0, NULL);
+        gpio_request(GPIO_FN_SD0_DAT1, NULL);
+        gpio_request(GPIO_FN_SD0_DAT2, NULL);
+        gpio_request(GPIO_FN_SD0_DAT3, NULL);
+        gpio_request(GPIO_FN_SD0_CD, NULL);
+        gpio_request(GPIO_FN_SD0_WP, NULL);
+
         r8a7779_add_standard_devices();
         platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
 }
diff --git a/arch/arm/mach-shmobile/common.c b/arch/arm/mach-shmobile/common.c
deleted file mode 100644
index 608aba9d60d7..000000000000
--- a/arch/arm/mach-shmobile/common.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <mach/common.h>
-
-void __init shmobile_init_late(void)
-{
-        shmobile_suspend_init();
-        shmobile_cpuidle_init();
-}
diff --git a/arch/arm/mach-shmobile/cpuidle.c b/arch/arm/mach-shmobile/cpuidle.c
index 7b541e911ab4..9e050268cde4 100644
--- a/arch/arm/mach-shmobile/cpuidle.c
+++ b/arch/arm/mach-shmobile/cpuidle.c
@@ -16,51 +16,38 @@
 #include <asm/cpuidle.h>
 #include <asm/io.h>
 
-static void shmobile_enter_wfi(void)
+int shmobile_enter_wfi(struct cpuidle_device *dev, struct cpuidle_driver *drv,
+                       int index)
 {
         cpu_do_idle();
-}
-
-void (*shmobile_cpuidle_modes[CPUIDLE_STATE_MAX])(void) = {
-        shmobile_enter_wfi, /* regular sleep mode */
-};
-
-static int shmobile_cpuidle_enter(struct cpuidle_device *dev,
-                                  struct cpuidle_driver *drv,
-                                  int index)
-{
-        shmobile_cpuidle_modes[index]();
-
-        return index;
+        return 0;
 }
 
 static struct cpuidle_device shmobile_cpuidle_dev;
-static struct cpuidle_driver shmobile_cpuidle_driver = {
+static struct cpuidle_driver shmobile_cpuidle_default_driver = {
         .name                   = "shmobile_cpuidle",
         .owner                  = THIS_MODULE,
         .en_core_tk_irqen       = 1,
         .states[0]              = ARM_CPUIDLE_WFI_STATE,
+        .states[0].enter        = shmobile_enter_wfi,
         .safe_state_index       = 0, /* C1 */
         .state_count            = 1,
 };
 
-void (*shmobile_cpuidle_setup)(struct cpuidle_driver *drv);
+static struct cpuidle_driver *cpuidle_drv = &shmobile_cpuidle_default_driver;
+
+void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv)
+{
+        cpuidle_drv = drv;
+}
 
 int shmobile_cpuidle_init(void)
 {
         struct cpuidle_device *dev = &shmobile_cpuidle_dev;
-        struct cpuidle_driver *drv = &shmobile_cpuidle_driver;
-        int i;
-
-        for (i = 0; i < CPUIDLE_STATE_MAX; i++)
-                drv->states[i].enter = shmobile_cpuidle_enter;
-
-        if (shmobile_cpuidle_setup)
-                shmobile_cpuidle_setup(drv);
 
-        cpuidle_register_driver(drv);
+        cpuidle_register_driver(cpuidle_drv);
 
-        dev->state_count = drv->state_count;
+        dev->state_count = cpuidle_drv->state_count;
         cpuidle_register_device(dev);
 
         return 0;
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index f80f9c549393..ed77ab8c9143 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -13,8 +13,10 @@ extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
 extern struct platform_suspend_ops shmobile_suspend_ops;
 struct cpuidle_driver;
-extern void (*shmobile_cpuidle_modes[])(void);
-extern void (*shmobile_cpuidle_setup)(struct cpuidle_driver *drv);
+struct cpuidle_device;
+extern int shmobile_enter_wfi(struct cpuidle_device *dev,
+                              struct cpuidle_driver *drv, int index);
+extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
 
 extern void sh7367_init_irq(void);
 extern void sh7367_map_io(void);
@@ -75,8 +77,6 @@ extern void r8a7740_meram_workaround(void);
 
 extern void r8a7779_register_twd(void);
 
-extern void shmobile_init_late(void);
-
 #ifdef CONFIG_SUSPEND
 int shmobile_suspend_init(void);
 #else
@@ -100,4 +100,10 @@ static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
 
 extern void shmobile_smp_init_cpus(unsigned int ncores);
 
+static inline void shmobile_init_late(void)
+{
+        shmobile_suspend_init();
+        shmobile_cpuidle_init();
+}
+
 #endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/include/mach/pm-rmobile.h b/arch/arm/mach-shmobile/include/mach/pm-rmobile.h
index 5a402840fe28..690553a06887 100644
--- a/arch/arm/mach-shmobile/include/mach/pm-rmobile.h
+++ b/arch/arm/mach-shmobile/include/mach/pm-rmobile.h
@@ -12,6 +12,8 @@
 
 #include <linux/pm_domain.h>
 
+#define DEFAULT_DEV_LATENCY_NS  250000
+
 struct platform_device;
 
 struct rmobile_pm_domain {
@@ -29,16 +31,33 @@ struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d)
         return container_of(d, struct rmobile_pm_domain, genpd);
 }
 
+struct pm_domain_device {
+        const char *domain_name;
+        struct platform_device *pdev;
+};
+
 #ifdef CONFIG_PM
-extern void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd);
-extern void rmobile_add_device_to_domain(struct rmobile_pm_domain *rmobile_pd,
-                                        struct platform_device *pdev);
-extern void rmobile_pm_add_subdomain(struct rmobile_pm_domain *rmobile_pd,
-                                    struct rmobile_pm_domain *rmobile_sd);
+extern void rmobile_init_domains(struct rmobile_pm_domain domains[], int num);
+extern void rmobile_add_device_to_domain_td(const char *domain_name,
+                                            struct platform_device *pdev,
+                                            struct gpd_timing_data *td);
+
+static inline void rmobile_add_device_to_domain(const char *domain_name,
+                                                struct platform_device *pdev)
+{
+        rmobile_add_device_to_domain_td(domain_name, pdev, NULL);
+}
+
+extern void rmobile_add_devices_to_domains(struct pm_domain_device data[],
+                                           int size);
 #else
-#define rmobile_init_pm_domain(pd) do { } while (0)
-#define rmobile_add_device_to_domain(pd, pdev) do { } while (0)
-#define rmobile_pm_add_subdomain(pd, sd) do { } while (0)
+
+#define rmobile_init_domains(domains, num) do { } while (0)
+#define rmobile_add_device_to_domain_td(name, pdev, td) do { } while (0)
+#define rmobile_add_device_to_domain(name, pdev) do { } while (0)
+
+static inline void rmobile_add_devices_to_domains(struct pm_domain_device d[],
+                                                  int size) {}
 #endif /* CONFIG_PM */
 
 #endif /* PM_RMOBILE_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 7143147780df..59d252f4cf97 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -607,9 +607,9 @@ enum {
 };
 
 #ifdef CONFIG_PM
-extern struct rmobile_pm_domain r8a7740_pd_a4s;
-extern struct rmobile_pm_domain r8a7740_pd_a3sp;
-extern struct rmobile_pm_domain r8a7740_pd_a4lc;
+extern void __init r8a7740_init_pm_domains(void);
+#else
+static inline void r8a7740_init_pm_domains(void) {}
 #endif /* CONFIG_PM */
 
 #endif /* __ASM_R8A7740_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index f504c5e81b47..499f52d2a4a1 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -347,17 +347,9 @@ extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
 extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
 
 #ifdef CONFIG_PM
-extern struct r8a7779_pm_domain r8a7779_sh4a;
-extern struct r8a7779_pm_domain r8a7779_sgx;
-extern struct r8a7779_pm_domain r8a7779_vdp1;
-extern struct r8a7779_pm_domain r8a7779_impx3;
-
-extern void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd);
-extern void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
-                                        struct platform_device *pdev);
+extern void __init r8a7779_init_pm_domains(void);
 #else
-#define r8a7779_init_pm_domain(pd) do { } while (0)
-#define r8a7779_add_device_to_domain(pd, pdev) do { } while (0)
+static inline void r8a7779_init_pm_domains(void) {}
 #endif /* CONFIG_PM */
 
 extern struct smp_operations r8a7779_smp_ops;
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index b59048e6d8fd..eb98b45c5089 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -478,21 +478,17 @@ extern struct clk sh7372_fsibck_clk;
 extern struct clk sh7372_fsidiva_clk;
 extern struct clk sh7372_fsidivb_clk;
 
-#ifdef CONFIG_PM
-extern struct rmobile_pm_domain sh7372_pd_a4lc;
-extern struct rmobile_pm_domain sh7372_pd_a4mp;
-extern struct rmobile_pm_domain sh7372_pd_d4;
-extern struct rmobile_pm_domain sh7372_pd_a4r;
-extern struct rmobile_pm_domain sh7372_pd_a3rv;
-extern struct rmobile_pm_domain sh7372_pd_a3ri;
-extern struct rmobile_pm_domain sh7372_pd_a4s;
-extern struct rmobile_pm_domain sh7372_pd_a3sp;
-extern struct rmobile_pm_domain sh7372_pd_a3sg;
-#endif /* CONFIG_PM */
-
 extern void sh7372_intcs_suspend(void);
 extern void sh7372_intcs_resume(void);
 extern void sh7372_intca_suspend(void);
 extern void sh7372_intca_resume(void);
 
+#ifdef CONFIG_PM
+extern void __init sh7372_init_pm_domains(void);
+#else
+static inline void sh7372_init_pm_domains(void) {}
+#endif
+
+extern void __init sh7372_pm_init_late(void);
+
 #endif /* __ASM_SH7372_H__ */
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
index 893504d012a6..21e5316d2d88 100644
--- a/arch/arm/mach-shmobile/pm-r8a7740.c
+++ b/arch/arm/mach-shmobile/pm-r8a7740.c
@@ -21,14 +21,6 @@ static int r8a7740_pd_a4s_suspend(void)
         return -EBUSY;
 }
 
-struct rmobile_pm_domain r8a7740_pd_a4s = {
-        .genpd.name     = "A4S",
-        .bit_shift      = 10,
-        .gov            = &pm_domain_always_on_gov,
-        .no_debug       = true,
-        .suspend        = r8a7740_pd_a4s_suspend,
-};
-
 static int r8a7740_pd_a3sp_suspend(void)
 {
         /*
@@ -38,17 +30,31 @@ static int r8a7740_pd_a3sp_suspend(void)
         return console_suspend_enabled ? 0 : -EBUSY;
 }
 
-struct rmobile_pm_domain r8a7740_pd_a3sp = {
-        .genpd.name     = "A3SP",
-        .bit_shift      = 11,
-        .gov            = &pm_domain_always_on_gov,
-        .no_debug       = true,
-        .suspend        = r8a7740_pd_a3sp_suspend,
+static struct rmobile_pm_domain r8a7740_pm_domains[] = {
+        {
+                .genpd.name     = "A4S",
+                .bit_shift      = 10,
+                .gov            = &pm_domain_always_on_gov,
+                .no_debug       = true,
+                .suspend        = r8a7740_pd_a4s_suspend,
+        },
+        {
+                .genpd.name     = "A3SP",
+                .bit_shift      = 11,
+                .gov            = &pm_domain_always_on_gov,
+                .no_debug       = true,
+                .suspend        = r8a7740_pd_a3sp_suspend,
+        },
+        {
+                .genpd.name     = "A4LC",
+                .bit_shift      = 1,
+        },
 };
 
-struct rmobile_pm_domain r8a7740_pd_a4lc = {
-        .genpd.name     = "A4LC",
-        .bit_shift      = 1,
-};
+void __init r8a7740_init_pm_domains(void)
+{
+        rmobile_init_domains(r8a7740_pm_domains, ARRAY_SIZE(r8a7740_pm_domains));
+        pm_genpd_add_subdomain_names("A4S", "A3SP");
+}
 
 #endif /* CONFIG_PM */
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
index a18a4ae16d2b..d50a8e9b94a4 100644
--- a/arch/arm/mach-shmobile/pm-r8a7779.c
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -183,7 +183,7 @@ static bool pd_active_wakeup(struct device *dev)
         return true;
 }
 
-void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
+static void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
 {
         struct generic_pm_domain *genpd = &r8a7779_pd->genpd;
 
@@ -199,43 +199,44 @@ void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
                 pd_power_up(&r8a7779_pd->genpd);
 }
 
-void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
-                                 struct platform_device *pdev)
-{
-        struct device *dev = &pdev->dev;
-
-        pm_genpd_add_device(&r8a7779_pd->genpd, dev);
-        if (pm_clk_no_clocks(dev))
-                pm_clk_add(dev, NULL);
-}
-
-struct r8a7779_pm_domain r8a7779_sh4a = {
-        .ch = {
-                .chan_offs = 0x80, /* PWRSR1 .. PWRER1 */
-                .isr_bit = 16, /* SH4A */
-        }
-};
-
-struct r8a7779_pm_domain r8a7779_sgx = {
-        .ch = {
-                .chan_offs = 0xc0, /* PWRSR2 .. PWRER2 */
-                .isr_bit = 20, /* SGX */
-        }
+static struct r8a7779_pm_domain r8a7779_pm_domains[] = {
+        {
+                .genpd.name = "SH4A",
+                .ch = {
+                        .chan_offs = 0x80, /* PWRSR1 .. PWRER1 */
+                        .isr_bit = 16, /* SH4A */
+                },
+        },
+        {
+                .genpd.name = "SGX",
+                .ch = {
+                        .chan_offs = 0xc0, /* PWRSR2 .. PWRER2 */
+                        .isr_bit = 20, /* SGX */
+                },
+        },
+        {
+                .genpd.name = "VDP1",
+                .ch = {
+                        .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */
+                        .isr_bit = 21, /* VDP */
+                },
+        },
+        {
+                .genpd.name = "IMPX3",
+                .ch = {
+                        .chan_offs = 0x140, /* PWRSR4 .. PWRER4 */
+                        .isr_bit = 24, /* IMP */
+                },
+        },
 };
 
-struct r8a7779_pm_domain r8a7779_vdp1 = {
-        .ch = {
-                .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */
-                .isr_bit = 21, /* VDP */
-        }
-};
+void __init r8a7779_init_pm_domains(void)
+{
+        int j;
 
-struct r8a7779_pm_domain r8a7779_impx3 = {
-        .ch = {
-                .chan_offs = 0x140, /* PWRSR4 .. PWRER4 */
-                .isr_bit = 24, /* IMP */
-        }
-};
+        for (j = 0; j < ARRAY_SIZE(r8a7779_pm_domains); j++)
+                r8a7779_init_pm_domain(&r8a7779_pm_domains[j]);
+}
 
 #endif /* CONFIG_PM */
 
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index 32e177275e47..1fc05d9453d0 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -134,7 +134,7 @@ static int rmobile_pd_start_dev(struct device *dev)
         return ret;
 }
 
-void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
+static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
 {
         struct generic_pm_domain *genpd = &rmobile_pd->genpd;
         struct dev_power_governor *gov = rmobile_pd->gov;
@@ -149,19 +149,38 @@ void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
         __rmobile_pd_power_up(rmobile_pd, false);
 }
 
-void rmobile_add_device_to_domain(struct rmobile_pm_domain *rmobile_pd,
-                                 struct platform_device *pdev)
+void rmobile_init_domains(struct rmobile_pm_domain domains[], int num)
+{
+        int j;
+
+        for (j = 0; j < num; j++)
+                rmobile_init_pm_domain(&domains[j]);
+}
+
+void rmobile_add_device_to_domain_td(const char *domain_name,
+                                     struct platform_device *pdev,
+                                     struct gpd_timing_data *td)
 {
         struct device *dev = &pdev->dev;
 
-        pm_genpd_add_device(&rmobile_pd->genpd, dev);
+        __pm_genpd_name_add_device(domain_name, dev, td);
         if (pm_clk_no_clocks(dev))
                 pm_clk_add(dev, NULL);
 }
 
-void rmobile_pm_add_subdomain(struct rmobile_pm_domain *rmobile_pd,
-                             struct rmobile_pm_domain *rmobile_sd)
+void rmobile_add_devices_to_domains(struct pm_domain_device data[],
+                                    int size)
 {
-        pm_genpd_add_subdomain(&rmobile_pd->genpd, &rmobile_sd->genpd);
+        struct gpd_timing_data latencies = {
+                .stop_latency_ns = DEFAULT_DEV_LATENCY_NS,
+                .start_latency_ns = DEFAULT_DEV_LATENCY_NS,
+                .save_state_latency_ns = DEFAULT_DEV_LATENCY_NS,
+                .restore_state_latency_ns = DEFAULT_DEV_LATENCY_NS,
+        };
+        int j;
+
+        for (j = 0; j < size; j++)
+                rmobile_add_device_to_domain_td(data[j].domain_name,
+                                                data[j].pdev, &latencies);
 }
 #endif /* CONFIG_PM */
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index 162121842a2b..a0826a48dd08 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -21,6 +21,7 @@
 #include <linux/irq.h>
 #include <linux/bitrev.h>
 #include <linux/console.h>
+#include <asm/cpuidle.h>
 #include <asm/io.h>
 #include <asm/tlbflush.h>
 #include <asm/suspend.h>
@@ -72,20 +73,7 @@
 
 #ifdef CONFIG_PM
 
-struct rmobile_pm_domain sh7372_pd_a4lc = {
-        .genpd.name = "A4LC",
-        .bit_shift = 1,
-};
-
-struct rmobile_pm_domain sh7372_pd_a4mp = {
-        .genpd.name = "A4MP",
-        .bit_shift = 2,
-};
-
-struct rmobile_pm_domain sh7372_pd_d4 = {
-        .genpd.name = "D4",
-        .bit_shift = 3,
-};
+#define PM_DOMAIN_ON_OFF_LATENCY_NS     250000
 
 static int sh7372_a4r_pd_suspend(void)
 {
@@ -94,39 +82,25 @@ static int sh7372_a4r_pd_suspend(void)
         return 0;
 }
 
-struct rmobile_pm_domain sh7372_pd_a4r = {
-        .genpd.name = "A4R",
-        .bit_shift = 5,
-        .suspend = sh7372_a4r_pd_suspend,
-        .resume = sh7372_intcs_resume,
-};
+static bool a4s_suspend_ready;
 
-struct rmobile_pm_domain sh7372_pd_a3rv = {
-        .genpd.name = "A3RV",
-        .bit_shift = 6,
-};
-
-struct rmobile_pm_domain sh7372_pd_a3ri = {
-        .genpd.name = "A3RI",
-        .bit_shift = 8,
-};
-
-static int sh7372_pd_a4s_suspend(void)
+static int sh7372_a4s_pd_suspend(void)
 {
         /*
          * The A4S domain contains the CPU core and therefore it should
-         * only be turned off if the CPU is in use.
+         * only be turned off if the CPU is not in use.  This may happen
+         * during system suspend, when SYSC is going to be used for generating
+         * resume signals and a4s_suspend_ready is set to let
+         * sh7372_enter_suspend() know that it can turn A4S off.
          */
+        a4s_suspend_ready = true;
         return -EBUSY;
 }
 
-struct rmobile_pm_domain sh7372_pd_a4s = {
-        .genpd.name = "A4S",
-        .bit_shift = 10,
-        .gov = &pm_domain_always_on_gov,
-        .no_debug = true,
-        .suspend = sh7372_pd_a4s_suspend,
-};
+static void sh7372_a4s_pd_resume(void)
+{
+        a4s_suspend_ready = false;
+}
 
 static int sh7372_a3sp_pd_suspend(void)
 {
@@ -137,18 +111,80 @@ static int sh7372_a3sp_pd_suspend(void)
         return console_suspend_enabled ? 0 : -EBUSY;
 }
 
-struct rmobile_pm_domain sh7372_pd_a3sp = {
-        .genpd.name = "A3SP",
-        .bit_shift = 11,
-        .gov = &pm_domain_always_on_gov,
-        .no_debug = true,
-        .suspend = sh7372_a3sp_pd_suspend,
+static struct rmobile_pm_domain sh7372_pm_domains[] = {
+        {
+                .genpd.name = "A4LC",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 1,
+        },
+        {
+                .genpd.name = "A4MP",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 2,
+        },
+        {
+                .genpd.name = "D4",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 3,
+        },
+        {
+                .genpd.name = "A4R",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 5,
+                .suspend = sh7372_a4r_pd_suspend,
+                .resume = sh7372_intcs_resume,
+        },
+        {
+                .genpd.name = "A3RV",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 6,
+        },
+        {
+                .genpd.name = "A3RI",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 8,
+        },
+        {
+                .genpd.name = "A4S",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 10,
+                .gov = &pm_domain_always_on_gov,
+                .no_debug = true,
+                .suspend = sh7372_a4s_pd_suspend,
+                .resume = sh7372_a4s_pd_resume,
+        },
+        {
+                .genpd.name = "A3SP",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 11,
+                .gov = &pm_domain_always_on_gov,
+                .no_debug = true,
+                .suspend = sh7372_a3sp_pd_suspend,
+        },
+        {
+                .genpd.name = "A3SG",
+                .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
+                .bit_shift = 13,
+        },
 };
 
-struct rmobile_pm_domain sh7372_pd_a3sg = {
-        .genpd.name = "A3SG",
-        .bit_shift = 13,
-};
+void __init sh7372_init_pm_domains(void)
+{
+        rmobile_init_domains(sh7372_pm_domains, ARRAY_SIZE(sh7372_pm_domains));
+        pm_genpd_add_subdomain_names("A4LC", "A3RV");
+        pm_genpd_add_subdomain_names("A4R", "A4LC");
+        pm_genpd_add_subdomain_names("A4S", "A3SG");
+        pm_genpd_add_subdomain_names("A4S", "A3SP");
+}
 
 #endif /* CONFIG_PM */
 
@@ -304,6 +340,21 @@ static void sh7372_enter_a3sm_common(int pllc0_on)
         sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
         sh7372_enter_sysc(pllc0_on, 1 << 12);
 }
+
+static void sh7372_enter_a4s_common(int pllc0_on)
+{
+        sh7372_intca_suspend();
+        sh7372_set_reset_vector(SMFRAM);
+        sh7372_enter_sysc(pllc0_on, 1 << 10);
+        sh7372_intca_resume();
+}
+
+static void sh7372_pm_setup_smfram(void)
+{
+        memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
+}
+#else
+static inline void sh7372_pm_setup_smfram(void) {}
 #endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */
 
 #ifdef CONFIG_CPU_IDLE
@@ -313,7 +364,8 @@ static int sh7372_do_idle_core_standby(unsigned long unused)
         return 0;
 }
 
-static void sh7372_enter_core_standby(void)
+static int sh7372_enter_core_standby(struct cpuidle_device *dev,
+                                     struct cpuidle_driver *drv, int index)
 {
         sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
 
@@ -324,83 +376,102 @@ static void sh7372_enter_core_standby(void)
 
          /* disable reset vector translation */
         __raw_writel(0, SBAR);
+
+        return 1;
 }
 
-static void sh7372_enter_a3sm_pll_on(void)
+static int sh7372_enter_a3sm_pll_on(struct cpuidle_device *dev,
+                                    struct cpuidle_driver *drv, int index)
 {
         sh7372_enter_a3sm_common(1);
+        return 2;
 }
 
-static void sh7372_enter_a3sm_pll_off(void)
+static int sh7372_enter_a3sm_pll_off(struct cpuidle_device *dev,
+                                     struct cpuidle_driver *drv, int index)
 {
         sh7372_enter_a3sm_common(0);
+        return 3;
 }
 
-static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
+static int sh7372_enter_a4s(struct cpuidle_device *dev,
+                            struct cpuidle_driver *drv, int index)
 {
-        struct cpuidle_state *state = &drv->states[drv->state_count];
-
-        snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
-        strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
-        state->exit_latency = 10;
-        state->target_residency = 20 + 10;
-        state->flags = CPUIDLE_FLAG_TIME_VALID;
-        shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby;
-        drv->state_count++;
-
-        state = &drv->states[drv->state_count];
-        snprintf(state->name, CPUIDLE_NAME_LEN, "C3");
-        strncpy(state->desc, "A3SM PLL ON", CPUIDLE_DESC_LEN);
-        state->exit_latency = 20;
-        state->target_residency = 30 + 20;
-        state->flags = CPUIDLE_FLAG_TIME_VALID;
-        shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_on;
-        drv->state_count++;
-
-        state = &drv->states[drv->state_count];
-        snprintf(state->name, CPUIDLE_NAME_LEN, "C4");
-        strncpy(state->desc, "A3SM PLL OFF", CPUIDLE_DESC_LEN);
-        state->exit_latency = 120;
-        state->target_residency = 30 + 120;
-        state->flags = CPUIDLE_FLAG_TIME_VALID;
-        shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_off;
-        drv->state_count++;
+        unsigned long msk, msk2;
+
+        if (!sh7372_sysc_valid(&msk, &msk2))
+                return sh7372_enter_a3sm_pll_off(dev, drv, index);
+
+        sh7372_setup_sysc(msk, msk2);
+        sh7372_enter_a4s_common(0);
+        return 4;
 }
 
+static struct cpuidle_driver sh7372_cpuidle_driver = {
+        .name                   = "sh7372_cpuidle",
+        .owner                  = THIS_MODULE,
+        .en_core_tk_irqen       = 1,
+        .state_count            = 5,
+        .safe_state_index       = 0, /* C1 */
+        .states[0] = ARM_CPUIDLE_WFI_STATE,
+        .states[0].enter = shmobile_enter_wfi,
+        .states[1] = {
+                .name = "C2",
+                .desc = "Core Standby Mode",
+                .exit_latency = 10,
+                .target_residency = 20 + 10,
+                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .enter = sh7372_enter_core_standby,
+        },
+        .states[2] = {
+                .name = "C3",
+                .desc = "A3SM PLL ON",
+                .exit_latency = 20,
+                .target_residency = 30 + 20,
+                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .enter = sh7372_enter_a3sm_pll_on,
+        },
+        .states[3] = {
+                .name = "C4",
+                .desc = "A3SM PLL OFF",
+                .exit_latency = 120,
+                .target_residency = 30 + 120,
+                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .enter = sh7372_enter_a3sm_pll_off,
+        },
+        .states[4] = {
+                .name = "C5",
+                .desc = "A4S PLL OFF",
+                .exit_latency = 240,
+                .target_residency = 30 + 240,
+                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .enter = sh7372_enter_a4s,
+                .disabled = true,
+        },
+};
+
 static void sh7372_cpuidle_init(void)
 {
-        shmobile_cpuidle_setup = sh7372_cpuidle_setup;
+        shmobile_cpuidle_set_driver(&sh7372_cpuidle_driver);
 }
 #else
 static void sh7372_cpuidle_init(void) {}
 #endif
 
 #ifdef CONFIG_SUSPEND
-static void sh7372_enter_a4s_common(int pllc0_on)
-{
-        sh7372_intca_suspend();
-        memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
-        sh7372_set_reset_vector(SMFRAM);
-        sh7372_enter_sysc(pllc0_on, 1 << 10);
-        sh7372_intca_resume();
-}
-
 static int sh7372_enter_suspend(suspend_state_t suspend_state)
 {
         unsigned long msk, msk2;
 
         /* check active clocks to determine potential wakeup sources */
-        if (sh7372_sysc_valid(&msk, &msk2)) {
-                if (!console_suspend_enabled &&
-                    sh7372_pd_a4s.genpd.status == GPD_STATE_POWER_OFF) {
-                        /* convert INTC mask/sense to SYSC mask/sense */
-                        sh7372_setup_sysc(msk, msk2);
-
-                        /* enter A4S sleep with PLLC0 off */
-                        pr_debug("entering A4S\n");
-                        sh7372_enter_a4s_common(0);
-                        return 0;
-                }
+        if (sh7372_sysc_valid(&msk, &msk2) && a4s_suspend_ready) {
+                /* convert INTC mask/sense to SYSC mask/sense */
+                sh7372_setup_sysc(msk, msk2);
+
+                /* enter A4S sleep with PLLC0 off */
+                pr_debug("entering A4S\n");
+                sh7372_enter_a4s_common(0);
+                return 0;
         }
 
         /* default to enter A3SM sleep with PLLC0 off */
@@ -426,7 +497,7 @@ static int sh7372_pm_notifier_fn(struct notifier_block *notifier,
                  * executed during system suspend and resume, respectively, so
                  * that those functions don't crash while accessing the INTCS.
                  */
-                pm_genpd_poweron(&sh7372_pd_a4r.genpd);
+                pm_genpd_name_poweron("A4R");
                 break;
         case PM_POST_SUSPEND:
                 pm_genpd_poweroff_unused();
@@ -455,6 +526,14 @@ void __init sh7372_pm_init(void)
         /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
         __raw_writel(0, PDNSEL);
 
+        sh7372_pm_setup_smfram();
+
         sh7372_suspend_init();
         sh7372_cpuidle_init();
 }
+
+void __init sh7372_pm_init_late(void)
+{
+        shmobile_init_late();
+        pm_genpd_name_attach_cpuidle("A4S", 4);
+}
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 78948a9dba0e..11bb1d984197 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -673,12 +673,7 @@ void __init r8a7740_add_standard_devices(void)
         r8a7740_i2c_workaround(&i2c0_device);
         r8a7740_i2c_workaround(&i2c1_device);
 
-        /* PM domain */
-        rmobile_init_pm_domain(&r8a7740_pd_a4s);
-        rmobile_init_pm_domain(&r8a7740_pd_a3sp);
-        rmobile_init_pm_domain(&r8a7740_pd_a4lc);
-
-        rmobile_pm_add_subdomain(&r8a7740_pd_a4s, &r8a7740_pd_a3sp);
+        r8a7740_init_pm_domains();
 
         /* add devices */
         platform_add_devices(r8a7740_early_devices,
@@ -688,16 +683,16 @@ void __init r8a7740_add_standard_devices(void)
 
         /* add devices to PM domain  */
 
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif0_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif1_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif2_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif3_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif4_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif5_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif6_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif7_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scifb_device);
-        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &i2c1_device);
+        rmobile_add_device_to_domain("A3SP",    &scif0_device);
+        rmobile_add_device_to_domain("A3SP",    &scif1_device);
+        rmobile_add_device_to_domain("A3SP",    &scif2_device);
+        rmobile_add_device_to_domain("A3SP",    &scif3_device);
+        rmobile_add_device_to_domain("A3SP",    &scif4_device);
+        rmobile_add_device_to_domain("A3SP",    &scif5_device);
+        rmobile_add_device_to_domain("A3SP",    &scif6_device);
+        rmobile_add_device_to_domain("A3SP",    &scif7_device);
+        rmobile_add_device_to_domain("A3SP",    &scifb_device);
+        rmobile_add_device_to_domain("A3SP",    &i2c1_device);
 }
 
 static void __init r8a7740_earlytimer_init(void)
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index e98e46f6cf55..2917668f0091 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -251,10 +251,7 @@ void __init r8a7779_add_standard_devices(void)
 #endif
         r8a7779_pm_init();
 
-        r8a7779_init_pm_domain(&r8a7779_sh4a);
-        r8a7779_init_pm_domain(&r8a7779_sgx);
-        r8a7779_init_pm_domain(&r8a7779_vdp1);
-        r8a7779_init_pm_domain(&r8a7779_impx3);
+        r8a7779_init_pm_domains();
 
         platform_add_devices(r8a7779_early_devices,
                             ARRAY_SIZE(r8a7779_early_devices));
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 838a87be1d5c..a07954fbcd22 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -1001,21 +1001,34 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
 
 void __init sh7372_add_standard_devices(void)
 {
-        rmobile_init_pm_domain(&sh7372_pd_a4lc);
-        rmobile_init_pm_domain(&sh7372_pd_a4mp);
-        rmobile_init_pm_domain(&sh7372_pd_d4);
-        rmobile_init_pm_domain(&sh7372_pd_a4r);
-        rmobile_init_pm_domain(&sh7372_pd_a3rv);
-        rmobile_init_pm_domain(&sh7372_pd_a3ri);
-        rmobile_init_pm_domain(&sh7372_pd_a4s);
-        rmobile_init_pm_domain(&sh7372_pd_a3sp);
-        rmobile_init_pm_domain(&sh7372_pd_a3sg);
-
-        rmobile_pm_add_subdomain(&sh7372_pd_a4lc, &sh7372_pd_a3rv);
-        rmobile_pm_add_subdomain(&sh7372_pd_a4r, &sh7372_pd_a4lc);
-
-        rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sg);
-        rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sp);
+        struct pm_domain_device domain_devices[] = {
+                { "A3RV", &vpu_device, },
+                { "A4MP", &spu0_device, },
+                { "A4MP", &spu1_device, },
+                { "A3SP", &scif0_device, },
+                { "A3SP", &scif1_device, },
+                { "A3SP", &scif2_device, },
+                { "A3SP", &scif3_device, },
+                { "A3SP", &scif4_device, },
+                { "A3SP", &scif5_device, },
+                { "A3SP", &scif6_device, },
+                { "A3SP", &iic1_device, },
+                { "A3SP", &dma0_device, },
+                { "A3SP", &dma1_device, },
+                { "A3SP", &dma2_device, },
+                { "A3SP", &usb_dma0_device, },
+                { "A3SP", &usb_dma1_device, },
+                { "A4R", &iic0_device, },
+                { "A4R", &veu0_device, },
+                { "A4R", &veu1_device, },
+                { "A4R", &veu2_device, },
+                { "A4R", &veu3_device, },
+                { "A4R", &jpu_device, },
+                { "A4R", &tmu00_device, },
+                { "A4R", &tmu01_device, },
+        };
+
+        sh7372_init_pm_domains();
 
         platform_add_devices(sh7372_early_devices,
                             ARRAY_SIZE(sh7372_early_devices));
@@ -1023,30 +1036,8 @@ void __init sh7372_add_standard_devices(void)
         platform_add_devices(sh7372_late_devices,
                             ARRAY_SIZE(sh7372_late_devices));
 
-        rmobile_add_device_to_domain(&sh7372_pd_a3rv, &vpu_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif2_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif3_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif4_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif5_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif6_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &iic1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma2_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &iic0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu0_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu1_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu2_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu3_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &jpu_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu00_device);
-        rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu01_device);
+        rmobile_add_devices_to_domains(domain_devices,
+                                       ARRAY_SIZE(domain_devices));
 }
 
 static void __init sh7372_earlytimer_init(void)
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 04eb74e3f601..9aa653b3eb32 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,6 +1,4 @@
-obj-y                                   += board-pinmux.o
 obj-y                                   += common.o
-obj-y                                   += devices.o
 obj-y                                   += io.o
 obj-y                                   += irq.o
 obj-y                                   += clock.o
@@ -24,7 +22,6 @@ obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
-obj-$(CONFIG_USB_SUPPORT)               += usb_phy.o
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-dt-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 5d8c8fb060b0..57e235f4ac74 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -28,9 +28,11 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/pda_power.h>
+#include <linux/platform_data/tegra_usb.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/i2c-tegra.h>
+#include <linux/usb/tegra_usb_phy.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
@@ -43,9 +45,32 @@
 
 #include "board.h"
 #include "clock.h"
-#include "devices.h"
 #include "common.h"
 
+struct tegra_ehci_platform_data tegra_ehci1_pdata = {
+        .operating_mode = TEGRA_USB_OTG,
+        .power_down_on_bus_suspend = 1,
+        .vbus_gpio = -1,
+};
+
+struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
+        .reset_gpio = -1,
+        .clk = "cdev2",
+};
+
+struct tegra_ehci_platform_data tegra_ehci2_pdata = {
+        .phy_config = &tegra_ehci2_ulpi_phy_config,
+        .operating_mode = TEGRA_USB_HOST,
+        .power_down_on_bus_suspend = 1,
+        .vbus_gpio = -1,
+};
+
+struct tegra_ehci_platform_data tegra_ehci3_pdata = {
+        .operating_mode = TEGRA_USB_HOST,
+        .power_down_on_bus_suspend = 1,
+        .vbus_gpio = -1,
+};
+
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
deleted file mode 100644
index a5574c71b931..000000000000
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (c) 2011,2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/device.h>
-#include <linux/kernel.h>
-#include <linux/notifier.h>
-#include <linux/string.h>
-
-#include "board-pinmux.h"
-#include "devices.h"
-
-unsigned long tegra_pincfg_pullnone_driven[2] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-};
-
-unsigned long tegra_pincfg_pullnone_tristate[2] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
-};
-
-unsigned long tegra_pincfg_pullnone_na[1] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
-};
-
-unsigned long tegra_pincfg_pullup_driven[2] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-};
-
-unsigned long tegra_pincfg_pullup_tristate[2] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
-};
-
-unsigned long tegra_pincfg_pullup_na[1] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
-};
-
-unsigned long tegra_pincfg_pulldown_driven[2] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-};
-
-unsigned long tegra_pincfg_pulldown_tristate[2] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
-};
-
-unsigned long tegra_pincfg_pulldown_na[1] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
-};
-
-unsigned long tegra_pincfg_pullna_driven[1] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-};
-
-unsigned long tegra_pincfg_pullna_tristate[1] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
-};
-
-static struct platform_device *devices[] = {
-        &tegra_gpio_device,
-        &tegra_pinmux_device,
-};
-
-void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
-                             struct tegra_board_pinmux_conf *conf_b)
-{
-        if (conf_a)
-                pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
-        if (conf_b)
-                pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
-
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-}
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
deleted file mode 100644
index c5f3f3381e86..000000000000
--- a/arch/arm/mach-tegra/board-pinmux.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2011,2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_BOARD_PINMUX_H
-#define __MACH_TEGRA_BOARD_PINMUX_H
-
-#include <linux/pinctrl/machine.h>
-
-#include <mach/pinconf-tegra.h>
-
-#define PINMUX_DEV "tegra20-pinctrl"
-
-#define TEGRA_MAP_MUX(_group_, _function_) \
-        PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
-
-#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
-        PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
-
-#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
-        TEGRA_MAP_MUX(_group_, _function_), \
-        TEGRA_MAP_CONF(_group_, _pull_, _drive_)
-
-extern unsigned long tegra_pincfg_pullnone_driven[2];
-extern unsigned long tegra_pincfg_pullnone_tristate[2];
-extern unsigned long tegra_pincfg_pullnone_na[1];
-extern unsigned long tegra_pincfg_pullup_driven[2];
-extern unsigned long tegra_pincfg_pullup_tristate[2];
-extern unsigned long tegra_pincfg_pullup_na[1];
-extern unsigned long tegra_pincfg_pulldown_driven[2];
-extern unsigned long tegra_pincfg_pulldown_tristate[2];
-extern unsigned long tegra_pincfg_pulldown_na[1];
-extern unsigned long tegra_pincfg_pullna_driven[1];
-extern unsigned long tegra_pincfg_pullna_tristate[1];
-
-struct tegra_board_pinmux_conf {
-        struct pinctrl_map *maps;
-        int map_count;
-};
-
-void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
-                             struct tegra_board_pinmux_conf *conf_b);
-
-#endif
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
deleted file mode 100644
index 61e9603744a7..000000000000
--- a/arch/arm/mach-tegra/devices.c
+++ /dev/null
@@ -1,701 +0,0 @@
-/*
- * Copyright (C) 2010,2011 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@android.com>
- *      Erik Gilling <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-
-#include <linux/resource.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/fsl_devices.h>
-#include <linux/serial_8250.h>
-#include <linux/i2c-tegra.h>
-#include <mach/irqs.h>
-#include <mach/iomap.h>
-#include <mach/dma.h>
-#include <mach/usb_phy.h>
-
-#include "gpio-names.h"
-#include "devices.h"
-
-static struct resource gpio_resource[] = {
-        [0] = {
-                .start  = TEGRA_GPIO_BASE,
-                .end    = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_GPIO1,
-                .end    = INT_GPIO1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = INT_GPIO2,
-                .end    = INT_GPIO2,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = INT_GPIO3,
-                .end    = INT_GPIO3,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [4] = {
-                .start  = INT_GPIO4,
-                .end    = INT_GPIO4,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [5] = {
-                .start  = INT_GPIO5,
-                .end    = INT_GPIO5,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [6] = {
-                .start  = INT_GPIO6,
-                .end    = INT_GPIO6,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [7] = {
-                .start  = INT_GPIO7,
-                .end    = INT_GPIO7,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device tegra_gpio_device = {
-        .name           = "tegra-gpio",
-        .id             = -1,
-        .resource       = gpio_resource,
-        .num_resources  = ARRAY_SIZE(gpio_resource),
-};
-
-static struct resource pinmux_resource[] = {
-        [0] = {
-                /* Tri-state registers */
-                .start  = TEGRA_APB_MISC_BASE + 0x14,
-                .end    = TEGRA_APB_MISC_BASE + 0x20 + 3,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                /* Mux registers */
-                .start  = TEGRA_APB_MISC_BASE + 0x80,
-                .end    = TEGRA_APB_MISC_BASE + 0x9c + 3,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                /* Pull-up/down registers */
-                .start  = TEGRA_APB_MISC_BASE + 0xa0,
-                .end    = TEGRA_APB_MISC_BASE + 0xb0 + 3,
-                .flags  = IORESOURCE_MEM,
-        },
-        [3] = {
-                /* Pad control registers */
-                .start  = TEGRA_APB_MISC_BASE + 0x868,
-                .end    = TEGRA_APB_MISC_BASE + 0x90c + 3,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device tegra_pinmux_device = {
-        .name           = "tegra20-pinctrl",
-        .id             = -1,
-        .resource       = pinmux_resource,
-        .num_resources  = ARRAY_SIZE(pinmux_resource),
-};
-
-static struct resource i2c_resource1[] = {
-        [0] = {
-                .start  = INT_I2C,
-                .end    = INT_I2C,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_I2C_BASE,
-                .end    = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct resource i2c_resource2[] = {
-        [0] = {
-                .start  = INT_I2C2,
-                .end    = INT_I2C2,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_I2C2_BASE,
-                .end    = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct resource i2c_resource3[] = {
-        [0] = {
-                .start  = INT_I2C3,
-                .end    = INT_I2C3,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_I2C3_BASE,
-                .end    = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct resource i2c_resource4[] = {
-        [0] = {
-                .start  = INT_DVC,
-                .end    = INT_DVC,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_DVC_BASE,
-                .end    = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-
-static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-
-static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-
-static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
-        .bus_clk_rate   = 400000,
-};
-
-struct platform_device tegra_i2c_device1 = {
-        .name           = "tegra-i2c",
-        .id             = 0,
-        .resource       = i2c_resource1,
-        .num_resources  = ARRAY_SIZE(i2c_resource1),
-        .dev = {
-                .platform_data = &tegra_i2c1_platform_data,
-        },
-};
-
-struct platform_device tegra_i2c_device2 = {
-        .name           = "tegra-i2c",
-        .id             = 1,
-        .resource       = i2c_resource2,
-        .num_resources  = ARRAY_SIZE(i2c_resource2),
-        .dev = {
-                .platform_data = &tegra_i2c2_platform_data,
-        },
-};
-
-struct platform_device tegra_i2c_device3 = {
-        .name           = "tegra-i2c",
-        .id             = 2,
-        .resource       = i2c_resource3,
-        .num_resources  = ARRAY_SIZE(i2c_resource3),
-        .dev = {
-                .platform_data = &tegra_i2c3_platform_data,
-        },
-};
-
-struct platform_device tegra_i2c_device4 = {
-        .name           = "tegra-i2c",
-        .id             = 3,
-        .resource       = i2c_resource4,
-        .num_resources  = ARRAY_SIZE(i2c_resource4),
-        .dev = {
-                .platform_data = &tegra_dvc_platform_data,
-        },
-};
-
-static struct resource spi_resource1[] = {
-        [0] = {
-                .start  = INT_S_LINK1,
-                .end    = INT_S_LINK1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SPI1_BASE,
-                .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct resource spi_resource2[] = {
-        [0] = {
-                .start  = INT_SPI_2,
-                .end    = INT_SPI_2,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SPI2_BASE,
-                .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct resource spi_resource3[] = {
-        [0] = {
-                .start  = INT_SPI_3,
-                .end    = INT_SPI_3,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SPI3_BASE,
-                .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct resource spi_resource4[] = {
-        [0] = {
-                .start  = INT_SPI_4,
-                .end    = INT_SPI_4,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SPI4_BASE,
-                .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device tegra_spi_device1 = {
-        .name           = "spi_tegra",
-        .id             = 0,
-        .resource       = spi_resource1,
-        .num_resources  = ARRAY_SIZE(spi_resource1),
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
-struct platform_device tegra_spi_device2 = {
-        .name           = "spi_tegra",
-        .id             = 1,
-        .resource       = spi_resource2,
-        .num_resources  = ARRAY_SIZE(spi_resource2),
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
-struct platform_device tegra_spi_device3 = {
-        .name           = "spi_tegra",
-        .id             = 2,
-        .resource       = spi_resource3,
-        .num_resources  = ARRAY_SIZE(spi_resource3),
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
-struct platform_device tegra_spi_device4 = {
-        .name           = "spi_tegra",
-        .id             = 3,
-        .resource       = spi_resource4,
-        .num_resources  = ARRAY_SIZE(spi_resource4),
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
-
-static struct resource sdhci_resource1[] = {
-        [0] = {
-                .start  = INT_SDMMC1,
-                .end    = INT_SDMMC1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SDMMC1_BASE,
-                .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct resource sdhci_resource2[] = {
-        [0] = {
-                .start  = INT_SDMMC2,
-                .end    = INT_SDMMC2,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SDMMC2_BASE,
-                .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct resource sdhci_resource3[] = {
-        [0] = {
-                .start  = INT_SDMMC3,
-                .end    = INT_SDMMC3,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SDMMC3_BASE,
-                .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct resource sdhci_resource4[] = {
-        [0] = {
-                .start  = INT_SDMMC4,
-                .end    = INT_SDMMC4,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = TEGRA_SDMMC4_BASE,
-                .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-/* board files should fill in platform_data register the devices themselvs.
- * See board-harmony.c for an example
- */
-struct platform_device tegra_sdhci_device1 = {
-        .name           = "sdhci-tegra",
-        .id             = 0,
-        .resource       = sdhci_resource1,
-        .num_resources  = ARRAY_SIZE(sdhci_resource1),
-};
-
-struct platform_device tegra_sdhci_device2 = {
-        .name           = "sdhci-tegra",
-        .id             = 1,
-        .resource       = sdhci_resource2,
-        .num_resources  = ARRAY_SIZE(sdhci_resource2),
-};
-
-struct platform_device tegra_sdhci_device3 = {
-        .name           = "sdhci-tegra",
-        .id             = 2,
-        .resource       = sdhci_resource3,
-        .num_resources  = ARRAY_SIZE(sdhci_resource3),
-};
-
-struct platform_device tegra_sdhci_device4 = {
-        .name           = "sdhci-tegra",
-        .id             = 3,
-        .resource       = sdhci_resource4,
-        .num_resources  = ARRAY_SIZE(sdhci_resource4),
-};
-
-static struct resource tegra_usb1_resources[] = {
-        [0] = {
-                .start  = TEGRA_USB_BASE,
-                .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_USB,
-                .end    = INT_USB,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource tegra_usb2_resources[] = {
-        [0] = {
-                .start  = TEGRA_USB2_BASE,
-                .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_USB2,
-                .end    = INT_USB2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource tegra_usb3_resources[] = {
-        [0] = {
-                .start  = TEGRA_USB3_BASE,
-                .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_USB3,
-                .end    = INT_USB3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
-        .reset_gpio = -1,
-        .clk = "cdev2",
-};
-
-struct tegra_ehci_platform_data tegra_ehci1_pdata = {
-        .operating_mode = TEGRA_USB_OTG,
-        .power_down_on_bus_suspend = 1,
-        .vbus_gpio = -1,
-};
-
-struct tegra_ehci_platform_data tegra_ehci2_pdata = {
-        .phy_config = &tegra_ehci2_ulpi_phy_config,
-        .operating_mode = TEGRA_USB_HOST,
-        .power_down_on_bus_suspend = 1,
-        .vbus_gpio = -1,
-};
-
-struct tegra_ehci_platform_data tegra_ehci3_pdata = {
-        .operating_mode = TEGRA_USB_HOST,
-        .power_down_on_bus_suspend = 1,
-        .vbus_gpio = -1,
-};
-
-static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device tegra_ehci1_device = {
-        .name   = "tegra-ehci",
-        .id     = 0,
-        .dev    = {
-                .dma_mask       = &tegra_ehci_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &tegra_ehci1_pdata,
-        },
-        .resource = tegra_usb1_resources,
-        .num_resources = ARRAY_SIZE(tegra_usb1_resources),
-};
-
-struct platform_device tegra_ehci2_device = {
-        .name   = "tegra-ehci",
-        .id     = 1,
-        .dev    = {
-                .dma_mask       = &tegra_ehci_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &tegra_ehci2_pdata,
-        },
-        .resource = tegra_usb2_resources,
-        .num_resources = ARRAY_SIZE(tegra_usb2_resources),
-};
-
-struct platform_device tegra_ehci3_device = {
-        .name   = "tegra-ehci",
-        .id     = 2,
-        .dev    = {
-                .dma_mask       = &tegra_ehci_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &tegra_ehci3_pdata,
-        },
-        .resource = tegra_usb3_resources,
-        .num_resources = ARRAY_SIZE(tegra_usb3_resources),
-};
-
-static struct resource tegra_pmu_resources[] = {
-        [0] = {
-                .start  = INT_CPU0_PMU_INTR,
-                .end    = INT_CPU0_PMU_INTR,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = INT_CPU1_PMU_INTR,
-                .end    = INT_CPU1_PMU_INTR,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device tegra_pmu_device = {
-        .name           = "arm-pmu",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
-        .resource       = tegra_pmu_resources,
-};
-
-static struct resource tegra_uarta_resources[] = {
-        [0] = {
-                .start  = TEGRA_UARTA_BASE,
-                .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_UARTA,
-                .end    = INT_UARTA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource tegra_uartb_resources[] = {
-        [0] = {
-                .start  = TEGRA_UARTB_BASE,
-                .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_UARTB,
-                .end    = INT_UARTB,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource tegra_uartc_resources[] = {
-        [0] = {
-                .start  = TEGRA_UARTC_BASE,
-                .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_UARTC,
-                .end    = INT_UARTC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource tegra_uartd_resources[] = {
-        [0] = {
-                .start  = TEGRA_UARTD_BASE,
-                .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_UARTD,
-                .end    = INT_UARTD,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource tegra_uarte_resources[] = {
-        [0] = {
-                .start  = TEGRA_UARTE_BASE,
-                .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = INT_UARTE,
-                .end    = INT_UARTE,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device tegra_uarta_device = {
-        .name   = "tegra_uart",
-        .id     = 0,
-        .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
-        .resource       = tegra_uarta_resources,
-        .dev    = {
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-
-struct platform_device tegra_uartb_device = {
-        .name   = "tegra_uart",
-        .id     = 1,
-        .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
-        .resource       = tegra_uartb_resources,
-        .dev    = {
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-
-struct platform_device tegra_uartc_device = {
-        .name   = "tegra_uart",
-        .id     = 2,
-        .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
-        .resource       = tegra_uartc_resources,
-        .dev    = {
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-
-struct platform_device tegra_uartd_device = {
-        .name   = "tegra_uart",
-        .id     = 3,
-        .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
-        .resource       = tegra_uartd_resources,
-        .dev    = {
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-
-struct platform_device tegra_uarte_device = {
-        .name   = "tegra_uart",
-        .id     = 4,
-        .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
-        .resource       = tegra_uarte_resources,
-        .dev    = {
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-
-static struct resource i2s_resource1[] = {
-        [0] = {
-                .start  = INT_I2S1,
-                .end    = INT_I2S1,
-                .flags  = IORESOURCE_IRQ
-        },
-        [1] = {
-                .start  = TEGRA_DMA_REQ_SEL_I2S_1,
-                .end    = TEGRA_DMA_REQ_SEL_I2S_1,
-                .flags  = IORESOURCE_DMA
-        },
-        [2] = {
-                .start  = TEGRA_I2S1_BASE,
-                .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
-                .flags  = IORESOURCE_MEM
-        }
-};
-
-static struct resource i2s_resource2[] = {
-        [0] = {
-                .start  = INT_I2S2,
-                .end    = INT_I2S2,
-                .flags  = IORESOURCE_IRQ
-        },
-        [1] = {
-                .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
-                .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
-                .flags  = IORESOURCE_DMA
-        },
-        [2] = {
-                .start  = TEGRA_I2S2_BASE,
-                .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
-                .flags  = IORESOURCE_MEM
-        }
-};
-
-struct platform_device tegra_i2s_device1 = {
-        .name           = "tegra20-i2s",
-        .id             = 0,
-        .resource       = i2s_resource1,
-        .num_resources  = ARRAY_SIZE(i2s_resource1),
-};
-
-struct platform_device tegra_i2s_device2 = {
-        .name           = "tegra20-i2s",
-        .id             = 1,
-        .resource       = i2s_resource2,
-        .num_resources  = ARRAY_SIZE(i2s_resource2),
-};
-
-static struct resource tegra_das_resources[] = {
-        [0] = {
-                .start = TEGRA_APB_MISC_DAS_BASE,
-                .end = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device tegra_das_device = {
-        .name           = "tegra20-das",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(tegra_das_resources),
-        .resource       = tegra_das_resources,
-};
diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
deleted file mode 100644
index 4f5052726495..000000000000
--- a/arch/arm/mach-tegra/devices.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 2010,2011 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@android.com>
- *      Erik Gilling <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_DEVICES_H
-#define __MACH_TEGRA_DEVICES_H
-
-#include <linux/platform_device.h>
-#include <linux/platform_data/tegra_usb.h>
-
-#include <mach/usb_phy.h>
-
-extern struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config;
-
-extern struct tegra_ehci_platform_data tegra_ehci1_pdata;
-extern struct tegra_ehci_platform_data tegra_ehci2_pdata;
-extern struct tegra_ehci_platform_data tegra_ehci3_pdata;
-
-extern struct platform_device tegra_gpio_device;
-extern struct platform_device tegra_pinmux_device;
-extern struct platform_device tegra_sdhci_device1;
-extern struct platform_device tegra_sdhci_device2;
-extern struct platform_device tegra_sdhci_device3;
-extern struct platform_device tegra_sdhci_device4;
-extern struct platform_device tegra_i2c_device1;
-extern struct platform_device tegra_i2c_device2;
-extern struct platform_device tegra_i2c_device3;
-extern struct platform_device tegra_i2c_device4;
-extern struct platform_device tegra_spi_device1;
-extern struct platform_device tegra_spi_device2;
-extern struct platform_device tegra_spi_device3;
-extern struct platform_device tegra_spi_device4;
-extern struct platform_device tegra_ehci1_device;
-extern struct platform_device tegra_ehci2_device;
-extern struct platform_device tegra_ehci3_device;
-extern struct platform_device tegra_uarta_device;
-extern struct platform_device tegra_uartb_device;
-extern struct platform_device tegra_uartc_device;
-extern struct platform_device tegra_uartd_device;
-extern struct platform_device tegra_uarte_device;
-extern struct platform_device tegra_pmu_device;
-extern struct platform_device tegra_i2s_device1;
-extern struct platform_device tegra_i2s_device2;
-extern struct platform_device tegra_das_device;
-
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/kbc.h b/arch/arm/mach-tegra/include/mach/kbc.h
deleted file mode 100644
index a13025612939..000000000000
--- a/arch/arm/mach-tegra/include/mach/kbc.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Platform definitions for tegra-kbc keyboard input driver
- *
- * Copyright (c) 2010-2011, NVIDIA Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#ifndef ASMARM_ARCH_TEGRA_KBC_H
-#define ASMARM_ARCH_TEGRA_KBC_H
-
-#include <linux/types.h>
-#include <linux/input/matrix_keypad.h>
-
-#define KBC_MAX_GPIO    24
-#define KBC_MAX_KPENT   8
-
-#define KBC_MAX_ROW     16
-#define KBC_MAX_COL     8
-#define KBC_MAX_KEY     (KBC_MAX_ROW * KBC_MAX_COL)
-
-enum tegra_pin_type {
-        PIN_CFG_IGNORE,
-        PIN_CFG_COL,
-        PIN_CFG_ROW,
-};
-
-struct tegra_kbc_pin_cfg {
-        enum tegra_pin_type type;
-        unsigned char num;
-};
-
-struct tegra_kbc_wake_key {
-        u8 row:4;
-        u8 col:4;
-};
-
-struct tegra_kbc_platform_data {
-        unsigned int debounce_cnt;
-        unsigned int repeat_cnt;
-
-        struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
-        const struct matrix_keymap_data *keymap_data;
-
-        u32 wakeup_key;
-        bool wakeup;
-        bool use_fn_map;
-        bool use_ghost_filter;
-};
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinconf-tegra.h b/arch/arm/mach-tegra/include/mach/pinconf-tegra.h
deleted file mode 100644
index 1f24d304921e..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinconf-tegra.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * pinctrl configuration definitions for the NVIDIA Tegra pinmux
- *
- * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- */
-
-#ifndef __PINCONF_TEGRA_H__
-#define __PINCONF_TEGRA_H__
-
-enum tegra_pinconf_param {
-        /* argument: tegra_pinconf_pull */
-        TEGRA_PINCONF_PARAM_PULL,
-        /* argument: tegra_pinconf_tristate */
-        TEGRA_PINCONF_PARAM_TRISTATE,
-        /* argument: Boolean */
-        TEGRA_PINCONF_PARAM_ENABLE_INPUT,
-        /* argument: Boolean */
-        TEGRA_PINCONF_PARAM_OPEN_DRAIN,
-        /* argument: Boolean */
-        TEGRA_PINCONF_PARAM_LOCK,
-        /* argument: Boolean */
-        TEGRA_PINCONF_PARAM_IORESET,
-        /* argument: Boolean */
-        TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
-        /* argument: Boolean */
-        TEGRA_PINCONF_PARAM_SCHMITT,
-        /* argument: Boolean */
-        TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
-        /* argument: Integer, range is HW-dependant */
-        TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
-        /* argument: Integer, range is HW-dependant */
-        TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
-        /* argument: Integer, range is HW-dependant */
-        TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
-        /* argument: Integer, range is HW-dependant */
-        TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
-};
-
-enum tegra_pinconf_pull {
-        TEGRA_PINCONFIG_PULL_NONE,
-        TEGRA_PINCONFIG_PULL_DOWN,
-        TEGRA_PINCONFIG_PULL_UP,
-};
-
-enum tegra_pinconf_tristate {
-        TEGRA_PINCONFIG_DRIVEN,
-        TEGRA_PINCONFIG_TRISTATE,
-};
-
-#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
-#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
-#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
-
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/suspend.h b/arch/arm/mach-tegra/include/mach/suspend.h
deleted file mode 100644
index 5af8715d2e1e..000000000000
--- a/arch/arm/mach-tegra/include/mach/suspend.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/suspend.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-
-#ifndef _MACH_TEGRA_SUSPEND_H_
-#define _MACH_TEGRA_SUSPEND_H_
-
-void tegra_pinmux_suspend(void);
-void tegra_irq_suspend(void);
-void tegra_gpio_suspend(void);
-void tegra_clk_suspend(void);
-void tegra_dma_suspend(void);
-void tegra_timer_suspend(void);
-
-void tegra_pinmux_resume(void);
-void tegra_irq_resume(void);
-void tegra_gpio_resume(void);
-void tegra_clk_resume(void);
-void tegra_dma_resume(void);
-void tegra_timer_resume(void);
-
-#endif /* _MACH_TEGRA_SUSPEND_H_ */
diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/arch/arm/mach-tegra/include/mach/usb_phy.h
deleted file mode 100644
index 935ce9f65590..000000000000
--- a/arch/arm/mach-tegra/include/mach/usb_phy.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/usb_phy.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_USB_PHY_H
-#define __MACH_USB_PHY_H
-
-#include <linux/clk.h>
-#include <linux/usb/otg.h>
-
-struct tegra_utmip_config {
-        u8 hssync_start_delay;
-        u8 elastic_limit;
-        u8 idle_wait_delay;
-        u8 term_range_adj;
-        u8 xcvr_setup;
-        u8 xcvr_lsfslew;
-        u8 xcvr_lsrslew;
-};
-
-struct tegra_ulpi_config {
-        int reset_gpio;
-        const char *clk;
-};
-
-enum tegra_usb_phy_port_speed {
-        TEGRA_USB_PHY_PORT_SPEED_FULL = 0,
-        TEGRA_USB_PHY_PORT_SPEED_LOW,
-        TEGRA_USB_PHY_PORT_SPEED_HIGH,
-};
-
-enum tegra_usb_phy_mode {
-        TEGRA_USB_PHY_MODE_DEVICE,
-        TEGRA_USB_PHY_MODE_HOST,
-};
-
-struct tegra_xtal_freq;
-
-struct tegra_usb_phy {
-        int instance;
-        const struct tegra_xtal_freq *freq;
-        void __iomem *regs;
-        void __iomem *pad_regs;
-        struct clk *clk;
-        struct clk *pll_u;
-        struct clk *pad_clk;
-        enum tegra_usb_phy_mode mode;
-        void *config;
-        struct usb_phy *ulpi;
-};
-
-struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
-        void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode);
-
-int tegra_usb_phy_power_on(struct tegra_usb_phy *phy);
-
-void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy);
-
-void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy);
-
-void tegra_usb_phy_power_off(struct tegra_usb_phy *phy);
-
-void tegra_usb_phy_preresume(struct tegra_usb_phy *phy);
-
-void tegra_usb_phy_postresume(struct tegra_usb_phy *phy);
-
-void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
-                                 enum tegra_usb_phy_port_speed port_speed);
-
-void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy);
-
-void tegra_usb_phy_close(struct tegra_usb_phy *phy);
-
-#endif /* __MACH_USB_PHY_H */
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 3463fb5b79c7..a8dba6489c9b 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -352,17 +352,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
 /* Tegra PCIE requires relaxed ordering */
 static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev)
 {
-        u16 val16;
-        int pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
-
-        if (pos <= 0) {
-                dev_err(&dev->dev, "skipping relaxed ordering fixup\n");
-                return;
-        }
-
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16);
-        val16 |= PCI_EXP_DEVCTL_RELAX_EN;
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16);
+        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
 
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 15d506501ccc..de0662de28a0 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -199,7 +199,9 @@ int __init tegra_powergate_init(void)
 
 #ifdef CONFIG_DEBUG_FS
 
-static const char * const powergate_name[] = {
+static const char * const *powergate_name;
+
+static const char * const powergate_name_t20[] = {
         [TEGRA_POWERGATE_CPU]   = "cpu",
         [TEGRA_POWERGATE_3D]    = "3d",
         [TEGRA_POWERGATE_VENC]  = "venc",
@@ -209,6 +211,23 @@ static const char * const powergate_name[] = {
         [TEGRA_POWERGATE_MPE]   = "mpe",
 };
 
+static const char * const powergate_name_t30[] = {
+        [TEGRA_POWERGATE_CPU]   = "cpu0",
+        [TEGRA_POWERGATE_3D]    = "3d0",
+        [TEGRA_POWERGATE_VENC]  = "venc",
+        [TEGRA_POWERGATE_VDEC]  = "vdec",
+        [TEGRA_POWERGATE_PCIE]  = "pcie",
+        [TEGRA_POWERGATE_L2]    = "l2",
+        [TEGRA_POWERGATE_MPE]   = "mpe",
+        [TEGRA_POWERGATE_HEG]   = "heg",
+        [TEGRA_POWERGATE_SATA]  = "sata",
+        [TEGRA_POWERGATE_CPU1]  = "cpu1",
+        [TEGRA_POWERGATE_CPU2]  = "cpu2",
+        [TEGRA_POWERGATE_CPU3]  = "cpu3",
+        [TEGRA_POWERGATE_CELP]  = "celp",
+        [TEGRA_POWERGATE_3D1]   = "3d1",
+};
+
 static int powergate_show(struct seq_file *s, void *data)
 {
         int i;
@@ -237,14 +256,24 @@ static const struct file_operations powergate_fops = {
 int __init tegra_powergate_debugfs_init(void)
 {
         struct dentry *d;
-        int err = -ENOMEM;
 
-        d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
-                &powergate_fops);
-        if (!d)
-                return -ENOMEM;
+        switch (tegra_chip_id) {
+        case TEGRA20:
+                powergate_name = powergate_name_t20;
+                break;
+        case TEGRA30:
+                powergate_name = powergate_name_t30;
+                break;
+        }
+
+        if (powergate_name) {
+                d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
+                        &powergate_fops);
+                if (!d)
+                        return -ENOMEM;
+        }
 
-        return err;
+        return 0;
 }
 
 #endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index 9273b0dffc66..deb873fb12b6 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -28,7 +28,6 @@
 #include <linux/clk.h>
 
 #include <mach/iomap.h>
-#include <mach/suspend.h>
 
 #include "clock.h"
 #include "fuse.h"
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index e81dcd239c95..cc9b5fd8c3d3 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -28,7 +28,6 @@
 #include <linux/clk.h>
 
 #include <mach/iomap.h>
-#include <mach/suspend.h>
 
 #include "clock.h"
 #include "fuse.h"
@@ -918,14 +917,10 @@ PERIPH_CLK(la,		"la",			NULL,	76,	0x1f8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX
 PERIPH_CLK(owr,         "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
 PERIPH_CLK(nor,         "nor",                  NULL,   42,     0x1d0,  92000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
 PERIPH_CLK(mipi,        "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
-PERIPH_CLK(i2c1,        "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
-PERIPH_CLK(i2c2,        "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
-PERIPH_CLK(i2c3,        "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
-PERIPH_CLK(dvc,         "tegra-i2c.3",          NULL,   47,     0x128,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
-PERIPH_CLK(i2c1_i2c,    "tegra-i2c.0",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0);
-PERIPH_CLK(i2c2_i2c,    "tegra-i2c.1",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0);
-PERIPH_CLK(i2c3_i2c,    "tegra-i2c.2",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0);
-PERIPH_CLK(dvc_i2c,     "tegra-i2c.3",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0);
+PERIPH_CLK(i2c1,        "tegra-i2c.0",          "div-clk", 12,  0x124,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(i2c2,        "tegra-i2c.1",          "div-clk", 54,  0x198,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(i2c3,        "tegra-i2c.2",          "div-clk", 67,  0x1b8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(dvc,         "tegra-i2c.3",          "div-clk", 47,  0x128,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
 PERIPH_CLK(uarta,       "tegra-uart.0",         NULL,   6,      0x178,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
 PERIPH_CLK(uartb,       "tegra-uart.1",         NULL,   7,      0x17c,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
 PERIPH_CLK(uartc,       "tegra-uart.2",         NULL,   55,     0x1a0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
@@ -990,10 +985,6 @@ static struct clk *tegra_list_clks[] = {
         &tegra_i2c2,
         &tegra_i2c3,
         &tegra_dvc,
-        &tegra_i2c1_i2c,
-        &tegra_i2c2_i2c,
-        &tegra_i2c3_i2c,
-        &tegra_dvc_i2c,
         &tegra_uarta,
         &tegra_uartb,
         &tegra_uartc,
@@ -1057,6 +1048,10 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
         CLK_DUPLICATE("vde",    "tegra-aes",    "vde"),
         CLK_DUPLICATE("cclk",   NULL,           "cpu"),
         CLK_DUPLICATE("twd",    "smp_twd",      NULL),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
 };
 
 #define CLK(dev, con, ck)       \
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index c10449603df0..d92cb556ae35 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -1071,11 +1071,11 @@ PERIPH_CLK(la,		"la",			NULL,	76,	0x1f8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX
 PERIPH_CLK(owr,         "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
 PERIPH_CLK(nor,         "nor",                  NULL,   42,     0x1d0,  127000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
 PERIPH_CLK(mipi,        "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
-PERIPH_CLK(i2c1,        "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
-PERIPH_CLK(i2c2,        "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
-PERIPH_CLK(i2c3,        "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
-PERIPH_CLK(i2c4,        "tegra-i2c.3",          NULL,   103,    0x3c4,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
-PERIPH_CLK(i2c5,        "tegra-i2c.4",          NULL,   47,     0x128,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c1,        "tegra-i2c.0",          "div-clk", 12,  0x124,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c2,        "tegra-i2c.1",          "div-clk", 54,  0x198,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c3,        "tegra-i2c.2",          "div-clk", 67,  0x1b8,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c4,        "tegra-i2c.3",          "div-clk", 103, 0x3c4,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c5,        "tegra-i2c.4",          "div-clk", 47,  0x128,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
 PERIPH_CLK(uarta,       "tegra-uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
 PERIPH_CLK(uartb,       "tegra-uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
 PERIPH_CLK(uartc,       "tegra-uart.2",         NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
@@ -1287,6 +1287,11 @@ struct clk_duplicate tegra_clk_duplicates[] = {
         CLK_DUPLICATE("dam1", NULL, "dam1"),
         CLK_DUPLICATE("dam2", NULL, "dam2"),
         CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
+        CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"),
 };
 
 struct clk *tegra_ptr_clks[] = {
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 57b5bdc13b9b..eccdce983043 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -33,7 +33,6 @@
 
 #include <mach/iomap.h>
 #include <mach/irqs.h>
-#include <mach/suspend.h>
 
 #include "board.h"
 #include "clock.h"
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
deleted file mode 100644
index 022b33a05c3a..000000000000
--- a/arch/arm/mach-tegra/usb_phy.c
+++ /dev/null
@@ -1,817 +0,0 @@
-/*
- * arch/arm/mach-tegra/usb_phy.c
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Erik Gilling <konkers@google.com>
- *      Benoit Goby <benoit@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/resource.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/of_gpio.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <asm/mach-types.h>
-#include <mach/gpio-tegra.h>
-#include <mach/usb_phy.h>
-#include <mach/iomap.h>
-
-#define ULPI_VIEWPORT           0x170
-
-#define USB_PORTSC1             0x184
-#define   USB_PORTSC1_PTS(x)    (((x) & 0x3) << 30)
-#define   USB_PORTSC1_PSPD(x)   (((x) & 0x3) << 26)
-#define   USB_PORTSC1_PHCD      (1 << 23)
-#define   USB_PORTSC1_WKOC      (1 << 22)
-#define   USB_PORTSC1_WKDS      (1 << 21)
-#define   USB_PORTSC1_WKCN      (1 << 20)
-#define   USB_PORTSC1_PTC(x)    (((x) & 0xf) << 16)
-#define   USB_PORTSC1_PP        (1 << 12)
-#define   USB_PORTSC1_SUSP      (1 << 7)
-#define   USB_PORTSC1_PE        (1 << 2)
-#define   USB_PORTSC1_CCS       (1 << 0)
-
-#define USB_SUSP_CTRL           0x400
-#define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
-#define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
-#define   USB_SUSP_CLR          (1 << 5)
-#define   USB_PHY_CLK_VALID     (1 << 7)
-#define   UTMIP_RESET                   (1 << 11)
-#define   UHSIC_RESET                   (1 << 11)
-#define   UTMIP_PHY_ENABLE              (1 << 12)
-#define   ULPI_PHY_ENABLE       (1 << 13)
-#define   USB_SUSP_SET          (1 << 14)
-#define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
-
-#define USB1_LEGACY_CTRL        0x410
-#define   USB1_NO_LEGACY_MODE                   (1 << 0)
-#define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
-#define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
-#define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
-                                                (1 << 1)
-#define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
-#define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
-
-#define ULPI_TIMING_CTRL_0      0x424
-#define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
-#define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
-
-#define ULPI_TIMING_CTRL_1      0x428
-#define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
-#define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
-#define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
-#define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
-#define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
-#define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
-
-#define UTMIP_PLL_CFG1          0x804
-#define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
-#define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
-
-#define UTMIP_XCVR_CFG0         0x808
-#define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
-#define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
-#define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
-#define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
-#define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
-#define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
-#define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
-
-#define UTMIP_BIAS_CFG0         0x80c
-#define   UTMIP_OTGPD                   (1 << 11)
-#define   UTMIP_BIASPD                  (1 << 10)
-
-#define UTMIP_HSRX_CFG0         0x810
-#define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
-#define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
-
-#define UTMIP_HSRX_CFG1         0x814
-#define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
-
-#define UTMIP_TX_CFG0           0x820
-#define   UTMIP_FS_PREABMLE_J           (1 << 19)
-#define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
-
-#define UTMIP_MISC_CFG0         0x824
-#define   UTMIP_DPDM_OBSERVE            (1 << 26)
-#define   UTMIP_DPDM_OBSERVE_SEL(x)     (((x) & 0xf) << 27)
-#define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
-#define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
-#define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
-#define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
-#define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
-
-#define UTMIP_MISC_CFG1         0x828
-#define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
-#define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
-
-#define UTMIP_DEBOUNCE_CFG0     0x82c
-#define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
-
-#define UTMIP_BAT_CHRG_CFG0     0x830
-#define   UTMIP_PD_CHRG                 (1 << 0)
-
-#define UTMIP_SPARE_CFG0        0x834
-#define   FUSE_SETUP_SEL                (1 << 3)
-
-#define UTMIP_XCVR_CFG1         0x838
-#define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
-#define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
-#define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
-#define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
-
-#define UTMIP_BIAS_CFG1         0x83c
-#define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
-
-static DEFINE_SPINLOCK(utmip_pad_lock);
-static int utmip_pad_count;
-
-struct tegra_xtal_freq {
-        int freq;
-        u8 enable_delay;
-        u8 stable_count;
-        u8 active_delay;
-        u8 xtal_freq_count;
-        u16 debounce;
-};
-
-static const struct tegra_xtal_freq tegra_freq_table[] = {
-        {
-                .freq = 12000000,
-                .enable_delay = 0x02,
-                .stable_count = 0x2F,
-                .active_delay = 0x04,
-                .xtal_freq_count = 0x76,
-                .debounce = 0x7530,
-        },
-        {
-                .freq = 13000000,
-                .enable_delay = 0x02,
-                .stable_count = 0x33,
-                .active_delay = 0x05,
-                .xtal_freq_count = 0x7F,
-                .debounce = 0x7EF4,
-        },
-        {
-                .freq = 19200000,
-                .enable_delay = 0x03,
-                .stable_count = 0x4B,
-                .active_delay = 0x06,
-                .xtal_freq_count = 0xBB,
-                .debounce = 0xBB80,
-        },
-        {
-                .freq = 26000000,
-                .enable_delay = 0x04,
-                .stable_count = 0x66,
-                .active_delay = 0x09,
-                .xtal_freq_count = 0xFE,
-                .debounce = 0xFDE8,
-        },
-};
-
-static struct tegra_utmip_config utmip_default[] = {
-        [0] = {
-                .hssync_start_delay = 9,
-                .idle_wait_delay = 17,
-                .elastic_limit = 16,
-                .term_range_adj = 6,
-                .xcvr_setup = 9,
-                .xcvr_lsfslew = 1,
-                .xcvr_lsrslew = 1,
-        },
-        [2] = {
-                .hssync_start_delay = 9,
-                .idle_wait_delay = 17,
-                .elastic_limit = 16,
-                .term_range_adj = 6,
-                .xcvr_setup = 9,
-                .xcvr_lsfslew = 2,
-                .xcvr_lsrslew = 2,
-        },
-};
-
-static inline bool phy_is_ulpi(struct tegra_usb_phy *phy)
-{
-        return (phy->instance == 1);
-}
-
-static int utmip_pad_open(struct tegra_usb_phy *phy)
-{
-        phy->pad_clk = clk_get_sys("utmip-pad", NULL);
-        if (IS_ERR(phy->pad_clk)) {
-                pr_err("%s: can't get utmip pad clock\n", __func__);
-                return PTR_ERR(phy->pad_clk);
-        }
-
-        if (phy->instance == 0) {
-                phy->pad_regs = phy->regs;
-        } else {
-                phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
-                if (!phy->pad_regs) {
-                        pr_err("%s: can't remap usb registers\n", __func__);
-                        clk_put(phy->pad_clk);
-                        return -ENOMEM;
-                }
-        }
-        return 0;
-}
-
-static void utmip_pad_close(struct tegra_usb_phy *phy)
-{
-        if (phy->instance != 0)
-                iounmap(phy->pad_regs);
-        clk_put(phy->pad_clk);
-}
-
-static void utmip_pad_power_on(struct tegra_usb_phy *phy)
-{
-        unsigned long val, flags;
-        void __iomem *base = phy->pad_regs;
-
-        clk_prepare_enable(phy->pad_clk);
-
-        spin_lock_irqsave(&utmip_pad_lock, flags);
-
-        if (utmip_pad_count++ == 0) {
-                val = readl(base + UTMIP_BIAS_CFG0);
-                val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
-                writel(val, base + UTMIP_BIAS_CFG0);
-        }
-
-        spin_unlock_irqrestore(&utmip_pad_lock, flags);
-
-        clk_disable_unprepare(phy->pad_clk);
-}
-
-static int utmip_pad_power_off(struct tegra_usb_phy *phy)
-{
-        unsigned long val, flags;
-        void __iomem *base = phy->pad_regs;
-
-        if (!utmip_pad_count) {
-                pr_err("%s: utmip pad already powered off\n", __func__);
-                return -EINVAL;
-        }
-
-        clk_prepare_enable(phy->pad_clk);
-
-        spin_lock_irqsave(&utmip_pad_lock, flags);
-
-        if (--utmip_pad_count == 0) {
-                val = readl(base + UTMIP_BIAS_CFG0);
-                val |= UTMIP_OTGPD | UTMIP_BIASPD;
-                writel(val, base + UTMIP_BIAS_CFG0);
-        }
-
-        spin_unlock_irqrestore(&utmip_pad_lock, flags);
-
-        clk_disable_unprepare(phy->pad_clk);
-
-        return 0;
-}
-
-static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
-{
-        unsigned long timeout = 2000;
-        do {
-                if ((readl(reg) & mask) == result)
-                        return 0;
-                udelay(1);
-                timeout--;
-        } while (timeout);
-        return -1;
-}
-
-static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-
-        if (phy->instance == 0) {
-                val = readl(base + USB_SUSP_CTRL);
-                val |= USB_SUSP_SET;
-                writel(val, base + USB_SUSP_CTRL);
-
-                udelay(10);
-
-                val = readl(base + USB_SUSP_CTRL);
-                val &= ~USB_SUSP_SET;
-                writel(val, base + USB_SUSP_CTRL);
-        }
-
-        if (phy->instance == 2) {
-                val = readl(base + USB_PORTSC1);
-                val |= USB_PORTSC1_PHCD;
-                writel(val, base + USB_PORTSC1);
-        }
-
-        if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
-                pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
-}
-
-static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-
-        if (phy->instance == 0) {
-                val = readl(base + USB_SUSP_CTRL);
-                val |= USB_SUSP_CLR;
-                writel(val, base + USB_SUSP_CTRL);
-
-                udelay(10);
-
-                val = readl(base + USB_SUSP_CTRL);
-                val &= ~USB_SUSP_CLR;
-                writel(val, base + USB_SUSP_CTRL);
-        }
-
-        if (phy->instance == 2) {
-                val = readl(base + USB_PORTSC1);
-                val &= ~USB_PORTSC1_PHCD;
-                writel(val, base + USB_PORTSC1);
-        }
-
-        if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
-                                                     USB_PHY_CLK_VALID))
-                pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
-}
-
-static int utmi_phy_power_on(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-        struct tegra_utmip_config *config = phy->config;
-
-        val = readl(base + USB_SUSP_CTRL);
-        val |= UTMIP_RESET;
-        writel(val, base + USB_SUSP_CTRL);
-
-        if (phy->instance == 0) {
-                val = readl(base + USB1_LEGACY_CTRL);
-                val |= USB1_NO_LEGACY_MODE;
-                writel(val, base + USB1_LEGACY_CTRL);
-        }
-
-        val = readl(base + UTMIP_TX_CFG0);
-        val &= ~UTMIP_FS_PREABMLE_J;
-        writel(val, base + UTMIP_TX_CFG0);
-
-        val = readl(base + UTMIP_HSRX_CFG0);
-        val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
-        val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
-        val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
-        writel(val, base + UTMIP_HSRX_CFG0);
-
-        val = readl(base + UTMIP_HSRX_CFG1);
-        val &= ~UTMIP_HS_SYNC_START_DLY(~0);
-        val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
-        writel(val, base + UTMIP_HSRX_CFG1);
-
-        val = readl(base + UTMIP_DEBOUNCE_CFG0);
-        val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
-        val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
-        writel(val, base + UTMIP_DEBOUNCE_CFG0);
-
-        val = readl(base + UTMIP_MISC_CFG0);
-        val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
-        writel(val, base + UTMIP_MISC_CFG0);
-
-        val = readl(base + UTMIP_MISC_CFG1);
-        val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
-        val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
-                UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
-        writel(val, base + UTMIP_MISC_CFG1);
-
-        val = readl(base + UTMIP_PLL_CFG1);
-        val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
-        val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
-                UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
-        writel(val, base + UTMIP_PLL_CFG1);
-
-        if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
-                val = readl(base + USB_SUSP_CTRL);
-                val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
-                writel(val, base + USB_SUSP_CTRL);
-        }
-
-        utmip_pad_power_on(phy);
-
-        val = readl(base + UTMIP_XCVR_CFG0);
-        val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
-                 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) |
-                 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) |
-                 UTMIP_XCVR_HSSLEW_MSB(~0));
-        val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
-        val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
-        val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
-        writel(val, base + UTMIP_XCVR_CFG0);
-
-        val = readl(base + UTMIP_XCVR_CFG1);
-        val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
-                 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
-        val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
-        writel(val, base + UTMIP_XCVR_CFG1);
-
-        val = readl(base + UTMIP_BAT_CHRG_CFG0);
-        val &= ~UTMIP_PD_CHRG;
-        writel(val, base + UTMIP_BAT_CHRG_CFG0);
-
-        val = readl(base + UTMIP_BIAS_CFG1);
-        val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
-        val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
-        writel(val, base + UTMIP_BIAS_CFG1);
-
-        if (phy->instance == 0) {
-                val = readl(base + UTMIP_SPARE_CFG0);
-                if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
-                        val &= ~FUSE_SETUP_SEL;
-                else
-                        val |= FUSE_SETUP_SEL;
-                writel(val, base + UTMIP_SPARE_CFG0);
-        }
-
-        if (phy->instance == 2) {
-                val = readl(base + USB_SUSP_CTRL);
-                val |= UTMIP_PHY_ENABLE;
-                writel(val, base + USB_SUSP_CTRL);
-        }
-
-        val = readl(base + USB_SUSP_CTRL);
-        val &= ~UTMIP_RESET;
-        writel(val, base + USB_SUSP_CTRL);
-
-        if (phy->instance == 0) {
-                val = readl(base + USB1_LEGACY_CTRL);
-                val &= ~USB1_VBUS_SENSE_CTL_MASK;
-                val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
-                writel(val, base + USB1_LEGACY_CTRL);
-
-                val = readl(base + USB_SUSP_CTRL);
-                val &= ~USB_SUSP_SET;
-                writel(val, base + USB_SUSP_CTRL);
-        }
-
-        utmi_phy_clk_enable(phy);
-
-        if (phy->instance == 2) {
-                val = readl(base + USB_PORTSC1);
-                val &= ~USB_PORTSC1_PTS(~0);
-                writel(val, base + USB_PORTSC1);
-        }
-
-        return 0;
-}
-
-static void utmi_phy_power_off(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-
-        utmi_phy_clk_disable(phy);
-
-        if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
-                val = readl(base + USB_SUSP_CTRL);
-                val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
-                val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
-                writel(val, base + USB_SUSP_CTRL);
-        }
-
-        val = readl(base + USB_SUSP_CTRL);
-        val |= UTMIP_RESET;
-        writel(val, base + USB_SUSP_CTRL);
-
-        val = readl(base + UTMIP_BAT_CHRG_CFG0);
-        val |= UTMIP_PD_CHRG;
-        writel(val, base + UTMIP_BAT_CHRG_CFG0);
-
-        val = readl(base + UTMIP_XCVR_CFG0);
-        val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
-               UTMIP_FORCE_PDZI_POWERDOWN;
-        writel(val, base + UTMIP_XCVR_CFG0);
-
-        val = readl(base + UTMIP_XCVR_CFG1);
-        val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
-               UTMIP_FORCE_PDDR_POWERDOWN;
-        writel(val, base + UTMIP_XCVR_CFG1);
-
-        utmip_pad_power_off(phy);
-}
-
-static void utmi_phy_preresume(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-
-        val = readl(base + UTMIP_TX_CFG0);
-        val |= UTMIP_HS_DISCON_DISABLE;
-        writel(val, base + UTMIP_TX_CFG0);
-}
-
-static void utmi_phy_postresume(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-
-        val = readl(base + UTMIP_TX_CFG0);
-        val &= ~UTMIP_HS_DISCON_DISABLE;
-        writel(val, base + UTMIP_TX_CFG0);
-}
-
-static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
-                                   enum tegra_usb_phy_port_speed port_speed)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-
-        val = readl(base + UTMIP_MISC_CFG0);
-        val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
-        if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
-                val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
-        else
-                val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
-        writel(val, base + UTMIP_MISC_CFG0);
-        udelay(1);
-
-        val = readl(base + UTMIP_MISC_CFG0);
-        val |= UTMIP_DPDM_OBSERVE;
-        writel(val, base + UTMIP_MISC_CFG0);
-        udelay(10);
-}
-
-static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-
-        val = readl(base + UTMIP_MISC_CFG0);
-        val &= ~UTMIP_DPDM_OBSERVE;
-        writel(val, base + UTMIP_MISC_CFG0);
-        udelay(10);
-}
-
-static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
-{
-        int ret;
-        unsigned long val;
-        void __iomem *base = phy->regs;
-        struct tegra_ulpi_config *config = phy->config;
-
-        gpio_direction_output(config->reset_gpio, 0);
-        msleep(5);
-        gpio_direction_output(config->reset_gpio, 1);
-
-        clk_prepare_enable(phy->clk);
-        msleep(1);
-
-        val = readl(base + USB_SUSP_CTRL);
-        val |= UHSIC_RESET;
-        writel(val, base + USB_SUSP_CTRL);
-
-        val = readl(base + ULPI_TIMING_CTRL_0);
-        val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
-        writel(val, base + ULPI_TIMING_CTRL_0);
-
-        val = readl(base + USB_SUSP_CTRL);
-        val |= ULPI_PHY_ENABLE;
-        writel(val, base + USB_SUSP_CTRL);
-
-        val = 0;
-        writel(val, base + ULPI_TIMING_CTRL_1);
-
-        val |= ULPI_DATA_TRIMMER_SEL(4);
-        val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
-        val |= ULPI_DIR_TRIMMER_SEL(4);
-        writel(val, base + ULPI_TIMING_CTRL_1);
-        udelay(10);
-
-        val |= ULPI_DATA_TRIMMER_LOAD;
-        val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
-        val |= ULPI_DIR_TRIMMER_LOAD;
-        writel(val, base + ULPI_TIMING_CTRL_1);
-
-        /* Fix VbusInvalid due to floating VBUS */
-        ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
-        if (ret) {
-                pr_err("%s: ulpi write failed\n", __func__);
-                return ret;
-        }
-
-        ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
-        if (ret) {
-                pr_err("%s: ulpi write failed\n", __func__);
-                return ret;
-        }
-
-        val = readl(base + USB_PORTSC1);
-        val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
-        writel(val, base + USB_PORTSC1);
-
-        val = readl(base + USB_SUSP_CTRL);
-        val |= USB_SUSP_CLR;
-        writel(val, base + USB_SUSP_CTRL);
-        udelay(100);
-
-        val = readl(base + USB_SUSP_CTRL);
-        val &= ~USB_SUSP_CLR;
-        writel(val, base + USB_SUSP_CTRL);
-
-        return 0;
-}
-
-static void ulpi_phy_power_off(struct tegra_usb_phy *phy)
-{
-        unsigned long val;
-        void __iomem *base = phy->regs;
-        struct tegra_ulpi_config *config = phy->config;
-
-        /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
-         * Controller to immediately bring the ULPI PHY out of low power
-         */
-        val = readl(base + USB_PORTSC1);
-        val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
-        writel(val, base + USB_PORTSC1);
-
-        gpio_direction_output(config->reset_gpio, 0);
-        clk_disable(phy->clk);
-}
-
-struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
-        void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode)
-{
-        struct tegra_usb_phy *phy;
-        struct tegra_ulpi_config *ulpi_config;
-        unsigned long parent_rate;
-        int i;
-        int err;
-
-        phy = kmalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
-        if (!phy)
-                return ERR_PTR(-ENOMEM);
-
-        phy->instance = instance;
-        phy->regs = regs;
-        phy->config = config;
-        phy->mode = phy_mode;
-
-        if (!phy->config) {
-                if (phy_is_ulpi(phy)) {
-                        pr_err("%s: ulpi phy configuration missing", __func__);
-                        err = -EINVAL;
-                        goto err0;
-                } else {
-                        phy->config = &utmip_default[instance];
-                }
-        }
-
-        phy->pll_u = clk_get_sys(NULL, "pll_u");
-        if (IS_ERR(phy->pll_u)) {
-                pr_err("Can't get pll_u clock\n");
-                err = PTR_ERR(phy->pll_u);
-                goto err0;
-        }
-        clk_prepare_enable(phy->pll_u);
-
-        parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
-        for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
-                if (tegra_freq_table[i].freq == parent_rate) {
-                        phy->freq = &tegra_freq_table[i];
-                        break;
-                }
-        }
-        if (!phy->freq) {
-                pr_err("invalid pll_u parent rate %ld\n", parent_rate);
-                err = -EINVAL;
-                goto err1;
-        }
-
-        if (phy_is_ulpi(phy)) {
-                ulpi_config = config;
-                phy->clk = clk_get_sys(NULL, ulpi_config->clk);
-                if (IS_ERR(phy->clk)) {
-                        pr_err("%s: can't get ulpi clock\n", __func__);
-                        err = -ENXIO;
-                        goto err1;
-                }
-                if (!gpio_is_valid(ulpi_config->reset_gpio))
-                        ulpi_config->reset_gpio =
-                                of_get_named_gpio(dev->of_node,
-                                                  "nvidia,phy-reset-gpio", 0);
-                if (!gpio_is_valid(ulpi_config->reset_gpio)) {
-                        pr_err("%s: invalid reset gpio: %d\n", __func__,
-                               ulpi_config->reset_gpio);
-                        err = -EINVAL;
-                        goto err1;
-                }
-                gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
-                gpio_direction_output(ulpi_config->reset_gpio, 0);
-                phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
-                phy->ulpi->io_priv = regs + ULPI_VIEWPORT;
-        } else {
-                err = utmip_pad_open(phy);
-                if (err < 0)
-                        goto err1;
-        }
-
-        return phy;
-
-err1:
-        clk_disable_unprepare(phy->pll_u);
-        clk_put(phy->pll_u);
-err0:
-        kfree(phy);
-        return ERR_PTR(err);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_open);
-
-int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
-{
-        if (phy_is_ulpi(phy))
-                return ulpi_phy_power_on(phy);
-        else
-                return utmi_phy_power_on(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_power_on);
-
-void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
-{
-        if (phy_is_ulpi(phy))
-                ulpi_phy_power_off(phy);
-        else
-                utmi_phy_power_off(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_power_off);
-
-void tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
-{
-        if (!phy_is_ulpi(phy))
-                utmi_phy_preresume(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
-
-void tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
-{
-        if (!phy_is_ulpi(phy))
-                utmi_phy_postresume(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
-
-void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
-                                 enum tegra_usb_phy_port_speed port_speed)
-{
-        if (!phy_is_ulpi(phy))
-                utmi_phy_restore_start(phy, port_speed);
-}
-EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
-
-void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
-{
-        if (!phy_is_ulpi(phy))
-                utmi_phy_restore_end(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
-
-void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
-{
-        if (!phy_is_ulpi(phy))
-                utmi_phy_clk_disable(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_disable);
-
-void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
-{
-        if (!phy_is_ulpi(phy))
-                utmi_phy_clk_enable(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_enable);
-
-void tegra_usb_phy_close(struct tegra_usb_phy *phy)
-{
-        if (phy_is_ulpi(phy))
-                clk_put(phy->clk);
-        else
-                utmip_pad_close(phy);
-        clk_disable_unprepare(phy->pll_u);
-        clk_put(phy->pll_u);
-        kfree(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_close);
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index ef6f602b7e48..b8efac4daed8 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1557,9 +1557,6 @@ static struct u300_mux_hog u300_mux_hogs[] = {
                 .dev = &uart0_device.dev,
         },
         {
-                .dev = &pl022_device.dev,
-        },
-        {
                 .dev = &mmcsd_device.dev,
         },
 };
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index 0d4620ed853c..96800aa1316d 100644
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -9,7 +9,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/i2c.h>
-#include <linux/mfd/abx500.h>
+#include <linux/mfd/ab3100.h>
 #include <linux/regulator/machine.h>
 #include <linux/amba/bus.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index a258996d954b..c77c86c47369 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -29,6 +29,7 @@ config MACH_MOP500
         select I2C
         select I2C_NOMADIK
         select SOC_BUS
+        select REGULATOR_FIXED_VOLTAGE
         help
           Include support for the MOP500 development platform.
 
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 5691ef679d01..f24710dfc395 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -12,6 +12,6 @@ obj-$(CONFIG_MACH_MOP500)	+= board-mop500.o board-mop500-sdi.o \
                                 board-mop500-uib.o board-mop500-stuib.o \
                                 board-mop500-u8500uib.o \
                                 board-mop500-pins.o \
-                                board-mop500-msp.o
+                                board-mop500-audio.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-audio.c
index df15646036aa..070629a95625 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -7,7 +7,6 @@
 #include <linux/platform_device.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
-#include <linux/pinctrl/consumer.h>
 
 #include <plat/gpio-nomadik.h>
 #include <plat/pincfg.h>
@@ -23,53 +22,6 @@
 #include "devices-db8500.h"
 #include "pins-db8500.h"
 
-/* MSP1/3 Tx/Rx usage protection */
-static DEFINE_SPINLOCK(msp_rxtx_lock);
-
-/* Reference Count */
-static int msp_rxtx_ref;
-
-/* Pin modes */
-struct pinctrl *msp1_p;
-struct pinctrl_state *msp1_def;
-struct pinctrl_state *msp1_sleep;
-
-int msp13_i2s_init(void)
-{
-        int retval = 0;
-        unsigned long flags;
-
-        spin_lock_irqsave(&msp_rxtx_lock, flags);
-        if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) {
-                retval = pinctrl_select_state(msp1_p, msp1_def);
-                if (retval)
-                        pr_err("could not set MSP1 defstate\n");
-        }
-        if (!retval)
-                msp_rxtx_ref++;
-        spin_unlock_irqrestore(&msp_rxtx_lock, flags);
-
-        return retval;
-}
-
-int msp13_i2s_exit(void)
-{
-        int retval = 0;
-        unsigned long flags;
-
-        spin_lock_irqsave(&msp_rxtx_lock, flags);
-        WARN_ON(!msp_rxtx_ref);
-        msp_rxtx_ref--;
-        if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) {
-                retval = pinctrl_select_state(msp1_p, msp1_sleep);
-                if (retval)
-                        pr_err("could not set MSP1 sleepstate\n");
-        }
-        spin_unlock_irqrestore(&msp_rxtx_lock, flags);
-
-        return retval;
-}
-
 static struct stedma40_chan_cfg msp0_dma_rx = {
         .high_priority = true,
         .dir = STEDMA40_PERIPH_TO_MEM,
@@ -96,7 +48,7 @@ static struct stedma40_chan_cfg msp0_dma_tx = {
         /* data_width is set during configuration */
 };
 
-static struct msp_i2s_platform_data msp0_platform_data = {
+struct msp_i2s_platform_data msp0_platform_data = {
         .id = MSP_I2S_0,
         .msp_i2s_dma_rx = &msp0_dma_rx,
         .msp_i2s_dma_tx = &msp0_dma_tx,
@@ -128,12 +80,10 @@ static struct stedma40_chan_cfg msp1_dma_tx = {
         /* data_width is set during configuration */
 };
 
-static struct msp_i2s_platform_data msp1_platform_data = {
+struct msp_i2s_platform_data msp1_platform_data = {
         .id = MSP_I2S_1,
         .msp_i2s_dma_rx = NULL,
         .msp_i2s_dma_tx = &msp1_dma_tx,
-        .msp_i2s_init = msp13_i2s_init,
-        .msp_i2s_exit = msp13_i2s_exit,
 };
 
 static struct stedma40_chan_cfg msp2_dma_rx = {
@@ -193,11 +143,11 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent,
 
 /* Platform device for ASoC MOP500 machine */
 static struct platform_device snd_soc_mop500 = {
-                .name = "snd-soc-mop500",
-                .id = 0,
-                .dev = {
-                        .platform_data = NULL,
-                },
+        .name = "snd-soc-mop500",
+        .id = 0,
+        .dev = {
+                .platform_data = NULL,
+        },
 };
 
 /* Platform device for Ux500-PCM */
@@ -209,59 +159,37 @@ static struct platform_device ux500_pcm = {
                 },
 };
 
-static struct msp_i2s_platform_data msp2_platform_data = {
+struct msp_i2s_platform_data msp2_platform_data = {
         .id = MSP_I2S_2,
         .msp_i2s_dma_rx = &msp2_dma_rx,
         .msp_i2s_dma_tx = &msp2_dma_tx,
 };
 
-static struct msp_i2s_platform_data msp3_platform_data = {
+struct msp_i2s_platform_data msp3_platform_data = {
         .id             = MSP_I2S_3,
         .msp_i2s_dma_rx = &msp1_dma_rx,
         .msp_i2s_dma_tx = NULL,
-        .msp_i2s_init = msp13_i2s_init,
-        .msp_i2s_exit = msp13_i2s_exit,
 };
 
-int mop500_msp_init(struct device *parent)
+void mop500_audio_init(struct device *parent)
 {
-        struct platform_device *msp1;
-
         pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
         platform_device_register(&snd_soc_mop500);
 
         pr_info("Initialize MSP I2S-devices.\n");
         db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
                            &msp0_platform_data);
-        msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
+        db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
                            &msp1_platform_data);
         db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
                            &msp2_platform_data);
         db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
                            &msp3_platform_data);
+}
 
-        /* Get the pinctrl handle for MSP1 */
-        if (msp1) {
-                msp1_p = pinctrl_get(&msp1->dev);
-                if (IS_ERR(msp1_p))
-                        dev_err(&msp1->dev, "could not get MSP1 pinctrl\n");
-                else {
-                        msp1_def = pinctrl_lookup_state(msp1_p,
-                                                        PINCTRL_STATE_DEFAULT);
-                        if (IS_ERR(msp1_def)) {
-                                dev_err(&msp1->dev,
-                                        "could not get MSP1 defstate\n");
-                        }
-                        msp1_sleep = pinctrl_lookup_state(msp1_p,
-                                                          PINCTRL_STATE_SLEEP);
-                        if (IS_ERR(msp1_sleep))
-                                dev_err(&msp1->dev,
-                                        "could not get MSP1 idlestate\n");
-                }
-        }
-
+/* Due for removal once the MSP driver has been fully DT:ed. */
+void mop500_of_audio_init(struct device *parent)
+{
         pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
         platform_device_register(&ux500_pcm);
-
-        return 0;
 }
diff --git a/arch/arm/mach-ux500/board-mop500-msp.h b/arch/arm/mach-ux500/board-mop500-msp.h
deleted file mode 100644
index 6fcfb5e2cc94..000000000000
--- a/arch/arm/mach-ux500/board-mop500-msp.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2012
- *
- * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
- *         for ST-Ericsson.
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-void mop500_msp_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 32fd99204464..a267c6d30e37 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -30,16 +30,15 @@ static enum custom_pin_cfg_t pinsfor;
 #define BIAS(a,b) static unsigned long a[] = { b }
 
 BIAS(pd, PIN_PULL_DOWN);
-BIAS(slpm_gpio_nopull, PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
 BIAS(in_nopull, PIN_INPUT_NOPULL);
-BIAS(in_nopull_sleep_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
+BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
 BIAS(in_pu, PIN_INPUT_PULLUP);
 BIAS(in_pd, PIN_INPUT_PULLDOWN);
 BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP);
 BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW);
 BIAS(out_hi, PIN_OUTPUT_HIGH);
 BIAS(out_lo, PIN_OUTPUT_LOW);
-BIAS(out_lo_sleep_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
+BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
 /* These also force them into GPIO mode */
 BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
 BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
@@ -48,23 +47,32 @@ BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SL
 BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
 BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
 /* Sleep modes */
-BIAS(sleep_in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(sleep_in_nopull_wkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE);
-BIAS(sleep_out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(sleep_out_lo_wkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
-BIAS(sleep_out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
+BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
+BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
 
 /* We use these to define hog settings that are always done on boot */
 #define DB8500_MUX_HOG(group,func) \
         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
 #define DB8500_PIN_HOG(pin,conf) \
         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
+#define DB8500_PIN_SLEEP(pin, conf, dev) \
+        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
+                            pin, conf)
 
 /* These are default states associated with device and changed runtime */
 #define DB8500_MUX(group,func,dev) \
         PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
 #define DB8500_PIN(pin,conf,dev) \
         PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
+#define DB8500_PIN_SLEEP(pin, conf, dev) \
+        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
+                            pin, conf)
 
 #define DB8500_PIN_SLEEP(pin,conf,dev) \
         PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
@@ -134,40 +142,47 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
         DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
         /* UART0 sleep state */
-        DB8500_PIN_SLEEP("GPIO0_AJ5", sleep_in_wkup_pdis, "uart0"),
-        DB8500_PIN_SLEEP("GPIO1_AJ3", sleep_out_hi_wkup_pdis, "uart0"),
-        DB8500_PIN_SLEEP("GPIO2_AH4", sleep_in_wkup_pdis, "uart0"),
-        DB8500_PIN_SLEEP("GPIO3_AH3", sleep_out_wkup_pdis, "uart0"),
+        DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
+        DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
+        DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
+        DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
         /* MSP1 for ALSA codec */
         DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
         DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO33_AF2", out_lo_sleep_nowkup, "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO34_AE1", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO35_AE2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO36_AG2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN("GPIO33_AF2", out_lo_slpm_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN("GPIO34_AE1", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN("GPIO35_AE2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN("GPIO36_AG2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
         /* MSP1 sleep state */
-        DB8500_PIN_SLEEP("GPIO33_AF2", sleep_out_lo_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO34_AE1", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO35_AE2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO36_AG2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_SLEEP("GPIO33_AF2", slpm_out_lo_wkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_SLEEP("GPIO34_AE1", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_SLEEP("GPIO35_AE2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_SLEEP("GPIO36_AG2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
         /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
         DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
         DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
         /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
         DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"),
-        /* Mux in I2C blocks, put pins into GPIO in sleepmode no pull-up */
+        /* Mux in i2c0 block, default state */
         DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
-        DB8500_PIN("GPIO147_C15", slpm_gpio_nopull, "nmk-i2c.0"),
-        DB8500_PIN("GPIO148_B16", slpm_gpio_nopull, "nmk-i2c.0"),
+        /* i2c0 sleep state */
+        DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
+        DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
+        /* Mux in i2c1 block, default state  */
         DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
-        DB8500_PIN("GPIO16_AD3", slpm_gpio_nopull, "nmk-i2c.1"),
-        DB8500_PIN("GPIO17_AD4", slpm_gpio_nopull, "nmk-i2c.1"),
+        /* i2c1 sleep state */
+        DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
+        DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
+        /* Mux in i2c2 block, default state  */
         DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
-        DB8500_PIN("GPIO10_AF5", slpm_gpio_nopull, "nmk-i2c.2"),
-        DB8500_PIN("GPIO11_AG4", slpm_gpio_nopull, "nmk-i2c.2"),
+        /* i2c2 sleep state */
+        DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
+        DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
+        /* Mux in i2c3 block, default state  */
         DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
-        DB8500_PIN("GPIO229_AG7", slpm_gpio_nopull, "nmk-i2c.3"),
-        DB8500_PIN("GPIO230_AF7", slpm_gpio_nopull, "nmk-i2c.3"),
+        /* i2c3 sleep state */
+        DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
+        DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
         /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
         DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
         DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
@@ -219,11 +234,15 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
         DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
         /* Mux in SPI2 pins on the "other C1" altfunction */
-        DB8500_MUX("spi2_oc1_1", "spi2", "spi2"),
+        DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
         DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
         DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
         DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
         DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
+        /* SPI2 sleep state */
+        DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
+        DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
+        DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
 };
 
 /*
@@ -410,7 +429,7 @@ static struct pinctrl_map __initdata u9500_pinmap[] = {
         DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
         /* HSI */
         DB8500_MUX_HOG("hsir_a_1", "hsi"),
-        DB8500_MUX_HOG("hsit_a_1", "hsi"),
+        DB8500_MUX_HOG("hsit_a_2", "hsi"),
         DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
         DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
         DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
@@ -418,7 +437,7 @@ static struct pinctrl_map __initdata u9500_pinmap[] = {
         DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
         DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
         DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
-        DB8500_PIN_HOG("GPIO226_AF8", out_hi), /* ACWAKE0 */
+        DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
 };
 
 static struct pinctrl_map __initdata u8500_pinmap[] = {
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 52426a425787..2a17bc506cff 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -13,6 +13,21 @@
 #include <linux/regulator/ab8500.h>
 #include "board-mop500-regulators.h"
 
+static struct regulator_consumer_supply gpio_en_3v3_consumers[] = {
+       REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
+};
+
+struct regulator_init_data gpio_en_3v3_regulator = {
+       .constraints = {
+               .name = "EN-3V3",
+               .min_uV = 3300000,
+               .max_uV = 3300000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+       },
+       .num_consumer_supplies = ARRAY_SIZE(gpio_en_3v3_consumers),
+       .consumer_supplies = gpio_en_3v3_consumers,
+};
+
 /*
  * TPS61052 regulator
  */
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
index 94992158d962..78a0642a2206 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.h
+++ b/arch/arm/mach-ux500/board-mop500-regulators.h
@@ -18,5 +18,6 @@ extern struct ab8500_regulator_reg_init
 ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS];
 extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS];
 extern struct regulator_init_data tps61052_regulator;
+extern struct regulator_init_data gpio_en_3v3_regulator;
 
 #endif
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 18ff781cfbe4..9c8e4a9e83ee 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -152,7 +152,7 @@ static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
 };
 #endif
 
-static struct mmci_platform_data mop500_sdi1_data = {
+struct mmci_platform_data mop500_sdi1_data = {
         .ocr_mask       = MMC_VDD_29_30,
         .f_max          = 50000000,
         .capabilities   = MMC_CAP_4_BIT_DATA,
@@ -189,7 +189,7 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
 };
 #endif
 
-static struct mmci_platform_data mop500_sdi2_data = {
+struct mmci_platform_data mop500_sdi2_data = {
         .ocr_mask       = MMC_VDD_165_195,
         .f_max          = 50000000,
         .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 7ebfcc7d7515..416d436111f2 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -23,6 +23,7 @@
 #include <linux/spi/spi.h>
 #include <linux/mfd/abx500/ab8500.h>
 #include <linux/regulator/ab8500.h>
+#include <linux/regulator/fixed.h>
 #include <linux/mfd/tc3589x.h>
 #include <linux/mfd/tps6105x.h>
 #include <linux/mfd/abx500/ab8500-gpio.h>
@@ -54,7 +55,6 @@
 #include "devices-db8500.h"
 #include "board-mop500.h"
 #include "board-mop500-regulators.h"
-#include "board-mop500-msp.h"
 
 static struct gpio_led snowball_led_array[] = {
         {
@@ -76,6 +76,23 @@ static struct platform_device snowball_led_dev = {
         },
 };
 
+static struct fixed_voltage_config snowball_gpio_en_3v3_data = {
+       .supply_name            = "EN-3V3",
+       .gpio                   = SNOWBALL_EN_3V3_ETH_GPIO,
+       .microvolts             = 3300000,
+       .enable_high            = 1,
+       .init_data              = &gpio_en_3v3_regulator,
+       .startup_delay          = 5000, /* 1200us */
+};
+
+static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
+       .name   = "reg-fixed-voltage",
+       .id     = 1,
+       .dev    = {
+               .platform_data  = &snowball_gpio_en_3v3_data,
+       },
+};
+
 static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
         .gpio_base              = MOP500_AB8500_PIN_GPIO(1),
         .irq_base               = MOP500_AB8500_VIR_GPIO_IRQ_BASE,
@@ -565,6 +582,7 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
         &snowball_led_dev,
         &snowball_key_dev,
         &snowball_sbnet_dev,
+        &snowball_gpio_en_3v3_regulator_dev,
 };
 
 static void __init mop500_init_machine(void)
@@ -587,7 +605,7 @@ static void __init mop500_init_machine(void)
         mop500_i2c_init(parent);
         mop500_sdi_init(parent);
         mop500_spi_init(parent);
-        mop500_msp_init(parent);
+        mop500_audio_init(parent);
         mop500_uart_init(parent);
 
         u8500_cryp1_hash1_init(parent);
@@ -621,7 +639,7 @@ static void __init snowball_init_machine(void)
         mop500_i2c_init(parent);
         snowball_sdi_init(parent);
         mop500_spi_init(parent);
-        mop500_msp_init(parent);
+        mop500_audio_init(parent);
         mop500_uart_init(parent);
 
         /* This board has full regulator constraints */
@@ -653,7 +671,7 @@ static void __init hrefv60_init_machine(void)
         mop500_i2c_init(parent);
         hrefv60_sdi_init(parent);
         mop500_spi_init(parent);
-        mop500_msp_init(parent);
+        mop500_audio_init(parent);
         mop500_uart_init(parent);
 
         i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -708,12 +726,9 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_UX500_DT
 
-static struct platform_device *snowball_of_platform_devs[] __initdata = {
-        &snowball_led_dev,
-        &snowball_key_dev,
-};
-
 struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
+        /* Requires call-back bindings. */
+        OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
         /* Requires DMA and call-back bindings. */
         OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
         OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
@@ -721,6 +736,8 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         /* Requires DMA bindings. */
         OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
         OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
+        OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
+        OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  &mop500_sdi2_data),
         OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  &mop500_sdi4_data),
         /* Requires clock name bindings. */
         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
@@ -739,6 +756,15 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
         /* Requires device name bindings. */
         OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
+        /* Requires clock name and DMA bindings. */
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
+                "ux500-msp-i2s.0", &msp0_platform_data),
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
+                "ux500-msp-i2s.1", &msp1_platform_data),
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
+                "ux500-msp-i2s.2", &msp2_platform_data),
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
+                "ux500-msp-i2s.3", &msp3_platform_data),
         {},
 };
 
@@ -779,7 +805,7 @@ static void __init u8500_init_machine(void)
                                 ARRAY_SIZE(mop500_platform_devs));
 
                 mop500_sdi_init(parent);
-                mop500_msp_init(parent);
+                mop500_audio_init(parent);
                 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
                 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
                 i2c_register_board_info(2, mop500_i2c2_devices,
@@ -788,7 +814,7 @@ static void __init u8500_init_machine(void)
                 mop500_uib_init();
 
         } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
-                mop500_msp_init(parent);
+                mop500_of_audio_init(parent);
         } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
                 /*
                  * The HREFv60 board removed a GPIO expander and routed
@@ -799,16 +825,6 @@ static void __init u8500_init_machine(void)
                 platform_add_devices(mop500_platform_devs,
                                 ARRAY_SIZE(mop500_platform_devs));
 
-                hrefv60_sdi_init(parent);
-                mop500_msp_init(parent);
-
-                i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
-                i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
-
-                i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
-                i2c_register_board_info(2, mop500_i2c2_devices,
-                                        ARRAY_SIZE(mop500_i2c2_devices));
-
                 mop500_uib_init();
         }
 
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index b5bfc1a78b1a..aca39a68712a 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -9,6 +9,7 @@
 
 /* For NOMADIK_NR_GPIO */
 #include <mach/irqs.h>
+#include <mach/msp.h>
 #include <linux/amba/mmci.h>
 
 /* Snowball specific GPIO assignments, this board has no GPIO expander */
@@ -80,7 +81,14 @@
 struct device;
 struct i2c_board_info;
 extern struct mmci_platform_data mop500_sdi0_data;
+extern struct mmci_platform_data mop500_sdi1_data;
+extern struct mmci_platform_data mop500_sdi2_data;
 extern struct mmci_platform_data mop500_sdi4_data;
+extern struct msp_i2s_platform_data msp0_platform_data;
+extern struct msp_i2s_platform_data msp1_platform_data;
+extern struct msp_i2s_platform_data msp2_platform_data;
+extern struct msp_i2s_platform_data msp3_platform_data;
+extern struct arm_pmu_platdata db8500_pmu_platdata;
 
 extern void mop500_sdi_init(struct device *parent);
 extern void snowball_sdi_init(struct device *parent);
@@ -91,6 +99,9 @@ void __init mop500_stuib_init(void);
 void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
 void __init hrefv60_pinmaps_init(void);
+void mop500_audio_init(struct device *parent);
+/* Due for removal once the MSP driver has been fully DT:ed. */
+void mop500_of_audio_init(struct device *parent);
 
 int __init mop500_uib_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index aef2c68e9ec1..bcdfe6b1d453 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -18,6 +18,7 @@
 #include <linux/io.h>
 #include <linux/mfd/abx500/ab8500.h>
 
+#include <asm/pmu.h>
 #include <asm/mach/map.h>
 #include <plat/gpio-nomadik.h>
 #include <mach/hardware.h>
@@ -137,10 +138,6 @@ static struct platform_device *platform_devs[] __initdata = {
         &db8500_prcmu_device,
 };
 
-static struct platform_device *of_platform_devs[] __initdata = {
-        &u8500_dma40_device,
-};
-
 static resource_size_t __initdata db8500_gpio_base[] = {
         U8500_GPIOBANK0_BASE,
         U8500_GPIOBANK1_BASE,
@@ -234,7 +231,6 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
 struct device * __init u8500_of_init_devices(void)
 {
         struct device *parent;
-        int i;
 
         parent = db8500_soc_device_init();
 
@@ -243,8 +239,7 @@ struct device * __init u8500_of_init_devices(void)
         platform_device_register_data(parent,
                 "cpufreq-u8500", -1, NULL, 0);
 
-        for (i = 0; i < ARRAY_SIZE(of_platform_devs); i++)
-                of_platform_devs[i]->dev.parent = parent;
+        u8500_dma40_device.dev.parent = parent;
 
         /*
          * Devices to be DT:ed:
@@ -252,7 +247,7 @@ struct device * __init u8500_of_init_devices(void)
          *   db8500_pmu_device   = done
          *   db8500_prcmu_device = done
          */
-        platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs));
+        platform_device_register(&u8500_dma40_device);
 
         return parent;
 }
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 3d62c64c84c4..2236cbd03cd7 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -49,6 +49,8 @@ void __init ux500_init_irq(void)
         void __iomem *dist_base;
         void __iomem *cpu_base;
 
+        gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+
         if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
                 dist_base = __io_address(U8500_GIC_DIST_BASE);
                 cpu_base = __io_address(U8500_GIC_CPU_BASE);
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h
index 798be19129ef..3cc7142eee02 100644
--- a/arch/arm/mach-ux500/include/mach/msp.h
+++ b/arch/arm/mach-ux500/include/mach/msp.h
@@ -22,8 +22,6 @@ struct msp_i2s_platform_data {
         enum msp_i2s_id id;
         struct stedma40_chan_cfg *msp_i2s_dma_rx;
         struct stedma40_chan_cfg *msp_i2s_dma_tx;
-        int (*msp_i2s_init) (void);
-        int (*msp_i2s_exit) (void);
 };
 
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 34775baadaea..d60ecd1753f0 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -24,7 +24,7 @@
 #include <linux/amba/serial.h>
 #include <mach/hardware.h>
 
-u32 ux500_uart_base;
+void __iomem *ux500_uart_base;
 
 static void putc(const char c)
 {
@@ -51,7 +51,7 @@ static void flush(void)
 static inline void arch_decomp_setup(void)
 {
         /* Use machine_is_foo() macro if you need to switch base someday */
-        ux500_uart_base = U8500_UART2_BASE;
+        ux500_uart_base = (void __iomem *)U8500_UART2_BASE;
 }
 
 #define arch_decomp_wdog() /* nothing to do here */
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index ca7902c6ed18..5b5c1eeb5b5c 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -37,7 +37,6 @@
 #include <linux/mtd/physmap.h>
 
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst.h>
 #include <asm/hardware/vic.h>
@@ -758,10 +757,6 @@ void __init versatile_init(void)
                 struct amba_device *d = amba_devs[i];
                 amba_device_register(d, &iomem_resource);
         }
-
-#ifdef CONFIG_LEDS
-        leds_event = versatile_leds_event;
-#endif
 }
 
 /*
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 5f6b7d543e55..560e0df728f8 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -659,6 +659,7 @@ static void __init v2m_dt_init(void)
 
 const static char *v2m_dt_match[] __initconst = {
         "arm,vexpress",
+        "xen,xenvm",
         NULL,
 };
 
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
deleted file mode 100644
index 2c20a341c11a..000000000000
--- a/arch/arm/mach-vt8500/Kconfig
+++ /dev/null
@@ -1,73 +0,0 @@
-if ARCH_VT8500
-
-config VTWM_VERSION_VT8500
-        bool
-
-config VTWM_VERSION_WM8505
-        bool
-
-config MACH_BV07
-        bool "Benign BV07-8500 Mini Netbook"
-        depends on ARCH_VT8500
-        select VTWM_VERSION_VT8500
-        help
-          Add support for the inexpensive 7-inch netbooks sold by many
-          Chinese distributors under various names. Note that there are
-          many hardware implementations in identical exterior, make sure
-          that yours is indeed based on a VIA VT8500 chip.
-
-config MACH_WM8505_7IN_NETBOOK
-        bool "WM8505 7-inch generic netbook"
-        depends on ARCH_VT8500
-        select VTWM_VERSION_WM8505
-        help
-          Add support for the inexpensive 7-inch netbooks sold by many
-          Chinese distributors under various names. Note that there are
-          many hardware implementations in identical exterior, make sure
-          that yours is indeed based on a WonderMedia WM8505 chip.
-
-comment "LCD panel size"
-
-config WMT_PANEL_800X480
-        bool "7-inch with 800x480 resolution"
-        depends on (FB_VT8500 || FB_WM8505)
-        default y
-        help
-          These are found in most of the netbooks in generic cases, as
-          well as in Eken M001 tablets and possibly elsewhere.
-
-          To select this panel at runtime, say y here and append
-          'panel=800x480' to your kernel command line. Otherwise, the
-          largest one available will be used.
-
-config WMT_PANEL_800X600
-        bool "8-inch with 800x600 resolution"
-        depends on (FB_VT8500 || FB_WM8505)
-        help
-          These are found in Eken M003 tablets and possibly elsewhere.
-
-          To select this panel at runtime, say y here and append
-          'panel=800x600' to your kernel command line. Otherwise, the
-          largest one available will be used.
-
-config WMT_PANEL_1024X576
-        bool "10-inch with 1024x576 resolution"
-        depends on (FB_VT8500 || FB_WM8505)
-        help
-          These are found in CherryPal netbooks and possibly elsewhere.
-
-          To select this panel at runtime, say y here and append
-          'panel=1024x576' to your kernel command line. Otherwise, the
-          largest one available will be used.
-
-config WMT_PANEL_1024X600
-        bool "10-inch with 1024x600 resolution"
-        depends on (FB_VT8500 || FB_WM8505)
-        help
-          These are found in Eken M006 tablets and possibly elsewhere.
-
-          To select this panel at runtime, say y here and append
-          'panel=1024x600' to your kernel command line. Otherwise, the
-          largest one available will be used.
-
-endif
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index 7ce51767c99c..e035251cda48 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -1,7 +1 @@
-obj-y += devices.o gpio.o irq.o timer.o restart.o
-
-obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o
-obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o
-
-obj-$(CONFIG_MACH_BV07) += bv07.o
-obj-$(CONFIG_MACH_WM8505_7IN_NETBOOK) += wm8505_7in.o
+obj-$(CONFIG_ARCH_VT8500) += irq.o timer.o vt8500.o
diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c
deleted file mode 100644
index f9fbeb2d10e9..000000000000
--- a/arch/arm/mach-vt8500/bv07.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/bv07.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/io.h>
-#include <linux/pm.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/restart.h>
-
-#include "devices.h"
-
-static void __iomem *pmc_hiber;
-
-static struct platform_device *devices[] __initdata = {
-        &vt8500_device_uart0,
-        &vt8500_device_lcdc,
-        &vt8500_device_ehci,
-        &vt8500_device_ge_rops,
-        &vt8500_device_pwm,
-        &vt8500_device_pwmbl,
-        &vt8500_device_rtc,
-};
-
-static void vt8500_power_off(void)
-{
-        local_irq_disable();
-        writew(5, pmc_hiber);
-        asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
-}
-
-void __init bv07_init(void)
-{
-#ifdef CONFIG_FB_VT8500
-        void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4);
-        if (gpio_mux_reg) {
-                writel(readl(gpio_mux_reg) | 1, gpio_mux_reg);
-                iounmap(gpio_mux_reg);
-        } else {
-                printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n");
-        }
-#endif
-        pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2);
-        if (pmc_hiber)
-                pm_power_off = &vt8500_power_off;
-        else
-                printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-
-        wmt_setup_restart();
-        vt8500_set_resources();
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-        vt8500_gpio_init();
-}
-
-MACHINE_START(BV07, "Benign BV07 Mini Netbook")
-        .atag_offset    = 0x100,
-        .restart        = wmt_restart,
-        .reserve        = vt8500_reserve_mem,
-        .map_io         = vt8500_map_io,
-        .init_irq       = vt8500_init_irq,
-        .timer          = &vt8500_timer,
-        .init_machine   = bv07_init,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/include/mach/gpio-tegra.h b/arch/arm/mach-vt8500/common.h
index a978b3cc3a8d..2b2419646e95 100644
--- a/arch/arm/mach-tegra/include/mach/gpio-tegra.h
+++ b/arch/arm/mach-vt8500/common.h
@@ -1,10 +1,6 @@
-/*
- * arch/arm/mach-tegra/include/mach/gpio.h
+/* linux/arch/arm/mach-vt8500/dt_common.h
  *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Erik Gilling <konkers@google.com>
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -17,12 +13,16 @@
  *
  */
 
-#ifndef __MACH_TEGRA_GPIO_TEGRA_H
-#define __MACH_TEGRA_GPIO_TEGRA_H
+#ifndef __ARCH_ARM_MACH_VT8500_DT_COMMON_H
+#define __ARCH_ARM_MACH_VT8500_DT_COMMON_H
+
+#include <linux/of.h>
 
-#include <linux/types.h>
-#include <mach/irqs.h>
+void __init vt8500_timer_init(void);
+int __init vt8500_irq_init(struct device_node *node,
+                                struct device_node *parent);
 
-#define TEGRA_NR_GPIOS          INT_GPIO_NR
+/* defined in drivers/clk/clk-vt8500.c */
+void __init vtwm_clk_init(void __iomem *pmc_base);
 
 #endif
diff --git a/arch/arm/mach-vt8500/devices-vt8500.c b/arch/arm/mach-vt8500/devices-vt8500.c
deleted file mode 100644
index 19519aeecf37..000000000000
--- a/arch/arm/mach-vt8500/devices-vt8500.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices-vt8500.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/platform_device.h>
-
-#include <mach/vt8500_regs.h>
-#include <mach/vt8500_irqs.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-void __init vt8500_set_resources(void)
-{
-        struct resource tmp[3];
-
-        tmp[0] = wmt_mmio_res(VT8500_LCDC_BASE, SZ_1K);
-        tmp[1] = wmt_irq_res(IRQ_LCDC);
-        wmt_res_add(&vt8500_device_lcdc, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(VT8500_UART0_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART0);
-        wmt_res_add(&vt8500_device_uart0, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(VT8500_UART1_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART1);
-        wmt_res_add(&vt8500_device_uart1, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(VT8500_UART2_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART2);
-        wmt_res_add(&vt8500_device_uart2, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(VT8500_UART3_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART3);
-        wmt_res_add(&vt8500_device_uart3, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(VT8500_EHCI_BASE, SZ_512);
-        tmp[1] = wmt_irq_res(IRQ_EHCI);
-        wmt_res_add(&vt8500_device_ehci, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(VT8500_GEGEA_BASE, SZ_256);
-        wmt_res_add(&vt8500_device_ge_rops, tmp, 1);
-
-        tmp[0] = wmt_mmio_res(VT8500_PWM_BASE, 0x44);
-        wmt_res_add(&vt8500_device_pwm, tmp, 1);
-
-        tmp[0] = wmt_mmio_res(VT8500_RTC_BASE, 0x2c);
-        tmp[1] = wmt_irq_res(IRQ_RTC);
-        tmp[2] = wmt_irq_res(IRQ_RTCSM);
-        wmt_res_add(&vt8500_device_rtc, tmp, 3);
-}
-
-static void __init vt8500_set_externs(void)
-{
-        /* Non-resource-aware stuff */
-        wmt_ic_base = VT8500_IC_BASE;
-        wmt_gpio_base = VT8500_GPIO_BASE;
-        wmt_pmc_base = VT8500_PMC_BASE;
-        wmt_i8042_base = VT8500_PS2_BASE;
-
-        wmt_nr_irqs = VT8500_NR_IRQS;
-        wmt_timer_irq = IRQ_PMCOS0;
-        wmt_gpio_ext_irq[0] = IRQ_EXT0;
-        wmt_gpio_ext_irq[1] = IRQ_EXT1;
-        wmt_gpio_ext_irq[2] = IRQ_EXT2;
-        wmt_gpio_ext_irq[3] = IRQ_EXT3;
-        wmt_gpio_ext_irq[4] = IRQ_EXT4;
-        wmt_gpio_ext_irq[5] = IRQ_EXT5;
-        wmt_gpio_ext_irq[6] = IRQ_EXT6;
-        wmt_gpio_ext_irq[7] = IRQ_EXT7;
-        wmt_i8042_kbd_irq = IRQ_PS2KBD;
-        wmt_i8042_aux_irq = IRQ_PS2MOUSE;
-}
-
-void __init vt8500_map_io(void)
-{
-        iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-
-        /* Should be done before interrupts and timers are initialized */
-        vt8500_set_externs();
-}
diff --git a/arch/arm/mach-vt8500/devices-wm8505.c b/arch/arm/mach-vt8500/devices-wm8505.c
deleted file mode 100644
index db4594e029f4..000000000000
--- a/arch/arm/mach-vt8500/devices-wm8505.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices-wm8505.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/platform_device.h>
-
-#include <mach/wm8505_regs.h>
-#include <mach/wm8505_irqs.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-void __init wm8505_set_resources(void)
-{
-        struct resource tmp[3];
-
-        tmp[0] = wmt_mmio_res(WM8505_GOVR_BASE, SZ_512);
-        wmt_res_add(&vt8500_device_wm8505_fb, tmp, 1);
-
-        tmp[0] = wmt_mmio_res(WM8505_UART0_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART0);
-        wmt_res_add(&vt8500_device_uart0, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_UART1_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART1);
-        wmt_res_add(&vt8500_device_uart1, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_UART2_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART2);
-        wmt_res_add(&vt8500_device_uart2, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_UART3_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART3);
-        wmt_res_add(&vt8500_device_uart3, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_UART4_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART4);
-        wmt_res_add(&vt8500_device_uart4, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_UART5_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART5);
-        wmt_res_add(&vt8500_device_uart5, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_EHCI_BASE, SZ_512);
-        tmp[1] = wmt_irq_res(IRQ_EHCI);
-        wmt_res_add(&vt8500_device_ehci, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_GEGEA_BASE, SZ_256);
-        wmt_res_add(&vt8500_device_ge_rops, tmp, 1);
-
-        tmp[0] = wmt_mmio_res(WM8505_PWM_BASE, 0x44);
-        wmt_res_add(&vt8500_device_pwm, tmp, 1);
-
-        tmp[0] = wmt_mmio_res(WM8505_RTC_BASE, 0x2c);
-        tmp[1] = wmt_irq_res(IRQ_RTC);
-        tmp[2] = wmt_irq_res(IRQ_RTCSM);
-        wmt_res_add(&vt8500_device_rtc, tmp, 3);
-}
-
-static void __init wm8505_set_externs(void)
-{
-        /* Non-resource-aware stuff */
-        wmt_ic_base = WM8505_IC_BASE;
-        wmt_sic_base = WM8505_SIC_BASE;
-        wmt_gpio_base = WM8505_GPIO_BASE;
-        wmt_pmc_base = WM8505_PMC_BASE;
-        wmt_i8042_base = WM8505_PS2_BASE;
-
-        wmt_nr_irqs = WM8505_NR_IRQS;
-        wmt_timer_irq = IRQ_PMCOS0;
-        wmt_gpio_ext_irq[0] = IRQ_EXT0;
-        wmt_gpio_ext_irq[1] = IRQ_EXT1;
-        wmt_gpio_ext_irq[2] = IRQ_EXT2;
-        wmt_gpio_ext_irq[3] = IRQ_EXT3;
-        wmt_gpio_ext_irq[4] = IRQ_EXT4;
-        wmt_gpio_ext_irq[5] = IRQ_EXT5;
-        wmt_gpio_ext_irq[6] = IRQ_EXT6;
-        wmt_gpio_ext_irq[7] = IRQ_EXT7;
-        wmt_i8042_kbd_irq = IRQ_PS2KBD;
-        wmt_i8042_aux_irq = IRQ_PS2MOUSE;
-}
-
-void __init wm8505_map_io(void)
-{
-        iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-
-        /* Should be done before interrupts and timers are initialized */
-        wm8505_set_externs();
-}
diff --git a/arch/arm/mach-vt8500/devices.c b/arch/arm/mach-vt8500/devices.c
deleted file mode 100644
index 82b4bcedffba..000000000000
--- a/arch/arm/mach-vt8500/devices.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/pwm_backlight.h>
-#include <linux/memblock.h>
-
-#include <asm/mach/arch.h>
-
-#include <linux/platform_data/video-vt8500lcdfb.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-/* These can't use resources currently */
-unsigned long wmt_ic_base __initdata;
-unsigned long wmt_sic_base __initdata;
-unsigned long wmt_gpio_base __initdata;
-unsigned long wmt_pmc_base __initdata;
-unsigned long wmt_i8042_base __initdata;
-
-int wmt_nr_irqs __initdata;
-int wmt_timer_irq __initdata;
-int wmt_gpio_ext_irq[8] __initdata;
-
-/* Should remain accessible after init.
- * i8042 driver desperately calls for attention...
- */
-int wmt_i8042_kbd_irq;
-int wmt_i8042_aux_irq;
-
-static u64 fb_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device vt8500_device_lcdc = {
-        .name           = "vt8500-lcd",
-        .id             = 0,
-        .dev            = {
-                .dma_mask       = &fb_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-struct platform_device vt8500_device_wm8505_fb = {
-        .name           = "wm8505-fb",
-        .id             = 0,
-};
-
-/* Smallest to largest */
-static struct vt8500fb_platform_data panels[] = {
-#ifdef CONFIG_WMT_PANEL_800X480
-{
-        .xres_virtual   = 800,
-        .yres_virtual   = 480 * 2,
-        .mode           = {
-                .name           = "800x480",
-                .xres           = 800,
-                .yres           = 480,
-                .left_margin    = 88,
-                .right_margin   = 40,
-                .upper_margin   = 32,
-                .lower_margin   = 11,
-                .hsync_len      = 0,
-                .vsync_len      = 1,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_800X600
-{
-        .xres_virtual   = 800,
-        .yres_virtual   = 600 * 2,
-        .mode           = {
-                .name           = "800x600",
-                .xres           = 800,
-                .yres           = 600,
-                .left_margin    = 88,
-                .right_margin   = 40,
-                .upper_margin   = 32,
-                .lower_margin   = 11,
-                .hsync_len      = 0,
-                .vsync_len      = 1,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_1024X576
-{
-        .xres_virtual   = 1024,
-        .yres_virtual   = 576 * 2,
-        .mode           = {
-                .name           = "1024x576",
-                .xres           = 1024,
-                .yres           = 576,
-                .left_margin    = 40,
-                .right_margin   = 24,
-                .upper_margin   = 32,
-                .lower_margin   = 11,
-                .hsync_len      = 96,
-                .vsync_len      = 2,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_1024X600
-{
-        .xres_virtual   = 1024,
-        .yres_virtual   = 600 * 2,
-        .mode           = {
-                .name           = "1024x600",
-                .xres           = 1024,
-                .yres           = 600,
-                .left_margin    = 66,
-                .right_margin   = 2,
-                .upper_margin   = 19,
-                .lower_margin   = 1,
-                .hsync_len      = 23,
-                .vsync_len      = 8,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-},
-#endif
-};
-
-static int current_panel_idx __initdata = ARRAY_SIZE(panels) - 1;
-
-static int __init panel_setup(char *str)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(panels); i++) {
-                if (strcmp(panels[i].mode.name, str) == 0) {
-                        current_panel_idx = i;
-                        break;
-                }
-        }
-        return 0;
-}
-
-early_param("panel", panel_setup);
-
-static inline void preallocate_fb(struct vt8500fb_platform_data *p,
-                                  unsigned long align) {
-        p->video_mem_len = (p->xres_virtual * p->yres_virtual * 4) >>
-                        (p->bpp > 16 ? 0 : (p->bpp > 8 ? 1 :
-                                        (8 / p->bpp) + 1));
-        p->video_mem_phys = (unsigned long)memblock_alloc(p->video_mem_len,
-                                                          align);
-        p->video_mem_virt = phys_to_virt(p->video_mem_phys);
-}
-
-struct platform_device vt8500_device_uart0 = {
-        .name           = "vt8500_serial",
-        .id             = 0,
-};
-
-struct platform_device vt8500_device_uart1 = {
-        .name           = "vt8500_serial",
-        .id             = 1,
-};
-
-struct platform_device vt8500_device_uart2 = {
-        .name           = "vt8500_serial",
-        .id             = 2,
-};
-
-struct platform_device vt8500_device_uart3 = {
-        .name           = "vt8500_serial",
-        .id             = 3,
-};
-
-struct platform_device vt8500_device_uart4 = {
-        .name           = "vt8500_serial",
-        .id             = 4,
-};
-
-struct platform_device vt8500_device_uart5 = {
-        .name           = "vt8500_serial",
-        .id             = 5,
-};
-
-static u64 ehci_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device vt8500_device_ehci = {
-        .name           = "vt8500-ehci",
-        .id             = 0,
-        .dev            = {
-                .dma_mask       = &ehci_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-struct platform_device vt8500_device_ge_rops = {
-        .name           = "wmt_ge_rops",
-        .id             = -1,
-};
-
-struct platform_device vt8500_device_pwm = {
-        .name           = "vt8500-pwm",
-        .id             = 0,
-};
-
-static struct platform_pwm_backlight_data vt8500_pwmbl_data = {
-        .pwm_id         = 0,
-        .max_brightness = 128,
-        .dft_brightness = 70,
-        .pwm_period_ns  = 250000, /* revisit when clocks are implemented */
-};
-
-struct platform_device vt8500_device_pwmbl = {
-        .name           = "pwm-backlight",
-        .id             = 0,
-        .dev            = {
-                .platform_data = &vt8500_pwmbl_data,
-        },
-};
-
-struct platform_device vt8500_device_rtc = {
-        .name           = "vt8500-rtc",
-        .id             = 0,
-};
-
-struct map_desc wmt_io_desc[] __initdata = {
-        /* SoC MMIO registers */
-        [0] = {
-                .virtual        = 0xf8000000,
-                .pfn            = __phys_to_pfn(0xd8000000),
-                .length         = 0x00390000, /* max of all chip variants */
-                .type           = MT_DEVICE
-        },
-        /* PCI I/O space, numbers tied to those in <mach/io.h> */
-        [1] = {
-                .virtual        = 0xf0000000,
-                .pfn            = __phys_to_pfn(0xc0000000),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE
-        },
-};
-
-void __init vt8500_reserve_mem(void)
-{
-#ifdef CONFIG_FB_VT8500
-        panels[current_panel_idx].bpp = 16; /* Always use RGB565 */
-        preallocate_fb(&panels[current_panel_idx], SZ_4M);
-        vt8500_device_lcdc.dev.platform_data = &panels[current_panel_idx];
-#endif
-}
-
-void __init wm8505_reserve_mem(void)
-{
-#if defined CONFIG_FB_WM8505
-        panels[current_panel_idx].bpp = 32; /* Always use RGB888 */
-        preallocate_fb(&panels[current_panel_idx], 32);
-        vt8500_device_wm8505_fb.dev.platform_data = &panels[current_panel_idx];
-#endif
-}
diff --git a/arch/arm/mach-vt8500/devices.h b/arch/arm/mach-vt8500/devices.h
deleted file mode 100644
index 188d4e17f35c..000000000000
--- a/arch/arm/mach-vt8500/devices.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_VT8500_DEVICES_H
-#define __ARCH_ARM_MACH_VT8500_DEVICES_H
-
-#include <linux/platform_device.h>
-#include <asm/mach/map.h>
-
-void __init vt8500_init_irq(void);
-void __init wm8505_init_irq(void);
-void __init vt8500_map_io(void);
-void __init wm8505_map_io(void);
-void __init vt8500_reserve_mem(void);
-void __init wm8505_reserve_mem(void);
-void __init vt8500_gpio_init(void);
-void __init vt8500_set_resources(void);
-void __init wm8505_set_resources(void);
-
-extern unsigned long wmt_ic_base __initdata;
-extern unsigned long wmt_sic_base __initdata;
-extern unsigned long wmt_gpio_base __initdata;
-extern unsigned long wmt_pmc_base __initdata;
-
-extern int wmt_nr_irqs __initdata;
-extern int wmt_timer_irq __initdata;
-extern int wmt_gpio_ext_irq[8] __initdata;
-
-extern struct map_desc wmt_io_desc[2] __initdata;
-
-static inline struct resource wmt_mmio_res(u32 start, u32 size)
-{
-        struct resource tmp = {
-                .flags = IORESOURCE_MEM,
-                .start = start,
-                .end = start + size - 1,
-        };
-
-        return tmp;
-}
-
-static inline struct resource wmt_irq_res(int irq)
-{
-        struct resource tmp = {
-                .flags = IORESOURCE_IRQ,
-                .start = irq,
-                .end = irq,
-        };
-
-        return tmp;
-}
-
-static inline void wmt_res_add(struct platform_device *pdev,
-                               const struct resource *res, unsigned int num)
-{
-        if (unlikely(platform_device_add_resources(pdev, res, num)))
-                pr_err("Failed to assign resources\n");
-}
-
-extern struct sys_timer vt8500_timer;
-
-extern struct platform_device vt8500_device_uart0;
-extern struct platform_device vt8500_device_uart1;
-extern struct platform_device vt8500_device_uart2;
-extern struct platform_device vt8500_device_uart3;
-extern struct platform_device vt8500_device_uart4;
-extern struct platform_device vt8500_device_uart5;
-
-extern struct platform_device vt8500_device_lcdc;
-extern struct platform_device vt8500_device_wm8505_fb;
-extern struct platform_device vt8500_device_ehci;
-extern struct platform_device vt8500_device_ge_rops;
-extern struct platform_device vt8500_device_pwm;
-extern struct platform_device vt8500_device_pwmbl;
-extern struct platform_device vt8500_device_rtc;
-#endif
diff --git a/arch/arm/mach-vt8500/gpio.c b/arch/arm/mach-vt8500/gpio.c
deleted file mode 100644
index 2bcc0ec783df..000000000000
--- a/arch/arm/mach-vt8500/gpio.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/* linux/arch/arm/mach-vt8500/gpio.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include "devices.h"
-
-#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
-
-#define ENABLE_REGS     0x0
-#define DIRECTION_REGS  0x20
-#define OUTVALUE_REGS   0x40
-#define INVALUE_REGS    0x60
-
-#define EXT_REGOFF      0x1c
-
-static void __iomem *regbase;
-
-struct vt8500_gpio_chip {
-        struct gpio_chip        chip;
-        unsigned int            shift;
-        unsigned int            regoff;
-};
-
-static int gpio_to_irq_map[8];
-
-static int vt8500_muxed_gpio_request(struct gpio_chip *chip,
-                                     unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-        val |= (1 << vt8500_chip->shift << offset);
-        writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-        return 0;
-}
-
-static void vt8500_muxed_gpio_free(struct gpio_chip *chip,
-                                   unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-        val &= ~(1 << vt8500_chip->shift << offset);
-        writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff);
-}
-
-static int vt8500_muxed_gpio_direction_input(struct gpio_chip *chip,
-                                       unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-        val &= ~(1 << vt8500_chip->shift << offset);
-        writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-        return 0;
-}
-
-static int vt8500_muxed_gpio_direction_output(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-        val |= (1 << vt8500_chip->shift << offset);
-        writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-        if (value) {
-                val = readl(regbase + OUTVALUE_REGS + vt8500_chip->regoff);
-                val |= (1 << vt8500_chip->shift << offset);
-                writel(val, regbase + OUTVALUE_REGS + vt8500_chip->regoff);
-        }
-        return 0;
-}
-
-static int vt8500_muxed_gpio_get_value(struct gpio_chip *chip,
-                                       unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-        return (readl(regbase + INVALUE_REGS + vt8500_chip->regoff)
-                >> vt8500_chip->shift >> offset) & 1;
-}
-
-static void vt8500_muxed_gpio_set_value(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + INVALUE_REGS + vt8500_chip->regoff);
-
-        if (value)
-                val |= (1 << vt8500_chip->shift << offset);
-        else
-                val &= ~(1 << vt8500_chip->shift << offset);
-
-        writel(val, regbase + INVALUE_REGS + vt8500_chip->regoff);
-}
-
-#define VT8500_GPIO_BANK(__name, __shift, __off, __base, __num)         \
-{                                                                       \
-        .chip = {                                                       \
-                .label                  = __name,                       \
-                .request                = vt8500_muxed_gpio_request,    \
-                .free                   = vt8500_muxed_gpio_free,       \
-                .direction_input  = vt8500_muxed_gpio_direction_input,  \
-                .direction_output = vt8500_muxed_gpio_direction_output, \
-                .get                    = vt8500_muxed_gpio_get_value,  \
-                .set                    = vt8500_muxed_gpio_set_value,  \
-                .can_sleep              = 0,                            \
-                .base                   = __base,                       \
-                .ngpio                  = __num,                        \
-        },                                                              \
-        .shift          = __shift,                                      \
-        .regoff         = __off,                                        \
-}
-
-static struct vt8500_gpio_chip vt8500_muxed_gpios[] = {
-        VT8500_GPIO_BANK("uart0",       0,      0x0,    8,      4),
-        VT8500_GPIO_BANK("uart1",       4,      0x0,    12,     4),
-        VT8500_GPIO_BANK("spi0",        8,      0x0,    16,     4),
-        VT8500_GPIO_BANK("spi1",        12,     0x0,    20,     4),
-        VT8500_GPIO_BANK("spi2",        16,     0x0,    24,     4),
-        VT8500_GPIO_BANK("pwmout",      24,     0x0,    28,     2),
-
-        VT8500_GPIO_BANK("sdmmc",       0,      0x4,    30,     11),
-        VT8500_GPIO_BANK("ms",          16,     0x4,    41,     7),
-        VT8500_GPIO_BANK("i2c0",        24,     0x4,    48,     2),
-        VT8500_GPIO_BANK("i2c1",        26,     0x4,    50,     2),
-
-        VT8500_GPIO_BANK("mii",         0,      0x8,    52,     20),
-        VT8500_GPIO_BANK("see",         20,     0x8,    72,     4),
-        VT8500_GPIO_BANK("ide",         24,     0x8,    76,     7),
-
-        VT8500_GPIO_BANK("ccir",        0,      0xc,    83,     19),
-
-        VT8500_GPIO_BANK("ts",          8,      0x10,   102,    11),
-
-        VT8500_GPIO_BANK("lcd",         0,      0x14,   113,    23),
-};
-
-static int vt8500_gpio_direction_input(struct gpio_chip *chip,
-                                       unsigned offset)
-{
-        unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF);
-
-        val &= ~(1 << offset);
-        writel(val, regbase + DIRECTION_REGS + EXT_REGOFF);
-        return 0;
-}
-
-static int vt8500_gpio_direction_output(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF);
-
-        val |= (1 << offset);
-        writel(val, regbase + DIRECTION_REGS + EXT_REGOFF);
-
-        if (value) {
-                val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF);
-                val |= (1 << offset);
-                writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF);
-        }
-        return 0;
-}
-
-static int vt8500_gpio_get_value(struct gpio_chip *chip,
-                                       unsigned offset)
-{
-        return (readl(regbase + INVALUE_REGS + EXT_REGOFF) >> offset) & 1;
-}
-
-static void vt8500_gpio_set_value(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        unsigned val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF);
-
-        if (value)
-                val |= (1 << offset);
-        else
-                val &= ~(1 << offset);
-
-        writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF);
-}
-
-static int vt8500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        if (offset > 7)
-                return -EINVAL;
-
-        return gpio_to_irq_map[offset];
-}
-
-static struct gpio_chip vt8500_external_gpios = {
-        .label                  = "extgpio",
-        .direction_input        = vt8500_gpio_direction_input,
-        .direction_output       = vt8500_gpio_direction_output,
-        .get                    = vt8500_gpio_get_value,
-        .set                    = vt8500_gpio_set_value,
-        .to_irq                 = vt8500_gpio_to_irq,
-        .can_sleep              = 0,
-        .base                   = 0,
-        .ngpio                  = 8,
-};
-
-void __init vt8500_gpio_init(void)
-{
-        int i;
-
-        for (i = 0; i < 8; i++)
-                gpio_to_irq_map[i] = wmt_gpio_ext_irq[i];
-
-        regbase = ioremap(wmt_gpio_base, SZ_64K);
-        if (!regbase) {
-                printk(KERN_ERR "Failed to map MMIO registers for GPIO\n");
-                return;
-        }
-
-        gpiochip_add(&vt8500_external_gpios);
-
-        for (i = 0; i < ARRAY_SIZE(vt8500_muxed_gpios); i++)
-                gpiochip_add(&vt8500_muxed_gpios[i].chip);
-}
diff --git a/arch/arm/mach-vt8500/include/mach/restart.h b/arch/arm/mach-vt8500/include/mach/restart.h
index 89f9b787d2a0..738979518acb 100644
--- a/arch/arm/mach-vt8500/include/mach/restart.h
+++ b/arch/arm/mach-vt8500/include/mach/restart.h
@@ -13,5 +13,5 @@
  *
  */
 
-void wmt_setup_restart(void);
-void wmt_restart(char mode, const char *cmd);
+void vt8500_setup_restart(void);
+void vt8500_restart(char mode, const char *cmd);
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h b/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
deleted file mode 100644
index ecfee9124711..000000000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/* VT8500 Interrupt Sources */
-
-#define IRQ_JPEGENC     0       /* JPEG Encoder */
-#define IRQ_JPEGDEC     1       /* JPEG Decoder */
-                                /* Reserved */
-#define IRQ_PATA        3       /* PATA Controller */
-                                /* Reserved */
-#define IRQ_DMA         5       /* DMA Controller */
-#define IRQ_EXT0        6       /* External Interrupt 0 */
-#define IRQ_EXT1        7       /* External Interrupt 1 */
-#define IRQ_GE          8       /* Graphic Engine */
-#define IRQ_GOV         9       /* Graphic Overlay Engine */
-#define IRQ_ETHER       10      /* Ethernet MAC */
-#define IRQ_MPEGTS      11      /* Transport Stream Interface */
-#define IRQ_LCDC        12      /* LCD Controller */
-#define IRQ_EXT2        13      /* External Interrupt 2 */
-#define IRQ_EXT3        14      /* External Interrupt 3 */
-#define IRQ_EXT4        15      /* External Interrupt 4 */
-#define IRQ_CIPHER      16      /* Cipher */
-#define IRQ_VPP         17      /* Video Post-Processor */
-#define IRQ_I2C1        18      /* I2C 1 */
-#define IRQ_I2C0        19      /* I2C 0 */
-#define IRQ_SDMMC       20      /* SD/MMC Controller */
-#define IRQ_SDMMC_DMA   21      /* SD/MMC Controller DMA */
-#define IRQ_PMC_WU      22      /* Power Management Controller Wakeup */
-                                /* Reserved */
-#define IRQ_SPI0        24      /* SPI 0 */
-#define IRQ_SPI1        25      /* SPI 1 */
-#define IRQ_SPI2        26      /* SPI 2 */
-#define IRQ_LCDDF       27      /* LCD Data Formatter */
-#define IRQ_NAND        28      /* NAND Flash Controller */
-#define IRQ_NAND_DMA    29      /* NAND Flash Controller DMA */
-#define IRQ_MS          30      /* MemoryStick Controller */
-#define IRQ_MS_DMA      31      /* MemoryStick Controller DMA */
-#define IRQ_UART0       32      /* UART 0 */
-#define IRQ_UART1       33      /* UART 1 */
-#define IRQ_I2S         34      /* I2S */
-#define IRQ_PCM         35      /* PCM */
-#define IRQ_PMCOS0      36      /* PMC OS Timer 0 */
-#define IRQ_PMCOS1      37      /* PMC OS Timer 1 */
-#define IRQ_PMCOS2      38      /* PMC OS Timer 2 */
-#define IRQ_PMCOS3      39      /* PMC OS Timer 3 */
-#define IRQ_VPU         40      /* Video Processing Unit */
-#define IRQ_VID         41      /* Video Digital Input Interface */
-#define IRQ_AC97        42      /* AC97 Interface */
-#define IRQ_EHCI        43      /* USB */
-#define IRQ_NOR         44      /* NOR Flash Controller */
-#define IRQ_PS2MOUSE    45      /* PS/2 Mouse */
-#define IRQ_PS2KBD      46      /* PS/2 Keyboard */
-#define IRQ_UART2       47      /* UART 2 */
-#define IRQ_RTC         48      /* RTC Interrupt */
-#define IRQ_RTCSM       49      /* RTC Second/Minute Update Interrupt */
-#define IRQ_UART3       50      /* UART 3 */
-#define IRQ_ADC         51      /* ADC */
-#define IRQ_EXT5        52      /* External Interrupt 5 */
-#define IRQ_EXT6        53      /* External Interrupt 6 */
-#define IRQ_EXT7        54      /* External Interrupt 7 */
-#define IRQ_CIR         55      /* CIR */
-#define IRQ_DMA0        56      /* DMA Channel 0 */
-#define IRQ_DMA1        57      /* DMA Channel 1 */
-#define IRQ_DMA2        58      /* DMA Channel 2 */
-#define IRQ_DMA3        59      /* DMA Channel 3 */
-#define IRQ_DMA4        60      /* DMA Channel 4 */
-#define IRQ_DMA5        61      /* DMA Channel 5 */
-#define IRQ_DMA6        62      /* DMA Channel 6 */
-#define IRQ_DMA7        63      /* DMA Channel 7 */
-
-#define VT8500_NR_IRQS          64
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h b/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
deleted file mode 100644
index 29c63ecb2383..000000000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vt8500_regs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_VT8500_REGS_H
-#define __ASM_ARM_ARCH_VT8500_REGS_H
-
-/* VT8500 Registers Map */
-
-#define VT8500_REGS_START_PHYS  0xd8000000      /* Start of MMIO registers */
-#define VT8500_REGS_START_VIRT  0xf8000000      /* Virtual mapping start */
-
-#define VT8500_DDR_BASE         0xd8000000      /* 1k   DDR/DDR2 Memory
-                                                        Controller */
-#define VT8500_DMA_BASE         0xd8001000      /* 1k   DMA Controller */
-#define VT8500_SFLASH_BASE      0xd8002000      /* 1k   Serial Flash Memory
-                                                        Controller */
-#define VT8500_ETHER_BASE       0xd8004000      /* 1k   Ethernet MAC 0 */
-#define VT8500_CIPHER_BASE      0xd8006000      /* 4k   Cipher */
-#define VT8500_USB_BASE         0xd8007800      /* 2k   USB OTG */
-# define VT8500_EHCI_BASE       0xd8007900      /*      EHCI */
-# define VT8500_UHCI_BASE       0xd8007b01      /*      UHCI */
-#define VT8500_PATA_BASE        0xd8008000      /* 512  PATA */
-#define VT8500_PS2_BASE         0xd8008800      /* 1k   PS/2 */
-#define VT8500_NAND_BASE        0xd8009000      /* 1k   NAND Controller */
-#define VT8500_NOR_BASE         0xd8009400      /* 1k   NOR Controller */
-#define VT8500_SDMMC_BASE       0xd800a000      /* 1k   SD/MMC Controller */
-#define VT8500_MS_BASE          0xd800b000      /* 1k   MS/MSPRO Controller */
-#define VT8500_LCDC_BASE        0xd800e400      /* 1k   LCD Controller */
-#define VT8500_VPU_BASE         0xd8050000      /* 256  VPU */
-#define VT8500_GOV_BASE         0xd8050300      /* 256  GOV */
-#define VT8500_GEGEA_BASE       0xd8050400      /* 768  GE/GE Alpha Mixing */
-#define VT8500_LCDF_BASE        0xd8050900      /* 256  LCD Formatter */
-#define VT8500_VID_BASE         0xd8050a00      /* 256  VID */
-#define VT8500_VPP_BASE         0xd8050b00      /* 256  VPP */
-#define VT8500_TSBK_BASE        0xd80f4000      /* 4k   TSBK */
-#define VT8500_JPEGDEC_BASE     0xd80fe000      /* 4k   JPEG Decoder */
-#define VT8500_JPEGENC_BASE     0xd80ff000      /* 4k   JPEG Encoder */
-#define VT8500_RTC_BASE         0xd8100000      /* 64k  RTC */
-#define VT8500_GPIO_BASE        0xd8110000      /* 64k  GPIO Configuration */
-#define VT8500_SCC_BASE         0xd8120000      /* 64k  System Configuration*/
-#define VT8500_PMC_BASE         0xd8130000      /* 64k  PMC Configuration */
-#define VT8500_IC_BASE          0xd8140000      /* 64k  Interrupt Controller*/
-#define VT8500_UART0_BASE       0xd8200000      /* 64k  UART 0 */
-#define VT8500_UART2_BASE       0xd8210000      /* 64k  UART 2 */
-#define VT8500_PWM_BASE         0xd8220000      /* 64k  PWM Configuration */
-#define VT8500_SPI0_BASE        0xd8240000      /* 64k  SPI 0 */
-#define VT8500_SPI1_BASE        0xd8250000      /* 64k  SPI 1 */
-#define VT8500_CIR_BASE         0xd8270000      /* 64k  CIR */
-#define VT8500_I2C0_BASE        0xd8280000      /* 64k  I2C 0 */
-#define VT8500_AC97_BASE        0xd8290000      /* 64k  AC97 */
-#define VT8500_SPI2_BASE        0xd82a0000      /* 64k  SPI 2 */
-#define VT8500_UART1_BASE       0xd82b0000      /* 64k  UART 1 */
-#define VT8500_UART3_BASE       0xd82c0000      /* 64k  UART 3 */
-#define VT8500_PCM_BASE         0xd82d0000      /* 64k  PCM */
-#define VT8500_I2C1_BASE        0xd8320000      /* 64k  I2C 1 */
-#define VT8500_I2S_BASE         0xd8330000      /* 64k  I2S */
-#define VT8500_ADC_BASE         0xd8340000      /* 64k  ADC */
-
-#define VT8500_REGS_END_PHYS    0xd834ffff      /* End of MMIO registers */
-#define VT8500_REGS_LENGTH      (VT8500_REGS_END_PHYS \
-                                - VT8500_REGS_START_PHYS + 1)
-
-#endif
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h b/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
deleted file mode 100644
index 6128627ac753..000000000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/* WM8505 Interrupt Sources */
-
-#define IRQ_UHCI        0       /* UHC FS (UHCI?) */
-#define IRQ_EHCI        1       /* UHC HS */
-#define IRQ_UDCDMA      2       /* UDC DMA */
-                                /* Reserved */
-#define IRQ_PS2MOUSE    4       /* PS/2 Mouse */
-#define IRQ_UDC         5       /* UDC */
-#define IRQ_EXT0        6       /* External Interrupt 0 */
-#define IRQ_EXT1        7       /* External Interrupt 1 */
-#define IRQ_KEYPAD      8       /* Keypad */
-#define IRQ_DMA         9       /* DMA Controller */
-#define IRQ_ETHER       10      /* Ethernet MAC */
-                                /* Reserved */
-                                /* Reserved */
-#define IRQ_EXT2        13      /* External Interrupt 2 */
-#define IRQ_EXT3        14      /* External Interrupt 3 */
-#define IRQ_EXT4        15      /* External Interrupt 4 */
-#define IRQ_APB         16      /* APB Bridge */
-#define IRQ_DMA0        17      /* DMA Channel 0 */
-#define IRQ_I2C1        18      /* I2C 1 */
-#define IRQ_I2C0        19      /* I2C 0 */
-#define IRQ_SDMMC       20      /* SD/MMC Controller */
-#define IRQ_SDMMC_DMA   21      /* SD/MMC Controller DMA */
-#define IRQ_PMC_WU      22      /* Power Management Controller Wakeup */
-#define IRQ_PS2KBD      23      /* PS/2 Keyboard */
-#define IRQ_SPI0        24      /* SPI 0 */
-#define IRQ_SPI1        25      /* SPI 1 */
-#define IRQ_SPI2        26      /* SPI 2 */
-#define IRQ_DMA1        27      /* DMA Channel 1 */
-#define IRQ_NAND        28      /* NAND Flash Controller */
-#define IRQ_NAND_DMA    29      /* NAND Flash Controller DMA */
-#define IRQ_UART5       30      /* UART 5 */
-#define IRQ_UART4       31      /* UART 4 */
-#define IRQ_UART0       32      /* UART 0 */
-#define IRQ_UART1       33      /* UART 1 */
-#define IRQ_DMA2        34      /* DMA Channel 2 */
-#define IRQ_I2S         35      /* I2S */
-#define IRQ_PMCOS0      36      /* PMC OS Timer 0 */
-#define IRQ_PMCOS1      37      /* PMC OS Timer 1 */
-#define IRQ_PMCOS2      38      /* PMC OS Timer 2 */
-#define IRQ_PMCOS3      39      /* PMC OS Timer 3 */
-#define IRQ_DMA3        40      /* DMA Channel 3 */
-#define IRQ_DMA4        41      /* DMA Channel 4 */
-#define IRQ_AC97        42      /* AC97 Interface */
-                                /* Reserved */
-#define IRQ_NOR         44      /* NOR Flash Controller */
-#define IRQ_DMA5        45      /* DMA Channel 5 */
-#define IRQ_DMA6        46      /* DMA Channel 6 */
-#define IRQ_UART2       47      /* UART 2 */
-#define IRQ_RTC         48      /* RTC Interrupt */
-#define IRQ_RTCSM       49      /* RTC Second/Minute Update Interrupt */
-#define IRQ_UART3       50      /* UART 3 */
-#define IRQ_DMA7        51      /* DMA Channel 7 */
-#define IRQ_EXT5        52      /* External Interrupt 5 */
-#define IRQ_EXT6        53      /* External Interrupt 6 */
-#define IRQ_EXT7        54      /* External Interrupt 7 */
-#define IRQ_CIR         55      /* CIR */
-#define IRQ_SIC0        56      /* SIC IRQ0 */
-#define IRQ_SIC1        57      /* SIC IRQ1 */
-#define IRQ_SIC2        58      /* SIC IRQ2 */
-#define IRQ_SIC3        59      /* SIC IRQ3 */
-#define IRQ_SIC4        60      /* SIC IRQ4 */
-#define IRQ_SIC5        61      /* SIC IRQ5 */
-#define IRQ_SIC6        62      /* SIC IRQ6 */
-#define IRQ_SIC7        63      /* SIC IRQ7 */
-                                /* Reserved */
-#define IRQ_JPEGDEC     65      /* JPEG Decoder */
-#define IRQ_SAE         66      /* SAE (?) */
-                                /* Reserved */
-#define IRQ_VPU         79      /* Video Processing Unit */
-#define IRQ_VPP         80      /* Video Post-Processor */
-#define IRQ_VID         81      /* Video Digital Input Interface */
-#define IRQ_SPU         82      /* SPU (?) */
-#define IRQ_PIP         83      /* PIP Error */
-#define IRQ_GE          84      /* Graphic Engine */
-#define IRQ_GOV         85      /* Graphic Overlay Engine */
-#define IRQ_DVO         86      /* Digital Video Output */
-                                /* Reserved */
-#define IRQ_DMA8        92      /* DMA Channel 8 */
-#define IRQ_DMA9        93      /* DMA Channel 9 */
-#define IRQ_DMA10       94      /* DMA Channel 10 */
-#define IRQ_DMA11       95      /* DMA Channel 11 */
-#define IRQ_DMA12       96      /* DMA Channel 12 */
-#define IRQ_DMA13       97      /* DMA Channel 13 */
-#define IRQ_DMA14       98      /* DMA Channel 14 */
-#define IRQ_DMA15       99      /* DMA Channel 15 */
-                                /* Reserved */
-#define IRQ_GOVW        111     /* GOVW (?) */
-#define IRQ_GOVRSDSCD   112     /* GOVR SDSCD (?) */
-#define IRQ_GOVRSDMIF   113     /* GOVR SDMIF (?) */
-#define IRQ_GOVRHDSCD   114     /* GOVR HDSCD (?) */
-#define IRQ_GOVRHDMIF   115     /* GOVR HDMIF (?) */
-
-#define WM8505_NR_IRQS          116
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h b/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
deleted file mode 100644
index df1550941efb..000000000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/wm8505_regs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_WM8505_REGS_H
-#define __ASM_ARM_ARCH_WM8505_REGS_H
-
-/* WM8505 Registers Map */
-
-#define WM8505_REGS_START_PHYS  0xd8000000      /* Start of MMIO registers */
-#define WM8505_REGS_START_VIRT  0xf8000000      /* Virtual mapping start */
-
-#define WM8505_DDR_BASE         0xd8000400      /* 1k   DDR/DDR2 Memory
-                                                        Controller */
-#define WM8505_DMA_BASE         0xd8001800      /* 1k   DMA Controller */
-#define WM8505_VDMA_BASE        0xd8001c00      /* 1k   VDMA */
-#define WM8505_SFLASH_BASE      0xd8002000      /* 1k   Serial Flash Memory
-                                                        Controller */
-#define WM8505_ETHER_BASE       0xd8004000      /* 1k   Ethernet MAC 0 */
-#define WM8505_CIPHER_BASE      0xd8006000      /* 4k   Cipher */
-#define WM8505_USB_BASE         0xd8007000      /* 2k   USB 2.0 Host */
-# define WM8505_EHCI_BASE       0xd8007100      /*      EHCI */
-# define WM8505_UHCI_BASE       0xd8007301      /*      UHCI */
-#define WM8505_PS2_BASE         0xd8008800      /* 1k   PS/2 */
-#define WM8505_NAND_BASE        0xd8009000      /* 1k   NAND Controller */
-#define WM8505_NOR_BASE         0xd8009400      /* 1k   NOR Controller */
-#define WM8505_SDMMC_BASE       0xd800a000      /* 1k   SD/MMC Controller */
-#define WM8505_VPU_BASE         0xd8050000      /* 256  VPU */
-#define WM8505_GOV_BASE         0xd8050300      /* 256  GOV */
-#define WM8505_GEGEA_BASE       0xd8050400      /* 768  GE/GE Alpha Mixing */
-#define WM8505_GOVR_BASE        0xd8050800      /* 512  GOVR (frambuffer) */
-#define WM8505_VID_BASE         0xd8050a00      /* 256  VID */
-#define WM8505_SCL_BASE         0xd8050d00      /* 256  SCL */
-#define WM8505_VPP_BASE         0xd8050f00      /* 256  VPP */
-#define WM8505_JPEGDEC_BASE     0xd80fe000      /* 4k   JPEG Decoder */
-#define WM8505_RTC_BASE         0xd8100000      /* 64k  RTC */
-#define WM8505_GPIO_BASE        0xd8110000      /* 64k  GPIO Configuration */
-#define WM8505_SCC_BASE         0xd8120000      /* 64k  System Configuration*/
-#define WM8505_PMC_BASE         0xd8130000      /* 64k  PMC Configuration */
-#define WM8505_IC_BASE          0xd8140000      /* 64k  Interrupt Controller*/
-#define WM8505_SIC_BASE         0xd8150000      /* 64k  Secondary IC */
-#define WM8505_UART0_BASE       0xd8200000      /* 64k  UART 0 */
-#define WM8505_UART2_BASE       0xd8210000      /* 64k  UART 2 */
-#define WM8505_PWM_BASE         0xd8220000      /* 64k  PWM Configuration */
-#define WM8505_SPI0_BASE        0xd8240000      /* 64k  SPI 0 */
-#define WM8505_SPI1_BASE        0xd8250000      /* 64k  SPI 1 */
-#define WM8505_KEYPAD_BASE      0xd8260000      /* 64k  Keypad control */
-#define WM8505_CIR_BASE         0xd8270000      /* 64k  CIR */
-#define WM8505_I2C0_BASE        0xd8280000      /* 64k  I2C 0 */
-#define WM8505_AC97_BASE        0xd8290000      /* 64k  AC97 */
-#define WM8505_SPI2_BASE        0xd82a0000      /* 64k  SPI 2 */
-#define WM8505_UART1_BASE       0xd82b0000      /* 64k  UART 1 */
-#define WM8505_UART3_BASE       0xd82c0000      /* 64k  UART 3 */
-#define WM8505_I2C1_BASE        0xd8320000      /* 64k  I2C 1 */
-#define WM8505_I2S_BASE         0xd8330000      /* 64k  I2S */
-#define WM8505_UART4_BASE       0xd8370000      /* 64k  UART 4 */
-#define WM8505_UART5_BASE       0xd8380000      /* 64k  UART 5 */
-
-#define WM8505_REGS_END_PHYS    0xd838ffff      /* End of MMIO registers */
-#define WM8505_REGS_LENGTH      (WM8505_REGS_END_PHYS \
-                                - WM8505_REGS_START_PHYS + 1)
-
-#endif
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c
index 642de0408f25..f8f9ab9bc56e 100644
--- a/arch/arm/mach-vt8500/irq.c
+++ b/arch/arm/mach-vt8500/irq.c
@@ -1,6 +1,7 @@
 /*
  *  arch/arm/mach-vt8500/irq.c
  *
+ *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
  *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -18,81 +19,102 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ * This file is copied and modified from the original irq.c provided by
+ * Alexey Charkov. Minor changes have been made for Device Tree Support.
+ */
+
+#include <linux/slab.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/interrupt.h>
+#include <linux/bitops.h>
+
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 
 #include <asm/irq.h>
 
-#include "devices.h"
 
-#define VT8500_IC_DCTR          0x40            /* Destination control
-                                                register, 64*u8 */
-#define VT8500_INT_ENABLE       (1 << 3)
-#define VT8500_TRIGGER_HIGH     (0 << 4)
-#define VT8500_TRIGGER_RISING   (1 << 4)
-#define VT8500_TRIGGER_FALLING  (2 << 4)
+#define VT8500_ICPC_IRQ         0x20
+#define VT8500_ICPC_FIQ         0x24
+#define VT8500_ICDC             0x40            /* Destination Control 64*u32 */
+#define VT8500_ICIS             0x80            /* Interrupt status, 16*u32 */
+
+/* ICPC */
+#define ICPC_MASK               0x3F
+#define ICPC_ROTATE             BIT(6)
+
+/* IC_DCTR */
+#define ICDC_IRQ                0x00
+#define ICDC_FIQ                0x01
+#define ICDC_DSS0               0x02
+#define ICDC_DSS1               0x03
+#define ICDC_DSS2               0x04
+#define ICDC_DSS3               0x05
+#define ICDC_DSS4               0x06
+#define ICDC_DSS5               0x07
+
+#define VT8500_INT_DISABLE      0
+#define VT8500_INT_ENABLE       BIT(3)
+
+#define VT8500_TRIGGER_HIGH     0
+#define VT8500_TRIGGER_RISING   BIT(5)
+#define VT8500_TRIGGER_FALLING  BIT(6)
 #define VT8500_EDGE             ( VT8500_TRIGGER_RISING \
                                 | VT8500_TRIGGER_FALLING)
-#define VT8500_IC_STATUS        0x80            /* Interrupt status, 2*u32 */
 
-static void __iomem *ic_regbase;
-static void __iomem *sic_regbase;
+static int irq_cnt;
+
+struct vt8500_irq_priv {
+        void __iomem *base;
+};
 
 static void vt8500_irq_mask(struct irq_data *d)
 {
-        void __iomem *base = ic_regbase;
-        unsigned irq = d->irq;
+        struct vt8500_irq_priv *priv =
+                        (struct vt8500_irq_priv *)(d->domain->host_data);
+        void __iomem *base = priv->base;
         u8 edge;
 
-        if (irq >= 64) {
-                base = sic_regbase;
-                irq -= 64;
-        }
-        edge = readb(base + VT8500_IC_DCTR + irq) & VT8500_EDGE;
+        edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
         if (edge) {
-                void __iomem *stat_reg = base + VT8500_IC_STATUS
-                                                + (irq < 32 ? 0 : 4);
+                void __iomem *stat_reg = base + VT8500_ICIS
+                                                + (d->hwirq < 32 ? 0 : 4);
                 unsigned status = readl(stat_reg);
 
-                status |= (1 << (irq & 0x1f));
+                status |= (1 << (d->hwirq & 0x1f));
                 writel(status, stat_reg);
         } else {
-                u8 dctr = readb(base + VT8500_IC_DCTR + irq);
+                u8 dctr = readb(base + VT8500_ICDC + d->hwirq);
 
                 dctr &= ~VT8500_INT_ENABLE;
-                writeb(dctr, base + VT8500_IC_DCTR + irq);
+                writeb(dctr, base + VT8500_ICDC + d->hwirq);
         }
 }
 
 static void vt8500_irq_unmask(struct irq_data *d)
 {
-        void __iomem *base = ic_regbase;
-        unsigned irq = d->irq;
+        struct vt8500_irq_priv *priv =
+                        (struct vt8500_irq_priv *)(d->domain->host_data);
+        void __iomem *base = priv->base;
         u8 dctr;
 
-        if (irq >= 64) {
-                base = sic_regbase;
-                irq -= 64;
-        }
-        dctr = readb(base + VT8500_IC_DCTR + irq);
+        dctr = readb(base + VT8500_ICDC + d->hwirq);
         dctr |= VT8500_INT_ENABLE;
-        writeb(dctr, base + VT8500_IC_DCTR + irq);
+        writeb(dctr, base + VT8500_ICDC + d->hwirq);
 }
 
 static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
-        void __iomem *base = ic_regbase;
-        unsigned irq = d->irq;
-        unsigned orig_irq = irq;
+        struct vt8500_irq_priv *priv =
+                        (struct vt8500_irq_priv *)(d->domain->host_data);
+        void __iomem *base = priv->base;
         u8 dctr;
 
-        if (irq >= 64) {
-                base = sic_regbase;
-                irq -= 64;
-        }
-
-        dctr = readb(base + VT8500_IC_DCTR + irq);
+        dctr = readb(base + VT8500_ICDC + d->hwirq);
         dctr &= ~VT8500_EDGE;
 
         switch (flow_type) {
@@ -100,18 +122,18 @@ static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
                 return -EINVAL;
         case IRQF_TRIGGER_HIGH:
                 dctr |= VT8500_TRIGGER_HIGH;
-                __irq_set_handler_locked(orig_irq, handle_level_irq);
+                __irq_set_handler_locked(d->irq, handle_level_irq);
                 break;
         case IRQF_TRIGGER_FALLING:
                 dctr |= VT8500_TRIGGER_FALLING;
-                __irq_set_handler_locked(orig_irq, handle_edge_irq);
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
                 break;
         case IRQF_TRIGGER_RISING:
                 dctr |= VT8500_TRIGGER_RISING;
-                __irq_set_handler_locked(orig_irq, handle_edge_irq);
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
                 break;
         }
-        writeb(dctr, base + VT8500_IC_DCTR + irq);
+        writeb(dctr, base + VT8500_ICDC + d->hwirq);
 
         return 0;
 }
@@ -124,57 +146,76 @@ static struct irq_chip vt8500_irq_chip = {
         .irq_set_type = vt8500_irq_set_type,
 };
 
-void __init vt8500_init_irq(void)
+static void __init vt8500_init_irq_hw(void __iomem *base)
 {
         unsigned int i;
 
-        ic_regbase = ioremap(wmt_ic_base, SZ_64K);
+        /* Enable rotating priority for IRQ */
+        writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
+        writel(0x00, base + VT8500_ICPC_FIQ);
 
-        if (ic_regbase) {
-                /* Enable rotating priority for IRQ */
-                writel((1 << 6), ic_regbase + 0x20);
-                writel(0, ic_regbase + 0x24);
+        for (i = 0; i < 64; i++) {
+                /* Disable all interrupts and route them to IRQ */
+                writeb(VT8500_INT_DISABLE | ICDC_IRQ,
+                                                base + VT8500_ICDC + i);
+        }
+}
 
-                for (i = 0; i < wmt_nr_irqs; i++) {
-                        /* Disable all interrupts and route them to IRQ */
-                        writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
+static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
+                                                        irq_hw_number_t hw)
+{
+        irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
+        set_irq_flags(virq, IRQF_VALID);
 
-                        irq_set_chip_and_handler(i, &vt8500_irq_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(i, IRQF_VALID);
-                }
-        } else {
-                printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
-        }
+        return 0;
 }
 
-void __init wm8505_init_irq(void)
+static struct irq_domain_ops vt8500_irq_domain_ops = {
+        .map = vt8500_irq_map,
+        .xlate = irq_domain_xlate_onecell,
+};
+
+int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
 {
-        unsigned int i;
+        struct irq_domain *vt8500_irq_domain;
+        struct vt8500_irq_priv *priv;
+        int irq, i;
+        struct device_node *np = node;
+
+        priv = kzalloc(sizeof(struct vt8500_irq_priv), GFP_KERNEL);
+        priv->base = of_iomap(np, 0);
+
+        vt8500_irq_domain = irq_domain_add_legacy(node, 64, irq_cnt, 0,
+                                &vt8500_irq_domain_ops, priv);
+        if (!vt8500_irq_domain)
+                pr_err("%s: Unable to add wmt irq domain!\n", __func__);
+
+        irq_set_default_host(vt8500_irq_domain);
+
+        vt8500_init_irq_hw(priv->base);
 
-        ic_regbase = ioremap(wmt_ic_base, SZ_64K);
-        sic_regbase = ioremap(wmt_sic_base, SZ_64K);
-
-        if (ic_regbase && sic_regbase) {
-                /* Enable rotating priority for IRQ */
-                writel((1 << 6), ic_regbase + 0x20);
-                writel(0, ic_regbase + 0x24);
-                writel((1 << 6), sic_regbase + 0x20);
-                writel(0, sic_regbase + 0x24);
-
-                for (i = 0; i < wmt_nr_irqs; i++) {
-                        /* Disable all interrupts and route them to IRQ */
-                        if (i < 64)
-                                writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
-                        else
-                                writeb(0x00, sic_regbase + VT8500_IC_DCTR
-                                                                + i - 64);
-
-                        irq_set_chip_and_handler(i, &vt8500_irq_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(i, IRQF_VALID);
+        pr_info("Added IRQ Controller @ %x [virq_base = %d]\n",
+                                                (u32)(priv->base), irq_cnt);
+
+        /* check if this is a slaved controller */
+        if (of_irq_count(np) != 0) {
+                /* check that we have the correct number of interrupts */
+                if (of_irq_count(np) != 8) {
+                        pr_err("%s: Incorrect IRQ map for slave controller\n",
+                                        __func__);
+                        return -EINVAL;
                 }
-        } else {
-                printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
+
+                for (i = 0; i < 8; i++) {
+                        irq = irq_of_parse_and_map(np, i);
+                        enable_irq(irq);
+                }
+
+                pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
         }
+
+        irq_cnt += 64;
+
+        return 0;
 }
+
diff --git a/arch/arm/mach-vt8500/restart.c b/arch/arm/mach-vt8500/restart.c
deleted file mode 100644
index 497e89a5e130..000000000000
--- a/arch/arm/mach-vt8500/restart.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/arch/arm/mach-vt8500/restart.c
- *
- * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <asm/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#define LEGACY_PMC_BASE         0xD8130000
-#define WMT_PRIZM_PMSR_REG      0x60
-
-static void __iomem *pmc_base;
-
-void wmt_setup_restart(void)
-{
-        struct device_node *np;
-
-        /*
-         * Check if Power Mgmt Controller node is present in device tree. If no
-         * device tree node, use the legacy PMSR value (valid for all current
-         * SoCs).
-         */
-        np = of_find_compatible_node(NULL, NULL, "wmt,prizm-pmc");
-        if (np) {
-                pmc_base = of_iomap(np, 0);
-
-                if (!pmc_base)
-                        pr_err("%s:of_iomap(pmc) failed\n", __func__);
-
-                of_node_put(np);
-        } else {
-                pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
-                if (!pmc_base) {
-                        pr_err("%s:ioremap(rstc) failed\n", __func__);
-                        return;
-                }
-        }
-}
-
-void wmt_restart(char mode, const char *cmd)
-{
-        if (pmc_base)
-                writel(1, pmc_base + WMT_PRIZM_PMSR_REG);
-}
diff --git a/arch/arm/mach-vt8500/timer.c b/arch/arm/mach-vt8500/timer.c
index d5376c592ab6..050e1833f2d0 100644
--- a/arch/arm/mach-vt8500/timer.c
+++ b/arch/arm/mach-vt8500/timer.c
@@ -1,6 +1,7 @@
 /*
- *  arch/arm/mach-vt8500/timer.c
+ *  arch/arm/mach-vt8500/timer_dt.c
  *
+ *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
  *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -18,18 +19,25 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ * This file is copied and modified from the original timer.c provided by
+ * Alexey Charkov. Minor changes have been made for Device Tree Support.
+ */
+
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/delay.h>
-
 #include <asm/mach/time.h>
 
-#include "devices.h"
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #define VT8500_TIMER_OFFSET     0x0100
+#define VT8500_TIMER_HZ         3000000
 #define TIMER_MATCH_VAL         0x0000
 #define TIMER_COUNT_VAL         0x0010
 #define TIMER_STATUS_VAL        0x0014
@@ -39,7 +47,6 @@
 #define TIMER_COUNT_R_ACTIVE    (1 << 5)        /* not ready for read */
 #define TIMER_COUNT_W_ACTIVE    (1 << 4)        /* not ready for write */
 #define TIMER_MATCH_W_ACTIVE    (1 << 0)        /* not ready for write */
-#define VT8500_TIMER_HZ         3000000
 
 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 
@@ -55,7 +62,7 @@ static cycle_t vt8500_timer_read(struct clocksource *cs)
         return readl(regbase + TIMER_COUNT_VAL);
 }
 
-struct clocksource clocksource = {
+static struct clocksource clocksource = {
         .name           = "vt8500_timer",
         .rating         = 200,
         .read           = vt8500_timer_read,
@@ -98,7 +105,7 @@ static void vt8500_timer_set_mode(enum clock_event_mode mode,
         }
 }
 
-struct clock_event_device clockevent = {
+static struct clock_event_device clockevent = {
         .name           = "vt8500_timer",
         .features       = CLOCK_EVT_FEAT_ONESHOT,
         .rating         = 200,
@@ -115,26 +122,51 @@ static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-struct irqaction irq = {
+static struct irqaction irq = {
         .name    = "vt8500_timer",
         .flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
         .handler = vt8500_timer_interrupt,
         .dev_id  = &clockevent,
 };
 
-static void __init vt8500_timer_init(void)
+static struct of_device_id vt8500_timer_ids[] = {
+        { .compatible = "via,vt8500-timer" },
+        { }
+};
+
+void __init vt8500_timer_init(void)
 {
-        regbase = ioremap(wmt_pmc_base + VT8500_TIMER_OFFSET, 0x28);
-        if (!regbase)
-                printk(KERN_ERR "vt8500_timer_init: failed to map MMIO registers\n");
+        struct device_node *np;
+        int timer_irq;
+
+        np = of_find_matching_node(NULL, vt8500_timer_ids);
+        if (!np) {
+                pr_err("%s: Timer description missing from Device Tree\n",
+                                                                __func__);
+                return;
+        }
+        regbase = of_iomap(np, 0);
+        if (!regbase) {
+                pr_err("%s: Missing iobase description in Device Tree\n",
+                                                                __func__);
+                of_node_put(np);
+                return;
+        }
+        timer_irq = irq_of_parse_and_map(np, 0);
+        if (!timer_irq) {
+                pr_err("%s: Missing irq description in Device Tree\n",
+                                                                __func__);
+                of_node_put(np);
+                return;
+        }
 
         writel(1, regbase + TIMER_CTRL_VAL);
         writel(0xf, regbase + TIMER_STATUS_VAL);
         writel(~0, regbase + TIMER_MATCH_VAL);
 
         if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ))
-                printk(KERN_ERR "vt8500_timer_init: clocksource_register failed for %s\n",
-                                        clocksource.name);
+                pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n",
+                                        __func__, clocksource.name);
 
         clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4);
 
@@ -144,12 +176,9 @@ static void __init vt8500_timer_init(void)
         clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent);
         clockevent.cpumask = cpumask_of(0);
 
-        if (setup_irq(wmt_timer_irq, &irq))
-                printk(KERN_ERR "vt8500_timer_init: setup_irq failed for %s\n",
-                                        clockevent.name);
+        if (setup_irq(timer_irq, &irq))
+                pr_err("%s: setup_irq failed for %s\n", __func__,
+                                                        clockevent.name);
         clockevents_register_device(&clockevent);
 }
 
-struct sys_timer vt8500_timer = {
-        .init = vt8500_timer_init
-};
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
new file mode 100644
index 000000000000..587ea950d08b
--- /dev/null
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -0,0 +1,195 @@
+/*
+ *  arch/arm/mach-vt8500/vt8500.c
+ *
+ *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/io.h>
+#include <linux/pm.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <mach/restart.h>
+
+#include "common.h"
+
+#define LEGACY_GPIO_BASE        0xD8110000
+#define LEGACY_PMC_BASE         0xD8130000
+
+/* Registers in GPIO Controller */
+#define VT8500_GPIO_MUX_REG     0x200
+
+/* Registers in Power Management Controller */
+#define VT8500_HCR_REG          0x12
+#define VT8500_PMSR_REG         0x60
+
+static void __iomem *pmc_base;
+
+void vt8500_restart(char mode, const char *cmd)
+{
+        if (pmc_base)
+                writel(1, pmc_base + VT8500_PMSR_REG);
+}
+
+static struct map_desc vt8500_io_desc[] __initdata = {
+        /* SoC MMIO registers */
+        [0] = {
+                .virtual        = 0xf8000000,
+                .pfn            = __phys_to_pfn(0xd8000000),
+                .length         = 0x00390000, /* max of all chip variants */
+                .type           = MT_DEVICE
+        },
+};
+
+void __init vt8500_map_io(void)
+{
+        iotable_init(vt8500_io_desc, ARRAY_SIZE(vt8500_io_desc));
+}
+
+static void vt8500_power_off(void)
+{
+        local_irq_disable();
+        writew(5, pmc_base + VT8500_HCR_REG);
+        asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
+}
+
+void __init vt8500_init(void)
+{
+        struct device_node *np, *fb;
+        void __iomem *gpio_base;
+
+#ifdef CONFIG_FB_VT8500
+        fb = of_find_compatible_node(NULL, NULL, "via,vt8500-fb");
+        if (fb) {
+                np = of_find_compatible_node(NULL, NULL, "via,vt8500-gpio");
+                if (np) {
+                        gpio_base = of_iomap(np, 0);
+
+                        if (!gpio_base)
+                                pr_err("%s: of_iomap(gpio_mux) failed\n",
+                                                                __func__);
+
+                        of_node_put(np);
+                } else {
+                        gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
+                        if (!gpio_base)
+                                pr_err("%s: ioremap(legacy_gpio_mux) failed\n",
+                                                                __func__);
+                }
+                if (gpio_base) {
+                        writel(readl(gpio_base + VT8500_GPIO_MUX_REG) | 1,
+                                gpio_base + VT8500_GPIO_MUX_REG);
+                        iounmap(gpio_base);
+                } else
+                        pr_err("%s: Could not remap GPIO mux\n", __func__);
+
+                of_node_put(fb);
+        }
+#endif
+
+#ifdef CONFIG_FB_WM8505
+        fb = of_find_compatible_node(NULL, NULL, "wm,wm8505-fb");
+        if (fb) {
+                np = of_find_compatible_node(NULL, NULL, "wm,wm8505-gpio");
+                if (!np)
+                        np = of_find_compatible_node(NULL, NULL,
+                                                        "wm,wm8650-gpio");
+                if (np) {
+                        gpio_base = of_iomap(np, 0);
+
+                        if (!gpio_base)
+                                pr_err("%s: of_iomap(gpio_mux) failed\n",
+                                                                __func__);
+
+                        of_node_put(np);
+                } else {
+                        gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
+                        if (!gpio_base)
+                                pr_err("%s: ioremap(legacy_gpio_mux) failed\n",
+                                                                __func__);
+                }
+                if (gpio_base) {
+                        writel(readl(gpio_base + VT8500_GPIO_MUX_REG) |
+                                0x80000000, gpio_base + VT8500_GPIO_MUX_REG);
+                        iounmap(gpio_base);
+                } else
+                        pr_err("%s: Could not remap GPIO mux\n", __func__);
+
+                of_node_put(fb);
+        }
+#endif
+
+        np = of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
+        if (np) {
+                pmc_base = of_iomap(np, 0);
+
+                if (!pmc_base)
+                        pr_err("%s:of_iomap(pmc) failed\n", __func__);
+
+                of_node_put(np);
+        } else {
+                pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
+                if (!pmc_base)
+                        pr_err("%s:ioremap(power_off) failed\n", __func__);
+        }
+        if (pmc_base)
+                pm_power_off = &vt8500_power_off;
+        else
+                pr_err("%s: PMC Hibernation register could not be remapped, not enabling power off!\n", __func__);
+
+        vtwm_clk_init(pmc_base);
+
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const struct of_device_id vt8500_irq_match[] __initconst = {
+        { .compatible = "via,vt8500-intc", .data = vt8500_irq_init, },
+        { /* sentinel */ },
+};
+
+static void __init vt8500_init_irq(void)
+{
+        of_irq_init(vt8500_irq_match);
+};
+
+static struct sys_timer vt8500_timer = {
+        .init = vt8500_timer_init,
+};
+
+static const char * const vt8500_dt_compat[] = {
+        "via,vt8500",
+        "wm,wm8650",
+        "wm,wm8505",
+};
+
+DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
+        .dt_compat      = vt8500_dt_compat,
+        .map_io         = vt8500_map_io,
+        .init_irq       = vt8500_init_irq,
+        .timer          = &vt8500_timer,
+        .init_machine   = vt8500_init,
+        .restart        = vt8500_restart,
+MACHINE_END
+
diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c
deleted file mode 100644
index db19886caf7c..000000000000
--- a/arch/arm/mach-vt8500/wm8505_7in.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/wm8505_7in.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/io.h>
-#include <linux/pm.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/restart.h>
-
-#include "devices.h"
-
-static void __iomem *pmc_hiber;
-
-static struct platform_device *devices[] __initdata = {
-        &vt8500_device_uart0,
-        &vt8500_device_ehci,
-        &vt8500_device_wm8505_fb,
-        &vt8500_device_ge_rops,
-        &vt8500_device_pwm,
-        &vt8500_device_pwmbl,
-        &vt8500_device_rtc,
-};
-
-static void vt8500_power_off(void)
-{
-        local_irq_disable();
-        writew(5, pmc_hiber);
-        asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
-}
-
-void __init wm8505_7in_init(void)
-{
-#ifdef CONFIG_FB_WM8505
-        void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4);
-        if (gpio_mux_reg) {
-                writel(readl(gpio_mux_reg) | 0x80000000, gpio_mux_reg);
-                iounmap(gpio_mux_reg);
-        } else {
-                printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n");
-        }
-#endif
-        pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2);
-        if (pmc_hiber)
-                pm_power_off = &vt8500_power_off;
-        else
-                printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-        wmt_setup_restart();
-        wm8505_set_resources();
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-        vt8500_gpio_init();
-}
-
-MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook")
-        .atag_offset    = 0x100,
-        .restart        = wmt_restart,
-        .reserve        = wm8505_reserve_mem,
-        .map_io         = wm8505_map_io,
-        .init_irq       = wm8505_init_irq,
-        .timer          = &vt8500_timer,
-        .init_machine   = wm8505_7in_init,
-MACHINE_END
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 2a8e380501e8..577baf7d0a8d 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -554,7 +554,7 @@ static const struct of_device_id l2x0_ids[] __initconst = {
 int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 {
         struct device_node *np;
-        struct l2x0_of_data *data;
+        const struct l2x0_of_data *data;
         struct resource res;
 
         np = of_find_matching_node(NULL, l2x0_ids);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index e59c4ab71bcb..477a2d23ddf1 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -73,11 +73,18 @@ static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
              unsigned long offset, size_t size, enum dma_data_direction dir,
              struct dma_attrs *attrs)
 {
-        if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+        if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                 __dma_page_cpu_to_dev(page, offset, size, dir);
         return pfn_to_dma(dev, page_to_pfn(page)) + offset;
 }
 
+static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
+             unsigned long offset, size_t size, enum dma_data_direction dir,
+             struct dma_attrs *attrs)
+{
+        return pfn_to_dma(dev, page_to_pfn(page)) + offset;
+}
+
 /**
  * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
@@ -96,7 +103,7 @@ static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
                 size_t size, enum dma_data_direction dir,
                 struct dma_attrs *attrs)
 {
-        if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+        if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
                                       handle & ~PAGE_MASK, size, dir);
 }
@@ -106,8 +113,7 @@ static void arm_dma_sync_single_for_cpu(struct device *dev,
 {
         unsigned int offset = handle & (PAGE_SIZE - 1);
         struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
-        if (!arch_is_coherent())
-                __dma_page_dev_to_cpu(page, offset, size, dir);
+        __dma_page_dev_to_cpu(page, offset, size, dir);
 }
 
 static void arm_dma_sync_single_for_device(struct device *dev,
@@ -115,8 +121,7 @@ static void arm_dma_sync_single_for_device(struct device *dev,
 {
         unsigned int offset = handle & (PAGE_SIZE - 1);
         struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
-        if (!arch_is_coherent())
-                __dma_page_cpu_to_dev(page, offset, size, dir);
+        __dma_page_cpu_to_dev(page, offset, size, dir);
 }
 
 static int arm_dma_set_mask(struct device *dev, u64 dma_mask);
@@ -138,6 +143,22 @@ struct dma_map_ops arm_dma_ops = {
 };
 EXPORT_SYMBOL(arm_dma_ops);
 
+static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
+        dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
+static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
+                                  dma_addr_t handle, struct dma_attrs *attrs);
+
+struct dma_map_ops arm_coherent_dma_ops = {
+        .alloc                  = arm_coherent_dma_alloc,
+        .free                   = arm_coherent_dma_free,
+        .mmap                   = arm_dma_mmap,
+        .get_sgtable            = arm_dma_get_sgtable,
+        .map_page               = arm_coherent_dma_map_page,
+        .map_sg                 = arm_dma_map_sg,
+        .set_dma_mask           = arm_dma_set_mask,
+};
+EXPORT_SYMBOL(arm_coherent_dma_ops);
+
 static u64 get_coherent_dma_mask(struct device *dev)
 {
         u64 mask = (u64)arm_dma_limit;
@@ -346,6 +367,8 @@ static int __init atomic_pool_init(void)
                        (unsigned)pool->size / 1024);
                 return 0;
         }
+
+        kfree(pages);
 no_pages:
         kfree(bitmap);
 no_bitmap:
@@ -584,7 +607,7 @@ static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
 
 
 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
-                         gfp_t gfp, pgprot_t prot, const void *caller)
+                         gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
 {
         u64 mask = get_coherent_dma_mask(dev);
         struct page *page;
@@ -617,7 +640,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
         *handle = DMA_ERROR_CODE;
         size = PAGE_ALIGN(size);
 
-        if (arch_is_coherent() || nommu())
+        if (is_coherent || nommu())
                 addr = __alloc_simple_buffer(dev, size, gfp, &page);
         else if (gfp & GFP_ATOMIC)
                 addr = __alloc_from_pool(size, &page);
@@ -645,7 +668,20 @@ void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
         if (dma_alloc_from_coherent(dev, size, handle, &memory))
                 return memory;
 
-        return __dma_alloc(dev, size, handle, gfp, prot,
+        return __dma_alloc(dev, size, handle, gfp, prot, false,
+                           __builtin_return_address(0));
+}
+
+static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
+        dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
+{
+        pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
+        void *memory;
+
+        if (dma_alloc_from_coherent(dev, size, handle, &memory))
+                return memory;
+
+        return __dma_alloc(dev, size, handle, gfp, prot, true,
                            __builtin_return_address(0));
 }
 
@@ -682,8 +718,9 @@ int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
 /*
  * Free a buffer as defined by the above mapping.
  */
-void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
-                  dma_addr_t handle, struct dma_attrs *attrs)
+static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
+                           dma_addr_t handle, struct dma_attrs *attrs,
+                           bool is_coherent)
 {
         struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
 
@@ -692,7 +729,7 @@ void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
 
         size = PAGE_ALIGN(size);
 
-        if (arch_is_coherent() || nommu()) {
+        if (is_coherent || nommu()) {
                 __dma_free_buffer(page, size);
         } else if (__free_from_pool(cpu_addr, size)) {
                 return;
@@ -708,6 +745,18 @@ void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
         }
 }
 
+void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
+                  dma_addr_t handle, struct dma_attrs *attrs)
+{
+        __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
+}
+
+static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
+                                  dma_addr_t handle, struct dma_attrs *attrs)
+{
+        __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
+}
+
 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
                  void *cpu_addr, dma_addr_t handle, size_t size,
                  struct dma_attrs *attrs)
@@ -1010,11 +1059,12 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t
                 if (!pages[i])
                         goto error;
 
-                if (order)
+                if (order) {
                         split_page(pages[i], order);
-                j = 1 << order;
-                while (--j)
-                        pages[i + j] = pages[i] + j;
+                        j = 1 << order;
+                        while (--j)
+                                pages[i + j] = pages[i] + j;
+                }
 
                 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
                 i += 1 << order;
@@ -1301,7 +1351,8 @@ static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
  */
 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
                           size_t size, dma_addr_t *handle,
-                          enum dma_data_direction dir, struct dma_attrs *attrs)
+                          enum dma_data_direction dir, struct dma_attrs *attrs,
+                          bool is_coherent)
 {
         struct dma_iommu_mapping *mapping = dev->archdata.mapping;
         dma_addr_t iova, iova_base;
@@ -1320,8 +1371,8 @@ static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
                 phys_addr_t phys = page_to_phys(sg_page(s));
                 unsigned int len = PAGE_ALIGN(s->offset + s->length);
 
-                if (!arch_is_coherent() &&
-                    !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+                if (!is_coherent &&
+                        !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                         __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
 
                 ret = iommu_map(mapping->domain, iova, phys, len, 0);
@@ -1339,20 +1390,9 @@ fail:
         return ret;
 }
 
-/**
- * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
- * @dev: valid struct device pointer
- * @sg: list of buffers
- * @nents: number of buffers to map
- * @dir: DMA transfer direction
- *
- * Map a set of buffers described by scatterlist in streaming mode for DMA.
- * The scatter gather list elements are merged together (if possible) and
- * tagged with the appropriate dma address and length. They are obtained via
- * sg_dma_{address,length}.
- */
-int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-                     enum dma_data_direction dir, struct dma_attrs *attrs)
+static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+                     enum dma_data_direction dir, struct dma_attrs *attrs,
+                     bool is_coherent)
 {
         struct scatterlist *s = sg, *dma = sg, *start = sg;
         int i, count = 0;
@@ -1368,7 +1408,7 @@ int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
 
                 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
                         if (__map_sg_chunk(dev, start, size, &dma->dma_address,
-                            dir, attrs) < 0)
+                            dir, attrs, is_coherent) < 0)
                                 goto bad_mapping;
 
                         dma->dma_address += offset;
@@ -1381,7 +1421,8 @@ int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
                 }
                 size += s->length;
         }
-        if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs) < 0)
+        if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
+                is_coherent) < 0)
                 goto bad_mapping;
 
         dma->dma_address += offset;
@@ -1396,17 +1437,44 @@ bad_mapping:
 }
 
 /**
- * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
+ * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
  * @dev: valid struct device pointer
  * @sg: list of buffers
- * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
- * @dir: DMA transfer direction (same as was passed to dma_map_sg)
+ * @nents: number of buffers to map
+ * @dir: DMA transfer direction
  *
- * Unmap a set of streaming mode DMA translations.  Again, CPU access
- * rules concerning calls here are the same as for dma_unmap_single().
+ * Map a set of i/o coherent buffers described by scatterlist in streaming
+ * mode for DMA. The scatter gather list elements are merged together (if
+ * possible) and tagged with the appropriate dma address and length. They are
+ * obtained via sg_dma_{address,length}.
  */
-void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
-                        enum dma_data_direction dir, struct dma_attrs *attrs)
+int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
+                int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+        return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
+}
+
+/**
+ * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
+ * @dev: valid struct device pointer
+ * @sg: list of buffers
+ * @nents: number of buffers to map
+ * @dir: DMA transfer direction
+ *
+ * Map a set of buffers described by scatterlist in streaming mode for DMA.
+ * The scatter gather list elements are merged together (if possible) and
+ * tagged with the appropriate dma address and length. They are obtained via
+ * sg_dma_{address,length}.
+ */
+int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
+                int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+        return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
+}
+
+static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
+                int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
+                bool is_coherent)
 {
         struct scatterlist *s;
         int i;
@@ -1415,7 +1483,7 @@ void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
                 if (sg_dma_len(s))
                         __iommu_remove_mapping(dev, sg_dma_address(s),
                                                sg_dma_len(s));
-                if (!arch_is_coherent() &&
+                if (!is_coherent &&
                     !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                         __dma_page_dev_to_cpu(sg_page(s), s->offset,
                                               s->length, dir);
@@ -1423,6 +1491,38 @@ void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
 }
 
 /**
+ * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
+ * @dev: valid struct device pointer
+ * @sg: list of buffers
+ * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
+ * @dir: DMA transfer direction (same as was passed to dma_map_sg)
+ *
+ * Unmap a set of streaming mode DMA translations.  Again, CPU access
+ * rules concerning calls here are the same as for dma_unmap_single().
+ */
+void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
+                int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+        __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
+}
+
+/**
+ * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
+ * @dev: valid struct device pointer
+ * @sg: list of buffers
+ * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
+ * @dir: DMA transfer direction (same as was passed to dma_map_sg)
+ *
+ * Unmap a set of streaming mode DMA translations.  Again, CPU access
+ * rules concerning calls here are the same as for dma_unmap_single().
+ */
+void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
+                        enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+        __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
+}
+
+/**
  * arm_iommu_sync_sg_for_cpu
  * @dev: valid struct device pointer
  * @sg: list of buffers
@@ -1436,8 +1536,7 @@ void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
         int i;
 
         for_each_sg(sg, s, nents, i)
-                if (!arch_is_coherent())
-                        __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
+                __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
 
 }
 
@@ -1455,22 +1554,21 @@ void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
         int i;
 
         for_each_sg(sg, s, nents, i)
-                if (!arch_is_coherent())
-                        __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
+                __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
 }
 
 
 /**
- * arm_iommu_map_page
+ * arm_coherent_iommu_map_page
  * @dev: valid struct device pointer
  * @page: page that buffer resides in
  * @offset: offset into page for start of buffer
  * @size: size of buffer to map
  * @dir: DMA transfer direction
  *
- * IOMMU aware version of arm_dma_map_page()
+ * Coherent IOMMU aware version of arm_dma_map_page()
  */
-static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
+static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
              unsigned long offset, size_t size, enum dma_data_direction dir,
              struct dma_attrs *attrs)
 {
@@ -1478,9 +1576,6 @@ static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
         dma_addr_t dma_addr;
         int ret, len = PAGE_ALIGN(size + offset);
 
-        if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
-                __dma_page_cpu_to_dev(page, offset, size, dir);
-
         dma_addr = __alloc_iova(mapping, len);
         if (dma_addr == DMA_ERROR_CODE)
                 return dma_addr;
@@ -1496,6 +1591,51 @@ fail:
 }
 
 /**
+ * arm_iommu_map_page
+ * @dev: valid struct device pointer
+ * @page: page that buffer resides in
+ * @offset: offset into page for start of buffer
+ * @size: size of buffer to map
+ * @dir: DMA transfer direction
+ *
+ * IOMMU aware version of arm_dma_map_page()
+ */
+static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
+             unsigned long offset, size_t size, enum dma_data_direction dir,
+             struct dma_attrs *attrs)
+{
+        if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+                __dma_page_cpu_to_dev(page, offset, size, dir);
+
+        return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
+}
+
+/**
+ * arm_coherent_iommu_unmap_page
+ * @dev: valid struct device pointer
+ * @handle: DMA address of buffer
+ * @size: size of buffer (same as passed to dma_map_page)
+ * @dir: DMA transfer direction (same as passed to dma_map_page)
+ *
+ * Coherent IOMMU aware version of arm_dma_unmap_page()
+ */
+static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
+                size_t size, enum dma_data_direction dir,
+                struct dma_attrs *attrs)
+{
+        struct dma_iommu_mapping *mapping = dev->archdata.mapping;
+        dma_addr_t iova = handle & PAGE_MASK;
+        int offset = handle & ~PAGE_MASK;
+        int len = PAGE_ALIGN(size + offset);
+
+        if (!iova)
+                return;
+
+        iommu_unmap(mapping->domain, iova, len);
+        __free_iova(mapping, iova, len);
+}
+
+/**
  * arm_iommu_unmap_page
  * @dev: valid struct device pointer
  * @handle: DMA address of buffer
@@ -1517,7 +1657,7 @@ static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
         if (!iova)
                 return;
 
-        if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+        if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                 __dma_page_dev_to_cpu(page, offset, size, dir);
 
         iommu_unmap(mapping->domain, iova, len);
@@ -1535,8 +1675,7 @@ static void arm_iommu_sync_single_for_cpu(struct device *dev,
         if (!iova)
                 return;
 
-        if (!arch_is_coherent())
-                __dma_page_dev_to_cpu(page, offset, size, dir);
+        __dma_page_dev_to_cpu(page, offset, size, dir);
 }
 
 static void arm_iommu_sync_single_for_device(struct device *dev,
@@ -1570,6 +1709,19 @@ struct dma_map_ops iommu_ops = {
         .sync_sg_for_device     = arm_iommu_sync_sg_for_device,
 };
 
+struct dma_map_ops iommu_coherent_ops = {
+        .alloc          = arm_iommu_alloc_attrs,
+        .free           = arm_iommu_free_attrs,
+        .mmap           = arm_iommu_mmap_attrs,
+        .get_sgtable    = arm_iommu_get_sgtable,
+
+        .map_page       = arm_coherent_iommu_map_page,
+        .unmap_page     = arm_coherent_iommu_unmap_page,
+
+        .map_sg         = arm_coherent_iommu_map_sg,
+        .unmap_sg       = arm_coherent_iommu_unmap_sg,
+};
+
 /**
  * arm_iommu_create_mapping
  * @bus: pointer to the bus holding the client device (for IOMMU calls)
@@ -1663,7 +1815,7 @@ int arm_iommu_attach_device(struct device *dev,
         dev->archdata.mapping = mapping;
         set_dma_ops(dev, &iommu_ops);
 
-        pr_info("Attached IOMMU controller to %s device.\n", dev_name(dev));
+        pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
         return 0;
 }
 
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 18144e6a3115..941dfb9e9a78 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -423,17 +423,6 @@ static void __init build_mem_type_table(void)
         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 
         /*
-         * Enable CPU-specific coherency if supported.
-         * (Only available on XSC3 at the moment.)
-         */
-        if (arch_is_coherent() && cpu_is_xsc3()) {
-                mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-                mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
-                mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
-                mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
-                mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
-        }
-        /*
          * ARMv6 and above have extended page tables.
          */
         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index cb3e3eef55c0..6b46cee2f9cd 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -15,7 +15,11 @@ config IMX_HAVE_PLATFORM_GPIO_KEYS
 
 config IMX_HAVE_PLATFORM_IMX21_HCD
         bool
-        
+
+config IMX_HAVE_PLATFORM_IMX27_CODA
+        bool
+        default y if SOC_IMX27
+
 config IMX_HAVE_PLATFORM_IMX2_WDT
         bool
 
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index c11ac8472beb..76f3195475d0 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
 obj-y += platform-gpio-mxc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
 obj-y += platform-imx-dma.o
diff --git a/arch/arm/plat-mxc/devices/platform-imx27-coda.c b/arch/arm/plat-mxc/devices/platform-imx27-coda.c
new file mode 100644
index 000000000000..8b12aacdf396
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx27-coda.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2012 Vista Silicon
+ * Javier Martin <javier.martin@vista-silicon.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_imx27_coda_data imx27_coda_data __initconst = {
+        .iobase = MX27_VPU_BASE_ADDR,
+        .iosize = SZ_512,
+        .irq = MX27_INT_VPU,
+};
+#endif
+
+struct platform_device *__init imx_add_imx27_coda(
+                const struct imx_imx27_coda_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device_dmamask("coda-imx27", 0, res, 2, NULL,
+                                        0, DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 9e3e3d8ae8c2..eaf79d220c9a 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -83,6 +83,14 @@ struct platform_device *__init imx_add_imx21_hcd(
                 const struct imx_imx21_hcd_data *data,
                 const struct mx21_usbh_platform_data *pdata);
 
+struct imx_imx27_coda_data {
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_imx27_coda(
+                const struct imx_imx27_coda_data *data);
+
 struct imx_imx2_wdt_data {
         int id;
         resource_size_t iobase;
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 627d94f1b010..ec466400a200 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -98,6 +98,7 @@
 #define MX25_INT_UART1          (NR_IRQS_LEGACY + 45)
 #define MX25_INT_GPIO2          (NR_IRQS_LEGACY + 51)
 #define MX25_INT_GPIO1          (NR_IRQS_LEGACY + 52)
+#define MX25_INT_GPT1           (NR_IRQS_LEGACY + 54)
 #define MX25_INT_FEC            (NR_IRQS_LEGACY + 57)
 
 #define MX25_DMA_REQ_SSI2_RX1   22
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index d15a4a6d6146..ca83a7659aef 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -42,9 +42,8 @@ config OMAP_DEBUG_DEVICES
           For debug cards on TI reference boards.
 
 config OMAP_DEBUG_LEDS
-        bool
+        def_bool y if NEW_LEDS
         depends on OMAP_DEBUG_DEVICES
-        default y if LEDS_CLASS
 
 config POWER_AVS_OMAP
         bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2"
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 195aaae65872..ea29bbe8e5cf 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -1,280 +1,119 @@
 /*
  * linux/arch/arm/plat-omap/debug-leds.c
  *
+ * Copyright 2011 by Bryan Wu <bryan.wu@canonical.com>
  * Copyright 2003 by Texas Instruments Incorporated
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/gpio.h>
+
+#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/leds.h>
 #include <linux/io.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <linux/slab.h>
 
 #include <mach/hardware.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 
 #include <plat/fpga.h>
 
-
 /* Many OMAP development platforms reuse the same "debug board"; these
  * platforms include H2, H3, H4, and Perseus2.  There are 16 LEDs on the
  * debug board (all green), accessed through FPGA registers.
- *
- * The "surfer" expansion board and H2 sample board also have two-color
- * green+red LEDs (in parallel), used here for timer and idle indicators
- * in preference to the ones on the debug board, for a "Disco LED" effect.
- *
- * This driver exports either the original ARM LED API, the new generic
- * one, or both.
- */
-
-static spinlock_t                       lock;
-static struct h2p2_dbg_fpga __iomem     *fpga;
-static u16                              led_state, hw_led_state;
-
-
-#ifdef  CONFIG_OMAP_DEBUG_LEDS
-#define new_led_api()   1
-#else
-#define new_led_api()   0
-#endif
-
-
-/*-------------------------------------------------------------------------*/
-
-/* original ARM debug LED API:
- *  - timer and idle leds (some boards use non-FPGA leds here);
- *  - up to 4 generic leds, easily accessed in-kernel (any context)
  */
 
-#define GPIO_LED_RED            3
-#define GPIO_LED_GREEN          OMAP_MPUIO(4)
-
-#define LED_STATE_ENABLED       0x01
-#define LED_STATE_CLAIMED       0x02
-#define LED_TIMER_ON            0x04
-
-#define GPIO_IDLE               GPIO_LED_GREEN
-#define GPIO_TIMER              GPIO_LED_RED
-
-static void h2p2_dbg_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&lock, flags);
-
-        if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
-                goto done;
-
-        switch (evt) {
-        case led_start:
-                if (fpga)
-                        led_state |= LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-        case led_halted:
-                /* all leds off during suspend or shutdown */
-
-                if (!(machine_is_omap_perseus2() || machine_is_omap_h4())) {
-                        gpio_set_value(GPIO_TIMER, 0);
-                        gpio_set_value(GPIO_IDLE, 0);
-                }
-
-                __raw_writew(~0, &fpga->leds);
-                led_state &= ~LED_STATE_ENABLED;
-                goto done;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                led_state ^= LED_TIMER_ON;
-
-                if (machine_is_omap_perseus2() || machine_is_omap_h4())
-                        hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER;
-                else {
-                        gpio_set_value(GPIO_TIMER,
-                                        led_state & LED_TIMER_ON);
-                        goto done;
-                }
-
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        /* LED lit iff busy */
-        case led_idle_start:
-                if (machine_is_omap_perseus2() || machine_is_omap_h4())
-                        hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE;
-                else {
-                        gpio_set_value(GPIO_IDLE, 1);
-                        goto done;
-                }
-
-                break;
+static struct h2p2_dbg_fpga __iomem *fpga;
 
-        case led_idle_end:
-                if (machine_is_omap_perseus2() || machine_is_omap_h4())
-                        hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE;
-                else {
-                        gpio_set_value(GPIO_IDLE, 0);
-                        goto done;
-                }
-
-                break;
-#endif
-
-        case led_green_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_GREEN;
-                break;
-        case led_green_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_GREEN;
-                break;
-
-        case led_amber_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_AMBER;
-                break;
-        case led_amber_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_AMBER;
-                break;
-
-        case led_red_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_RED;
-                break;
-        case led_red_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_RED;
-                break;
-
-        case led_blue_on:
-                hw_led_state |= H2P2_DBG_FPGA_LED_BLUE;
-                break;
-        case led_blue_off:
-                hw_led_state &= ~H2P2_DBG_FPGA_LED_BLUE;
-                break;
-
-        default:
-                break;
-        }
-
-
-        /*
-         *  Actually burn the LEDs
-         */
-        if (led_state & LED_STATE_ENABLED)
-                __raw_writew(~hw_led_state, &fpga->leds);
-
-done:
-        spin_unlock_irqrestore(&lock, flags);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* "new" LED API
- *  - with syfs access and generic triggering
- *  - not readily accessible to in-kernel drivers
- */
+static u16 fpga_led_state;
 
 struct dbg_led {
         struct led_classdev     cdev;
         u16                     mask;
 };
 
-static struct dbg_led dbg_leds[] = {
-        /* REVISIT at least H2 uses different timer & cpu leds... */
-#ifndef CONFIG_LEDS_TIMER
-        { .mask = 1 << 0,  .cdev.name =  "d4:green",
-                .cdev.default_trigger = "heartbeat", },
-#endif
-#ifndef CONFIG_LEDS_CPU
-        { .mask = 1 << 1,  .cdev.name =  "d5:green", },         /* !idle */
-#endif
-        { .mask = 1 << 2,  .cdev.name =  "d6:green", },
-        { .mask = 1 << 3,  .cdev.name =  "d7:green", },
-
-        { .mask = 1 << 4,  .cdev.name =  "d8:green", },
-        { .mask = 1 << 5,  .cdev.name =  "d9:green", },
-        { .mask = 1 << 6,  .cdev.name = "d10:green", },
-        { .mask = 1 << 7,  .cdev.name = "d11:green", },
-
-        { .mask = 1 << 8,  .cdev.name = "d12:green", },
-        { .mask = 1 << 9,  .cdev.name = "d13:green", },
-        { .mask = 1 << 10, .cdev.name = "d14:green", },
-        { .mask = 1 << 11, .cdev.name = "d15:green", },
-
-#ifndef CONFIG_LEDS
-        { .mask = 1 << 12, .cdev.name = "d16:green", },
-        { .mask = 1 << 13, .cdev.name = "d17:green", },
-        { .mask = 1 << 14, .cdev.name = "d18:green", },
-        { .mask = 1 << 15, .cdev.name = "d19:green", },
-#endif
+static const struct {
+        const char *name;
+        const char *trigger;
+} dbg_leds[] = {
+        { "dbg:d4", "heartbeat", },
+        { "dbg:d5", "cpu0", },
+        { "dbg:d6", "default-on", },
+        { "dbg:d7", },
+        { "dbg:d8", },
+        { "dbg:d9", },
+        { "dbg:d10", },
+        { "dbg:d11", },
+        { "dbg:d12", },
+        { "dbg:d13", },
+        { "dbg:d14", },
+        { "dbg:d15", },
+        { "dbg:d16", },
+        { "dbg:d17", },
+        { "dbg:d18", },
+        { "dbg:d19", },
 };
 
-static void
-fpga_led_set(struct led_classdev *cdev, enum led_brightness value)
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static void dbg_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
 {
-        struct dbg_led  *led = container_of(cdev, struct dbg_led, cdev);
-        unsigned long   flags;
+        struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
+        u16 reg;
 
-        spin_lock_irqsave(&lock, flags);
-        if (value == LED_OFF)
-                hw_led_state &= ~led->mask;
+        reg = __raw_readw(&fpga->leds);
+        if (b != LED_OFF)
+                reg |= led->mask;
         else
-                hw_led_state |= led->mask;
-        __raw_writew(~hw_led_state, &fpga->leds);
-        spin_unlock_irqrestore(&lock, flags);
+                reg &= ~led->mask;
+        __raw_writew(reg, &fpga->leds);
 }
 
-static void __init newled_init(struct device *dev)
+static enum led_brightness dbg_led_get(struct led_classdev *cdev)
 {
-        unsigned        i;
-        struct dbg_led  *led;
-        int             status;
+        struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
+        u16 reg;
 
-        for (i = 0, led = dbg_leds; i < ARRAY_SIZE(dbg_leds); i++, led++) {
-                led->cdev.brightness_set = fpga_led_set;
-                status = led_classdev_register(dev, &led->cdev);
-                if (status < 0)
-                        break;
-        }
-        return;
+        reg = __raw_readw(&fpga->leds);
+        return (reg & led->mask) ? LED_FULL : LED_OFF;
 }
 
-
-/*-------------------------------------------------------------------------*/
-
-static int /* __init */ fpga_probe(struct platform_device *pdev)
+static int fpga_probe(struct platform_device *pdev)
 {
         struct resource *iomem;
-
-        spin_lock_init(&lock);
+        int i;
 
         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!iomem)
                 return -ENODEV;
 
         fpga = ioremap(iomem->start, H2P2_DBG_FPGA_SIZE);
-        __raw_writew(~0, &fpga->leds);
+        __raw_writew(0xff, &fpga->leds);
+
+        for (i = 0; i < ARRAY_SIZE(dbg_leds); i++) {
+                struct dbg_led *led;
+
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
 
-#ifdef  CONFIG_LEDS
-        leds_event = h2p2_dbg_leds_event;
-        leds_event(led_start);
-#endif
+                led->cdev.name = dbg_leds[i].name;
+                led->cdev.brightness_set = dbg_led_set;
+                led->cdev.brightness_get = dbg_led_get;
+                led->cdev.default_trigger = dbg_leds[i].trigger;
+                led->mask = BIT(i);
 
-        if (new_led_api()) {
-                newled_init(&pdev->dev);
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
         }
 
         return 0;
@@ -282,13 +121,15 @@ static int /* __init */ fpga_probe(struct platform_device *pdev)
 
 static int fpga_suspend_noirq(struct device *dev)
 {
-        __raw_writew(~0, &fpga->leds);
+        fpga_led_state = __raw_readw(&fpga->leds);
+        __raw_writew(0xff, &fpga->leds);
+
         return 0;
 }
 
 static int fpga_resume_noirq(struct device *dev)
 {
-        __raw_writew(~hw_led_state, &fpga->leds);
+        __raw_writew(~fpga_led_state, &fpga->leds);
         return 0;
 }
 
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index b2eac60b6904..f4a4cd014795 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -52,7 +52,7 @@
 
 #define OMAP_UART_DMA_CH_FREE   -1
 
-#define OMAP_MAX_HSUART_PORTS   4
+#define OMAP_MAX_HSUART_PORTS   6
 
 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
 
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index bd20588c356b..87ee140fefaa 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -4,6 +4,7 @@
 #define __ASM_ARCH_OMAP_USB_H
 
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #include <linux/usb/musb.h>
 
 #define OMAP3_HS_USB_PORTS      3
@@ -63,6 +64,10 @@ struct usbhs_omap_platform_data {
         struct ehci_hcd_omap_platform_data      *ehci_data;
         struct ohci_hcd_omap_platform_data      *ohci_data;
 };
+
+struct usbtll_omap_platform_data {
+        enum usbhs_omap_port_mode               port_mode[OMAP3_HS_USB_PORTS];
+};
 /*-------------------------------------------------------------------------*/
 
 struct omap_musb_board_data {
@@ -81,6 +86,8 @@ enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
 extern void usb_musb_init(struct omap_musb_board_data *board_data);
 
 extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
+extern int omap_tll_enable(void);
+extern int omap_tll_disable(void);
 
 extern int omap4430_phy_power(struct device *dev, int ID, int on);
 extern int omap4430_phy_set_clk(struct device *dev, int on);
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 5e13c3884aa4..42377ef9ea3d 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -310,7 +310,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
                 omap_mbox_disable_irq(mbox, IRQ_RX);
                 free_irq(mbox->irq, mbox);
                 tasklet_kill(&mbox->txq->tasklet);
-                flush_work_sync(&mbox->rxq->work);
+                flush_work(&mbox->rxq->work);
                 mbox_queue_free(mbox->txq);
                 mbox_queue_free(mbox->rxq);
         }
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 65c5eca475e7..012bbd0b8d81 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -119,7 +119,7 @@ void clk_disable(struct clk *clk)
 
 unsigned long clk_get_rate(struct clk *clk)
 {
-        if (IS_ERR(clk))
+        if (IS_ERR_OR_NULL(clk))
                 return 0;
 
         if (clk->rate != 0)
@@ -136,7 +136,7 @@ unsigned long clk_get_rate(struct clk *clk)
 
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
-        if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
+        if (!IS_ERR_OR_NULL(clk) && clk->ops && clk->ops->round_rate)
                 return (clk->ops->round_rate)(clk, rate);
 
         return rate;
@@ -144,9 +144,10 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
 
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
+        unsigned long flags;
         int ret;
 
-        if (IS_ERR(clk))
+        if (IS_ERR_OR_NULL(clk))
                 return -EINVAL;
 
         /* We do not default just do a clk->rate = rate as
@@ -159,9 +160,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
         if (clk->ops == NULL || clk->ops->set_rate == NULL)
                 return -EINVAL;
 
-        spin_lock(&clocks_lock);
+        spin_lock_irqsave(&clocks_lock, flags);
         ret = (clk->ops->set_rate)(clk, rate);
-        spin_unlock(&clocks_lock);
+        spin_unlock_irqrestore(&clocks_lock, flags);
 
         return ret;
 }
@@ -173,17 +174,18 @@ struct clk *clk_get_parent(struct clk *clk)
 
 int clk_set_parent(struct clk *clk, struct clk *parent)
 {
+        unsigned long flags;
         int ret = 0;
 
-        if (IS_ERR(clk))
+        if (IS_ERR_OR_NULL(clk) || IS_ERR_OR_NULL(parent))
                 return -EINVAL;
 
-        spin_lock(&clocks_lock);
+        spin_lock_irqsave(&clocks_lock, flags);
 
         if (clk->ops && clk->ops->set_parent)
                 ret = (clk->ops->set_parent)(clk, parent);
 
-        spin_unlock(&clocks_lock);
+        spin_unlock_irqrestore(&clocks_lock, flags);
 
         return ret;
 }
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index b151d4932661..03f654d55eff 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -51,6 +51,7 @@
 #include <linux/platform_data/usb-ehci-s5p.h>
 #include <plat/fb.h>
 #include <plat/fb-s3c2410.h>
+#include <plat/hdmi.h>
 #include <linux/platform_data/hwmon-s3c.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/keypad.h>
@@ -762,7 +763,7 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
                                &s5p_device_i2c_hdmiphy);
 }
 
-struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
+static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
 
 void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
                                   struct i2c_board_info *mhl_info, int mhl_bus)
@@ -1590,6 +1591,8 @@ struct platform_device s3c64xx_device_spi1 = {
 void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
                                                 int num_cs)
 {
+        struct s3c64xx_spi_info pd;
+
         /* Reject invalid configuration */
         if (!num_cs || src_clk_nr < 0) {
                 pr_err("%s: Invalid SPI configuration\n", __func__);
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
index 4dcb11c3d894..60552e22f22e 100644
--- a/arch/arm/plat-samsung/time.c
+++ b/arch/arm/plat-samsung/time.c
@@ -28,7 +28,6 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 
 #include <asm/irq.h>
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index 8d5c10a5084d..2a4ae8a6a081 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -16,8 +16,10 @@ config PLAT_VERSATILE_FPGA_IRQ_NR
        depends on PLAT_VERSATILE_FPGA_IRQ
 
 config PLAT_VERSATILE_LEDS
-        def_bool y if LEDS_CLASS
+        def_bool y if NEW_LEDS
         depends on ARCH_REALVIEW || ARCH_VERSATILE
+        select LEDS_CLASS
+        select LEDS_TRIGGER
 
 config PLAT_VERSATILE_SCHED_CLOCK
         def_bool y
diff --git a/arch/arm/plat-versatile/leds.c b/arch/arm/plat-versatile/leds.c
index 3169fa555ea6..d2490d00b46c 100644
--- a/arch/arm/plat-versatile/leds.c
+++ b/arch/arm/plat-versatile/leds.c
@@ -37,10 +37,10 @@ static const struct {
 } versatile_leds[] = {
         { "versatile:0", "heartbeat", },
         { "versatile:1", "mmc0", },
-        { "versatile:2", },
-        { "versatile:3", },
-        { "versatile:4", },
-        { "versatile:5", },
+        { "versatile:2", "cpu0" },
+        { "versatile:3", "cpu1" },
+        { "versatile:4", "cpu2" },
+        { "versatile:5", "cpu3" },
         { "versatile:6", },
         { "versatile:7", },
 };
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 7bc7948c5432..831e1fdfdb2f 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -66,7 +66,6 @@ iq80321			ARCH_IQ80321		IQ80321			169
 ks8695                  ARCH_KS8695             KS8695                  180
 karo                    ARCH_KARO               KARO                    190
 smdk2410                ARCH_SMDK2410           SMDK2410                193
-ceiva                   ARCH_CEIVA              CEIVA                   200
 voiceblue               MACH_VOICEBLUE          VOICEBLUE               218
 h5400                   ARCH_H5400              H5400                   220
 omap_innovator          MACH_OMAP_INNOVATOR     OMAP_INNOVATOR          234
diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
new file mode 100644
index 000000000000..43841033afd3
--- /dev/null
+++ b/arch/arm/xen/Makefile
@@ -0,0 +1 @@
+obj-y           := enlighten.o hypercall.o grant-table.o
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
new file mode 100644
index 000000000000..59bcb96ac369
--- /dev/null
+++ b/arch/arm/xen/enlighten.c
@@ -0,0 +1,168 @@
+#include <xen/xen.h>
+#include <xen/events.h>
+#include <xen/grant_table.h>
+#include <xen/hvm.h>
+#include <xen/interface/xen.h>
+#include <xen/interface/memory.h>
+#include <xen/interface/hvm/params.h>
+#include <xen/features.h>
+#include <xen/platform_pci.h>
+#include <xen/xenbus.h>
+#include <asm/xen/hypervisor.h>
+#include <asm/xen/hypercall.h>
+#include <linux/interrupt.h>
+#include <linux/irqreturn.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+
+struct start_info _xen_start_info;
+struct start_info *xen_start_info = &_xen_start_info;
+EXPORT_SYMBOL_GPL(xen_start_info);
+
+enum xen_domain_type xen_domain_type = XEN_NATIVE;
+EXPORT_SYMBOL_GPL(xen_domain_type);
+
+struct shared_info xen_dummy_shared_info;
+struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info;
+
+DEFINE_PER_CPU(struct vcpu_info *, xen_vcpu);
+
+/* TODO: to be removed */
+__read_mostly int xen_have_vector_callback;
+EXPORT_SYMBOL_GPL(xen_have_vector_callback);
+
+int xen_platform_pci_unplug = XEN_UNPLUG_ALL;
+EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
+
+static __read_mostly int xen_events_irq = -1;
+
+int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
+                               unsigned long addr,
+                               unsigned long mfn, int nr,
+                               pgprot_t prot, unsigned domid)
+{
+        return -ENOSYS;
+}
+EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
+
+/*
+ * see Documentation/devicetree/bindings/arm/xen.txt for the
+ * documentation of the Xen Device Tree format.
+ */
+#define GRANT_TABLE_PHYSADDR 0
+static int __init xen_guest_init(void)
+{
+        struct xen_add_to_physmap xatp;
+        static struct shared_info *shared_info_page = 0;
+        struct device_node *node;
+        int len;
+        const char *s = NULL;
+        const char *version = NULL;
+        const char *xen_prefix = "xen,xen-";
+        struct resource res;
+
+        node = of_find_compatible_node(NULL, NULL, "xen,xen");
+        if (!node) {
+                pr_debug("No Xen support\n");
+                return 0;
+        }
+        s = of_get_property(node, "compatible", &len);
+        if (strlen(xen_prefix) + 3  < len &&
+                        !strncmp(xen_prefix, s, strlen(xen_prefix)))
+                version = s + strlen(xen_prefix);
+        if (version == NULL) {
+                pr_debug("Xen version not found\n");
+                return 0;
+        }
+        if (of_address_to_resource(node, GRANT_TABLE_PHYSADDR, &res))
+                return 0;
+        xen_hvm_resume_frames = res.start >> PAGE_SHIFT;
+        xen_events_irq = irq_of_parse_and_map(node, 0);
+        pr_info("Xen %s support found, events_irq=%d gnttab_frame_pfn=%lx\n",
+                        version, xen_events_irq, xen_hvm_resume_frames);
+        xen_domain_type = XEN_HVM_DOMAIN;
+
+        xen_setup_features();
+        if (xen_feature(XENFEAT_dom0))
+                xen_start_info->flags |= SIF_INITDOMAIN|SIF_PRIVILEGED;
+        else
+                xen_start_info->flags &= ~(SIF_INITDOMAIN|SIF_PRIVILEGED);
+
+        if (!shared_info_page)
+                shared_info_page = (struct shared_info *)
+                        get_zeroed_page(GFP_KERNEL);
+        if (!shared_info_page) {
+                pr_err("not enough memory\n");
+                return -ENOMEM;
+        }
+        xatp.domid = DOMID_SELF;
+        xatp.idx = 0;
+        xatp.space = XENMAPSPACE_shared_info;
+        xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
+        if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
+                BUG();
+
+        HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
+
+        /* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
+         * page, we use it in the event channel upcall and in some pvclock
+         * related functions. We don't need the vcpu_info placement
+         * optimizations because we don't use any pv_mmu or pv_irq op on
+         * HVM.
+         * The shared info contains exactly 1 CPU (the boot CPU). The guest
+         * is required to use VCPUOP_register_vcpu_info to place vcpu info
+         * for secondary CPUs as they are brought up. */
+        per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
+
+        gnttab_init();
+        if (!xen_initial_domain())
+                xenbus_probe(NULL);
+
+        return 0;
+}
+core_initcall(xen_guest_init);
+
+static irqreturn_t xen_arm_callback(int irq, void *arg)
+{
+        xen_hvm_evtchn_do_upcall();
+        return IRQ_HANDLED;
+}
+
+static int __init xen_init_events(void)
+{
+        if (!xen_domain() || xen_events_irq < 0)
+                return -ENODEV;
+
+        xen_init_IRQ();
+
+        if (request_percpu_irq(xen_events_irq, xen_arm_callback,
+                        "events", xen_vcpu)) {
+                pr_err("Error requesting IRQ %d\n", xen_events_irq);
+                return -EINVAL;
+        }
+
+        enable_percpu_irq(xen_events_irq, 0);
+
+        return 0;
+}
+postcore_initcall(xen_init_events);
+
+/* XXX: only until balloon is properly working */
+int alloc_xenballooned_pages(int nr_pages, struct page **pages, bool highmem)
+{
+        *pages = alloc_pages(highmem ? GFP_HIGHUSER : GFP_KERNEL,
+                        get_order(nr_pages));
+        if (*pages == NULL)
+                return -ENOMEM;
+        return 0;
+}
+EXPORT_SYMBOL_GPL(alloc_xenballooned_pages);
+
+void free_xenballooned_pages(int nr_pages, struct page **pages)
+{
+        kfree(*pages);
+        *pages = NULL;
+}
+EXPORT_SYMBOL_GPL(free_xenballooned_pages);
diff --git a/arch/arm/xen/grant-table.c b/arch/arm/xen/grant-table.c
new file mode 100644
index 000000000000..dbd1330c0196
--- /dev/null
+++ b/arch/arm/xen/grant-table.c
@@ -0,0 +1,53 @@
+/******************************************************************************
+ * grant_table.c
+ * ARM specific part
+ *
+ * Granting foreign access to our memory reservation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <xen/interface/xen.h>
+#include <xen/page.h>
+#include <xen/grant_table.h>
+
+int arch_gnttab_map_shared(unsigned long *frames, unsigned long nr_gframes,
+                           unsigned long max_nr_gframes,
+                           void **__shared)
+{
+        return -ENOSYS;
+}
+
+void arch_gnttab_unmap(void *shared, unsigned long nr_gframes)
+{
+        return;
+}
+
+int arch_gnttab_map_status(uint64_t *frames, unsigned long nr_gframes,
+                           unsigned long max_nr_gframes,
+                           grant_status_t **__shared)
+{
+        return -ENOSYS;
+}
diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S
new file mode 100644
index 000000000000..074f5ed101b9
--- /dev/null
+++ b/arch/arm/xen/hypercall.S
@@ -0,0 +1,106 @@
+/******************************************************************************
+ * hypercall.S
+ *
+ * Xen hypercall wrappers
+ *
+ * Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/*
+ * The Xen hypercall calling convention is very similar to the ARM
+ * procedure calling convention: the first paramter is passed in r0, the
+ * second in r1, the third in r2 and the fourth in r3. Considering that
+ * Xen hypercalls have 5 arguments at most, the fifth paramter is passed
+ * in r4, differently from the procedure calling convention of using the
+ * stack for that case.
+ *
+ * The hypercall number is passed in r12.
+ *
+ * The return value is in r0.
+ *
+ * The hvc ISS is required to be 0xEA1, that is the Xen specific ARM
+ * hypercall tag.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <xen/interface/xen.h>
+
+
+/* HVC 0xEA1 */
+#ifdef CONFIG_THUMB2_KERNEL
+#define xen_hvc .word 0xf7e08ea1
+#else
+#define xen_hvc .word 0xe140ea71
+#endif
+
+#define HYPERCALL_SIMPLE(hypercall)             \
+ENTRY(HYPERVISOR_##hypercall)                   \
+        mov r12, #__HYPERVISOR_##hypercall;     \
+        xen_hvc;                                                        \
+        mov pc, lr;                                                     \
+ENDPROC(HYPERVISOR_##hypercall)
+
+#define HYPERCALL0 HYPERCALL_SIMPLE
+#define HYPERCALL1 HYPERCALL_SIMPLE
+#define HYPERCALL2 HYPERCALL_SIMPLE
+#define HYPERCALL3 HYPERCALL_SIMPLE
+#define HYPERCALL4 HYPERCALL_SIMPLE
+
+#define HYPERCALL5(hypercall)                   \
+ENTRY(HYPERVISOR_##hypercall)                   \
+        stmdb sp!, {r4}                                         \
+        ldr r4, [sp, #4]                                        \
+        mov r12, #__HYPERVISOR_##hypercall;     \
+        xen_hvc                                                         \
+        ldm sp!, {r4}                                           \
+        mov pc, lr                                                      \
+ENDPROC(HYPERVISOR_##hypercall)
+
+                .text
+
+HYPERCALL2(xen_version);
+HYPERCALL3(console_io);
+HYPERCALL3(grant_table_op);
+HYPERCALL2(sched_op);
+HYPERCALL2(event_channel_op);
+HYPERCALL2(hvm_op);
+HYPERCALL2(memory_op);
+HYPERCALL2(physdev_op);
+
+ENTRY(privcmd_call)
+        stmdb sp!, {r4}
+        mov r12, r0
+        mov r0, r1
+        mov r1, r2
+        mov r2, r3
+        ldr r3, [sp, #8]
+        ldr r4, [sp, #4]
+        xen_hvc
+        ldm sp!, {r4}
+        mov pc, lr
+ENDPROC(privcmd_call);