aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig.debug2
-rw-r--r--arch/arm/boot/compressed/head.S20
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts2
-rw-r--r--arch/arm/boot/dts/am437x-gp-evm.dts4
-rw-r--r--arch/arm/boot/dts/am437x-sk-evm.dts4
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts4
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi5
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts1
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts2
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi2
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi4
-rw-r--r--arch/arm/boot/dts/sama5d31.dtsi2
-rw-r--r--arch/arm/boot/dts/sama5d33.dtsi2
-rw-r--r--arch/arm/boot/dts/sama5d34.dtsi2
-rw-r--r--arch/arm/boot/dts/sama5d35.dtsi2
-rw-r--r--arch/arm/boot/dts/sama5d36.dtsi2
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi2
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi12
-rw-r--r--arch/arm/boot/dts/socfpga_arria5.dtsi2
-rw-r--r--arch/arm/boot/dts/socfpga_arria5_socdk.dts12
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_socdk.dts15
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_sockit.dts12
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi4
-rw-r--r--arch/arm/boot/dts/vf610-cosmic.dts19
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi24
-rw-r--r--arch/arm/boot/dts/zynq-parallella.dts4
-rw-r--r--arch/arm/common/edma.c9
-rw-r--r--arch/arm/configs/imx_v4_v5_defconfig1
-rw-r--r--arch/arm/configs/imx_v6_v7_defconfig1
-rw-r--r--arch/arm/configs/multi_v7_defconfig4
-rw-r--r--arch/arm/configs/omap2plus_defconfig4
-rw-r--r--arch/arm/configs/socfpga_defconfig71
-rw-r--r--arch/arm/configs/sunxi_defconfig1
-rw-r--r--arch/arm/include/uapi/asm/unistd.h1
-rw-r--r--arch/arm/kernel/asm-offsets.c12
-rw-r--r--arch/arm/kernel/calls.S1
-rw-r--r--arch/arm/mach-highbank/highbank.c2
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c14
-rw-r--r--arch/arm/mach-imx/clk-vf610.c134
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/io.h4
-rw-r--r--arch/arm/mach-mvebu/board-v7.c2
-rw-r--r--arch/arm/mach-omap2/omap_device.c4
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c3
-rw-r--r--arch/arm/mach-pxa/include/mach/addr-map.h5
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c9
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c2
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c20
-rw-r--r--arch/arm/mach-socfpga/core.h2
-rw-r--r--arch/arm/mach-socfpga/headsmp.S25
-rw-r--r--arch/arm/mach-socfpga/platsmp.c4
-rw-r--r--arch/arm/mach-socfpga/socfpga.c4
-rw-r--r--arch/arm/mm/Kconfig1
-rw-r--r--arch/arm/mm/cache-l2x0.c26
-rw-r--r--arch/arm/mm/dma-mapping.c1
-rw-r--r--arch/arm/mm/highmem.c3
-rw-r--r--arch/arm/mm/init.c8
-rw-r--r--arch/arm/plat-orion/gpio.c36
57 files changed, 404 insertions, 176 deletions
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 03dc4c1a8736..d8f6a2ec3d4e 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1187,7 +1187,7 @@ config DEBUG_UART_VIRT
1187 default 0xf1c28000 if DEBUG_SUNXI_UART0 1187 default 0xf1c28000 if DEBUG_SUNXI_UART0
1188 default 0xf1c28400 if DEBUG_SUNXI_UART1 1188 default 0xf1c28400 if DEBUG_SUNXI_UART1
1189 default 0xf1f02800 if DEBUG_SUNXI_R_UART 1189 default 0xf1f02800 if DEBUG_SUNXI_R_UART
1190 default 0xf2100000 if DEBUG_PXA_UART1 1190 default 0xf6200000 if DEBUG_PXA_UART1
1191 default 0xf4090000 if ARCH_LPC32XX 1191 default 0xf4090000 if ARCH_LPC32XX
1192 default 0xf4200000 if ARCH_GEMINI 1192 default 0xf4200000 if ARCH_GEMINI
1193 default 0xf7000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \ 1193 default 0xf7000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 413fd94b5301..68be9017593d 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -397,8 +397,7 @@ dtb_check_done:
397 add sp, sp, r6 397 add sp, sp, r6
398#endif 398#endif
399 399
400 tst r4, #1 400 bl cache_clean_flush
401 bleq cache_clean_flush
402 401
403 adr r0, BSYM(restart) 402 adr r0, BSYM(restart)
404 add r0, r0, r6 403 add r0, r0, r6
@@ -1047,6 +1046,8 @@ cache_clean_flush:
1047 b call_cache_fn 1046 b call_cache_fn
1048 1047
1049__armv4_mpu_cache_flush: 1048__armv4_mpu_cache_flush:
1049 tst r4, #1
1050 movne pc, lr
1050 mov r2, #1 1051 mov r2, #1
1051 mov r3, #0 1052 mov r3, #0
1052 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 1053 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -1064,6 +1065,8 @@ __armv4_mpu_cache_flush:
1064 mov pc, lr 1065 mov pc, lr
1065 1066
1066__fa526_cache_flush: 1067__fa526_cache_flush:
1068 tst r4, #1
1069 movne pc, lr
1067 mov r1, #0 1070 mov r1, #0
1068 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache 1071 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1069 mcr p15, 0, r1, c7, c5, 0 @ flush I cache 1072 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
@@ -1072,13 +1075,16 @@ __fa526_cache_flush:
1072 1075
1073__armv6_mmu_cache_flush: 1076__armv6_mmu_cache_flush:
1074 mov r1, #0 1077 mov r1, #0
1075 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D 1078 tst r4, #1
1079 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1076 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB 1080 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1077 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified 1081 mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1078 mcr p15, 0, r1, c7, c10, 4 @ drain WB 1082 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1079 mov pc, lr 1083 mov pc, lr
1080 1084
1081__armv7_mmu_cache_flush: 1085__armv7_mmu_cache_flush:
1086 tst r4, #1
1087 bne iflush
1082 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 1088 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1083 tst r10, #0xf << 16 @ hierarchical cache (ARMv7) 1089 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1084 mov r10, #0 1090 mov r10, #0
@@ -1139,6 +1145,8 @@ iflush:
1139 mov pc, lr 1145 mov pc, lr
1140 1146
1141__armv5tej_mmu_cache_flush: 1147__armv5tej_mmu_cache_flush:
1148 tst r4, #1
1149 movne pc, lr
11421: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache 11501: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1143 bne 1b 1151 bne 1b
1144 mcr p15, 0, r0, c7, c5, 0 @ flush I cache 1152 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
@@ -1146,6 +1154,8 @@ __armv5tej_mmu_cache_flush:
1146 mov pc, lr 1154 mov pc, lr
1147 1155
1148__armv4_mmu_cache_flush: 1156__armv4_mmu_cache_flush:
1157 tst r4, #1
1158 movne pc, lr
1149 mov r2, #64*1024 @ default: 32K dcache size (*2) 1159 mov r2, #64*1024 @ default: 32K dcache size (*2)
1150 mov r11, #32 @ default: 32 byte line size 1160 mov r11, #32 @ default: 32 byte line size
1151 mrc p15, 0, r3, c0, c0, 1 @ read cache type 1161 mrc p15, 0, r3, c0, c0, 1 @ read cache type
@@ -1179,6 +1189,8 @@ no_cache_id:
1179 1189
1180__armv3_mmu_cache_flush: 1190__armv3_mmu_cache_flush:
1181__armv3_mpu_cache_flush: 1191__armv3_mpu_cache_flush:
1192 tst r4, #1
1193 movne pc, lr
1182 mov r1, #0 1194 mov r1, #0
1183 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3 1195 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1184 mov pc, lr 1196 mov pc, lr
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index e2156a583de7..c4b968f0feb5 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -489,7 +489,7 @@
489 reg = <0x00060000 0x00020000>; 489 reg = <0x00060000 0x00020000>;
490 }; 490 };
491 partition@4 { 491 partition@4 {
492 label = "NAND.u-boot-spl"; 492 label = "NAND.u-boot-spl-os";
493 reg = <0x00080000 0x00040000>; 493 reg = <0x00080000 0x00040000>;
494 }; 494 };
495 partition@5 { 495 partition@5 {
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index e7ac47fa6615..a521ac0a7d5a 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -291,8 +291,8 @@
291 dcdc3: regulator-dcdc3 { 291 dcdc3: regulator-dcdc3 {
292 compatible = "ti,tps65218-dcdc3"; 292 compatible = "ti,tps65218-dcdc3";
293 regulator-name = "vdcdc3"; 293 regulator-name = "vdcdc3";
294 regulator-min-microvolt = <1350000>; 294 regulator-min-microvolt = <1500000>;
295 regulator-max-microvolt = <1350000>; 295 regulator-max-microvolt = <1500000>;
296 regulator-boot-on; 296 regulator-boot-on;
297 regulator-always-on; 297 regulator-always-on;
298 }; 298 };
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 859ff3d620ee..87aa4f3b8b3d 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -363,8 +363,8 @@
363 dcdc3: regulator-dcdc3 { 363 dcdc3: regulator-dcdc3 {
364 compatible = "ti,tps65218-dcdc3"; 364 compatible = "ti,tps65218-dcdc3";
365 regulator-name = "vdds_ddr"; 365 regulator-name = "vdds_ddr";
366 regulator-min-microvolt = <1350000>; 366 regulator-min-microvolt = <1500000>;
367 regulator-max-microvolt = <1350000>; 367 regulator-max-microvolt = <1500000>;
368 regulator-boot-on; 368 regulator-boot-on;
369 regulator-always-on; 369 regulator-always-on;
370 }; 370 };
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index ac3e4859935f..f7e9bba10bd6 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -358,8 +358,8 @@
358 dcdc3: regulator-dcdc3 { 358 dcdc3: regulator-dcdc3 {
359 compatible = "ti,tps65218-dcdc3"; 359 compatible = "ti,tps65218-dcdc3";
360 regulator-name = "vdcdc3"; 360 regulator-name = "vdcdc3";
361 regulator-min-microvolt = <1350000>; 361 regulator-min-microvolt = <1500000>;
362 regulator-max-microvolt = <1350000>; 362 regulator-max-microvolt = <1500000>;
363 regulator-boot-on; 363 regulator-boot-on;
364 regulator-always-on; 364 regulator-always-on;
365 }; 365 };
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index d68b3c4862bc..51416c7d0625 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -122,9 +122,10 @@
122 interrupts-extended = <&pmc AT91_PMC_LOCKB>; 122 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
123 clocks = <&main>; 123 clocks = <&main>;
124 reg = <1>; 124 reg = <1>;
125 atmel,clk-input-range = <1000000 5000000>; 125 atmel,clk-input-range = <1000000 32000000>;
126 #atmel,pll-clk-output-range-cells = <4>; 126 #atmel,pll-clk-output-range-cells = <4>;
127 atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; 127 atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
128 <190000000 240000000 2 1>;
128 }; 129 };
129 130
130 mck: masterck { 131 mck: masterck {
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 09664fcf5afb..0e13b4b10a92 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -193,7 +193,6 @@
193 i2c0: i2c@80058000 { 193 i2c0: i2c@80058000 {
194 pinctrl-names = "default"; 194 pinctrl-names = "default";
195 pinctrl-0 = <&i2c0_pins_a>; 195 pinctrl-0 = <&i2c0_pins_a>;
196 clock-frequency = <400000>;
197 status = "okay"; 196 status = "okay";
198 197
199 sgtl5000: codec@0a { 198 sgtl5000: codec@0a {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 739fcf29c643..bc82a12d4c2c 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -668,6 +668,8 @@
668 bank-width = <2>; 668 bank-width = <2>;
669 pinctrl-names = "default"; 669 pinctrl-names = "default";
670 pinctrl-0 = <&ethernet_pins>; 670 pinctrl-0 = <&ethernet_pins>;
671 power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */
672 reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */
671 gpmc,device-width = <2>; 673 gpmc,device-width = <2>;
672 gpmc,sync-clk-ps = <0>; 674 gpmc,sync-clk-ps = <0>;
673 gpmc,cs-on-ns = <0>; 675 gpmc,cs-on-ns = <0>;
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index d46c213a17ad..eed697a6bd6b 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -433,7 +433,7 @@
433 clocks = <&cpg_clocks R8A7740_CLK_S>, 433 clocks = <&cpg_clocks R8A7740_CLK_S>,
434 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, 434 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
435 <&cpg_clocks R8A7740_CLK_B>, 435 <&cpg_clocks R8A7740_CLK_B>,
436 <&sub_clk>, <&sub_clk>, 436 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
437 <&cpg_clocks R8A7740_CLK_B>; 437 <&cpg_clocks R8A7740_CLK_B>;
438 #clock-cells = <1>; 438 #clock-cells = <1>;
439 renesas,clock-indices = < 439 renesas,clock-indices = <
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index d0e17733dc1a..e20affe156c1 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -666,9 +666,9 @@
666 #clock-cells = <0>; 666 #clock-cells = <0>;
667 clock-output-names = "sd2"; 667 clock-output-names = "sd2";
668 }; 668 };
669 sd3_clk: sd3_clk@e615007c { 669 sd3_clk: sd3_clk@e615026c {
670 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; 670 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
671 reg = <0 0xe615007c 0 4>; 671 reg = <0 0xe615026c 0 4>;
672 clocks = <&pll1_div2_clk>; 672 clocks = <&pll1_div2_clk>;
673 #clock-cells = <0>; 673 #clock-cells = <0>;
674 clock-output-names = "sd3"; 674 clock-output-names = "sd3";
diff --git a/arch/arm/boot/dts/sama5d31.dtsi b/arch/arm/boot/dts/sama5d31.dtsi
index 7997dc9863ed..883878b32971 100644
--- a/arch/arm/boot/dts/sama5d31.dtsi
+++ b/arch/arm/boot/dts/sama5d31.dtsi
@@ -12,5 +12,5 @@
12#include "sama5d3_uart.dtsi" 12#include "sama5d3_uart.dtsi"
13 13
14/ { 14/ {
15 compatible = "atmel,samad31", "atmel,sama5d3", "atmel,sama5"; 15 compatible = "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
16}; 16};
diff --git a/arch/arm/boot/dts/sama5d33.dtsi b/arch/arm/boot/dts/sama5d33.dtsi
index 39f832253caf..4b4434aca351 100644
--- a/arch/arm/boot/dts/sama5d33.dtsi
+++ b/arch/arm/boot/dts/sama5d33.dtsi
@@ -10,5 +10,5 @@
10#include "sama5d3_gmac.dtsi" 10#include "sama5d3_gmac.dtsi"
11 11
12/ { 12/ {
13 compatible = "atmel,samad33", "atmel,sama5d3", "atmel,sama5"; 13 compatible = "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5";
14}; 14};
diff --git a/arch/arm/boot/dts/sama5d34.dtsi b/arch/arm/boot/dts/sama5d34.dtsi
index 89cda2c0da39..aa01573fdee9 100644
--- a/arch/arm/boot/dts/sama5d34.dtsi
+++ b/arch/arm/boot/dts/sama5d34.dtsi
@@ -12,5 +12,5 @@
12#include "sama5d3_mci2.dtsi" 12#include "sama5d3_mci2.dtsi"
13 13
14/ { 14/ {
15 compatible = "atmel,samad34", "atmel,sama5d3", "atmel,sama5"; 15 compatible = "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5";
16}; 16};
diff --git a/arch/arm/boot/dts/sama5d35.dtsi b/arch/arm/boot/dts/sama5d35.dtsi
index d20cd71b5f0e..16c39f4c96a4 100644
--- a/arch/arm/boot/dts/sama5d35.dtsi
+++ b/arch/arm/boot/dts/sama5d35.dtsi
@@ -14,5 +14,5 @@
14#include "sama5d3_tcb1.dtsi" 14#include "sama5d3_tcb1.dtsi"
15 15
16/ { 16/ {
17 compatible = "atmel,samad35", "atmel,sama5d3", "atmel,sama5"; 17 compatible = "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5";
18}; 18};
diff --git a/arch/arm/boot/dts/sama5d36.dtsi b/arch/arm/boot/dts/sama5d36.dtsi
index db58cad6acd3..e85139ef40af 100644
--- a/arch/arm/boot/dts/sama5d36.dtsi
+++ b/arch/arm/boot/dts/sama5d36.dtsi
@@ -16,5 +16,5 @@
16#include "sama5d3_uart.dtsi" 16#include "sama5d3_uart.dtsi"
17 17
18/ { 18/ {
19 compatible = "atmel,samad36", "atmel,sama5d3", "atmel,sama5"; 19 compatible = "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5";
20}; 20};
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 962dc28dc37b..cfcd200b0c17 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -8,7 +8,7 @@
8 */ 8 */
9 9
10/ { 10/ {
11 compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5"; 11 compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
12 12
13 chosen { 13 chosen {
14 bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; 14 bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs";
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 45fce2cf6fed..4472fd92685c 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -547,7 +547,7 @@
547 status = "disabled"; 547 status = "disabled";
548 }; 548 };
549 549
550 gpio@ff708000 { 550 gpio0: gpio@ff708000 {
551 #address-cells = <1>; 551 #address-cells = <1>;
552 #size-cells = <0>; 552 #size-cells = <0>;
553 compatible = "snps,dw-apb-gpio"; 553 compatible = "snps,dw-apb-gpio";
@@ -555,7 +555,7 @@
555 clocks = <&per_base_clk>; 555 clocks = <&per_base_clk>;
556 status = "disabled"; 556 status = "disabled";
557 557
558 gpio0: gpio-controller@0 { 558 porta: gpio-controller@0 {
559 compatible = "snps,dw-apb-gpio-port"; 559 compatible = "snps,dw-apb-gpio-port";
560 gpio-controller; 560 gpio-controller;
561 #gpio-cells = <2>; 561 #gpio-cells = <2>;
@@ -567,7 +567,7 @@
567 }; 567 };
568 }; 568 };
569 569
570 gpio@ff709000 { 570 gpio1: gpio@ff709000 {
571 #address-cells = <1>; 571 #address-cells = <1>;
572 #size-cells = <0>; 572 #size-cells = <0>;
573 compatible = "snps,dw-apb-gpio"; 573 compatible = "snps,dw-apb-gpio";
@@ -575,7 +575,7 @@
575 clocks = <&per_base_clk>; 575 clocks = <&per_base_clk>;
576 status = "disabled"; 576 status = "disabled";
577 577
578 gpio1: gpio-controller@0 { 578 portb: gpio-controller@0 {
579 compatible = "snps,dw-apb-gpio-port"; 579 compatible = "snps,dw-apb-gpio-port";
580 gpio-controller; 580 gpio-controller;
581 #gpio-cells = <2>; 581 #gpio-cells = <2>;
@@ -587,7 +587,7 @@
587 }; 587 };
588 }; 588 };
589 589
590 gpio@ff70a000 { 590 gpio2: gpio@ff70a000 {
591 #address-cells = <1>; 591 #address-cells = <1>;
592 #size-cells = <0>; 592 #size-cells = <0>;
593 compatible = "snps,dw-apb-gpio"; 593 compatible = "snps,dw-apb-gpio";
@@ -595,7 +595,7 @@
595 clocks = <&per_base_clk>; 595 clocks = <&per_base_clk>;
596 status = "disabled"; 596 status = "disabled";
597 597
598 gpio2: gpio-controller@0 { 598 portc: gpio-controller@0 {
599 compatible = "snps,dw-apb-gpio-port"; 599 compatible = "snps,dw-apb-gpio-port";
600 gpio-controller; 600 gpio-controller;
601 #gpio-cells = <2>; 601 #gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 03e8268ae219..1907cc600452 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -29,7 +29,7 @@
29 }; 29 };
30 }; 30 };
31 31
32 dwmmc0@ff704000 { 32 mmc0: dwmmc0@ff704000 {
33 num-slots = <1>; 33 num-slots = <1>;
34 broken-cd; 34 broken-cd;
35 bus-width = <4>; 35 bus-width = <4>;
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 27d551c384d0..ccaf41742fc3 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: 3-3-v-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "3.3V";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -68,6 +75,11 @@
68 }; 75 };
69}; 76};
70 77
78&mmc0 {
79 vmmc-supply = <&regulator_3_3v>;
80 vqmmc-supply = <&regulator_3_3v>;
81};
82
71&usb1 { 83&usb1 {
72 status = "okay"; 84 status = "okay";
73}; 85};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index d7296a5f750c..258865da8f6a 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: 3-3-v-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "3.3V";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -53,6 +60,10 @@
53 rxc-skew-ps = <2000>; 60 rxc-skew-ps = <2000>;
54}; 61};
55 62
63&gpio1 {
64 status = "okay";
65};
66
56&i2c0 { 67&i2c0 {
57 status = "okay"; 68 status = "okay";
58 69
@@ -69,7 +80,9 @@
69}; 80};
70 81
71&mmc0 { 82&mmc0 {
72 cd-gpios = <&gpio1 18 0>; 83 cd-gpios = <&portb 18 0>;
84 vmmc-supply = <&regulator_3_3v>;
85 vqmmc-supply = <&regulator_3_3v>;
73}; 86};
74 87
75&usb1 { 88&usb1 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index d26f155f5fd9..16ea6f5f2ab8 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: vcc3p3-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "VCC3P3";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -53,6 +60,11 @@
53 rxc-skew-ps = <2000>; 60 rxc-skew-ps = <2000>;
54}; 61};
55 62
63&mmc0 {
64 vmmc-supply = <&regulator_3_3v>;
65 vqmmc-supply = <&regulator_3_3v>;
66};
67
56&usb1 { 68&usb1 {
57 status = "okay"; 69 status = "okay";
58}; 70};
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 543f895d18d3..2e652e2339e9 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -361,6 +361,10 @@
361 clocks = <&ahb1_gates 6>; 361 clocks = <&ahb1_gates 6>;
362 resets = <&ahb1_rst 6>; 362 resets = <&ahb1_rst 6>;
363 #dma-cells = <1>; 363 #dma-cells = <1>;
364
365 /* DMA controller requires AHB1 clocked from PLL6 */
366 assigned-clocks = <&ahb1_mux>;
367 assigned-clock-parents = <&pll6>;
364 }; 368 };
365 369
366 mmc0: mmc@01c0f000 { 370 mmc0: mmc@01c0f000 {
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts
index 3fd1b74e1216..de1b453c2932 100644
--- a/arch/arm/boot/dts/vf610-cosmic.dts
+++ b/arch/arm/boot/dts/vf610-cosmic.dts
@@ -33,6 +33,13 @@
33 33
34}; 34};
35 35
36&esdhc1 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_esdhc1>;
39 bus-width = <4>;
40 status = "okay";
41};
42
36&fec1 { 43&fec1 {
37 phy-mode = "rmii"; 44 phy-mode = "rmii";
38 pinctrl-names = "default"; 45 pinctrl-names = "default";
@@ -42,6 +49,18 @@
42 49
43&iomuxc { 50&iomuxc {
44 vf610-cosmic { 51 vf610-cosmic {
52 pinctrl_esdhc1: esdhc1grp {
53 fsl,pins = <
54 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
55 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
56 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
57 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
58 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
59 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
60 VF610_PAD_PTB28__GPIO_98 0x219d
61 >;
62 };
63
45 pinctrl_fec1: fec1grp { 64 pinctrl_fec1: fec1grp {
46 fsl,pins = < 65 fsl,pins = <
47 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 66 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 24036c440440..ce2ef5bec4f2 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -30,7 +30,6 @@
30 /* kHz uV */ 30 /* kHz uV */
31 666667 1000000 31 666667 1000000
32 333334 1000000 32 333334 1000000
33 222223 1000000
34 >; 33 >;
35 }; 34 };
36 35
@@ -65,7 +64,7 @@
65 interrupt-parent = <&intc>; 64 interrupt-parent = <&intc>;
66 ranges; 65 ranges;
67 66
68 adc@f8007100 { 67 adc: adc@f8007100 {
69 compatible = "xlnx,zynq-xadc-1.00.a"; 68 compatible = "xlnx,zynq-xadc-1.00.a";
70 reg = <0xf8007100 0x20>; 69 reg = <0xf8007100 0x20>;
71 interrupts = <0 7 4>; 70 interrupts = <0 7 4>;
@@ -137,7 +136,7 @@
137 <0xF8F00100 0x100>; 136 <0xF8F00100 0x100>;
138 }; 137 };
139 138
140 L2: cache-controller { 139 L2: cache-controller@f8f02000 {
141 compatible = "arm,pl310-cache"; 140 compatible = "arm,pl310-cache";
142 reg = <0xF8F02000 0x1000>; 141 reg = <0xF8F02000 0x1000>;
143 arm,data-latency = <3 2 2>; 142 arm,data-latency = <3 2 2>;
@@ -146,10 +145,10 @@
146 cache-level = <2>; 145 cache-level = <2>;
147 }; 146 };
148 147
149 memory-controller@f8006000 { 148 mc: memory-controller@f8006000 {
150 compatible = "xlnx,zynq-ddrc-a05"; 149 compatible = "xlnx,zynq-ddrc-a05";
151 reg = <0xf8006000 0x1000>; 150 reg = <0xf8006000 0x1000>;
152 } ; 151 };
153 152
154 uart0: serial@e0000000 { 153 uart0: serial@e0000000 {
155 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 154 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
@@ -195,7 +194,7 @@
195 194
196 gem0: ethernet@e000b000 { 195 gem0: ethernet@e000b000 {
197 compatible = "cdns,gem"; 196 compatible = "cdns,gem";
198 reg = <0xe000b000 0x4000>; 197 reg = <0xe000b000 0x1000>;
199 status = "disabled"; 198 status = "disabled";
200 interrupts = <0 22 4>; 199 interrupts = <0 22 4>;
201 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 200 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
@@ -206,7 +205,7 @@
206 205
207 gem1: ethernet@e000c000 { 206 gem1: ethernet@e000c000 {
208 compatible = "cdns,gem"; 207 compatible = "cdns,gem";
209 reg = <0xe000c000 0x4000>; 208 reg = <0xe000c000 0x1000>;
210 status = "disabled"; 209 status = "disabled";
211 interrupts = <0 45 4>; 210 interrupts = <0 45 4>;
212 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 211 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
@@ -315,5 +314,16 @@
315 reg = <0xf8f00600 0x20>; 314 reg = <0xf8f00600 0x20>;
316 clocks = <&clkc 4>; 315 clocks = <&clkc 4>;
317 }; 316 };
317
318 watchdog0: watchdog@f8005000 {
319 clocks = <&clkc 45>;
320 compatible = "xlnx,zynq-wdt-r1p2";
321 device_type = "watchdog";
322 interrupt-parent = <&intc>;
323 interrupts = <0 9 1>;
324 reg = <0xf8005000 0x1000>;
325 reset = <0>;
326 timeout-sec = <10>;
327 };
318 }; 328 };
319}; 329};
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index e1f51ca127fe..0429bbd89fba 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -34,6 +34,10 @@
34 }; 34 };
35}; 35};
36 36
37&clkc {
38 fclk-enable = <0xf>;
39};
40
37&gem0 { 41&gem0 {
38 status = "okay"; 42 status = "okay";
39 phy-mode = "rgmii-id"; 43 phy-mode = "rgmii-id";
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index d86771abbf57..72041f002b7e 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -26,6 +26,7 @@
26#include <linux/io.h> 26#include <linux/io.h>
27#include <linux/slab.h> 27#include <linux/slab.h>
28#include <linux/edma.h> 28#include <linux/edma.h>
29#include <linux/dma-mapping.h>
29#include <linux/of_address.h> 30#include <linux/of_address.h>
30#include <linux/of_device.h> 31#include <linux/of_device.h>
31#include <linux/of_dma.h> 32#include <linux/of_dma.h>
@@ -1623,6 +1624,11 @@ static int edma_probe(struct platform_device *pdev)
1623 struct device_node *node = pdev->dev.of_node; 1624 struct device_node *node = pdev->dev.of_node;
1624 struct device *dev = &pdev->dev; 1625 struct device *dev = &pdev->dev;
1625 int ret; 1626 int ret;
1627 struct platform_device_info edma_dev_info = {
1628 .name = "edma-dma-engine",
1629 .dma_mask = DMA_BIT_MASK(32),
1630 .parent = &pdev->dev,
1631 };
1626 1632
1627 if (node) { 1633 if (node) {
1628 /* Check if this is a second instance registered */ 1634 /* Check if this is a second instance registered */
@@ -1793,6 +1799,9 @@ static int edma_probe(struct platform_device *pdev)
1793 edma_write_array(j, EDMA_QRAE, i, 0x0); 1799 edma_write_array(j, EDMA_QRAE, i, 0x0);
1794 } 1800 }
1795 arch_num_cc++; 1801 arch_num_cc++;
1802
1803 edma_dev_info.id = j;
1804 platform_device_register_full(&edma_dev_info);
1796 } 1805 }
1797 1806
1798 return 0; 1807 return 0;
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index e688741c89aa..e6b0007355f8 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -97,6 +97,7 @@ CONFIG_SERIAL_IMX_CONSOLE=y
97# CONFIG_HW_RANDOM is not set 97# CONFIG_HW_RANDOM is not set
98CONFIG_I2C_CHARDEV=y 98CONFIG_I2C_CHARDEV=y
99CONFIG_I2C_IMX=y 99CONFIG_I2C_IMX=y
100CONFIG_SPI=y
100CONFIG_SPI_IMX=y 101CONFIG_SPI_IMX=y
101CONFIG_SPI_SPIDEV=y 102CONFIG_SPI_SPIDEV=y
102CONFIG_GPIO_SYSFS=y 103CONFIG_GPIO_SYSFS=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 8fca6e276b69..6790f1b3f3a1 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -158,6 +158,7 @@ CONFIG_I2C_CHARDEV=y
158CONFIG_I2C_ALGOPCF=m 158CONFIG_I2C_ALGOPCF=m
159CONFIG_I2C_ALGOPCA=m 159CONFIG_I2C_ALGOPCA=m
160CONFIG_I2C_IMX=y 160CONFIG_I2C_IMX=y
161CONFIG_SPI=y
161CONFIG_SPI_IMX=y 162CONFIG_SPI_IMX=y
162CONFIG_GPIO_SYSFS=y 163CONFIG_GPIO_SYSFS=y
163CONFIG_GPIO_MC9S08DZ60=y 164CONFIG_GPIO_MC9S08DZ60=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 491b7d5523bf..3487046d8a78 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -235,6 +235,7 @@ CONFIG_SPI_TEGRA20_SLINK=y
235CONFIG_SPI_XILINX=y 235CONFIG_SPI_XILINX=y
236CONFIG_PINCTRL_AS3722=y 236CONFIG_PINCTRL_AS3722=y
237CONFIG_PINCTRL_PALMAS=y 237CONFIG_PINCTRL_PALMAS=y
238CONFIG_PINCTRL_APQ8084=y
238CONFIG_GPIO_SYSFS=y 239CONFIG_GPIO_SYSFS=y
239CONFIG_GPIO_GENERIC_PLATFORM=y 240CONFIG_GPIO_GENERIC_PLATFORM=y
240CONFIG_GPIO_DWAPB=y 241CONFIG_GPIO_DWAPB=y
@@ -261,6 +262,7 @@ CONFIG_WATCHDOG=y
261CONFIG_XILINX_WATCHDOG=y 262CONFIG_XILINX_WATCHDOG=y
262CONFIG_ORION_WATCHDOG=y 263CONFIG_ORION_WATCHDOG=y
263CONFIG_SUNXI_WATCHDOG=y 264CONFIG_SUNXI_WATCHDOG=y
265CONFIG_MESON_WATCHDOG=y
264CONFIG_MFD_AS3722=y 266CONFIG_MFD_AS3722=y
265CONFIG_MFD_BCM590XX=y 267CONFIG_MFD_BCM590XX=y
266CONFIG_MFD_CROS_EC=y 268CONFIG_MFD_CROS_EC=y
@@ -353,6 +355,7 @@ CONFIG_MMC_MVSDIO=y
353CONFIG_MMC_SUNXI=y 355CONFIG_MMC_SUNXI=y
354CONFIG_MMC_DW=y 356CONFIG_MMC_DW=y
355CONFIG_MMC_DW_EXYNOS=y 357CONFIG_MMC_DW_EXYNOS=y
358CONFIG_MMC_DW_ROCKCHIP=y
356CONFIG_NEW_LEDS=y 359CONFIG_NEW_LEDS=y
357CONFIG_LEDS_CLASS=y 360CONFIG_LEDS_CLASS=y
358CONFIG_LEDS_GPIO=y 361CONFIG_LEDS_GPIO=y
@@ -409,6 +412,7 @@ CONFIG_NVEC_POWER=y
409CONFIG_NVEC_PAZ00=y 412CONFIG_NVEC_PAZ00=y
410CONFIG_QCOM_GSBI=y 413CONFIG_QCOM_GSBI=y
411CONFIG_COMMON_CLK_QCOM=y 414CONFIG_COMMON_CLK_QCOM=y
415CONFIG_APQ_MMCC_8084=y
412CONFIG_MSM_GCC_8660=y 416CONFIG_MSM_GCC_8660=y
413CONFIG_MSM_MMCC_8960=y 417CONFIG_MSM_MMCC_8960=y
414CONFIG_MSM_MMCC_8974=y 418CONFIG_MSM_MMCC_8974=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 16e719c268dd..b3f86670d2eb 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -86,7 +86,6 @@ CONFIG_IP_PNP_DHCP=y
86CONFIG_IP_PNP_BOOTP=y 86CONFIG_IP_PNP_BOOTP=y
87CONFIG_IP_PNP_RARP=y 87CONFIG_IP_PNP_RARP=y
88# CONFIG_INET_LRO is not set 88# CONFIG_INET_LRO is not set
89CONFIG_IPV6=y
90CONFIG_NETFILTER=y 89CONFIG_NETFILTER=y
91CONFIG_CAN=m 90CONFIG_CAN=m
92CONFIG_CAN_C_CAN=m 91CONFIG_CAN_C_CAN=m
@@ -112,6 +111,7 @@ CONFIG_MTD_OOPS=y
112CONFIG_MTD_CFI=y 111CONFIG_MTD_CFI=y
113CONFIG_MTD_CFI_INTELEXT=y 112CONFIG_MTD_CFI_INTELEXT=y
114CONFIG_MTD_NAND=y 113CONFIG_MTD_NAND=y
114CONFIG_MTD_NAND_ECC_BCH=y
115CONFIG_MTD_NAND_OMAP2=y 115CONFIG_MTD_NAND_OMAP2=y
116CONFIG_MTD_ONENAND=y 116CONFIG_MTD_ONENAND=y
117CONFIG_MTD_ONENAND_VERIFY_WRITE=y 117CONFIG_MTD_ONENAND_VERIFY_WRITE=y
@@ -317,7 +317,7 @@ CONFIG_EXT4_FS=y
317CONFIG_FANOTIFY=y 317CONFIG_FANOTIFY=y
318CONFIG_QUOTA=y 318CONFIG_QUOTA=y
319CONFIG_QFMT_V2=y 319CONFIG_QFMT_V2=y
320CONFIG_AUTOFS4_FS=y 320CONFIG_AUTOFS4_FS=m
321CONFIG_MSDOS_FS=y 321CONFIG_MSDOS_FS=y
322CONFIG_VFAT_FS=y 322CONFIG_VFAT_FS=y
323CONFIG_TMPFS=y 323CONFIG_TMPFS=y
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index d7a5855a5db8..a2956c3112f1 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -1,5 +1,6 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y 1CONFIG_SYSVIPC=y
2CONFIG_FHANDLE=y
3CONFIG_HIGH_RES_TIMERS=y
3CONFIG_IKCONFIG=y 4CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y 5CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=14 6CONFIG_LOG_BUF_SHIFT=14
@@ -11,23 +12,17 @@ CONFIG_PROFILING=y
11CONFIG_OPROFILE=y 12CONFIG_OPROFILE=y
12CONFIG_MODULES=y 13CONFIG_MODULES=y
13CONFIG_MODULE_UNLOAD=y 14CONFIG_MODULE_UNLOAD=y
14CONFIG_HOTPLUG=y
15# CONFIG_LBDAF is not set 15# CONFIG_LBDAF is not set
16# CONFIG_BLK_DEV_BSG is not set 16# CONFIG_BLK_DEV_BSG is not set
17# CONFIG_IOSCHED_DEADLINE is not set 17# CONFIG_IOSCHED_DEADLINE is not set
18# CONFIG_IOSCHED_CFQ is not set 18# CONFIG_IOSCHED_CFQ is not set
19CONFIG_ARCH_SOCFPGA=y 19CONFIG_ARCH_SOCFPGA=y
20CONFIG_MACH_SOCFPGA_CYCLONE5=y
21CONFIG_ARM_THUMBEE=y 20CONFIG_ARM_THUMBEE=y
22# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
23# CONFIG_CACHE_L2X0 is not set
24CONFIG_HIGH_RES_TIMERS=y
25CONFIG_SMP=y 21CONFIG_SMP=y
26CONFIG_NR_CPUS=2 22CONFIG_NR_CPUS=2
27CONFIG_AEABI=y 23CONFIG_AEABI=y
28CONFIG_ZBOOT_ROM_TEXT=0x0 24CONFIG_ZBOOT_ROM_TEXT=0x0
29CONFIG_ZBOOT_ROM_BSS=0x0 25CONFIG_ZBOOT_ROM_BSS=0x0
30CONFIG_CMDLINE=""
31CONFIG_VFP=y 26CONFIG_VFP=y
32CONFIG_NEON=y 27CONFIG_NEON=y
33CONFIG_NET=y 28CONFIG_NET=y
@@ -41,38 +36,30 @@ CONFIG_IP_PNP=y
41CONFIG_IP_PNP_DHCP=y 36CONFIG_IP_PNP_DHCP=y
42CONFIG_IP_PNP_BOOTP=y 37CONFIG_IP_PNP_BOOTP=y
43CONFIG_IP_PNP_RARP=y 38CONFIG_IP_PNP_RARP=y
39CONFIG_IPV6=y
40CONFIG_NETWORK_PHY_TIMESTAMPING=y
41CONFIG_VLAN_8021Q=y
42CONFIG_VLAN_8021Q_GVRP=y
44CONFIG_CAN=y 43CONFIG_CAN=y
45CONFIG_CAN_RAW=y
46CONFIG_CAN_BCM=y
47CONFIG_CAN_GW=y
48CONFIG_CAN_DEV=y
49CONFIG_CAN_CALC_BITTIMING=y
50CONFIG_CAN_C_CAN=y 44CONFIG_CAN_C_CAN=y
51CONFIG_CAN_C_CAN_PLATFORM=y 45CONFIG_CAN_C_CAN_PLATFORM=y
52CONFIG_CAN_DEBUG_DEVICES=y 46CONFIG_CAN_DEBUG_DEVICES=y
53CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 47CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
54CONFIG_DEVTMPFS=y 48CONFIG_DEVTMPFS=y
55CONFIG_PROC_DEVICETREE=y 49CONFIG_DEVTMPFS_MOUNT=y
56CONFIG_BLK_DEV_RAM=y 50CONFIG_BLK_DEV_RAM=y
57CONFIG_BLK_DEV_RAM_COUNT=2 51CONFIG_BLK_DEV_RAM_COUNT=2
58CONFIG_BLK_DEV_RAM_SIZE=8192 52CONFIG_BLK_DEV_RAM_SIZE=8192
53CONFIG_SRAM=y
59CONFIG_SCSI=y 54CONFIG_SCSI=y
60# CONFIG_SCSI_PROC_FS is not set 55# CONFIG_SCSI_PROC_FS is not set
61CONFIG_BLK_DEV_SD=y 56CONFIG_BLK_DEV_SD=y
62# CONFIG_SCSI_LOWLEVEL is not set 57# CONFIG_SCSI_LOWLEVEL is not set
63CONFIG_NETDEVICES=y 58CONFIG_NETDEVICES=y
64CONFIG_STMMAC_ETH=y 59CONFIG_STMMAC_ETH=y
60CONFIG_DWMAC_SOCFPGA=y
65CONFIG_MICREL_PHY=y 61CONFIG_MICREL_PHY=y
66# CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set
67CONFIG_INPUT_EVDEV=y 62CONFIG_INPUT_EVDEV=y
68CONFIG_DWMAC_SOCFPGA=y
69CONFIG_PPS=y
70CONFIG_NETWORK_PHY_TIMESTAMPING=y
71CONFIG_PTP_1588_CLOCK=y
72CONFIG_VLAN_8021Q=y
73CONFIG_VLAN_8021Q_GVRP=y
74CONFIG_GARP=y
75CONFIG_IPV6=y
76# CONFIG_SERIO_SERPORT is not set 63# CONFIG_SERIO_SERPORT is not set
77CONFIG_SERIO_AMBAKMI=y 64CONFIG_SERIO_AMBAKMI=y
78CONFIG_LEGACY_PTY_COUNT=16 65CONFIG_LEGACY_PTY_COUNT=16
@@ -81,45 +68,43 @@ CONFIG_SERIAL_8250_CONSOLE=y
81CONFIG_SERIAL_8250_NR_UARTS=2 68CONFIG_SERIAL_8250_NR_UARTS=2
82CONFIG_SERIAL_8250_RUNTIME_UARTS=2 69CONFIG_SERIAL_8250_RUNTIME_UARTS=2
83CONFIG_SERIAL_8250_DW=y 70CONFIG_SERIAL_8250_DW=y
71CONFIG_I2C=y
72CONFIG_I2C_CHARDEV=y
73CONFIG_I2C_DESIGNWARE_PLATFORM=y
84CONFIG_GPIOLIB=y 74CONFIG_GPIOLIB=y
85CONFIG_GPIO_SYSFS=y 75CONFIG_GPIO_SYSFS=y
86CONFIG_GPIO_DWAPB=y 76CONFIG_GPIO_DWAPB=y
87# CONFIG_RTC_HCTOSYS is not set 77CONFIG_PMBUS=y
78CONFIG_SENSORS_LTC2978=y
79CONFIG_SENSORS_LTC2978_REGULATOR=y
88CONFIG_WATCHDOG=y 80CONFIG_WATCHDOG=y
89CONFIG_DW_WATCHDOG=y 81CONFIG_DW_WATCHDOG=y
82CONFIG_REGULATOR=y
83CONFIG_REGULATOR_FIXED_VOLTAGE=y
84CONFIG_USB=y
85CONFIG_USB_DWC2=y
86CONFIG_USB_DWC2_HOST=y
87CONFIG_MMC=y
88CONFIG_MMC_DW=y
90CONFIG_EXT2_FS=y 89CONFIG_EXT2_FS=y
91CONFIG_EXT2_FS_XATTR=y 90CONFIG_EXT2_FS_XATTR=y
92CONFIG_EXT2_FS_POSIX_ACL=y 91CONFIG_EXT2_FS_POSIX_ACL=y
93CONFIG_EXT3_FS=y 92CONFIG_EXT3_FS=y
94CONFIG_NFS_FS=y 93CONFIG_EXT4_FS=y
95CONFIG_ROOT_NFS=y
96# CONFIG_DNOTIFY is not set
97# CONFIG_INOTIFY_USER is not set
98CONFIG_FHANDLE=y
99CONFIG_VFAT_FS=y 94CONFIG_VFAT_FS=y
100CONFIG_NTFS_FS=y 95CONFIG_NTFS_FS=y
101CONFIG_NTFS_RW=y 96CONFIG_NTFS_RW=y
102CONFIG_TMPFS=y 97CONFIG_TMPFS=y
103CONFIG_JFFS2_FS=y 98CONFIG_CONFIGFS_FS=y
99CONFIG_NFS_FS=y
100CONFIG_ROOT_NFS=y
104CONFIG_NLS_CODEPAGE_437=y 101CONFIG_NLS_CODEPAGE_437=y
105CONFIG_NLS_ISO8859_1=y 102CONFIG_NLS_ISO8859_1=y
103CONFIG_PRINTK_TIME=y
104CONFIG_DEBUG_INFO=y
106CONFIG_MAGIC_SYSRQ=y 105CONFIG_MAGIC_SYSRQ=y
107CONFIG_DETECT_HUNG_TASK=y 106CONFIG_DETECT_HUNG_TASK=y
108# CONFIG_SCHED_DEBUG is not set 107# CONFIG_SCHED_DEBUG is not set
109CONFIG_DEBUG_INFO=y
110CONFIG_ENABLE_DEFAULT_TRACERS=y 108CONFIG_ENABLE_DEFAULT_TRACERS=y
111CONFIG_DEBUG_USER=y 109CONFIG_DEBUG_USER=y
112CONFIG_XZ_DEC=y 110CONFIG_XZ_DEC=y
113CONFIG_I2C=y
114CONFIG_I2C_DESIGNWARE_CORE=y
115CONFIG_I2C_DESIGNWARE_PLATFORM=y
116CONFIG_I2C_CHARDEV=y
117CONFIG_MMC=y
118CONFIG_MMC_DW=y
119CONFIG_PM=y
120CONFIG_SUSPEND=y
121CONFIG_MMC_UNSAFE_RESUME=y
122CONFIG_USB=y
123CONFIG_USB_DWC2=y
124CONFIG_USB_DWC2_HOST=y
125CONFIG_USB_DWC2_PLATFORM=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 847045313101..f7ac0379850f 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -76,6 +76,7 @@ CONFIG_WATCHDOG=y
76CONFIG_SUNXI_WATCHDOG=y 76CONFIG_SUNXI_WATCHDOG=y
77CONFIG_MFD_AXP20X=y 77CONFIG_MFD_AXP20X=y
78CONFIG_REGULATOR=y 78CONFIG_REGULATOR=y
79CONFIG_REGULATOR_FIXED_VOLTAGE=y
79CONFIG_REGULATOR_GPIO=y 80CONFIG_REGULATOR_GPIO=y
80CONFIG_USB=y 81CONFIG_USB=y
81CONFIG_USB_EHCI_HCD=y 82CONFIG_USB_EHCI_HCD=y
diff --git a/arch/arm/include/uapi/asm/unistd.h b/arch/arm/include/uapi/asm/unistd.h
index 3aaa75cae90c..705bb7620673 100644
--- a/arch/arm/include/uapi/asm/unistd.h
+++ b/arch/arm/include/uapi/asm/unistd.h
@@ -412,6 +412,7 @@
412#define __NR_seccomp (__NR_SYSCALL_BASE+383) 412#define __NR_seccomp (__NR_SYSCALL_BASE+383)
413#define __NR_getrandom (__NR_SYSCALL_BASE+384) 413#define __NR_getrandom (__NR_SYSCALL_BASE+384)
414#define __NR_memfd_create (__NR_SYSCALL_BASE+385) 414#define __NR_memfd_create (__NR_SYSCALL_BASE+385)
415#define __NR_bpf (__NR_SYSCALL_BASE+386)
415 416
416/* 417/*
417 * The following SWIs are ARM private. 418 * The following SWIs are ARM private.
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 713e807621d2..2d2d6087b9b1 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -10,6 +10,7 @@
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13#include <linux/compiler.h>
13#include <linux/sched.h> 14#include <linux/sched.h>
14#include <linux/mm.h> 15#include <linux/mm.h>
15#include <linux/dma-mapping.h> 16#include <linux/dma-mapping.h>
@@ -39,10 +40,19 @@
39 * GCC 3.2.x: miscompiles NEW_AUX_ENT in fs/binfmt_elf.c 40 * GCC 3.2.x: miscompiles NEW_AUX_ENT in fs/binfmt_elf.c
40 * (http://gcc.gnu.org/PR8896) and incorrect structure 41 * (http://gcc.gnu.org/PR8896) and incorrect structure
41 * initialisation in fs/jffs2/erase.c 42 * initialisation in fs/jffs2/erase.c
43 * GCC 4.8.0-4.8.2: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58854
44 * miscompiles find_get_entry(), and can result in EXT3 and EXT4
45 * filesystem corruption (possibly other FS too).
42 */ 46 */
47#ifdef __GNUC__
43#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3) 48#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
44#error Your compiler is too buggy; it is known to miscompile kernels. 49#error Your compiler is too buggy; it is known to miscompile kernels.
45#error Known good compilers: 3.3 50#error Known good compilers: 3.3, 4.x
51#endif
52#if GCC_VERSION >= 40800 && GCC_VERSION < 40803
53#error Your compiler is too buggy; it is known to miscompile kernels
54#error and result in filesystem corruption and oopses.
55#endif
46#endif 56#endif
47 57
48int main(void) 58int main(void)
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 9f899d8fdcca..e51833f8cc38 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -395,6 +395,7 @@
395 CALL(sys_seccomp) 395 CALL(sys_seccomp)
396 CALL(sys_getrandom) 396 CALL(sys_getrandom)
397/* 385 */ CALL(sys_memfd_create) 397/* 385 */ CALL(sys_memfd_create)
398 CALL(sys_bpf)
398#ifndef syscalls_counted 399#ifndef syscalls_counted
399.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls 400.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
400#define syscalls_counted 401#define syscalls_counted
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 8c35ae4ff176..07a09570175d 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -20,7 +20,7 @@
20#include <linux/input.h> 20#include <linux/input.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/irqchip.h> 22#include <linux/irqchip.h>
23#include <linux/mailbox.h> 23#include <linux/pl320-ipc.h>
24#include <linux/of.h> 24#include <linux/of.h>
25#include <linux/of_irq.h> 25#include <linux/of_irq.h>
26#include <linux/of_platform.h> 26#include <linux/of_platform.h>
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 1412daf4a714..4e79da7c5e30 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -50,8 +50,8 @@ static const char *pcie_axi_sels[] = { "axi", "ahb", };
50static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; 50static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
51static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; 51static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
52static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; 52static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
53static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; 53static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
54static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 54static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
55static const char *vdo_axi_sels[] = { "axi", "ahb", }; 55static const char *vdo_axi_sels[] = { "axi", "ahb", };
56static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 56static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
57static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", 57static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
@@ -302,8 +302,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
302 clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 302 clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
303 clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 303 clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
304 clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); 304 clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
305 clk[IMX6QDL_CLK_EMI_SEL] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup); 305 clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup);
306 clk[IMX6QDL_CLK_EMI_SLOW_SEL] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup); 306 clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup);
307 clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); 307 clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
308 clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); 308 clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
309 clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); 309 clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
@@ -354,8 +354,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
354 clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); 354 clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
355 clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); 355 clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
356 clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); 356 clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
357 clk[IMX6QDL_CLK_EMI_PODF] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); 357 clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
358 clk[IMX6QDL_CLK_EMI_SLOW_PODF] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); 358 clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
359 clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); 359 clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
360 clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); 360 clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
361 clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); 361 clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
@@ -456,7 +456,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
456 clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); 456 clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
457 clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); 457 clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
458 clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); 458 clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
459 clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10); 459 clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
460 clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); 460 clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
461 clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); 461 clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
462 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); 462 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index a17818475050..409637254594 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -58,8 +58,14 @@
58#define PFD_PLL1_BASE (anatop_base + 0x2b0) 58#define PFD_PLL1_BASE (anatop_base + 0x2b0)
59#define PFD_PLL2_BASE (anatop_base + 0x100) 59#define PFD_PLL2_BASE (anatop_base + 0x100)
60#define PFD_PLL3_BASE (anatop_base + 0xf0) 60#define PFD_PLL3_BASE (anatop_base + 0xf0)
61#define PLL1_CTRL (anatop_base + 0x270)
62#define PLL2_CTRL (anatop_base + 0x30)
61#define PLL3_CTRL (anatop_base + 0x10) 63#define PLL3_CTRL (anatop_base + 0x10)
64#define PLL4_CTRL (anatop_base + 0x70)
65#define PLL5_CTRL (anatop_base + 0xe0)
66#define PLL6_CTRL (anatop_base + 0xa0)
62#define PLL7_CTRL (anatop_base + 0x20) 67#define PLL7_CTRL (anatop_base + 0x20)
68#define ANA_MISC1 (anatop_base + 0x160)
63 69
64static void __iomem *anatop_base; 70static void __iomem *anatop_base;
65static void __iomem *ccm_base; 71static void __iomem *ccm_base;
@@ -67,25 +73,34 @@ static void __iomem *ccm_base;
67/* sources for multiplexer clocks, this is used multiple times */ 73/* sources for multiplexer clocks, this is used multiple times */
68static const char *fast_sels[] = { "firc", "fxosc", }; 74static const char *fast_sels[] = { "firc", "fxosc", };
69static const char *slow_sels[] = { "sirc_32k", "sxosc", }; 75static const char *slow_sels[] = { "sirc_32k", "sxosc", };
70static const char *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", }; 76static const char *pll1_sels[] = { "pll1_sys", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
71static const char *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", }; 77static const char *pll2_sels[] = { "pll2_bus", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
72static const char *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", }; 78static const char *pll_bypass_src_sels[] = { "fast_clk_sel", "lvds1_in", };
79static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
80static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
81static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
82static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
83static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
84static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
85static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
86static const char *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_bus", "pll1_pfd_sel", "pll3_usb_otg", };
73static const char *ddr_sels[] = { "pll2_pfd2", "sys_sel", }; 87static const char *ddr_sels[] = { "pll2_pfd2", "sys_sel", };
74static const char *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", }; 88static const char *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
75static const char *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", }; 89static const char *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
76static const char *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; 90static const char *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_audio_div", };
77static const char *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; 91static const char *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_audio_div", };
78static const char *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", }; 92static const char *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
79static const char *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", }; 93static const char *qspi_sels[] = { "pll3_usb_otg", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
80static const char *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", }; 94static const char *esdhc_sels[] = { "pll3_usb_otg", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
81static const char *dcu_sels[] = { "pll1_pfd2", "pll3_main", }; 95static const char *dcu_sels[] = { "pll1_pfd2", "pll3_usb_otg", };
82static const char *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", }; 96static const char *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", };
83static const char *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", }; 97static const char *vadc_sels[] = { "pll6_video_div", "pll3_usb_otg_div", "pll3_usb_otg", };
84/* FTM counter clock source, not module clock */ 98/* FTM counter clock source, not module clock */
85static const char *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", }; 99static const char *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
86static const char *ftm_fix_sels[] = { "sxosc", "ipg_bus", }; 100static const char *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
87 101
88static struct clk_div_table pll4_main_div_table[] = { 102
103static struct clk_div_table pll4_audio_div_table[] = {
89 { .val = 0, .div = 1 }, 104 { .val = 0, .div = 1 },
90 { .val = 1, .div = 2 }, 105 { .val = 1, .div = 2 },
91 { .val = 2, .div = 6 }, 106 { .val = 2, .div = 6 },
@@ -120,6 +135,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
120 clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0); 135 clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0);
121 clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0); 136 clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0);
122 137
138 /* Clock source from external clock via LVDs PAD */
139 clk[VF610_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
140
123 clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2); 141 clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
124 142
125 np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop"); 143 np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop");
@@ -133,31 +151,63 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
133 clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels)); 151 clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels));
134 clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels)); 152 clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels));
135 153
136 clk[VF610_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1); 154 clk[VF610_CLK_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", PLL1_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
137 clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0); 155 clk[VF610_CLK_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", PLL2_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
138 clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1); 156 clk[VF610_CLK_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", PLL3_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
139 clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2); 157 clk[VF610_CLK_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", PLL4_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
140 clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3); 158 clk[VF610_CLK_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", PLL5_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
141 159 clk[VF610_CLK_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", PLL6_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
142 clk[VF610_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1); 160 clk[VF610_CLK_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", PLL7_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
143 clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0); 161
144 clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1); 162 clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1);
145 clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2); 163 clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1);
146 clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3); 164 clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x1);
147 165 clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f);
148 clk[VF610_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1); 166 clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3);
149 clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0); 167 clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f);
150 clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1); 168 clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", PLL7_CTRL, 0x1);
151 clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2); 169
152 clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3); 170 clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
153 171 clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
154 clk[VF610_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1); 172 clk[VF610_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", PLL3_CTRL, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
155 /* Enet pll: fixed 50Mhz */ 173 clk[VF610_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", PLL4_CTRL, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
156 clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6); 174 clk[VF610_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", PLL5_CTRL, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
157 /* pll6: default 960Mhz */ 175 clk[VF610_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", PLL6_CTRL, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
158 clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1); 176 clk[VF610_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", PLL7_CTRL, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
159 /* pll7: USB1 PLL at 480MHz */ 177
160 clk[VF610_CLK_PLL7_MAIN] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_main", "fast_clk_sel", PLL7_CTRL, 0x2); 178 /* Do not bypass PLLs initially */
179 clk_set_parent(clk[VF610_PLL1_BYPASS], clk[VF610_CLK_PLL1]);
180 clk_set_parent(clk[VF610_PLL2_BYPASS], clk[VF610_CLK_PLL2]);
181 clk_set_parent(clk[VF610_PLL3_BYPASS], clk[VF610_CLK_PLL3]);
182 clk_set_parent(clk[VF610_PLL4_BYPASS], clk[VF610_CLK_PLL4]);
183 clk_set_parent(clk[VF610_PLL5_BYPASS], clk[VF610_CLK_PLL5]);
184 clk_set_parent(clk[VF610_PLL6_BYPASS], clk[VF610_CLK_PLL6]);
185 clk_set_parent(clk[VF610_PLL7_BYPASS], clk[VF610_CLK_PLL7]);
186
187 clk[VF610_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", PLL1_CTRL, 13);
188 clk[VF610_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", PLL2_CTRL, 13);
189 clk[VF610_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", PLL3_CTRL, 13);
190 clk[VF610_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", PLL4_CTRL, 13);
191 clk[VF610_CLK_PLL5_ENET] = imx_clk_gate("pll5_enet", "pll5_bypass", PLL5_CTRL, 13);
192 clk[VF610_CLK_PLL6_VIDEO] = imx_clk_gate("pll6_video", "pll6_bypass", PLL6_CTRL, 13);
193 clk[VF610_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", PLL7_CTRL, 13);
194
195 clk[VF610_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", ANA_MISC1, 12, BIT(10));
196
197 clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_sys", PFD_PLL1_BASE, 0);
198 clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_sys", PFD_PLL1_BASE, 1);
199 clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_sys", PFD_PLL1_BASE, 2);
200 clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_sys", PFD_PLL1_BASE, 3);
201
202 clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", PFD_PLL2_BASE, 0);
203 clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", PFD_PLL2_BASE, 1);
204 clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_bus", PFD_PLL2_BASE, 2);
205 clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_bus", PFD_PLL2_BASE, 3);
206
207 clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", PFD_PLL3_BASE, 0);
208 clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", PFD_PLL3_BASE, 1);
209 clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", PFD_PLL3_BASE, 2);
210 clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_usb_otg", PFD_PLL3_BASE, 3);
161 211
162 clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); 212 clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
163 clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); 213 clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
@@ -167,12 +217,12 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
167 clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3); 217 clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
168 clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2); 218 clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
169 219
170 clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1); 220 clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_usb_otg_div", "pll3_usb_otg", CCM_CACRR, 20, 1);
171 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock); 221 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock);
172 clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1); 222 clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_video_div", "pll6_video", CCM_CACRR, 21, 1);
173 223
174 clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_main", PLL3_CTRL, 6); 224 clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_usb_otg", PLL3_CTRL, 6);
175 clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_main", PLL7_CTRL, 6); 225 clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_usb_host", PLL7_CTRL, 6);
176 226
177 clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4)); 227 clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4));
178 clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4)); 228 clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4));
@@ -191,8 +241,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
191 clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1); 241 clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);
192 clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4)); 242 clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4));
193 243
194 clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10); 244 clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_enet", 1, 10);
195 clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20); 245 clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_enet", 1, 20);
196 clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4); 246 clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4);
197 clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7); 247 clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
198 clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24); 248 clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index 559c69a47731..7d11979da030 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -76,7 +76,7 @@ static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
76 u32 n, byte_enables, data; 76 u32 n, byte_enables, data;
77 77
78 if (!is_pci_memory(addr)) { 78 if (!is_pci_memory(addr)) {
79 __raw_writeb(value, addr); 79 __raw_writeb(value, p);
80 return; 80 return;
81 } 81 }
82 82
@@ -141,7 +141,7 @@ static inline unsigned char __indirect_readb(const volatile void __iomem *p)
141 u32 n, byte_enables, data; 141 u32 n, byte_enables, data;
142 142
143 if (!is_pci_memory(addr)) 143 if (!is_pci_memory(addr))
144 return __raw_readb(addr); 144 return __raw_readb(p);
145 145
146 n = addr % 4; 146 n = addr % 4;
147 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; 147 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index 6478626e3ff6..d0d39f150fab 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -188,7 +188,7 @@ static void __init thermal_quirk(void)
188 188
189static void __init mvebu_dt_init(void) 189static void __init mvebu_dt_init(void)
190{ 190{
191 if (of_machine_is_compatible("plathome,openblocks-ax3-4")) 191 if (of_machine_is_compatible("marvell,armadaxp"))
192 i2c_quirk(); 192 i2c_quirk();
193 if (of_machine_is_compatible("marvell,a375-db")) { 193 if (of_machine_is_compatible("marvell,a375-db")) {
194 external_abort_quirk(); 194 external_abort_quirk();
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index d22c30d3ccfa..8c58b71c2727 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -917,6 +917,10 @@ static int __init omap_device_late_idle(struct device *dev, void *data)
917static int __init omap_device_late_init(void) 917static int __init omap_device_late_init(void)
918{ 918{
919 bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle); 919 bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
920
921 WARN(!of_have_populated_dt(),
922 "legacy booting deprecated, please update to boot with .dts\n");
923
920 return 0; 924 return 0;
921} 925}
922omap_late_initcall_sync(omap_device_late_init); 926omap_late_initcall_sync(omap_device_late_init);
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index c95346c94829..cec9d6c6442c 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -252,9 +252,6 @@ static void __init nokia_n900_legacy_init(void)
252 platform_device_register(&omap3_rom_rng_device); 252 platform_device_register(&omap3_rom_rng_device);
253 253
254 } 254 }
255
256 /* Only on some development boards */
257 gpio_request_one(164, GPIOF_OUT_INIT_LOW, "smc91x reset");
258} 255}
259 256
260static void __init omap3_tao3530_legacy_init(void) 257static void __init omap3_tao3530_legacy_init(void)
diff --git a/arch/arm/mach-pxa/include/mach/addr-map.h b/arch/arm/mach-pxa/include/mach/addr-map.h
index bbf9df37ad4b..d28fe291233a 100644
--- a/arch/arm/mach-pxa/include/mach/addr-map.h
+++ b/arch/arm/mach-pxa/include/mach/addr-map.h
@@ -39,6 +39,11 @@
39#define DMEMC_SIZE 0x00100000 39#define DMEMC_SIZE 0x00100000
40 40
41/* 41/*
42 * Reserved space for low level debug virtual addresses within
43 * 0xf6200000..0xf6201000
44 */
45
46/*
42 * Internal Memory Controller (PXA27x and later) 47 * Internal Memory Controller (PXA27x and later)
43 */ 48 */
44#define IMEMC_PHYS 0x58000000 49#define IMEMC_PHYS 0x58000000
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 0794f0426e70..19df9cb30495 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -455,7 +455,7 @@ enum {
455 MSTP128, MSTP127, MSTP125, 455 MSTP128, MSTP127, MSTP125,
456 MSTP116, MSTP111, MSTP100, MSTP117, 456 MSTP116, MSTP111, MSTP100, MSTP117,
457 457
458 MSTP230, 458 MSTP230, MSTP229,
459 MSTP222, 459 MSTP222,
460 MSTP218, MSTP217, MSTP216, MSTP214, 460 MSTP218, MSTP217, MSTP216, MSTP214,
461 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, 461 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
@@ -474,11 +474,12 @@ static struct clk mstp_clks[MSTP_NR] = {
474 [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */ 474 [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */
475 [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ 475 [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
476 [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ 476 [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
477 [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */ 477 [MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_HPP], SMSTPCR1, 16, 0), /* IIC0 */
478 [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */ 478 [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
479 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ 479 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
480 480
481 [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */ 481 [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
482 [MSTP229] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 29, 0), /* INTCA */
482 [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */ 483 [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
483 [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */ 484 [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
484 [MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */ 485 [MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
@@ -575,6 +576,10 @@ static struct clk_lookup lookups[] = {
575 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), 576 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
576 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), 577 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
577 CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP222]), 578 CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP222]),
579 CLKDEV_DEV_ID("renesas_intc_irqpin.0", &mstp_clks[MSTP229]),
580 CLKDEV_DEV_ID("renesas_intc_irqpin.1", &mstp_clks[MSTP229]),
581 CLKDEV_DEV_ID("renesas_intc_irqpin.2", &mstp_clks[MSTP229]),
582 CLKDEV_DEV_ID("renesas_intc_irqpin.3", &mstp_clks[MSTP229]),
578 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), 583 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
579 CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP230]), 584 CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP230]),
580 585
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 126ddafad526..f62265200592 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -68,7 +68,7 @@
68 68
69#define SDCKCR 0xE6150074 69#define SDCKCR 0xE6150074
70#define SD2CKCR 0xE6150078 70#define SD2CKCR 0xE6150078
71#define SD3CKCR 0xE615007C 71#define SD3CKCR 0xE615026C
72#define MMC0CKCR 0xE6150240 72#define MMC0CKCR 0xE6150240
73#define MMC1CKCR 0xE6150244 73#define MMC1CKCR 0xE6150244
74#define SSPCKCR 0xE6150248 74#define SSPCKCR 0xE6150248
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index b7bd8e509668..328657d011d5 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -26,6 +26,7 @@
26#include <linux/of_platform.h> 26#include <linux/of_platform.h>
27#include <linux/delay.h> 27#include <linux/delay.h>
28#include <linux/input.h> 28#include <linux/input.h>
29#include <linux/i2c/i2c-sh_mobile.h>
29#include <linux/io.h> 30#include <linux/io.h>
30#include <linux/serial_sci.h> 31#include <linux/serial_sci.h>
31#include <linux/sh_dma.h> 32#include <linux/sh_dma.h>
@@ -192,11 +193,18 @@ static struct resource i2c4_resources[] = {
192 }, 193 },
193}; 194};
194 195
196static struct i2c_sh_mobile_platform_data i2c_platform_data = {
197 .clks_per_count = 2,
198};
199
195static struct platform_device i2c0_device = { 200static struct platform_device i2c0_device = {
196 .name = "i2c-sh_mobile", 201 .name = "i2c-sh_mobile",
197 .id = 0, 202 .id = 0,
198 .resource = i2c0_resources, 203 .resource = i2c0_resources,
199 .num_resources = ARRAY_SIZE(i2c0_resources), 204 .num_resources = ARRAY_SIZE(i2c0_resources),
205 .dev = {
206 .platform_data = &i2c_platform_data,
207 },
200}; 208};
201 209
202static struct platform_device i2c1_device = { 210static struct platform_device i2c1_device = {
@@ -204,6 +212,9 @@ static struct platform_device i2c1_device = {
204 .id = 1, 212 .id = 1,
205 .resource = i2c1_resources, 213 .resource = i2c1_resources,
206 .num_resources = ARRAY_SIZE(i2c1_resources), 214 .num_resources = ARRAY_SIZE(i2c1_resources),
215 .dev = {
216 .platform_data = &i2c_platform_data,
217 },
207}; 218};
208 219
209static struct platform_device i2c2_device = { 220static struct platform_device i2c2_device = {
@@ -211,6 +222,9 @@ static struct platform_device i2c2_device = {
211 .id = 2, 222 .id = 2,
212 .resource = i2c2_resources, 223 .resource = i2c2_resources,
213 .num_resources = ARRAY_SIZE(i2c2_resources), 224 .num_resources = ARRAY_SIZE(i2c2_resources),
225 .dev = {
226 .platform_data = &i2c_platform_data,
227 },
214}; 228};
215 229
216static struct platform_device i2c3_device = { 230static struct platform_device i2c3_device = {
@@ -218,6 +232,9 @@ static struct platform_device i2c3_device = {
218 .id = 3, 232 .id = 3,
219 .resource = i2c3_resources, 233 .resource = i2c3_resources,
220 .num_resources = ARRAY_SIZE(i2c3_resources), 234 .num_resources = ARRAY_SIZE(i2c3_resources),
235 .dev = {
236 .platform_data = &i2c_platform_data,
237 },
221}; 238};
222 239
223static struct platform_device i2c4_device = { 240static struct platform_device i2c4_device = {
@@ -225,6 +242,9 @@ static struct platform_device i2c4_device = {
225 .id = 4, 242 .id = 4,
226 .resource = i2c4_resources, 243 .resource = i2c4_resources,
227 .num_resources = ARRAY_SIZE(i2c4_resources), 244 .num_resources = ARRAY_SIZE(i2c4_resources),
245 .dev = {
246 .platform_data = &i2c_platform_data,
247 },
228}; 248};
229 249
230static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = { 250static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 572b8f719ffb..60c443dadb58 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -40,7 +40,7 @@ extern void __iomem *rst_manager_base_addr;
40extern struct smp_operations socfpga_smp_ops; 40extern struct smp_operations socfpga_smp_ops;
41extern char secondary_trampoline, secondary_trampoline_end; 41extern char secondary_trampoline, secondary_trampoline_end;
42 42
43extern unsigned long cpu1start_addr; 43extern unsigned long socfpga_cpu1start_addr;
44 44
45#define SOCFPGA_SCU_VIRT_BASE 0xfffec000 45#define SOCFPGA_SCU_VIRT_BASE 0xfffec000
46 46
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index 95c115d8b5ee..f65ea0af4af3 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -9,21 +9,26 @@
9 */ 9 */
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <asm/memory.h>
12 13
13 .arch armv7-a 14 .arch armv7-a
14 15
15ENTRY(secondary_trampoline) 16ENTRY(secondary_trampoline)
16 movw r2, #:lower16:cpu1start_addr 17 /* CPU1 will always fetch from 0x0 when it is brought out of reset.
17 movt r2, #:upper16:cpu1start_addr 18 * Thus, we can just subtract the PAGE_OFFSET to get the physical
18 19 * address of &cpu1start_addr. This would not work for platforms
19 /* The socfpga VT cannot handle a 0xC0000000 page offset when loading 20 * where the physical memory does not start at 0x0.
20 the cpu1start_addr, we bit clear it. Tested on HW and VT. */ 21 */
21 bic r2, r2, #0x40000000 22 adr r0, 1f
22 23 ldmia r0, {r1, r2}
23 ldr r0, [r2] 24 sub r2, r2, #PAGE_OFFSET
24 ldr r1, [r0] 25 ldr r3, [r2]
25 bx r1 26 ldr r4, [r3]
27 bx r4
26 28
29 .align
301: .long .
31 .long socfpga_cpu1start_addr
27ENTRY(secondary_trampoline_end) 32ENTRY(secondary_trampoline_end)
28 33
29ENTRY(socfpga_secondary_startup) 34ENTRY(socfpga_secondary_startup)
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 5356a72bc8ce..16ca97b039f9 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -33,11 +33,11 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
33{ 33{
34 int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; 34 int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
35 35
36 if (cpu1start_addr) { 36 if (socfpga_cpu1start_addr) {
37 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); 37 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
38 38
39 __raw_writel(virt_to_phys(socfpga_secondary_startup), 39 __raw_writel(virt_to_phys(socfpga_secondary_startup),
40 (sys_manager_base_addr + (cpu1start_addr & 0x000000ff))); 40 (sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)));
41 41
42 flush_cache_all(); 42 flush_cache_all();
43 smp_wmb(); 43 smp_wmb();
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index adbf38314ca8..383d61e138af 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -29,7 +29,7 @@
29void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); 29void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
30void __iomem *sys_manager_base_addr; 30void __iomem *sys_manager_base_addr;
31void __iomem *rst_manager_base_addr; 31void __iomem *rst_manager_base_addr;
32unsigned long cpu1start_addr; 32unsigned long socfpga_cpu1start_addr;
33 33
34static struct map_desc scu_io_desc __initdata = { 34static struct map_desc scu_io_desc __initdata = {
35 .virtual = SOCFPGA_SCU_VIRT_BASE, 35 .virtual = SOCFPGA_SCU_VIRT_BASE,
@@ -70,7 +70,7 @@ void __init socfpga_sysmgr_init(void)
70 np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr"); 70 np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
71 71
72 if (of_property_read_u32(np, "cpu1-start-addr", 72 if (of_property_read_u32(np, "cpu1-start-addr",
73 (u32 *) &cpu1start_addr)) 73 (u32 *) &socfpga_cpu1start_addr))
74 pr_err("SMP: Need cpu1-start-addr in device tree.\n"); 74 pr_err("SMP: Need cpu1-start-addr in device tree.\n");
75 75
76 sys_manager_base_addr = of_iomap(np, 0); 76 sys_manager_base_addr = of_iomap(np, 0);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index ae69809a9e47..7eb94e6fc376 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -798,6 +798,7 @@ config NEED_KUSER_HELPERS
798 798
799config KUSER_HELPERS 799config KUSER_HELPERS
800 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS 800 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
801 depends on MMU
801 default y 802 default y
802 help 803 help
803 Warning: disabling this option may break user programs. 804 Warning: disabling this option may break user programs.
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 55f9d6e0cc88..5e65ca8dea62 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -956,7 +956,7 @@ static u32 cache_id_part_number_from_dt;
956 * @associativity: variable to return the calculated associativity in 956 * @associativity: variable to return the calculated associativity in
957 * @max_way_size: the maximum size in bytes for the cache ways 957 * @max_way_size: the maximum size in bytes for the cache ways
958 */ 958 */
959static void __init l2x0_cache_size_of_parse(const struct device_node *np, 959static int __init l2x0_cache_size_of_parse(const struct device_node *np,
960 u32 *aux_val, u32 *aux_mask, 960 u32 *aux_val, u32 *aux_mask,
961 u32 *associativity, 961 u32 *associativity,
962 u32 max_way_size) 962 u32 max_way_size)
@@ -974,7 +974,7 @@ static void __init l2x0_cache_size_of_parse(const struct device_node *np,
974 of_property_read_u32(np, "cache-line-size", &line_size); 974 of_property_read_u32(np, "cache-line-size", &line_size);
975 975
976 if (!cache_size || !sets) 976 if (!cache_size || !sets)
977 return; 977 return -ENODEV;
978 978
979 /* All these l2 caches have the same line = block size actually */ 979 /* All these l2 caches have the same line = block size actually */
980 if (!line_size) { 980 if (!line_size) {
@@ -1009,7 +1009,7 @@ static void __init l2x0_cache_size_of_parse(const struct device_node *np,
1009 1009
1010 if (way_size > max_way_size) { 1010 if (way_size > max_way_size) {
1011 pr_err("L2C OF: set size %dKB is too large\n", way_size); 1011 pr_err("L2C OF: set size %dKB is too large\n", way_size);
1012 return; 1012 return -EINVAL;
1013 } 1013 }
1014 1014
1015 pr_info("L2C OF: override cache size: %d bytes (%dKB)\n", 1015 pr_info("L2C OF: override cache size: %d bytes (%dKB)\n",
@@ -1027,7 +1027,7 @@ static void __init l2x0_cache_size_of_parse(const struct device_node *np,
1027 if (way_size_bits < 1 || way_size_bits > 6) { 1027 if (way_size_bits < 1 || way_size_bits > 6) {
1028 pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n", 1028 pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n",
1029 way_size); 1029 way_size);
1030 return; 1030 return -EINVAL;
1031 } 1031 }
1032 1032
1033 mask |= L2C_AUX_CTRL_WAY_SIZE_MASK; 1033 mask |= L2C_AUX_CTRL_WAY_SIZE_MASK;
@@ -1036,6 +1036,8 @@ static void __init l2x0_cache_size_of_parse(const struct device_node *np,
1036 *aux_val &= ~mask; 1036 *aux_val &= ~mask;
1037 *aux_val |= val; 1037 *aux_val |= val;
1038 *aux_mask &= ~mask; 1038 *aux_mask &= ~mask;
1039
1040 return 0;
1039} 1041}
1040 1042
1041static void __init l2x0_of_parse(const struct device_node *np, 1043static void __init l2x0_of_parse(const struct device_node *np,
@@ -1046,6 +1048,7 @@ static void __init l2x0_of_parse(const struct device_node *np,
1046 u32 dirty = 0; 1048 u32 dirty = 0;
1047 u32 val = 0, mask = 0; 1049 u32 val = 0, mask = 0;
1048 u32 assoc; 1050 u32 assoc;
1051 int ret;
1049 1052
1050 of_property_read_u32(np, "arm,tag-latency", &tag); 1053 of_property_read_u32(np, "arm,tag-latency", &tag);
1051 if (tag) { 1054 if (tag) {
@@ -1068,7 +1071,10 @@ static void __init l2x0_of_parse(const struct device_node *np,
1068 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; 1071 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
1069 } 1072 }
1070 1073
1071 l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K); 1074 ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K);
1075 if (ret)
1076 return;
1077
1072 if (assoc > 8) { 1078 if (assoc > 8) {
1073 pr_err("l2x0 of: cache setting yield too high associativity\n"); 1079 pr_err("l2x0 of: cache setting yield too high associativity\n");
1074 pr_err("l2x0 of: %d calculated, max 8\n", assoc); 1080 pr_err("l2x0 of: %d calculated, max 8\n", assoc);
@@ -1125,6 +1131,7 @@ static void __init l2c310_of_parse(const struct device_node *np,
1125 u32 tag[3] = { 0, 0, 0 }; 1131 u32 tag[3] = { 0, 0, 0 };
1126 u32 filter[2] = { 0, 0 }; 1132 u32 filter[2] = { 0, 0 };
1127 u32 assoc; 1133 u32 assoc;
1134 int ret;
1128 1135
1129 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); 1136 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
1130 if (tag[0] && tag[1] && tag[2]) 1137 if (tag[0] && tag[1] && tag[2])
@@ -1152,7 +1159,10 @@ static void __init l2c310_of_parse(const struct device_node *np,
1152 l2x0_base + L310_ADDR_FILTER_START); 1159 l2x0_base + L310_ADDR_FILTER_START);
1153 } 1160 }
1154 1161
1155 l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K); 1162 ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K);
1163 if (ret)
1164 return;
1165
1156 switch (assoc) { 1166 switch (assoc) {
1157 case 16: 1167 case 16:
1158 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1168 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
@@ -1164,8 +1174,8 @@ static void __init l2c310_of_parse(const struct device_node *np,
1164 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1174 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1165 break; 1175 break;
1166 default: 1176 default:
1167 pr_err("PL310 OF: cache setting yield illegal associativity\n"); 1177 pr_err("L2C-310 OF cache associativity %d invalid, only 8 or 16 permitted\n",
1168 pr_err("PL310 OF: %d calculated, only 8 and 16 legal\n", assoc); 1178 assoc);
1169 break; 1179 break;
1170 } 1180 }
1171} 1181}
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index c245d903927f..e8907117861e 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1198,7 +1198,6 @@ __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1198{ 1198{
1199 return dma_common_pages_remap(pages, size, 1199 return dma_common_pages_remap(pages, size,
1200 VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller); 1200 VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller);
1201 return NULL;
1202} 1201}
1203 1202
1204/* 1203/*
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index 45aeaaca9052..e17ed00828d7 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -127,8 +127,11 @@ void *kmap_atomic_pfn(unsigned long pfn)
127{ 127{
128 unsigned long vaddr; 128 unsigned long vaddr;
129 int idx, type; 129 int idx, type;
130 struct page *page = pfn_to_page(pfn);
130 131
131 pagefault_disable(); 132 pagefault_disable();
133 if (!PageHighMem(page))
134 return page_address(page);
132 135
133 type = kmap_atomic_idx_push(); 136 type = kmap_atomic_idx_push();
134 idx = type + KM_TYPE_NR * smp_processor_id(); 137 idx = type + KM_TYPE_NR * smp_processor_id();
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 92bba32d9230..9481f85c56e6 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -559,10 +559,10 @@ void __init mem_init(void)
559#ifdef CONFIG_MODULES 559#ifdef CONFIG_MODULES
560 " modules : 0x%08lx - 0x%08lx (%4ld MB)\n" 560 " modules : 0x%08lx - 0x%08lx (%4ld MB)\n"
561#endif 561#endif
562 " .text : 0x%p" " - 0x%p" " (%4d kB)\n" 562 " .text : 0x%p" " - 0x%p" " (%4td kB)\n"
563 " .init : 0x%p" " - 0x%p" " (%4d kB)\n" 563 " .init : 0x%p" " - 0x%p" " (%4td kB)\n"
564 " .data : 0x%p" " - 0x%p" " (%4d kB)\n" 564 " .data : 0x%p" " - 0x%p" " (%4td kB)\n"
565 " .bss : 0x%p" " - 0x%p" " (%4d kB)\n", 565 " .bss : 0x%p" " - 0x%p" " (%4td kB)\n",
566 566
567 MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) + 567 MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
568 (PAGE_SIZE)), 568 (PAGE_SIZE)),
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index b61a3bcc2fa8..e048f6198d68 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -497,6 +497,34 @@ static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
497#define orion_gpio_dbg_show NULL 497#define orion_gpio_dbg_show NULL
498#endif 498#endif
499 499
500static void orion_gpio_unmask_irq(struct irq_data *d)
501{
502 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
503 struct irq_chip_type *ct = irq_data_get_chip_type(d);
504 u32 reg_val;
505 u32 mask = d->mask;
506
507 irq_gc_lock(gc);
508 reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);
509 reg_val |= mask;
510 irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);
511 irq_gc_unlock(gc);
512}
513
514static void orion_gpio_mask_irq(struct irq_data *d)
515{
516 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
517 struct irq_chip_type *ct = irq_data_get_chip_type(d);
518 u32 mask = d->mask;
519 u32 reg_val;
520
521 irq_gc_lock(gc);
522 reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);
523 reg_val &= ~mask;
524 irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);
525 irq_gc_unlock(gc);
526}
527
500void __init orion_gpio_init(struct device_node *np, 528void __init orion_gpio_init(struct device_node *np,
501 int gpio_base, int ngpio, 529 int gpio_base, int ngpio,
502 void __iomem *base, int mask_offset, 530 void __iomem *base, int mask_offset,
@@ -565,8 +593,8 @@ void __init orion_gpio_init(struct device_node *np,
565 ct = gc->chip_types; 593 ct = gc->chip_types;
566 ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF; 594 ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
567 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 595 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
568 ct->chip.irq_mask = irq_gc_mask_clr_bit; 596 ct->chip.irq_mask = orion_gpio_mask_irq;
569 ct->chip.irq_unmask = irq_gc_mask_set_bit; 597 ct->chip.irq_unmask = orion_gpio_unmask_irq;
570 ct->chip.irq_set_type = gpio_irq_set_type; 598 ct->chip.irq_set_type = gpio_irq_set_type;
571 ct->chip.name = ochip->chip.label; 599 ct->chip.name = ochip->chip.label;
572 600
@@ -575,8 +603,8 @@ void __init orion_gpio_init(struct device_node *np,
575 ct->regs.ack = GPIO_EDGE_CAUSE_OFF; 603 ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
576 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 604 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
577 ct->chip.irq_ack = irq_gc_ack_clr_bit; 605 ct->chip.irq_ack = irq_gc_ack_clr_bit;
578 ct->chip.irq_mask = irq_gc_mask_clr_bit; 606 ct->chip.irq_mask = orion_gpio_mask_irq;
579 ct->chip.irq_unmask = irq_gc_mask_set_bit; 607 ct->chip.irq_unmask = orion_gpio_unmask_irq;
580 ct->chip.irq_set_type = gpio_irq_set_type; 608 ct->chip.irq_set_type = gpio_irq_set_type;
581 ct->handler = handle_edge_irq; 609 ct->handler = handle_edge_irq;
582 ct->chip.name = ochip->chip.label; 610 ct->chip.name = ochip->chip.label;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 18:44:46 -0500